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drm/amd/display: dce110: fix plane validation
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
62#include "raven1/DCN/dcn_1_0_offset.h"
63#include "raven1/DCN/dcn_1_0_sh_mask.h"
64#include "vega10/soc15ip.h"
65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
73
3be5262e 74static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 75 DRM_PLANE_TYPE_PRIMARY,
76 DRM_PLANE_TYPE_PRIMARY,
77 DRM_PLANE_TYPE_PRIMARY,
78 DRM_PLANE_TYPE_PRIMARY,
79 DRM_PLANE_TYPE_PRIMARY,
80 DRM_PLANE_TYPE_PRIMARY,
81};
82
3be5262e 83static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 84 DRM_PLANE_TYPE_PRIMARY,
85 DRM_PLANE_TYPE_PRIMARY,
86 DRM_PLANE_TYPE_PRIMARY,
87 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
88};
89
3be5262e 90static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 91 DRM_PLANE_TYPE_PRIMARY,
92 DRM_PLANE_TYPE_PRIMARY,
93 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
94};
95
4562236b
HW		 96/*
97 * dm_vblank_get_counter
98 *
99 * @brief
100 * Get counter for number of vertical blanks
101 *
102 * @param
103 * struct amdgpu_device *adev - [in] desired amdgpu device
104 * int disp_idx - [in] which CRTC to get the counter from
105 *
106 * @return
107 * Counter for vertical blanks
108 */
109static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
110{
111 if (crtc >= adev->mode_info.num_crtc)
112 return 0;
113 else {
114 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 115 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
116 acrtc->base.state);
4562236b 117
da5c47f6
AG		 118
119 if (acrtc_state->stream == NULL) {
0971c40e
HW		 120 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
121 crtc);
4562236b
HW		 122 return 0;
123 }
124
da5c47f6 125 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 126 }
127}
128
129static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
130 u32 *vbl, u32 *position)
131{
81c50963
ST		 132 uint32_t v_blank_start, v_blank_end, h_position, v_position;
133
4562236b
HW		 134 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
135 return -EINVAL;
136 else {
137 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 138 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
139 acrtc->base.state);
4562236b 140
da5c47f6 141 if (acrtc_state->stream == NULL) {
0971c40e
HW		 142 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
143 crtc);
4562236b
HW		 144 return 0;
145 }
146
81c50963
ST		 147 /*
148 * TODO rework base driver to use values directly.
149 * for now parse it back into reg-format
150 */
da5c47f6 151 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 152 &v_blank_start,
153 &v_blank_end,
154 &h_position,
155 &v_position);
156
e806208d
AG		 157 *position = v_position | (h_position << 16);
158 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 159 }
160
161 return 0;
162}
163
164static bool dm_is_idle(void *handle)
165{
166 /* XXX todo */
167 return true;
168}
169
170static int dm_wait_for_idle(void *handle)
171{
172 /* XXX todo */
173 return 0;
174}
175
176static bool dm_check_soft_reset(void *handle)
177{
178 return false;
179}
180
181static int dm_soft_reset(void *handle)
182{
183 /* XXX todo */
184 return 0;
185}
186
187static struct amdgpu_crtc *get_crtc_by_otg_inst(
188 struct amdgpu_device *adev,
189 int otg_inst)
190{
191 struct drm_device *dev = adev->ddev;
192 struct drm_crtc *crtc;
193 struct amdgpu_crtc *amdgpu_crtc;
194
195 /*
196 * following if is check inherited from both functions where this one is
197 * used now. Need to be checked why it could happen.
198 */
199 if (otg_inst == -1) {
200 WARN_ON(1);
201 return adev->mode_info.crtcs[0];
202 }
203
204 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
205 amdgpu_crtc = to_amdgpu_crtc(crtc);
206
207 if (amdgpu_crtc->otg_inst == otg_inst)
208 return amdgpu_crtc;
209 }
210
211 return NULL;
212}
213
214static void dm_pflip_high_irq(void *interrupt_params)
215{
4562236b
HW		 216 struct amdgpu_crtc *amdgpu_crtc;
217 struct common_irq_params *irq_params = interrupt_params;
218 struct amdgpu_device *adev = irq_params->adev;
219 unsigned long flags;
220
221 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
222
223 /* IRQ could occur when in initial stage */
224 /*TODO work and BO cleanup */
225 if (amdgpu_crtc == NULL) {
226 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
227 return;
228 }
229
230 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 231
232 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
233 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
234 amdgpu_crtc->pflip_status,
235 AMDGPU_FLIP_SUBMITTED,
236 amdgpu_crtc->crtc_id,
237 amdgpu_crtc);
238 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
239 return;
240 }
241
4562236b
HW		 242
243 /* wakeup usersapce */
1159898a 244 if (amdgpu_crtc->event) {
753c66c9
MK		 245 /* Update to correct count/ts if racing with vblank irq */
246 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
247
54f5499a 248 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 249
54f5499a
AG		 250 /* page flip completed. clean up */
251 amdgpu_crtc->event = NULL;
1159898a 252
54f5499a
AG		 253 } else
254 WARN_ON(1);
4562236b 255
54f5499a 256 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 257 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
258
54f5499a
AG		 259 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
260 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 261
262 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 263}
264
265static void dm_crtc_high_irq(void *interrupt_params)
266{
267 struct common_irq_params *irq_params = interrupt_params;
268 struct amdgpu_device *adev = irq_params->adev;
269 uint8_t crtc_index = 0;
270 struct amdgpu_crtc *acrtc;
271
b57de80a 272 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 273
274 if (acrtc)
275 crtc_index = acrtc->crtc_id;
276
277 drm_handle_vblank(adev->ddev, crtc_index);
278}
279
280static int dm_set_clockgating_state(void *handle,
281 enum amd_clockgating_state state)
282{
283 return 0;
284}
285
286static int dm_set_powergating_state(void *handle,
287 enum amd_powergating_state state)
288{
289 return 0;
290}
291
292/* Prototypes of private functions */
293static int dm_early_init(void* handle);
294
295static void hotplug_notify_work_func(struct work_struct *work)
296{
297 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
298 struct drm_device *dev = dm->ddev;
299
300 drm_kms_helper_hotplug_event(dev);
301}
302
a32e24b4
RL		 303#ifdef ENABLE_FBC
304#include "dal_asic_id.h"
305/* Allocate memory for FBC compressed data */
306/* TODO: Dynamic allocation */
307#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
308
309void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
310{
311 int r;
312 struct dm_comressor_info *compressor = &adev->dm.compressor;
313
314 if (!compressor->bo_ptr) {
315 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
316 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
317 &compressor->gpu_addr, &compressor->cpu_addr);
318
319 if (r)
320 DRM_ERROR("DM: Failed to initialize fbc\n");
321 }
322
323}
324#endif
325
326
4562236b
HW		 327/* Init display KMS
328 *
329 * Returns 0 on success
330 */
331int amdgpu_dm_init(struct amdgpu_device *adev)
332{
333 struct dc_init_data init_data;
334 adev->dm.ddev = adev->ddev;
335 adev->dm.adev = adev;
336
337 DRM_INFO("DAL is enabled\n");
338 /* Zero all the fields */
339 memset(&init_data, 0, sizeof(init_data));
340
341 /* initialize DAL's lock (for SYNC context use) */
342 spin_lock_init(&adev->dm.dal_lock);
343
344 /* initialize DAL's mutex */
345 mutex_init(&adev->dm.dal_mutex);
346
347 if(amdgpu_dm_irq_init(adev)) {
348 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
349 goto error;
350 }
351
352 init_data.asic_id.chip_family = adev->family;
353
354 init_data.asic_id.pci_revision_id = adev->rev_id;
355 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
356
357 init_data.asic_id.vram_width = adev->mc.vram_width;
358 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
359 init_data.asic_id.atombios_base_address =
360 adev->mode_info.atom_context->bios;
361
362 init_data.driver = adev;
363
364 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
365
366 if (!adev->dm.cgs_device) {
367 DRM_ERROR("amdgpu: failed to create cgs device.\n");
368 goto error;
369 }
370
371 init_data.cgs_device = adev->dm.cgs_device;
372
373 adev->dm.dal = NULL;
374
375 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
376
a32e24b4
RL		 377#ifdef ENABLE_FBC
378 if (adev->family == FAMILY_CZ)
379 amdgpu_dm_initialize_fbc(adev);
380 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
381#endif
4562236b
HW		 382 /* Display Core create. */
383 adev->dm.dc = dc_create(&init_data);
384
385 if (!adev->dm.dc)
386 DRM_INFO("Display Core failed to initialize!\n");
387
388 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
389
390 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
391 if (!adev->dm.freesync_module) {
392 DRM_ERROR(
393 "amdgpu: failed to initialize freesync_module.\n");
394 } else
395 DRM_INFO("amdgpu: freesync_module init done %p.\n",
396 adev->dm.freesync_module);
397
398 if (amdgpu_dm_initialize_drm_device(adev)) {
399 DRM_ERROR(
400 "amdgpu: failed to initialize sw for display support.\n");
401 goto error;
402 }
403
404 /* Update the actual used number of crtc */
405 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
406
407 /* TODO: Add_display_info? */
408
409 /* TODO use dynamic cursor width */
ce75805e
AG		 410 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
411 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 412
413 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
414 DRM_ERROR(
415 "amdgpu: failed to initialize sw for display support.\n");
416 goto error;
417 }
418
419 DRM_INFO("KMS initialized.\n");
420
421 return 0;
422error:
423 amdgpu_dm_fini(adev);
424
425 return -1;
426}
427
428void amdgpu_dm_fini(struct amdgpu_device *adev)
429{
430 amdgpu_dm_destroy_drm_device(&adev->dm);
431 /*
432 * TODO: pageflip, vlank interrupt
433 *
434 * amdgpu_dm_irq_fini(adev);
435 */
436
437 if (adev->dm.cgs_device) {
438 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
439 adev->dm.cgs_device = NULL;
440 }
441 if (adev->dm.freesync_module) {
442 mod_freesync_destroy(adev->dm.freesync_module);
443 adev->dm.freesync_module = NULL;
444 }
445 /* DC Destroy TODO: Replace destroy DAL */
21de3396 446 if (adev->dm.dc)
4562236b 447 dc_destroy(&adev->dm.dc);
4562236b
HW		 448 return;
449}
450
451/* moved from amdgpu_dm_kms.c */
452void amdgpu_dm_destroy()
453{
454}
455
456static int dm_sw_init(void *handle)
457{
458 return 0;
459}
460
461static int dm_sw_fini(void *handle)
462{
463 return 0;
464}
465
7abcf6b5 466static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b
HW		 467{
468 struct amdgpu_connector *aconnector;
469 struct drm_connector *connector;
7abcf6b5 470 int ret = 0;
4562236b
HW		 471
472 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
473
474 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
475 aconnector = to_amdgpu_connector(connector);
7abcf6b5
AG		 476 if (aconnector->dc_link->type == dc_connection_mst_branch) {
477 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
478 aconnector, aconnector->base.base.id);
479
480 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
481 if (ret < 0) {
482 DRM_ERROR("DM_MST: Failed to start MST\n");
483 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
484 return ret;
4562236b 485 }
7abcf6b5 486 }
4562236b
HW		 487 }
488
489 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 490 return ret;
491}
492
493static int dm_late_init(void *handle)
494{
495 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
496 int r = detect_mst_link_for_all_connectors(dev);
497
498 return r;
4562236b
HW		 499}
500
501static void s3_handle_mst(struct drm_device *dev, bool suspend)
502{
503 struct amdgpu_connector *aconnector;
504 struct drm_connector *connector;
505
506 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
507
508 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
509 aconnector = to_amdgpu_connector(connector);
510 if (aconnector->dc_link->type == dc_connection_mst_branch &&
511 !aconnector->mst_port) {
512
513 if (suspend)
514 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
515 else
516 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
517 }
518 }
519
520 drm_modeset_unlock(&dev->mode_config.connection_mutex);
521}
522
523static int dm_hw_init(void *handle)
524{
525 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
526 /* Create DAL display manager */
527 amdgpu_dm_init(adev);
4562236b
HW		 528 amdgpu_dm_hpd_init(adev);
529
4562236b
HW		 530 return 0;
531}
532
533static int dm_hw_fini(void *handle)
534{
535 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
536
537 amdgpu_dm_hpd_fini(adev);
538
539 amdgpu_dm_irq_fini(adev);
21de3396 540 amdgpu_dm_fini(adev);
4562236b
HW		 541 return 0;
542}
543
544static int dm_suspend(void *handle)
545{
546 struct amdgpu_device *adev = handle;
547 struct amdgpu_display_manager *dm = &adev->dm;
548 int ret = 0;
4562236b
HW		 549
550 s3_handle_mst(adev->ddev, true);
551
4562236b
HW		 552 amdgpu_dm_irq_suspend(adev);
553
0a214e2f 554 WARN_ON(adev->dm.cached_state);
a3621485
AG		 555 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
556
4562236b
HW		 557 dc_set_power_state(
558 dm->dc,
a3621485
AG		 559 DC_ACPI_CM_POWER_STATE_D3
560 );
4562236b
HW		 561
562 return ret;
563}
564
565struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
566 struct drm_atomic_state *state,
567 struct drm_crtc *crtc,
568 bool from_state_var)
569{
570 uint32_t i;
571 struct drm_connector_state *conn_state;
572 struct drm_connector *connector;
573 struct drm_crtc *crtc_from_state;
574
575 for_each_connector_in_state(
576 state,
577 connector,
578 conn_state,
579 i) {
580 crtc_from_state =
581 from_state_var ?
582 conn_state->crtc :
583 connector->state->crtc;
584
585 if (crtc_from_state == crtc)
586 return to_amdgpu_connector(connector);
587 }
588
589 return NULL;
590}
591
4562236b
HW		 592static int dm_resume(void *handle)
593{
594 struct amdgpu_device *adev = handle;
595 struct amdgpu_display_manager *dm = &adev->dm;
596
597 /* power on hardware */
598 dc_set_power_state(
599 dm->dc,
a3621485
AG		 600 DC_ACPI_CM_POWER_STATE_D0
601 );
4562236b
HW		 602
603 return 0;
604}
605
606int amdgpu_dm_display_resume(struct amdgpu_device *adev )
607{
608 struct drm_device *ddev = adev->ddev;
609 struct amdgpu_display_manager *dm = &adev->dm;
610 struct amdgpu_connector *aconnector;
611 struct drm_connector *connector;
4562236b 612 struct drm_crtc *crtc;
a3621485
AG		 613 struct drm_crtc_state *crtc_state;
614 int ret = 0;
615 int i;
4562236b
HW		 616
617 /* program HPD filter */
618 dc_resume(dm->dc);
619
620 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
621 s3_handle_mst(ddev, false);
622
623 /*
624 * early enable HPD Rx IRQ, should be done before set mode as short
625 * pulse interrupts are used for MST
626 */
627 amdgpu_dm_irq_resume_early(adev);
628
4562236b
HW		 629 /* Do detection*/
630 list_for_each_entry(connector,
631 &ddev->mode_config.connector_list, head) {
632 aconnector = to_amdgpu_connector(connector);
633
634 /*
635 * this is the case when traversing through already created
636 * MST connectors, should be skipped
637 */
638 if (aconnector->mst_port)
639 continue;
640
03ea364c 641 mutex_lock(&aconnector->hpd_lock);
4562236b
HW		 642 dc_link_detect(aconnector->dc_link, false);
643 aconnector->dc_sink = NULL;
644 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 645 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 646 }
647
a3621485
AG		 648 /* Force mode set in atomic comit */
649 for_each_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i)
650 crtc_state->active_changed = true;
651
652 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 653
0a214e2f
AG		 654 drm_atomic_state_put(adev->dm.cached_state);
655 adev->dm.cached_state = NULL;
656
9faa4237 657 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 658
659 return ret;
660}
661
662static const struct amd_ip_funcs amdgpu_dm_funcs = {
663 .name = "dm",
664 .early_init = dm_early_init,
7abcf6b5 665 .late_init = dm_late_init,
4562236b
HW		 666 .sw_init = dm_sw_init,
667 .sw_fini = dm_sw_fini,
668 .hw_init = dm_hw_init,
669 .hw_fini = dm_hw_fini,
670 .suspend = dm_suspend,
671 .resume = dm_resume,
672 .is_idle = dm_is_idle,
673 .wait_for_idle = dm_wait_for_idle,
674 .check_soft_reset = dm_check_soft_reset,
675 .soft_reset = dm_soft_reset,
676 .set_clockgating_state = dm_set_clockgating_state,
677 .set_powergating_state = dm_set_powergating_state,
678};
679
680const struct amdgpu_ip_block_version dm_ip_block =
681{
682 .type = AMD_IP_BLOCK_TYPE_DCE,
683 .major = 1,
684 .minor = 0,
685 .rev = 0,
686 .funcs = &amdgpu_dm_funcs,
687};
688
ca3268c4
HW		 689
690struct drm_atomic_state *
691dm_atomic_state_alloc(struct drm_device *dev)
692{
693 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
694
1dc90497 695 if (!state)
ca3268c4 696 return NULL;
1dc90497
AG		 697
698 if (drm_atomic_state_init(dev, &state->base) < 0)
699 goto fail;
700
ca3268c4 701 return &state->base;
1dc90497
AG		 702
703fail:
704 kfree(state);
705 return NULL;
ca3268c4
HW		 706}
707
0a323b84
AG		 708static void
709dm_atomic_state_clear(struct drm_atomic_state *state)
710{
711 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
712
713 if (dm_state->context) {
608ac7bb 714 dc_release_state(dm_state->context);
0a323b84
AG		 715 dm_state->context = NULL;
716 }
717
718 drm_atomic_state_default_clear(state);
719}
720
721static void
722dm_atomic_state_alloc_free(struct drm_atomic_state *state)
723{
724 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
725 drm_atomic_state_default_release(state);
726 kfree(dm_state);
727}
728
b3663f70 729static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 730 .fb_create = amdgpu_user_framebuffer_create,
731 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 732 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 733 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 734 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 735 .atomic_state_clear = dm_atomic_state_clear,
736 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 737};
738
739static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
740 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 741};
742
743void amdgpu_dm_update_connector_after_detect(
744 struct amdgpu_connector *aconnector)
745{
746 struct drm_connector *connector = &aconnector->base;
747 struct drm_device *dev = connector->dev;
b73a22d3 748 struct dc_sink *sink;
4562236b
HW		 749
750 /* MST handled by drm_mst framework */
751 if (aconnector->mst_mgr.mst_state == true)
752 return;
753
754
755 sink = aconnector->dc_link->local_sink;
756
757 /* Edid mgmt connector gets first update only in mode_valid hook and then
758 * the connector sink is set to either fake or physical sink depends on link status.
759 * don't do it here if u are during boot
760 */
761 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
762 && aconnector->dc_em_sink) {
763
ab2541b6 764 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 765 * because on resume connecotr->sink is set ti NULL
766 */
767 mutex_lock(&dev->mode_config.mutex);
768
769 if (sink) {
922aa1e1 770 if (aconnector->dc_sink) {
4562236b
HW		 771 amdgpu_dm_remove_sink_from_freesync_module(
772 connector);
922aa1e1
AG		 773 /* retain and release bellow are used for
774 * bump up refcount for sink because the link don't point
775 * to it anymore after disconnect so on next crtc to connector
776 * reshuffle by UMD we will get into unwanted dc_sink release
777 */
778 if (aconnector->dc_sink != aconnector->dc_em_sink)
779 dc_sink_release(aconnector->dc_sink);
780 }
4562236b
HW		 781 aconnector->dc_sink = sink;
782 amdgpu_dm_add_sink_to_freesync_module(
783 connector, aconnector->edid);
784 } else {
785 amdgpu_dm_remove_sink_from_freesync_module(connector);
786 if (!aconnector->dc_sink)
787 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 788 else if (aconnector->dc_sink != aconnector->dc_em_sink)
789 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 790 }
791
792 mutex_unlock(&dev->mode_config.mutex);
793 return;
794 }
795
796 /*
797 * TODO: temporary guard to look for proper fix
798 * if this sink is MST sink, we should not do anything
799 */
800 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
801 return;
802
803 if (aconnector->dc_sink == sink) {
804 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
805 * Do nothing!! */
806 DRM_INFO("DCHPD: connector_id=%d: dc_sink didn't change.\n",
807 aconnector->connector_id);
808 return;
809 }
810
811 DRM_INFO("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
812 aconnector->connector_id, aconnector->dc_sink, sink);
813
814 mutex_lock(&dev->mode_config.mutex);
815
816 /* 1. Update status of the drm connector
817 * 2. Send an event and let userspace tell us what to do */
818 if (sink) {
819 /* TODO: check if we still need the S3 mode update workaround.
820 * If yes, put it here. */
821 if (aconnector->dc_sink)
822 amdgpu_dm_remove_sink_from_freesync_module(
823 connector);
824
825 aconnector->dc_sink = sink;
826 if (sink->dc_edid.length == 0)
827 aconnector->edid = NULL;
828 else {
829 aconnector->edid =
830 (struct edid *) sink->dc_edid.raw_edid;
831
832
833 drm_mode_connector_update_edid_property(connector,
834 aconnector->edid);
835 }
836 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
837
838 } else {
839 amdgpu_dm_remove_sink_from_freesync_module(connector);
840 drm_mode_connector_update_edid_property(connector, NULL);
841 aconnector->num_modes = 0;
842 aconnector->dc_sink = NULL;
843 }
844
845 mutex_unlock(&dev->mode_config.mutex);
846}
847
848static void handle_hpd_irq(void *param)
849{
850 struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
851 struct drm_connector *connector = &aconnector->base;
852 struct drm_device *dev = connector->dev;
853
854 /* In case of failure or MST no need to update connector status or notify the OS
855 * since (for MST case) MST does this in it's own context.
856 */
857 mutex_lock(&aconnector->hpd_lock);
858 if (dc_link_detect(aconnector->dc_link, false)) {
859 amdgpu_dm_update_connector_after_detect(aconnector);
860
861
862 drm_modeset_lock_all(dev);
863 dm_restore_drm_connector_state(dev, connector);
864 drm_modeset_unlock_all(dev);
865
866 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
867 drm_kms_helper_hotplug_event(dev);
868 }
869 mutex_unlock(&aconnector->hpd_lock);
870
871}
872
873static void dm_handle_hpd_rx_irq(struct amdgpu_connector *aconnector)
874{
875 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
876 uint8_t dret;
877 bool new_irq_handled = false;
878 int dpcd_addr;
879 int dpcd_bytes_to_read;
880
881 const int max_process_count = 30;
882 int process_count = 0;
883
884 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
885
886 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
887 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
888 /* DPCD 0x200 - 0x201 for downstream IRQ */
889 dpcd_addr = DP_SINK_COUNT;
890 } else {
891 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
892 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
893 dpcd_addr = DP_SINK_COUNT_ESI;
894 }
895
896 dret = drm_dp_dpcd_read(
897 &aconnector->dm_dp_aux.aux,
898 dpcd_addr,
899 esi,
900 dpcd_bytes_to_read);
901
902 while (dret == dpcd_bytes_to_read &&
903 process_count < max_process_count) {
904 uint8_t retry;
905 dret = 0;
906
907 process_count++;
908
909 DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 910 /* handle HPD short pulse irq */
911 if (aconnector->mst_mgr.mst_state)
912 drm_dp_mst_hpd_irq(
913 &aconnector->mst_mgr,
914 esi,
915 &new_irq_handled);
4562236b
HW		 916
917 if (new_irq_handled) {
918 /* ACK at DPCD to notify down stream */
919 const int ack_dpcd_bytes_to_write =
920 dpcd_bytes_to_read - 1;
921
922 for (retry = 0; retry < 3; retry++) {
923 uint8_t wret;
924
925 wret = drm_dp_dpcd_write(
926 &aconnector->dm_dp_aux.aux,
927 dpcd_addr + 1,
928 &esi[1],
929 ack_dpcd_bytes_to_write);
930 if (wret == ack_dpcd_bytes_to_write)
931 break;
932 }
933
934 /* check if there is new irq to be handle */
935 dret = drm_dp_dpcd_read(
936 &aconnector->dm_dp_aux.aux,
937 dpcd_addr,
938 esi,
939 dpcd_bytes_to_read);
940
941 new_irq_handled = false;
942 } else
943 break;
944 }
945
946 if (process_count == max_process_count)
947 DRM_DEBUG_KMS("Loop exceeded max iterations\n");
948}
949
950static void handle_hpd_rx_irq(void *param)
951{
952 struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
953 struct drm_connector *connector = &aconnector->base;
954 struct drm_device *dev = connector->dev;
955 const struct dc_link *dc_link = aconnector->dc_link;
956 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
957
958 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
959 * conflict, after implement i2c helper, this mutex should be
960 * retired.
961 */
962 if (aconnector->dc_link->type != dc_connection_mst_branch)
963 mutex_lock(&aconnector->hpd_lock);
964
8ee65d7c 965 if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
4562236b
HW		 966 !is_mst_root_connector) {
967 /* Downstream Port status changed. */
968 if (dc_link_detect(aconnector->dc_link, false)) {
969 amdgpu_dm_update_connector_after_detect(aconnector);
970
971
972 drm_modeset_lock_all(dev);
973 dm_restore_drm_connector_state(dev, connector);
974 drm_modeset_unlock_all(dev);
975
976 drm_kms_helper_hotplug_event(dev);
977 }
978 }
979 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
980 (dc_link->type == dc_connection_mst_branch))
981 dm_handle_hpd_rx_irq(aconnector);
982
983 if (aconnector->dc_link->type != dc_connection_mst_branch)
984 mutex_unlock(&aconnector->hpd_lock);
985}
986
987static void register_hpd_handlers(struct amdgpu_device *adev)
988{
989 struct drm_device *dev = adev->ddev;
990 struct drm_connector *connector;
991 struct amdgpu_connector *aconnector;
992 const struct dc_link *dc_link;
993 struct dc_interrupt_params int_params = {0};
994
995 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
996 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
997
998 list_for_each_entry(connector,
999 &dev->mode_config.connector_list, head) {
1000
1001 aconnector = to_amdgpu_connector(connector);
1002 dc_link = aconnector->dc_link;
1003
1004 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1005 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1006 int_params.irq_source = dc_link->irq_source_hpd;
1007
1008 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1009 handle_hpd_irq,
1010 (void *) aconnector);
1011 }
1012
1013 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1014
1015 /* Also register for DP short pulse (hpd_rx). */
1016 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1017 int_params.irq_source = dc_link->irq_source_hpd_rx;
1018
1019 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1020 handle_hpd_rx_irq,
1021 (void *) aconnector);
1022 }
1023 }
1024}
1025
1026/* Register IRQ sources and initialize IRQ callbacks */
1027static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1028{
1029 struct dc *dc = adev->dm.dc;
1030 struct common_irq_params *c_irq_params;
1031 struct dc_interrupt_params int_params = {0};
1032 int r;
1033 int i;
2c8ad2d5
AD		 1034 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1035
ff5ef992
AD		 1036 if (adev->asic_type == CHIP_VEGA10 ||
1037 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1038 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1039
1040 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1041 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1042
1043 /* Actions of amdgpu_irq_add_id():
1044 * 1. Register a set() function with base driver.
1045 * Base driver will call set() function to enable/disable an
1046 * interrupt in DC hardware.
1047 * 2. Register amdgpu_dm_irq_handler().
1048 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1049 * coming from DC hardware.
1050 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1051 * for acknowledging and handling. */
1052
b57de80a 1053 /* Use VBLANK interrupt */
e9029155 1054 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1055 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1056 if (r) {
1057 DRM_ERROR("Failed to add crtc irq id!\n");
1058 return r;
1059 }
1060
1061 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1062 int_params.irq_source =
3d761e79 1063 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1064
b57de80a 1065 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1066
1067 c_irq_params->adev = adev;
1068 c_irq_params->irq_src = int_params.irq_source;
1069
1070 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1071 dm_crtc_high_irq, c_irq_params);
1072 }
1073
3d761e79 1074 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1075 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1076 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1077 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1078 if (r) {
1079 DRM_ERROR("Failed to add page flip irq id!\n");
1080 return r;
1081 }
1082
1083 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1084 int_params.irq_source =
1085 dc_interrupt_to_irq_source(dc, i, 0);
1086
1087 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1088
1089 c_irq_params->adev = adev;
1090 c_irq_params->irq_src = int_params.irq_source;
1091
1092 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1093 dm_pflip_high_irq, c_irq_params);
1094
1095 }
1096
1097 /* HPD */
2c8ad2d5
AD		 1098 r = amdgpu_irq_add_id(adev, client_id,
1099 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1100 if (r) {
1101 DRM_ERROR("Failed to add hpd irq id!\n");
1102 return r;
1103 }
1104
1105 register_hpd_handlers(adev);
1106
1107 return 0;
1108}
1109
ff5ef992
AD		 1110#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1111/* Register IRQ sources and initialize IRQ callbacks */
1112static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1113{
1114 struct dc *dc = adev->dm.dc;
1115 struct common_irq_params *c_irq_params;
1116 struct dc_interrupt_params int_params = {0};
1117 int r;
1118 int i;
1119
1120 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1121 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1122
1123 /* Actions of amdgpu_irq_add_id():
1124 * 1. Register a set() function with base driver.
1125 * Base driver will call set() function to enable/disable an
1126 * interrupt in DC hardware.
1127 * 2. Register amdgpu_dm_irq_handler().
1128 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1129 * coming from DC hardware.
1130 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1131 * for acknowledging and handling.
1132 * */
1133
1134 /* Use VSTARTUP interrupt */
1135 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1136 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1137 i++) {
1138 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1139
1140 if (r) {
1141 DRM_ERROR("Failed to add crtc irq id!\n");
1142 return r;
1143 }
1144
1145 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1146 int_params.irq_source =
1147 dc_interrupt_to_irq_source(dc, i, 0);
1148
1149 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1150
1151 c_irq_params->adev = adev;
1152 c_irq_params->irq_src = int_params.irq_source;
1153
1154 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1155 dm_crtc_high_irq, c_irq_params);
1156 }
1157
1158 /* Use GRPH_PFLIP interrupt */
1159 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1160 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1161 i++) {
1162 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1163 if (r) {
1164 DRM_ERROR("Failed to add page flip irq id!\n");
1165 return r;
1166 }
1167
1168 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1169 int_params.irq_source =
1170 dc_interrupt_to_irq_source(dc, i, 0);
1171
1172 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1173
1174 c_irq_params->adev = adev;
1175 c_irq_params->irq_src = int_params.irq_source;
1176
1177 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1178 dm_pflip_high_irq, c_irq_params);
1179
1180 }
1181
1182 /* HPD */
1183 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1184 &adev->hpd_irq);
1185 if (r) {
1186 DRM_ERROR("Failed to add hpd irq id!\n");
1187 return r;
1188 }
1189
1190 register_hpd_handlers(adev);
1191
1192 return 0;
1193}
1194#endif
1195
4562236b
HW		 1196static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1197{
1198 int r;
1199
1200 adev->mode_info.mode_config_initialized = true;
1201
4562236b 1202 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1203 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1204
1205 adev->ddev->mode_config.max_width = 16384;
1206 adev->ddev->mode_config.max_height = 16384;
1207
1208 adev->ddev->mode_config.preferred_depth = 24;
1209 adev->ddev->mode_config.prefer_shadow = 1;
1210 /* indicate support of immediate flip */
1211 adev->ddev->mode_config.async_page_flip = true;
1212
1213 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1214
1215 r = amdgpu_modeset_create_props(adev);
1216 if (r)
1217 return r;
1218
1219 return 0;
1220}
1221
1222#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1223 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1224
1225static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1226{
1227 struct amdgpu_display_manager *dm = bl_get_data(bd);
1228
1229 if (dc_link_set_backlight_level(dm->backlight_link,
1230 bd->props.brightness, 0, 0))
1231 return 0;
1232 else
1233 return 1;
1234}
1235
1236static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1237{
1238 return bd->props.brightness;
1239}
1240
1241static const struct backlight_ops amdgpu_dm_backlight_ops = {
1242 .get_brightness = amdgpu_dm_backlight_get_brightness,
1243 .update_status = amdgpu_dm_backlight_update_status,
1244};
1245
1246void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1247{
1248 char bl_name[16];
1249 struct backlight_properties props = { 0 };
1250
1251 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1252 props.type = BACKLIGHT_RAW;
1253
1254 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1255 dm->adev->ddev->primary->index);
1256
1257 dm->backlight_dev = backlight_device_register(bl_name,
1258 dm->adev->ddev->dev,
1259 dm,
1260 &amdgpu_dm_backlight_ops,
1261 &props);
1262
1263 if (NULL == dm->backlight_dev)
1264 DRM_ERROR("DM: Backlight registration failed!\n");
1265 else
1266 DRM_INFO("DM: Registered Backlight device: %s\n", bl_name);
1267}
1268
1269#endif
1270
1271/* In this architecture, the association
1272 * connector -> encoder -> crtc
1273 * id not really requried. The crtc and connector will hold the
1274 * display_index as an abstraction to use with DAL component
1275 *
1276 * Returns 0 on success
1277 */
1278int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1279{
1280 struct amdgpu_display_manager *dm = &adev->dm;
1281 uint32_t i;
f2a0f5e6
HW		 1282 struct amdgpu_connector *aconnector = NULL;
1283 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1284 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1285 uint32_t link_cnt;
92f3ac40 1286 unsigned long possible_crtcs;
4562236b
HW		 1287
1288 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1289 if (amdgpu_dm_mode_config_init(dm->adev)) {
1290 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1291 return -1;
4562236b
HW		 1292 }
1293
3be5262e 1294 for (i = 0; i < dm->dc->caps.max_planes; i++) {
d4e13b0d
AD		 1295 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1296 GFP_KERNEL);
1297 if (!mode_info->planes[i]) {
3be5262e 1298 DRM_ERROR("KMS: Failed to allocate plane\n");
d4e13b0d
AD		 1299 goto fail_free_planes;
1300 }
1605b3be 1301 mode_info->planes[i]->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1302
1303 /*
1304 * HACK: IGT tests expect that each plane can only have one
1305 * one possible CRTC. For now, set one CRTC for each
1306 * plane that is not an underlay, but still allow multiple
1307 * CRTCs for underlay planes.
1308 */
1309 possible_crtcs = 1 << i;
1310 if (i >= dm->dc->caps.max_streams)
1311 possible_crtcs = 0xff;
1312
1313 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d
AD		 1314 DRM_ERROR("KMS: Failed to initialize plane\n");
1315 goto fail_free_planes;
1316 }
1317 }
4562236b 1318
d4e13b0d
AD		 1319 for (i = 0; i < dm->dc->caps.max_streams; i++)
1320 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1321 DRM_ERROR("KMS: Failed to initialize crtc\n");
d4e13b0d 1322 goto fail_free_planes;
4562236b 1323 }
4562236b 1324
ab2541b6 1325 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1326
1327 /* loops over all connectors on the board */
1328 for (i = 0; i < link_cnt; i++) {
1329
1330 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1331 DRM_ERROR(
1332 "KMS: Cannot support more than %d display indexes\n",
1333 AMDGPU_DM_MAX_DISPLAY_INDEX);
1334 continue;
1335 }
1336
1337 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1338 if (!aconnector)
f2a0f5e6 1339 goto fail_free_planes;
4562236b
HW		 1340
1341 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1342 if (!aencoder) {
1343 goto fail_free_connector;
1344 }
1345
1346 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1347 DRM_ERROR("KMS: Failed to initialize encoder\n");
1348 goto fail_free_encoder;
1349 }
1350
1351 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1352 DRM_ERROR("KMS: Failed to initialize connector\n");
f2a0f5e6 1353 goto fail_free_encoder;
4562236b
HW		 1354 }
1355
1356 if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true))
1357 amdgpu_dm_update_connector_after_detect(aconnector);
1358 }
1359
1360 /* Software is initialized. Now we can register interrupt handlers. */
1361 switch (adev->asic_type) {
1362 case CHIP_BONAIRE:
1363 case CHIP_HAWAII:
cd4b356f
AD		 1364 case CHIP_KAVERI:
1365 case CHIP_KABINI:
1366 case CHIP_MULLINS:
4562236b
HW		 1367 case CHIP_TONGA:
1368 case CHIP_FIJI:
1369 case CHIP_CARRIZO:
1370 case CHIP_STONEY:
1371 case CHIP_POLARIS11:
1372 case CHIP_POLARIS10:
b264d345 1373 case CHIP_POLARIS12:
2c8ad2d5 1374 case CHIP_VEGA10:
4562236b
HW		 1375 if (dce110_register_irq_handlers(dm->adev)) {
1376 DRM_ERROR("DM: Failed to initialize IRQ\n");
d4e13b0d 1377 goto fail_free_encoder;
4562236b
HW		 1378 }
1379 break;
ff5ef992
AD		 1380#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1381 case CHIP_RAVEN:
1382 if (dcn10_register_irq_handlers(dm->adev)) {
1383 DRM_ERROR("DM: Failed to initialize IRQ\n");
1384 goto fail_free_encoder;
1385 }
79c24086
BL		 1386 /*
1387 * Temporary disable until pplib/smu interaction is implemented
1388 */
1389 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1390 break;
1391#endif
4562236b
HW		 1392 default:
1393 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
d4e13b0d 1394 goto fail_free_encoder;
4562236b
HW		 1395 }
1396
1397 drm_mode_config_reset(dm->ddev);
1398
1399 return 0;
1400fail_free_encoder:
1401 kfree(aencoder);
1402fail_free_connector:
1403 kfree(aconnector);
d4e13b0d 1404fail_free_planes:
3be5262e 1405 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1406 kfree(mode_info->planes[i]);
4562236b
HW		 1407 return -1;
1408}
1409
1410void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1411{
1412 drm_mode_config_cleanup(dm->ddev);
1413 return;
1414}
1415
1416/******************************************************************************
1417 * amdgpu_display_funcs functions
1418 *****************************************************************************/
1419
1420/**
1421 * dm_bandwidth_update - program display watermarks
1422 *
1423 * @adev: amdgpu_device pointer
1424 *
1425 * Calculate and program the display watermarks and line buffer allocation.
1426 */
1427static void dm_bandwidth_update(struct amdgpu_device *adev)
1428{
49c07a99 1429 /* TODO: implement later */
4562236b
HW		 1430}
1431
1432static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1433 u8 level)
1434{
1435 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1436}
1437
1438static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1439{
1440 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1441 return 0;
1442}
1443
4562236b
HW		 1444static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1445 struct drm_file *filp)
1446{
1447 struct mod_freesync_params freesync_params;
ab2541b6 1448 uint8_t num_streams;
4562236b 1449 uint8_t i;
4562236b
HW		 1450
1451 struct amdgpu_device *adev = dev->dev_private;
1452 int r = 0;
1453
1454 /* Get freesync enable flag from DRM */
1455
ab2541b6 1456 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1457
ab2541b6 1458 for (i = 0; i < num_streams; i++) {
0971c40e 1459 struct dc_stream_state *stream;
ab2541b6 1460 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1461
1462 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1463 &stream, 1, &freesync_params);
4562236b
HW		 1464 }
1465
1466 return r;
1467}
1468
39cc5be2 1469static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1470 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1471 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1472 .vblank_wait = NULL,
1473 .backlight_set_level =
1474 dm_set_backlight_level,/* called unconditionally */
1475 .backlight_get_level =
1476 dm_get_backlight_level,/* called unconditionally */
1477 .hpd_sense = NULL,/* called unconditionally */
1478 .hpd_set_polarity = NULL, /* called unconditionally */
1479 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1480 .page_flip_get_scanoutpos =
1481 dm_crtc_get_scanoutpos,/* called unconditionally */
1482 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1483 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1484 .notify_freesync = amdgpu_notify_freesync,
1485
1486};
1487
1488#if defined(CONFIG_DEBUG_KERNEL_DC)
1489
1490static ssize_t s3_debug_store(
1491 struct device *device,
1492 struct device_attribute *attr,
1493 const char *buf,
1494 size_t count)
1495{
1496 int ret;
1497 int s3_state;
1498 struct pci_dev *pdev = to_pci_dev(device);
1499 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1500 struct amdgpu_device *adev = drm_dev->dev_private;
1501
1502 ret = kstrtoint(buf, 0, &s3_state);
1503
1504 if (ret == 0) {
1505 if (s3_state) {
1506 dm_resume(adev);
1507 amdgpu_dm_display_resume(adev);
1508 drm_kms_helper_hotplug_event(adev->ddev);
1509 } else
1510 dm_suspend(adev);
1511 }
1512
1513 return ret == 0 ? count : 0;
1514}
1515
1516DEVICE_ATTR_WO(s3_debug);
1517
1518#endif
1519
1520static int dm_early_init(void *handle)
1521{
1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1523
d7ec53d9 1524 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1525 amdgpu_dm_set_irq_funcs(adev);
1526
1527 switch (adev->asic_type) {
1528 case CHIP_BONAIRE:
1529 case CHIP_HAWAII:
1530 adev->mode_info.num_crtc = 6;
1531 adev->mode_info.num_hpd = 6;
1532 adev->mode_info.num_dig = 6;
3be5262e 1533 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1534 break;
cd4b356f
AD		 1535 case CHIP_KAVERI:
1536 adev->mode_info.num_crtc = 4;
1537 adev->mode_info.num_hpd = 6;
1538 adev->mode_info.num_dig = 7;
1539 adev->mode_info.plane_type = dm_plane_type_default;
1540 break;
1541 case CHIP_KABINI:
1542 case CHIP_MULLINS:
1543 adev->mode_info.num_crtc = 2;
1544 adev->mode_info.num_hpd = 6;
1545 adev->mode_info.num_dig = 6;
1546 adev->mode_info.plane_type = dm_plane_type_default;
1547 break;
4562236b
HW		 1548 case CHIP_FIJI:
1549 case CHIP_TONGA:
1550 adev->mode_info.num_crtc = 6;
1551 adev->mode_info.num_hpd = 6;
1552 adev->mode_info.num_dig = 7;
3be5262e 1553 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1554 break;
1555 case CHIP_CARRIZO:
1556 adev->mode_info.num_crtc = 3;
1557 adev->mode_info.num_hpd = 6;
1558 adev->mode_info.num_dig = 9;
3be5262e 1559 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1560 break;
1561 case CHIP_STONEY:
1562 adev->mode_info.num_crtc = 2;
1563 adev->mode_info.num_hpd = 6;
1564 adev->mode_info.num_dig = 9;
3be5262e 1565 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1566 break;
1567 case CHIP_POLARIS11:
b264d345 1568 case CHIP_POLARIS12:
4562236b
HW		 1569 adev->mode_info.num_crtc = 5;
1570 adev->mode_info.num_hpd = 5;
1571 adev->mode_info.num_dig = 5;
3be5262e 1572 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1573 break;
1574 case CHIP_POLARIS10:
1575 adev->mode_info.num_crtc = 6;
1576 adev->mode_info.num_hpd = 6;
1577 adev->mode_info.num_dig = 6;
3be5262e 1578 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1579 break;
2c8ad2d5
AD		 1580 case CHIP_VEGA10:
1581 adev->mode_info.num_crtc = 6;
1582 adev->mode_info.num_hpd = 6;
1583 adev->mode_info.num_dig = 6;
3be5262e 1584 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1585 break;
ff5ef992
AD		 1586#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1587 case CHIP_RAVEN:
1588 adev->mode_info.num_crtc = 4;
1589 adev->mode_info.num_hpd = 4;
1590 adev->mode_info.num_dig = 4;
3be5262e 1591 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1592 break;
1593#endif
4562236b
HW		 1594 default:
1595 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1596 return -EINVAL;
1597 }
1598
39cc5be2
AD		 1599 if (adev->mode_info.funcs == NULL)
1600 adev->mode_info.funcs = &dm_display_funcs;
1601
4562236b
HW		 1602 /* Note: Do NOT change adev->audio_endpt_rreg and
1603 * adev->audio_endpt_wreg because they are initialised in
1604 * amdgpu_device_init() */
1605#if defined(CONFIG_DEBUG_KERNEL_DC)
1606 device_create_file(
1607 adev->ddev->dev,
1608 &dev_attr_s3_debug);
1609#endif
1610
1611 return 0;
1612}
1613
1614bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm)
1615{
1616 /* TODO */
1617 return true;
1618}
1619
1620bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm)
1621{
e1403629
HW		 1622 /* TODO */
1623 return true;
e7b07cee
HW		 1624}
1625
1626
1627struct dm_connector_state {
1628 struct drm_connector_state base;
1629
1630 enum amdgpu_rmx_type scaling;
1631 uint8_t underscan_vborder;
1632 uint8_t underscan_hborder;
1633 bool underscan_enable;
1634};
1635
1636#define to_dm_connector_state(x)\
1637 container_of((x), struct dm_connector_state, base)
1638
9b690ef3 1639static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1640 struct dc_stream_state *new_stream,
1641 struct dc_stream_state *old_stream)
9b690ef3 1642{
e7b07cee
HW		 1643 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1644 return false;
1645
1646 if (!crtc_state->enable)
1647 return false;
1648
1649 return crtc_state->active;
1650}
1651
1652static bool modereset_required(struct drm_crtc_state *crtc_state)
1653{
1654 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1655 return false;
1656
1657 return !crtc_state->enable || !crtc_state->active;
1658}
1659
1660void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1661{
1662 drm_encoder_cleanup(encoder);
1663 kfree(encoder);
1664}
1665
1666static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1667 .destroy = amdgpu_dm_encoder_destroy,
1668};
1669
e7b07cee
HW		 1670static bool fill_rects_from_plane_state(
1671 const struct drm_plane_state *state,
3be5262e 1672 struct dc_plane_state *plane_state)
e7b07cee 1673{
3be5262e
HW		 1674 plane_state->src_rect.x = state->src_x >> 16;
1675 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1676 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1677 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1678
3be5262e 1679 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1680 return false;
1681
3be5262e
HW		 1682 plane_state->src_rect.height = state->src_h >> 16;
1683 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1684 return false;
1685
3be5262e
HW		 1686 plane_state->dst_rect.x = state->crtc_x;
1687 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1688
1689 if (state->crtc_w == 0)
1690 return false;
1691
3be5262e 1692 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1693
1694 if (state->crtc_h == 0)
1695 return false;
1696
3be5262e 1697 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1698
3be5262e 1699 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1700
1701 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1702 case DRM_MODE_ROTATE_0:
3be5262e 1703 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1704 break;
1705 case DRM_MODE_ROTATE_90:
3be5262e 1706 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1707 break;
1708 case DRM_MODE_ROTATE_180:
3be5262e 1709 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1710 break;
1711 case DRM_MODE_ROTATE_270:
3be5262e 1712 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1713 break;
1714 default:
3be5262e 1715 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1716 break;
1717 }
1718
4562236b
HW		 1719 return true;
1720}
e7b07cee
HW		 1721static int get_fb_info(
1722 const struct amdgpu_framebuffer *amdgpu_fb,
1723 uint64_t *tiling_flags,
1724 uint64_t *fb_location)
1725{
1726 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1727 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1728
e7b07cee
HW		 1729 if (unlikely(r)) {
1730 DRM_ERROR("Unable to reserve buffer\n");
1731 return r;
1732 }
1733
1734 if (fb_location)
1735 *fb_location = amdgpu_bo_gpu_offset(rbo);
1736
1737 if (tiling_flags)
1738 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1739
1740 amdgpu_bo_unreserve(rbo);
1741
1742 return r;
1743}
1744
1745static int fill_plane_attributes_from_fb(
1746 struct amdgpu_device *adev,
3be5262e 1747 struct dc_plane_state *plane_state,
e7b07cee
HW		 1748 const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
1749{
1750 uint64_t tiling_flags;
1751 uint64_t fb_location = 0;
1752 unsigned int awidth;
1753 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1754 int ret = 0;
1755 struct drm_format_name_buf format_name;
1756
1757 ret = get_fb_info(
1758 amdgpu_fb,
1759 &tiling_flags,
1760 addReq == true ? &fb_location:NULL);
1761
1762 if (ret)
1763 return ret;
1764
1765 switch (fb->format->format) {
1766 case DRM_FORMAT_C8:
3be5262e 1767 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1768 break;
1769 case DRM_FORMAT_RGB565:
3be5262e 1770 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1771 break;
1772 case DRM_FORMAT_XRGB8888:
1773 case DRM_FORMAT_ARGB8888:
3be5262e 1774 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1775 break;
1776 case DRM_FORMAT_XRGB2101010:
1777 case DRM_FORMAT_ARGB2101010:
3be5262e 1778 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1779 break;
1780 case DRM_FORMAT_XBGR2101010:
1781 case DRM_FORMAT_ABGR2101010:
3be5262e 1782 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1783 break;
1784 case DRM_FORMAT_NV21:
3be5262e 1785 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1786 break;
1787 case DRM_FORMAT_NV12:
3be5262e 1788 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1789 break;
1790 default:
1791 DRM_ERROR("Unsupported screen format %s\n",
1792 drm_get_format_name(fb->format->format, &format_name));
1793 return -EINVAL;
1794 }
1795
3be5262e
HW		 1796 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1797 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1798 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1799 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1800 plane_state->plane_size.grph.surface_size.x = 0;
1801 plane_state->plane_size.grph.surface_size.y = 0;
1802 plane_state->plane_size.grph.surface_size.width = fb->width;
1803 plane_state->plane_size.grph.surface_size.height = fb->height;
1804 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1805 fb->pitches[0] / fb->format->cpp[0];
1806 /* TODO: unhardcode */
3be5262e 1807 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1808
1809 } else {
1810 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1811 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1812 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1813 = lower_32_bits(fb_location);
3be5262e 1814 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 1815 = lower_32_bits(fb_location) +
1816 (awidth * fb->height);
3be5262e
HW		 1817 plane_state->plane_size.video.luma_size.x = 0;
1818 plane_state->plane_size.video.luma_size.y = 0;
1819 plane_state->plane_size.video.luma_size.width = awidth;
1820 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1821 /* TODO: unhardcode */
3be5262e 1822 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1823
3be5262e
HW		 1824 plane_state->plane_size.video.chroma_size.x = 0;
1825 plane_state->plane_size.video.chroma_size.y = 0;
1826 plane_state->plane_size.video.chroma_size.width = awidth;
1827 plane_state->plane_size.video.chroma_size.height = fb->height;
1828 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1829
1830 /* TODO: unhardcode */
3be5262e 1831 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1832 }
1833
3be5262e 1834 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1835
b830ebc9
HW		 1836 /* Fill GFX8 params */
1837 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1838 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1839
1840 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1841 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1842 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1843 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1844 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1845
1846 /* XXX fix me for VI */
3be5262e
HW		 1847 plane_state->tiling_info.gfx8.num_banks = num_banks;
1848 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1849 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1850 plane_state->tiling_info.gfx8.tile_split = tile_split;
1851 plane_state->tiling_info.gfx8.bank_width = bankw;
1852 plane_state->tiling_info.gfx8.bank_height = bankh;
1853 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1854 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1855 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1856 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1857 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1858 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1859 }
1860
3be5262e 1861 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1862 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1863
1864 if (adev->asic_type == CHIP_VEGA10 ||
1865 adev->asic_type == CHIP_RAVEN) {
1866 /* Fill GFX9 params */
3be5262e 1867 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1868 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1869 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1870 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1871 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1872 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1873 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1874 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1875 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1876 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1877 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1878 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1879 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1880 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1881 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1882 }
1883
3be5262e
HW		 1884 plane_state->visible = true;
1885 plane_state->scaling_quality.h_taps_c = 0;
1886 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1887
3be5262e
HW		 1888 /* is this needed? is plane_state zeroed at allocation? */
1889 plane_state->scaling_quality.h_taps = 0;
1890 plane_state->scaling_quality.v_taps = 0;
1891 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1892
1893 return ret;
1894
1895}
1896
e7b07cee
HW		 1897static void fill_gamma_from_crtc_state(
1898 const struct drm_crtc_state *crtc_state,
3be5262e 1899 struct dc_plane_state *plane_state)
e7b07cee
HW		 1900{
1901 int i;
1902 struct dc_gamma *gamma;
d66cf5f5
AK		 1903 struct drm_color_lut *lut =
1904 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1905
1906 gamma = dc_create_gamma();
1907
1908 if (gamma == NULL) {
1909 WARN_ON(1);
1910 return;
1911 }
1912
7483bed4
HW		 1913 gamma->type = GAMMA_RGB_256;
1914 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1915 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1916 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1917 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1918 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1919 }
1920
3be5262e 1921 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1922}
1923
1924static int fill_plane_attributes(
1925 struct amdgpu_device *adev,
3be5262e 1926 struct dc_plane_state *dc_plane_state,
e7b07cee
HW		 1927 struct drm_plane_state *plane_state,
1928 struct drm_crtc_state *crtc_state,
1929 bool addrReq)
1930{
1931 const struct amdgpu_framebuffer *amdgpu_fb =
1932 to_amdgpu_framebuffer(plane_state->fb);
1933 const struct drm_crtc *crtc = plane_state->crtc;
1934 struct dc_transfer_func *input_tf;
1935 int ret = 0;
1936
3be5262e 1937 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1938 return -EINVAL;
1939
1940 ret = fill_plane_attributes_from_fb(
1941 crtc->dev->dev_private,
3be5262e 1942 dc_plane_state,
e7b07cee
HW		 1943 amdgpu_fb,
1944 addrReq);
1945
1946 if (ret)
1947 return ret;
1948
1949 input_tf = dc_create_transfer_func();
1950
1951 if (input_tf == NULL)
1952 return -ENOMEM;
1953
1954 input_tf->type = TF_TYPE_PREDEFINED;
1955 input_tf->tf = TRANSFER_FUNCTION_SRGB;
1956
3be5262e 1957 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 1958
1959 /* In case of gamma set, update gamma value */
1960 if (crtc_state->gamma_lut)
3be5262e 1961 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 1962
1963 return ret;
1964}
1965
1966/*****************************************************************************/
1967
1968struct amdgpu_connector *aconnector_from_drm_crtc_id(
1969 const struct drm_crtc *crtc)
1970{
1971 struct drm_device *dev = crtc->dev;
1972 struct drm_connector *connector;
1973 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
1974 struct amdgpu_connector *aconnector;
1975
1976 list_for_each_entry(connector,
1977 &dev->mode_config.connector_list, head) {
1978
1979 aconnector = to_amdgpu_connector(connector);
1980
1981 if (aconnector->base.state->crtc != &acrtc->base)
1982 continue;
1983
1984 /* Found the connector */
1985 return aconnector;
1986 }
1987
1988 /* If we get here, not found. */
1989 return NULL;
1990}
1991
1992static void update_stream_scaling_settings(
1993 const struct drm_display_mode *mode,
1994 const struct dm_connector_state *dm_state,
0971c40e 1995 struct dc_stream_state *stream)
e7b07cee
HW		 1996{
1997 enum amdgpu_rmx_type rmx_type;
1998
1999 struct rect src = { 0 }; /* viewport in composition space*/
2000 struct rect dst = { 0 }; /* stream addressable area */
2001
2002 /* no mode. nothing to be done */
2003 if (!mode)
2004 return;
2005
2006 /* Full screen scaling by default */
2007 src.width = mode->hdisplay;
2008 src.height = mode->vdisplay;
2009 dst.width = stream->timing.h_addressable;
2010 dst.height = stream->timing.v_addressable;
2011
2012 rmx_type = dm_state->scaling;
2013 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2014 if (src.width * dst.height <
2015 src.height * dst.width) {
2016 /* height needs less upscaling/more downscaling */
2017 dst.width = src.width *
2018 dst.height / src.height;
2019 } else {
2020 /* width needs less upscaling/more downscaling */
2021 dst.height = src.height *
2022 dst.width / src.width;
2023 }
2024 } else if (rmx_type == RMX_CENTER) {
2025 dst = src;
2026 }
2027
2028 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2029 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2030
2031 if (dm_state->underscan_enable) {
2032 dst.x += dm_state->underscan_hborder / 2;
2033 dst.y += dm_state->underscan_vborder / 2;
2034 dst.width -= dm_state->underscan_hborder;
2035 dst.height -= dm_state->underscan_vborder;
2036 }
2037
2038 stream->src = src;
2039 stream->dst = dst;
2040
2041 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
2042 dst.x, dst.y, dst.width, dst.height);
2043
2044}
2045
2046static enum dc_color_depth convert_color_depth_from_display_info(
2047 const struct drm_connector *connector)
2048{
2049 uint32_t bpc = connector->display_info.bpc;
2050
2051 /* Limited color depth to 8bit
b830ebc9
HW		 2052 * TODO: Still need to handle deep color
2053 */
e7b07cee
HW		 2054 if (bpc > 8)
2055 bpc = 8;
2056
2057 switch (bpc) {
2058 case 0:
2059 /* Temporary Work around, DRM don't parse color depth for
2060 * EDID revision before 1.4
2061 * TODO: Fix edid parsing
2062 */
2063 return COLOR_DEPTH_888;
2064 case 6:
2065 return COLOR_DEPTH_666;
2066 case 8:
2067 return COLOR_DEPTH_888;
2068 case 10:
2069 return COLOR_DEPTH_101010;
2070 case 12:
2071 return COLOR_DEPTH_121212;
2072 case 14:
2073 return COLOR_DEPTH_141414;
2074 case 16:
2075 return COLOR_DEPTH_161616;
2076 default:
2077 return COLOR_DEPTH_UNDEFINED;
2078 }
2079}
2080
2081static enum dc_aspect_ratio get_aspect_ratio(
2082 const struct drm_display_mode *mode_in)
2083{
2084 int32_t width = mode_in->crtc_hdisplay * 9;
2085 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2086
e7b07cee
HW		 2087 if ((width - height) < 10 && (width - height) > -10)
2088 return ASPECT_RATIO_16_9;
2089 else
2090 return ASPECT_RATIO_4_3;
2091}
2092
2093static enum dc_color_space get_output_color_space(
2094 const struct dc_crtc_timing *dc_crtc_timing)
2095{
2096 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2097
2098 switch (dc_crtc_timing->pixel_encoding) {
2099 case PIXEL_ENCODING_YCBCR422:
2100 case PIXEL_ENCODING_YCBCR444:
2101 case PIXEL_ENCODING_YCBCR420:
2102 {
2103 /*
2104 * 27030khz is the separation point between HDTV and SDTV
2105 * according to HDMI spec, we use YCbCr709 and YCbCr601
2106 * respectively
2107 */
2108 if (dc_crtc_timing->pix_clk_khz > 27030) {
2109 if (dc_crtc_timing->flags.Y_ONLY)
2110 color_space =
2111 COLOR_SPACE_YCBCR709_LIMITED;
2112 else
2113 color_space = COLOR_SPACE_YCBCR709;
2114 } else {
2115 if (dc_crtc_timing->flags.Y_ONLY)
2116 color_space =
2117 COLOR_SPACE_YCBCR601_LIMITED;
2118 else
2119 color_space = COLOR_SPACE_YCBCR601;
2120 }
2121
2122 }
2123 break;
2124 case PIXEL_ENCODING_RGB:
2125 color_space = COLOR_SPACE_SRGB;
2126 break;
2127
2128 default:
2129 WARN_ON(1);
2130 break;
2131 }
2132
2133 return color_space;
2134}
2135
2136/*****************************************************************************/
2137
2138static void fill_stream_properties_from_drm_display_mode(
0971c40e 2139 struct dc_stream_state *stream,
e7b07cee
HW		 2140 const struct drm_display_mode *mode_in,
2141 const struct drm_connector *connector)
2142{
2143 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2144
e7b07cee
HW		 2145 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2146
2147 timing_out->h_border_left = 0;
2148 timing_out->h_border_right = 0;
2149 timing_out->v_border_top = 0;
2150 timing_out->v_border_bottom = 0;
2151 /* TODO: un-hardcode */
2152
2153 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2154 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2155 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2156 else
2157 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2158
2159 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2160 timing_out->display_color_depth = convert_color_depth_from_display_info(
2161 connector);
2162 timing_out->scan_type = SCANNING_TYPE_NODATA;
2163 timing_out->hdmi_vic = 0;
2164 timing_out->vic = drm_match_cea_mode(mode_in);
2165
2166 timing_out->h_addressable = mode_in->crtc_hdisplay;
2167 timing_out->h_total = mode_in->crtc_htotal;
2168 timing_out->h_sync_width =
2169 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2170 timing_out->h_front_porch =
2171 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2172 timing_out->v_total = mode_in->crtc_vtotal;
2173 timing_out->v_addressable = mode_in->crtc_vdisplay;
2174 timing_out->v_front_porch =
2175 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2176 timing_out->v_sync_width =
2177 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2178 timing_out->pix_clk_khz = mode_in->crtc_clock;
2179 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2180 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2181 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2182 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2183 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2184
2185 stream->output_color_space = get_output_color_space(timing_out);
2186
2187 {
2188 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2189
e7b07cee
HW		 2190 tf->type = TF_TYPE_PREDEFINED;
2191 tf->tf = TRANSFER_FUNCTION_SRGB;
2192 stream->out_transfer_func = tf;
2193 }
2194}
2195
2196static void fill_audio_info(
2197 struct audio_info *audio_info,
2198 const struct drm_connector *drm_connector,
2199 const struct dc_sink *dc_sink)
2200{
2201 int i = 0;
2202 int cea_revision = 0;
2203 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2204
2205 audio_info->manufacture_id = edid_caps->manufacturer_id;
2206 audio_info->product_id = edid_caps->product_id;
2207
2208 cea_revision = drm_connector->display_info.cea_rev;
2209
2210 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
2211 edid_caps->display_name[i]) {
2212 audio_info->display_name[i] = edid_caps->display_name[i];
2213 i++;
2214 }
2215
b830ebc9 2216 if (cea_revision >= 3) {
e7b07cee
HW		 2217 audio_info->mode_count = edid_caps->audio_mode_count;
2218
2219 for (i = 0; i < audio_info->mode_count; ++i) {
2220 audio_info->modes[i].format_code =
2221 (enum audio_format_code)
2222 (edid_caps->audio_modes[i].format_code);
2223 audio_info->modes[i].channel_count =
2224 edid_caps->audio_modes[i].channel_count;
2225 audio_info->modes[i].sample_rates.all =
2226 edid_caps->audio_modes[i].sample_rate;
2227 audio_info->modes[i].sample_size =
2228 edid_caps->audio_modes[i].sample_size;
2229 }
2230 }
2231
2232 audio_info->flags.all = edid_caps->speaker_flags;
2233
2234 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2235 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2236 audio_info->video_latency = drm_connector->video_latency[0];
2237 audio_info->audio_latency = drm_connector->audio_latency[0];
2238 }
2239
2240 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2241
2242}
2243
2244static void copy_crtc_timing_for_drm_display_mode(
2245 const struct drm_display_mode *src_mode,
2246 struct drm_display_mode *dst_mode)
2247{
2248 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2249 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2250 dst_mode->crtc_clock = src_mode->crtc_clock;
2251 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2252 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2253 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2254 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2255 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2256 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2257 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2258 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2259 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2260 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2261 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2262}
2263
2264static void decide_crtc_timing_for_drm_display_mode(
2265 struct drm_display_mode *drm_mode,
2266 const struct drm_display_mode *native_mode,
2267 bool scale_enabled)
2268{
2269 if (scale_enabled) {
2270 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2271 } else if (native_mode->clock == drm_mode->clock &&
2272 native_mode->htotal == drm_mode->htotal &&
2273 native_mode->vtotal == drm_mode->vtotal) {
2274 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2275 } else {
2276 /* no scaling nor amdgpu inserted, no need to patch */
2277 }
2278}
2279
0971c40e 2280static struct dc_stream_state *create_stream_for_sink(
e7b07cee
HW		 2281 struct amdgpu_connector *aconnector,
2282 const struct drm_display_mode *drm_mode,
2283 const struct dm_connector_state *dm_state)
2284{
2285 struct drm_display_mode *preferred_mode = NULL;
2286 const struct drm_connector *drm_connector;
0971c40e 2287 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2288 struct drm_display_mode mode = *drm_mode;
2289 bool native_mode_found = false;
2290
b830ebc9 2291 if (aconnector == NULL) {
e7b07cee
HW		 2292 DRM_ERROR("aconnector is NULL!\n");
2293 goto drm_connector_null;
2294 }
2295
b830ebc9 2296 if (dm_state == NULL) {
e7b07cee
HW		 2297 DRM_ERROR("dm_state is NULL!\n");
2298 goto dm_state_null;
2299 }
4562236b 2300
e7b07cee
HW		 2301 drm_connector = &aconnector->base;
2302 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2303
b830ebc9 2304 if (stream == NULL) {
e7b07cee
HW		 2305 DRM_ERROR("Failed to create stream for sink!\n");
2306 goto stream_create_fail;
2307 }
2308
2309 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2310 /* Search for preferred mode */
2311 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2312 native_mode_found = true;
2313 break;
2314 }
2315 }
2316 if (!native_mode_found)
2317 preferred_mode = list_first_entry_or_null(
2318 &aconnector->base.modes,
2319 struct drm_display_mode,
2320 head);
2321
b830ebc9 2322 if (preferred_mode == NULL) {
e7b07cee
HW		 2323 /* This may not be an error, the use case is when we we have no
2324 * usermode calls to reset and set mode upon hotplug. In this
2325 * case, we call set mode ourselves to restore the previous mode
2326 * and the modelist may not be filled in in time.
2327 */
2328 DRM_INFO("No preferred mode found\n");
2329 } else {
2330 decide_crtc_timing_for_drm_display_mode(
2331 &mode, preferred_mode,
2332 dm_state->scaling != RMX_OFF);
2333 }
2334
2335 fill_stream_properties_from_drm_display_mode(stream,
2336 &mode, &aconnector->base);
2337 update_stream_scaling_settings(&mode, dm_state, stream);
2338
2339 fill_audio_info(
2340 &stream->audio_info,
2341 drm_connector,
2342 aconnector->dc_sink);
2343
2344stream_create_fail:
2345dm_state_null:
2346drm_connector_null:
2347 return stream;
2348}
2349
2350void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2351{
2352 drm_crtc_cleanup(crtc);
2353 kfree(crtc);
2354}
2355
2356static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2357 struct drm_crtc_state *state)
2358{
2359 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2360
2361 /* TODO Destroy dc_stream objects are stream object is flattened */
2362 if (cur->stream)
2363 dc_stream_release(cur->stream);
2364
2365
2366 __drm_atomic_helper_crtc_destroy_state(state);
2367
2368
2369 kfree(state);
2370}
2371
2372static void dm_crtc_reset_state(struct drm_crtc *crtc)
2373{
2374 struct dm_crtc_state *state;
2375
2376 if (crtc->state)
2377 dm_crtc_destroy_state(crtc, crtc->state);
2378
2379 state = kzalloc(sizeof(*state), GFP_KERNEL);
2380 if (WARN_ON(!state))
2381 return;
2382
2383 crtc->state = &state->base;
2384 crtc->state->crtc = crtc;
2385
2386}
2387
2388static struct drm_crtc_state *
2389dm_crtc_duplicate_state(struct drm_crtc *crtc)
2390{
2391 struct dm_crtc_state *state, *cur;
2392
2393 cur = to_dm_crtc_state(crtc->state);
2394
2395 if (WARN_ON(!crtc->state))
2396 return NULL;
2397
2398 state = dm_alloc(sizeof(*state));
2399
2400 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2401
2402 if (cur->stream) {
2403 state->stream = cur->stream;
2404 dc_stream_retain(state->stream);
2405 }
2406
2407 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2408
2409 return &state->base;
2410}
2411
2412/* Implemented only the options currently availible for the driver */
2413static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2414 .reset = dm_crtc_reset_state,
2415 .destroy = amdgpu_dm_crtc_destroy,
2416 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2417 .set_config = drm_atomic_helper_set_config,
2418 .page_flip = drm_atomic_helper_page_flip,
2419 .atomic_duplicate_state = dm_crtc_duplicate_state,
2420 .atomic_destroy_state = dm_crtc_destroy_state,
2421};
2422
2423static enum drm_connector_status
2424amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2425{
2426 bool connected;
2427 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2428
2429 /* Notes:
2430 * 1. This interface is NOT called in context of HPD irq.
2431 * 2. This interface *is called* in context of user-mode ioctl. Which
2432 * makes it a bad place for *any* MST-related activit. */
2433
2434 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2435 connected = (aconnector->dc_sink != NULL);
2436 else
2437 connected = (aconnector->base.force == DRM_FORCE_ON);
2438
2439 return (connected ? connector_status_connected :
2440 connector_status_disconnected);
2441}
2442
2443int amdgpu_dm_connector_atomic_set_property(
2444 struct drm_connector *connector,
2445 struct drm_connector_state *connector_state,
2446 struct drm_property *property,
2447 uint64_t val)
2448{
2449 struct drm_device *dev = connector->dev;
2450 struct amdgpu_device *adev = dev->dev_private;
2451 struct dm_connector_state *dm_old_state =
2452 to_dm_connector_state(connector->state);
2453 struct dm_connector_state *dm_new_state =
2454 to_dm_connector_state(connector_state);
2455
2456 int ret = -EINVAL;
2457
2458 if (property == dev->mode_config.scaling_mode_property) {
2459 enum amdgpu_rmx_type rmx_type;
2460
2461 switch (val) {
2462 case DRM_MODE_SCALE_CENTER:
2463 rmx_type = RMX_CENTER;
2464 break;
2465 case DRM_MODE_SCALE_ASPECT:
2466 rmx_type = RMX_ASPECT;
2467 break;
2468 case DRM_MODE_SCALE_FULLSCREEN:
2469 rmx_type = RMX_FULL;
2470 break;
2471 case DRM_MODE_SCALE_NONE:
2472 default:
2473 rmx_type = RMX_OFF;
2474 break;
2475 }
2476
2477 if (dm_old_state->scaling == rmx_type)
2478 return 0;
2479
2480 dm_new_state->scaling = rmx_type;
2481 ret = 0;
2482 } else if (property == adev->mode_info.underscan_hborder_property) {
2483 dm_new_state->underscan_hborder = val;
2484 ret = 0;
2485 } else if (property == adev->mode_info.underscan_vborder_property) {
2486 dm_new_state->underscan_vborder = val;
2487 ret = 0;
2488 } else if (property == adev->mode_info.underscan_property) {
2489 dm_new_state->underscan_enable = val;
2490 ret = 0;
2491 }
2492
2493 return ret;
2494}
2495
2496int amdgpu_dm_connector_atomic_get_property(
2497 struct drm_connector *connector,
2498 const struct drm_connector_state *state,
2499 struct drm_property *property,
2500 uint64_t *val)
2501{
2502 struct drm_device *dev = connector->dev;
2503 struct amdgpu_device *adev = dev->dev_private;
2504 struct dm_connector_state *dm_state =
2505 to_dm_connector_state(state);
2506 int ret = -EINVAL;
2507
2508 if (property == dev->mode_config.scaling_mode_property) {
2509 switch (dm_state->scaling) {
2510 case RMX_CENTER:
2511 *val = DRM_MODE_SCALE_CENTER;
2512 break;
2513 case RMX_ASPECT:
2514 *val = DRM_MODE_SCALE_ASPECT;
2515 break;
2516 case RMX_FULL:
2517 *val = DRM_MODE_SCALE_FULLSCREEN;
2518 break;
2519 case RMX_OFF:
2520 default:
2521 *val = DRM_MODE_SCALE_NONE;
2522 break;
2523 }
2524 ret = 0;
2525 } else if (property == adev->mode_info.underscan_hborder_property) {
2526 *val = dm_state->underscan_hborder;
2527 ret = 0;
2528 } else if (property == adev->mode_info.underscan_vborder_property) {
2529 *val = dm_state->underscan_vborder;
2530 ret = 0;
2531 } else if (property == adev->mode_info.underscan_property) {
2532 *val = dm_state->underscan_enable;
2533 ret = 0;
2534 }
2535 return ret;
2536}
2537
2538void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2539{
2540 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2541 const struct dc_link *link = aconnector->dc_link;
2542 struct amdgpu_device *adev = connector->dev->dev_private;
2543 struct amdgpu_display_manager *dm = &adev->dm;
2544#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2545 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2546
2547 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2548 amdgpu_dm_register_backlight_device(dm);
2549
2550 if (dm->backlight_dev) {
2551 backlight_device_unregister(dm->backlight_dev);
2552 dm->backlight_dev = NULL;
2553 }
2554
2555 }
2556#endif
2557 drm_connector_unregister(connector);
2558 drm_connector_cleanup(connector);
2559 kfree(connector);
2560}
2561
2562void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2563{
2564 struct dm_connector_state *state =
2565 to_dm_connector_state(connector->state);
2566
2567 kfree(state);
2568
2569 state = kzalloc(sizeof(*state), GFP_KERNEL);
2570
2571 if (state) {
2572 state->scaling = RMX_OFF;
2573 state->underscan_enable = false;
2574 state->underscan_hborder = 0;
2575 state->underscan_vborder = 0;
2576
2577 connector->state = &state->base;
2578 connector->state->connector = connector;
2579 }
2580}
2581
2582struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
2583 struct drm_connector *connector)
2584{
2585 struct dm_connector_state *state =
2586 to_dm_connector_state(connector->state);
2587
2588 struct dm_connector_state *new_state =
2589 kmemdup(state, sizeof(*state), GFP_KERNEL);
2590
2591 if (new_state) {
2592 __drm_atomic_helper_connector_duplicate_state(connector,
2593 &new_state->base);
2594 return &new_state->base;
2595 }
2596
2597 return NULL;
2598}
2599
2600static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2601 .reset = amdgpu_dm_connector_funcs_reset,
2602 .detect = amdgpu_dm_connector_detect,
2603 .fill_modes = drm_helper_probe_single_connector_modes,
2604 .destroy = amdgpu_dm_connector_destroy,
2605 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2606 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2607 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2608 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2609};
2610
2611static struct drm_encoder *best_encoder(struct drm_connector *connector)
2612{
2613 int enc_id = connector->encoder_ids[0];
2614 struct drm_mode_object *obj;
2615 struct drm_encoder *encoder;
2616
2617 DRM_DEBUG_KMS("Finding the best encoder\n");
2618
2619 /* pick the encoder ids */
2620 if (enc_id) {
2621 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
2622 if (!obj) {
2623 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2624 return NULL;
2625 }
2626 encoder = obj_to_encoder(obj);
2627 return encoder;
2628 }
2629 DRM_ERROR("No encoder id\n");
2630 return NULL;
2631}
2632
2633static int get_modes(struct drm_connector *connector)
2634{
2635 return amdgpu_dm_connector_get_modes(connector);
2636}
2637
2638static void create_eml_sink(struct amdgpu_connector *aconnector)
2639{
2640 struct dc_sink_init_data init_params = {
2641 .link = aconnector->dc_link,
2642 .sink_signal = SIGNAL_TYPE_VIRTUAL
2643 };
2644 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2645
2646 if (!aconnector->base.edid_blob_ptr ||
2647 !aconnector->base.edid_blob_ptr->data) {
2648 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2649 aconnector->base.name);
2650
2651 aconnector->base.force = DRM_FORCE_OFF;
2652 aconnector->base.override_edid = false;
2653 return;
2654 }
2655
2656 aconnector->edid = edid;
2657
2658 aconnector->dc_em_sink = dc_link_add_remote_sink(
2659 aconnector->dc_link,
2660 (uint8_t *)edid,
2661 (edid->extensions + 1) * EDID_LENGTH,
2662 &init_params);
2663
2664 if (aconnector->base.force
2665 == DRM_FORCE_ON)
2666 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2667 aconnector->dc_link->local_sink :
2668 aconnector->dc_em_sink;
2669}
2670
2671static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
2672{
2673 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2674
2675 /* In case of headless boot with force on for DP managed connector
2676 * Those settings have to be != 0 to get initial modeset
2677 */
2678 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2679 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2680 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2681 }
2682
2683
2684 aconnector->base.override_edid = true;
2685 create_eml_sink(aconnector);
2686}
2687
2688int amdgpu_dm_connector_mode_valid(
2689 struct drm_connector *connector,
2690 struct drm_display_mode *mode)
2691{
2692 int result = MODE_ERROR;
2693 struct dc_sink *dc_sink;
2694 struct amdgpu_device *adev = connector->dev->dev_private;
2695 /* TODO: Unhardcode stream count */
0971c40e 2696 struct dc_stream_state *stream;
e7b07cee
HW		 2697 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2698
2699 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2700 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2701 return result;
2702
2703 /* Only run this the first time mode_valid is called to initilialize
2704 * EDID mgmt
2705 */
2706 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2707 !aconnector->dc_em_sink)
2708 handle_edid_mgmt(aconnector);
2709
2710 dc_sink = to_amdgpu_connector(connector)->dc_sink;
2711
b830ebc9 2712 if (dc_sink == NULL) {
e7b07cee
HW		 2713 DRM_ERROR("dc_sink is NULL!\n");
2714 goto fail;
2715 }
2716
2717 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2718 if (stream == NULL) {
e7b07cee
HW		 2719 DRM_ERROR("Failed to create stream for sink!\n");
2720 goto fail;
2721 }
2722
2723 drm_mode_set_crtcinfo(mode, 0);
2724 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2725
2726 stream->src.width = mode->hdisplay;
2727 stream->src.height = mode->vdisplay;
2728 stream->dst = stream->src;
2729
2730 if (dc_validate_stream(adev->dm.dc, stream))
2731 result = MODE_OK;
2732
2733 dc_stream_release(stream);
2734
2735fail:
2736 /* TODO: error handling*/
2737 return result;
2738}
2739
2740static const struct drm_connector_helper_funcs
2741amdgpu_dm_connector_helper_funcs = {
2742 /*
b830ebc9
HW		 2743 * If hotplug a second bigger display in FB Con mode, bigger resolution
2744 * modes will be filtered by drm_mode_validate_size(), and those modes
2745 * is missing after user start lightdm. So we need to renew modes list.
2746 * in get_modes call back, not just return the modes count
2747 */
e7b07cee
HW		 2748 .get_modes = get_modes,
2749 .mode_valid = amdgpu_dm_connector_mode_valid,
2750 .best_encoder = best_encoder
2751};
2752
2753static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2754{
2755}
2756
2757static int dm_crtc_helper_atomic_check(
2758 struct drm_crtc *crtc,
2759 struct drm_crtc_state *state)
2760{
2761 struct amdgpu_device *adev = crtc->dev->dev_private;
2762 struct dc *dc = adev->dm.dc;
2763 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2764 int ret = -EINVAL;
2765
9b690ef3
BL		 2766 if (unlikely(!dm_crtc_state->stream &&
2767 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2768 WARN_ON(1);
2769 return ret;
2770 }
2771
2772 /* In some use cases, like reset, no stream is attached */
2773 if (!dm_crtc_state->stream)
2774 return 0;
2775
2776 if (dc_validate_stream(dc, dm_crtc_state->stream))
2777 return 0;
2778
2779 return ret;
2780}
2781
2782static bool dm_crtc_helper_mode_fixup(
2783 struct drm_crtc *crtc,
2784 const struct drm_display_mode *mode,
2785 struct drm_display_mode *adjusted_mode)
2786{
2787 return true;
2788}
2789
2790static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2791 .disable = dm_crtc_helper_disable,
2792 .atomic_check = dm_crtc_helper_atomic_check,
2793 .mode_fixup = dm_crtc_helper_mode_fixup
2794};
2795
2796static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2797{
2798
2799}
2800
2801static int dm_encoder_helper_atomic_check(
2802 struct drm_encoder *encoder,
2803 struct drm_crtc_state *crtc_state,
2804 struct drm_connector_state *conn_state)
2805{
2806 return 0;
2807}
2808
2809const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2810 .disable = dm_encoder_helper_disable,
2811 .atomic_check = dm_encoder_helper_atomic_check
2812};
2813
2814static void dm_drm_plane_reset(struct drm_plane *plane)
2815{
2816 struct dm_plane_state *amdgpu_state = NULL;
2817
2818 if (plane->state)
2819 plane->funcs->atomic_destroy_state(plane, plane->state);
2820
2821 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2822
2823 if (amdgpu_state) {
2824 plane->state = &amdgpu_state->base;
2825 plane->state->plane = plane;
2826 plane->state->rotation = DRM_MODE_ROTATE_0;
2827 } else
2828 WARN_ON(1);
2829}
2830
2831static struct drm_plane_state *
2832dm_drm_plane_duplicate_state(struct drm_plane *plane)
2833{
2834 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2835
2836 old_dm_plane_state = to_dm_plane_state(plane->state);
2837 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2838 if (!dm_plane_state)
2839 return NULL;
2840
2841 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2842
3be5262e
HW		 2843 if (old_dm_plane_state->dc_state) {
2844 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2845 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2846 }
2847
2848 return &dm_plane_state->base;
2849}
2850
2851void dm_drm_plane_destroy_state(struct drm_plane *plane,
2852 struct drm_plane_state *state)
2853{
2854 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2855
3be5262e
HW		 2856 if (dm_plane_state->dc_state)
2857 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2858
0627bbd3 2859 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2860}
2861
2862static const struct drm_plane_funcs dm_plane_funcs = {
2863 .update_plane = drm_atomic_helper_update_plane,
2864 .disable_plane = drm_atomic_helper_disable_plane,
2865 .destroy = drm_plane_cleanup,
2866 .reset = dm_drm_plane_reset,
2867 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2868 .atomic_destroy_state = dm_drm_plane_destroy_state,
2869};
2870
2871static int dm_plane_helper_prepare_fb(
2872 struct drm_plane *plane,
2873 struct drm_plane_state *new_state)
2874{
2875 struct amdgpu_framebuffer *afb;
2876 struct drm_gem_object *obj;
2877 struct amdgpu_bo *rbo;
2878 int r;
2879 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2880 unsigned int awidth;
2881
2882 dm_plane_state_old = to_dm_plane_state(plane->state);
2883 dm_plane_state_new = to_dm_plane_state(new_state);
2884
2885 if (!new_state->fb) {
2886 DRM_DEBUG_KMS("No FB bound\n");
2887 return 0;
2888 }
2889
2890 afb = to_amdgpu_framebuffer(new_state->fb);
2891
2892 obj = afb->obj;
2893 rbo = gem_to_amdgpu_bo(obj);
2894 r = amdgpu_bo_reserve(rbo, false);
2895 if (unlikely(r != 0))
2896 return r;
2897
2898 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2899
2900
2901 amdgpu_bo_unreserve(rbo);
2902
2903 if (unlikely(r != 0)) {
2904 DRM_ERROR("Failed to pin framebuffer\n");
2905 return r;
2906 }
2907
2908 amdgpu_bo_ref(rbo);
2909
3be5262e
HW		 2910 if (dm_plane_state_new->dc_state &&
2911 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2912 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2913
3be5262e
HW		 2914 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2915 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2916 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2917 } else {
2918 awidth = ALIGN(new_state->fb->width, 64);
3be5262e 2919 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2920 = lower_32_bits(afb->address);
3be5262e 2921 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 2922 = lower_32_bits(afb->address) +
2923 (awidth * new_state->fb->height);
2924 }
2925 }
2926
2927 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2928 * prepare and cleanup in drm_atomic_helper_prepare_planes
2929 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2930 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2931 * code touching fram buffers should be avoided for DC.
2932 */
2933 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2934 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2935
2936 acrtc->cursor_bo = obj;
2937 }
2938 return 0;
2939}
2940
2941static void dm_plane_helper_cleanup_fb(
2942 struct drm_plane *plane,
2943 struct drm_plane_state *old_state)
2944{
2945 struct amdgpu_bo *rbo;
2946 struct amdgpu_framebuffer *afb;
2947 int r;
2948
2949 if (!old_state->fb)
2950 return;
2951
2952 afb = to_amdgpu_framebuffer(old_state->fb);
2953 rbo = gem_to_amdgpu_bo(afb->obj);
2954 r = amdgpu_bo_reserve(rbo, false);
2955 if (unlikely(r)) {
2956 DRM_ERROR("failed to reserve rbo before unpin\n");
2957 return;
b830ebc9
HW		 2958 }
2959
2960 amdgpu_bo_unpin(rbo);
2961 amdgpu_bo_unreserve(rbo);
2962 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 2963}
2964
2965int dm_create_validation_set_for_connector(struct drm_connector *connector,
2966 struct drm_display_mode *mode, struct dc_validation_set *val_set)
2967{
2968 int result = MODE_ERROR;
2969 struct dc_sink *dc_sink =
2970 to_amdgpu_connector(connector)->dc_sink;
2971 /* TODO: Unhardcode stream count */
0971c40e 2972 struct dc_stream_state *stream;
e7b07cee
HW		 2973
2974 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2975 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2976 return result;
2977
b830ebc9 2978 if (dc_sink == NULL) {
e7b07cee
HW		 2979 DRM_ERROR("dc_sink is NULL!\n");
2980 return result;
2981 }
2982
2983 stream = dc_create_stream_for_sink(dc_sink);
2984
b830ebc9 2985 if (stream == NULL) {
e7b07cee
HW		 2986 DRM_ERROR("Failed to create stream for sink!\n");
2987 return result;
2988 }
2989
2990 drm_mode_set_crtcinfo(mode, 0);
2991
2992 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2993
2994 val_set->stream = stream;
2995
2996 stream->src.width = mode->hdisplay;
2997 stream->src.height = mode->vdisplay;
2998 stream->dst = stream->src;
2999
3000 return MODE_OK;
3001}
3002
cbd19488
AG		 3003int dm_plane_atomic_check(struct drm_plane *plane,
3004 struct drm_plane_state *state)
3005{
3006 struct amdgpu_device *adev = plane->dev->dev_private;
3007 struct dc *dc = adev->dm.dc;
3008 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3009
3be5262e 3010 if (!dm_plane_state->dc_state)
9a3329b1 3011 return 0;
cbd19488 3012
3be5262e 3013 if (dc_validate_plane(dc, dm_plane_state->dc_state))
cbd19488
AG		 3014 return 0;
3015
3016 return -EINVAL;
3017}
3018
e7b07cee
HW		 3019static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3020 .prepare_fb = dm_plane_helper_prepare_fb,
3021 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3022 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3023};
3024
3025/*
3026 * TODO: these are currently initialized to rgb formats only.
3027 * For future use cases we should either initialize them dynamically based on
3028 * plane capabilities, or initialize this array to all formats, so internal drm
3029 * check will succeed, and let DC to implement proper check
3030 */
3031static uint32_t rgb_formats[] = {
3032 DRM_FORMAT_RGB888,
3033 DRM_FORMAT_XRGB8888,
3034 DRM_FORMAT_ARGB8888,
3035 DRM_FORMAT_RGBA8888,
3036 DRM_FORMAT_XRGB2101010,
3037 DRM_FORMAT_XBGR2101010,
3038 DRM_FORMAT_ARGB2101010,
3039 DRM_FORMAT_ABGR2101010,
3040};
3041
3042static uint32_t yuv_formats[] = {
3043 DRM_FORMAT_NV12,
3044 DRM_FORMAT_NV21,
3045};
3046
3047static const u32 cursor_formats[] = {
3048 DRM_FORMAT_ARGB8888
3049};
3050
3051int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3052 struct amdgpu_plane *aplane,
3053 unsigned long possible_crtcs)
3054{
3055 int res = -EPERM;
3056
3057 switch (aplane->base.type) {
3058 case DRM_PLANE_TYPE_PRIMARY:
3059 aplane->base.format_default = true;
3060
3061 res = drm_universal_plane_init(
3062 dm->adev->ddev,
3063 &aplane->base,
3064 possible_crtcs,
3065 &dm_plane_funcs,
3066 rgb_formats,
3067 ARRAY_SIZE(rgb_formats),
3068 NULL, aplane->base.type, NULL);
3069 break;
3070 case DRM_PLANE_TYPE_OVERLAY:
3071 res = drm_universal_plane_init(
3072 dm->adev->ddev,
3073 &aplane->base,
3074 possible_crtcs,
3075 &dm_plane_funcs,
3076 yuv_formats,
3077 ARRAY_SIZE(yuv_formats),
3078 NULL, aplane->base.type, NULL);
3079 break;
3080 case DRM_PLANE_TYPE_CURSOR:
3081 res = drm_universal_plane_init(
3082 dm->adev->ddev,
3083 &aplane->base,
3084 possible_crtcs,
3085 &dm_plane_funcs,
3086 cursor_formats,
3087 ARRAY_SIZE(cursor_formats),
3088 NULL, aplane->base.type, NULL);
3089 break;
3090 }
3091
3092 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3093
3094 return res;
3095}
3096
3097int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3098 struct drm_plane *plane,
3099 uint32_t crtc_index)
3100{
3101 struct amdgpu_crtc *acrtc = NULL;
3102 struct amdgpu_plane *cursor_plane;
3103
3104 int res = -ENOMEM;
3105
3106 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3107 if (!cursor_plane)
3108 goto fail;
3109
3110 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3111 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3112
3113 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3114 if (!acrtc)
3115 goto fail;
3116
3117 res = drm_crtc_init_with_planes(
3118 dm->ddev,
3119 &acrtc->base,
3120 plane,
3121 &cursor_plane->base,
3122 &amdgpu_dm_crtc_funcs, NULL);
3123
3124 if (res)
3125 goto fail;
3126
3127 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3128
3129 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3130 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3131
3132 acrtc->crtc_id = crtc_index;
3133 acrtc->base.enabled = false;
3134
3135 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3136 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3137
3138 return 0;
3139
3140fail:
b830ebc9
HW		 3141 kfree(acrtc);
3142 kfree(cursor_plane);
e7b07cee
HW		 3143 acrtc->crtc_id = -1;
3144 return res;
3145}
3146
3147
3148static int to_drm_connector_type(enum signal_type st)
3149{
3150 switch (st) {
3151 case SIGNAL_TYPE_HDMI_TYPE_A:
3152 return DRM_MODE_CONNECTOR_HDMIA;
3153 case SIGNAL_TYPE_EDP:
3154 return DRM_MODE_CONNECTOR_eDP;
3155 case SIGNAL_TYPE_RGB:
3156 return DRM_MODE_CONNECTOR_VGA;
3157 case SIGNAL_TYPE_DISPLAY_PORT:
3158 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3159 return DRM_MODE_CONNECTOR_DisplayPort;
3160 case SIGNAL_TYPE_DVI_DUAL_LINK:
3161 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3162 return DRM_MODE_CONNECTOR_DVID;
3163 case SIGNAL_TYPE_VIRTUAL:
3164 return DRM_MODE_CONNECTOR_VIRTUAL;
3165
3166 default:
3167 return DRM_MODE_CONNECTOR_Unknown;
3168 }
3169}
3170
3171static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3172{
3173 const struct drm_connector_helper_funcs *helper =
3174 connector->helper_private;
3175 struct drm_encoder *encoder;
3176 struct amdgpu_encoder *amdgpu_encoder;
3177
3178 encoder = helper->best_encoder(connector);
3179
3180 if (encoder == NULL)
3181 return;
3182
3183 amdgpu_encoder = to_amdgpu_encoder(encoder);
3184
3185 amdgpu_encoder->native_mode.clock = 0;
3186
3187 if (!list_empty(&connector->probed_modes)) {
3188 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3189
e7b07cee 3190 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3191 &connector->probed_modes,
3192 head) {
3193 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3194 amdgpu_encoder->native_mode = *preferred_mode;
3195
e7b07cee
HW		 3196 break;
3197 }
3198
3199 }
3200}
3201
3202static struct drm_display_mode *amdgpu_dm_create_common_mode(
3203 struct drm_encoder *encoder, char *name,
3204 int hdisplay, int vdisplay)
3205{
3206 struct drm_device *dev = encoder->dev;
3207 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3208 struct drm_display_mode *mode = NULL;
3209 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3210
3211 mode = drm_mode_duplicate(dev, native_mode);
3212
b830ebc9 3213 if (mode == NULL)
e7b07cee
HW		 3214 return NULL;
3215
3216 mode->hdisplay = hdisplay;
3217 mode->vdisplay = vdisplay;
3218 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3219 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3220
3221 return mode;
3222
3223}
3224
3225static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3226 struct drm_connector *connector)
3227{
3228 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3229 struct drm_display_mode *mode = NULL;
3230 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3231 struct amdgpu_connector *amdgpu_connector =
3232 to_amdgpu_connector(connector);
3233 int i;
3234 int n;
3235 struct mode_size {
3236 char name[DRM_DISPLAY_MODE_LEN];
3237 int w;
3238 int h;
b830ebc9 3239 } common_modes[] = {
e7b07cee
HW		 3240 { "640x480", 640, 480},
3241 { "800x600", 800, 600},
3242 { "1024x768", 1024, 768},
3243 { "1280x720", 1280, 720},
3244 { "1280x800", 1280, 800},
3245 {"1280x1024", 1280, 1024},
3246 { "1440x900", 1440, 900},
3247 {"1680x1050", 1680, 1050},
3248 {"1600x1200", 1600, 1200},
3249 {"1920x1080", 1920, 1080},
3250 {"1920x1200", 1920, 1200}
3251 };
3252
b830ebc9 3253 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3254
3255 for (i = 0; i < n; i++) {
3256 struct drm_display_mode *curmode = NULL;
3257 bool mode_existed = false;
3258
3259 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3260 common_modes[i].h > native_mode->vdisplay ||
3261 (common_modes[i].w == native_mode->hdisplay &&
3262 common_modes[i].h == native_mode->vdisplay))
3263 continue;
e7b07cee
HW		 3264
3265 list_for_each_entry(curmode, &connector->probed_modes, head) {
3266 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3267 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3268 mode_existed = true;
3269 break;
3270 }
3271 }
3272
3273 if (mode_existed)
3274 continue;
3275
3276 mode = amdgpu_dm_create_common_mode(encoder,
3277 common_modes[i].name, common_modes[i].w,
3278 common_modes[i].h);
3279 drm_mode_probed_add(connector, mode);
3280 amdgpu_connector->num_modes++;
3281 }
3282}
3283
3284static void amdgpu_dm_connector_ddc_get_modes(
3285 struct drm_connector *connector,
3286 struct edid *edid)
3287{
3288 struct amdgpu_connector *amdgpu_connector =
3289 to_amdgpu_connector(connector);
3290
3291 if (edid) {
3292 /* empty probed_modes */
3293 INIT_LIST_HEAD(&connector->probed_modes);
3294 amdgpu_connector->num_modes =
3295 drm_add_edid_modes(connector, edid);
3296
3297 drm_edid_to_eld(connector, edid);
3298
3299 amdgpu_dm_get_native_mode(connector);
3300 } else
3301 amdgpu_connector->num_modes = 0;
3302}
3303
3304int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3305{
3306 const struct drm_connector_helper_funcs *helper =
3307 connector->helper_private;
3308 struct amdgpu_connector *amdgpu_connector =
3309 to_amdgpu_connector(connector);
3310 struct drm_encoder *encoder;
3311 struct edid *edid = amdgpu_connector->edid;
3312
3313 encoder = helper->best_encoder(connector);
3314
3315 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3316 amdgpu_dm_connector_add_common_modes(encoder, connector);
3317 return amdgpu_connector->num_modes;
3318}
3319
3320void amdgpu_dm_connector_init_helper(
3321 struct amdgpu_display_manager *dm,
3322 struct amdgpu_connector *aconnector,
3323 int connector_type,
3324 struct dc_link *link,
3325 int link_index)
3326{
3327 struct amdgpu_device *adev = dm->ddev->dev_private;
3328
3329 aconnector->connector_id = link_index;
3330 aconnector->dc_link = link;
3331 aconnector->base.interlace_allowed = false;
3332 aconnector->base.doublescan_allowed = false;
3333 aconnector->base.stereo_allowed = false;
3334 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3335 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3336
3337 mutex_init(&aconnector->hpd_lock);
3338
b830ebc9
HW		 3339 /* configure support HPD hot plug connector_>polled default value is 0
3340 * which means HPD hot plug not supported
3341 */
e7b07cee
HW		 3342 switch (connector_type) {
3343 case DRM_MODE_CONNECTOR_HDMIA:
3344 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3345 break;
3346 case DRM_MODE_CONNECTOR_DisplayPort:
3347 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3348 break;
3349 case DRM_MODE_CONNECTOR_DVID:
3350 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3351 break;
3352 default:
3353 break;
3354 }
3355
3356 drm_object_attach_property(&aconnector->base.base,
3357 dm->ddev->mode_config.scaling_mode_property,
3358 DRM_MODE_SCALE_NONE);
3359
3360 drm_object_attach_property(&aconnector->base.base,
3361 adev->mode_info.underscan_property,
3362 UNDERSCAN_OFF);
3363 drm_object_attach_property(&aconnector->base.base,
3364 adev->mode_info.underscan_hborder_property,
3365 0);
3366 drm_object_attach_property(&aconnector->base.base,
3367 adev->mode_info.underscan_vborder_property,
3368 0);
3369
3370}
3371
3372int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3373 struct i2c_msg *msgs, int num)
3374{
3375 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3376 struct ddc_service *ddc_service = i2c->ddc_service;
3377 struct i2c_command cmd;
3378 int i;
3379 int result = -EIO;
3380
b830ebc9 3381 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3382
3383 if (!cmd.payloads)
3384 return result;
3385
3386 cmd.number_of_payloads = num;
3387 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3388 cmd.speed = 100;
3389
3390 for (i = 0; i < num; i++) {
3391 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3392 cmd.payloads[i].address = msgs[i].addr;
3393 cmd.payloads[i].length = msgs[i].len;
3394 cmd.payloads[i].data = msgs[i].buf;
3395 }
3396
3397 if (dal_i2caux_submit_i2c_command(
3398 ddc_service->ctx->i2caux,
3399 ddc_service->ddc_pin,
3400 &cmd))
3401 result = num;
3402
3403 kfree(cmd.payloads);
3404 return result;
3405}
3406
3407u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3408{
3409 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3410}
3411
3412static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3413 .master_xfer = amdgpu_dm_i2c_xfer,
3414 .functionality = amdgpu_dm_i2c_func,
3415};
3416
3417static struct amdgpu_i2c_adapter *create_i2c(
3418 struct ddc_service *ddc_service,
3419 int link_index,
3420 int *res)
3421{
3422 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3423 struct amdgpu_i2c_adapter *i2c;
3424
b830ebc9 3425 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
e7b07cee
HW		 3426 i2c->base.owner = THIS_MODULE;
3427 i2c->base.class = I2C_CLASS_DDC;
3428 i2c->base.dev.parent = &adev->pdev->dev;
3429 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3430 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3431 i2c_set_adapdata(&i2c->base, i2c);
3432 i2c->ddc_service = ddc_service;
3433
3434 return i2c;
3435}
3436
3437/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3438 * dc_link which will be represented by this aconnector.
3439 */
e7b07cee
HW		 3440int amdgpu_dm_connector_init(
3441 struct amdgpu_display_manager *dm,
3442 struct amdgpu_connector *aconnector,
3443 uint32_t link_index,
3444 struct amdgpu_encoder *aencoder)
3445{
3446 int res = 0;
3447 int connector_type;
3448 struct dc *dc = dm->dc;
3449 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3450 struct amdgpu_i2c_adapter *i2c;
3451 ((struct dc_link *)link)->priv = aconnector;
3452
3453 DRM_DEBUG_KMS("%s()\n", __func__);
3454
3455 i2c = create_i2c(link->ddc, link->link_index, &res);
3456 aconnector->i2c = i2c;
3457 res = i2c_add_adapter(&i2c->base);
3458
3459 if (res) {
3460 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3461 goto out_free;
3462 }
3463
3464 connector_type = to_drm_connector_type(link->connector_signal);
3465
3466 res = drm_connector_init(
3467 dm->ddev,
3468 &aconnector->base,
3469 &amdgpu_dm_connector_funcs,
3470 connector_type);
3471
3472 if (res) {
3473 DRM_ERROR("connector_init failed\n");
3474 aconnector->connector_id = -1;
3475 goto out_free;
3476 }
3477
3478 drm_connector_helper_add(
3479 &aconnector->base,
3480 &amdgpu_dm_connector_helper_funcs);
3481
3482 amdgpu_dm_connector_init_helper(
3483 dm,
3484 aconnector,
3485 connector_type,
3486 link,
3487 link_index);
3488
3489 drm_mode_connector_attach_encoder(
3490 &aconnector->base, &aencoder->base);
3491
3492 drm_connector_register(&aconnector->base);
3493
3494 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3495 || connector_type == DRM_MODE_CONNECTOR_eDP)
3496 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3497
3498#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3499 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3500
3501 /* NOTE: this currently will create backlight device even if a panel
3502 * is not connected to the eDP/LVDS connector.
3503 *
3504 * This is less than ideal but we don't have sink information at this
3505 * stage since detection happens after. We can't do detection earlier
3506 * since MST detection needs connectors to be created first.
3507 */
3508 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3509 /* Event if registration failed, we should continue with
3510 * DM initialization because not having a backlight control
b830ebc9
HW		 3511 * is better then a black screen.
3512 */
e7b07cee
HW		 3513 amdgpu_dm_register_backlight_device(dm);
3514
3515 if (dm->backlight_dev)
3516 dm->backlight_link = link;
3517 }
3518#endif
3519
3520out_free:
3521 if (res) {
3522 kfree(i2c);
3523 aconnector->i2c = NULL;
3524 }
3525 return res;
3526}
3527
3528int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3529{
3530 switch (adev->mode_info.num_crtc) {
3531 case 1:
3532 return 0x1;
3533 case 2:
3534 return 0x3;
3535 case 3:
3536 return 0x7;
3537 case 4:
3538 return 0xf;
3539 case 5:
3540 return 0x1f;
3541 case 6:
3542 default:
3543 return 0x3f;
3544 }
3545}
3546
3547int amdgpu_dm_encoder_init(
3548 struct drm_device *dev,
3549 struct amdgpu_encoder *aencoder,
3550 uint32_t link_index)
3551{
3552 struct amdgpu_device *adev = dev->dev_private;
3553
3554 int res = drm_encoder_init(dev,
3555 &aencoder->base,
3556 &amdgpu_dm_encoder_funcs,
3557 DRM_MODE_ENCODER_TMDS,
3558 NULL);
3559
3560 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3561
3562 if (!res)
3563 aencoder->encoder_id = link_index;
3564 else
3565 aencoder->encoder_id = -1;
3566
3567 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3568
3569 return res;
3570}
3571
3572static void manage_dm_interrupts(
3573 struct amdgpu_device *adev,
3574 struct amdgpu_crtc *acrtc,
3575 bool enable)
3576{
3577 /*
3578 * this is not correct translation but will work as soon as VBLANK
3579 * constant is the same as PFLIP
3580 */
3581 int irq_type =
3582 amdgpu_crtc_idx_to_irq_type(
3583 adev,
3584 acrtc->crtc_id);
3585
3586 if (enable) {
3587 drm_crtc_vblank_on(&acrtc->base);
3588 amdgpu_irq_get(
3589 adev,
3590 &adev->pageflip_irq,
3591 irq_type);
3592 } else {
3593
3594 amdgpu_irq_put(
3595 adev,
3596 &adev->pageflip_irq,
3597 irq_type);
3598 drm_crtc_vblank_off(&acrtc->base);
3599 }
3600}
3601
3602static bool is_scaling_state_different(
3603 const struct dm_connector_state *dm_state,
3604 const struct dm_connector_state *old_dm_state)
3605{
3606 if (dm_state->scaling != old_dm_state->scaling)
3607 return true;
3608 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3609 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3610 return true;
3611 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3612 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3613 return true;
b830ebc9
HW		 3614 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3615 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3616 return true;
e7b07cee
HW		 3617 return false;
3618}
3619
3620static void remove_stream(
3621 struct amdgpu_device *adev,
3622 struct amdgpu_crtc *acrtc,
0971c40e 3623 struct dc_stream_state *stream)
e7b07cee
HW		 3624{
3625 /* this is the update mode case */
3626 if (adev->dm.freesync_module)
3627 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3628
3629 acrtc->otg_inst = -1;
3630 acrtc->enabled = false;
3631}
3632
2a8f6ccb
HW		 3633int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3634 struct dc_cursor_position *position)
3635{
3636 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3637 int x, y;
3638 int xorigin = 0, yorigin = 0;
3639
3640 if (!crtc || !plane->state->fb) {
3641 position->enable = false;
3642 position->x = 0;
3643 position->y = 0;
3644 return 0;
3645 }
3646
3647 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3648 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3649 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3650 __func__,
3651 plane->state->crtc_w,
3652 plane->state->crtc_h);
3653 return -EINVAL;
3654 }
3655
3656 x = plane->state->crtc_x;
3657 y = plane->state->crtc_y;
3658 /* avivo cursor are offset into the total surface */
3659 x += crtc->primary->state->src_x >> 16;
3660 y += crtc->primary->state->src_y >> 16;
3661 if (x < 0) {
3662 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3663 x = 0;
3664 }
3665 if (y < 0) {
3666 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3667 y = 0;
3668 }
3669 position->enable = true;
3670 position->x = x;
3671 position->y = y;
3672 position->x_hotspot = xorigin;
3673 position->y_hotspot = yorigin;
3674
3675 return 0;
3676}
3677
e7b07cee
HW		 3678static void handle_cursor_update(
3679 struct drm_plane *plane,
3680 struct drm_plane_state *old_plane_state)
3681{
2a8f6ccb
HW		 3682 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3683 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3684 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3685 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3686 uint64_t address = afb ? afb->address : 0;
3687 struct dc_cursor_position position;
3688 struct dc_cursor_attributes attributes;
3689 int ret;
3690
e7b07cee
HW		 3691 if (!plane->state->fb && !old_plane_state->fb)
3692 return;
3693
2a8f6ccb
HW		 3694 DRM_DEBUG_KMS("%s: crtc_id=%d with size %d to %d\n",
3695 __func__,
3696 amdgpu_crtc->crtc_id,
3697 plane->state->crtc_w,
3698 plane->state->crtc_h);
3699
3700 ret = get_cursor_position(plane, crtc, &position);
3701 if (ret)
3702 return;
3703
3704 if (!position.enable) {
3705 /* turn off cursor */
3706 if (crtc_state && crtc_state->stream)
3707 dc_stream_set_cursor_position(crtc_state->stream,
3708 &position);
3709 return;
e7b07cee 3710 }
e7b07cee 3711
2a8f6ccb
HW		 3712 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3713 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3714
3715 attributes.address.high_part = upper_32_bits(address);
3716 attributes.address.low_part = lower_32_bits(address);
3717 attributes.width = plane->state->crtc_w;
3718 attributes.height = plane->state->crtc_h;
3719 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3720 attributes.rotation_angle = 0;
3721 attributes.attribute_flags.value = 0;
3722
3723 attributes.pitch = attributes.width;
3724
3725 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3726 &attributes))
3727 DRM_ERROR("DC failed to set cursor attributes\n");
3728
3729 if (crtc_state->stream)
3730 if (!dc_stream_set_cursor_position(crtc_state->stream,
3731 &position))
3732 DRM_ERROR("DC failed to set cursor position\n");
3733}
e7b07cee
HW		 3734
3735static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3736{
3737
3738 assert_spin_locked(&acrtc->base.dev->event_lock);
3739 WARN_ON(acrtc->event);
3740
3741 acrtc->event = acrtc->base.state->event;
3742
3743 /* Set the flip status */
3744 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3745
3746 /* Mark this event as consumed */
3747 acrtc->base.state->event = NULL;
3748
3749 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3750 acrtc->crtc_id);
3751}
3752
3753/*
3754 * Executes flip
3755 *
3756 * Waits on all BO's fences and for proper vblank count
3757 */
3758static void amdgpu_dm_do_flip(
3759 struct drm_crtc *crtc,
3760 struct drm_framebuffer *fb,
3761 uint32_t target)
3762{
3763 unsigned long flags;
3764 uint32_t target_vblank;
3765 int r, vpos, hpos;
3766 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3767 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3768 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3769 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3770 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3771 struct dc_flip_addrs addr = { {0} };
3be5262e 3772 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3773 struct dc_surface_update surface_updates[1] = { {0} };
3774 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3775
3776
3777 /* Prepare wait for target vblank early - before the fence-waits */
3778 target_vblank = target - drm_crtc_vblank_count(crtc) +
3779 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3780
b830ebc9 3781 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3782 * explicitly on fences instead
3783 * and in general should be called for
3784 * blocking commit to as per framework helpers
b830ebc9 3785 */
e7b07cee
HW		 3786 r = amdgpu_bo_reserve(abo, true);
3787 if (unlikely(r != 0)) {
3788 DRM_ERROR("failed to reserve buffer before flip\n");
3789 WARN_ON(1);
3790 }
3791
3792 /* Wait for all fences on this FB */
3793 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3794 MAX_SCHEDULE_TIMEOUT) < 0);
3795
3796 amdgpu_bo_unreserve(abo);
3797
3798 /* Wait until we're out of the vertical blank period before the one
3799 * targeted by the flip
3800 */
3801 while ((acrtc->enabled &&
3802 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3803 &vpos, &hpos, NULL, NULL,
3804 &crtc->hwmode)
3805 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3806 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3807 (int)(target_vblank -
3808 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3809 usleep_range(1000, 1100);
3810 }
3811
3812 /* Flip */
3813 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3814 /* update crtc fb */
3815 crtc->primary->fb = fb;
3816
3817 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3818 WARN_ON(!acrtc_state->stream);
3819
3820 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3821 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3822 addr.flip_immediate = async_flip;
3823
3824
3825 if (acrtc->base.state->event)
3826 prepare_flip_isr(acrtc);
3827
3be5262e 3828 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3829 surface_updates->flip_addr = &addr;
3830
3831
3be5262e 3832 dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);
e7b07cee
HW		 3833
3834 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3835 __func__,
3836 addr.address.grph.addr.high_part,
3837 addr.address.grph.addr.low_part);
3838
3839
3840 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3841}
3842
3be5262e 3843static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
e7b07cee
HW		 3844 struct drm_device *dev,
3845 struct amdgpu_display_manager *dm,
3846 struct drm_crtc *pcrtc,
3847 bool *wait_for_vblank)
3848{
3849 uint32_t i;
3850 struct drm_plane *plane;
3851 struct drm_plane_state *old_plane_state;
0971c40e 3852 struct dc_stream_state *dc_stream_attach;
3be5262e 3853 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee
HW		 3854 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
3855 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);
3856 int planes_count = 0;
3857 unsigned long flags;
3858
3859 /* update planes when needed */
3860 for_each_plane_in_state(state, plane, old_plane_state, i) {
3861 struct drm_plane_state *plane_state = plane->state;
3862 struct drm_crtc *crtc = plane_state->crtc;
3863 struct drm_framebuffer *fb = plane_state->fb;
3864 bool pflip_needed;
3865 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
3866
3867 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3868 handle_cursor_update(plane, old_plane_state);
3869 continue;
3870 }
3871
62f55537 3872 if (!fb || !crtc || pcrtc != crtc || !crtc->state->active)
e7b07cee
HW		 3873 continue;
3874
3875 pflip_needed = !state->allow_modeset;
3876
3877 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3878 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3879 DRM_ERROR("%s: acrtc %d, already busy\n",
3880 __func__,
3881 acrtc_attach->crtc_id);
e7b07cee 3882 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
b830ebc9 3883 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3884 WARN_ON(1);
3885 }
3886 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3887
3888 if (!pflip_needed) {
3be5262e 3889 WARN_ON(!dm_plane_state->dc_state);
e7b07cee 3890
3be5262e 3891 plane_states_constructed[planes_count] = dm_plane_state->dc_state;
e7b07cee
HW		 3892
3893 dc_stream_attach = acrtc_state->stream;
3894 planes_count++;
3895
3896 } else if (crtc->state->planes_changed) {
3897 /* Assume even ONE crtc with immediate flip means
3898 * entire can't wait for VBLANK
3899 * TODO Check if it's correct
3900 */
3901 *wait_for_vblank =
aac6a07e 3902 pcrtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3903 false : true;
3904
3905 /* TODO: Needs rework for multiplane flip */
3906 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3907 drm_crtc_vblank_get(crtc);
3908
3909 amdgpu_dm_do_flip(
3910 crtc,
3911 fb,
3912 drm_crtc_vblank_count(crtc) + *wait_for_vblank);
e7b07cee
HW		 3913 }
3914
3915 }
3916
3917 if (planes_count) {
3918 unsigned long flags;
3919
3920 if (pcrtc->state->event) {
3921
3922 drm_crtc_vblank_get(pcrtc);
3923
3924 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3925 prepare_flip_isr(acrtc_attach);
3926 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3927 }
3928
3be5262e
HW		 3929 if (false == dc_commit_planes_to_stream(dm->dc,
3930 plane_states_constructed,
3931 planes_count,
3932 dc_stream_attach))
3933 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3934 } else {
3935 /*TODO BUG Here should go disable planes on CRTC. */
3936 }
3937}
3938
3939
3940int amdgpu_dm_atomic_commit(
3941 struct drm_device *dev,
3942 struct drm_atomic_state *state,
3943 bool nonblock)
3944{
3945 struct drm_crtc *crtc;
3946 struct drm_crtc_state *new_state;
3947 struct amdgpu_device *adev = dev->dev_private;
3948 int i;
3949
3950 /*
3951 * We evade vblanks and pflips on crtc that
3952 * should be changed. We do it here to flush & disable
3953 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3954 * it will update crtc->dm_crtc_state->stream pointer which is used in
3955 * the ISRs.
3956 */
3957 for_each_crtc_in_state(state, crtc, new_state, i) {
3958 struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state);
3959 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3960
3961 if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream)
3962 manage_dm_interrupts(adev, acrtc, false);
3963 }
3964
3965 return drm_atomic_helper_commit(dev, state, nonblock);
3966
3967 /*TODO Handle EINTR, reenable IRQ*/
3968}
3969
3970void amdgpu_dm_atomic_commit_tail(
3971 struct drm_atomic_state *state)
3972{
3973 struct drm_device *dev = state->dev;
3974 struct amdgpu_device *adev = dev->dev_private;
3975 struct amdgpu_display_manager *dm = &adev->dm;
3976 struct dm_atomic_state *dm_state;
3977 uint32_t i, j;
3978 uint32_t new_crtcs_count = 0;
3979 struct drm_crtc *crtc, *pcrtc;
3980 struct drm_crtc_state *old_crtc_state;
3981 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 3982 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 3983 unsigned long flags;
3984 bool wait_for_vblank = true;
3985 struct drm_connector *connector;
3986 struct drm_connector_state *old_conn_state;
3987 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
3988
3989 drm_atomic_helper_update_legacy_modeset_state(dev, state);
3990
3991 dm_state = to_dm_atomic_state(state);
3992
3993 /* update changed items */
3994 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
3995 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3996 struct drm_crtc_state *new_state = crtc->state;
b830ebc9 3997
e7b07cee
HW		 3998 new_acrtc_state = to_dm_crtc_state(new_state);
3999 old_acrtc_state = to_dm_crtc_state(old_crtc_state);
4000
4001 DRM_DEBUG_KMS(
4002 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4003 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4004 "connectors_changed:%d\n",
4005 acrtc->crtc_id,
4006 new_state->enable,
4007 new_state->active,
4008 new_state->planes_changed,
4009 new_state->mode_changed,
4010 new_state->active_changed,
4011 new_state->connectors_changed);
4012
4013 /* handles headless hotplug case, updating new_state and
4014 * aconnector as needed
4015 */
4016
9b690ef3 4017 if (modeset_required(new_state, new_acrtc_state->stream, old_acrtc_state->stream)) {
e7b07cee
HW		 4018
4019 DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4020
4021 if (!new_acrtc_state->stream) {
4022 /*
b830ebc9
HW		 4023 * this could happen because of issues with
4024 * userspace notifications delivery.
4025 * In this case userspace tries to set mode on
4026 * display which is disconnect in fact.
4027 * dc_sink in NULL in this case on aconnector.
4028 * We expect reset mode will come soon.
4029 *
4030 * This can also happen when unplug is done
4031 * during resume sequence ended
4032 *
4033 * In this case, we want to pretend we still
4034 * have a sink to keep the pipe running so that
4035 * hw state is consistent with the sw state
4036 */
e7b07cee
HW		 4037 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4038 __func__, acrtc->base.base.id);
4039 continue;
4040 }
4041
4042
4043 if (old_acrtc_state->stream)
4044 remove_stream(adev, acrtc, old_acrtc_state->stream);
4045
4046
4047 /*
4048 * this loop saves set mode crtcs
4049 * we needed to enable vblanks once all
4050 * resources acquired in dc after dc_commit_streams
4051 */
4052
4053 /*TODO move all this into dm_crtc_state, get rid of
4054 * new_crtcs array and use old and new atomic states
4055 * instead
4056 */
4057 new_crtcs[new_crtcs_count] = acrtc;
4058 new_crtcs_count++;
4059
4060 acrtc->enabled = true;
4061 acrtc->hw_mode = crtc->state->mode;
4062 crtc->hwmode = crtc->state->mode;
4063 } else if (modereset_required(new_state)) {
4064 DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4065
4066 /* i.e. reset mode */
4067 if (old_acrtc_state->stream)
4068 remove_stream(adev, acrtc, old_acrtc_state->stream);
4069 }
4070 } /* for_each_crtc_in_state() */
4071
4072 /*
4073 * Add streams after required streams from new and replaced streams
4074 * are removed from freesync module
4075 */
4076 if (adev->dm.freesync_module) {
4077 for (i = 0; i < new_crtcs_count; i++) {
4078 struct amdgpu_connector *aconnector = NULL;
b830ebc9 4079
e7b07cee
HW		 4080 new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state);
4081
4082 new_stream = new_acrtc_state->stream;
4083 aconnector =
4084 amdgpu_dm_find_first_crct_matching_connector(
4085 state,
4086 &new_crtcs[i]->base,
4087 false);
4088 if (!aconnector) {
b830ebc9
HW		 4089 DRM_INFO("Atomic commit: Failed to find connector for acrtc id:%d "
4090 "skipping freesync init\n",
4091 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4092 continue;
4093 }
4094
4095 mod_freesync_add_stream(adev->dm.freesync_module,
4096 new_stream, &aconnector->caps);
4097 }
4098 }
4099
4100 if (dm_state->context)
608ac7bb 4101 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
e7b07cee
HW		 4102
4103
4104 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4105 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4106
e7b07cee
HW		 4107 new_acrtc_state = to_dm_crtc_state(crtc->state);
4108
4109 if (new_acrtc_state->stream != NULL) {
4110 const struct dc_stream_status *status =
4111 dc_stream_get_status(new_acrtc_state->stream);
4112
4113 if (!status)
4114 DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc);
4115 else
4116 acrtc->otg_inst = status->primary_otg_inst;
4117 }
4118 }
4119
4120 /* Handle scaling and undersacn changes*/
4121 for_each_connector_in_state(state, connector, old_conn_state, i) {
4122 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4123 struct dm_connector_state *con_new_state =
4124 to_dm_connector_state(aconnector->base.state);
4125 struct dm_connector_state *con_old_state =
4126 to_dm_connector_state(old_conn_state);
4127 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
4128 struct dc_stream_status *status = NULL;
4129
4130 /* Skip any modesets/resets */
4131 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
4132 continue;
4133
4134 /* Skip any thing not scale or underscan changes */
4135 if (!is_scaling_state_different(con_new_state, con_old_state))
4136 continue;
4137
4138 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4139
4140 update_stream_scaling_settings(&con_new_state->base.crtc->mode,
0971c40e 4141 con_new_state, (struct dc_stream_state *)new_acrtc_state->stream);
e7b07cee
HW		 4142
4143 status = dc_stream_get_status(new_acrtc_state->stream);
4144 WARN_ON(!status);
3be5262e 4145 WARN_ON(!status->plane_count);
e7b07cee
HW		 4146
4147 if (!new_acrtc_state->stream)
4148 continue;
4149
4150 /*TODO How it works with MPO ?*/
3be5262e 4151 if (!dc_commit_planes_to_stream(
e7b07cee 4152 dm->dc,
3be5262e
HW		 4153 status->plane_states,
4154 status->plane_count,
e7b07cee
HW		 4155 new_acrtc_state->stream))
4156 dm_error("%s: Failed to update stream scaling!\n", __func__);
4157 }
4158
4159 for (i = 0; i < new_crtcs_count; i++) {
4160 /*
4161 * loop to enable interrupts on newly arrived crtc
4162 */
4163 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4164
e7b07cee
HW		 4165 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4166
4167 if (adev->dm.freesync_module)
4168 mod_freesync_notify_mode_change(
4169 adev->dm.freesync_module, &new_acrtc_state->stream, 1);
4170
4171 manage_dm_interrupts(adev, acrtc, true);
4172 }
4173
4174 /* update planes when needed per crtc*/
4175 for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) {
4176 new_acrtc_state = to_dm_crtc_state(pcrtc->state);
4177
4178 if (new_acrtc_state->stream)
3be5262e 4179 amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank);
e7b07cee
HW		 4180 }
4181
4182
4183 /*
4184 * send vblank event on all events not handled in flip and
4185 * mark consumed event for drm_atomic_helper_commit_hw_done
4186 */
4187 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4188 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
4189 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4190
4191 if (acrtc->base.state->event)
4192 drm_send_event_locked(dev, &crtc->state->event->base);
4193
4194 acrtc->base.state->event = NULL;
4195 }
4196 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4197
4198 /* Signal HW programming completion */
4199 drm_atomic_helper_commit_hw_done(state);
4200
4201 if (wait_for_vblank)
4202 drm_atomic_helper_wait_for_vblanks(dev, state);
4203
4204 drm_atomic_helper_cleanup_planes(dev, state);
4205}
4206
4207
4208static int dm_force_atomic_commit(struct drm_connector *connector)
4209{
4210 int ret = 0;
4211 struct drm_device *ddev = connector->dev;
4212 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4213 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4214 struct drm_plane *plane = disconnected_acrtc->base.primary;
4215 struct drm_connector_state *conn_state;
4216 struct drm_crtc_state *crtc_state;
4217 struct drm_plane_state *plane_state;
4218
4219 if (!state)
4220 return -ENOMEM;
4221
4222 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4223
4224 /* Construct an atomic state to restore previous display setting */
4225
4226 /*
4227 * Attach connectors to drm_atomic_state
4228 */
4229 conn_state = drm_atomic_get_connector_state(state, connector);
4230
4231 ret = PTR_ERR_OR_ZERO(conn_state);
4232 if (ret)
4233 goto err;
4234
4235 /* Attach crtc to drm_atomic_state*/
4236 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4237
4238 ret = PTR_ERR_OR_ZERO(crtc_state);
4239 if (ret)
4240 goto err;
4241
4242 /* force a restore */
4243 crtc_state->mode_changed = true;
4244
4245 /* Attach plane to drm_atomic_state */
4246 plane_state = drm_atomic_get_plane_state(state, plane);
4247
4248 ret = PTR_ERR_OR_ZERO(plane_state);
4249 if (ret)
4250 goto err;
4251
4252
4253 /* Call commit internally with the state we just constructed */
4254 ret = drm_atomic_commit(state);
4255 if (!ret)
4256 return 0;
4257
4258err:
4259 DRM_ERROR("Restoring old state failed with %i\n", ret);
4260 drm_atomic_state_put(state);
4261
4262 return ret;
4263}
4264
4265/*
4266 * This functions handle all cases when set mode does not come upon hotplug.
4267 * This include when the same display is unplugged then plugged back into the
4268 * same port and when we are running without usermode desktop manager supprot
4269 */
4270void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
4271{
4272 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4273 struct amdgpu_crtc *disconnected_acrtc;
4274 struct dm_crtc_state *acrtc_state;
4275
4276 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4277 return;
4278
4279 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4280 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4281
4282 if (!disconnected_acrtc || !acrtc_state->stream)
4283 return;
4284
4285 /*
4286 * If the previous sink is not released and different from the current,
4287 * we deduce we are in a state where we can not rely on usermode call
4288 * to turn on the display, so we do it here
4289 */
4290 if (acrtc_state->stream->sink != aconnector->dc_sink)
4291 dm_force_atomic_commit(&aconnector->base);
4292}
4293
e7b07cee
HW		 4294/*`
4295 * Grabs all modesetting locks to serialize against any blocking commits,
4296 * Waits for completion of all non blocking commits.
4297 */
4298static int do_aquire_global_lock(
4299 struct drm_device *dev,
4300 struct drm_atomic_state *state)
4301{
4302 struct drm_crtc *crtc;
4303 struct drm_crtc_commit *commit;
4304 long ret;
4305
4306 /* Adding all modeset locks to aquire_ctx will
4307 * ensure that when the framework release it the
4308 * extra locks we are locking here will get released to
4309 */
4310 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4311 if (ret)
4312 return ret;
4313
4314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4315 spin_lock(&crtc->commit_lock);
4316 commit = list_first_entry_or_null(&crtc->commit_list,
4317 struct drm_crtc_commit, commit_entry);
4318 if (commit)
4319 drm_crtc_commit_get(commit);
4320 spin_unlock(&crtc->commit_lock);
4321
4322 if (!commit)
4323 continue;
4324
4325 /* Make sure all pending HW programming completed and
4326 * page flips done
4327 */
4328 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4329
4330 if (ret > 0)
4331 ret = wait_for_completion_interruptible_timeout(
4332 &commit->flip_done, 10*HZ);
4333
4334 if (ret == 0)
4335 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4336 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4337
4338 drm_crtc_commit_put(commit);
4339 }
4340
4341 return ret < 0 ? ret : 0;
4342}
4343
62f55537
AG		 4344static int dm_update_crtcs_state(
4345 struct dc *dc,
4346 struct drm_atomic_state *state,
4347 bool enable,
4348 bool *lock_and_validation_needed)
e7b07cee 4349{
e7b07cee
HW		 4350 struct drm_crtc *crtc;
4351 struct drm_crtc_state *crtc_state;
62f55537 4352 int i;
e7b07cee 4353 struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
1dc90497 4354 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4355 struct dc_stream_state *new_stream;
62f55537 4356 int ret = 0;
d4d4a645 4357
62f55537
AG		 4358 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4359 /* update changed items */
19f89e23 4360 for_each_crtc_in_state(state, crtc, crtc_state, i) {
62f55537
AG		 4361 struct amdgpu_crtc *acrtc = NULL;
4362 struct amdgpu_connector *aconnector = NULL;
62f55537
AG		 4363 struct drm_connector_state *conn_state = NULL;
4364 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4365
9635b754
DS		 4366 new_stream = NULL;
4367
62f55537
AG		 4368 old_acrtc_state = to_dm_crtc_state(crtc->state);
4369 new_acrtc_state = to_dm_crtc_state(crtc_state);
4370 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4371
62f55537 4372 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
19f89e23 4373
62f55537
AG		 4374 /* TODO This hack should go away */
4375 if (aconnector && aconnector->dc_sink) {
4376 conn_state = drm_atomic_get_connector_state(state,
4377 &aconnector->base);
19f89e23 4378
62f55537
AG		 4379 if (IS_ERR(conn_state)) {
4380 ret = PTR_ERR_OR_ZERO(conn_state);
4381 break;
4382 }
19f89e23 4383
62f55537 4384 dm_conn_state = to_dm_connector_state(conn_state);
19f89e23 4385
62f55537
AG		 4386 new_stream = create_stream_for_sink(aconnector,
4387 &crtc_state->mode,
4388 dm_conn_state);
19f89e23 4389
62f55537
AG		 4390 /*
4391 * we can have no stream on ACTION_SET if a display
4392 * was disconnected during S3, in this case it not and
4393 * error, the OS will be updated after detection, and
4394 * do the right thing on next atomic commit
4395 */
19f89e23 4396
62f55537
AG		 4397 if (!new_stream) {
4398 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4399 __func__, acrtc->base.base.id);
4400 break;
19f89e23 4401 }
62f55537 4402 }
19f89e23 4403
62f55537
AG		 4404 if (dc_is_stream_unchanged(new_stream,
4405 old_acrtc_state->stream)) {
19f89e23 4406
62f55537 4407 crtc_state->mode_changed = false;
e7b07cee 4408
62f55537
AG		 4409 DRM_DEBUG_KMS("Mode change not required, setting mode_changed to %d",
4410 crtc_state->mode_changed);
4411 }
b830ebc9 4412
e7b07cee 4413
62f55537 4414 if (!drm_atomic_crtc_needs_modeset(crtc_state))
9635b754 4415 goto next_crtc;
e7b07cee
HW		 4416
4417 DRM_DEBUG_KMS(
4418 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4419 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4420 "connectors_changed:%d\n",
4421 acrtc->crtc_id,
4422 crtc_state->enable,
4423 crtc_state->active,
4424 crtc_state->planes_changed,
4425 crtc_state->mode_changed,
4426 crtc_state->active_changed,
4427 crtc_state->connectors_changed);
4428
62f55537
AG		 4429 /* Remove stream for any changed/disabled CRTC */
4430 if (!enable) {
4431
4432 if (!old_acrtc_state->stream)
9635b754 4433 goto next_crtc;
62f55537
AG		 4434
4435 DRM_DEBUG_KMS("Disabling DRM crtc: %d\n",
4436 crtc->base.id);
e7b07cee 4437
1dc90497 4438 /* i.e. reset mode */
62f55537
AG		 4439 if (!dc_remove_stream_from_ctx(
4440 dc,
4441 dm_state->context,
4442 old_acrtc_state->stream)) {
4443 ret = -EINVAL;
9635b754 4444 goto fail;
62f55537
AG		 4445 }
4446
4447 dc_stream_release(old_acrtc_state->stream);
4448 new_acrtc_state->stream = NULL;
4449
4450 *lock_and_validation_needed = true;
4451
4452 } else {/* Add stream for any updated/enabled CRTC */
4453
4454 if (modereset_required(crtc_state))
9635b754 4455 goto next_crtc;
62f55537
AG		 4456
4457 if (modeset_required(crtc_state, new_stream,
4458 old_acrtc_state->stream)) {
4459
4460 WARN_ON(new_acrtc_state->stream);
4461
4462 new_acrtc_state->stream = new_stream;
4463 dc_stream_retain(new_stream);
4464
4465 DRM_DEBUG_KMS("Enabling DRM crtc: %d\n",
4466 crtc->base.id);
1dc90497 4467
62f55537 4468 if (!dc_add_stream_to_ctx(
1dc90497
AG		 4469 dc,
4470 dm_state->context,
4471 new_acrtc_state->stream)) {
4472 ret = -EINVAL;
9635b754 4473 goto fail;
1dc90497
AG		 4474 }
4475
62f55537 4476 *lock_and_validation_needed = true;
9b690ef3 4477 }
62f55537 4478 }
9b690ef3 4479
9635b754 4480next_crtc:
62f55537
AG		 4481 /* Release extra reference */
4482 if (new_stream)
4483 dc_stream_release(new_stream);
4484 }
e7b07cee 4485
62f55537 4486 return ret;
9635b754
DS		 4487
4488fail:
4489 if (new_stream)
4490 dc_stream_release(new_stream);
4491 return ret;
62f55537 4492}
9b690ef3 4493
62f55537
AG		 4494static int dm_update_planes_state(
4495 struct dc *dc,
4496 struct drm_atomic_state *state,
4497 bool enable,
4498 bool *lock_and_validation_needed)
4499{
4500 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
4501 struct drm_crtc_state *new_crtc_state;
4502 struct drm_plane *plane;
4503 struct drm_plane_state *old_plane_state, *new_plane_state;
4504 struct dm_crtc_state *new_acrtc_state, *old_acrtc_state;
4505 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4506 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
4507 int i ;
4508 /* TODO return page_flip_needed() function */
4509 bool pflip_needed = !state->allow_modeset;
4510 int ret = 0;
e7b07cee 4511
62f55537
AG		 4512 if (pflip_needed)
4513 return ret;
9b690ef3 4514
62f55537
AG		 4515 /* Add new planes */
4516 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4517 new_plane_crtc = new_plane_state->crtc;
4518 old_plane_crtc = old_plane_state->crtc;
4519 new_dm_plane_state = to_dm_plane_state(new_plane_state);
4520 old_dm_plane_state = to_dm_plane_state(old_plane_state);
4521
4522 /*TODO Implement atomic check for cursor plane */
4523 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4524 continue;
9b690ef3 4525
62f55537
AG		 4526 /* Remove any changed/removed planes */
4527 if (!enable) {
a7b06724 4528
62f55537
AG		 4529 if (!old_plane_crtc)
4530 continue;
4531
4532 old_acrtc_state = to_dm_crtc_state(
4533 drm_atomic_get_old_crtc_state(
4534 state,
4535 old_plane_crtc));
9b690ef3 4536
62f55537
AG		 4537 if (!old_acrtc_state->stream)
4538 continue;
4539
4540 DRM_DEBUG_KMS("Disabling DRM plane: %d on DRM crtc %d\n",
4541 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4542
62f55537
AG		 4543 if (!dc_remove_plane_from_context(
4544 dc,
4545 old_acrtc_state->stream,
4546 old_dm_plane_state->dc_state,
4547 dm_state->context)) {
4548
4549 ret = EINVAL;
4550 return ret;
e7b07cee
HW		 4551 }
4552
9b690ef3 4553
62f55537
AG		 4554 dc_plane_state_release(old_dm_plane_state->dc_state);
4555 new_dm_plane_state->dc_state = NULL;
1dc90497 4556
62f55537 4557 *lock_and_validation_needed = true;
1dc90497 4558
62f55537 4559 } else { /* Add new planes */
1dc90497 4560
62f55537
AG		 4561 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4562 continue;
e7b07cee 4563
62f55537
AG		 4564 if (!new_plane_crtc)
4565 continue;
e7b07cee 4566
62f55537
AG		 4567 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
4568 new_acrtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4569
62f55537
AG		 4570 if (!new_acrtc_state->stream)
4571 continue;
4572
4573
4574 WARN_ON(new_dm_plane_state->dc_state);
9b690ef3 4575
62f55537
AG		 4576 new_dm_plane_state->dc_state = dc_create_plane_state(dc);
4577
4578 DRM_DEBUG_KMS("Enabling DRM plane: %d on DRM crtc %d\n",
4579 plane->base.id, new_plane_crtc->base.id);
4580
4581 if (!new_dm_plane_state->dc_state) {
4582 ret = -EINVAL;
4583 return ret;
4584 }
4585
4586 ret = fill_plane_attributes(
4587 new_plane_crtc->dev->dev_private,
4588 new_dm_plane_state->dc_state,
4589 new_plane_state,
4590 new_crtc_state,
4591 false);
4592 if (ret)
4593 return ret;
4594
4595
4596 if (!dc_add_plane_to_context(
4597 dc,
4598 new_acrtc_state->stream,
4599 new_dm_plane_state->dc_state,
4600 dm_state->context)) {
4601
4602 ret = -EINVAL;
4603 return ret;
e7b07cee 4604 }
62f55537
AG		 4605
4606 *lock_and_validation_needed = true;
e7b07cee 4607 }
62f55537 4608 }
e7b07cee
HW		 4609
4610
62f55537
AG		 4611 return ret;
4612}
4613
4614int amdgpu_dm_atomic_check(struct drm_device *dev,
4615 struct drm_atomic_state *state)
4616{
4617 int i;
4618 int ret;
4619 struct amdgpu_device *adev = dev->dev_private;
4620 struct dc *dc = adev->dm.dc;
4621 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4622 struct drm_connector *connector;
4623 struct drm_connector_state *conn_state;
4624 struct drm_crtc *crtc;
4625 struct drm_crtc_state *crtc_state;
e7b07cee 4626
62f55537
AG		 4627 /*
4628 * This bool will be set for true for any modeset/reset
4629 * or plane update which implies non fast surface update.
4630 */
4631 bool lock_and_validation_needed = false;
4632
4633 ret = drm_atomic_helper_check_modeset(dev, state);
4634
4635 if (ret) {
4636 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4637 return ret;
4638 }
4639
4640 /*
4641 * Hack: Commit needs planes right now, specifically for gamma
4642 * TODO rework commit to check CRTC for gamma change
4643 */
4644 for_each_crtc_in_state(state, crtc, crtc_state, i) {
4645 if (crtc_state->color_mgmt_changed) {
e7b07cee
HW		 4646 ret = drm_atomic_add_affected_planes(state, crtc);
4647 if (ret)
4648 goto fail;
4649 }
4650 }
4651
62f55537
AG		 4652 dm_state->context = dc_create_state();
4653 ASSERT(dm_state->context);
f36cc577 4654 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4655
4656 /* Remove exiting planes if they are modified */
4657 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4658 if (ret) {
4659 goto fail;
4660 }
4661
4662 /* Disable all crtcs which require disable */
4663 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4664 if (ret) {
4665 goto fail;
4666 }
4667
4668 /* Enable all crtcs which require enable */
4669 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4670 if (ret) {
4671 goto fail;
4672 }
4673
4674 /* Add new/modified planes */
4675 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4676 if (ret) {
4677 goto fail;
4678 }
4679
4680 /* Run this here since we want to validate the streams we created */
4681 ret = drm_atomic_helper_check_planes(dev, state);
4682 if (ret)
4683 goto fail;
4684
e7b07cee
HW		 4685 /* Check scaling and undersacn changes*/
4686 /*TODO Removed scaling changes validation due to inability to commit
4687 * new stream into context w\o causing full reset. Need to
4688 * decide how to handle.
4689 */
4690 for_each_connector_in_state(state, connector, conn_state, i) {
4691 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4692 struct dm_connector_state *con_old_state =
4693 to_dm_connector_state(aconnector->base.state);
4694 struct dm_connector_state *con_new_state =
4695 to_dm_connector_state(conn_state);
4696 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
4697
4698 /* Skip any modesets/resets */
4699 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
4700 continue;
4701
b830ebc9 4702 /* Skip any thing not scale or underscan changes */
e7b07cee
HW		 4703 if (!is_scaling_state_different(con_new_state, con_old_state))
4704 continue;
4705
4706 lock_and_validation_needed = true;
4707 }
4708
e7b07cee
HW		 4709 /*
4710 * For full updates case when
4711 * removing/adding/updating streams on once CRTC while flipping
4712 * on another CRTC,
4713 * acquiring global lock will guarantee that any such full
4714 * update commit
4715 * will wait for completion of any outstanding flip using DRMs
4716 * synchronization events.
4717 */
4718
4719 if (lock_and_validation_needed) {
4720
4721 ret = do_aquire_global_lock(dev, state);
4722 if (ret)
4723 goto fail;
1dc90497 4724
19f89e23 4725 if (!dc_validate_global_state(dc, dm_state->context)) {
e7b07cee
HW		 4726 ret = -EINVAL;
4727 goto fail;
4728 }
4729 }
4730
4731 /* Must be success */
4732 WARN_ON(ret);
4733 return ret;
4734
4735fail:
4736 if (ret == -EDEADLK)
4737 DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n");
4738 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
4739 DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n");
4740 else
62f55537 4741 DRM_ERROR("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4742
4743 return ret;
4744}
4745
4746static bool is_dp_capable_without_timing_msa(
4747 struct dc *dc,
4748 struct amdgpu_connector *amdgpu_connector)
4749{
4750 uint8_t dpcd_data;
4751 bool capable = false;
4752
4753 if (amdgpu_connector->dc_link &&
4754 dm_helpers_dp_read_dpcd(
4755 NULL,
4756 amdgpu_connector->dc_link,
4757 DP_DOWN_STREAM_PORT_COUNT,
4758 &dpcd_data,
4759 sizeof(dpcd_data))) {
4760 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4761 }
4762
4763 return capable;
4764}
4765void amdgpu_dm_add_sink_to_freesync_module(
4766 struct drm_connector *connector,
4767 struct edid *edid)
4768{
4769 int i;
4770 uint64_t val_capable;
4771 bool edid_check_required;
4772 struct detailed_timing *timing;
4773 struct detailed_non_pixel *data;
4774 struct detailed_data_monitor_range *range;
4775 struct amdgpu_connector *amdgpu_connector =
4776 to_amdgpu_connector(connector);
4777
4778 struct drm_device *dev = connector->dev;
4779 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4780
e7b07cee
HW		 4781 edid_check_required = false;
4782 if (!amdgpu_connector->dc_sink) {
4783 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4784 return;
4785 }
4786 if (!adev->dm.freesync_module)
4787 return;
4788 /*
4789 * if edid non zero restrict freesync only for dp and edp
4790 */
4791 if (edid) {
4792 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4793 || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
4794 edid_check_required = is_dp_capable_without_timing_msa(
4795 adev->dm.dc,
4796 amdgpu_connector);
4797 }
4798 }
4799 val_capable = 0;
4800 if (edid_check_required == true && (edid->version > 1 ||
4801 (edid->version == 1 && edid->revision > 1))) {
4802 for (i = 0; i < 4; i++) {
4803
4804 timing = &edid->detailed_timings[i];
4805 data = &timing->data.other_data;
4806 range = &data->data.range;
4807 /*
4808 * Check if monitor has continuous frequency mode
4809 */
4810 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4811 continue;
4812 /*
4813 * Check for flag range limits only. If flag == 1 then
4814 * no additional timing information provided.
4815 * Default GTF, GTF Secondary curve and CVT are not
4816 * supported
4817 */
4818 if (range->flags != 1)
4819 continue;
4820
4821 amdgpu_connector->min_vfreq = range->min_vfreq;
4822 amdgpu_connector->max_vfreq = range->max_vfreq;
4823 amdgpu_connector->pixel_clock_mhz =
4824 range->pixel_clock_mhz * 10;
4825 break;
4826 }
4827
4828 if (amdgpu_connector->max_vfreq -
4829 amdgpu_connector->min_vfreq > 10) {
4830 amdgpu_connector->caps.supported = true;
4831 amdgpu_connector->caps.min_refresh_in_micro_hz =
4832 amdgpu_connector->min_vfreq * 1000000;
4833 amdgpu_connector->caps.max_refresh_in_micro_hz =
4834 amdgpu_connector->max_vfreq * 1000000;
4835 val_capable = 1;
4836 }
4837 }
4838
4839 /*
4840 * TODO figure out how to notify user-mode or DRM of freesync caps
4841 * once we figure out how to deal with freesync in an upstreamable
4842 * fashion
4843 */
4844
4845}
4846
4847void amdgpu_dm_remove_sink_from_freesync_module(
4848 struct drm_connector *connector)
4849{
4850 /*
4851 * TODO fill in once we figure out how to deal with freesync in
4852 * an upstreamable fashion
4853 */
4854}
Linux 6.x block layer and io_uring tree(s)