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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
0cf5eb76 DF |
26 | /* The caprices of the preprocessor require that this be declared right here */ |
27 | #define CREATE_TRACE_POINTS | |
28 | ||
4562236b HW |
29 | #include "dm_services_types.h" |
30 | #include "dc.h" | |
1dc90497 | 31 | #include "dc/inc/core_types.h" |
a7669aff | 32 | #include "dal_asic_id.h" |
4562236b HW |
33 | |
34 | #include "vid.h" | |
35 | #include "amdgpu.h" | |
a49dcb88 | 36 | #include "amdgpu_display.h" |
a94d5569 | 37 | #include "amdgpu_ucode.h" |
4562236b HW |
38 | #include "atom.h" |
39 | #include "amdgpu_dm.h" | |
e7b07cee | 40 | #include "amdgpu_pm.h" |
4562236b HW |
41 | |
42 | #include "amd_shared.h" | |
43 | #include "amdgpu_dm_irq.h" | |
44 | #include "dm_helpers.h" | |
e7b07cee | 45 | #include "amdgpu_dm_mst_types.h" |
dc38fd9d DF |
46 | #if defined(CONFIG_DEBUG_FS) |
47 | #include "amdgpu_dm_debugfs.h" | |
48 | #endif | |
4562236b HW |
49 | |
50 | #include "ivsrcid/ivsrcid_vislands30.h" | |
51 | ||
52 | #include <linux/module.h> | |
53 | #include <linux/moduleparam.h> | |
54 | #include <linux/version.h> | |
e7b07cee | 55 | #include <linux/types.h> |
97028037 | 56 | #include <linux/pm_runtime.h> |
09d21852 | 57 | #include <linux/pci.h> |
a94d5569 | 58 | #include <linux/firmware.h> |
6ce8f316 | 59 | #include <linux/component.h> |
4562236b HW |
60 | |
61 | #include <drm/drm_atomic.h> | |
674e78ac | 62 | #include <drm/drm_atomic_uapi.h> |
4562236b HW |
63 | #include <drm/drm_atomic_helper.h> |
64 | #include <drm/drm_dp_mst_helper.h> | |
e7b07cee | 65 | #include <drm/drm_fb_helper.h> |
09d21852 | 66 | #include <drm/drm_fourcc.h> |
e7b07cee | 67 | #include <drm/drm_edid.h> |
09d21852 | 68 | #include <drm/drm_vblank.h> |
6ce8f316 | 69 | #include <drm/drm_audio_component.h> |
4562236b | 70 | |
ff5ef992 | 71 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
5527cd06 | 72 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
ff5ef992 | 73 | |
ad941f7a FX |
74 | #include "dcn/dcn_1_0_offset.h" |
75 | #include "dcn/dcn_1_0_sh_mask.h" | |
407e7517 HZ |
76 | #include "soc15_hw_ip.h" |
77 | #include "vega10_ip_offset.h" | |
ff5ef992 AD |
78 | |
79 | #include "soc15_common.h" | |
80 | #endif | |
81 | ||
e7b07cee | 82 | #include "modules/inc/mod_freesync.h" |
bbf854dc | 83 | #include "modules/power/power_helpers.h" |
ecd0136b | 84 | #include "modules/inc/mod_info_packet.h" |
e7b07cee | 85 | |
a94d5569 DF |
86 | #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" |
87 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); | |
e7b07cee | 88 | |
b8592b48 LL |
89 | /** |
90 | * DOC: overview | |
91 | * | |
92 | * The AMDgpu display manager, **amdgpu_dm** (or even simpler, | |
93 | * **dm**) sits between DRM and DC. It acts as a liason, converting DRM | |
94 | * requests into DC requests, and DC responses into DRM responses. | |
95 | * | |
96 | * The root control structure is &struct amdgpu_display_manager. | |
97 | */ | |
98 | ||
7578ecda AD |
99 | /* basic init/fini API */ |
100 | static int amdgpu_dm_init(struct amdgpu_device *adev); | |
101 | static void amdgpu_dm_fini(struct amdgpu_device *adev); | |
102 | ||
1f6010a9 DF |
103 | /* |
104 | * initializes drm_device display related structures, based on the information | |
7578ecda AD |
105 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
106 | * drm_encoder, drm_mode_config | |
107 | * | |
108 | * Returns 0 on success | |
109 | */ | |
110 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); | |
111 | /* removes and deallocates the drm structures, created by the above function */ | |
112 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); | |
113 | ||
114 | static void | |
115 | amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); | |
116 | ||
117 | static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, | |
f180b4bc | 118 | struct drm_plane *plane, |
cc1fec57 NK |
119 | unsigned long possible_crtcs, |
120 | const struct dc_plane_cap *plane_cap); | |
7578ecda AD |
121 | static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, |
122 | struct drm_plane *plane, | |
123 | uint32_t link_index); | |
124 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, | |
125 | struct amdgpu_dm_connector *amdgpu_dm_connector, | |
126 | uint32_t link_index, | |
127 | struct amdgpu_encoder *amdgpu_encoder); | |
128 | static int amdgpu_dm_encoder_init(struct drm_device *dev, | |
129 | struct amdgpu_encoder *aencoder, | |
130 | uint32_t link_index); | |
131 | ||
132 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); | |
133 | ||
134 | static int amdgpu_dm_atomic_commit(struct drm_device *dev, | |
135 | struct drm_atomic_state *state, | |
136 | bool nonblock); | |
137 | ||
138 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); | |
139 | ||
140 | static int amdgpu_dm_atomic_check(struct drm_device *dev, | |
141 | struct drm_atomic_state *state); | |
142 | ||
674e78ac NK |
143 | static void handle_cursor_update(struct drm_plane *plane, |
144 | struct drm_plane_state *old_plane_state); | |
7578ecda | 145 | |
4562236b HW |
146 | /* |
147 | * dm_vblank_get_counter | |
148 | * | |
149 | * @brief | |
150 | * Get counter for number of vertical blanks | |
151 | * | |
152 | * @param | |
153 | * struct amdgpu_device *adev - [in] desired amdgpu device | |
154 | * int disp_idx - [in] which CRTC to get the counter from | |
155 | * | |
156 | * @return | |
157 | * Counter for vertical blanks | |
158 | */ | |
159 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
160 | { | |
161 | if (crtc >= adev->mode_info.num_crtc) | |
162 | return 0; | |
163 | else { | |
164 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
da5c47f6 AG |
165 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state( |
166 | acrtc->base.state); | |
4562236b | 167 | |
da5c47f6 AG |
168 | |
169 | if (acrtc_state->stream == NULL) { | |
0971c40e HW |
170 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
171 | crtc); | |
4562236b HW |
172 | return 0; |
173 | } | |
174 | ||
da5c47f6 | 175 | return dc_stream_get_vblank_counter(acrtc_state->stream); |
4562236b HW |
176 | } |
177 | } | |
178 | ||
179 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
3ee6b26b | 180 | u32 *vbl, u32 *position) |
4562236b | 181 | { |
81c50963 ST |
182 | uint32_t v_blank_start, v_blank_end, h_position, v_position; |
183 | ||
4562236b HW |
184 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
185 | return -EINVAL; | |
186 | else { | |
187 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
da5c47f6 AG |
188 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state( |
189 | acrtc->base.state); | |
4562236b | 190 | |
da5c47f6 | 191 | if (acrtc_state->stream == NULL) { |
0971c40e HW |
192 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
193 | crtc); | |
4562236b HW |
194 | return 0; |
195 | } | |
196 | ||
81c50963 ST |
197 | /* |
198 | * TODO rework base driver to use values directly. | |
199 | * for now parse it back into reg-format | |
200 | */ | |
da5c47f6 | 201 | dc_stream_get_scanoutpos(acrtc_state->stream, |
81c50963 ST |
202 | &v_blank_start, |
203 | &v_blank_end, | |
204 | &h_position, | |
205 | &v_position); | |
206 | ||
e806208d AG |
207 | *position = v_position | (h_position << 16); |
208 | *vbl = v_blank_start | (v_blank_end << 16); | |
4562236b HW |
209 | } |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | static bool dm_is_idle(void *handle) | |
215 | { | |
216 | /* XXX todo */ | |
217 | return true; | |
218 | } | |
219 | ||
220 | static int dm_wait_for_idle(void *handle) | |
221 | { | |
222 | /* XXX todo */ | |
223 | return 0; | |
224 | } | |
225 | ||
226 | static bool dm_check_soft_reset(void *handle) | |
227 | { | |
228 | return false; | |
229 | } | |
230 | ||
231 | static int dm_soft_reset(void *handle) | |
232 | { | |
233 | /* XXX todo */ | |
234 | return 0; | |
235 | } | |
236 | ||
3ee6b26b AD |
237 | static struct amdgpu_crtc * |
238 | get_crtc_by_otg_inst(struct amdgpu_device *adev, | |
239 | int otg_inst) | |
4562236b HW |
240 | { |
241 | struct drm_device *dev = adev->ddev; | |
242 | struct drm_crtc *crtc; | |
243 | struct amdgpu_crtc *amdgpu_crtc; | |
244 | ||
4562236b HW |
245 | if (otg_inst == -1) { |
246 | WARN_ON(1); | |
247 | return adev->mode_info.crtcs[0]; | |
248 | } | |
249 | ||
250 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
251 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
252 | ||
253 | if (amdgpu_crtc->otg_inst == otg_inst) | |
254 | return amdgpu_crtc; | |
255 | } | |
256 | ||
257 | return NULL; | |
258 | } | |
259 | ||
66b0c973 MK |
260 | static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) |
261 | { | |
262 | return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || | |
263 | dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; | |
264 | } | |
265 | ||
4562236b HW |
266 | static void dm_pflip_high_irq(void *interrupt_params) |
267 | { | |
4562236b HW |
268 | struct amdgpu_crtc *amdgpu_crtc; |
269 | struct common_irq_params *irq_params = interrupt_params; | |
270 | struct amdgpu_device *adev = irq_params->adev; | |
271 | unsigned long flags; | |
71bbe51a MK |
272 | struct drm_pending_vblank_event *e; |
273 | struct dm_crtc_state *acrtc_state; | |
274 | uint32_t vpos, hpos, v_blank_start, v_blank_end; | |
275 | bool vrr_active; | |
4562236b HW |
276 | |
277 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); | |
278 | ||
279 | /* IRQ could occur when in initial stage */ | |
1f6010a9 | 280 | /* TODO work and BO cleanup */ |
4562236b HW |
281 | if (amdgpu_crtc == NULL) { |
282 | DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); | |
283 | return; | |
284 | } | |
285 | ||
286 | spin_lock_irqsave(&adev->ddev->event_lock, flags); | |
4562236b HW |
287 | |
288 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ | |
289 | DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", | |
290 | amdgpu_crtc->pflip_status, | |
291 | AMDGPU_FLIP_SUBMITTED, | |
292 | amdgpu_crtc->crtc_id, | |
293 | amdgpu_crtc); | |
294 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
295 | return; | |
296 | } | |
297 | ||
71bbe51a MK |
298 | /* page flip completed. */ |
299 | e = amdgpu_crtc->event; | |
300 | amdgpu_crtc->event = NULL; | |
4562236b | 301 | |
71bbe51a MK |
302 | if (!e) |
303 | WARN_ON(1); | |
1159898a | 304 | |
71bbe51a MK |
305 | acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state); |
306 | vrr_active = amdgpu_dm_vrr_active(acrtc_state); | |
307 | ||
308 | /* Fixed refresh rate, or VRR scanout position outside front-porch? */ | |
309 | if (!vrr_active || | |
310 | !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start, | |
311 | &v_blank_end, &hpos, &vpos) || | |
312 | (vpos < v_blank_start)) { | |
313 | /* Update to correct count and vblank timestamp if racing with | |
314 | * vblank irq. This also updates to the correct vblank timestamp | |
315 | * even in VRR mode, as scanout is past the front-porch atm. | |
316 | */ | |
317 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); | |
1159898a | 318 | |
71bbe51a MK |
319 | /* Wake up userspace by sending the pageflip event with proper |
320 | * count and timestamp of vblank of flip completion. | |
321 | */ | |
322 | if (e) { | |
323 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); | |
324 | ||
325 | /* Event sent, so done with vblank for this flip */ | |
326 | drm_crtc_vblank_put(&amdgpu_crtc->base); | |
327 | } | |
328 | } else if (e) { | |
329 | /* VRR active and inside front-porch: vblank count and | |
330 | * timestamp for pageflip event will only be up to date after | |
331 | * drm_crtc_handle_vblank() has been executed from late vblank | |
332 | * irq handler after start of back-porch (vline 0). We queue the | |
333 | * pageflip event for send-out by drm_crtc_handle_vblank() with | |
334 | * updated timestamp and count, once it runs after us. | |
335 | * | |
336 | * We need to open-code this instead of using the helper | |
337 | * drm_crtc_arm_vblank_event(), as that helper would | |
338 | * call drm_crtc_accurate_vblank_count(), which we must | |
339 | * not call in VRR mode while we are in front-porch! | |
340 | */ | |
341 | ||
342 | /* sequence will be replaced by real count during send-out. */ | |
343 | e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); | |
344 | e->pipe = amdgpu_crtc->crtc_id; | |
345 | ||
346 | list_add_tail(&e->base.link, &adev->ddev->vblank_event_list); | |
347 | e = NULL; | |
348 | } | |
4562236b | 349 | |
fdd1fe57 MK |
350 | /* Keep track of vblank of this flip for flip throttling. We use the |
351 | * cooked hw counter, as that one incremented at start of this vblank | |
352 | * of pageflip completion, so last_flip_vblank is the forbidden count | |
353 | * for queueing new pageflips if vsync + VRR is enabled. | |
354 | */ | |
355 | amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, | |
356 | amdgpu_crtc->crtc_id); | |
357 | ||
54f5499a | 358 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
4562236b HW |
359 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); |
360 | ||
71bbe51a MK |
361 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", |
362 | amdgpu_crtc->crtc_id, amdgpu_crtc, | |
363 | vrr_active, (int) !e); | |
4562236b HW |
364 | } |
365 | ||
d2574c33 MK |
366 | static void dm_vupdate_high_irq(void *interrupt_params) |
367 | { | |
368 | struct common_irq_params *irq_params = interrupt_params; | |
369 | struct amdgpu_device *adev = irq_params->adev; | |
370 | struct amdgpu_crtc *acrtc; | |
371 | struct dm_crtc_state *acrtc_state; | |
09aef2c4 | 372 | unsigned long flags; |
d2574c33 MK |
373 | |
374 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); | |
375 | ||
376 | if (acrtc) { | |
377 | acrtc_state = to_dm_crtc_state(acrtc->base.state); | |
378 | ||
379 | DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, | |
380 | amdgpu_dm_vrr_active(acrtc_state)); | |
381 | ||
382 | /* Core vblank handling is done here after end of front-porch in | |
383 | * vrr mode, as vblank timestamping will give valid results | |
384 | * while now done after front-porch. This will also deliver | |
385 | * page-flip completion events that have been queued to us | |
386 | * if a pageflip happened inside front-porch. | |
387 | */ | |
09aef2c4 | 388 | if (amdgpu_dm_vrr_active(acrtc_state)) { |
d2574c33 | 389 | drm_crtc_handle_vblank(&acrtc->base); |
09aef2c4 MK |
390 | |
391 | /* BTR processing for pre-DCE12 ASICs */ | |
392 | if (acrtc_state->stream && | |
393 | adev->family < AMDGPU_FAMILY_AI) { | |
394 | spin_lock_irqsave(&adev->ddev->event_lock, flags); | |
395 | mod_freesync_handle_v_update( | |
396 | adev->dm.freesync_module, | |
397 | acrtc_state->stream, | |
398 | &acrtc_state->vrr_params); | |
399 | ||
400 | dc_stream_adjust_vmin_vmax( | |
401 | adev->dm.dc, | |
402 | acrtc_state->stream, | |
403 | &acrtc_state->vrr_params.adjust); | |
404 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
405 | } | |
406 | } | |
d2574c33 MK |
407 | } |
408 | } | |
409 | ||
4562236b HW |
410 | static void dm_crtc_high_irq(void *interrupt_params) |
411 | { | |
412 | struct common_irq_params *irq_params = interrupt_params; | |
413 | struct amdgpu_device *adev = irq_params->adev; | |
4562236b | 414 | struct amdgpu_crtc *acrtc; |
180db303 | 415 | struct dm_crtc_state *acrtc_state; |
09aef2c4 | 416 | unsigned long flags; |
4562236b | 417 | |
b57de80a | 418 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
4562236b | 419 | |
e5d0170e | 420 | if (acrtc) { |
180db303 NK |
421 | acrtc_state = to_dm_crtc_state(acrtc->base.state); |
422 | ||
d2574c33 MK |
423 | DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, |
424 | amdgpu_dm_vrr_active(acrtc_state)); | |
425 | ||
426 | /* Core vblank handling at start of front-porch is only possible | |
427 | * in non-vrr mode, as only there vblank timestamping will give | |
428 | * valid results while done in front-porch. Otherwise defer it | |
429 | * to dm_vupdate_high_irq after end of front-porch. | |
430 | */ | |
431 | if (!amdgpu_dm_vrr_active(acrtc_state)) | |
432 | drm_crtc_handle_vblank(&acrtc->base); | |
433 | ||
434 | /* Following stuff must happen at start of vblank, for crc | |
435 | * computation and below-the-range btr support in vrr mode. | |
436 | */ | |
437 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); | |
438 | ||
09aef2c4 | 439 | if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI && |
180db303 NK |
440 | acrtc_state->vrr_params.supported && |
441 | acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) { | |
09aef2c4 | 442 | spin_lock_irqsave(&adev->ddev->event_lock, flags); |
180db303 NK |
443 | mod_freesync_handle_v_update( |
444 | adev->dm.freesync_module, | |
445 | acrtc_state->stream, | |
446 | &acrtc_state->vrr_params); | |
447 | ||
448 | dc_stream_adjust_vmin_vmax( | |
449 | adev->dm.dc, | |
450 | acrtc_state->stream, | |
451 | &acrtc_state->vrr_params.adjust); | |
09aef2c4 | 452 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); |
180db303 | 453 | } |
e5d0170e | 454 | } |
4562236b HW |
455 | } |
456 | ||
457 | static int dm_set_clockgating_state(void *handle, | |
458 | enum amd_clockgating_state state) | |
459 | { | |
460 | return 0; | |
461 | } | |
462 | ||
463 | static int dm_set_powergating_state(void *handle, | |
464 | enum amd_powergating_state state) | |
465 | { | |
466 | return 0; | |
467 | } | |
468 | ||
469 | /* Prototypes of private functions */ | |
470 | static int dm_early_init(void* handle); | |
471 | ||
a32e24b4 | 472 | /* Allocate memory for FBC compressed data */ |
3e332d3a | 473 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
a32e24b4 | 474 | { |
3e332d3a RL |
475 | struct drm_device *dev = connector->dev; |
476 | struct amdgpu_device *adev = dev->dev_private; | |
a32e24b4 | 477 | struct dm_comressor_info *compressor = &adev->dm.compressor; |
3e332d3a RL |
478 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); |
479 | struct drm_display_mode *mode; | |
42e67c3b RL |
480 | unsigned long max_size = 0; |
481 | ||
482 | if (adev->dm.dc->fbc_compressor == NULL) | |
483 | return; | |
a32e24b4 | 484 | |
3e332d3a | 485 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
42e67c3b RL |
486 | return; |
487 | ||
3e332d3a RL |
488 | if (compressor->bo_ptr) |
489 | return; | |
42e67c3b | 490 | |
42e67c3b | 491 | |
3e332d3a RL |
492 | list_for_each_entry(mode, &connector->modes, head) { |
493 | if (max_size < mode->htotal * mode->vtotal) | |
494 | max_size = mode->htotal * mode->vtotal; | |
42e67c3b RL |
495 | } |
496 | ||
497 | if (max_size) { | |
498 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, | |
0e5916ff | 499 | AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, |
42e67c3b | 500 | &compressor->gpu_addr, &compressor->cpu_addr); |
a32e24b4 RL |
501 | |
502 | if (r) | |
42e67c3b RL |
503 | DRM_ERROR("DM: Failed to initialize FBC\n"); |
504 | else { | |
505 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; | |
506 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4); | |
507 | } | |
508 | ||
a32e24b4 RL |
509 | } |
510 | ||
511 | } | |
a32e24b4 | 512 | |
6ce8f316 NK |
513 | static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, |
514 | int pipe, bool *enabled, | |
515 | unsigned char *buf, int max_bytes) | |
516 | { | |
517 | struct drm_device *dev = dev_get_drvdata(kdev); | |
518 | struct amdgpu_device *adev = dev->dev_private; | |
519 | struct drm_connector *connector; | |
520 | struct drm_connector_list_iter conn_iter; | |
521 | struct amdgpu_dm_connector *aconnector; | |
522 | int ret = 0; | |
523 | ||
524 | *enabled = false; | |
525 | ||
526 | mutex_lock(&adev->dm.audio_lock); | |
527 | ||
528 | drm_connector_list_iter_begin(dev, &conn_iter); | |
529 | drm_for_each_connector_iter(connector, &conn_iter) { | |
530 | aconnector = to_amdgpu_dm_connector(connector); | |
531 | if (aconnector->audio_inst != port) | |
532 | continue; | |
533 | ||
534 | *enabled = true; | |
535 | ret = drm_eld_size(connector->eld); | |
536 | memcpy(buf, connector->eld, min(max_bytes, ret)); | |
537 | ||
538 | break; | |
539 | } | |
540 | drm_connector_list_iter_end(&conn_iter); | |
541 | ||
542 | mutex_unlock(&adev->dm.audio_lock); | |
543 | ||
544 | DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); | |
545 | ||
546 | return ret; | |
547 | } | |
548 | ||
549 | static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { | |
550 | .get_eld = amdgpu_dm_audio_component_get_eld, | |
551 | }; | |
552 | ||
553 | static int amdgpu_dm_audio_component_bind(struct device *kdev, | |
554 | struct device *hda_kdev, void *data) | |
555 | { | |
556 | struct drm_device *dev = dev_get_drvdata(kdev); | |
557 | struct amdgpu_device *adev = dev->dev_private; | |
558 | struct drm_audio_component *acomp = data; | |
559 | ||
560 | acomp->ops = &amdgpu_dm_audio_component_ops; | |
561 | acomp->dev = kdev; | |
562 | adev->dm.audio_component = acomp; | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
567 | static void amdgpu_dm_audio_component_unbind(struct device *kdev, | |
568 | struct device *hda_kdev, void *data) | |
569 | { | |
570 | struct drm_device *dev = dev_get_drvdata(kdev); | |
571 | struct amdgpu_device *adev = dev->dev_private; | |
572 | struct drm_audio_component *acomp = data; | |
573 | ||
574 | acomp->ops = NULL; | |
575 | acomp->dev = NULL; | |
576 | adev->dm.audio_component = NULL; | |
577 | } | |
578 | ||
579 | static const struct component_ops amdgpu_dm_audio_component_bind_ops = { | |
580 | .bind = amdgpu_dm_audio_component_bind, | |
581 | .unbind = amdgpu_dm_audio_component_unbind, | |
582 | }; | |
583 | ||
584 | static int amdgpu_dm_audio_init(struct amdgpu_device *adev) | |
585 | { | |
586 | int i, ret; | |
587 | ||
588 | if (!amdgpu_audio) | |
589 | return 0; | |
590 | ||
591 | adev->mode_info.audio.enabled = true; | |
592 | ||
593 | adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; | |
594 | ||
595 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { | |
596 | adev->mode_info.audio.pin[i].channels = -1; | |
597 | adev->mode_info.audio.pin[i].rate = -1; | |
598 | adev->mode_info.audio.pin[i].bits_per_sample = -1; | |
599 | adev->mode_info.audio.pin[i].status_bits = 0; | |
600 | adev->mode_info.audio.pin[i].category_code = 0; | |
601 | adev->mode_info.audio.pin[i].connected = false; | |
602 | adev->mode_info.audio.pin[i].id = | |
603 | adev->dm.dc->res_pool->audios[i]->inst; | |
604 | adev->mode_info.audio.pin[i].offset = 0; | |
605 | } | |
606 | ||
607 | ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
608 | if (ret < 0) | |
609 | return ret; | |
610 | ||
611 | adev->dm.audio_registered = true; | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) | |
617 | { | |
618 | if (!amdgpu_audio) | |
619 | return; | |
620 | ||
621 | if (!adev->mode_info.audio.enabled) | |
622 | return; | |
623 | ||
624 | if (adev->dm.audio_registered) { | |
625 | component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); | |
626 | adev->dm.audio_registered = false; | |
627 | } | |
628 | ||
629 | /* TODO: Disable audio? */ | |
630 | ||
631 | adev->mode_info.audio.enabled = false; | |
632 | } | |
633 | ||
634 | void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) | |
635 | { | |
636 | struct drm_audio_component *acomp = adev->dm.audio_component; | |
637 | ||
638 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { | |
639 | DRM_DEBUG_KMS("Notify ELD: %d\n", pin); | |
640 | ||
641 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, | |
642 | pin, -1); | |
643 | } | |
644 | } | |
645 | ||
7578ecda | 646 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
4562236b HW |
647 | { |
648 | struct dc_init_data init_data; | |
649 | adev->dm.ddev = adev->ddev; | |
650 | adev->dm.adev = adev; | |
651 | ||
4562236b HW |
652 | /* Zero all the fields */ |
653 | memset(&init_data, 0, sizeof(init_data)); | |
654 | ||
674e78ac | 655 | mutex_init(&adev->dm.dc_lock); |
6ce8f316 | 656 | mutex_init(&adev->dm.audio_lock); |
674e78ac | 657 | |
4562236b HW |
658 | if(amdgpu_dm_irq_init(adev)) { |
659 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); | |
660 | goto error; | |
661 | } | |
662 | ||
663 | init_data.asic_id.chip_family = adev->family; | |
664 | ||
665 | init_data.asic_id.pci_revision_id = adev->rev_id; | |
666 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; | |
667 | ||
770d13b1 | 668 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
4562236b HW |
669 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
670 | init_data.asic_id.atombios_base_address = | |
671 | adev->mode_info.atom_context->bios; | |
672 | ||
673 | init_data.driver = adev; | |
674 | ||
675 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); | |
676 | ||
677 | if (!adev->dm.cgs_device) { | |
678 | DRM_ERROR("amdgpu: failed to create cgs device.\n"); | |
679 | goto error; | |
680 | } | |
681 | ||
682 | init_data.cgs_device = adev->dm.cgs_device; | |
683 | ||
4562236b HW |
684 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
685 | ||
6e227308 HW |
686 | /* |
687 | * TODO debug why this doesn't work on Raven | |
688 | */ | |
689 | if (adev->flags & AMD_IS_APU && | |
690 | adev->asic_type >= CHIP_CARRIZO && | |
1c425915 | 691 | adev->asic_type <= CHIP_RAVEN) |
6e227308 HW |
692 | init_data.flags.gpu_vm_support = true; |
693 | ||
04b94af4 AD |
694 | if (amdgpu_dc_feature_mask & DC_FBC_MASK) |
695 | init_data.flags.fbc_support = true; | |
696 | ||
27eaa492 | 697 | init_data.flags.power_down_display_on_boot = true; |
78ad75f8 | 698 | |
48321c3d HW |
699 | #ifdef CONFIG_DRM_AMD_DC_DCN2_0 |
700 | init_data.soc_bounding_box = adev->dm.soc_bounding_box; | |
701 | #endif | |
27eaa492 | 702 | |
4562236b HW |
703 | /* Display Core create. */ |
704 | adev->dm.dc = dc_create(&init_data); | |
705 | ||
423788c7 | 706 | if (adev->dm.dc) { |
76121231 | 707 | DRM_INFO("Display Core initialized with v%s!\n", DC_VER); |
423788c7 | 708 | } else { |
76121231 | 709 | DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); |
423788c7 ES |
710 | goto error; |
711 | } | |
4562236b | 712 | |
4562236b HW |
713 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
714 | if (!adev->dm.freesync_module) { | |
715 | DRM_ERROR( | |
716 | "amdgpu: failed to initialize freesync_module.\n"); | |
717 | } else | |
f1ad2f5e | 718 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", |
4562236b HW |
719 | adev->dm.freesync_module); |
720 | ||
e277adc5 LSL |
721 | amdgpu_dm_init_color_mod(); |
722 | ||
4562236b HW |
723 | if (amdgpu_dm_initialize_drm_device(adev)) { |
724 | DRM_ERROR( | |
725 | "amdgpu: failed to initialize sw for display support.\n"); | |
726 | goto error; | |
727 | } | |
728 | ||
729 | /* Update the actual used number of crtc */ | |
730 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; | |
731 | ||
732 | /* TODO: Add_display_info? */ | |
733 | ||
734 | /* TODO use dynamic cursor width */ | |
ce75805e AG |
735 | adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
736 | adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; | |
4562236b HW |
737 | |
738 | if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { | |
739 | DRM_ERROR( | |
740 | "amdgpu: failed to initialize sw for display support.\n"); | |
741 | goto error; | |
742 | } | |
743 | ||
e498eb71 NK |
744 | #if defined(CONFIG_DEBUG_FS) |
745 | if (dtn_debugfs_init(adev)) | |
746 | DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); | |
747 | #endif | |
748 | ||
f1ad2f5e | 749 | DRM_DEBUG_DRIVER("KMS initialized.\n"); |
4562236b HW |
750 | |
751 | return 0; | |
752 | error: | |
753 | amdgpu_dm_fini(adev); | |
754 | ||
59d0f396 | 755 | return -EINVAL; |
4562236b HW |
756 | } |
757 | ||
7578ecda | 758 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
4562236b | 759 | { |
6ce8f316 NK |
760 | amdgpu_dm_audio_fini(adev); |
761 | ||
4562236b | 762 | amdgpu_dm_destroy_drm_device(&adev->dm); |
c8bdf2b6 ED |
763 | |
764 | /* DC Destroy TODO: Replace destroy DAL */ | |
765 | if (adev->dm.dc) | |
766 | dc_destroy(&adev->dm.dc); | |
4562236b HW |
767 | /* |
768 | * TODO: pageflip, vlank interrupt | |
769 | * | |
770 | * amdgpu_dm_irq_fini(adev); | |
771 | */ | |
772 | ||
773 | if (adev->dm.cgs_device) { | |
774 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); | |
775 | adev->dm.cgs_device = NULL; | |
776 | } | |
777 | if (adev->dm.freesync_module) { | |
778 | mod_freesync_destroy(adev->dm.freesync_module); | |
779 | adev->dm.freesync_module = NULL; | |
780 | } | |
674e78ac | 781 | |
6ce8f316 | 782 | mutex_destroy(&adev->dm.audio_lock); |
674e78ac NK |
783 | mutex_destroy(&adev->dm.dc_lock); |
784 | ||
4562236b HW |
785 | return; |
786 | } | |
787 | ||
a94d5569 | 788 | static int load_dmcu_fw(struct amdgpu_device *adev) |
4562236b | 789 | { |
a7669aff | 790 | const char *fw_name_dmcu = NULL; |
a94d5569 DF |
791 | int r; |
792 | const struct dmcu_firmware_header_v1_0 *hdr; | |
793 | ||
794 | switch(adev->asic_type) { | |
795 | case CHIP_BONAIRE: | |
796 | case CHIP_HAWAII: | |
797 | case CHIP_KAVERI: | |
798 | case CHIP_KABINI: | |
799 | case CHIP_MULLINS: | |
800 | case CHIP_TONGA: | |
801 | case CHIP_FIJI: | |
802 | case CHIP_CARRIZO: | |
803 | case CHIP_STONEY: | |
804 | case CHIP_POLARIS11: | |
805 | case CHIP_POLARIS10: | |
806 | case CHIP_POLARIS12: | |
807 | case CHIP_VEGAM: | |
808 | case CHIP_VEGA10: | |
809 | case CHIP_VEGA12: | |
810 | case CHIP_VEGA20: | |
476e955d | 811 | case CHIP_NAVI10: |
baebcf2e | 812 | case CHIP_NAVI14: |
a94d5569 DF |
813 | return 0; |
814 | case CHIP_RAVEN: | |
a7669aff HW |
815 | if (ASICREV_IS_PICASSO(adev->external_rev_id)) |
816 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
817 | else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) | |
818 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
819 | else | |
a7669aff | 820 | return 0; |
a94d5569 DF |
821 | break; |
822 | default: | |
823 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); | |
59d0f396 | 824 | return -EINVAL; |
a94d5569 DF |
825 | } |
826 | ||
827 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
828 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); | |
829 | return 0; | |
830 | } | |
831 | ||
832 | r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); | |
833 | if (r == -ENOENT) { | |
834 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ | |
835 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); | |
836 | adev->dm.fw_dmcu = NULL; | |
837 | return 0; | |
838 | } | |
839 | if (r) { | |
840 | dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", | |
841 | fw_name_dmcu); | |
842 | return r; | |
843 | } | |
844 | ||
845 | r = amdgpu_ucode_validate(adev->dm.fw_dmcu); | |
846 | if (r) { | |
847 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", | |
848 | fw_name_dmcu); | |
849 | release_firmware(adev->dm.fw_dmcu); | |
850 | adev->dm.fw_dmcu = NULL; | |
851 | return r; | |
852 | } | |
853 | ||
854 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; | |
855 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; | |
856 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; | |
857 | adev->firmware.fw_size += | |
858 | ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
859 | ||
860 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; | |
861 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; | |
862 | adev->firmware.fw_size += | |
863 | ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
864 | ||
ee6e89c0 DF |
865 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); |
866 | ||
a94d5569 DF |
867 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); |
868 | ||
4562236b HW |
869 | return 0; |
870 | } | |
871 | ||
a94d5569 DF |
872 | static int dm_sw_init(void *handle) |
873 | { | |
874 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
875 | ||
876 | return load_dmcu_fw(adev); | |
877 | } | |
878 | ||
4562236b HW |
879 | static int dm_sw_fini(void *handle) |
880 | { | |
a94d5569 DF |
881 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
882 | ||
883 | if(adev->dm.fw_dmcu) { | |
884 | release_firmware(adev->dm.fw_dmcu); | |
885 | adev->dm.fw_dmcu = NULL; | |
886 | } | |
887 | ||
4562236b HW |
888 | return 0; |
889 | } | |
890 | ||
7abcf6b5 | 891 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
4562236b | 892 | { |
c84dec2f | 893 | struct amdgpu_dm_connector *aconnector; |
4562236b | 894 | struct drm_connector *connector; |
7abcf6b5 | 895 | int ret = 0; |
4562236b HW |
896 | |
897 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
898 | ||
899 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
b349f76e | 900 | aconnector = to_amdgpu_dm_connector(connector); |
30ec2b97 JFZ |
901 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
902 | aconnector->mst_mgr.aux) { | |
f1ad2f5e | 903 | DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", |
7abcf6b5 AG |
904 | aconnector, aconnector->base.base.id); |
905 | ||
906 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); | |
907 | if (ret < 0) { | |
908 | DRM_ERROR("DM_MST: Failed to start MST\n"); | |
909 | ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; | |
910 | return ret; | |
4562236b | 911 | } |
7abcf6b5 | 912 | } |
4562236b HW |
913 | } |
914 | ||
915 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
7abcf6b5 AG |
916 | return ret; |
917 | } | |
918 | ||
919 | static int dm_late_init(void *handle) | |
920 | { | |
42e67c3b | 921 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7abcf6b5 | 922 | |
bbf854dc DF |
923 | struct dmcu_iram_parameters params; |
924 | unsigned int linear_lut[16]; | |
925 | int i; | |
926 | struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; | |
96cb7cf1 | 927 | bool ret = false; |
bbf854dc DF |
928 | |
929 | for (i = 0; i < 16; i++) | |
930 | linear_lut[i] = 0xFFFF * i / 15; | |
931 | ||
932 | params.set = 0; | |
933 | params.backlight_ramping_start = 0xCCCC; | |
934 | params.backlight_ramping_reduction = 0xCCCCCCCC; | |
935 | params.backlight_lut_array_size = 16; | |
936 | params.backlight_lut_array = linear_lut; | |
937 | ||
96cb7cf1 | 938 | /* todo will enable for navi10 */ |
939 | if (adev->asic_type <= CHIP_RAVEN) { | |
940 | ret = dmcu_load_iram(dmcu, params); | |
bbf854dc | 941 | |
96cb7cf1 | 942 | if (!ret) |
943 | return -EINVAL; | |
944 | } | |
bbf854dc | 945 | |
42e67c3b | 946 | return detect_mst_link_for_all_connectors(adev->ddev); |
4562236b HW |
947 | } |
948 | ||
949 | static void s3_handle_mst(struct drm_device *dev, bool suspend) | |
950 | { | |
c84dec2f | 951 | struct amdgpu_dm_connector *aconnector; |
4562236b | 952 | struct drm_connector *connector; |
fe7553be LP |
953 | struct drm_dp_mst_topology_mgr *mgr; |
954 | int ret; | |
955 | bool need_hotplug = false; | |
4562236b HW |
956 | |
957 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
958 | ||
fe7553be LP |
959 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
960 | head) { | |
961 | aconnector = to_amdgpu_dm_connector(connector); | |
962 | if (aconnector->dc_link->type != dc_connection_mst_branch || | |
963 | aconnector->mst_port) | |
964 | continue; | |
965 | ||
966 | mgr = &aconnector->mst_mgr; | |
967 | ||
968 | if (suspend) { | |
969 | drm_dp_mst_topology_mgr_suspend(mgr); | |
970 | } else { | |
971 | ret = drm_dp_mst_topology_mgr_resume(mgr); | |
972 | if (ret < 0) { | |
973 | drm_dp_mst_topology_mgr_set_mst(mgr, false); | |
974 | need_hotplug = true; | |
975 | } | |
976 | } | |
4562236b HW |
977 | } |
978 | ||
979 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
fe7553be LP |
980 | |
981 | if (need_hotplug) | |
982 | drm_kms_helper_hotplug_event(dev); | |
4562236b HW |
983 | } |
984 | ||
b8592b48 LL |
985 | /** |
986 | * dm_hw_init() - Initialize DC device | |
987 | * @handle: The base driver device containing the amdpgu_dm device. | |
988 | * | |
989 | * Initialize the &struct amdgpu_display_manager device. This involves calling | |
990 | * the initializers of each DM component, then populating the struct with them. | |
991 | * | |
992 | * Although the function implies hardware initialization, both hardware and | |
993 | * software are initialized here. Splitting them out to their relevant init | |
994 | * hooks is a future TODO item. | |
995 | * | |
996 | * Some notable things that are initialized here: | |
997 | * | |
998 | * - Display Core, both software and hardware | |
999 | * - DC modules that we need (freesync and color management) | |
1000 | * - DRM software states | |
1001 | * - Interrupt sources and handlers | |
1002 | * - Vblank support | |
1003 | * - Debug FS entries, if enabled | |
1004 | */ | |
4562236b HW |
1005 | static int dm_hw_init(void *handle) |
1006 | { | |
1007 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1008 | /* Create DAL display manager */ | |
1009 | amdgpu_dm_init(adev); | |
4562236b HW |
1010 | amdgpu_dm_hpd_init(adev); |
1011 | ||
4562236b HW |
1012 | return 0; |
1013 | } | |
1014 | ||
b8592b48 LL |
1015 | /** |
1016 | * dm_hw_fini() - Teardown DC device | |
1017 | * @handle: The base driver device containing the amdpgu_dm device. | |
1018 | * | |
1019 | * Teardown components within &struct amdgpu_display_manager that require | |
1020 | * cleanup. This involves cleaning up the DRM device, DC, and any modules that | |
1021 | * were loaded. Also flush IRQ workqueues and disable them. | |
1022 | */ | |
4562236b HW |
1023 | static int dm_hw_fini(void *handle) |
1024 | { | |
1025 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1026 | ||
1027 | amdgpu_dm_hpd_fini(adev); | |
1028 | ||
1029 | amdgpu_dm_irq_fini(adev); | |
21de3396 | 1030 | amdgpu_dm_fini(adev); |
4562236b HW |
1031 | return 0; |
1032 | } | |
1033 | ||
1034 | static int dm_suspend(void *handle) | |
1035 | { | |
1036 | struct amdgpu_device *adev = handle; | |
1037 | struct amdgpu_display_manager *dm = &adev->dm; | |
1038 | int ret = 0; | |
4562236b | 1039 | |
d2f0b53b LHM |
1040 | WARN_ON(adev->dm.cached_state); |
1041 | adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); | |
1042 | ||
4562236b HW |
1043 | s3_handle_mst(adev->ddev, true); |
1044 | ||
4562236b HW |
1045 | amdgpu_dm_irq_suspend(adev); |
1046 | ||
a3621485 | 1047 | |
32f5062d | 1048 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
4562236b HW |
1049 | |
1050 | return ret; | |
1051 | } | |
1052 | ||
1daf8c63 AD |
1053 | static struct amdgpu_dm_connector * |
1054 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, | |
1055 | struct drm_crtc *crtc) | |
4562236b HW |
1056 | { |
1057 | uint32_t i; | |
c2cea706 | 1058 | struct drm_connector_state *new_con_state; |
4562236b HW |
1059 | struct drm_connector *connector; |
1060 | struct drm_crtc *crtc_from_state; | |
1061 | ||
c2cea706 LSL |
1062 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
1063 | crtc_from_state = new_con_state->crtc; | |
4562236b HW |
1064 | |
1065 | if (crtc_from_state == crtc) | |
c84dec2f | 1066 | return to_amdgpu_dm_connector(connector); |
4562236b HW |
1067 | } |
1068 | ||
1069 | return NULL; | |
1070 | } | |
1071 | ||
fbbdadf2 BL |
1072 | static void emulated_link_detect(struct dc_link *link) |
1073 | { | |
1074 | struct dc_sink_init_data sink_init_data = { 0 }; | |
1075 | struct display_sink_capability sink_caps = { 0 }; | |
1076 | enum dc_edid_status edid_status; | |
1077 | struct dc_context *dc_ctx = link->ctx; | |
1078 | struct dc_sink *sink = NULL; | |
1079 | struct dc_sink *prev_sink = NULL; | |
1080 | ||
1081 | link->type = dc_connection_none; | |
1082 | prev_sink = link->local_sink; | |
1083 | ||
1084 | if (prev_sink != NULL) | |
1085 | dc_sink_retain(prev_sink); | |
1086 | ||
1087 | switch (link->connector_signal) { | |
1088 | case SIGNAL_TYPE_HDMI_TYPE_A: { | |
1089 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
1090 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; | |
1091 | break; | |
1092 | } | |
1093 | ||
1094 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { | |
1095 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
1096 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; | |
1097 | break; | |
1098 | } | |
1099 | ||
1100 | case SIGNAL_TYPE_DVI_DUAL_LINK: { | |
1101 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
1102 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; | |
1103 | break; | |
1104 | } | |
1105 | ||
1106 | case SIGNAL_TYPE_LVDS: { | |
1107 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
1108 | sink_caps.signal = SIGNAL_TYPE_LVDS; | |
1109 | break; | |
1110 | } | |
1111 | ||
1112 | case SIGNAL_TYPE_EDP: { | |
1113 | sink_caps.transaction_type = | |
1114 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
1115 | sink_caps.signal = SIGNAL_TYPE_EDP; | |
1116 | break; | |
1117 | } | |
1118 | ||
1119 | case SIGNAL_TYPE_DISPLAY_PORT: { | |
1120 | sink_caps.transaction_type = | |
1121 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
1122 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; | |
1123 | break; | |
1124 | } | |
1125 | ||
1126 | default: | |
1127 | DC_ERROR("Invalid connector type! signal:%d\n", | |
1128 | link->connector_signal); | |
1129 | return; | |
1130 | } | |
1131 | ||
1132 | sink_init_data.link = link; | |
1133 | sink_init_data.sink_signal = sink_caps.signal; | |
1134 | ||
1135 | sink = dc_sink_create(&sink_init_data); | |
1136 | if (!sink) { | |
1137 | DC_ERROR("Failed to create sink!\n"); | |
1138 | return; | |
1139 | } | |
1140 | ||
dcd5fb82 | 1141 | /* dc_sink_create returns a new reference */ |
fbbdadf2 BL |
1142 | link->local_sink = sink; |
1143 | ||
1144 | edid_status = dm_helpers_read_local_edid( | |
1145 | link->ctx, | |
1146 | link, | |
1147 | sink); | |
1148 | ||
1149 | if (edid_status != EDID_OK) | |
1150 | DC_ERROR("Failed to read EDID"); | |
1151 | ||
1152 | } | |
1153 | ||
4562236b HW |
1154 | static int dm_resume(void *handle) |
1155 | { | |
1156 | struct amdgpu_device *adev = handle; | |
4562236b HW |
1157 | struct drm_device *ddev = adev->ddev; |
1158 | struct amdgpu_display_manager *dm = &adev->dm; | |
c84dec2f | 1159 | struct amdgpu_dm_connector *aconnector; |
4562236b | 1160 | struct drm_connector *connector; |
4562236b | 1161 | struct drm_crtc *crtc; |
c2cea706 | 1162 | struct drm_crtc_state *new_crtc_state; |
fcb4019e LSL |
1163 | struct dm_crtc_state *dm_new_crtc_state; |
1164 | struct drm_plane *plane; | |
1165 | struct drm_plane_state *new_plane_state; | |
1166 | struct dm_plane_state *dm_new_plane_state; | |
113b7a01 | 1167 | struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); |
fbbdadf2 | 1168 | enum dc_connection_type new_connection_type = dc_connection_none; |
a3621485 | 1169 | int i; |
4562236b | 1170 | |
113b7a01 LL |
1171 | /* Recreate dc_state - DC invalidates it when setting power state to S3. */ |
1172 | dc_release_state(dm_state->context); | |
1173 | dm_state->context = dc_create_state(dm->dc); | |
1174 | /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ | |
1175 | dc_resource_state_construct(dm->dc, dm_state->context); | |
1176 | ||
a80aa93d ML |
1177 | /* power on hardware */ |
1178 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
1179 | ||
4562236b HW |
1180 | /* program HPD filter */ |
1181 | dc_resume(dm->dc); | |
1182 | ||
1183 | /* On resume we need to rewrite the MSTM control bits to enamble MST*/ | |
1184 | s3_handle_mst(ddev, false); | |
1185 | ||
1186 | /* | |
1187 | * early enable HPD Rx IRQ, should be done before set mode as short | |
1188 | * pulse interrupts are used for MST | |
1189 | */ | |
1190 | amdgpu_dm_irq_resume_early(adev); | |
1191 | ||
4562236b | 1192 | /* Do detection*/ |
a80aa93d | 1193 | list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { |
c84dec2f | 1194 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
1195 | |
1196 | /* | |
1197 | * this is the case when traversing through already created | |
1198 | * MST connectors, should be skipped | |
1199 | */ | |
1200 | if (aconnector->mst_port) | |
1201 | continue; | |
1202 | ||
03ea364c | 1203 | mutex_lock(&aconnector->hpd_lock); |
fbbdadf2 BL |
1204 | if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) |
1205 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
1206 | ||
1207 | if (aconnector->base.force && new_connection_type == dc_connection_none) | |
1208 | emulated_link_detect(aconnector->dc_link); | |
1209 | else | |
1210 | dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); | |
3eb4eba4 RL |
1211 | |
1212 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) | |
1213 | aconnector->fake_enable = false; | |
1214 | ||
dcd5fb82 MF |
1215 | if (aconnector->dc_sink) |
1216 | dc_sink_release(aconnector->dc_sink); | |
4562236b HW |
1217 | aconnector->dc_sink = NULL; |
1218 | amdgpu_dm_update_connector_after_detect(aconnector); | |
03ea364c | 1219 | mutex_unlock(&aconnector->hpd_lock); |
4562236b HW |
1220 | } |
1221 | ||
1f6010a9 | 1222 | /* Force mode set in atomic commit */ |
a80aa93d | 1223 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) |
c2cea706 | 1224 | new_crtc_state->active_changed = true; |
4f346e65 | 1225 | |
fcb4019e LSL |
1226 | /* |
1227 | * atomic_check is expected to create the dc states. We need to release | |
1228 | * them here, since they were duplicated as part of the suspend | |
1229 | * procedure. | |
1230 | */ | |
a80aa93d | 1231 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
fcb4019e LSL |
1232 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
1233 | if (dm_new_crtc_state->stream) { | |
1234 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); | |
1235 | dc_stream_release(dm_new_crtc_state->stream); | |
1236 | dm_new_crtc_state->stream = NULL; | |
1237 | } | |
1238 | } | |
1239 | ||
a80aa93d | 1240 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { |
fcb4019e LSL |
1241 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
1242 | if (dm_new_plane_state->dc_state) { | |
1243 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); | |
1244 | dc_plane_state_release(dm_new_plane_state->dc_state); | |
1245 | dm_new_plane_state->dc_state = NULL; | |
1246 | } | |
1247 | } | |
1248 | ||
2d1af6a1 | 1249 | drm_atomic_helper_resume(ddev, dm->cached_state); |
4562236b | 1250 | |
a80aa93d | 1251 | dm->cached_state = NULL; |
0a214e2f | 1252 | |
9faa4237 | 1253 | amdgpu_dm_irq_resume_late(adev); |
4562236b | 1254 | |
2d1af6a1 | 1255 | return 0; |
4562236b HW |
1256 | } |
1257 | ||
b8592b48 LL |
1258 | /** |
1259 | * DOC: DM Lifecycle | |
1260 | * | |
1261 | * DM (and consequently DC) is registered in the amdgpu base driver as a IP | |
1262 | * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to | |
1263 | * the base driver's device list to be initialized and torn down accordingly. | |
1264 | * | |
1265 | * The functions to do so are provided as hooks in &struct amd_ip_funcs. | |
1266 | */ | |
1267 | ||
4562236b HW |
1268 | static const struct amd_ip_funcs amdgpu_dm_funcs = { |
1269 | .name = "dm", | |
1270 | .early_init = dm_early_init, | |
7abcf6b5 | 1271 | .late_init = dm_late_init, |
4562236b HW |
1272 | .sw_init = dm_sw_init, |
1273 | .sw_fini = dm_sw_fini, | |
1274 | .hw_init = dm_hw_init, | |
1275 | .hw_fini = dm_hw_fini, | |
1276 | .suspend = dm_suspend, | |
1277 | .resume = dm_resume, | |
1278 | .is_idle = dm_is_idle, | |
1279 | .wait_for_idle = dm_wait_for_idle, | |
1280 | .check_soft_reset = dm_check_soft_reset, | |
1281 | .soft_reset = dm_soft_reset, | |
1282 | .set_clockgating_state = dm_set_clockgating_state, | |
1283 | .set_powergating_state = dm_set_powergating_state, | |
1284 | }; | |
1285 | ||
1286 | const struct amdgpu_ip_block_version dm_ip_block = | |
1287 | { | |
1288 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
1289 | .major = 1, | |
1290 | .minor = 0, | |
1291 | .rev = 0, | |
1292 | .funcs = &amdgpu_dm_funcs, | |
1293 | }; | |
1294 | ||
ca3268c4 | 1295 | |
b8592b48 LL |
1296 | /** |
1297 | * DOC: atomic | |
1298 | * | |
1299 | * *WIP* | |
1300 | */ | |
0a323b84 | 1301 | |
b3663f70 | 1302 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
4d4772f6 | 1303 | .fb_create = amdgpu_display_user_framebuffer_create, |
366c1baa | 1304 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
4562236b | 1305 | .atomic_check = amdgpu_dm_atomic_check, |
da5c47f6 | 1306 | .atomic_commit = amdgpu_dm_atomic_commit, |
54f5499a AG |
1307 | }; |
1308 | ||
1309 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { | |
1310 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail | |
4562236b HW |
1311 | }; |
1312 | ||
7578ecda | 1313 | static void |
3ee6b26b | 1314 | amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) |
4562236b HW |
1315 | { |
1316 | struct drm_connector *connector = &aconnector->base; | |
1317 | struct drm_device *dev = connector->dev; | |
b73a22d3 | 1318 | struct dc_sink *sink; |
4562236b HW |
1319 | |
1320 | /* MST handled by drm_mst framework */ | |
1321 | if (aconnector->mst_mgr.mst_state == true) | |
1322 | return; | |
1323 | ||
1324 | ||
1325 | sink = aconnector->dc_link->local_sink; | |
dcd5fb82 MF |
1326 | if (sink) |
1327 | dc_sink_retain(sink); | |
4562236b | 1328 | |
1f6010a9 DF |
1329 | /* |
1330 | * Edid mgmt connector gets first update only in mode_valid hook and then | |
4562236b | 1331 | * the connector sink is set to either fake or physical sink depends on link status. |
1f6010a9 | 1332 | * Skip if already done during boot. |
4562236b HW |
1333 | */ |
1334 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED | |
1335 | && aconnector->dc_em_sink) { | |
1336 | ||
1f6010a9 DF |
1337 | /* |
1338 | * For S3 resume with headless use eml_sink to fake stream | |
1339 | * because on resume connector->sink is set to NULL | |
4562236b HW |
1340 | */ |
1341 | mutex_lock(&dev->mode_config.mutex); | |
1342 | ||
1343 | if (sink) { | |
922aa1e1 | 1344 | if (aconnector->dc_sink) { |
98e6436d | 1345 | amdgpu_dm_update_freesync_caps(connector, NULL); |
1f6010a9 DF |
1346 | /* |
1347 | * retain and release below are used to | |
1348 | * bump up refcount for sink because the link doesn't point | |
1349 | * to it anymore after disconnect, so on next crtc to connector | |
922aa1e1 AG |
1350 | * reshuffle by UMD we will get into unwanted dc_sink release |
1351 | */ | |
dcd5fb82 | 1352 | dc_sink_release(aconnector->dc_sink); |
922aa1e1 | 1353 | } |
4562236b | 1354 | aconnector->dc_sink = sink; |
dcd5fb82 | 1355 | dc_sink_retain(aconnector->dc_sink); |
98e6436d AK |
1356 | amdgpu_dm_update_freesync_caps(connector, |
1357 | aconnector->edid); | |
4562236b | 1358 | } else { |
98e6436d | 1359 | amdgpu_dm_update_freesync_caps(connector, NULL); |
dcd5fb82 | 1360 | if (!aconnector->dc_sink) { |
4562236b | 1361 | aconnector->dc_sink = aconnector->dc_em_sink; |
922aa1e1 | 1362 | dc_sink_retain(aconnector->dc_sink); |
dcd5fb82 | 1363 | } |
4562236b HW |
1364 | } |
1365 | ||
1366 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 MF |
1367 | |
1368 | if (sink) | |
1369 | dc_sink_release(sink); | |
4562236b HW |
1370 | return; |
1371 | } | |
1372 | ||
1373 | /* | |
1374 | * TODO: temporary guard to look for proper fix | |
1375 | * if this sink is MST sink, we should not do anything | |
1376 | */ | |
dcd5fb82 MF |
1377 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { |
1378 | dc_sink_release(sink); | |
4562236b | 1379 | return; |
dcd5fb82 | 1380 | } |
4562236b HW |
1381 | |
1382 | if (aconnector->dc_sink == sink) { | |
1f6010a9 DF |
1383 | /* |
1384 | * We got a DP short pulse (Link Loss, DP CTS, etc...). | |
1385 | * Do nothing!! | |
1386 | */ | |
f1ad2f5e | 1387 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", |
4562236b | 1388 | aconnector->connector_id); |
dcd5fb82 MF |
1389 | if (sink) |
1390 | dc_sink_release(sink); | |
4562236b HW |
1391 | return; |
1392 | } | |
1393 | ||
f1ad2f5e | 1394 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", |
4562236b HW |
1395 | aconnector->connector_id, aconnector->dc_sink, sink); |
1396 | ||
1397 | mutex_lock(&dev->mode_config.mutex); | |
1398 | ||
1f6010a9 DF |
1399 | /* |
1400 | * 1. Update status of the drm connector | |
1401 | * 2. Send an event and let userspace tell us what to do | |
1402 | */ | |
4562236b | 1403 | if (sink) { |
1f6010a9 DF |
1404 | /* |
1405 | * TODO: check if we still need the S3 mode update workaround. | |
1406 | * If yes, put it here. | |
1407 | */ | |
4562236b | 1408 | if (aconnector->dc_sink) |
98e6436d | 1409 | amdgpu_dm_update_freesync_caps(connector, NULL); |
4562236b HW |
1410 | |
1411 | aconnector->dc_sink = sink; | |
dcd5fb82 | 1412 | dc_sink_retain(aconnector->dc_sink); |
900b3cb1 | 1413 | if (sink->dc_edid.length == 0) { |
4562236b | 1414 | aconnector->edid = NULL; |
e86e8947 | 1415 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
900b3cb1 | 1416 | } else { |
4562236b HW |
1417 | aconnector->edid = |
1418 | (struct edid *) sink->dc_edid.raw_edid; | |
1419 | ||
1420 | ||
c555f023 | 1421 | drm_connector_update_edid_property(connector, |
4562236b | 1422 | aconnector->edid); |
e86e8947 HV |
1423 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, |
1424 | aconnector->edid); | |
4562236b | 1425 | } |
98e6436d | 1426 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
4562236b HW |
1427 | |
1428 | } else { | |
e86e8947 | 1429 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
98e6436d | 1430 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c555f023 | 1431 | drm_connector_update_edid_property(connector, NULL); |
4562236b | 1432 | aconnector->num_modes = 0; |
dcd5fb82 | 1433 | dc_sink_release(aconnector->dc_sink); |
4562236b | 1434 | aconnector->dc_sink = NULL; |
5326c452 | 1435 | aconnector->edid = NULL; |
4562236b HW |
1436 | } |
1437 | ||
1438 | mutex_unlock(&dev->mode_config.mutex); | |
dcd5fb82 MF |
1439 | |
1440 | if (sink) | |
1441 | dc_sink_release(sink); | |
4562236b HW |
1442 | } |
1443 | ||
1444 | static void handle_hpd_irq(void *param) | |
1445 | { | |
c84dec2f | 1446 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
1447 | struct drm_connector *connector = &aconnector->base; |
1448 | struct drm_device *dev = connector->dev; | |
fbbdadf2 | 1449 | enum dc_connection_type new_connection_type = dc_connection_none; |
4562236b | 1450 | |
1f6010a9 DF |
1451 | /* |
1452 | * In case of failure or MST no need to update connector status or notify the OS | |
1453 | * since (for MST case) MST does this in its own context. | |
4562236b HW |
1454 | */ |
1455 | mutex_lock(&aconnector->hpd_lock); | |
2e0ac3d6 HW |
1456 | |
1457 | if (aconnector->fake_enable) | |
1458 | aconnector->fake_enable = false; | |
1459 | ||
fbbdadf2 BL |
1460 | if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) |
1461 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
1462 | ||
1463 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
1464 | emulated_link_detect(aconnector->dc_link); | |
1465 | ||
1466 | ||
1467 | drm_modeset_lock_all(dev); | |
1468 | dm_restore_drm_connector_state(dev, connector); | |
1469 | drm_modeset_unlock_all(dev); | |
1470 | ||
1471 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
1472 | drm_kms_helper_hotplug_event(dev); | |
1473 | ||
1474 | } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { | |
4562236b HW |
1475 | amdgpu_dm_update_connector_after_detect(aconnector); |
1476 | ||
1477 | ||
1478 | drm_modeset_lock_all(dev); | |
1479 | dm_restore_drm_connector_state(dev, connector); | |
1480 | drm_modeset_unlock_all(dev); | |
1481 | ||
1482 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
1483 | drm_kms_helper_hotplug_event(dev); | |
1484 | } | |
1485 | mutex_unlock(&aconnector->hpd_lock); | |
1486 | ||
1487 | } | |
1488 | ||
c84dec2f | 1489 | static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) |
4562236b HW |
1490 | { |
1491 | uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; | |
1492 | uint8_t dret; | |
1493 | bool new_irq_handled = false; | |
1494 | int dpcd_addr; | |
1495 | int dpcd_bytes_to_read; | |
1496 | ||
1497 | const int max_process_count = 30; | |
1498 | int process_count = 0; | |
1499 | ||
1500 | const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); | |
1501 | ||
1502 | if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { | |
1503 | dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; | |
1504 | /* DPCD 0x200 - 0x201 for downstream IRQ */ | |
1505 | dpcd_addr = DP_SINK_COUNT; | |
1506 | } else { | |
1507 | dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; | |
1508 | /* DPCD 0x2002 - 0x2005 for downstream IRQ */ | |
1509 | dpcd_addr = DP_SINK_COUNT_ESI; | |
1510 | } | |
1511 | ||
1512 | dret = drm_dp_dpcd_read( | |
1513 | &aconnector->dm_dp_aux.aux, | |
1514 | dpcd_addr, | |
1515 | esi, | |
1516 | dpcd_bytes_to_read); | |
1517 | ||
1518 | while (dret == dpcd_bytes_to_read && | |
1519 | process_count < max_process_count) { | |
1520 | uint8_t retry; | |
1521 | dret = 0; | |
1522 | ||
1523 | process_count++; | |
1524 | ||
f1ad2f5e | 1525 | DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
4562236b HW |
1526 | /* handle HPD short pulse irq */ |
1527 | if (aconnector->mst_mgr.mst_state) | |
1528 | drm_dp_mst_hpd_irq( | |
1529 | &aconnector->mst_mgr, | |
1530 | esi, | |
1531 | &new_irq_handled); | |
4562236b HW |
1532 | |
1533 | if (new_irq_handled) { | |
1534 | /* ACK at DPCD to notify down stream */ | |
1535 | const int ack_dpcd_bytes_to_write = | |
1536 | dpcd_bytes_to_read - 1; | |
1537 | ||
1538 | for (retry = 0; retry < 3; retry++) { | |
1539 | uint8_t wret; | |
1540 | ||
1541 | wret = drm_dp_dpcd_write( | |
1542 | &aconnector->dm_dp_aux.aux, | |
1543 | dpcd_addr + 1, | |
1544 | &esi[1], | |
1545 | ack_dpcd_bytes_to_write); | |
1546 | if (wret == ack_dpcd_bytes_to_write) | |
1547 | break; | |
1548 | } | |
1549 | ||
1f6010a9 | 1550 | /* check if there is new irq to be handled */ |
4562236b HW |
1551 | dret = drm_dp_dpcd_read( |
1552 | &aconnector->dm_dp_aux.aux, | |
1553 | dpcd_addr, | |
1554 | esi, | |
1555 | dpcd_bytes_to_read); | |
1556 | ||
1557 | new_irq_handled = false; | |
d4a6e8a9 | 1558 | } else { |
4562236b | 1559 | break; |
d4a6e8a9 | 1560 | } |
4562236b HW |
1561 | } |
1562 | ||
1563 | if (process_count == max_process_count) | |
f1ad2f5e | 1564 | DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); |
4562236b HW |
1565 | } |
1566 | ||
1567 | static void handle_hpd_rx_irq(void *param) | |
1568 | { | |
c84dec2f | 1569 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
1570 | struct drm_connector *connector = &aconnector->base; |
1571 | struct drm_device *dev = connector->dev; | |
53cbf65c | 1572 | struct dc_link *dc_link = aconnector->dc_link; |
4562236b | 1573 | bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
fbbdadf2 | 1574 | enum dc_connection_type new_connection_type = dc_connection_none; |
4562236b | 1575 | |
1f6010a9 DF |
1576 | /* |
1577 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio | |
4562236b HW |
1578 | * conflict, after implement i2c helper, this mutex should be |
1579 | * retired. | |
1580 | */ | |
53cbf65c | 1581 | if (dc_link->type != dc_connection_mst_branch) |
4562236b HW |
1582 | mutex_lock(&aconnector->hpd_lock); |
1583 | ||
4e18814e | 1584 | if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && |
4562236b HW |
1585 | !is_mst_root_connector) { |
1586 | /* Downstream Port status changed. */ | |
fbbdadf2 BL |
1587 | if (!dc_link_detect_sink(dc_link, &new_connection_type)) |
1588 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
1589 | ||
1590 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
1591 | emulated_link_detect(dc_link); | |
1592 | ||
1593 | if (aconnector->fake_enable) | |
1594 | aconnector->fake_enable = false; | |
1595 | ||
1596 | amdgpu_dm_update_connector_after_detect(aconnector); | |
1597 | ||
1598 | ||
1599 | drm_modeset_lock_all(dev); | |
1600 | dm_restore_drm_connector_state(dev, connector); | |
1601 | drm_modeset_unlock_all(dev); | |
1602 | ||
1603 | drm_kms_helper_hotplug_event(dev); | |
1604 | } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { | |
88ac3dda RL |
1605 | |
1606 | if (aconnector->fake_enable) | |
1607 | aconnector->fake_enable = false; | |
1608 | ||
4562236b HW |
1609 | amdgpu_dm_update_connector_after_detect(aconnector); |
1610 | ||
1611 | ||
1612 | drm_modeset_lock_all(dev); | |
1613 | dm_restore_drm_connector_state(dev, connector); | |
1614 | drm_modeset_unlock_all(dev); | |
1615 | ||
1616 | drm_kms_helper_hotplug_event(dev); | |
1617 | } | |
1618 | } | |
1619 | if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || | |
53cbf65c | 1620 | (dc_link->type == dc_connection_mst_branch)) |
4562236b HW |
1621 | dm_handle_hpd_rx_irq(aconnector); |
1622 | ||
e86e8947 HV |
1623 | if (dc_link->type != dc_connection_mst_branch) { |
1624 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); | |
4562236b | 1625 | mutex_unlock(&aconnector->hpd_lock); |
e86e8947 | 1626 | } |
4562236b HW |
1627 | } |
1628 | ||
1629 | static void register_hpd_handlers(struct amdgpu_device *adev) | |
1630 | { | |
1631 | struct drm_device *dev = adev->ddev; | |
1632 | struct drm_connector *connector; | |
c84dec2f | 1633 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
1634 | const struct dc_link *dc_link; |
1635 | struct dc_interrupt_params int_params = {0}; | |
1636 | ||
1637 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1638 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1639 | ||
1640 | list_for_each_entry(connector, | |
1641 | &dev->mode_config.connector_list, head) { | |
1642 | ||
c84dec2f | 1643 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
1644 | dc_link = aconnector->dc_link; |
1645 | ||
1646 | if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { | |
1647 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
1648 | int_params.irq_source = dc_link->irq_source_hpd; | |
1649 | ||
1650 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1651 | handle_hpd_irq, | |
1652 | (void *) aconnector); | |
1653 | } | |
1654 | ||
1655 | if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { | |
1656 | ||
1657 | /* Also register for DP short pulse (hpd_rx). */ | |
1658 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
1659 | int_params.irq_source = dc_link->irq_source_hpd_rx; | |
1660 | ||
1661 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1662 | handle_hpd_rx_irq, | |
1663 | (void *) aconnector); | |
1664 | } | |
1665 | } | |
1666 | } | |
1667 | ||
1668 | /* Register IRQ sources and initialize IRQ callbacks */ | |
1669 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) | |
1670 | { | |
1671 | struct dc *dc = adev->dm.dc; | |
1672 | struct common_irq_params *c_irq_params; | |
1673 | struct dc_interrupt_params int_params = {0}; | |
1674 | int r; | |
1675 | int i; | |
1ffdeca6 | 1676 | unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
2c8ad2d5 | 1677 | |
84374725 | 1678 | if (adev->asic_type >= CHIP_VEGA10) |
3760f76c | 1679 | client_id = SOC15_IH_CLIENTID_DCE; |
4562236b HW |
1680 | |
1681 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1682 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1683 | ||
1f6010a9 DF |
1684 | /* |
1685 | * Actions of amdgpu_irq_add_id(): | |
4562236b HW |
1686 | * 1. Register a set() function with base driver. |
1687 | * Base driver will call set() function to enable/disable an | |
1688 | * interrupt in DC hardware. | |
1689 | * 2. Register amdgpu_dm_irq_handler(). | |
1690 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
1691 | * coming from DC hardware. | |
1692 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
1693 | * for acknowledging and handling. */ | |
1694 | ||
b57de80a | 1695 | /* Use VBLANK interrupt */ |
e9029155 | 1696 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { |
2c8ad2d5 | 1697 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
4562236b HW |
1698 | if (r) { |
1699 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
1700 | return r; | |
1701 | } | |
1702 | ||
1703 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1704 | int_params.irq_source = | |
3d761e79 | 1705 | dc_interrupt_to_irq_source(dc, i, 0); |
4562236b | 1706 | |
b57de80a | 1707 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
4562236b HW |
1708 | |
1709 | c_irq_params->adev = adev; | |
1710 | c_irq_params->irq_src = int_params.irq_source; | |
1711 | ||
1712 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1713 | dm_crtc_high_irq, c_irq_params); | |
1714 | } | |
1715 | ||
d2574c33 MK |
1716 | /* Use VUPDATE interrupt */ |
1717 | for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { | |
1718 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); | |
1719 | if (r) { | |
1720 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
1721 | return r; | |
1722 | } | |
1723 | ||
1724 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1725 | int_params.irq_source = | |
1726 | dc_interrupt_to_irq_source(dc, i, 0); | |
1727 | ||
1728 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
1729 | ||
1730 | c_irq_params->adev = adev; | |
1731 | c_irq_params->irq_src = int_params.irq_source; | |
1732 | ||
1733 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1734 | dm_vupdate_high_irq, c_irq_params); | |
1735 | } | |
1736 | ||
3d761e79 | 1737 | /* Use GRPH_PFLIP interrupt */ |
4562236b HW |
1738 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
1739 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
2c8ad2d5 | 1740 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
4562236b HW |
1741 | if (r) { |
1742 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
1743 | return r; | |
1744 | } | |
1745 | ||
1746 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1747 | int_params.irq_source = | |
1748 | dc_interrupt_to_irq_source(dc, i, 0); | |
1749 | ||
1750 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
1751 | ||
1752 | c_irq_params->adev = adev; | |
1753 | c_irq_params->irq_src = int_params.irq_source; | |
1754 | ||
1755 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1756 | dm_pflip_high_irq, c_irq_params); | |
1757 | ||
1758 | } | |
1759 | ||
1760 | /* HPD */ | |
2c8ad2d5 AD |
1761 | r = amdgpu_irq_add_id(adev, client_id, |
1762 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
4562236b HW |
1763 | if (r) { |
1764 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
1765 | return r; | |
1766 | } | |
1767 | ||
1768 | register_hpd_handlers(adev); | |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
ff5ef992 AD |
1773 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1774 | /* Register IRQ sources and initialize IRQ callbacks */ | |
1775 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) | |
1776 | { | |
1777 | struct dc *dc = adev->dm.dc; | |
1778 | struct common_irq_params *c_irq_params; | |
1779 | struct dc_interrupt_params int_params = {0}; | |
1780 | int r; | |
1781 | int i; | |
1782 | ||
1783 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1784 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1785 | ||
1f6010a9 DF |
1786 | /* |
1787 | * Actions of amdgpu_irq_add_id(): | |
ff5ef992 AD |
1788 | * 1. Register a set() function with base driver. |
1789 | * Base driver will call set() function to enable/disable an | |
1790 | * interrupt in DC hardware. | |
1791 | * 2. Register amdgpu_dm_irq_handler(). | |
1792 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
1793 | * coming from DC hardware. | |
1794 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
1795 | * for acknowledging and handling. | |
1f6010a9 | 1796 | */ |
ff5ef992 AD |
1797 | |
1798 | /* Use VSTARTUP interrupt */ | |
1799 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; | |
1800 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; | |
1801 | i++) { | |
3760f76c | 1802 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
ff5ef992 AD |
1803 | |
1804 | if (r) { | |
1805 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
1806 | return r; | |
1807 | } | |
1808 | ||
1809 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1810 | int_params.irq_source = | |
1811 | dc_interrupt_to_irq_source(dc, i, 0); | |
1812 | ||
1813 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
1814 | ||
1815 | c_irq_params->adev = adev; | |
1816 | c_irq_params->irq_src = int_params.irq_source; | |
1817 | ||
1818 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1819 | dm_crtc_high_irq, c_irq_params); | |
1820 | } | |
1821 | ||
d2574c33 MK |
1822 | /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to |
1823 | * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx | |
1824 | * to trigger at end of each vblank, regardless of state of the lock, | |
1825 | * matching DCE behaviour. | |
1826 | */ | |
1827 | for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; | |
1828 | i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; | |
1829 | i++) { | |
1830 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); | |
1831 | ||
1832 | if (r) { | |
1833 | DRM_ERROR("Failed to add vupdate irq id!\n"); | |
1834 | return r; | |
1835 | } | |
1836 | ||
1837 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1838 | int_params.irq_source = | |
1839 | dc_interrupt_to_irq_source(dc, i, 0); | |
1840 | ||
1841 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; | |
1842 | ||
1843 | c_irq_params->adev = adev; | |
1844 | c_irq_params->irq_src = int_params.irq_source; | |
1845 | ||
1846 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1847 | dm_vupdate_high_irq, c_irq_params); | |
1848 | } | |
1849 | ||
ff5ef992 AD |
1850 | /* Use GRPH_PFLIP interrupt */ |
1851 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; | |
1852 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; | |
1853 | i++) { | |
3760f76c | 1854 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
ff5ef992 AD |
1855 | if (r) { |
1856 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
1857 | return r; | |
1858 | } | |
1859 | ||
1860 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1861 | int_params.irq_source = | |
1862 | dc_interrupt_to_irq_source(dc, i, 0); | |
1863 | ||
1864 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
1865 | ||
1866 | c_irq_params->adev = adev; | |
1867 | c_irq_params->irq_src = int_params.irq_source; | |
1868 | ||
1869 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1870 | dm_pflip_high_irq, c_irq_params); | |
1871 | ||
1872 | } | |
1873 | ||
1874 | /* HPD */ | |
3760f76c | 1875 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, |
ff5ef992 AD |
1876 | &adev->hpd_irq); |
1877 | if (r) { | |
1878 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
1879 | return r; | |
1880 | } | |
1881 | ||
1882 | register_hpd_handlers(adev); | |
1883 | ||
1884 | return 0; | |
1885 | } | |
1886 | #endif | |
1887 | ||
eb3dc897 NK |
1888 | /* |
1889 | * Acquires the lock for the atomic state object and returns | |
1890 | * the new atomic state. | |
1891 | * | |
1892 | * This should only be called during atomic check. | |
1893 | */ | |
1894 | static int dm_atomic_get_state(struct drm_atomic_state *state, | |
1895 | struct dm_atomic_state **dm_state) | |
1896 | { | |
1897 | struct drm_device *dev = state->dev; | |
1898 | struct amdgpu_device *adev = dev->dev_private; | |
1899 | struct amdgpu_display_manager *dm = &adev->dm; | |
1900 | struct drm_private_state *priv_state; | |
eb3dc897 NK |
1901 | |
1902 | if (*dm_state) | |
1903 | return 0; | |
1904 | ||
eb3dc897 NK |
1905 | priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); |
1906 | if (IS_ERR(priv_state)) | |
1907 | return PTR_ERR(priv_state); | |
1908 | ||
1909 | *dm_state = to_dm_atomic_state(priv_state); | |
1910 | ||
1911 | return 0; | |
1912 | } | |
1913 | ||
1914 | struct dm_atomic_state * | |
1915 | dm_atomic_get_new_state(struct drm_atomic_state *state) | |
1916 | { | |
1917 | struct drm_device *dev = state->dev; | |
1918 | struct amdgpu_device *adev = dev->dev_private; | |
1919 | struct amdgpu_display_manager *dm = &adev->dm; | |
1920 | struct drm_private_obj *obj; | |
1921 | struct drm_private_state *new_obj_state; | |
1922 | int i; | |
1923 | ||
1924 | for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { | |
1925 | if (obj->funcs == dm->atomic_obj.funcs) | |
1926 | return to_dm_atomic_state(new_obj_state); | |
1927 | } | |
1928 | ||
1929 | return NULL; | |
1930 | } | |
1931 | ||
1932 | struct dm_atomic_state * | |
1933 | dm_atomic_get_old_state(struct drm_atomic_state *state) | |
1934 | { | |
1935 | struct drm_device *dev = state->dev; | |
1936 | struct amdgpu_device *adev = dev->dev_private; | |
1937 | struct amdgpu_display_manager *dm = &adev->dm; | |
1938 | struct drm_private_obj *obj; | |
1939 | struct drm_private_state *old_obj_state; | |
1940 | int i; | |
1941 | ||
1942 | for_each_old_private_obj_in_state(state, obj, old_obj_state, i) { | |
1943 | if (obj->funcs == dm->atomic_obj.funcs) | |
1944 | return to_dm_atomic_state(old_obj_state); | |
1945 | } | |
1946 | ||
1947 | return NULL; | |
1948 | } | |
1949 | ||
1950 | static struct drm_private_state * | |
1951 | dm_atomic_duplicate_state(struct drm_private_obj *obj) | |
1952 | { | |
1953 | struct dm_atomic_state *old_state, *new_state; | |
1954 | ||
1955 | new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); | |
1956 | if (!new_state) | |
1957 | return NULL; | |
1958 | ||
1959 | __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); | |
1960 | ||
813d20dc AW |
1961 | old_state = to_dm_atomic_state(obj->state); |
1962 | ||
1963 | if (old_state && old_state->context) | |
1964 | new_state->context = dc_copy_state(old_state->context); | |
1965 | ||
eb3dc897 NK |
1966 | if (!new_state->context) { |
1967 | kfree(new_state); | |
1968 | return NULL; | |
1969 | } | |
1970 | ||
eb3dc897 NK |
1971 | return &new_state->base; |
1972 | } | |
1973 | ||
1974 | static void dm_atomic_destroy_state(struct drm_private_obj *obj, | |
1975 | struct drm_private_state *state) | |
1976 | { | |
1977 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
1978 | ||
1979 | if (dm_state && dm_state->context) | |
1980 | dc_release_state(dm_state->context); | |
1981 | ||
1982 | kfree(dm_state); | |
1983 | } | |
1984 | ||
1985 | static struct drm_private_state_funcs dm_atomic_state_funcs = { | |
1986 | .atomic_duplicate_state = dm_atomic_duplicate_state, | |
1987 | .atomic_destroy_state = dm_atomic_destroy_state, | |
1988 | }; | |
1989 | ||
4562236b HW |
1990 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
1991 | { | |
eb3dc897 | 1992 | struct dm_atomic_state *state; |
4562236b HW |
1993 | int r; |
1994 | ||
1995 | adev->mode_info.mode_config_initialized = true; | |
1996 | ||
4562236b | 1997 | adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
54f5499a | 1998 | adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; |
4562236b HW |
1999 | |
2000 | adev->ddev->mode_config.max_width = 16384; | |
2001 | adev->ddev->mode_config.max_height = 16384; | |
2002 | ||
2003 | adev->ddev->mode_config.preferred_depth = 24; | |
2004 | adev->ddev->mode_config.prefer_shadow = 1; | |
1f6010a9 | 2005 | /* indicates support for immediate flip */ |
4562236b HW |
2006 | adev->ddev->mode_config.async_page_flip = true; |
2007 | ||
770d13b1 | 2008 | adev->ddev->mode_config.fb_base = adev->gmc.aper_base; |
4562236b | 2009 | |
eb3dc897 NK |
2010 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
2011 | if (!state) | |
2012 | return -ENOMEM; | |
2013 | ||
813d20dc | 2014 | state->context = dc_create_state(adev->dm.dc); |
eb3dc897 NK |
2015 | if (!state->context) { |
2016 | kfree(state); | |
2017 | return -ENOMEM; | |
2018 | } | |
2019 | ||
2020 | dc_resource_state_copy_construct_current(adev->dm.dc, state->context); | |
2021 | ||
8c1a765b DA |
2022 | drm_atomic_private_obj_init(adev->ddev, |
2023 | &adev->dm.atomic_obj, | |
eb3dc897 NK |
2024 | &state->base, |
2025 | &dm_atomic_state_funcs); | |
2026 | ||
3dc9b1ce | 2027 | r = amdgpu_display_modeset_create_props(adev); |
4562236b HW |
2028 | if (r) |
2029 | return r; | |
2030 | ||
6ce8f316 NK |
2031 | r = amdgpu_dm_audio_init(adev); |
2032 | if (r) | |
2033 | return r; | |
2034 | ||
4562236b HW |
2035 | return 0; |
2036 | } | |
2037 | ||
206bbafe DF |
2038 | #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 |
2039 | #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 | |
2040 | ||
4562236b HW |
2041 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ |
2042 | defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) | |
2043 | ||
206bbafe DF |
2044 | static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) |
2045 | { | |
2046 | #if defined(CONFIG_ACPI) | |
2047 | struct amdgpu_dm_backlight_caps caps; | |
2048 | ||
2049 | if (dm->backlight_caps.caps_valid) | |
2050 | return; | |
2051 | ||
2052 | amdgpu_acpi_get_backlight_caps(dm->adev, &caps); | |
2053 | if (caps.caps_valid) { | |
2054 | dm->backlight_caps.min_input_signal = caps.min_input_signal; | |
2055 | dm->backlight_caps.max_input_signal = caps.max_input_signal; | |
2056 | dm->backlight_caps.caps_valid = true; | |
2057 | } else { | |
2058 | dm->backlight_caps.min_input_signal = | |
2059 | AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; | |
2060 | dm->backlight_caps.max_input_signal = | |
2061 | AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; | |
2062 | } | |
2063 | #else | |
8bcbc9ef DF |
2064 | dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; |
2065 | dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; | |
206bbafe DF |
2066 | #endif |
2067 | } | |
2068 | ||
4562236b HW |
2069 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) |
2070 | { | |
2071 | struct amdgpu_display_manager *dm = bl_get_data(bd); | |
206bbafe DF |
2072 | struct amdgpu_dm_backlight_caps caps; |
2073 | uint32_t brightness = bd->props.brightness; | |
4562236b | 2074 | |
206bbafe DF |
2075 | amdgpu_dm_update_backlight_caps(dm); |
2076 | caps = dm->backlight_caps; | |
0cafc82f | 2077 | /* |
206bbafe DF |
2078 | * The brightness input is in the range 0-255 |
2079 | * It needs to be rescaled to be between the | |
2080 | * requested min and max input signal | |
2081 | * | |
2082 | * It also needs to be scaled up by 0x101 to | |
2083 | * match the DC interface which has a range of | |
2084 | * 0 to 0xffff | |
0cafc82f | 2085 | */ |
206bbafe DF |
2086 | brightness = |
2087 | brightness | |
2088 | * 0x101 | |
2089 | * (caps.max_input_signal - caps.min_input_signal) | |
2090 | / AMDGPU_MAX_BL_LEVEL | |
2091 | + caps.min_input_signal * 0x101; | |
4562236b HW |
2092 | |
2093 | if (dc_link_set_backlight_level(dm->backlight_link, | |
923fe495 | 2094 | brightness, 0)) |
4562236b HW |
2095 | return 0; |
2096 | else | |
2097 | return 1; | |
2098 | } | |
2099 | ||
2100 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) | |
2101 | { | |
620a0d27 DF |
2102 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
2103 | int ret = dc_link_get_backlight_level(dm->backlight_link); | |
2104 | ||
2105 | if (ret == DC_ERROR_UNEXPECTED) | |
2106 | return bd->props.brightness; | |
2107 | return ret; | |
4562236b HW |
2108 | } |
2109 | ||
2110 | static const struct backlight_ops amdgpu_dm_backlight_ops = { | |
2111 | .get_brightness = amdgpu_dm_backlight_get_brightness, | |
2112 | .update_status = amdgpu_dm_backlight_update_status, | |
2113 | }; | |
2114 | ||
7578ecda AD |
2115 | static void |
2116 | amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) | |
4562236b HW |
2117 | { |
2118 | char bl_name[16]; | |
2119 | struct backlight_properties props = { 0 }; | |
2120 | ||
206bbafe DF |
2121 | amdgpu_dm_update_backlight_caps(dm); |
2122 | ||
4562236b | 2123 | props.max_brightness = AMDGPU_MAX_BL_LEVEL; |
53a53f86 | 2124 | props.brightness = AMDGPU_MAX_BL_LEVEL; |
4562236b HW |
2125 | props.type = BACKLIGHT_RAW; |
2126 | ||
2127 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", | |
2128 | dm->adev->ddev->primary->index); | |
2129 | ||
2130 | dm->backlight_dev = backlight_device_register(bl_name, | |
2131 | dm->adev->ddev->dev, | |
2132 | dm, | |
2133 | &amdgpu_dm_backlight_ops, | |
2134 | &props); | |
2135 | ||
74baea42 | 2136 | if (IS_ERR(dm->backlight_dev)) |
4562236b HW |
2137 | DRM_ERROR("DM: Backlight registration failed!\n"); |
2138 | else | |
f1ad2f5e | 2139 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); |
4562236b HW |
2140 | } |
2141 | ||
2142 | #endif | |
2143 | ||
df534fff | 2144 | static int initialize_plane(struct amdgpu_display_manager *dm, |
b2fddb13 | 2145 | struct amdgpu_mode_info *mode_info, int plane_id, |
cc1fec57 NK |
2146 | enum drm_plane_type plane_type, |
2147 | const struct dc_plane_cap *plane_cap) | |
df534fff | 2148 | { |
f180b4bc | 2149 | struct drm_plane *plane; |
df534fff S |
2150 | unsigned long possible_crtcs; |
2151 | int ret = 0; | |
2152 | ||
f180b4bc | 2153 | plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); |
df534fff S |
2154 | if (!plane) { |
2155 | DRM_ERROR("KMS: Failed to allocate plane\n"); | |
2156 | return -ENOMEM; | |
2157 | } | |
b2fddb13 | 2158 | plane->type = plane_type; |
df534fff S |
2159 | |
2160 | /* | |
b2fddb13 NK |
2161 | * HACK: IGT tests expect that the primary plane for a CRTC |
2162 | * can only have one possible CRTC. Only expose support for | |
2163 | * any CRTC if they're not going to be used as a primary plane | |
2164 | * for a CRTC - like overlay or underlay planes. | |
df534fff S |
2165 | */ |
2166 | possible_crtcs = 1 << plane_id; | |
2167 | if (plane_id >= dm->dc->caps.max_streams) | |
2168 | possible_crtcs = 0xff; | |
2169 | ||
cc1fec57 | 2170 | ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); |
df534fff S |
2171 | |
2172 | if (ret) { | |
2173 | DRM_ERROR("KMS: Failed to initialize plane\n"); | |
54087768 | 2174 | kfree(plane); |
df534fff S |
2175 | return ret; |
2176 | } | |
2177 | ||
54087768 NK |
2178 | if (mode_info) |
2179 | mode_info->planes[plane_id] = plane; | |
2180 | ||
df534fff S |
2181 | return ret; |
2182 | } | |
2183 | ||
89fc8d4e HW |
2184 | |
2185 | static void register_backlight_device(struct amdgpu_display_manager *dm, | |
2186 | struct dc_link *link) | |
2187 | { | |
2188 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ | |
2189 | defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) | |
2190 | ||
2191 | if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && | |
2192 | link->type != dc_connection_none) { | |
1f6010a9 DF |
2193 | /* |
2194 | * Event if registration failed, we should continue with | |
89fc8d4e HW |
2195 | * DM initialization because not having a backlight control |
2196 | * is better then a black screen. | |
2197 | */ | |
2198 | amdgpu_dm_register_backlight_device(dm); | |
2199 | ||
2200 | if (dm->backlight_dev) | |
2201 | dm->backlight_link = link; | |
2202 | } | |
2203 | #endif | |
2204 | } | |
2205 | ||
2206 | ||
1f6010a9 DF |
2207 | /* |
2208 | * In this architecture, the association | |
4562236b HW |
2209 | * connector -> encoder -> crtc |
2210 | * id not really requried. The crtc and connector will hold the | |
2211 | * display_index as an abstraction to use with DAL component | |
2212 | * | |
2213 | * Returns 0 on success | |
2214 | */ | |
7578ecda | 2215 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
4562236b HW |
2216 | { |
2217 | struct amdgpu_display_manager *dm = &adev->dm; | |
df534fff | 2218 | int32_t i; |
c84dec2f | 2219 | struct amdgpu_dm_connector *aconnector = NULL; |
f2a0f5e6 | 2220 | struct amdgpu_encoder *aencoder = NULL; |
d4e13b0d | 2221 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
4562236b | 2222 | uint32_t link_cnt; |
cc1fec57 | 2223 | int32_t primary_planes; |
fbbdadf2 | 2224 | enum dc_connection_type new_connection_type = dc_connection_none; |
cc1fec57 | 2225 | const struct dc_plane_cap *plane; |
4562236b HW |
2226 | |
2227 | link_cnt = dm->dc->caps.max_links; | |
4562236b HW |
2228 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
2229 | DRM_ERROR("DM: Failed to initialize mode config\n"); | |
59d0f396 | 2230 | return -EINVAL; |
4562236b HW |
2231 | } |
2232 | ||
b2fddb13 NK |
2233 | /* There is one primary plane per CRTC */ |
2234 | primary_planes = dm->dc->caps.max_streams; | |
54087768 | 2235 | ASSERT(primary_planes <= AMDGPU_MAX_PLANES); |
efa6a8b7 | 2236 | |
b2fddb13 NK |
2237 | /* |
2238 | * Initialize primary planes, implicit planes for legacy IOCTLS. | |
2239 | * Order is reversed to match iteration order in atomic check. | |
2240 | */ | |
2241 | for (i = (primary_planes - 1); i >= 0; i--) { | |
cc1fec57 NK |
2242 | plane = &dm->dc->caps.planes[i]; |
2243 | ||
b2fddb13 | 2244 | if (initialize_plane(dm, mode_info, i, |
cc1fec57 | 2245 | DRM_PLANE_TYPE_PRIMARY, plane)) { |
df534fff | 2246 | DRM_ERROR("KMS: Failed to initialize primary plane\n"); |
cd8a2ae8 | 2247 | goto fail; |
d4e13b0d | 2248 | } |
df534fff | 2249 | } |
92f3ac40 | 2250 | |
0d579c7e NK |
2251 | /* |
2252 | * Initialize overlay planes, index starting after primary planes. | |
2253 | * These planes have a higher DRM index than the primary planes since | |
2254 | * they should be considered as having a higher z-order. | |
2255 | * Order is reversed to match iteration order in atomic check. | |
cc1fec57 NK |
2256 | * |
2257 | * Only support DCN for now, and only expose one so we don't encourage | |
2258 | * userspace to use up all the pipes. | |
0d579c7e | 2259 | */ |
cc1fec57 NK |
2260 | for (i = 0; i < dm->dc->caps.max_planes; ++i) { |
2261 | struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; | |
2262 | ||
2263 | if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) | |
2264 | continue; | |
2265 | ||
2266 | if (!plane->blends_with_above || !plane->blends_with_below) | |
2267 | continue; | |
2268 | ||
ea36ad34 | 2269 | if (!plane->pixel_format_support.argb8888) |
cc1fec57 NK |
2270 | continue; |
2271 | ||
54087768 | 2272 | if (initialize_plane(dm, NULL, primary_planes + i, |
cc1fec57 | 2273 | DRM_PLANE_TYPE_OVERLAY, plane)) { |
0d579c7e | 2274 | DRM_ERROR("KMS: Failed to initialize overlay plane\n"); |
cd8a2ae8 | 2275 | goto fail; |
d4e13b0d | 2276 | } |
cc1fec57 NK |
2277 | |
2278 | /* Only create one overlay plane. */ | |
2279 | break; | |
d4e13b0d | 2280 | } |
4562236b | 2281 | |
d4e13b0d | 2282 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
f180b4bc | 2283 | if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { |
4562236b | 2284 | DRM_ERROR("KMS: Failed to initialize crtc\n"); |
cd8a2ae8 | 2285 | goto fail; |
4562236b | 2286 | } |
4562236b | 2287 | |
ab2541b6 | 2288 | dm->display_indexes_num = dm->dc->caps.max_streams; |
4562236b HW |
2289 | |
2290 | /* loops over all connectors on the board */ | |
2291 | for (i = 0; i < link_cnt; i++) { | |
89fc8d4e | 2292 | struct dc_link *link = NULL; |
4562236b HW |
2293 | |
2294 | if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { | |
2295 | DRM_ERROR( | |
2296 | "KMS: Cannot support more than %d display indexes\n", | |
2297 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
2298 | continue; | |
2299 | } | |
2300 | ||
2301 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); | |
2302 | if (!aconnector) | |
cd8a2ae8 | 2303 | goto fail; |
4562236b HW |
2304 | |
2305 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); | |
8440c304 | 2306 | if (!aencoder) |
cd8a2ae8 | 2307 | goto fail; |
4562236b HW |
2308 | |
2309 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { | |
2310 | DRM_ERROR("KMS: Failed to initialize encoder\n"); | |
cd8a2ae8 | 2311 | goto fail; |
4562236b HW |
2312 | } |
2313 | ||
2314 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { | |
2315 | DRM_ERROR("KMS: Failed to initialize connector\n"); | |
cd8a2ae8 | 2316 | goto fail; |
4562236b HW |
2317 | } |
2318 | ||
89fc8d4e HW |
2319 | link = dc_get_link_at_index(dm->dc, i); |
2320 | ||
fbbdadf2 BL |
2321 | if (!dc_link_detect_sink(link, &new_connection_type)) |
2322 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
2323 | ||
2324 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
2325 | emulated_link_detect(link); | |
2326 | amdgpu_dm_update_connector_after_detect(aconnector); | |
2327 | ||
2328 | } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { | |
4562236b | 2329 | amdgpu_dm_update_connector_after_detect(aconnector); |
89fc8d4e HW |
2330 | register_backlight_device(dm, link); |
2331 | } | |
2332 | ||
2333 | ||
4562236b HW |
2334 | } |
2335 | ||
2336 | /* Software is initialized. Now we can register interrupt handlers. */ | |
2337 | switch (adev->asic_type) { | |
2338 | case CHIP_BONAIRE: | |
2339 | case CHIP_HAWAII: | |
cd4b356f AD |
2340 | case CHIP_KAVERI: |
2341 | case CHIP_KABINI: | |
2342 | case CHIP_MULLINS: | |
4562236b HW |
2343 | case CHIP_TONGA: |
2344 | case CHIP_FIJI: | |
2345 | case CHIP_CARRIZO: | |
2346 | case CHIP_STONEY: | |
2347 | case CHIP_POLARIS11: | |
2348 | case CHIP_POLARIS10: | |
b264d345 | 2349 | case CHIP_POLARIS12: |
7737de91 | 2350 | case CHIP_VEGAM: |
2c8ad2d5 | 2351 | case CHIP_VEGA10: |
2325ff30 | 2352 | case CHIP_VEGA12: |
1fe6bf2f | 2353 | case CHIP_VEGA20: |
4562236b HW |
2354 | if (dce110_register_irq_handlers(dm->adev)) { |
2355 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 2356 | goto fail; |
4562236b HW |
2357 | } |
2358 | break; | |
ff5ef992 AD |
2359 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
2360 | case CHIP_RAVEN: | |
476e955d HW |
2361 | #if defined(CONFIG_DRM_AMD_DC_DCN2_0) |
2362 | case CHIP_NAVI10: | |
fce651e3 | 2363 | case CHIP_NAVI14: |
476e955d | 2364 | #endif |
ff5ef992 AD |
2365 | if (dcn10_register_irq_handlers(dm->adev)) { |
2366 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 2367 | goto fail; |
ff5ef992 AD |
2368 | } |
2369 | break; | |
2370 | #endif | |
4562236b | 2371 | default: |
e63f8673 | 2372 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
cd8a2ae8 | 2373 | goto fail; |
4562236b HW |
2374 | } |
2375 | ||
1bc460a4 HW |
2376 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
2377 | dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; | |
2378 | ||
4562236b | 2379 | return 0; |
cd8a2ae8 | 2380 | fail: |
4562236b | 2381 | kfree(aencoder); |
4562236b | 2382 | kfree(aconnector); |
54087768 | 2383 | |
59d0f396 | 2384 | return -EINVAL; |
4562236b HW |
2385 | } |
2386 | ||
7578ecda | 2387 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
4562236b HW |
2388 | { |
2389 | drm_mode_config_cleanup(dm->ddev); | |
eb3dc897 | 2390 | drm_atomic_private_obj_fini(&dm->atomic_obj); |
4562236b HW |
2391 | return; |
2392 | } | |
2393 | ||
2394 | /****************************************************************************** | |
2395 | * amdgpu_display_funcs functions | |
2396 | *****************************************************************************/ | |
2397 | ||
1f6010a9 | 2398 | /* |
4562236b HW |
2399 | * dm_bandwidth_update - program display watermarks |
2400 | * | |
2401 | * @adev: amdgpu_device pointer | |
2402 | * | |
2403 | * Calculate and program the display watermarks and line buffer allocation. | |
2404 | */ | |
2405 | static void dm_bandwidth_update(struct amdgpu_device *adev) | |
2406 | { | |
49c07a99 | 2407 | /* TODO: implement later */ |
4562236b HW |
2408 | } |
2409 | ||
39cc5be2 | 2410 | static const struct amdgpu_display_funcs dm_display_funcs = { |
4562236b HW |
2411 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
2412 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ | |
7b42573b HW |
2413 | .backlight_set_level = NULL, /* never called for DC */ |
2414 | .backlight_get_level = NULL, /* never called for DC */ | |
4562236b HW |
2415 | .hpd_sense = NULL,/* called unconditionally */ |
2416 | .hpd_set_polarity = NULL, /* called unconditionally */ | |
2417 | .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
2418 | .page_flip_get_scanoutpos = |
2419 | dm_crtc_get_scanoutpos,/* called unconditionally */ | |
2420 | .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ | |
2421 | .add_connector = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
2422 | }; |
2423 | ||
2424 | #if defined(CONFIG_DEBUG_KERNEL_DC) | |
2425 | ||
3ee6b26b AD |
2426 | static ssize_t s3_debug_store(struct device *device, |
2427 | struct device_attribute *attr, | |
2428 | const char *buf, | |
2429 | size_t count) | |
4562236b HW |
2430 | { |
2431 | int ret; | |
2432 | int s3_state; | |
ef1de361 | 2433 | struct drm_device *drm_dev = dev_get_drvdata(device); |
4562236b HW |
2434 | struct amdgpu_device *adev = drm_dev->dev_private; |
2435 | ||
2436 | ret = kstrtoint(buf, 0, &s3_state); | |
2437 | ||
2438 | if (ret == 0) { | |
2439 | if (s3_state) { | |
2440 | dm_resume(adev); | |
4562236b HW |
2441 | drm_kms_helper_hotplug_event(adev->ddev); |
2442 | } else | |
2443 | dm_suspend(adev); | |
2444 | } | |
2445 | ||
2446 | return ret == 0 ? count : 0; | |
2447 | } | |
2448 | ||
2449 | DEVICE_ATTR_WO(s3_debug); | |
2450 | ||
2451 | #endif | |
2452 | ||
2453 | static int dm_early_init(void *handle) | |
2454 | { | |
2455 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
2456 | ||
4562236b HW |
2457 | switch (adev->asic_type) { |
2458 | case CHIP_BONAIRE: | |
2459 | case CHIP_HAWAII: | |
2460 | adev->mode_info.num_crtc = 6; | |
2461 | adev->mode_info.num_hpd = 6; | |
2462 | adev->mode_info.num_dig = 6; | |
4562236b | 2463 | break; |
cd4b356f AD |
2464 | case CHIP_KAVERI: |
2465 | adev->mode_info.num_crtc = 4; | |
2466 | adev->mode_info.num_hpd = 6; | |
2467 | adev->mode_info.num_dig = 7; | |
cd4b356f AD |
2468 | break; |
2469 | case CHIP_KABINI: | |
2470 | case CHIP_MULLINS: | |
2471 | adev->mode_info.num_crtc = 2; | |
2472 | adev->mode_info.num_hpd = 6; | |
2473 | adev->mode_info.num_dig = 6; | |
cd4b356f | 2474 | break; |
4562236b HW |
2475 | case CHIP_FIJI: |
2476 | case CHIP_TONGA: | |
2477 | adev->mode_info.num_crtc = 6; | |
2478 | adev->mode_info.num_hpd = 6; | |
2479 | adev->mode_info.num_dig = 7; | |
4562236b HW |
2480 | break; |
2481 | case CHIP_CARRIZO: | |
2482 | adev->mode_info.num_crtc = 3; | |
2483 | adev->mode_info.num_hpd = 6; | |
2484 | adev->mode_info.num_dig = 9; | |
4562236b HW |
2485 | break; |
2486 | case CHIP_STONEY: | |
2487 | adev->mode_info.num_crtc = 2; | |
2488 | adev->mode_info.num_hpd = 6; | |
2489 | adev->mode_info.num_dig = 9; | |
4562236b HW |
2490 | break; |
2491 | case CHIP_POLARIS11: | |
b264d345 | 2492 | case CHIP_POLARIS12: |
4562236b HW |
2493 | adev->mode_info.num_crtc = 5; |
2494 | adev->mode_info.num_hpd = 5; | |
2495 | adev->mode_info.num_dig = 5; | |
4562236b HW |
2496 | break; |
2497 | case CHIP_POLARIS10: | |
7737de91 | 2498 | case CHIP_VEGAM: |
4562236b HW |
2499 | adev->mode_info.num_crtc = 6; |
2500 | adev->mode_info.num_hpd = 6; | |
2501 | adev->mode_info.num_dig = 6; | |
4562236b | 2502 | break; |
2c8ad2d5 | 2503 | case CHIP_VEGA10: |
2325ff30 | 2504 | case CHIP_VEGA12: |
1fe6bf2f | 2505 | case CHIP_VEGA20: |
2c8ad2d5 AD |
2506 | adev->mode_info.num_crtc = 6; |
2507 | adev->mode_info.num_hpd = 6; | |
2508 | adev->mode_info.num_dig = 6; | |
2509 | break; | |
ff5ef992 AD |
2510 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
2511 | case CHIP_RAVEN: | |
2512 | adev->mode_info.num_crtc = 4; | |
2513 | adev->mode_info.num_hpd = 4; | |
2514 | adev->mode_info.num_dig = 4; | |
ff5ef992 | 2515 | break; |
476e955d HW |
2516 | #endif |
2517 | #if defined(CONFIG_DRM_AMD_DC_DCN2_0) | |
2518 | case CHIP_NAVI10: | |
2519 | adev->mode_info.num_crtc = 6; | |
2520 | adev->mode_info.num_hpd = 6; | |
2521 | adev->mode_info.num_dig = 6; | |
2522 | break; | |
fce651e3 BL |
2523 | case CHIP_NAVI14: |
2524 | adev->mode_info.num_crtc = 5; | |
2525 | adev->mode_info.num_hpd = 5; | |
2526 | adev->mode_info.num_dig = 5; | |
2527 | break; | |
ff5ef992 | 2528 | #endif |
4562236b | 2529 | default: |
e63f8673 | 2530 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
4562236b HW |
2531 | return -EINVAL; |
2532 | } | |
2533 | ||
c8dd5715 MD |
2534 | amdgpu_dm_set_irq_funcs(adev); |
2535 | ||
39cc5be2 AD |
2536 | if (adev->mode_info.funcs == NULL) |
2537 | adev->mode_info.funcs = &dm_display_funcs; | |
2538 | ||
1f6010a9 DF |
2539 | /* |
2540 | * Note: Do NOT change adev->audio_endpt_rreg and | |
4562236b | 2541 | * adev->audio_endpt_wreg because they are initialised in |
1f6010a9 DF |
2542 | * amdgpu_device_init() |
2543 | */ | |
4562236b HW |
2544 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
2545 | device_create_file( | |
2546 | adev->ddev->dev, | |
2547 | &dev_attr_s3_debug); | |
2548 | #endif | |
2549 | ||
2550 | return 0; | |
2551 | } | |
2552 | ||
9b690ef3 | 2553 | static bool modeset_required(struct drm_crtc_state *crtc_state, |
0971c40e HW |
2554 | struct dc_stream_state *new_stream, |
2555 | struct dc_stream_state *old_stream) | |
9b690ef3 | 2556 | { |
e7b07cee HW |
2557 | if (!drm_atomic_crtc_needs_modeset(crtc_state)) |
2558 | return false; | |
2559 | ||
2560 | if (!crtc_state->enable) | |
2561 | return false; | |
2562 | ||
2563 | return crtc_state->active; | |
2564 | } | |
2565 | ||
2566 | static bool modereset_required(struct drm_crtc_state *crtc_state) | |
2567 | { | |
2568 | if (!drm_atomic_crtc_needs_modeset(crtc_state)) | |
2569 | return false; | |
2570 | ||
2571 | return !crtc_state->enable || !crtc_state->active; | |
2572 | } | |
2573 | ||
7578ecda | 2574 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
e7b07cee HW |
2575 | { |
2576 | drm_encoder_cleanup(encoder); | |
2577 | kfree(encoder); | |
2578 | } | |
2579 | ||
2580 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { | |
2581 | .destroy = amdgpu_dm_encoder_destroy, | |
2582 | }; | |
2583 | ||
e7b07cee | 2584 | |
695af5f9 NK |
2585 | static int fill_dc_scaling_info(const struct drm_plane_state *state, |
2586 | struct dc_scaling_info *scaling_info) | |
e7b07cee | 2587 | { |
6491f0c0 | 2588 | int scale_w, scale_h; |
e7b07cee | 2589 | |
695af5f9 | 2590 | memset(scaling_info, 0, sizeof(*scaling_info)); |
e7b07cee | 2591 | |
695af5f9 NK |
2592 | /* Source is fixed 16.16 but we ignore mantissa for now... */ |
2593 | scaling_info->src_rect.x = state->src_x >> 16; | |
2594 | scaling_info->src_rect.y = state->src_y >> 16; | |
e7b07cee | 2595 | |
695af5f9 NK |
2596 | scaling_info->src_rect.width = state->src_w >> 16; |
2597 | if (scaling_info->src_rect.width == 0) | |
2598 | return -EINVAL; | |
2599 | ||
2600 | scaling_info->src_rect.height = state->src_h >> 16; | |
2601 | if (scaling_info->src_rect.height == 0) | |
2602 | return -EINVAL; | |
2603 | ||
2604 | scaling_info->dst_rect.x = state->crtc_x; | |
2605 | scaling_info->dst_rect.y = state->crtc_y; | |
e7b07cee HW |
2606 | |
2607 | if (state->crtc_w == 0) | |
695af5f9 | 2608 | return -EINVAL; |
e7b07cee | 2609 | |
695af5f9 | 2610 | scaling_info->dst_rect.width = state->crtc_w; |
e7b07cee HW |
2611 | |
2612 | if (state->crtc_h == 0) | |
695af5f9 | 2613 | return -EINVAL; |
e7b07cee | 2614 | |
695af5f9 | 2615 | scaling_info->dst_rect.height = state->crtc_h; |
e7b07cee | 2616 | |
695af5f9 NK |
2617 | /* DRM doesn't specify clipping on destination output. */ |
2618 | scaling_info->clip_rect = scaling_info->dst_rect; | |
e7b07cee | 2619 | |
6491f0c0 NK |
2620 | /* TODO: Validate scaling per-format with DC plane caps */ |
2621 | scale_w = scaling_info->dst_rect.width * 1000 / | |
2622 | scaling_info->src_rect.width; | |
e7b07cee | 2623 | |
6491f0c0 NK |
2624 | if (scale_w < 250 || scale_w > 16000) |
2625 | return -EINVAL; | |
2626 | ||
2627 | scale_h = scaling_info->dst_rect.height * 1000 / | |
2628 | scaling_info->src_rect.height; | |
2629 | ||
2630 | if (scale_h < 250 || scale_h > 16000) | |
2631 | return -EINVAL; | |
2632 | ||
695af5f9 NK |
2633 | /* |
2634 | * The "scaling_quality" can be ignored for now, quality = 0 has DC | |
2635 | * assume reasonable defaults based on the format. | |
2636 | */ | |
e7b07cee | 2637 | |
695af5f9 | 2638 | return 0; |
4562236b | 2639 | } |
695af5f9 | 2640 | |
3ee6b26b | 2641 | static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, |
9817d5f5 | 2642 | uint64_t *tiling_flags) |
e7b07cee | 2643 | { |
e68d14dd | 2644 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); |
e7b07cee | 2645 | int r = amdgpu_bo_reserve(rbo, false); |
b830ebc9 | 2646 | |
e7b07cee | 2647 | if (unlikely(r)) { |
1f6010a9 | 2648 | /* Don't show error message when returning -ERESTARTSYS */ |
9bbc3031 JZ |
2649 | if (r != -ERESTARTSYS) |
2650 | DRM_ERROR("Unable to reserve buffer: %d\n", r); | |
e7b07cee HW |
2651 | return r; |
2652 | } | |
2653 | ||
e7b07cee HW |
2654 | if (tiling_flags) |
2655 | amdgpu_bo_get_tiling_flags(rbo, tiling_flags); | |
2656 | ||
2657 | amdgpu_bo_unreserve(rbo); | |
2658 | ||
2659 | return r; | |
2660 | } | |
2661 | ||
7df7e505 NK |
2662 | static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) |
2663 | { | |
2664 | uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); | |
2665 | ||
2666 | return offset ? (address + offset * 256) : 0; | |
2667 | } | |
2668 | ||
695af5f9 NK |
2669 | static int |
2670 | fill_plane_dcc_attributes(struct amdgpu_device *adev, | |
2671 | const struct amdgpu_framebuffer *afb, | |
2672 | const enum surface_pixel_format format, | |
2673 | const enum dc_rotation_angle rotation, | |
12e2b2d4 | 2674 | const struct plane_size *plane_size, |
695af5f9 NK |
2675 | const union dc_tiling_info *tiling_info, |
2676 | const uint64_t info, | |
2677 | struct dc_plane_dcc_param *dcc, | |
2678 | struct dc_plane_address *address) | |
7df7e505 NK |
2679 | { |
2680 | struct dc *dc = adev->dm.dc; | |
8daa1218 NC |
2681 | struct dc_dcc_surface_param input; |
2682 | struct dc_surface_dcc_cap output; | |
7df7e505 NK |
2683 | uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); |
2684 | uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; | |
2685 | uint64_t dcc_address; | |
2686 | ||
8daa1218 NC |
2687 | memset(&input, 0, sizeof(input)); |
2688 | memset(&output, 0, sizeof(output)); | |
2689 | ||
7df7e505 | 2690 | if (!offset) |
09e5665a NK |
2691 | return 0; |
2692 | ||
695af5f9 | 2693 | if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
09e5665a | 2694 | return 0; |
7df7e505 NK |
2695 | |
2696 | if (!dc->cap_funcs.get_dcc_compression_cap) | |
09e5665a | 2697 | return -EINVAL; |
7df7e505 | 2698 | |
695af5f9 | 2699 | input.format = format; |
12e2b2d4 DL |
2700 | input.surface_size.width = plane_size->surface_size.width; |
2701 | input.surface_size.height = plane_size->surface_size.height; | |
695af5f9 | 2702 | input.swizzle_mode = tiling_info->gfx9.swizzle; |
7df7e505 | 2703 | |
695af5f9 | 2704 | if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180) |
7df7e505 | 2705 | input.scan = SCAN_DIRECTION_HORIZONTAL; |
695af5f9 | 2706 | else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) |
7df7e505 NK |
2707 | input.scan = SCAN_DIRECTION_VERTICAL; |
2708 | ||
2709 | if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output)) | |
09e5665a | 2710 | return -EINVAL; |
7df7e505 NK |
2711 | |
2712 | if (!output.capable) | |
09e5665a | 2713 | return -EINVAL; |
7df7e505 NK |
2714 | |
2715 | if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) | |
09e5665a | 2716 | return -EINVAL; |
7df7e505 | 2717 | |
09e5665a | 2718 | dcc->enable = 1; |
12e2b2d4 | 2719 | dcc->meta_pitch = |
7df7e505 | 2720 | AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1; |
12e2b2d4 | 2721 | dcc->independent_64b_blks = i64b; |
7df7e505 NK |
2722 | |
2723 | dcc_address = get_dcc_address(afb->address, info); | |
09e5665a NK |
2724 | address->grph.meta_addr.low_part = lower_32_bits(dcc_address); |
2725 | address->grph.meta_addr.high_part = upper_32_bits(dcc_address); | |
7df7e505 | 2726 | |
09e5665a NK |
2727 | return 0; |
2728 | } | |
2729 | ||
2730 | static int | |
320932bf | 2731 | fill_plane_buffer_attributes(struct amdgpu_device *adev, |
09e5665a | 2732 | const struct amdgpu_framebuffer *afb, |
695af5f9 NK |
2733 | const enum surface_pixel_format format, |
2734 | const enum dc_rotation_angle rotation, | |
2735 | const uint64_t tiling_flags, | |
09e5665a | 2736 | union dc_tiling_info *tiling_info, |
12e2b2d4 | 2737 | struct plane_size *plane_size, |
09e5665a | 2738 | struct dc_plane_dcc_param *dcc, |
695af5f9 | 2739 | struct dc_plane_address *address) |
09e5665a | 2740 | { |
320932bf | 2741 | const struct drm_framebuffer *fb = &afb->base; |
09e5665a NK |
2742 | int ret; |
2743 | ||
2744 | memset(tiling_info, 0, sizeof(*tiling_info)); | |
320932bf | 2745 | memset(plane_size, 0, sizeof(*plane_size)); |
09e5665a | 2746 | memset(dcc, 0, sizeof(*dcc)); |
e0634e8d NK |
2747 | memset(address, 0, sizeof(*address)); |
2748 | ||
695af5f9 | 2749 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { |
12e2b2d4 DL |
2750 | plane_size->surface_size.x = 0; |
2751 | plane_size->surface_size.y = 0; | |
2752 | plane_size->surface_size.width = fb->width; | |
2753 | plane_size->surface_size.height = fb->height; | |
2754 | plane_size->surface_pitch = | |
320932bf NK |
2755 | fb->pitches[0] / fb->format->cpp[0]; |
2756 | ||
e0634e8d NK |
2757 | address->type = PLN_ADDR_TYPE_GRAPHICS; |
2758 | address->grph.addr.low_part = lower_32_bits(afb->address); | |
2759 | address->grph.addr.high_part = upper_32_bits(afb->address); | |
1894478a | 2760 | } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { |
1791e54f | 2761 | uint64_t chroma_addr = afb->address + fb->offsets[1]; |
e0634e8d | 2762 | |
12e2b2d4 DL |
2763 | plane_size->surface_size.x = 0; |
2764 | plane_size->surface_size.y = 0; | |
2765 | plane_size->surface_size.width = fb->width; | |
2766 | plane_size->surface_size.height = fb->height; | |
2767 | plane_size->surface_pitch = | |
320932bf NK |
2768 | fb->pitches[0] / fb->format->cpp[0]; |
2769 | ||
12e2b2d4 DL |
2770 | plane_size->chroma_size.x = 0; |
2771 | plane_size->chroma_size.y = 0; | |
320932bf | 2772 | /* TODO: set these based on surface format */ |
12e2b2d4 DL |
2773 | plane_size->chroma_size.width = fb->width / 2; |
2774 | plane_size->chroma_size.height = fb->height / 2; | |
320932bf | 2775 | |
12e2b2d4 | 2776 | plane_size->chroma_pitch = |
320932bf NK |
2777 | fb->pitches[1] / fb->format->cpp[1]; |
2778 | ||
e0634e8d NK |
2779 | address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; |
2780 | address->video_progressive.luma_addr.low_part = | |
2781 | lower_32_bits(afb->address); | |
2782 | address->video_progressive.luma_addr.high_part = | |
2783 | upper_32_bits(afb->address); | |
2784 | address->video_progressive.chroma_addr.low_part = | |
2785 | lower_32_bits(chroma_addr); | |
2786 | address->video_progressive.chroma_addr.high_part = | |
2787 | upper_32_bits(chroma_addr); | |
2788 | } | |
09e5665a NK |
2789 | |
2790 | /* Fill GFX8 params */ | |
2791 | if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { | |
2792 | unsigned int bankw, bankh, mtaspect, tile_split, num_banks; | |
2793 | ||
2794 | bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); | |
2795 | bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); | |
2796 | mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); | |
2797 | tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); | |
2798 | num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); | |
2799 | ||
2800 | /* XXX fix me for VI */ | |
2801 | tiling_info->gfx8.num_banks = num_banks; | |
2802 | tiling_info->gfx8.array_mode = | |
2803 | DC_ARRAY_2D_TILED_THIN1; | |
2804 | tiling_info->gfx8.tile_split = tile_split; | |
2805 | tiling_info->gfx8.bank_width = bankw; | |
2806 | tiling_info->gfx8.bank_height = bankh; | |
2807 | tiling_info->gfx8.tile_aspect = mtaspect; | |
2808 | tiling_info->gfx8.tile_mode = | |
2809 | DC_ADDR_SURF_MICRO_TILING_DISPLAY; | |
2810 | } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) | |
2811 | == DC_ARRAY_1D_TILED_THIN1) { | |
2812 | tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; | |
2813 | } | |
2814 | ||
2815 | tiling_info->gfx8.pipe_config = | |
2816 | AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); | |
2817 | ||
2818 | if (adev->asic_type == CHIP_VEGA10 || | |
2819 | adev->asic_type == CHIP_VEGA12 || | |
2820 | adev->asic_type == CHIP_VEGA20 || | |
476e955d HW |
2821 | #if defined(CONFIG_DRM_AMD_DC_DCN2_0) |
2822 | adev->asic_type == CHIP_NAVI10 || | |
fce651e3 | 2823 | adev->asic_type == CHIP_NAVI14 || |
476e955d | 2824 | #endif |
09e5665a NK |
2825 | adev->asic_type == CHIP_RAVEN) { |
2826 | /* Fill GFX9 params */ | |
2827 | tiling_info->gfx9.num_pipes = | |
2828 | adev->gfx.config.gb_addr_config_fields.num_pipes; | |
2829 | tiling_info->gfx9.num_banks = | |
2830 | adev->gfx.config.gb_addr_config_fields.num_banks; | |
2831 | tiling_info->gfx9.pipe_interleave = | |
2832 | adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; | |
2833 | tiling_info->gfx9.num_shader_engines = | |
2834 | adev->gfx.config.gb_addr_config_fields.num_se; | |
2835 | tiling_info->gfx9.max_compressed_frags = | |
2836 | adev->gfx.config.gb_addr_config_fields.max_compress_frags; | |
2837 | tiling_info->gfx9.num_rb_per_se = | |
2838 | adev->gfx.config.gb_addr_config_fields.num_rb_per_se; | |
2839 | tiling_info->gfx9.swizzle = | |
2840 | AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); | |
2841 | tiling_info->gfx9.shaderEnable = 1; | |
2842 | ||
695af5f9 NK |
2843 | ret = fill_plane_dcc_attributes(adev, afb, format, rotation, |
2844 | plane_size, tiling_info, | |
2845 | tiling_flags, dcc, address); | |
09e5665a NK |
2846 | if (ret) |
2847 | return ret; | |
2848 | } | |
2849 | ||
2850 | return 0; | |
7df7e505 NK |
2851 | } |
2852 | ||
d74004b6 | 2853 | static void |
695af5f9 | 2854 | fill_blending_from_plane_state(const struct drm_plane_state *plane_state, |
d74004b6 NK |
2855 | bool *per_pixel_alpha, bool *global_alpha, |
2856 | int *global_alpha_value) | |
2857 | { | |
2858 | *per_pixel_alpha = false; | |
2859 | *global_alpha = false; | |
2860 | *global_alpha_value = 0xff; | |
2861 | ||
2862 | if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) | |
2863 | return; | |
2864 | ||
2865 | if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { | |
2866 | static const uint32_t alpha_formats[] = { | |
2867 | DRM_FORMAT_ARGB8888, | |
2868 | DRM_FORMAT_RGBA8888, | |
2869 | DRM_FORMAT_ABGR8888, | |
2870 | }; | |
2871 | uint32_t format = plane_state->fb->format->format; | |
2872 | unsigned int i; | |
2873 | ||
2874 | for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) { | |
2875 | if (format == alpha_formats[i]) { | |
2876 | *per_pixel_alpha = true; | |
2877 | break; | |
2878 | } | |
2879 | } | |
2880 | } | |
2881 | ||
2882 | if (plane_state->alpha < 0xffff) { | |
2883 | *global_alpha = true; | |
2884 | *global_alpha_value = plane_state->alpha >> 8; | |
2885 | } | |
2886 | } | |
2887 | ||
004fefa3 NK |
2888 | static int |
2889 | fill_plane_color_attributes(const struct drm_plane_state *plane_state, | |
695af5f9 | 2890 | const enum surface_pixel_format format, |
004fefa3 NK |
2891 | enum dc_color_space *color_space) |
2892 | { | |
2893 | bool full_range; | |
2894 | ||
2895 | *color_space = COLOR_SPACE_SRGB; | |
2896 | ||
2897 | /* DRM color properties only affect non-RGB formats. */ | |
695af5f9 | 2898 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
004fefa3 NK |
2899 | return 0; |
2900 | ||
2901 | full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); | |
2902 | ||
2903 | switch (plane_state->color_encoding) { | |
2904 | case DRM_COLOR_YCBCR_BT601: | |
2905 | if (full_range) | |
2906 | *color_space = COLOR_SPACE_YCBCR601; | |
2907 | else | |
2908 | *color_space = COLOR_SPACE_YCBCR601_LIMITED; | |
2909 | break; | |
2910 | ||
2911 | case DRM_COLOR_YCBCR_BT709: | |
2912 | if (full_range) | |
2913 | *color_space = COLOR_SPACE_YCBCR709; | |
2914 | else | |
2915 | *color_space = COLOR_SPACE_YCBCR709_LIMITED; | |
2916 | break; | |
2917 | ||
2918 | case DRM_COLOR_YCBCR_BT2020: | |
2919 | if (full_range) | |
2920 | *color_space = COLOR_SPACE_2020_YCBCR; | |
2921 | else | |
2922 | return -EINVAL; | |
2923 | break; | |
2924 | ||
2925 | default: | |
2926 | return -EINVAL; | |
2927 | } | |
2928 | ||
2929 | return 0; | |
2930 | } | |
2931 | ||
695af5f9 NK |
2932 | static int |
2933 | fill_dc_plane_info_and_addr(struct amdgpu_device *adev, | |
2934 | const struct drm_plane_state *plane_state, | |
2935 | const uint64_t tiling_flags, | |
2936 | struct dc_plane_info *plane_info, | |
2937 | struct dc_plane_address *address) | |
2938 | { | |
2939 | const struct drm_framebuffer *fb = plane_state->fb; | |
2940 | const struct amdgpu_framebuffer *afb = | |
2941 | to_amdgpu_framebuffer(plane_state->fb); | |
2942 | struct drm_format_name_buf format_name; | |
2943 | int ret; | |
2944 | ||
2945 | memset(plane_info, 0, sizeof(*plane_info)); | |
2946 | ||
2947 | switch (fb->format->format) { | |
2948 | case DRM_FORMAT_C8: | |
2949 | plane_info->format = | |
2950 | SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; | |
2951 | break; | |
2952 | case DRM_FORMAT_RGB565: | |
2953 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; | |
2954 | break; | |
2955 | case DRM_FORMAT_XRGB8888: | |
2956 | case DRM_FORMAT_ARGB8888: | |
2957 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; | |
2958 | break; | |
2959 | case DRM_FORMAT_XRGB2101010: | |
2960 | case DRM_FORMAT_ARGB2101010: | |
2961 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; | |
2962 | break; | |
2963 | case DRM_FORMAT_XBGR2101010: | |
2964 | case DRM_FORMAT_ABGR2101010: | |
2965 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; | |
2966 | break; | |
2967 | case DRM_FORMAT_XBGR8888: | |
2968 | case DRM_FORMAT_ABGR8888: | |
2969 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; | |
2970 | break; | |
2971 | case DRM_FORMAT_NV21: | |
2972 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; | |
2973 | break; | |
2974 | case DRM_FORMAT_NV12: | |
2975 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; | |
2976 | break; | |
2977 | default: | |
2978 | DRM_ERROR( | |
2979 | "Unsupported screen format %s\n", | |
2980 | drm_get_format_name(fb->format->format, &format_name)); | |
2981 | return -EINVAL; | |
2982 | } | |
2983 | ||
2984 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { | |
2985 | case DRM_MODE_ROTATE_0: | |
2986 | plane_info->rotation = ROTATION_ANGLE_0; | |
2987 | break; | |
2988 | case DRM_MODE_ROTATE_90: | |
2989 | plane_info->rotation = ROTATION_ANGLE_90; | |
2990 | break; | |
2991 | case DRM_MODE_ROTATE_180: | |
2992 | plane_info->rotation = ROTATION_ANGLE_180; | |
2993 | break; | |
2994 | case DRM_MODE_ROTATE_270: | |
2995 | plane_info->rotation = ROTATION_ANGLE_270; | |
2996 | break; | |
2997 | default: | |
2998 | plane_info->rotation = ROTATION_ANGLE_0; | |
2999 | break; | |
3000 | } | |
3001 | ||
3002 | plane_info->visible = true; | |
3003 | plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; | |
3004 | ||
3005 | ret = fill_plane_color_attributes(plane_state, plane_info->format, | |
3006 | &plane_info->color_space); | |
3007 | if (ret) | |
3008 | return ret; | |
3009 | ||
3010 | ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, | |
3011 | plane_info->rotation, tiling_flags, | |
3012 | &plane_info->tiling_info, | |
3013 | &plane_info->plane_size, | |
3014 | &plane_info->dcc, address); | |
3015 | if (ret) | |
3016 | return ret; | |
3017 | ||
3018 | fill_blending_from_plane_state( | |
3019 | plane_state, &plane_info->per_pixel_alpha, | |
3020 | &plane_info->global_alpha, &plane_info->global_alpha_value); | |
3021 | ||
3022 | return 0; | |
3023 | } | |
3024 | ||
3025 | static int fill_dc_plane_attributes(struct amdgpu_device *adev, | |
3026 | struct dc_plane_state *dc_plane_state, | |
3027 | struct drm_plane_state *plane_state, | |
3028 | struct drm_crtc_state *crtc_state) | |
e7b07cee | 3029 | { |
cf020d49 | 3030 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); |
e7b07cee HW |
3031 | const struct amdgpu_framebuffer *amdgpu_fb = |
3032 | to_amdgpu_framebuffer(plane_state->fb); | |
695af5f9 NK |
3033 | struct dc_scaling_info scaling_info; |
3034 | struct dc_plane_info plane_info; | |
3035 | uint64_t tiling_flags; | |
3036 | int ret; | |
e7b07cee | 3037 | |
695af5f9 NK |
3038 | ret = fill_dc_scaling_info(plane_state, &scaling_info); |
3039 | if (ret) | |
3040 | return ret; | |
e7b07cee | 3041 | |
695af5f9 NK |
3042 | dc_plane_state->src_rect = scaling_info.src_rect; |
3043 | dc_plane_state->dst_rect = scaling_info.dst_rect; | |
3044 | dc_plane_state->clip_rect = scaling_info.clip_rect; | |
3045 | dc_plane_state->scaling_quality = scaling_info.scaling_quality; | |
e7b07cee | 3046 | |
695af5f9 | 3047 | ret = get_fb_info(amdgpu_fb, &tiling_flags); |
e7b07cee HW |
3048 | if (ret) |
3049 | return ret; | |
3050 | ||
695af5f9 NK |
3051 | ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags, |
3052 | &plane_info, | |
3053 | &dc_plane_state->address); | |
004fefa3 NK |
3054 | if (ret) |
3055 | return ret; | |
3056 | ||
695af5f9 NK |
3057 | dc_plane_state->format = plane_info.format; |
3058 | dc_plane_state->color_space = plane_info.color_space; | |
3059 | dc_plane_state->format = plane_info.format; | |
3060 | dc_plane_state->plane_size = plane_info.plane_size; | |
3061 | dc_plane_state->rotation = plane_info.rotation; | |
3062 | dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; | |
3063 | dc_plane_state->stereo_format = plane_info.stereo_format; | |
3064 | dc_plane_state->tiling_info = plane_info.tiling_info; | |
3065 | dc_plane_state->visible = plane_info.visible; | |
3066 | dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; | |
3067 | dc_plane_state->global_alpha = plane_info.global_alpha; | |
3068 | dc_plane_state->global_alpha_value = plane_info.global_alpha_value; | |
3069 | dc_plane_state->dcc = plane_info.dcc; | |
3070 | ||
e277adc5 LSL |
3071 | /* |
3072 | * Always set input transfer function, since plane state is refreshed | |
3073 | * every time. | |
3074 | */ | |
cf020d49 NK |
3075 | ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); |
3076 | if (ret) | |
3077 | return ret; | |
e7b07cee | 3078 | |
cf020d49 | 3079 | return 0; |
e7b07cee HW |
3080 | } |
3081 | ||
3ee6b26b AD |
3082 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
3083 | const struct dm_connector_state *dm_state, | |
3084 | struct dc_stream_state *stream) | |
e7b07cee HW |
3085 | { |
3086 | enum amdgpu_rmx_type rmx_type; | |
3087 | ||
3088 | struct rect src = { 0 }; /* viewport in composition space*/ | |
3089 | struct rect dst = { 0 }; /* stream addressable area */ | |
3090 | ||
3091 | /* no mode. nothing to be done */ | |
3092 | if (!mode) | |
3093 | return; | |
3094 | ||
3095 | /* Full screen scaling by default */ | |
3096 | src.width = mode->hdisplay; | |
3097 | src.height = mode->vdisplay; | |
3098 | dst.width = stream->timing.h_addressable; | |
3099 | dst.height = stream->timing.v_addressable; | |
3100 | ||
f4791779 HW |
3101 | if (dm_state) { |
3102 | rmx_type = dm_state->scaling; | |
3103 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { | |
3104 | if (src.width * dst.height < | |
3105 | src.height * dst.width) { | |
3106 | /* height needs less upscaling/more downscaling */ | |
3107 | dst.width = src.width * | |
3108 | dst.height / src.height; | |
3109 | } else { | |
3110 | /* width needs less upscaling/more downscaling */ | |
3111 | dst.height = src.height * | |
3112 | dst.width / src.width; | |
3113 | } | |
3114 | } else if (rmx_type == RMX_CENTER) { | |
3115 | dst = src; | |
e7b07cee | 3116 | } |
e7b07cee | 3117 | |
f4791779 HW |
3118 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
3119 | dst.y = (stream->timing.v_addressable - dst.height) / 2; | |
e7b07cee | 3120 | |
f4791779 HW |
3121 | if (dm_state->underscan_enable) { |
3122 | dst.x += dm_state->underscan_hborder / 2; | |
3123 | dst.y += dm_state->underscan_vborder / 2; | |
3124 | dst.width -= dm_state->underscan_hborder; | |
3125 | dst.height -= dm_state->underscan_vborder; | |
3126 | } | |
e7b07cee HW |
3127 | } |
3128 | ||
3129 | stream->src = src; | |
3130 | stream->dst = dst; | |
3131 | ||
f1ad2f5e | 3132 | DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", |
e7b07cee HW |
3133 | dst.x, dst.y, dst.width, dst.height); |
3134 | ||
3135 | } | |
3136 | ||
3ee6b26b | 3137 | static enum dc_color_depth |
42ba01fc NK |
3138 | convert_color_depth_from_display_info(const struct drm_connector *connector, |
3139 | const struct drm_connector_state *state) | |
e7b07cee HW |
3140 | { |
3141 | uint32_t bpc = connector->display_info.bpc; | |
3142 | ||
01933ba4 NK |
3143 | if (!state) |
3144 | state = connector->state; | |
3145 | ||
42ba01fc NK |
3146 | if (state) { |
3147 | bpc = state->max_bpc; | |
1825fd34 NK |
3148 | /* Round down to the nearest even number. */ |
3149 | bpc = bpc - (bpc & 1); | |
3150 | } | |
07e3a1cf | 3151 | |
e7b07cee HW |
3152 | switch (bpc) { |
3153 | case 0: | |
1f6010a9 DF |
3154 | /* |
3155 | * Temporary Work around, DRM doesn't parse color depth for | |
e7b07cee HW |
3156 | * EDID revision before 1.4 |
3157 | * TODO: Fix edid parsing | |
3158 | */ | |
3159 | return COLOR_DEPTH_888; | |
3160 | case 6: | |
3161 | return COLOR_DEPTH_666; | |
3162 | case 8: | |
3163 | return COLOR_DEPTH_888; | |
3164 | case 10: | |
3165 | return COLOR_DEPTH_101010; | |
3166 | case 12: | |
3167 | return COLOR_DEPTH_121212; | |
3168 | case 14: | |
3169 | return COLOR_DEPTH_141414; | |
3170 | case 16: | |
3171 | return COLOR_DEPTH_161616; | |
3172 | default: | |
3173 | return COLOR_DEPTH_UNDEFINED; | |
3174 | } | |
3175 | } | |
3176 | ||
3ee6b26b AD |
3177 | static enum dc_aspect_ratio |
3178 | get_aspect_ratio(const struct drm_display_mode *mode_in) | |
e7b07cee | 3179 | { |
e11d4147 LSL |
3180 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
3181 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; | |
e7b07cee HW |
3182 | } |
3183 | ||
3ee6b26b AD |
3184 | static enum dc_color_space |
3185 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) | |
e7b07cee HW |
3186 | { |
3187 | enum dc_color_space color_space = COLOR_SPACE_SRGB; | |
3188 | ||
3189 | switch (dc_crtc_timing->pixel_encoding) { | |
3190 | case PIXEL_ENCODING_YCBCR422: | |
3191 | case PIXEL_ENCODING_YCBCR444: | |
3192 | case PIXEL_ENCODING_YCBCR420: | |
3193 | { | |
3194 | /* | |
3195 | * 27030khz is the separation point between HDTV and SDTV | |
3196 | * according to HDMI spec, we use YCbCr709 and YCbCr601 | |
3197 | * respectively | |
3198 | */ | |
380604e2 | 3199 | if (dc_crtc_timing->pix_clk_100hz > 270300) { |
e7b07cee HW |
3200 | if (dc_crtc_timing->flags.Y_ONLY) |
3201 | color_space = | |
3202 | COLOR_SPACE_YCBCR709_LIMITED; | |
3203 | else | |
3204 | color_space = COLOR_SPACE_YCBCR709; | |
3205 | } else { | |
3206 | if (dc_crtc_timing->flags.Y_ONLY) | |
3207 | color_space = | |
3208 | COLOR_SPACE_YCBCR601_LIMITED; | |
3209 | else | |
3210 | color_space = COLOR_SPACE_YCBCR601; | |
3211 | } | |
3212 | ||
3213 | } | |
3214 | break; | |
3215 | case PIXEL_ENCODING_RGB: | |
3216 | color_space = COLOR_SPACE_SRGB; | |
3217 | break; | |
3218 | ||
3219 | default: | |
3220 | WARN_ON(1); | |
3221 | break; | |
3222 | } | |
3223 | ||
3224 | return color_space; | |
3225 | } | |
3226 | ||
400443e8 ML |
3227 | static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) |
3228 | { | |
3229 | if (timing_out->display_color_depth <= COLOR_DEPTH_888) | |
3230 | return; | |
3231 | ||
3232 | timing_out->display_color_depth--; | |
3233 | } | |
3234 | ||
3235 | static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, | |
3236 | const struct drm_display_info *info) | |
3237 | { | |
3238 | int normalized_clk; | |
3239 | if (timing_out->display_color_depth <= COLOR_DEPTH_888) | |
3240 | return; | |
3241 | do { | |
380604e2 | 3242 | normalized_clk = timing_out->pix_clk_100hz / 10; |
400443e8 ML |
3243 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ |
3244 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) | |
3245 | normalized_clk /= 2; | |
3246 | /* Adjusting pix clock following on HDMI spec based on colour depth */ | |
3247 | switch (timing_out->display_color_depth) { | |
3248 | case COLOR_DEPTH_101010: | |
3249 | normalized_clk = (normalized_clk * 30) / 24; | |
3250 | break; | |
3251 | case COLOR_DEPTH_121212: | |
3252 | normalized_clk = (normalized_clk * 36) / 24; | |
3253 | break; | |
3254 | case COLOR_DEPTH_161616: | |
3255 | normalized_clk = (normalized_clk * 48) / 24; | |
3256 | break; | |
3257 | default: | |
3258 | return; | |
3259 | } | |
3260 | if (normalized_clk <= info->max_tmds_clock) | |
3261 | return; | |
3262 | reduce_mode_colour_depth(timing_out); | |
3263 | ||
3264 | } while (timing_out->display_color_depth > COLOR_DEPTH_888); | |
3265 | ||
3266 | } | |
e7b07cee | 3267 | |
42ba01fc NK |
3268 | static void fill_stream_properties_from_drm_display_mode( |
3269 | struct dc_stream_state *stream, | |
3270 | const struct drm_display_mode *mode_in, | |
3271 | const struct drm_connector *connector, | |
3272 | const struct drm_connector_state *connector_state, | |
3273 | const struct dc_stream_state *old_stream) | |
e7b07cee HW |
3274 | { |
3275 | struct dc_crtc_timing *timing_out = &stream->timing; | |
fe61a2f1 | 3276 | const struct drm_display_info *info = &connector->display_info; |
b830ebc9 | 3277 | |
e7b07cee HW |
3278 | memset(timing_out, 0, sizeof(struct dc_crtc_timing)); |
3279 | ||
3280 | timing_out->h_border_left = 0; | |
3281 | timing_out->h_border_right = 0; | |
3282 | timing_out->v_border_top = 0; | |
3283 | timing_out->v_border_bottom = 0; | |
3284 | /* TODO: un-hardcode */ | |
fe61a2f1 | 3285 | if (drm_mode_is_420_only(info, mode_in) |
ceb3dbb4 | 3286 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
fe61a2f1 ML |
3287 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
3288 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) | |
ceb3dbb4 | 3289 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
e7b07cee HW |
3290 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; |
3291 | else | |
3292 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; | |
3293 | ||
3294 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; | |
3295 | timing_out->display_color_depth = convert_color_depth_from_display_info( | |
42ba01fc | 3296 | connector, connector_state); |
e7b07cee HW |
3297 | timing_out->scan_type = SCANNING_TYPE_NODATA; |
3298 | timing_out->hdmi_vic = 0; | |
b333730d BL |
3299 | |
3300 | if(old_stream) { | |
3301 | timing_out->vic = old_stream->timing.vic; | |
3302 | timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; | |
3303 | timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; | |
3304 | } else { | |
3305 | timing_out->vic = drm_match_cea_mode(mode_in); | |
3306 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) | |
3307 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; | |
3308 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) | |
3309 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; | |
3310 | } | |
e7b07cee HW |
3311 | |
3312 | timing_out->h_addressable = mode_in->crtc_hdisplay; | |
3313 | timing_out->h_total = mode_in->crtc_htotal; | |
3314 | timing_out->h_sync_width = | |
3315 | mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; | |
3316 | timing_out->h_front_porch = | |
3317 | mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; | |
3318 | timing_out->v_total = mode_in->crtc_vtotal; | |
3319 | timing_out->v_addressable = mode_in->crtc_vdisplay; | |
3320 | timing_out->v_front_porch = | |
3321 | mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; | |
3322 | timing_out->v_sync_width = | |
3323 | mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; | |
380604e2 | 3324 | timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; |
e7b07cee | 3325 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); |
e7b07cee HW |
3326 | |
3327 | stream->output_color_space = get_output_color_space(timing_out); | |
3328 | ||
e43a432c AK |
3329 | stream->out_transfer_func->type = TF_TYPE_PREDEFINED; |
3330 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; | |
ceb3dbb4 | 3331 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
400443e8 | 3332 | adjust_colour_depth_from_display_info(timing_out, info); |
e7b07cee HW |
3333 | } |
3334 | ||
3ee6b26b AD |
3335 | static void fill_audio_info(struct audio_info *audio_info, |
3336 | const struct drm_connector *drm_connector, | |
3337 | const struct dc_sink *dc_sink) | |
e7b07cee HW |
3338 | { |
3339 | int i = 0; | |
3340 | int cea_revision = 0; | |
3341 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; | |
3342 | ||
3343 | audio_info->manufacture_id = edid_caps->manufacturer_id; | |
3344 | audio_info->product_id = edid_caps->product_id; | |
3345 | ||
3346 | cea_revision = drm_connector->display_info.cea_rev; | |
3347 | ||
090afc1e | 3348 | strscpy(audio_info->display_name, |
d2b2562c | 3349 | edid_caps->display_name, |
090afc1e | 3350 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); |
e7b07cee | 3351 | |
b830ebc9 | 3352 | if (cea_revision >= 3) { |
e7b07cee HW |
3353 | audio_info->mode_count = edid_caps->audio_mode_count; |
3354 | ||
3355 | for (i = 0; i < audio_info->mode_count; ++i) { | |
3356 | audio_info->modes[i].format_code = | |
3357 | (enum audio_format_code) | |
3358 | (edid_caps->audio_modes[i].format_code); | |
3359 | audio_info->modes[i].channel_count = | |
3360 | edid_caps->audio_modes[i].channel_count; | |
3361 | audio_info->modes[i].sample_rates.all = | |
3362 | edid_caps->audio_modes[i].sample_rate; | |
3363 | audio_info->modes[i].sample_size = | |
3364 | edid_caps->audio_modes[i].sample_size; | |
3365 | } | |
3366 | } | |
3367 | ||
3368 | audio_info->flags.all = edid_caps->speaker_flags; | |
3369 | ||
3370 | /* TODO: We only check for the progressive mode, check for interlace mode too */ | |
b830ebc9 | 3371 | if (drm_connector->latency_present[0]) { |
e7b07cee HW |
3372 | audio_info->video_latency = drm_connector->video_latency[0]; |
3373 | audio_info->audio_latency = drm_connector->audio_latency[0]; | |
3374 | } | |
3375 | ||
3376 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ | |
3377 | ||
3378 | } | |
3379 | ||
3ee6b26b AD |
3380 | static void |
3381 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, | |
3382 | struct drm_display_mode *dst_mode) | |
e7b07cee HW |
3383 | { |
3384 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; | |
3385 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; | |
3386 | dst_mode->crtc_clock = src_mode->crtc_clock; | |
3387 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; | |
3388 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; | |
b830ebc9 | 3389 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
e7b07cee HW |
3390 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
3391 | dst_mode->crtc_htotal = src_mode->crtc_htotal; | |
3392 | dst_mode->crtc_hskew = src_mode->crtc_hskew; | |
3393 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; | |
3394 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; | |
3395 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; | |
3396 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; | |
3397 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; | |
3398 | } | |
3399 | ||
3ee6b26b AD |
3400 | static void |
3401 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, | |
3402 | const struct drm_display_mode *native_mode, | |
3403 | bool scale_enabled) | |
e7b07cee HW |
3404 | { |
3405 | if (scale_enabled) { | |
3406 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
3407 | } else if (native_mode->clock == drm_mode->clock && | |
3408 | native_mode->htotal == drm_mode->htotal && | |
3409 | native_mode->vtotal == drm_mode->vtotal) { | |
3410 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
3411 | } else { | |
3412 | /* no scaling nor amdgpu inserted, no need to patch */ | |
3413 | } | |
3414 | } | |
3415 | ||
aed15309 ML |
3416 | static struct dc_sink * |
3417 | create_fake_sink(struct amdgpu_dm_connector *aconnector) | |
2e0ac3d6 | 3418 | { |
2e0ac3d6 | 3419 | struct dc_sink_init_data sink_init_data = { 0 }; |
aed15309 | 3420 | struct dc_sink *sink = NULL; |
2e0ac3d6 HW |
3421 | sink_init_data.link = aconnector->dc_link; |
3422 | sink_init_data.sink_signal = aconnector->dc_link->connector_signal; | |
3423 | ||
3424 | sink = dc_sink_create(&sink_init_data); | |
423788c7 | 3425 | if (!sink) { |
2e0ac3d6 | 3426 | DRM_ERROR("Failed to create sink!\n"); |
aed15309 | 3427 | return NULL; |
423788c7 | 3428 | } |
2e0ac3d6 | 3429 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
423788c7 | 3430 | |
aed15309 | 3431 | return sink; |
2e0ac3d6 HW |
3432 | } |
3433 | ||
fa2123db ML |
3434 | static void set_multisync_trigger_params( |
3435 | struct dc_stream_state *stream) | |
3436 | { | |
3437 | if (stream->triggered_crtc_reset.enabled) { | |
3438 | stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; | |
3439 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; | |
3440 | } | |
3441 | } | |
3442 | ||
3443 | static void set_master_stream(struct dc_stream_state *stream_set[], | |
3444 | int stream_count) | |
3445 | { | |
3446 | int j, highest_rfr = 0, master_stream = 0; | |
3447 | ||
3448 | for (j = 0; j < stream_count; j++) { | |
3449 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { | |
3450 | int refresh_rate = 0; | |
3451 | ||
380604e2 | 3452 | refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ |
fa2123db ML |
3453 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); |
3454 | if (refresh_rate > highest_rfr) { | |
3455 | highest_rfr = refresh_rate; | |
3456 | master_stream = j; | |
3457 | } | |
3458 | } | |
3459 | } | |
3460 | for (j = 0; j < stream_count; j++) { | |
03736f4c | 3461 | if (stream_set[j]) |
fa2123db ML |
3462 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
3463 | } | |
3464 | } | |
3465 | ||
3466 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) | |
3467 | { | |
3468 | int i = 0; | |
3469 | ||
3470 | if (context->stream_count < 2) | |
3471 | return; | |
3472 | for (i = 0; i < context->stream_count ; i++) { | |
3473 | if (!context->streams[i]) | |
3474 | continue; | |
1f6010a9 DF |
3475 | /* |
3476 | * TODO: add a function to read AMD VSDB bits and set | |
fa2123db | 3477 | * crtc_sync_master.multi_sync_enabled flag |
1f6010a9 | 3478 | * For now it's set to false |
fa2123db ML |
3479 | */ |
3480 | set_multisync_trigger_params(context->streams[i]); | |
3481 | } | |
3482 | set_master_stream(context->streams, context->stream_count); | |
3483 | } | |
3484 | ||
3ee6b26b AD |
3485 | static struct dc_stream_state * |
3486 | create_stream_for_sink(struct amdgpu_dm_connector *aconnector, | |
3487 | const struct drm_display_mode *drm_mode, | |
b333730d BL |
3488 | const struct dm_connector_state *dm_state, |
3489 | const struct dc_stream_state *old_stream) | |
e7b07cee HW |
3490 | { |
3491 | struct drm_display_mode *preferred_mode = NULL; | |
391ef035 | 3492 | struct drm_connector *drm_connector; |
42ba01fc NK |
3493 | const struct drm_connector_state *con_state = |
3494 | dm_state ? &dm_state->base : NULL; | |
0971c40e | 3495 | struct dc_stream_state *stream = NULL; |
e7b07cee HW |
3496 | struct drm_display_mode mode = *drm_mode; |
3497 | bool native_mode_found = false; | |
b333730d BL |
3498 | bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false; |
3499 | int mode_refresh; | |
58124bf8 | 3500 | int preferred_refresh = 0; |
b333730d | 3501 | |
aed15309 | 3502 | struct dc_sink *sink = NULL; |
b830ebc9 | 3503 | if (aconnector == NULL) { |
e7b07cee | 3504 | DRM_ERROR("aconnector is NULL!\n"); |
64245fa7 | 3505 | return stream; |
e7b07cee HW |
3506 | } |
3507 | ||
e7b07cee | 3508 | drm_connector = &aconnector->base; |
2e0ac3d6 | 3509 | |
f4ac176e | 3510 | if (!aconnector->dc_sink) { |
e3fa5c4c JFZ |
3511 | sink = create_fake_sink(aconnector); |
3512 | if (!sink) | |
3513 | return stream; | |
aed15309 ML |
3514 | } else { |
3515 | sink = aconnector->dc_sink; | |
dcd5fb82 | 3516 | dc_sink_retain(sink); |
f4ac176e | 3517 | } |
2e0ac3d6 | 3518 | |
aed15309 | 3519 | stream = dc_create_stream_for_sink(sink); |
4562236b | 3520 | |
b830ebc9 | 3521 | if (stream == NULL) { |
e7b07cee | 3522 | DRM_ERROR("Failed to create stream for sink!\n"); |
aed15309 | 3523 | goto finish; |
e7b07cee HW |
3524 | } |
3525 | ||
ceb3dbb4 JL |
3526 | stream->dm_stream_context = aconnector; |
3527 | ||
e7b07cee HW |
3528 | list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { |
3529 | /* Search for preferred mode */ | |
3530 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { | |
3531 | native_mode_found = true; | |
3532 | break; | |
3533 | } | |
3534 | } | |
3535 | if (!native_mode_found) | |
3536 | preferred_mode = list_first_entry_or_null( | |
3537 | &aconnector->base.modes, | |
3538 | struct drm_display_mode, | |
3539 | head); | |
3540 | ||
b333730d BL |
3541 | mode_refresh = drm_mode_vrefresh(&mode); |
3542 | ||
b830ebc9 | 3543 | if (preferred_mode == NULL) { |
1f6010a9 DF |
3544 | /* |
3545 | * This may not be an error, the use case is when we have no | |
e7b07cee HW |
3546 | * usermode calls to reset and set mode upon hotplug. In this |
3547 | * case, we call set mode ourselves to restore the previous mode | |
3548 | * and the modelist may not be filled in in time. | |
3549 | */ | |
f1ad2f5e | 3550 | DRM_DEBUG_DRIVER("No preferred mode found\n"); |
e7b07cee HW |
3551 | } else { |
3552 | decide_crtc_timing_for_drm_display_mode( | |
3553 | &mode, preferred_mode, | |
f4791779 | 3554 | dm_state ? (dm_state->scaling != RMX_OFF) : false); |
58124bf8 | 3555 | preferred_refresh = drm_mode_vrefresh(preferred_mode); |
e7b07cee HW |
3556 | } |
3557 | ||
f783577c JFZ |
3558 | if (!dm_state) |
3559 | drm_mode_set_crtcinfo(&mode, 0); | |
3560 | ||
b333730d BL |
3561 | /* |
3562 | * If scaling is enabled and refresh rate didn't change | |
3563 | * we copy the vic and polarities of the old timings | |
3564 | */ | |
3565 | if (!scale || mode_refresh != preferred_refresh) | |
3566 | fill_stream_properties_from_drm_display_mode(stream, | |
42ba01fc | 3567 | &mode, &aconnector->base, con_state, NULL); |
b333730d BL |
3568 | else |
3569 | fill_stream_properties_from_drm_display_mode(stream, | |
42ba01fc | 3570 | &mode, &aconnector->base, con_state, old_stream); |
b333730d | 3571 | |
39a4eb85 WL |
3572 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT |
3573 | /* stream->timing.flags.DSC = 0; */ | |
3574 | /* */ | |
3575 | /* if (aconnector->dc_link && */ | |
3576 | /* aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */ | |
3577 | /* aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */ | |
3578 | /* if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */ | |
3579 | /* &aconnector->dc_link->dpcd_caps.dsc_caps, */ | |
3580 | /* dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */ | |
3581 | /* &stream->timing, */ | |
3582 | /* &stream->timing.dsc_cfg)) */ | |
3583 | /* stream->timing.flags.DSC = 1; */ | |
3584 | #endif | |
3585 | ||
e7b07cee HW |
3586 | update_stream_scaling_settings(&mode, dm_state, stream); |
3587 | ||
3588 | fill_audio_info( | |
3589 | &stream->audio_info, | |
3590 | drm_connector, | |
aed15309 | 3591 | sink); |
e7b07cee | 3592 | |
ceb3dbb4 | 3593 | update_stream_signal(stream, sink); |
9182b4cb | 3594 | |
aed15309 | 3595 | finish: |
dcd5fb82 | 3596 | dc_sink_release(sink); |
9e3efe3e | 3597 | |
e7b07cee HW |
3598 | return stream; |
3599 | } | |
3600 | ||
7578ecda | 3601 | static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) |
e7b07cee HW |
3602 | { |
3603 | drm_crtc_cleanup(crtc); | |
3604 | kfree(crtc); | |
3605 | } | |
3606 | ||
3607 | static void dm_crtc_destroy_state(struct drm_crtc *crtc, | |
3ee6b26b | 3608 | struct drm_crtc_state *state) |
e7b07cee HW |
3609 | { |
3610 | struct dm_crtc_state *cur = to_dm_crtc_state(state); | |
3611 | ||
3612 | /* TODO Destroy dc_stream objects are stream object is flattened */ | |
3613 | if (cur->stream) | |
3614 | dc_stream_release(cur->stream); | |
3615 | ||
3616 | ||
3617 | __drm_atomic_helper_crtc_destroy_state(state); | |
3618 | ||
3619 | ||
3620 | kfree(state); | |
3621 | } | |
3622 | ||
3623 | static void dm_crtc_reset_state(struct drm_crtc *crtc) | |
3624 | { | |
3625 | struct dm_crtc_state *state; | |
3626 | ||
3627 | if (crtc->state) | |
3628 | dm_crtc_destroy_state(crtc, crtc->state); | |
3629 | ||
3630 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
3631 | if (WARN_ON(!state)) | |
3632 | return; | |
3633 | ||
3634 | crtc->state = &state->base; | |
3635 | crtc->state->crtc = crtc; | |
3636 | ||
3637 | } | |
3638 | ||
3639 | static struct drm_crtc_state * | |
3640 | dm_crtc_duplicate_state(struct drm_crtc *crtc) | |
3641 | { | |
3642 | struct dm_crtc_state *state, *cur; | |
3643 | ||
3644 | cur = to_dm_crtc_state(crtc->state); | |
3645 | ||
3646 | if (WARN_ON(!crtc->state)) | |
3647 | return NULL; | |
3648 | ||
2004f45e | 3649 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
2a55f096 ES |
3650 | if (!state) |
3651 | return NULL; | |
e7b07cee HW |
3652 | |
3653 | __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); | |
3654 | ||
3655 | if (cur->stream) { | |
3656 | state->stream = cur->stream; | |
3657 | dc_stream_retain(state->stream); | |
3658 | } | |
3659 | ||
d6ef9b41 NK |
3660 | state->active_planes = cur->active_planes; |
3661 | state->interrupts_enabled = cur->interrupts_enabled; | |
180db303 | 3662 | state->vrr_params = cur->vrr_params; |
98e6436d | 3663 | state->vrr_infopacket = cur->vrr_infopacket; |
c1ee92f9 | 3664 | state->abm_level = cur->abm_level; |
bb47de73 NK |
3665 | state->vrr_supported = cur->vrr_supported; |
3666 | state->freesync_config = cur->freesync_config; | |
14b25846 | 3667 | state->crc_src = cur->crc_src; |
cf020d49 NK |
3668 | state->cm_has_degamma = cur->cm_has_degamma; |
3669 | state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; | |
98e6436d | 3670 | |
e7b07cee HW |
3671 | /* TODO Duplicate dc_stream after objects are stream object is flattened */ |
3672 | ||
3673 | return &state->base; | |
3674 | } | |
3675 | ||
d2574c33 MK |
3676 | static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) |
3677 | { | |
3678 | enum dc_irq_source irq_source; | |
3679 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
3680 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
3681 | int rc; | |
3682 | ||
3683 | irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; | |
3684 | ||
3685 | rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; | |
3686 | ||
3687 | DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n", | |
3688 | acrtc->crtc_id, enable ? "en" : "dis", rc); | |
3689 | return rc; | |
3690 | } | |
589d2739 HW |
3691 | |
3692 | static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) | |
3693 | { | |
3694 | enum dc_irq_source irq_source; | |
3695 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
3696 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
d2574c33 MK |
3697 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); |
3698 | int rc = 0; | |
3699 | ||
3700 | if (enable) { | |
3701 | /* vblank irq on -> Only need vupdate irq in vrr mode */ | |
3702 | if (amdgpu_dm_vrr_active(acrtc_state)) | |
3703 | rc = dm_set_vupdate_irq(crtc, true); | |
3704 | } else { | |
3705 | /* vblank irq off -> vupdate irq off */ | |
3706 | rc = dm_set_vupdate_irq(crtc, false); | |
3707 | } | |
3708 | ||
3709 | if (rc) | |
3710 | return rc; | |
589d2739 HW |
3711 | |
3712 | irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; | |
a0e30392 | 3713 | return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; |
589d2739 HW |
3714 | } |
3715 | ||
3716 | static int dm_enable_vblank(struct drm_crtc *crtc) | |
3717 | { | |
3718 | return dm_set_vblank(crtc, true); | |
3719 | } | |
3720 | ||
3721 | static void dm_disable_vblank(struct drm_crtc *crtc) | |
3722 | { | |
3723 | dm_set_vblank(crtc, false); | |
3724 | } | |
3725 | ||
e7b07cee HW |
3726 | /* Implemented only the options currently availible for the driver */ |
3727 | static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { | |
3728 | .reset = dm_crtc_reset_state, | |
3729 | .destroy = amdgpu_dm_crtc_destroy, | |
3730 | .gamma_set = drm_atomic_helper_legacy_gamma_set, | |
3731 | .set_config = drm_atomic_helper_set_config, | |
3732 | .page_flip = drm_atomic_helper_page_flip, | |
3733 | .atomic_duplicate_state = dm_crtc_duplicate_state, | |
3734 | .atomic_destroy_state = dm_crtc_destroy_state, | |
31aec354 | 3735 | .set_crc_source = amdgpu_dm_crtc_set_crc_source, |
3b3b8448 | 3736 | .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, |
8fb843d1 | 3737 | .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, |
589d2739 HW |
3738 | .enable_vblank = dm_enable_vblank, |
3739 | .disable_vblank = dm_disable_vblank, | |
e7b07cee HW |
3740 | }; |
3741 | ||
3742 | static enum drm_connector_status | |
3743 | amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) | |
3744 | { | |
3745 | bool connected; | |
c84dec2f | 3746 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee | 3747 | |
1f6010a9 DF |
3748 | /* |
3749 | * Notes: | |
e7b07cee HW |
3750 | * 1. This interface is NOT called in context of HPD irq. |
3751 | * 2. This interface *is called* in context of user-mode ioctl. Which | |
1f6010a9 DF |
3752 | * makes it a bad place for *any* MST-related activity. |
3753 | */ | |
e7b07cee | 3754 | |
8580d60b HW |
3755 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && |
3756 | !aconnector->fake_enable) | |
e7b07cee HW |
3757 | connected = (aconnector->dc_sink != NULL); |
3758 | else | |
3759 | connected = (aconnector->base.force == DRM_FORCE_ON); | |
3760 | ||
3761 | return (connected ? connector_status_connected : | |
3762 | connector_status_disconnected); | |
3763 | } | |
3764 | ||
3ee6b26b AD |
3765 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
3766 | struct drm_connector_state *connector_state, | |
3767 | struct drm_property *property, | |
3768 | uint64_t val) | |
e7b07cee HW |
3769 | { |
3770 | struct drm_device *dev = connector->dev; | |
3771 | struct amdgpu_device *adev = dev->dev_private; | |
3772 | struct dm_connector_state *dm_old_state = | |
3773 | to_dm_connector_state(connector->state); | |
3774 | struct dm_connector_state *dm_new_state = | |
3775 | to_dm_connector_state(connector_state); | |
3776 | ||
3777 | int ret = -EINVAL; | |
3778 | ||
3779 | if (property == dev->mode_config.scaling_mode_property) { | |
3780 | enum amdgpu_rmx_type rmx_type; | |
3781 | ||
3782 | switch (val) { | |
3783 | case DRM_MODE_SCALE_CENTER: | |
3784 | rmx_type = RMX_CENTER; | |
3785 | break; | |
3786 | case DRM_MODE_SCALE_ASPECT: | |
3787 | rmx_type = RMX_ASPECT; | |
3788 | break; | |
3789 | case DRM_MODE_SCALE_FULLSCREEN: | |
3790 | rmx_type = RMX_FULL; | |
3791 | break; | |
3792 | case DRM_MODE_SCALE_NONE: | |
3793 | default: | |
3794 | rmx_type = RMX_OFF; | |
3795 | break; | |
3796 | } | |
3797 | ||
3798 | if (dm_old_state->scaling == rmx_type) | |
3799 | return 0; | |
3800 | ||
3801 | dm_new_state->scaling = rmx_type; | |
3802 | ret = 0; | |
3803 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
3804 | dm_new_state->underscan_hborder = val; | |
3805 | ret = 0; | |
3806 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
3807 | dm_new_state->underscan_vborder = val; | |
3808 | ret = 0; | |
3809 | } else if (property == adev->mode_info.underscan_property) { | |
3810 | dm_new_state->underscan_enable = val; | |
3811 | ret = 0; | |
c1ee92f9 DF |
3812 | } else if (property == adev->mode_info.abm_level_property) { |
3813 | dm_new_state->abm_level = val; | |
3814 | ret = 0; | |
e7b07cee HW |
3815 | } |
3816 | ||
3817 | return ret; | |
3818 | } | |
3819 | ||
3ee6b26b AD |
3820 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
3821 | const struct drm_connector_state *state, | |
3822 | struct drm_property *property, | |
3823 | uint64_t *val) | |
e7b07cee HW |
3824 | { |
3825 | struct drm_device *dev = connector->dev; | |
3826 | struct amdgpu_device *adev = dev->dev_private; | |
3827 | struct dm_connector_state *dm_state = | |
3828 | to_dm_connector_state(state); | |
3829 | int ret = -EINVAL; | |
3830 | ||
3831 | if (property == dev->mode_config.scaling_mode_property) { | |
3832 | switch (dm_state->scaling) { | |
3833 | case RMX_CENTER: | |
3834 | *val = DRM_MODE_SCALE_CENTER; | |
3835 | break; | |
3836 | case RMX_ASPECT: | |
3837 | *val = DRM_MODE_SCALE_ASPECT; | |
3838 | break; | |
3839 | case RMX_FULL: | |
3840 | *val = DRM_MODE_SCALE_FULLSCREEN; | |
3841 | break; | |
3842 | case RMX_OFF: | |
3843 | default: | |
3844 | *val = DRM_MODE_SCALE_NONE; | |
3845 | break; | |
3846 | } | |
3847 | ret = 0; | |
3848 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
3849 | *val = dm_state->underscan_hborder; | |
3850 | ret = 0; | |
3851 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
3852 | *val = dm_state->underscan_vborder; | |
3853 | ret = 0; | |
3854 | } else if (property == adev->mode_info.underscan_property) { | |
3855 | *val = dm_state->underscan_enable; | |
3856 | ret = 0; | |
c1ee92f9 DF |
3857 | } else if (property == adev->mode_info.abm_level_property) { |
3858 | *val = dm_state->abm_level; | |
3859 | ret = 0; | |
e7b07cee | 3860 | } |
c1ee92f9 | 3861 | |
e7b07cee HW |
3862 | return ret; |
3863 | } | |
3864 | ||
526c654a ED |
3865 | static void amdgpu_dm_connector_unregister(struct drm_connector *connector) |
3866 | { | |
3867 | struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); | |
3868 | ||
3869 | drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); | |
3870 | } | |
3871 | ||
7578ecda | 3872 | static void amdgpu_dm_connector_destroy(struct drm_connector *connector) |
e7b07cee | 3873 | { |
c84dec2f | 3874 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
3875 | const struct dc_link *link = aconnector->dc_link; |
3876 | struct amdgpu_device *adev = connector->dev->dev_private; | |
3877 | struct amdgpu_display_manager *dm = &adev->dm; | |
ada8ce15 | 3878 | |
e7b07cee HW |
3879 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ |
3880 | defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) | |
3881 | ||
89fc8d4e | 3882 | if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && |
5cd29ed0 HW |
3883 | link->type != dc_connection_none && |
3884 | dm->backlight_dev) { | |
3885 | backlight_device_unregister(dm->backlight_dev); | |
3886 | dm->backlight_dev = NULL; | |
e7b07cee HW |
3887 | } |
3888 | #endif | |
dcd5fb82 MF |
3889 | |
3890 | if (aconnector->dc_em_sink) | |
3891 | dc_sink_release(aconnector->dc_em_sink); | |
3892 | aconnector->dc_em_sink = NULL; | |
3893 | if (aconnector->dc_sink) | |
3894 | dc_sink_release(aconnector->dc_sink); | |
3895 | aconnector->dc_sink = NULL; | |
3896 | ||
e86e8947 | 3897 | drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); |
e7b07cee HW |
3898 | drm_connector_unregister(connector); |
3899 | drm_connector_cleanup(connector); | |
526c654a ED |
3900 | if (aconnector->i2c) { |
3901 | i2c_del_adapter(&aconnector->i2c->base); | |
3902 | kfree(aconnector->i2c); | |
3903 | } | |
3904 | ||
e7b07cee HW |
3905 | kfree(connector); |
3906 | } | |
3907 | ||
3908 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) | |
3909 | { | |
3910 | struct dm_connector_state *state = | |
3911 | to_dm_connector_state(connector->state); | |
3912 | ||
df099b9b LSL |
3913 | if (connector->state) |
3914 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
3915 | ||
e7b07cee HW |
3916 | kfree(state); |
3917 | ||
3918 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
3919 | ||
3920 | if (state) { | |
3921 | state->scaling = RMX_OFF; | |
3922 | state->underscan_enable = false; | |
3923 | state->underscan_hborder = 0; | |
3924 | state->underscan_vborder = 0; | |
01933ba4 | 3925 | state->base.max_requested_bpc = 8; |
e7b07cee | 3926 | |
c3e50f89 NK |
3927 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
3928 | state->abm_level = amdgpu_dm_abm_level; | |
3929 | ||
df099b9b | 3930 | __drm_atomic_helper_connector_reset(connector, &state->base); |
e7b07cee HW |
3931 | } |
3932 | } | |
3933 | ||
3ee6b26b AD |
3934 | struct drm_connector_state * |
3935 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) | |
e7b07cee HW |
3936 | { |
3937 | struct dm_connector_state *state = | |
3938 | to_dm_connector_state(connector->state); | |
3939 | ||
3940 | struct dm_connector_state *new_state = | |
3941 | kmemdup(state, sizeof(*state), GFP_KERNEL); | |
3942 | ||
98e6436d AK |
3943 | if (!new_state) |
3944 | return NULL; | |
e7b07cee | 3945 | |
98e6436d AK |
3946 | __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); |
3947 | ||
3948 | new_state->freesync_capable = state->freesync_capable; | |
c1ee92f9 | 3949 | new_state->abm_level = state->abm_level; |
922454c2 NK |
3950 | new_state->scaling = state->scaling; |
3951 | new_state->underscan_enable = state->underscan_enable; | |
3952 | new_state->underscan_hborder = state->underscan_hborder; | |
3953 | new_state->underscan_vborder = state->underscan_vborder; | |
98e6436d AK |
3954 | |
3955 | return &new_state->base; | |
e7b07cee HW |
3956 | } |
3957 | ||
3958 | static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { | |
3959 | .reset = amdgpu_dm_connector_funcs_reset, | |
3960 | .detect = amdgpu_dm_connector_detect, | |
3961 | .fill_modes = drm_helper_probe_single_connector_modes, | |
3962 | .destroy = amdgpu_dm_connector_destroy, | |
3963 | .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, | |
3964 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
3965 | .atomic_set_property = amdgpu_dm_connector_atomic_set_property, | |
526c654a ED |
3966 | .atomic_get_property = amdgpu_dm_connector_atomic_get_property, |
3967 | .early_unregister = amdgpu_dm_connector_unregister | |
e7b07cee HW |
3968 | }; |
3969 | ||
e7b07cee HW |
3970 | static int get_modes(struct drm_connector *connector) |
3971 | { | |
3972 | return amdgpu_dm_connector_get_modes(connector); | |
3973 | } | |
3974 | ||
c84dec2f | 3975 | static void create_eml_sink(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
3976 | { |
3977 | struct dc_sink_init_data init_params = { | |
3978 | .link = aconnector->dc_link, | |
3979 | .sink_signal = SIGNAL_TYPE_VIRTUAL | |
3980 | }; | |
70e8ffc5 | 3981 | struct edid *edid; |
e7b07cee | 3982 | |
a89ff457 | 3983 | if (!aconnector->base.edid_blob_ptr) { |
e7b07cee HW |
3984 | DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", |
3985 | aconnector->base.name); | |
3986 | ||
3987 | aconnector->base.force = DRM_FORCE_OFF; | |
3988 | aconnector->base.override_edid = false; | |
3989 | return; | |
3990 | } | |
3991 | ||
70e8ffc5 HW |
3992 | edid = (struct edid *) aconnector->base.edid_blob_ptr->data; |
3993 | ||
e7b07cee HW |
3994 | aconnector->edid = edid; |
3995 | ||
3996 | aconnector->dc_em_sink = dc_link_add_remote_sink( | |
3997 | aconnector->dc_link, | |
3998 | (uint8_t *)edid, | |
3999 | (edid->extensions + 1) * EDID_LENGTH, | |
4000 | &init_params); | |
4001 | ||
dcd5fb82 | 4002 | if (aconnector->base.force == DRM_FORCE_ON) { |
e7b07cee HW |
4003 | aconnector->dc_sink = aconnector->dc_link->local_sink ? |
4004 | aconnector->dc_link->local_sink : | |
4005 | aconnector->dc_em_sink; | |
dcd5fb82 MF |
4006 | dc_sink_retain(aconnector->dc_sink); |
4007 | } | |
e7b07cee HW |
4008 | } |
4009 | ||
c84dec2f | 4010 | static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
4011 | { |
4012 | struct dc_link *link = (struct dc_link *)aconnector->dc_link; | |
4013 | ||
1f6010a9 DF |
4014 | /* |
4015 | * In case of headless boot with force on for DP managed connector | |
e7b07cee HW |
4016 | * Those settings have to be != 0 to get initial modeset |
4017 | */ | |
4018 | if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
4019 | link->verified_link_cap.lane_count = LANE_COUNT_FOUR; | |
4020 | link->verified_link_cap.link_rate = LINK_RATE_HIGH2; | |
4021 | } | |
4022 | ||
4023 | ||
4024 | aconnector->base.override_edid = true; | |
4025 | create_eml_sink(aconnector); | |
4026 | } | |
4027 | ||
ba9ca088 | 4028 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
3ee6b26b | 4029 | struct drm_display_mode *mode) |
e7b07cee HW |
4030 | { |
4031 | int result = MODE_ERROR; | |
4032 | struct dc_sink *dc_sink; | |
4033 | struct amdgpu_device *adev = connector->dev->dev_private; | |
4034 | /* TODO: Unhardcode stream count */ | |
0971c40e | 4035 | struct dc_stream_state *stream; |
c84dec2f | 4036 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
a39438f0 | 4037 | enum dc_status dc_result = DC_OK; |
e7b07cee HW |
4038 | |
4039 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
4040 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) | |
4041 | return result; | |
4042 | ||
1f6010a9 DF |
4043 | /* |
4044 | * Only run this the first time mode_valid is called to initilialize | |
e7b07cee HW |
4045 | * EDID mgmt |
4046 | */ | |
4047 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && | |
4048 | !aconnector->dc_em_sink) | |
4049 | handle_edid_mgmt(aconnector); | |
4050 | ||
c84dec2f | 4051 | dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; |
e7b07cee | 4052 | |
b830ebc9 | 4053 | if (dc_sink == NULL) { |
e7b07cee HW |
4054 | DRM_ERROR("dc_sink is NULL!\n"); |
4055 | goto fail; | |
4056 | } | |
4057 | ||
b333730d | 4058 | stream = create_stream_for_sink(aconnector, mode, NULL, NULL); |
b830ebc9 | 4059 | if (stream == NULL) { |
e7b07cee HW |
4060 | DRM_ERROR("Failed to create stream for sink!\n"); |
4061 | goto fail; | |
4062 | } | |
4063 | ||
a39438f0 HW |
4064 | dc_result = dc_validate_stream(adev->dm.dc, stream); |
4065 | ||
4066 | if (dc_result == DC_OK) | |
e7b07cee | 4067 | result = MODE_OK; |
a39438f0 | 4068 | else |
9f921b14 | 4069 | DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", |
a39438f0 HW |
4070 | mode->vdisplay, |
4071 | mode->hdisplay, | |
9f921b14 HW |
4072 | mode->clock, |
4073 | dc_result); | |
e7b07cee HW |
4074 | |
4075 | dc_stream_release(stream); | |
4076 | ||
4077 | fail: | |
4078 | /* TODO: error handling*/ | |
4079 | return result; | |
4080 | } | |
4081 | ||
88694af9 NK |
4082 | static int fill_hdr_info_packet(const struct drm_connector_state *state, |
4083 | struct dc_info_packet *out) | |
4084 | { | |
4085 | struct hdmi_drm_infoframe frame; | |
4086 | unsigned char buf[30]; /* 26 + 4 */ | |
4087 | ssize_t len; | |
4088 | int ret, i; | |
4089 | ||
4090 | memset(out, 0, sizeof(*out)); | |
4091 | ||
4092 | if (!state->hdr_output_metadata) | |
4093 | return 0; | |
4094 | ||
4095 | ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); | |
4096 | if (ret) | |
4097 | return ret; | |
4098 | ||
4099 | len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); | |
4100 | if (len < 0) | |
4101 | return (int)len; | |
4102 | ||
4103 | /* Static metadata is a fixed 26 bytes + 4 byte header. */ | |
4104 | if (len != 30) | |
4105 | return -EINVAL; | |
4106 | ||
4107 | /* Prepare the infopacket for DC. */ | |
4108 | switch (state->connector->connector_type) { | |
4109 | case DRM_MODE_CONNECTOR_HDMIA: | |
4110 | out->hb0 = 0x87; /* type */ | |
4111 | out->hb1 = 0x01; /* version */ | |
4112 | out->hb2 = 0x1A; /* length */ | |
4113 | out->sb[0] = buf[3]; /* checksum */ | |
4114 | i = 1; | |
4115 | break; | |
4116 | ||
4117 | case DRM_MODE_CONNECTOR_DisplayPort: | |
4118 | case DRM_MODE_CONNECTOR_eDP: | |
4119 | out->hb0 = 0x00; /* sdp id, zero */ | |
4120 | out->hb1 = 0x87; /* type */ | |
4121 | out->hb2 = 0x1D; /* payload len - 1 */ | |
4122 | out->hb3 = (0x13 << 2); /* sdp version */ | |
4123 | out->sb[0] = 0x01; /* version */ | |
4124 | out->sb[1] = 0x1A; /* length */ | |
4125 | i = 2; | |
4126 | break; | |
4127 | ||
4128 | default: | |
4129 | return -EINVAL; | |
4130 | } | |
4131 | ||
4132 | memcpy(&out->sb[i], &buf[4], 26); | |
4133 | out->valid = true; | |
4134 | ||
4135 | print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, | |
4136 | sizeof(out->sb), false); | |
4137 | ||
4138 | return 0; | |
4139 | } | |
4140 | ||
4141 | static bool | |
4142 | is_hdr_metadata_different(const struct drm_connector_state *old_state, | |
4143 | const struct drm_connector_state *new_state) | |
4144 | { | |
4145 | struct drm_property_blob *old_blob = old_state->hdr_output_metadata; | |
4146 | struct drm_property_blob *new_blob = new_state->hdr_output_metadata; | |
4147 | ||
4148 | if (old_blob != new_blob) { | |
4149 | if (old_blob && new_blob && | |
4150 | old_blob->length == new_blob->length) | |
4151 | return memcmp(old_blob->data, new_blob->data, | |
4152 | old_blob->length); | |
4153 | ||
4154 | return true; | |
4155 | } | |
4156 | ||
4157 | return false; | |
4158 | } | |
4159 | ||
4160 | static int | |
4161 | amdgpu_dm_connector_atomic_check(struct drm_connector *conn, | |
51e857af | 4162 | struct drm_atomic_state *state) |
88694af9 | 4163 | { |
51e857af SP |
4164 | struct drm_connector_state *new_con_state = |
4165 | drm_atomic_get_new_connector_state(state, conn); | |
88694af9 NK |
4166 | struct drm_connector_state *old_con_state = |
4167 | drm_atomic_get_old_connector_state(state, conn); | |
4168 | struct drm_crtc *crtc = new_con_state->crtc; | |
4169 | struct drm_crtc_state *new_crtc_state; | |
4170 | int ret; | |
4171 | ||
4172 | if (!crtc) | |
4173 | return 0; | |
4174 | ||
4175 | if (is_hdr_metadata_different(old_con_state, new_con_state)) { | |
4176 | struct dc_info_packet hdr_infopacket; | |
4177 | ||
4178 | ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); | |
4179 | if (ret) | |
4180 | return ret; | |
4181 | ||
4182 | new_crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
4183 | if (IS_ERR(new_crtc_state)) | |
4184 | return PTR_ERR(new_crtc_state); | |
4185 | ||
4186 | /* | |
4187 | * DC considers the stream backends changed if the | |
4188 | * static metadata changes. Forcing the modeset also | |
4189 | * gives a simple way for userspace to switch from | |
b232d4ed NK |
4190 | * 8bpc to 10bpc when setting the metadata to enter |
4191 | * or exit HDR. | |
4192 | * | |
4193 | * Changing the static metadata after it's been | |
4194 | * set is permissible, however. So only force a | |
4195 | * modeset if we're entering or exiting HDR. | |
88694af9 | 4196 | */ |
b232d4ed NK |
4197 | new_crtc_state->mode_changed = |
4198 | !old_con_state->hdr_output_metadata || | |
4199 | !new_con_state->hdr_output_metadata; | |
88694af9 NK |
4200 | } |
4201 | ||
4202 | return 0; | |
4203 | } | |
4204 | ||
e7b07cee HW |
4205 | static const struct drm_connector_helper_funcs |
4206 | amdgpu_dm_connector_helper_funcs = { | |
4207 | /* | |
1f6010a9 | 4208 | * If hotplugging a second bigger display in FB Con mode, bigger resolution |
b830ebc9 | 4209 | * modes will be filtered by drm_mode_validate_size(), and those modes |
1f6010a9 | 4210 | * are missing after user start lightdm. So we need to renew modes list. |
b830ebc9 HW |
4211 | * in get_modes call back, not just return the modes count |
4212 | */ | |
e7b07cee HW |
4213 | .get_modes = get_modes, |
4214 | .mode_valid = amdgpu_dm_connector_mode_valid, | |
88694af9 | 4215 | .atomic_check = amdgpu_dm_connector_atomic_check, |
e7b07cee HW |
4216 | }; |
4217 | ||
4218 | static void dm_crtc_helper_disable(struct drm_crtc *crtc) | |
4219 | { | |
4220 | } | |
4221 | ||
bc92c065 NK |
4222 | static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state) |
4223 | { | |
4224 | struct drm_device *dev = new_crtc_state->crtc->dev; | |
4225 | struct drm_plane *plane; | |
4226 | ||
4227 | drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) { | |
4228 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
4229 | return true; | |
4230 | } | |
4231 | ||
4232 | return false; | |
4233 | } | |
4234 | ||
d6ef9b41 | 4235 | static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) |
c14a005c NK |
4236 | { |
4237 | struct drm_atomic_state *state = new_crtc_state->state; | |
4238 | struct drm_plane *plane; | |
4239 | int num_active = 0; | |
4240 | ||
4241 | drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { | |
4242 | struct drm_plane_state *new_plane_state; | |
4243 | ||
4244 | /* Cursor planes are "fake". */ | |
4245 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
4246 | continue; | |
4247 | ||
4248 | new_plane_state = drm_atomic_get_new_plane_state(state, plane); | |
4249 | ||
4250 | if (!new_plane_state) { | |
4251 | /* | |
4252 | * The plane is enable on the CRTC and hasn't changed | |
4253 | * state. This means that it previously passed | |
4254 | * validation and is therefore enabled. | |
4255 | */ | |
4256 | num_active += 1; | |
4257 | continue; | |
4258 | } | |
4259 | ||
4260 | /* We need a framebuffer to be considered enabled. */ | |
4261 | num_active += (new_plane_state->fb != NULL); | |
4262 | } | |
4263 | ||
d6ef9b41 NK |
4264 | return num_active; |
4265 | } | |
4266 | ||
4267 | /* | |
4268 | * Sets whether interrupts should be enabled on a specific CRTC. | |
4269 | * We require that the stream be enabled and that there exist active | |
4270 | * DC planes on the stream. | |
4271 | */ | |
4272 | static void | |
4273 | dm_update_crtc_interrupt_state(struct drm_crtc *crtc, | |
4274 | struct drm_crtc_state *new_crtc_state) | |
4275 | { | |
4276 | struct dm_crtc_state *dm_new_crtc_state = | |
4277 | to_dm_crtc_state(new_crtc_state); | |
4278 | ||
4279 | dm_new_crtc_state->active_planes = 0; | |
4280 | dm_new_crtc_state->interrupts_enabled = false; | |
4281 | ||
4282 | if (!dm_new_crtc_state->stream) | |
4283 | return; | |
4284 | ||
4285 | dm_new_crtc_state->active_planes = | |
4286 | count_crtc_active_planes(new_crtc_state); | |
4287 | ||
4288 | dm_new_crtc_state->interrupts_enabled = | |
4289 | dm_new_crtc_state->active_planes > 0; | |
c14a005c NK |
4290 | } |
4291 | ||
3ee6b26b AD |
4292 | static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, |
4293 | struct drm_crtc_state *state) | |
e7b07cee HW |
4294 | { |
4295 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
4296 | struct dc *dc = adev->dm.dc; | |
4297 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); | |
4298 | int ret = -EINVAL; | |
4299 | ||
d6ef9b41 NK |
4300 | /* |
4301 | * Update interrupt state for the CRTC. This needs to happen whenever | |
4302 | * the CRTC has changed or whenever any of its planes have changed. | |
4303 | * Atomic check satisfies both of these requirements since the CRTC | |
4304 | * is added to the state by DRM during drm_atomic_helper_check_planes. | |
4305 | */ | |
4306 | dm_update_crtc_interrupt_state(crtc, state); | |
4307 | ||
9b690ef3 BL |
4308 | if (unlikely(!dm_crtc_state->stream && |
4309 | modeset_required(state, NULL, dm_crtc_state->stream))) { | |
e7b07cee HW |
4310 | WARN_ON(1); |
4311 | return ret; | |
4312 | } | |
4313 | ||
1f6010a9 | 4314 | /* In some use cases, like reset, no stream is attached */ |
e7b07cee HW |
4315 | if (!dm_crtc_state->stream) |
4316 | return 0; | |
4317 | ||
bc92c065 NK |
4318 | /* |
4319 | * We want at least one hardware plane enabled to use | |
4320 | * the stream with a cursor enabled. | |
4321 | */ | |
c14a005c | 4322 | if (state->enable && state->active && |
bc92c065 | 4323 | does_crtc_have_active_cursor(state) && |
d6ef9b41 | 4324 | dm_crtc_state->active_planes == 0) |
c14a005c NK |
4325 | return -EINVAL; |
4326 | ||
62c933f9 | 4327 | if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) |
e7b07cee HW |
4328 | return 0; |
4329 | ||
4330 | return ret; | |
4331 | } | |
4332 | ||
3ee6b26b AD |
4333 | static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, |
4334 | const struct drm_display_mode *mode, | |
4335 | struct drm_display_mode *adjusted_mode) | |
e7b07cee HW |
4336 | { |
4337 | return true; | |
4338 | } | |
4339 | ||
4340 | static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { | |
4341 | .disable = dm_crtc_helper_disable, | |
4342 | .atomic_check = dm_crtc_helper_atomic_check, | |
4343 | .mode_fixup = dm_crtc_helper_mode_fixup | |
4344 | }; | |
4345 | ||
4346 | static void dm_encoder_helper_disable(struct drm_encoder *encoder) | |
4347 | { | |
4348 | ||
4349 | } | |
4350 | ||
3ee6b26b AD |
4351 | static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, |
4352 | struct drm_crtc_state *crtc_state, | |
4353 | struct drm_connector_state *conn_state) | |
e7b07cee HW |
4354 | { |
4355 | return 0; | |
4356 | } | |
4357 | ||
4358 | const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { | |
4359 | .disable = dm_encoder_helper_disable, | |
4360 | .atomic_check = dm_encoder_helper_atomic_check | |
4361 | }; | |
4362 | ||
4363 | static void dm_drm_plane_reset(struct drm_plane *plane) | |
4364 | { | |
4365 | struct dm_plane_state *amdgpu_state = NULL; | |
4366 | ||
4367 | if (plane->state) | |
4368 | plane->funcs->atomic_destroy_state(plane, plane->state); | |
4369 | ||
4370 | amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); | |
f922237d | 4371 | WARN_ON(amdgpu_state == NULL); |
1f6010a9 | 4372 | |
7ddaef96 NK |
4373 | if (amdgpu_state) |
4374 | __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); | |
e7b07cee HW |
4375 | } |
4376 | ||
4377 | static struct drm_plane_state * | |
4378 | dm_drm_plane_duplicate_state(struct drm_plane *plane) | |
4379 | { | |
4380 | struct dm_plane_state *dm_plane_state, *old_dm_plane_state; | |
4381 | ||
4382 | old_dm_plane_state = to_dm_plane_state(plane->state); | |
4383 | dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); | |
4384 | if (!dm_plane_state) | |
4385 | return NULL; | |
4386 | ||
4387 | __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); | |
4388 | ||
3be5262e HW |
4389 | if (old_dm_plane_state->dc_state) { |
4390 | dm_plane_state->dc_state = old_dm_plane_state->dc_state; | |
4391 | dc_plane_state_retain(dm_plane_state->dc_state); | |
e7b07cee HW |
4392 | } |
4393 | ||
4394 | return &dm_plane_state->base; | |
4395 | } | |
4396 | ||
4397 | void dm_drm_plane_destroy_state(struct drm_plane *plane, | |
3ee6b26b | 4398 | struct drm_plane_state *state) |
e7b07cee HW |
4399 | { |
4400 | struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); | |
4401 | ||
3be5262e HW |
4402 | if (dm_plane_state->dc_state) |
4403 | dc_plane_state_release(dm_plane_state->dc_state); | |
e7b07cee | 4404 | |
0627bbd3 | 4405 | drm_atomic_helper_plane_destroy_state(plane, state); |
e7b07cee HW |
4406 | } |
4407 | ||
4408 | static const struct drm_plane_funcs dm_plane_funcs = { | |
4409 | .update_plane = drm_atomic_helper_update_plane, | |
4410 | .disable_plane = drm_atomic_helper_disable_plane, | |
02680efb | 4411 | .destroy = drm_primary_helper_destroy, |
e7b07cee HW |
4412 | .reset = dm_drm_plane_reset, |
4413 | .atomic_duplicate_state = dm_drm_plane_duplicate_state, | |
4414 | .atomic_destroy_state = dm_drm_plane_destroy_state, | |
4415 | }; | |
4416 | ||
3ee6b26b AD |
4417 | static int dm_plane_helper_prepare_fb(struct drm_plane *plane, |
4418 | struct drm_plane_state *new_state) | |
e7b07cee HW |
4419 | { |
4420 | struct amdgpu_framebuffer *afb; | |
4421 | struct drm_gem_object *obj; | |
5d43be0c | 4422 | struct amdgpu_device *adev; |
e7b07cee | 4423 | struct amdgpu_bo *rbo; |
e7b07cee | 4424 | struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; |
0f257b09 CZ |
4425 | struct list_head list; |
4426 | struct ttm_validate_buffer tv; | |
4427 | struct ww_acquire_ctx ticket; | |
e0634e8d | 4428 | uint64_t tiling_flags; |
5d43be0c CK |
4429 | uint32_t domain; |
4430 | int r; | |
e7b07cee HW |
4431 | |
4432 | dm_plane_state_old = to_dm_plane_state(plane->state); | |
4433 | dm_plane_state_new = to_dm_plane_state(new_state); | |
4434 | ||
4435 | if (!new_state->fb) { | |
f1ad2f5e | 4436 | DRM_DEBUG_DRIVER("No FB bound\n"); |
e7b07cee HW |
4437 | return 0; |
4438 | } | |
4439 | ||
4440 | afb = to_amdgpu_framebuffer(new_state->fb); | |
e68d14dd | 4441 | obj = new_state->fb->obj[0]; |
e7b07cee | 4442 | rbo = gem_to_amdgpu_bo(obj); |
5d43be0c | 4443 | adev = amdgpu_ttm_adev(rbo->tbo.bdev); |
0f257b09 CZ |
4444 | INIT_LIST_HEAD(&list); |
4445 | ||
4446 | tv.bo = &rbo->tbo; | |
4447 | tv.num_shared = 1; | |
4448 | list_add(&tv.head, &list); | |
4449 | ||
4450 | r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true); | |
4451 | if (r) { | |
4452 | dev_err(adev->dev, "fail to reserve bo (%d)\n", r); | |
e7b07cee | 4453 | return r; |
0f257b09 | 4454 | } |
e7b07cee | 4455 | |
5d43be0c | 4456 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
f2bd8a0e | 4457 | domain = amdgpu_display_supported_domains(adev, rbo->flags); |
5d43be0c CK |
4458 | else |
4459 | domain = AMDGPU_GEM_DOMAIN_VRAM; | |
e7b07cee | 4460 | |
7b7c6c81 | 4461 | r = amdgpu_bo_pin(rbo, domain); |
e7b07cee | 4462 | if (unlikely(r != 0)) { |
30b7c614 HW |
4463 | if (r != -ERESTARTSYS) |
4464 | DRM_ERROR("Failed to pin framebuffer with error %d\n", r); | |
0f257b09 | 4465 | ttm_eu_backoff_reservation(&ticket, &list); |
e7b07cee HW |
4466 | return r; |
4467 | } | |
4468 | ||
bb812f1e JZ |
4469 | r = amdgpu_ttm_alloc_gart(&rbo->tbo); |
4470 | if (unlikely(r != 0)) { | |
4471 | amdgpu_bo_unpin(rbo); | |
0f257b09 | 4472 | ttm_eu_backoff_reservation(&ticket, &list); |
bb812f1e | 4473 | DRM_ERROR("%p bind failed\n", rbo); |
e7b07cee HW |
4474 | return r; |
4475 | } | |
7df7e505 NK |
4476 | |
4477 | amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); | |
4478 | ||
0f257b09 | 4479 | ttm_eu_backoff_reservation(&ticket, &list); |
bb812f1e | 4480 | |
7b7c6c81 | 4481 | afb->address = amdgpu_bo_gpu_offset(rbo); |
e7b07cee HW |
4482 | |
4483 | amdgpu_bo_ref(rbo); | |
4484 | ||
3be5262e HW |
4485 | if (dm_plane_state_new->dc_state && |
4486 | dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { | |
4487 | struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; | |
e7b07cee | 4488 | |
320932bf | 4489 | fill_plane_buffer_attributes( |
695af5f9 NK |
4490 | adev, afb, plane_state->format, plane_state->rotation, |
4491 | tiling_flags, &plane_state->tiling_info, | |
320932bf | 4492 | &plane_state->plane_size, &plane_state->dcc, |
695af5f9 | 4493 | &plane_state->address); |
e7b07cee HW |
4494 | } |
4495 | ||
e7b07cee HW |
4496 | return 0; |
4497 | } | |
4498 | ||
3ee6b26b AD |
4499 | static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, |
4500 | struct drm_plane_state *old_state) | |
e7b07cee HW |
4501 | { |
4502 | struct amdgpu_bo *rbo; | |
e7b07cee HW |
4503 | int r; |
4504 | ||
4505 | if (!old_state->fb) | |
4506 | return; | |
4507 | ||
e68d14dd | 4508 | rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); |
e7b07cee HW |
4509 | r = amdgpu_bo_reserve(rbo, false); |
4510 | if (unlikely(r)) { | |
4511 | DRM_ERROR("failed to reserve rbo before unpin\n"); | |
4512 | return; | |
b830ebc9 HW |
4513 | } |
4514 | ||
4515 | amdgpu_bo_unpin(rbo); | |
4516 | amdgpu_bo_unreserve(rbo); | |
4517 | amdgpu_bo_unref(&rbo); | |
e7b07cee HW |
4518 | } |
4519 | ||
7578ecda AD |
4520 | static int dm_plane_atomic_check(struct drm_plane *plane, |
4521 | struct drm_plane_state *state) | |
cbd19488 AG |
4522 | { |
4523 | struct amdgpu_device *adev = plane->dev->dev_private; | |
4524 | struct dc *dc = adev->dm.dc; | |
78171832 | 4525 | struct dm_plane_state *dm_plane_state; |
695af5f9 NK |
4526 | struct dc_scaling_info scaling_info; |
4527 | int ret; | |
78171832 NK |
4528 | |
4529 | dm_plane_state = to_dm_plane_state(state); | |
cbd19488 | 4530 | |
3be5262e | 4531 | if (!dm_plane_state->dc_state) |
9a3329b1 | 4532 | return 0; |
cbd19488 | 4533 | |
695af5f9 NK |
4534 | ret = fill_dc_scaling_info(state, &scaling_info); |
4535 | if (ret) | |
4536 | return ret; | |
a05bcff1 | 4537 | |
62c933f9 | 4538 | if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) |
cbd19488 AG |
4539 | return 0; |
4540 | ||
4541 | return -EINVAL; | |
4542 | } | |
4543 | ||
674e78ac NK |
4544 | static int dm_plane_atomic_async_check(struct drm_plane *plane, |
4545 | struct drm_plane_state *new_plane_state) | |
4546 | { | |
4547 | /* Only support async updates on cursor planes. */ | |
4548 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
4549 | return -EINVAL; | |
4550 | ||
4551 | return 0; | |
4552 | } | |
4553 | ||
4554 | static void dm_plane_atomic_async_update(struct drm_plane *plane, | |
4555 | struct drm_plane_state *new_state) | |
4556 | { | |
4557 | struct drm_plane_state *old_state = | |
4558 | drm_atomic_get_old_plane_state(new_state->state, plane); | |
4559 | ||
332af874 | 4560 | swap(plane->state->fb, new_state->fb); |
674e78ac NK |
4561 | |
4562 | plane->state->src_x = new_state->src_x; | |
4563 | plane->state->src_y = new_state->src_y; | |
4564 | plane->state->src_w = new_state->src_w; | |
4565 | plane->state->src_h = new_state->src_h; | |
4566 | plane->state->crtc_x = new_state->crtc_x; | |
4567 | plane->state->crtc_y = new_state->crtc_y; | |
4568 | plane->state->crtc_w = new_state->crtc_w; | |
4569 | plane->state->crtc_h = new_state->crtc_h; | |
4570 | ||
4571 | handle_cursor_update(plane, old_state); | |
4572 | } | |
4573 | ||
e7b07cee HW |
4574 | static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { |
4575 | .prepare_fb = dm_plane_helper_prepare_fb, | |
4576 | .cleanup_fb = dm_plane_helper_cleanup_fb, | |
cbd19488 | 4577 | .atomic_check = dm_plane_atomic_check, |
674e78ac NK |
4578 | .atomic_async_check = dm_plane_atomic_async_check, |
4579 | .atomic_async_update = dm_plane_atomic_async_update | |
e7b07cee HW |
4580 | }; |
4581 | ||
4582 | /* | |
4583 | * TODO: these are currently initialized to rgb formats only. | |
4584 | * For future use cases we should either initialize them dynamically based on | |
4585 | * plane capabilities, or initialize this array to all formats, so internal drm | |
1f6010a9 | 4586 | * check will succeed, and let DC implement proper check |
e7b07cee | 4587 | */ |
d90371b0 | 4588 | static const uint32_t rgb_formats[] = { |
e7b07cee HW |
4589 | DRM_FORMAT_XRGB8888, |
4590 | DRM_FORMAT_ARGB8888, | |
4591 | DRM_FORMAT_RGBA8888, | |
4592 | DRM_FORMAT_XRGB2101010, | |
4593 | DRM_FORMAT_XBGR2101010, | |
4594 | DRM_FORMAT_ARGB2101010, | |
4595 | DRM_FORMAT_ABGR2101010, | |
bcd47f60 MR |
4596 | DRM_FORMAT_XBGR8888, |
4597 | DRM_FORMAT_ABGR8888, | |
46dd9ff7 | 4598 | DRM_FORMAT_RGB565, |
e7b07cee HW |
4599 | }; |
4600 | ||
0d579c7e NK |
4601 | static const uint32_t overlay_formats[] = { |
4602 | DRM_FORMAT_XRGB8888, | |
4603 | DRM_FORMAT_ARGB8888, | |
4604 | DRM_FORMAT_RGBA8888, | |
4605 | DRM_FORMAT_XBGR8888, | |
4606 | DRM_FORMAT_ABGR8888, | |
7267a1a9 | 4607 | DRM_FORMAT_RGB565 |
e7b07cee HW |
4608 | }; |
4609 | ||
4610 | static const u32 cursor_formats[] = { | |
4611 | DRM_FORMAT_ARGB8888 | |
4612 | }; | |
4613 | ||
37c6a93b NK |
4614 | static int get_plane_formats(const struct drm_plane *plane, |
4615 | const struct dc_plane_cap *plane_cap, | |
4616 | uint32_t *formats, int max_formats) | |
e7b07cee | 4617 | { |
37c6a93b NK |
4618 | int i, num_formats = 0; |
4619 | ||
4620 | /* | |
4621 | * TODO: Query support for each group of formats directly from | |
4622 | * DC plane caps. This will require adding more formats to the | |
4623 | * caps list. | |
4624 | */ | |
e7b07cee | 4625 | |
f180b4bc | 4626 | switch (plane->type) { |
e7b07cee | 4627 | case DRM_PLANE_TYPE_PRIMARY: |
37c6a93b NK |
4628 | for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) { |
4629 | if (num_formats >= max_formats) | |
4630 | break; | |
4631 | ||
4632 | formats[num_formats++] = rgb_formats[i]; | |
4633 | } | |
4634 | ||
ea36ad34 | 4635 | if (plane_cap && plane_cap->pixel_format_support.nv12) |
37c6a93b | 4636 | formats[num_formats++] = DRM_FORMAT_NV12; |
e7b07cee | 4637 | break; |
37c6a93b | 4638 | |
e7b07cee | 4639 | case DRM_PLANE_TYPE_OVERLAY: |
37c6a93b NK |
4640 | for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) { |
4641 | if (num_formats >= max_formats) | |
4642 | break; | |
4643 | ||
4644 | formats[num_formats++] = overlay_formats[i]; | |
4645 | } | |
e7b07cee | 4646 | break; |
37c6a93b | 4647 | |
e7b07cee | 4648 | case DRM_PLANE_TYPE_CURSOR: |
37c6a93b NK |
4649 | for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) { |
4650 | if (num_formats >= max_formats) | |
4651 | break; | |
4652 | ||
4653 | formats[num_formats++] = cursor_formats[i]; | |
4654 | } | |
e7b07cee HW |
4655 | break; |
4656 | } | |
4657 | ||
37c6a93b NK |
4658 | return num_formats; |
4659 | } | |
4660 | ||
4661 | static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, | |
4662 | struct drm_plane *plane, | |
4663 | unsigned long possible_crtcs, | |
4664 | const struct dc_plane_cap *plane_cap) | |
4665 | { | |
4666 | uint32_t formats[32]; | |
4667 | int num_formats; | |
4668 | int res = -EPERM; | |
4669 | ||
4670 | num_formats = get_plane_formats(plane, plane_cap, formats, | |
4671 | ARRAY_SIZE(formats)); | |
4672 | ||
4673 | res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs, | |
4674 | &dm_plane_funcs, formats, num_formats, | |
4675 | NULL, plane->type, NULL); | |
4676 | if (res) | |
4677 | return res; | |
4678 | ||
cc1fec57 NK |
4679 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && |
4680 | plane_cap && plane_cap->per_pixel_alpha) { | |
d74004b6 NK |
4681 | unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | |
4682 | BIT(DRM_MODE_BLEND_PREMULTI); | |
4683 | ||
4684 | drm_plane_create_alpha_property(plane); | |
4685 | drm_plane_create_blend_mode_property(plane, blend_caps); | |
4686 | } | |
4687 | ||
fc8e5230 | 4688 | if (plane->type == DRM_PLANE_TYPE_PRIMARY && |
ea36ad34 | 4689 | plane_cap && plane_cap->pixel_format_support.nv12) { |
fc8e5230 NK |
4690 | /* This only affects YUV formats. */ |
4691 | drm_plane_create_color_properties( | |
4692 | plane, | |
4693 | BIT(DRM_COLOR_YCBCR_BT601) | | |
4694 | BIT(DRM_COLOR_YCBCR_BT709), | |
4695 | BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | | |
4696 | BIT(DRM_COLOR_YCBCR_FULL_RANGE), | |
4697 | DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); | |
4698 | } | |
4699 | ||
f180b4bc | 4700 | drm_plane_helper_add(plane, &dm_plane_helper_funcs); |
e7b07cee | 4701 | |
96719c54 | 4702 | /* Create (reset) the plane state */ |
f180b4bc HW |
4703 | if (plane->funcs->reset) |
4704 | plane->funcs->reset(plane); | |
96719c54 | 4705 | |
37c6a93b | 4706 | return 0; |
e7b07cee HW |
4707 | } |
4708 | ||
7578ecda AD |
4709 | static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, |
4710 | struct drm_plane *plane, | |
4711 | uint32_t crtc_index) | |
e7b07cee HW |
4712 | { |
4713 | struct amdgpu_crtc *acrtc = NULL; | |
f180b4bc | 4714 | struct drm_plane *cursor_plane; |
e7b07cee HW |
4715 | |
4716 | int res = -ENOMEM; | |
4717 | ||
4718 | cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); | |
4719 | if (!cursor_plane) | |
4720 | goto fail; | |
4721 | ||
f180b4bc | 4722 | cursor_plane->type = DRM_PLANE_TYPE_CURSOR; |
cc1fec57 | 4723 | res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); |
e7b07cee HW |
4724 | |
4725 | acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); | |
4726 | if (!acrtc) | |
4727 | goto fail; | |
4728 | ||
4729 | res = drm_crtc_init_with_planes( | |
4730 | dm->ddev, | |
4731 | &acrtc->base, | |
4732 | plane, | |
f180b4bc | 4733 | cursor_plane, |
e7b07cee HW |
4734 | &amdgpu_dm_crtc_funcs, NULL); |
4735 | ||
4736 | if (res) | |
4737 | goto fail; | |
4738 | ||
4739 | drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); | |
4740 | ||
96719c54 HW |
4741 | /* Create (reset) the plane state */ |
4742 | if (acrtc->base.funcs->reset) | |
4743 | acrtc->base.funcs->reset(&acrtc->base); | |
4744 | ||
e7b07cee HW |
4745 | acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; |
4746 | acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; | |
4747 | ||
4748 | acrtc->crtc_id = crtc_index; | |
4749 | acrtc->base.enabled = false; | |
c37e2d29 | 4750 | acrtc->otg_inst = -1; |
e7b07cee HW |
4751 | |
4752 | dm->adev->mode_info.crtcs[crtc_index] = acrtc; | |
236d0e4f LSL |
4753 | drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, |
4754 | true, MAX_COLOR_LUT_ENTRIES); | |
086247a4 | 4755 | drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); |
e7b07cee HW |
4756 | |
4757 | return 0; | |
4758 | ||
4759 | fail: | |
b830ebc9 HW |
4760 | kfree(acrtc); |
4761 | kfree(cursor_plane); | |
e7b07cee HW |
4762 | return res; |
4763 | } | |
4764 | ||
4765 | ||
4766 | static int to_drm_connector_type(enum signal_type st) | |
4767 | { | |
4768 | switch (st) { | |
4769 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
4770 | return DRM_MODE_CONNECTOR_HDMIA; | |
4771 | case SIGNAL_TYPE_EDP: | |
4772 | return DRM_MODE_CONNECTOR_eDP; | |
11c3ee48 AD |
4773 | case SIGNAL_TYPE_LVDS: |
4774 | return DRM_MODE_CONNECTOR_LVDS; | |
e7b07cee HW |
4775 | case SIGNAL_TYPE_RGB: |
4776 | return DRM_MODE_CONNECTOR_VGA; | |
4777 | case SIGNAL_TYPE_DISPLAY_PORT: | |
4778 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
4779 | return DRM_MODE_CONNECTOR_DisplayPort; | |
4780 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
4781 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
4782 | return DRM_MODE_CONNECTOR_DVID; | |
4783 | case SIGNAL_TYPE_VIRTUAL: | |
4784 | return DRM_MODE_CONNECTOR_VIRTUAL; | |
4785 | ||
4786 | default: | |
4787 | return DRM_MODE_CONNECTOR_Unknown; | |
4788 | } | |
4789 | } | |
4790 | ||
2b4c1c05 DV |
4791 | static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) |
4792 | { | |
4793 | return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); | |
4794 | } | |
4795 | ||
e7b07cee HW |
4796 | static void amdgpu_dm_get_native_mode(struct drm_connector *connector) |
4797 | { | |
e7b07cee HW |
4798 | struct drm_encoder *encoder; |
4799 | struct amdgpu_encoder *amdgpu_encoder; | |
4800 | ||
2b4c1c05 | 4801 | encoder = amdgpu_dm_connector_to_encoder(connector); |
e7b07cee HW |
4802 | |
4803 | if (encoder == NULL) | |
4804 | return; | |
4805 | ||
4806 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
4807 | ||
4808 | amdgpu_encoder->native_mode.clock = 0; | |
4809 | ||
4810 | if (!list_empty(&connector->probed_modes)) { | |
4811 | struct drm_display_mode *preferred_mode = NULL; | |
b830ebc9 | 4812 | |
e7b07cee | 4813 | list_for_each_entry(preferred_mode, |
b830ebc9 HW |
4814 | &connector->probed_modes, |
4815 | head) { | |
4816 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) | |
4817 | amdgpu_encoder->native_mode = *preferred_mode; | |
4818 | ||
e7b07cee HW |
4819 | break; |
4820 | } | |
4821 | ||
4822 | } | |
4823 | } | |
4824 | ||
3ee6b26b AD |
4825 | static struct drm_display_mode * |
4826 | amdgpu_dm_create_common_mode(struct drm_encoder *encoder, | |
4827 | char *name, | |
4828 | int hdisplay, int vdisplay) | |
e7b07cee HW |
4829 | { |
4830 | struct drm_device *dev = encoder->dev; | |
4831 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
4832 | struct drm_display_mode *mode = NULL; | |
4833 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
4834 | ||
4835 | mode = drm_mode_duplicate(dev, native_mode); | |
4836 | ||
b830ebc9 | 4837 | if (mode == NULL) |
e7b07cee HW |
4838 | return NULL; |
4839 | ||
4840 | mode->hdisplay = hdisplay; | |
4841 | mode->vdisplay = vdisplay; | |
4842 | mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
090afc1e | 4843 | strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); |
e7b07cee HW |
4844 | |
4845 | return mode; | |
4846 | ||
4847 | } | |
4848 | ||
4849 | static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, | |
3ee6b26b | 4850 | struct drm_connector *connector) |
e7b07cee HW |
4851 | { |
4852 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
4853 | struct drm_display_mode *mode = NULL; | |
4854 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
c84dec2f HW |
4855 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
4856 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
4857 | int i; |
4858 | int n; | |
4859 | struct mode_size { | |
4860 | char name[DRM_DISPLAY_MODE_LEN]; | |
4861 | int w; | |
4862 | int h; | |
b830ebc9 | 4863 | } common_modes[] = { |
e7b07cee HW |
4864 | { "640x480", 640, 480}, |
4865 | { "800x600", 800, 600}, | |
4866 | { "1024x768", 1024, 768}, | |
4867 | { "1280x720", 1280, 720}, | |
4868 | { "1280x800", 1280, 800}, | |
4869 | {"1280x1024", 1280, 1024}, | |
4870 | { "1440x900", 1440, 900}, | |
4871 | {"1680x1050", 1680, 1050}, | |
4872 | {"1600x1200", 1600, 1200}, | |
4873 | {"1920x1080", 1920, 1080}, | |
4874 | {"1920x1200", 1920, 1200} | |
4875 | }; | |
4876 | ||
b830ebc9 | 4877 | n = ARRAY_SIZE(common_modes); |
e7b07cee HW |
4878 | |
4879 | for (i = 0; i < n; i++) { | |
4880 | struct drm_display_mode *curmode = NULL; | |
4881 | bool mode_existed = false; | |
4882 | ||
4883 | if (common_modes[i].w > native_mode->hdisplay || | |
b830ebc9 HW |
4884 | common_modes[i].h > native_mode->vdisplay || |
4885 | (common_modes[i].w == native_mode->hdisplay && | |
4886 | common_modes[i].h == native_mode->vdisplay)) | |
4887 | continue; | |
e7b07cee HW |
4888 | |
4889 | list_for_each_entry(curmode, &connector->probed_modes, head) { | |
4890 | if (common_modes[i].w == curmode->hdisplay && | |
b830ebc9 | 4891 | common_modes[i].h == curmode->vdisplay) { |
e7b07cee HW |
4892 | mode_existed = true; |
4893 | break; | |
4894 | } | |
4895 | } | |
4896 | ||
4897 | if (mode_existed) | |
4898 | continue; | |
4899 | ||
4900 | mode = amdgpu_dm_create_common_mode(encoder, | |
4901 | common_modes[i].name, common_modes[i].w, | |
4902 | common_modes[i].h); | |
4903 | drm_mode_probed_add(connector, mode); | |
c84dec2f | 4904 | amdgpu_dm_connector->num_modes++; |
e7b07cee HW |
4905 | } |
4906 | } | |
4907 | ||
3ee6b26b AD |
4908 | static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, |
4909 | struct edid *edid) | |
e7b07cee | 4910 | { |
c84dec2f HW |
4911 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
4912 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
4913 | |
4914 | if (edid) { | |
4915 | /* empty probed_modes */ | |
4916 | INIT_LIST_HEAD(&connector->probed_modes); | |
c84dec2f | 4917 | amdgpu_dm_connector->num_modes = |
e7b07cee HW |
4918 | drm_add_edid_modes(connector, edid); |
4919 | ||
f1e5e913 YMM |
4920 | /* sorting the probed modes before calling function |
4921 | * amdgpu_dm_get_native_mode() since EDID can have | |
4922 | * more than one preferred mode. The modes that are | |
4923 | * later in the probed mode list could be of higher | |
4924 | * and preferred resolution. For example, 3840x2160 | |
4925 | * resolution in base EDID preferred timing and 4096x2160 | |
4926 | * preferred resolution in DID extension block later. | |
4927 | */ | |
4928 | drm_mode_sort(&connector->probed_modes); | |
e7b07cee | 4929 | amdgpu_dm_get_native_mode(connector); |
a8d8d3dc | 4930 | } else { |
c84dec2f | 4931 | amdgpu_dm_connector->num_modes = 0; |
a8d8d3dc | 4932 | } |
e7b07cee HW |
4933 | } |
4934 | ||
7578ecda | 4935 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) |
e7b07cee | 4936 | { |
c84dec2f HW |
4937 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
4938 | to_amdgpu_dm_connector(connector); | |
e7b07cee | 4939 | struct drm_encoder *encoder; |
c84dec2f | 4940 | struct edid *edid = amdgpu_dm_connector->edid; |
e7b07cee | 4941 | |
2b4c1c05 | 4942 | encoder = amdgpu_dm_connector_to_encoder(connector); |
3e332d3a | 4943 | |
85ee15d6 | 4944 | if (!edid || !drm_edid_is_valid(edid)) { |
1b369d3c ML |
4945 | amdgpu_dm_connector->num_modes = |
4946 | drm_add_modes_noedid(connector, 640, 480); | |
85ee15d6 ML |
4947 | } else { |
4948 | amdgpu_dm_connector_ddc_get_modes(connector, edid); | |
4949 | amdgpu_dm_connector_add_common_modes(encoder, connector); | |
4950 | } | |
3e332d3a | 4951 | amdgpu_dm_fbc_init(connector); |
5099114b | 4952 | |
c84dec2f | 4953 | return amdgpu_dm_connector->num_modes; |
e7b07cee HW |
4954 | } |
4955 | ||
3ee6b26b AD |
4956 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
4957 | struct amdgpu_dm_connector *aconnector, | |
4958 | int connector_type, | |
4959 | struct dc_link *link, | |
4960 | int link_index) | |
e7b07cee HW |
4961 | { |
4962 | struct amdgpu_device *adev = dm->ddev->dev_private; | |
4963 | ||
f04bee34 NK |
4964 | /* |
4965 | * Some of the properties below require access to state, like bpc. | |
4966 | * Allocate some default initial connector state with our reset helper. | |
4967 | */ | |
4968 | if (aconnector->base.funcs->reset) | |
4969 | aconnector->base.funcs->reset(&aconnector->base); | |
4970 | ||
e7b07cee HW |
4971 | aconnector->connector_id = link_index; |
4972 | aconnector->dc_link = link; | |
4973 | aconnector->base.interlace_allowed = false; | |
4974 | aconnector->base.doublescan_allowed = false; | |
4975 | aconnector->base.stereo_allowed = false; | |
4976 | aconnector->base.dpms = DRM_MODE_DPMS_OFF; | |
4977 | aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ | |
6ce8f316 | 4978 | aconnector->audio_inst = -1; |
e7b07cee HW |
4979 | mutex_init(&aconnector->hpd_lock); |
4980 | ||
1f6010a9 DF |
4981 | /* |
4982 | * configure support HPD hot plug connector_>polled default value is 0 | |
b830ebc9 HW |
4983 | * which means HPD hot plug not supported |
4984 | */ | |
e7b07cee HW |
4985 | switch (connector_type) { |
4986 | case DRM_MODE_CONNECTOR_HDMIA: | |
4987 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 4988 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 4989 | link->link_enc->features.hdmi_ycbcr420_supported ? true : false; |
e7b07cee HW |
4990 | break; |
4991 | case DRM_MODE_CONNECTOR_DisplayPort: | |
4992 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 4993 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 4994 | link->link_enc->features.dp_ycbcr420_supported ? true : false; |
e7b07cee HW |
4995 | break; |
4996 | case DRM_MODE_CONNECTOR_DVID: | |
4997 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
4998 | break; | |
4999 | default: | |
5000 | break; | |
5001 | } | |
5002 | ||
5003 | drm_object_attach_property(&aconnector->base.base, | |
5004 | dm->ddev->mode_config.scaling_mode_property, | |
5005 | DRM_MODE_SCALE_NONE); | |
5006 | ||
5007 | drm_object_attach_property(&aconnector->base.base, | |
5008 | adev->mode_info.underscan_property, | |
5009 | UNDERSCAN_OFF); | |
5010 | drm_object_attach_property(&aconnector->base.base, | |
5011 | adev->mode_info.underscan_hborder_property, | |
5012 | 0); | |
5013 | drm_object_attach_property(&aconnector->base.base, | |
5014 | adev->mode_info.underscan_vborder_property, | |
5015 | 0); | |
1825fd34 NK |
5016 | |
5017 | drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); | |
5018 | ||
5019 | /* This defaults to the max in the range, but we want 8bpc. */ | |
5020 | aconnector->base.state->max_bpc = 8; | |
5021 | aconnector->base.state->max_requested_bpc = 8; | |
e7b07cee | 5022 | |
c1ee92f9 DF |
5023 | if (connector_type == DRM_MODE_CONNECTOR_eDP && |
5024 | dc_is_dmcu_initialized(adev->dm.dc)) { | |
5025 | drm_object_attach_property(&aconnector->base.base, | |
5026 | adev->mode_info.abm_level_property, 0); | |
5027 | } | |
bb47de73 NK |
5028 | |
5029 | if (connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
7fad8da1 NK |
5030 | connector_type == DRM_MODE_CONNECTOR_DisplayPort || |
5031 | connector_type == DRM_MODE_CONNECTOR_eDP) { | |
88694af9 NK |
5032 | drm_object_attach_property( |
5033 | &aconnector->base.base, | |
5034 | dm->ddev->mode_config.hdr_output_metadata_property, 0); | |
5035 | ||
bb47de73 NK |
5036 | drm_connector_attach_vrr_capable_property( |
5037 | &aconnector->base); | |
5038 | } | |
e7b07cee HW |
5039 | } |
5040 | ||
7578ecda AD |
5041 | static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, |
5042 | struct i2c_msg *msgs, int num) | |
e7b07cee HW |
5043 | { |
5044 | struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); | |
5045 | struct ddc_service *ddc_service = i2c->ddc_service; | |
5046 | struct i2c_command cmd; | |
5047 | int i; | |
5048 | int result = -EIO; | |
5049 | ||
b830ebc9 | 5050 | cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); |
e7b07cee HW |
5051 | |
5052 | if (!cmd.payloads) | |
5053 | return result; | |
5054 | ||
5055 | cmd.number_of_payloads = num; | |
5056 | cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; | |
5057 | cmd.speed = 100; | |
5058 | ||
5059 | for (i = 0; i < num; i++) { | |
5060 | cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); | |
5061 | cmd.payloads[i].address = msgs[i].addr; | |
5062 | cmd.payloads[i].length = msgs[i].len; | |
5063 | cmd.payloads[i].data = msgs[i].buf; | |
5064 | } | |
5065 | ||
c85e6e54 DF |
5066 | if (dc_submit_i2c( |
5067 | ddc_service->ctx->dc, | |
5068 | ddc_service->ddc_pin->hw_info.ddc_channel, | |
e7b07cee HW |
5069 | &cmd)) |
5070 | result = num; | |
5071 | ||
5072 | kfree(cmd.payloads); | |
5073 | return result; | |
5074 | } | |
5075 | ||
7578ecda | 5076 | static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) |
e7b07cee HW |
5077 | { |
5078 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
5079 | } | |
5080 | ||
5081 | static const struct i2c_algorithm amdgpu_dm_i2c_algo = { | |
5082 | .master_xfer = amdgpu_dm_i2c_xfer, | |
5083 | .functionality = amdgpu_dm_i2c_func, | |
5084 | }; | |
5085 | ||
3ee6b26b AD |
5086 | static struct amdgpu_i2c_adapter * |
5087 | create_i2c(struct ddc_service *ddc_service, | |
5088 | int link_index, | |
5089 | int *res) | |
e7b07cee HW |
5090 | { |
5091 | struct amdgpu_device *adev = ddc_service->ctx->driver_context; | |
5092 | struct amdgpu_i2c_adapter *i2c; | |
5093 | ||
b830ebc9 | 5094 | i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); |
2a55f096 ES |
5095 | if (!i2c) |
5096 | return NULL; | |
e7b07cee HW |
5097 | i2c->base.owner = THIS_MODULE; |
5098 | i2c->base.class = I2C_CLASS_DDC; | |
5099 | i2c->base.dev.parent = &adev->pdev->dev; | |
5100 | i2c->base.algo = &amdgpu_dm_i2c_algo; | |
b830ebc9 | 5101 | snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); |
e7b07cee HW |
5102 | i2c_set_adapdata(&i2c->base, i2c); |
5103 | i2c->ddc_service = ddc_service; | |
c85e6e54 | 5104 | i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; |
e7b07cee HW |
5105 | |
5106 | return i2c; | |
5107 | } | |
5108 | ||
89fc8d4e | 5109 | |
1f6010a9 DF |
5110 | /* |
5111 | * Note: this function assumes that dc_link_detect() was called for the | |
b830ebc9 HW |
5112 | * dc_link which will be represented by this aconnector. |
5113 | */ | |
7578ecda AD |
5114 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
5115 | struct amdgpu_dm_connector *aconnector, | |
5116 | uint32_t link_index, | |
5117 | struct amdgpu_encoder *aencoder) | |
e7b07cee HW |
5118 | { |
5119 | int res = 0; | |
5120 | int connector_type; | |
5121 | struct dc *dc = dm->dc; | |
5122 | struct dc_link *link = dc_get_link_at_index(dc, link_index); | |
5123 | struct amdgpu_i2c_adapter *i2c; | |
9a227d26 TSD |
5124 | |
5125 | link->priv = aconnector; | |
e7b07cee | 5126 | |
f1ad2f5e | 5127 | DRM_DEBUG_DRIVER("%s()\n", __func__); |
e7b07cee HW |
5128 | |
5129 | i2c = create_i2c(link->ddc, link->link_index, &res); | |
2a55f096 ES |
5130 | if (!i2c) { |
5131 | DRM_ERROR("Failed to create i2c adapter data\n"); | |
5132 | return -ENOMEM; | |
5133 | } | |
5134 | ||
e7b07cee HW |
5135 | aconnector->i2c = i2c; |
5136 | res = i2c_add_adapter(&i2c->base); | |
5137 | ||
5138 | if (res) { | |
5139 | DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); | |
5140 | goto out_free; | |
5141 | } | |
5142 | ||
5143 | connector_type = to_drm_connector_type(link->connector_signal); | |
5144 | ||
5145 | res = drm_connector_init( | |
5146 | dm->ddev, | |
5147 | &aconnector->base, | |
5148 | &amdgpu_dm_connector_funcs, | |
5149 | connector_type); | |
5150 | ||
5151 | if (res) { | |
5152 | DRM_ERROR("connector_init failed\n"); | |
5153 | aconnector->connector_id = -1; | |
5154 | goto out_free; | |
5155 | } | |
5156 | ||
5157 | drm_connector_helper_add( | |
5158 | &aconnector->base, | |
5159 | &amdgpu_dm_connector_helper_funcs); | |
5160 | ||
5161 | amdgpu_dm_connector_init_helper( | |
5162 | dm, | |
5163 | aconnector, | |
5164 | connector_type, | |
5165 | link, | |
5166 | link_index); | |
5167 | ||
cde4c44d | 5168 | drm_connector_attach_encoder( |
e7b07cee HW |
5169 | &aconnector->base, &aencoder->base); |
5170 | ||
5171 | drm_connector_register(&aconnector->base); | |
dc38fd9d | 5172 | #if defined(CONFIG_DEBUG_FS) |
4be8be78 | 5173 | connector_debugfs_init(aconnector); |
f258fee6 DF |
5174 | aconnector->debugfs_dpcd_address = 0; |
5175 | aconnector->debugfs_dpcd_size = 0; | |
dc38fd9d | 5176 | #endif |
e7b07cee HW |
5177 | |
5178 | if (connector_type == DRM_MODE_CONNECTOR_DisplayPort | |
5179 | || connector_type == DRM_MODE_CONNECTOR_eDP) | |
5180 | amdgpu_dm_initialize_dp_connector(dm, aconnector); | |
5181 | ||
e7b07cee HW |
5182 | out_free: |
5183 | if (res) { | |
5184 | kfree(i2c); | |
5185 | aconnector->i2c = NULL; | |
5186 | } | |
5187 | return res; | |
5188 | } | |
5189 | ||
5190 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) | |
5191 | { | |
5192 | switch (adev->mode_info.num_crtc) { | |
5193 | case 1: | |
5194 | return 0x1; | |
5195 | case 2: | |
5196 | return 0x3; | |
5197 | case 3: | |
5198 | return 0x7; | |
5199 | case 4: | |
5200 | return 0xf; | |
5201 | case 5: | |
5202 | return 0x1f; | |
5203 | case 6: | |
5204 | default: | |
5205 | return 0x3f; | |
5206 | } | |
5207 | } | |
5208 | ||
7578ecda AD |
5209 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
5210 | struct amdgpu_encoder *aencoder, | |
5211 | uint32_t link_index) | |
e7b07cee HW |
5212 | { |
5213 | struct amdgpu_device *adev = dev->dev_private; | |
5214 | ||
5215 | int res = drm_encoder_init(dev, | |
5216 | &aencoder->base, | |
5217 | &amdgpu_dm_encoder_funcs, | |
5218 | DRM_MODE_ENCODER_TMDS, | |
5219 | NULL); | |
5220 | ||
5221 | aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); | |
5222 | ||
5223 | if (!res) | |
5224 | aencoder->encoder_id = link_index; | |
5225 | else | |
5226 | aencoder->encoder_id = -1; | |
5227 | ||
5228 | drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); | |
5229 | ||
5230 | return res; | |
5231 | } | |
5232 | ||
3ee6b26b AD |
5233 | static void manage_dm_interrupts(struct amdgpu_device *adev, |
5234 | struct amdgpu_crtc *acrtc, | |
5235 | bool enable) | |
e7b07cee HW |
5236 | { |
5237 | /* | |
5238 | * this is not correct translation but will work as soon as VBLANK | |
5239 | * constant is the same as PFLIP | |
5240 | */ | |
5241 | int irq_type = | |
734dd01d | 5242 | amdgpu_display_crtc_idx_to_irq_type( |
e7b07cee HW |
5243 | adev, |
5244 | acrtc->crtc_id); | |
5245 | ||
5246 | if (enable) { | |
5247 | drm_crtc_vblank_on(&acrtc->base); | |
5248 | amdgpu_irq_get( | |
5249 | adev, | |
5250 | &adev->pageflip_irq, | |
5251 | irq_type); | |
5252 | } else { | |
5253 | ||
5254 | amdgpu_irq_put( | |
5255 | adev, | |
5256 | &adev->pageflip_irq, | |
5257 | irq_type); | |
5258 | drm_crtc_vblank_off(&acrtc->base); | |
5259 | } | |
5260 | } | |
5261 | ||
3ee6b26b AD |
5262 | static bool |
5263 | is_scaling_state_different(const struct dm_connector_state *dm_state, | |
5264 | const struct dm_connector_state *old_dm_state) | |
e7b07cee HW |
5265 | { |
5266 | if (dm_state->scaling != old_dm_state->scaling) | |
5267 | return true; | |
5268 | if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { | |
5269 | if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) | |
5270 | return true; | |
5271 | } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { | |
5272 | if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) | |
5273 | return true; | |
b830ebc9 HW |
5274 | } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || |
5275 | dm_state->underscan_vborder != old_dm_state->underscan_vborder) | |
5276 | return true; | |
e7b07cee HW |
5277 | return false; |
5278 | } | |
5279 | ||
3ee6b26b AD |
5280 | static void remove_stream(struct amdgpu_device *adev, |
5281 | struct amdgpu_crtc *acrtc, | |
5282 | struct dc_stream_state *stream) | |
e7b07cee HW |
5283 | { |
5284 | /* this is the update mode case */ | |
e7b07cee HW |
5285 | |
5286 | acrtc->otg_inst = -1; | |
5287 | acrtc->enabled = false; | |
5288 | } | |
5289 | ||
7578ecda AD |
5290 | static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, |
5291 | struct dc_cursor_position *position) | |
2a8f6ccb | 5292 | { |
f4c2cc43 | 5293 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
2a8f6ccb HW |
5294 | int x, y; |
5295 | int xorigin = 0, yorigin = 0; | |
5296 | ||
e371e19c NK |
5297 | position->enable = false; |
5298 | position->x = 0; | |
5299 | position->y = 0; | |
5300 | ||
5301 | if (!crtc || !plane->state->fb) | |
2a8f6ccb | 5302 | return 0; |
2a8f6ccb HW |
5303 | |
5304 | if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || | |
5305 | (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { | |
5306 | DRM_ERROR("%s: bad cursor width or height %d x %d\n", | |
5307 | __func__, | |
5308 | plane->state->crtc_w, | |
5309 | plane->state->crtc_h); | |
5310 | return -EINVAL; | |
5311 | } | |
5312 | ||
5313 | x = plane->state->crtc_x; | |
5314 | y = plane->state->crtc_y; | |
c14a005c | 5315 | |
e371e19c NK |
5316 | if (x <= -amdgpu_crtc->max_cursor_width || |
5317 | y <= -amdgpu_crtc->max_cursor_height) | |
5318 | return 0; | |
5319 | ||
c14a005c NK |
5320 | if (crtc->primary->state) { |
5321 | /* avivo cursor are offset into the total surface */ | |
5322 | x += crtc->primary->state->src_x >> 16; | |
5323 | y += crtc->primary->state->src_y >> 16; | |
5324 | } | |
5325 | ||
2a8f6ccb HW |
5326 | if (x < 0) { |
5327 | xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); | |
5328 | x = 0; | |
5329 | } | |
5330 | if (y < 0) { | |
5331 | yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); | |
5332 | y = 0; | |
5333 | } | |
5334 | position->enable = true; | |
5335 | position->x = x; | |
5336 | position->y = y; | |
5337 | position->x_hotspot = xorigin; | |
5338 | position->y_hotspot = yorigin; | |
5339 | ||
5340 | return 0; | |
5341 | } | |
5342 | ||
3ee6b26b AD |
5343 | static void handle_cursor_update(struct drm_plane *plane, |
5344 | struct drm_plane_state *old_plane_state) | |
e7b07cee | 5345 | { |
674e78ac | 5346 | struct amdgpu_device *adev = plane->dev->dev_private; |
2a8f6ccb HW |
5347 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); |
5348 | struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; | |
5349 | struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; | |
5350 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
5351 | uint64_t address = afb ? afb->address : 0; | |
5352 | struct dc_cursor_position position; | |
5353 | struct dc_cursor_attributes attributes; | |
5354 | int ret; | |
5355 | ||
e7b07cee HW |
5356 | if (!plane->state->fb && !old_plane_state->fb) |
5357 | return; | |
5358 | ||
f1ad2f5e | 5359 | DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", |
c12a7ba5 HW |
5360 | __func__, |
5361 | amdgpu_crtc->crtc_id, | |
5362 | plane->state->crtc_w, | |
5363 | plane->state->crtc_h); | |
2a8f6ccb HW |
5364 | |
5365 | ret = get_cursor_position(plane, crtc, &position); | |
5366 | if (ret) | |
5367 | return; | |
5368 | ||
5369 | if (!position.enable) { | |
5370 | /* turn off cursor */ | |
674e78ac NK |
5371 | if (crtc_state && crtc_state->stream) { |
5372 | mutex_lock(&adev->dm.dc_lock); | |
2a8f6ccb HW |
5373 | dc_stream_set_cursor_position(crtc_state->stream, |
5374 | &position); | |
674e78ac NK |
5375 | mutex_unlock(&adev->dm.dc_lock); |
5376 | } | |
2a8f6ccb | 5377 | return; |
e7b07cee | 5378 | } |
e7b07cee | 5379 | |
2a8f6ccb HW |
5380 | amdgpu_crtc->cursor_width = plane->state->crtc_w; |
5381 | amdgpu_crtc->cursor_height = plane->state->crtc_h; | |
5382 | ||
c1cefe11 | 5383 | memset(&attributes, 0, sizeof(attributes)); |
2a8f6ccb HW |
5384 | attributes.address.high_part = upper_32_bits(address); |
5385 | attributes.address.low_part = lower_32_bits(address); | |
5386 | attributes.width = plane->state->crtc_w; | |
5387 | attributes.height = plane->state->crtc_h; | |
5388 | attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; | |
5389 | attributes.rotation_angle = 0; | |
5390 | attributes.attribute_flags.value = 0; | |
5391 | ||
5392 | attributes.pitch = attributes.width; | |
5393 | ||
886daac9 | 5394 | if (crtc_state->stream) { |
674e78ac | 5395 | mutex_lock(&adev->dm.dc_lock); |
886daac9 JZ |
5396 | if (!dc_stream_set_cursor_attributes(crtc_state->stream, |
5397 | &attributes)) | |
5398 | DRM_ERROR("DC failed to set cursor attributes\n"); | |
2a8f6ccb | 5399 | |
2a8f6ccb HW |
5400 | if (!dc_stream_set_cursor_position(crtc_state->stream, |
5401 | &position)) | |
5402 | DRM_ERROR("DC failed to set cursor position\n"); | |
674e78ac | 5403 | mutex_unlock(&adev->dm.dc_lock); |
886daac9 | 5404 | } |
2a8f6ccb | 5405 | } |
e7b07cee HW |
5406 | |
5407 | static void prepare_flip_isr(struct amdgpu_crtc *acrtc) | |
5408 | { | |
5409 | ||
5410 | assert_spin_locked(&acrtc->base.dev->event_lock); | |
5411 | WARN_ON(acrtc->event); | |
5412 | ||
5413 | acrtc->event = acrtc->base.state->event; | |
5414 | ||
5415 | /* Set the flip status */ | |
5416 | acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; | |
5417 | ||
5418 | /* Mark this event as consumed */ | |
5419 | acrtc->base.state->event = NULL; | |
5420 | ||
5421 | DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", | |
5422 | acrtc->crtc_id); | |
5423 | } | |
5424 | ||
bb47de73 NK |
5425 | static void update_freesync_state_on_stream( |
5426 | struct amdgpu_display_manager *dm, | |
5427 | struct dm_crtc_state *new_crtc_state, | |
180db303 NK |
5428 | struct dc_stream_state *new_stream, |
5429 | struct dc_plane_state *surface, | |
5430 | u32 flip_timestamp_in_us) | |
bb47de73 | 5431 | { |
09aef2c4 | 5432 | struct mod_vrr_params vrr_params; |
bb47de73 | 5433 | struct dc_info_packet vrr_infopacket = {0}; |
09aef2c4 MK |
5434 | struct amdgpu_device *adev = dm->adev; |
5435 | unsigned long flags; | |
bb47de73 NK |
5436 | |
5437 | if (!new_stream) | |
5438 | return; | |
5439 | ||
5440 | /* | |
5441 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
5442 | * For now it's sufficient to just guard against these conditions. | |
5443 | */ | |
5444 | ||
5445 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
5446 | return; | |
5447 | ||
09aef2c4 MK |
5448 | spin_lock_irqsave(&adev->ddev->event_lock, flags); |
5449 | vrr_params = new_crtc_state->vrr_params; | |
5450 | ||
180db303 NK |
5451 | if (surface) { |
5452 | mod_freesync_handle_preflip( | |
5453 | dm->freesync_module, | |
5454 | surface, | |
5455 | new_stream, | |
5456 | flip_timestamp_in_us, | |
5457 | &vrr_params); | |
09aef2c4 MK |
5458 | |
5459 | if (adev->family < AMDGPU_FAMILY_AI && | |
5460 | amdgpu_dm_vrr_active(new_crtc_state)) { | |
5461 | mod_freesync_handle_v_update(dm->freesync_module, | |
5462 | new_stream, &vrr_params); | |
e63e2491 EB |
5463 | |
5464 | /* Need to call this before the frame ends. */ | |
5465 | dc_stream_adjust_vmin_vmax(dm->dc, | |
5466 | new_crtc_state->stream, | |
5467 | &vrr_params.adjust); | |
09aef2c4 | 5468 | } |
180db303 | 5469 | } |
bb47de73 NK |
5470 | |
5471 | mod_freesync_build_vrr_infopacket( | |
5472 | dm->freesync_module, | |
5473 | new_stream, | |
180db303 | 5474 | &vrr_params, |
ecd0136b HT |
5475 | PACKET_TYPE_VRR, |
5476 | TRANSFER_FUNC_UNKNOWN, | |
bb47de73 NK |
5477 | &vrr_infopacket); |
5478 | ||
8a48b44c | 5479 | new_crtc_state->freesync_timing_changed |= |
180db303 NK |
5480 | (memcmp(&new_crtc_state->vrr_params.adjust, |
5481 | &vrr_params.adjust, | |
5482 | sizeof(vrr_params.adjust)) != 0); | |
bb47de73 | 5483 | |
8a48b44c | 5484 | new_crtc_state->freesync_vrr_info_changed |= |
bb47de73 NK |
5485 | (memcmp(&new_crtc_state->vrr_infopacket, |
5486 | &vrr_infopacket, | |
5487 | sizeof(vrr_infopacket)) != 0); | |
5488 | ||
180db303 | 5489 | new_crtc_state->vrr_params = vrr_params; |
bb47de73 NK |
5490 | new_crtc_state->vrr_infopacket = vrr_infopacket; |
5491 | ||
180db303 | 5492 | new_stream->adjust = new_crtc_state->vrr_params.adjust; |
bb47de73 NK |
5493 | new_stream->vrr_infopacket = vrr_infopacket; |
5494 | ||
5495 | if (new_crtc_state->freesync_vrr_info_changed) | |
5496 | DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", | |
5497 | new_crtc_state->base.crtc->base.id, | |
5498 | (int)new_crtc_state->base.vrr_enabled, | |
180db303 | 5499 | (int)vrr_params.state); |
09aef2c4 MK |
5500 | |
5501 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
bb47de73 NK |
5502 | } |
5503 | ||
e854194c MK |
5504 | static void pre_update_freesync_state_on_stream( |
5505 | struct amdgpu_display_manager *dm, | |
5506 | struct dm_crtc_state *new_crtc_state) | |
5507 | { | |
5508 | struct dc_stream_state *new_stream = new_crtc_state->stream; | |
09aef2c4 | 5509 | struct mod_vrr_params vrr_params; |
e854194c | 5510 | struct mod_freesync_config config = new_crtc_state->freesync_config; |
09aef2c4 MK |
5511 | struct amdgpu_device *adev = dm->adev; |
5512 | unsigned long flags; | |
e854194c MK |
5513 | |
5514 | if (!new_stream) | |
5515 | return; | |
5516 | ||
5517 | /* | |
5518 | * TODO: Determine why min/max totals and vrefresh can be 0 here. | |
5519 | * For now it's sufficient to just guard against these conditions. | |
5520 | */ | |
5521 | if (!new_stream->timing.h_total || !new_stream->timing.v_total) | |
5522 | return; | |
5523 | ||
09aef2c4 MK |
5524 | spin_lock_irqsave(&adev->ddev->event_lock, flags); |
5525 | vrr_params = new_crtc_state->vrr_params; | |
5526 | ||
e854194c MK |
5527 | if (new_crtc_state->vrr_supported && |
5528 | config.min_refresh_in_uhz && | |
5529 | config.max_refresh_in_uhz) { | |
5530 | config.state = new_crtc_state->base.vrr_enabled ? | |
5531 | VRR_STATE_ACTIVE_VARIABLE : | |
5532 | VRR_STATE_INACTIVE; | |
5533 | } else { | |
5534 | config.state = VRR_STATE_UNSUPPORTED; | |
5535 | } | |
5536 | ||
5537 | mod_freesync_build_vrr_params(dm->freesync_module, | |
5538 | new_stream, | |
5539 | &config, &vrr_params); | |
5540 | ||
5541 | new_crtc_state->freesync_timing_changed |= | |
5542 | (memcmp(&new_crtc_state->vrr_params.adjust, | |
5543 | &vrr_params.adjust, | |
5544 | sizeof(vrr_params.adjust)) != 0); | |
5545 | ||
5546 | new_crtc_state->vrr_params = vrr_params; | |
09aef2c4 | 5547 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); |
e854194c MK |
5548 | } |
5549 | ||
66b0c973 MK |
5550 | static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, |
5551 | struct dm_crtc_state *new_state) | |
5552 | { | |
5553 | bool old_vrr_active = amdgpu_dm_vrr_active(old_state); | |
5554 | bool new_vrr_active = amdgpu_dm_vrr_active(new_state); | |
5555 | ||
5556 | if (!old_vrr_active && new_vrr_active) { | |
5557 | /* Transition VRR inactive -> active: | |
5558 | * While VRR is active, we must not disable vblank irq, as a | |
5559 | * reenable after disable would compute bogus vblank/pflip | |
5560 | * timestamps if it likely happened inside display front-porch. | |
d2574c33 MK |
5561 | * |
5562 | * We also need vupdate irq for the actual core vblank handling | |
5563 | * at end of vblank. | |
66b0c973 | 5564 | */ |
d2574c33 | 5565 | dm_set_vupdate_irq(new_state->base.crtc, true); |
66b0c973 MK |
5566 | drm_crtc_vblank_get(new_state->base.crtc); |
5567 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", | |
5568 | __func__, new_state->base.crtc->base.id); | |
5569 | } else if (old_vrr_active && !new_vrr_active) { | |
5570 | /* Transition VRR active -> inactive: | |
5571 | * Allow vblank irq disable again for fixed refresh rate. | |
5572 | */ | |
d2574c33 | 5573 | dm_set_vupdate_irq(new_state->base.crtc, false); |
66b0c973 MK |
5574 | drm_crtc_vblank_put(new_state->base.crtc); |
5575 | DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", | |
5576 | __func__, new_state->base.crtc->base.id); | |
5577 | } | |
5578 | } | |
5579 | ||
8ad27806 NK |
5580 | static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) |
5581 | { | |
5582 | struct drm_plane *plane; | |
5583 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
5584 | int i; | |
5585 | ||
5586 | /* | |
5587 | * TODO: Make this per-stream so we don't issue redundant updates for | |
5588 | * commits with multiple streams. | |
5589 | */ | |
5590 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, | |
5591 | new_plane_state, i) | |
5592 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
5593 | handle_cursor_update(plane, old_plane_state); | |
5594 | } | |
5595 | ||
3be5262e | 5596 | static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, |
eb3dc897 | 5597 | struct dc_state *dc_state, |
3ee6b26b AD |
5598 | struct drm_device *dev, |
5599 | struct amdgpu_display_manager *dm, | |
5600 | struct drm_crtc *pcrtc, | |
420cd472 | 5601 | bool wait_for_vblank) |
e7b07cee | 5602 | { |
570c91d5 | 5603 | uint32_t i; |
8a48b44c | 5604 | uint64_t timestamp_ns; |
e7b07cee | 5605 | struct drm_plane *plane; |
0bc9706d | 5606 | struct drm_plane_state *old_plane_state, *new_plane_state; |
e7b07cee | 5607 | struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); |
0bc9706d LSL |
5608 | struct drm_crtc_state *new_pcrtc_state = |
5609 | drm_atomic_get_new_crtc_state(state, pcrtc); | |
5610 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); | |
44d09c6a HW |
5611 | struct dm_crtc_state *dm_old_crtc_state = |
5612 | to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); | |
74aa7bd4 | 5613 | int planes_count = 0, vpos, hpos; |
570c91d5 | 5614 | long r; |
e7b07cee | 5615 | unsigned long flags; |
8a48b44c | 5616 | struct amdgpu_bo *abo; |
09e5665a | 5617 | uint64_t tiling_flags; |
fdd1fe57 MK |
5618 | uint32_t target_vblank, last_flip_vblank; |
5619 | bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); | |
74aa7bd4 | 5620 | bool pflip_present = false; |
bc7f670e DF |
5621 | struct { |
5622 | struct dc_surface_update surface_updates[MAX_SURFACES]; | |
5623 | struct dc_plane_info plane_infos[MAX_SURFACES]; | |
5624 | struct dc_scaling_info scaling_infos[MAX_SURFACES]; | |
74aa7bd4 | 5625 | struct dc_flip_addrs flip_addrs[MAX_SURFACES]; |
bc7f670e | 5626 | struct dc_stream_update stream_update; |
74aa7bd4 | 5627 | } *bundle; |
bc7f670e | 5628 | |
74aa7bd4 | 5629 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); |
8a48b44c | 5630 | |
74aa7bd4 DF |
5631 | if (!bundle) { |
5632 | dm_error("Failed to allocate update bundle\n"); | |
4b510503 NK |
5633 | goto cleanup; |
5634 | } | |
e7b07cee | 5635 | |
8ad27806 NK |
5636 | /* |
5637 | * Disable the cursor first if we're disabling all the planes. | |
5638 | * It'll remain on the screen after the planes are re-enabled | |
5639 | * if we don't. | |
5640 | */ | |
5641 | if (acrtc_state->active_planes == 0) | |
5642 | amdgpu_dm_commit_cursors(state); | |
5643 | ||
e7b07cee | 5644 | /* update planes when needed */ |
0bc9706d LSL |
5645 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
5646 | struct drm_crtc *crtc = new_plane_state->crtc; | |
f5ba60fe | 5647 | struct drm_crtc_state *new_crtc_state; |
0bc9706d | 5648 | struct drm_framebuffer *fb = new_plane_state->fb; |
34bafd27 | 5649 | bool plane_needs_flip; |
c7af5f77 | 5650 | struct dc_plane_state *dc_plane; |
54d76575 | 5651 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
e7b07cee | 5652 | |
80c218d5 NK |
5653 | /* Cursor plane is handled after stream updates */ |
5654 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
e7b07cee | 5655 | continue; |
e7b07cee | 5656 | |
f5ba60fe DD |
5657 | if (!fb || !crtc || pcrtc != crtc) |
5658 | continue; | |
5659 | ||
5660 | new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); | |
5661 | if (!new_crtc_state->active) | |
e7b07cee HW |
5662 | continue; |
5663 | ||
bc7f670e | 5664 | dc_plane = dm_new_plane_state->dc_state; |
e7b07cee | 5665 | |
74aa7bd4 | 5666 | bundle->surface_updates[planes_count].surface = dc_plane; |
bc7f670e | 5667 | if (new_pcrtc_state->color_mgmt_changed) { |
74aa7bd4 DF |
5668 | bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; |
5669 | bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; | |
bc7f670e | 5670 | } |
8a48b44c | 5671 | |
695af5f9 NK |
5672 | fill_dc_scaling_info(new_plane_state, |
5673 | &bundle->scaling_infos[planes_count]); | |
8a48b44c | 5674 | |
695af5f9 NK |
5675 | bundle->surface_updates[planes_count].scaling_info = |
5676 | &bundle->scaling_infos[planes_count]; | |
8a48b44c | 5677 | |
f5031000 | 5678 | plane_needs_flip = old_plane_state->fb && new_plane_state->fb; |
8a48b44c | 5679 | |
f5031000 | 5680 | pflip_present = pflip_present || plane_needs_flip; |
8a48b44c | 5681 | |
f5031000 DF |
5682 | if (!plane_needs_flip) { |
5683 | planes_count += 1; | |
5684 | continue; | |
5685 | } | |
8a48b44c | 5686 | |
2fac0f53 CK |
5687 | abo = gem_to_amdgpu_bo(fb->obj[0]); |
5688 | ||
f8308898 AG |
5689 | /* |
5690 | * Wait for all fences on this FB. Do limited wait to avoid | |
5691 | * deadlock during GPU reset when this fence will not signal | |
5692 | * but we hold reservation lock for the BO. | |
5693 | */ | |
2fac0f53 CK |
5694 | r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true, |
5695 | false, | |
f8308898 AG |
5696 | msecs_to_jiffies(5000)); |
5697 | if (unlikely(r <= 0)) | |
5698 | DRM_ERROR("Waiting for fences timed out or interrupted!"); | |
2fac0f53 | 5699 | |
f5031000 DF |
5700 | /* |
5701 | * TODO This might fail and hence better not used, wait | |
5702 | * explicitly on fences instead | |
5703 | * and in general should be called for | |
5704 | * blocking commit to as per framework helpers | |
5705 | */ | |
f5031000 | 5706 | r = amdgpu_bo_reserve(abo, true); |
f8308898 | 5707 | if (unlikely(r != 0)) |
f5031000 | 5708 | DRM_ERROR("failed to reserve buffer before flip\n"); |
8a48b44c | 5709 | |
f5031000 | 5710 | amdgpu_bo_get_tiling_flags(abo, &tiling_flags); |
8a48b44c | 5711 | |
f5031000 | 5712 | amdgpu_bo_unreserve(abo); |
8a48b44c | 5713 | |
695af5f9 NK |
5714 | fill_dc_plane_info_and_addr( |
5715 | dm->adev, new_plane_state, tiling_flags, | |
5716 | &bundle->plane_infos[planes_count], | |
5717 | &bundle->flip_addrs[planes_count].address); | |
5718 | ||
5719 | bundle->surface_updates[planes_count].plane_info = | |
5720 | &bundle->plane_infos[planes_count]; | |
8a48b44c | 5721 | |
f5031000 DF |
5722 | bundle->flip_addrs[planes_count].flip_immediate = |
5723 | (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; | |
8a48b44c | 5724 | |
f5031000 DF |
5725 | timestamp_ns = ktime_get_ns(); |
5726 | bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); | |
5727 | bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; | |
5728 | bundle->surface_updates[planes_count].surface = dc_plane; | |
8a48b44c | 5729 | |
f5031000 DF |
5730 | if (!bundle->surface_updates[planes_count].surface) { |
5731 | DRM_ERROR("No surface for CRTC: id=%d\n", | |
5732 | acrtc_attach->crtc_id); | |
5733 | continue; | |
bc7f670e DF |
5734 | } |
5735 | ||
f5031000 DF |
5736 | if (plane == pcrtc->primary) |
5737 | update_freesync_state_on_stream( | |
5738 | dm, | |
5739 | acrtc_state, | |
5740 | acrtc_state->stream, | |
5741 | dc_plane, | |
5742 | bundle->flip_addrs[planes_count].flip_timestamp_in_us); | |
bc7f670e | 5743 | |
f5031000 DF |
5744 | DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n", |
5745 | __func__, | |
5746 | bundle->flip_addrs[planes_count].address.grph.addr.high_part, | |
5747 | bundle->flip_addrs[planes_count].address.grph.addr.low_part); | |
bc7f670e DF |
5748 | |
5749 | planes_count += 1; | |
5750 | ||
8a48b44c DF |
5751 | } |
5752 | ||
74aa7bd4 | 5753 | if (pflip_present) { |
634092b1 MK |
5754 | if (!vrr_active) { |
5755 | /* Use old throttling in non-vrr fixed refresh rate mode | |
5756 | * to keep flip scheduling based on target vblank counts | |
5757 | * working in a backwards compatible way, e.g., for | |
5758 | * clients using the GLX_OML_sync_control extension or | |
5759 | * DRI3/Present extension with defined target_msc. | |
5760 | */ | |
fdd1fe57 | 5761 | last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); |
634092b1 MK |
5762 | } |
5763 | else { | |
5764 | /* For variable refresh rate mode only: | |
5765 | * Get vblank of last completed flip to avoid > 1 vrr | |
5766 | * flips per video frame by use of throttling, but allow | |
5767 | * flip programming anywhere in the possibly large | |
5768 | * variable vrr vblank interval for fine-grained flip | |
5769 | * timing control and more opportunity to avoid stutter | |
5770 | * on late submission of flips. | |
5771 | */ | |
5772 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
5773 | last_flip_vblank = acrtc_attach->last_flip_vblank; | |
5774 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
5775 | } | |
5776 | ||
fdd1fe57 | 5777 | target_vblank = last_flip_vblank + wait_for_vblank; |
8a48b44c DF |
5778 | |
5779 | /* | |
5780 | * Wait until we're out of the vertical blank period before the one | |
5781 | * targeted by the flip | |
5782 | */ | |
5783 | while ((acrtc_attach->enabled && | |
5784 | (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, | |
5785 | 0, &vpos, &hpos, NULL, | |
5786 | NULL, &pcrtc->hwmode) | |
5787 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == | |
5788 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
5789 | (int)(target_vblank - | |
5790 | amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) { | |
5791 | usleep_range(1000, 1100); | |
5792 | } | |
5793 | ||
5794 | if (acrtc_attach->base.state->event) { | |
5795 | drm_crtc_vblank_get(pcrtc); | |
5796 | ||
5797 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
5798 | ||
5799 | WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); | |
5800 | prepare_flip_isr(acrtc_attach); | |
5801 | ||
5802 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
5803 | } | |
5804 | ||
5805 | if (acrtc_state->stream) { | |
8a48b44c | 5806 | if (acrtc_state->freesync_vrr_info_changed) |
74aa7bd4 | 5807 | bundle->stream_update.vrr_infopacket = |
8a48b44c | 5808 | &acrtc_state->stream->vrr_infopacket; |
e7b07cee | 5809 | } |
e7b07cee HW |
5810 | } |
5811 | ||
bc92c065 | 5812 | /* Update the planes if changed or disable if we don't have any. */ |
ed9656fb ES |
5813 | if ((planes_count || acrtc_state->active_planes == 0) && |
5814 | acrtc_state->stream) { | |
bc7f670e | 5815 | if (new_pcrtc_state->mode_changed) { |
74aa7bd4 DF |
5816 | bundle->stream_update.src = acrtc_state->stream->src; |
5817 | bundle->stream_update.dst = acrtc_state->stream->dst; | |
e7b07cee HW |
5818 | } |
5819 | ||
cf020d49 NK |
5820 | if (new_pcrtc_state->color_mgmt_changed) { |
5821 | /* | |
5822 | * TODO: This isn't fully correct since we've actually | |
5823 | * already modified the stream in place. | |
5824 | */ | |
5825 | bundle->stream_update.gamut_remap = | |
5826 | &acrtc_state->stream->gamut_remap_matrix; | |
5827 | bundle->stream_update.output_csc_transform = | |
5828 | &acrtc_state->stream->csc_color_matrix; | |
5829 | bundle->stream_update.out_transfer_func = | |
5830 | acrtc_state->stream->out_transfer_func; | |
5831 | } | |
bc7f670e | 5832 | |
8a48b44c | 5833 | acrtc_state->stream->abm_level = acrtc_state->abm_level; |
bc7f670e | 5834 | if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) |
74aa7bd4 | 5835 | bundle->stream_update.abm_level = &acrtc_state->abm_level; |
44d09c6a | 5836 | |
e63e2491 EB |
5837 | /* |
5838 | * If FreeSync state on the stream has changed then we need to | |
5839 | * re-adjust the min/max bounds now that DC doesn't handle this | |
5840 | * as part of commit. | |
5841 | */ | |
5842 | if (amdgpu_dm_vrr_active(dm_old_crtc_state) != | |
5843 | amdgpu_dm_vrr_active(acrtc_state)) { | |
5844 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
5845 | dc_stream_adjust_vmin_vmax( | |
5846 | dm->dc, acrtc_state->stream, | |
5847 | &acrtc_state->vrr_params.adjust); | |
5848 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
5849 | } | |
5850 | ||
bc7f670e DF |
5851 | mutex_lock(&dm->dc_lock); |
5852 | dc_commit_updates_for_stream(dm->dc, | |
74aa7bd4 | 5853 | bundle->surface_updates, |
bc7f670e DF |
5854 | planes_count, |
5855 | acrtc_state->stream, | |
74aa7bd4 | 5856 | &bundle->stream_update, |
bc7f670e DF |
5857 | dc_state); |
5858 | mutex_unlock(&dm->dc_lock); | |
e7b07cee | 5859 | } |
4b510503 | 5860 | |
8ad27806 NK |
5861 | /* |
5862 | * Update cursor state *after* programming all the planes. | |
5863 | * This avoids redundant programming in the case where we're going | |
5864 | * to be disabling a single plane - those pipes are being disabled. | |
5865 | */ | |
5866 | if (acrtc_state->active_planes) | |
5867 | amdgpu_dm_commit_cursors(state); | |
80c218d5 | 5868 | |
4b510503 | 5869 | cleanup: |
74aa7bd4 | 5870 | kfree(bundle); |
e7b07cee HW |
5871 | } |
5872 | ||
6ce8f316 NK |
5873 | static void amdgpu_dm_commit_audio(struct drm_device *dev, |
5874 | struct drm_atomic_state *state) | |
5875 | { | |
5876 | struct amdgpu_device *adev = dev->dev_private; | |
5877 | struct amdgpu_dm_connector *aconnector; | |
5878 | struct drm_connector *connector; | |
5879 | struct drm_connector_state *old_con_state, *new_con_state; | |
5880 | struct drm_crtc_state *new_crtc_state; | |
5881 | struct dm_crtc_state *new_dm_crtc_state; | |
5882 | const struct dc_stream_status *status; | |
5883 | int i, inst; | |
5884 | ||
5885 | /* Notify device removals. */ | |
5886 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { | |
5887 | if (old_con_state->crtc != new_con_state->crtc) { | |
5888 | /* CRTC changes require notification. */ | |
5889 | goto notify; | |
5890 | } | |
5891 | ||
5892 | if (!new_con_state->crtc) | |
5893 | continue; | |
5894 | ||
5895 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
5896 | state, new_con_state->crtc); | |
5897 | ||
5898 | if (!new_crtc_state) | |
5899 | continue; | |
5900 | ||
5901 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
5902 | continue; | |
5903 | ||
5904 | notify: | |
5905 | aconnector = to_amdgpu_dm_connector(connector); | |
5906 | ||
5907 | mutex_lock(&adev->dm.audio_lock); | |
5908 | inst = aconnector->audio_inst; | |
5909 | aconnector->audio_inst = -1; | |
5910 | mutex_unlock(&adev->dm.audio_lock); | |
5911 | ||
5912 | amdgpu_dm_audio_eld_notify(adev, inst); | |
5913 | } | |
5914 | ||
5915 | /* Notify audio device additions. */ | |
5916 | for_each_new_connector_in_state(state, connector, new_con_state, i) { | |
5917 | if (!new_con_state->crtc) | |
5918 | continue; | |
5919 | ||
5920 | new_crtc_state = drm_atomic_get_new_crtc_state( | |
5921 | state, new_con_state->crtc); | |
5922 | ||
5923 | if (!new_crtc_state) | |
5924 | continue; | |
5925 | ||
5926 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) | |
5927 | continue; | |
5928 | ||
5929 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); | |
5930 | if (!new_dm_crtc_state->stream) | |
5931 | continue; | |
5932 | ||
5933 | status = dc_stream_get_status(new_dm_crtc_state->stream); | |
5934 | if (!status) | |
5935 | continue; | |
5936 | ||
5937 | aconnector = to_amdgpu_dm_connector(connector); | |
5938 | ||
5939 | mutex_lock(&adev->dm.audio_lock); | |
5940 | inst = status->audio_inst; | |
5941 | aconnector->audio_inst = inst; | |
5942 | mutex_unlock(&adev->dm.audio_lock); | |
5943 | ||
5944 | amdgpu_dm_audio_eld_notify(adev, inst); | |
5945 | } | |
5946 | } | |
5947 | ||
b5e83f6f NK |
5948 | /* |
5949 | * Enable interrupts on CRTCs that are newly active, undergone | |
5950 | * a modeset, or have active planes again. | |
5951 | * | |
5952 | * Done in two passes, based on the for_modeset flag: | |
5953 | * Pass 1: For CRTCs going through modeset | |
5954 | * Pass 2: For CRTCs going from 0 to n active planes | |
5955 | * | |
5956 | * Interrupts can only be enabled after the planes are programmed, | |
5957 | * so this requires a two-pass approach since we don't want to | |
5958 | * just defer the interrupts until after commit planes every time. | |
5959 | */ | |
5960 | static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev, | |
5961 | struct drm_atomic_state *state, | |
5962 | bool for_modeset) | |
5963 | { | |
5964 | struct amdgpu_device *adev = dev->dev_private; | |
5965 | struct drm_crtc *crtc; | |
5966 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; | |
5967 | int i; | |
14b25846 | 5968 | enum amdgpu_dm_pipe_crc_source source; |
b5e83f6f NK |
5969 | |
5970 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, | |
5971 | new_crtc_state, i) { | |
5972 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
5973 | struct dm_crtc_state *dm_new_crtc_state = | |
5974 | to_dm_crtc_state(new_crtc_state); | |
5975 | struct dm_crtc_state *dm_old_crtc_state = | |
5976 | to_dm_crtc_state(old_crtc_state); | |
5977 | bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state); | |
5978 | bool run_pass; | |
5979 | ||
5980 | run_pass = (for_modeset && modeset) || | |
5981 | (!for_modeset && !modeset && | |
5982 | !dm_old_crtc_state->interrupts_enabled); | |
5983 | ||
5984 | if (!run_pass) | |
5985 | continue; | |
5986 | ||
b5e83f6f NK |
5987 | if (!dm_new_crtc_state->interrupts_enabled) |
5988 | continue; | |
5989 | ||
5990 | manage_dm_interrupts(adev, acrtc, true); | |
5991 | ||
5992 | #ifdef CONFIG_DEBUG_FS | |
5993 | /* The stream has changed so CRC capture needs to re-enabled. */ | |
14b25846 DZ |
5994 | source = dm_new_crtc_state->crc_src; |
5995 | if (amdgpu_dm_is_valid_crc_source(source)) { | |
5996 | dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE; | |
5997 | if (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) | |
5998 | amdgpu_dm_crtc_set_crc_source(crtc, "crtc"); | |
5999 | else if (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) | |
6000 | amdgpu_dm_crtc_set_crc_source(crtc, "dprx"); | |
b5e83f6f NK |
6001 | } |
6002 | #endif | |
6003 | } | |
6004 | } | |
6005 | ||
1f6010a9 | 6006 | /* |
27b3f4fc LSL |
6007 | * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC |
6008 | * @crtc_state: the DRM CRTC state | |
6009 | * @stream_state: the DC stream state. | |
6010 | * | |
6011 | * Copy the mirrored transient state flags from DRM, to DC. It is used to bring | |
6012 | * a dc_stream_state's flags in sync with a drm_crtc_state's flags. | |
6013 | */ | |
6014 | static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, | |
6015 | struct dc_stream_state *stream_state) | |
6016 | { | |
b9952f93 | 6017 | stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); |
27b3f4fc | 6018 | } |
e7b07cee | 6019 | |
7578ecda AD |
6020 | static int amdgpu_dm_atomic_commit(struct drm_device *dev, |
6021 | struct drm_atomic_state *state, | |
6022 | bool nonblock) | |
e7b07cee HW |
6023 | { |
6024 | struct drm_crtc *crtc; | |
c2cea706 | 6025 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
e7b07cee HW |
6026 | struct amdgpu_device *adev = dev->dev_private; |
6027 | int i; | |
6028 | ||
6029 | /* | |
d6ef9b41 NK |
6030 | * We evade vblank and pflip interrupts on CRTCs that are undergoing |
6031 | * a modeset, being disabled, or have no active planes. | |
6032 | * | |
6033 | * It's done in atomic commit rather than commit tail for now since | |
6034 | * some of these interrupt handlers access the current CRTC state and | |
6035 | * potentially the stream pointer itself. | |
6036 | * | |
6037 | * Since the atomic state is swapped within atomic commit and not within | |
6038 | * commit tail this would leave to new state (that hasn't been committed yet) | |
6039 | * being accesssed from within the handlers. | |
6040 | * | |
6041 | * TODO: Fix this so we can do this in commit tail and not have to block | |
6042 | * in atomic check. | |
e7b07cee | 6043 | */ |
c2cea706 | 6044 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
54d76575 | 6045 | struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
428da2bd | 6046 | struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee HW |
6047 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
6048 | ||
d6ef9b41 NK |
6049 | if (dm_old_crtc_state->interrupts_enabled && |
6050 | (!dm_new_crtc_state->interrupts_enabled || | |
6051 | drm_atomic_crtc_needs_modeset(new_crtc_state))) { | |
428da2bd | 6052 | /* |
e39575b9 NK |
6053 | * Drop the extra vblank reference added by CRC |
6054 | * capture if applicable. | |
428da2bd | 6055 | */ |
14b25846 | 6056 | if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) |
428da2bd | 6057 | drm_crtc_vblank_put(crtc); |
e39575b9 NK |
6058 | |
6059 | /* | |
6060 | * Only keep CRC capture enabled if there's | |
6061 | * still a stream for the CRTC. | |
6062 | */ | |
6063 | if (!dm_new_crtc_state->stream) | |
14b25846 | 6064 | dm_new_crtc_state->crc_src = AMDGPU_DM_PIPE_CRC_SOURCE_NONE; |
428da2bd | 6065 | |
e7b07cee | 6066 | manage_dm_interrupts(adev, acrtc, false); |
428da2bd | 6067 | } |
e7b07cee | 6068 | } |
1f6010a9 DF |
6069 | /* |
6070 | * Add check here for SoC's that support hardware cursor plane, to | |
6071 | * unset legacy_cursor_update | |
6072 | */ | |
e7b07cee HW |
6073 | |
6074 | return drm_atomic_helper_commit(dev, state, nonblock); | |
6075 | ||
6076 | /*TODO Handle EINTR, reenable IRQ*/ | |
6077 | } | |
6078 | ||
b8592b48 LL |
6079 | /** |
6080 | * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. | |
6081 | * @state: The atomic state to commit | |
6082 | * | |
6083 | * This will tell DC to commit the constructed DC state from atomic_check, | |
6084 | * programming the hardware. Any failures here implies a hardware failure, since | |
6085 | * atomic check should have filtered anything non-kosher. | |
6086 | */ | |
7578ecda | 6087 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) |
e7b07cee HW |
6088 | { |
6089 | struct drm_device *dev = state->dev; | |
6090 | struct amdgpu_device *adev = dev->dev_private; | |
6091 | struct amdgpu_display_manager *dm = &adev->dm; | |
6092 | struct dm_atomic_state *dm_state; | |
eb3dc897 | 6093 | struct dc_state *dc_state = NULL, *dc_state_temp = NULL; |
e7b07cee | 6094 | uint32_t i, j; |
5cc6dcbd | 6095 | struct drm_crtc *crtc; |
0bc9706d | 6096 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
e7b07cee HW |
6097 | unsigned long flags; |
6098 | bool wait_for_vblank = true; | |
6099 | struct drm_connector *connector; | |
c2cea706 | 6100 | struct drm_connector_state *old_con_state, *new_con_state; |
54d76575 | 6101 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
fe2a1965 | 6102 | int crtc_disable_count = 0; |
e7b07cee HW |
6103 | |
6104 | drm_atomic_helper_update_legacy_modeset_state(dev, state); | |
6105 | ||
eb3dc897 NK |
6106 | dm_state = dm_atomic_get_new_state(state); |
6107 | if (dm_state && dm_state->context) { | |
6108 | dc_state = dm_state->context; | |
6109 | } else { | |
6110 | /* No state changes, retain current state. */ | |
813d20dc | 6111 | dc_state_temp = dc_create_state(dm->dc); |
eb3dc897 NK |
6112 | ASSERT(dc_state_temp); |
6113 | dc_state = dc_state_temp; | |
6114 | dc_resource_state_copy_construct_current(dm->dc, dc_state); | |
6115 | } | |
e7b07cee HW |
6116 | |
6117 | /* update changed items */ | |
0bc9706d | 6118 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
e7b07cee | 6119 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 6120 | |
54d76575 LSL |
6121 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
6122 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
e7b07cee | 6123 | |
f1ad2f5e | 6124 | DRM_DEBUG_DRIVER( |
e7b07cee HW |
6125 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " |
6126 | "planes_changed:%d, mode_changed:%d,active_changed:%d," | |
6127 | "connectors_changed:%d\n", | |
6128 | acrtc->crtc_id, | |
0bc9706d LSL |
6129 | new_crtc_state->enable, |
6130 | new_crtc_state->active, | |
6131 | new_crtc_state->planes_changed, | |
6132 | new_crtc_state->mode_changed, | |
6133 | new_crtc_state->active_changed, | |
6134 | new_crtc_state->connectors_changed); | |
e7b07cee | 6135 | |
27b3f4fc LSL |
6136 | /* Copy all transient state flags into dc state */ |
6137 | if (dm_new_crtc_state->stream) { | |
6138 | amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, | |
6139 | dm_new_crtc_state->stream); | |
6140 | } | |
6141 | ||
e7b07cee HW |
6142 | /* handles headless hotplug case, updating new_state and |
6143 | * aconnector as needed | |
6144 | */ | |
6145 | ||
54d76575 | 6146 | if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { |
e7b07cee | 6147 | |
f1ad2f5e | 6148 | DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 6149 | |
54d76575 | 6150 | if (!dm_new_crtc_state->stream) { |
e7b07cee | 6151 | /* |
b830ebc9 HW |
6152 | * this could happen because of issues with |
6153 | * userspace notifications delivery. | |
6154 | * In this case userspace tries to set mode on | |
1f6010a9 DF |
6155 | * display which is disconnected in fact. |
6156 | * dc_sink is NULL in this case on aconnector. | |
b830ebc9 HW |
6157 | * We expect reset mode will come soon. |
6158 | * | |
6159 | * This can also happen when unplug is done | |
6160 | * during resume sequence ended | |
6161 | * | |
6162 | * In this case, we want to pretend we still | |
6163 | * have a sink to keep the pipe running so that | |
6164 | * hw state is consistent with the sw state | |
6165 | */ | |
f1ad2f5e | 6166 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
e7b07cee HW |
6167 | __func__, acrtc->base.base.id); |
6168 | continue; | |
6169 | } | |
6170 | ||
54d76575 LSL |
6171 | if (dm_old_crtc_state->stream) |
6172 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee | 6173 | |
97028037 LP |
6174 | pm_runtime_get_noresume(dev->dev); |
6175 | ||
e7b07cee | 6176 | acrtc->enabled = true; |
0bc9706d LSL |
6177 | acrtc->hw_mode = new_crtc_state->mode; |
6178 | crtc->hwmode = new_crtc_state->mode; | |
6179 | } else if (modereset_required(new_crtc_state)) { | |
f1ad2f5e | 6180 | DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee HW |
6181 | |
6182 | /* i.e. reset mode */ | |
54d76575 LSL |
6183 | if (dm_old_crtc_state->stream) |
6184 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee HW |
6185 | } |
6186 | } /* for_each_crtc_in_state() */ | |
6187 | ||
eb3dc897 NK |
6188 | if (dc_state) { |
6189 | dm_enable_per_frame_crtc_master_sync(dc_state); | |
674e78ac | 6190 | mutex_lock(&dm->dc_lock); |
eb3dc897 | 6191 | WARN_ON(!dc_commit_state(dm->dc, dc_state)); |
674e78ac | 6192 | mutex_unlock(&dm->dc_lock); |
fa2123db | 6193 | } |
e7b07cee | 6194 | |
0bc9706d | 6195 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 6196 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 6197 | |
54d76575 | 6198 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 6199 | |
54d76575 | 6200 | if (dm_new_crtc_state->stream != NULL) { |
e7b07cee | 6201 | const struct dc_stream_status *status = |
54d76575 | 6202 | dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee | 6203 | |
eb3dc897 | 6204 | if (!status) |
09f609c3 LL |
6205 | status = dc_stream_get_status_from_state(dc_state, |
6206 | dm_new_crtc_state->stream); | |
eb3dc897 | 6207 | |
e7b07cee | 6208 | if (!status) |
54d76575 | 6209 | DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); |
e7b07cee HW |
6210 | else |
6211 | acrtc->otg_inst = status->primary_otg_inst; | |
6212 | } | |
6213 | } | |
6214 | ||
02d6a6fc | 6215 | /* Handle connector state changes */ |
c2cea706 | 6216 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
6217 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
6218 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
6219 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
19afd799 NC |
6220 | struct dc_surface_update dummy_updates[MAX_SURFACES]; |
6221 | struct dc_stream_update stream_update; | |
b232d4ed | 6222 | struct dc_info_packet hdr_packet; |
e7b07cee | 6223 | struct dc_stream_status *status = NULL; |
b232d4ed | 6224 | bool abm_changed, hdr_changed, scaling_changed; |
e7b07cee | 6225 | |
19afd799 NC |
6226 | memset(&dummy_updates, 0, sizeof(dummy_updates)); |
6227 | memset(&stream_update, 0, sizeof(stream_update)); | |
6228 | ||
44d09c6a | 6229 | if (acrtc) { |
0bc9706d | 6230 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
44d09c6a HW |
6231 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
6232 | } | |
0bc9706d | 6233 | |
e7b07cee | 6234 | /* Skip any modesets/resets */ |
0bc9706d | 6235 | if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) |
e7b07cee HW |
6236 | continue; |
6237 | ||
54d76575 | 6238 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
c1ee92f9 DF |
6239 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
6240 | ||
b232d4ed NK |
6241 | scaling_changed = is_scaling_state_different(dm_new_con_state, |
6242 | dm_old_con_state); | |
6243 | ||
6244 | abm_changed = dm_new_crtc_state->abm_level != | |
6245 | dm_old_crtc_state->abm_level; | |
6246 | ||
6247 | hdr_changed = | |
6248 | is_hdr_metadata_different(old_con_state, new_con_state); | |
6249 | ||
6250 | if (!scaling_changed && !abm_changed && !hdr_changed) | |
c1ee92f9 | 6251 | continue; |
e7b07cee | 6252 | |
b232d4ed | 6253 | if (scaling_changed) { |
02d6a6fc DF |
6254 | update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, |
6255 | dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); | |
e7b07cee | 6256 | |
02d6a6fc DF |
6257 | stream_update.src = dm_new_crtc_state->stream->src; |
6258 | stream_update.dst = dm_new_crtc_state->stream->dst; | |
6259 | } | |
6260 | ||
b232d4ed | 6261 | if (abm_changed) { |
02d6a6fc DF |
6262 | dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; |
6263 | ||
6264 | stream_update.abm_level = &dm_new_crtc_state->abm_level; | |
6265 | } | |
70e8ffc5 | 6266 | |
b232d4ed NK |
6267 | if (hdr_changed) { |
6268 | fill_hdr_info_packet(new_con_state, &hdr_packet); | |
6269 | stream_update.hdr_static_metadata = &hdr_packet; | |
6270 | } | |
6271 | ||
54d76575 | 6272 | status = dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee | 6273 | WARN_ON(!status); |
3be5262e | 6274 | WARN_ON(!status->plane_count); |
e7b07cee | 6275 | |
02d6a6fc DF |
6276 | /* |
6277 | * TODO: DC refuses to perform stream updates without a dc_surface_update. | |
6278 | * Here we create an empty update on each plane. | |
6279 | * To fix this, DC should permit updating only stream properties. | |
6280 | */ | |
6281 | for (j = 0; j < status->plane_count; j++) | |
6282 | dummy_updates[j].surface = status->plane_states[0]; | |
6283 | ||
6284 | ||
6285 | mutex_lock(&dm->dc_lock); | |
6286 | dc_commit_updates_for_stream(dm->dc, | |
6287 | dummy_updates, | |
6288 | status->plane_count, | |
6289 | dm_new_crtc_state->stream, | |
6290 | &stream_update, | |
6291 | dc_state); | |
6292 | mutex_unlock(&dm->dc_lock); | |
e7b07cee HW |
6293 | } |
6294 | ||
b5e83f6f | 6295 | /* Count number of newly disabled CRTCs for dropping PM refs later. */ |
e1fc2dca | 6296 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, |
057be086 | 6297 | new_crtc_state, i) { |
fe2a1965 LP |
6298 | if (old_crtc_state->active && !new_crtc_state->active) |
6299 | crtc_disable_count++; | |
6300 | ||
54d76575 | 6301 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e1fc2dca | 6302 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
66b0c973 | 6303 | |
057be086 NK |
6304 | /* Update freesync active state. */ |
6305 | pre_update_freesync_state_on_stream(dm, dm_new_crtc_state); | |
6306 | ||
66b0c973 MK |
6307 | /* Handle vrr on->off / off->on transitions */ |
6308 | amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, | |
6309 | dm_new_crtc_state); | |
e7b07cee HW |
6310 | } |
6311 | ||
b5e83f6f NK |
6312 | /* Enable interrupts for CRTCs going through a modeset. */ |
6313 | amdgpu_dm_enable_crtc_interrupts(dev, state, true); | |
e7b07cee | 6314 | |
420cd472 DF |
6315 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) |
6316 | if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) | |
6317 | wait_for_vblank = false; | |
6318 | ||
e7b07cee | 6319 | /* update planes when needed per crtc*/ |
5cc6dcbd | 6320 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { |
54d76575 | 6321 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 6322 | |
54d76575 | 6323 | if (dm_new_crtc_state->stream) |
eb3dc897 | 6324 | amdgpu_dm_commit_planes(state, dc_state, dev, |
420cd472 | 6325 | dm, crtc, wait_for_vblank); |
e7b07cee HW |
6326 | } |
6327 | ||
b5e83f6f NK |
6328 | /* Enable interrupts for CRTCs going from 0 to n active planes. */ |
6329 | amdgpu_dm_enable_crtc_interrupts(dev, state, false); | |
e7b07cee | 6330 | |
6ce8f316 NK |
6331 | /* Update audio instances for each connector. */ |
6332 | amdgpu_dm_commit_audio(dev, state); | |
6333 | ||
e7b07cee HW |
6334 | /* |
6335 | * send vblank event on all events not handled in flip and | |
6336 | * mark consumed event for drm_atomic_helper_commit_hw_done | |
6337 | */ | |
6338 | spin_lock_irqsave(&adev->ddev->event_lock, flags); | |
0bc9706d | 6339 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 6340 | |
0bc9706d LSL |
6341 | if (new_crtc_state->event) |
6342 | drm_send_event_locked(dev, &new_crtc_state->event->base); | |
e7b07cee | 6343 | |
0bc9706d | 6344 | new_crtc_state->event = NULL; |
e7b07cee HW |
6345 | } |
6346 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
6347 | ||
29c8f234 LL |
6348 | /* Signal HW programming completion */ |
6349 | drm_atomic_helper_commit_hw_done(state); | |
e7b07cee HW |
6350 | |
6351 | if (wait_for_vblank) | |
320a1274 | 6352 | drm_atomic_helper_wait_for_flip_done(dev, state); |
e7b07cee HW |
6353 | |
6354 | drm_atomic_helper_cleanup_planes(dev, state); | |
97028037 | 6355 | |
1f6010a9 DF |
6356 | /* |
6357 | * Finally, drop a runtime PM reference for each newly disabled CRTC, | |
97028037 LP |
6358 | * so we can put the GPU into runtime suspend if we're not driving any |
6359 | * displays anymore | |
6360 | */ | |
fe2a1965 LP |
6361 | for (i = 0; i < crtc_disable_count; i++) |
6362 | pm_runtime_put_autosuspend(dev->dev); | |
97028037 | 6363 | pm_runtime_mark_last_busy(dev->dev); |
eb3dc897 NK |
6364 | |
6365 | if (dc_state_temp) | |
6366 | dc_release_state(dc_state_temp); | |
e7b07cee HW |
6367 | } |
6368 | ||
6369 | ||
6370 | static int dm_force_atomic_commit(struct drm_connector *connector) | |
6371 | { | |
6372 | int ret = 0; | |
6373 | struct drm_device *ddev = connector->dev; | |
6374 | struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); | |
6375 | struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
6376 | struct drm_plane *plane = disconnected_acrtc->base.primary; | |
6377 | struct drm_connector_state *conn_state; | |
6378 | struct drm_crtc_state *crtc_state; | |
6379 | struct drm_plane_state *plane_state; | |
6380 | ||
6381 | if (!state) | |
6382 | return -ENOMEM; | |
6383 | ||
6384 | state->acquire_ctx = ddev->mode_config.acquire_ctx; | |
6385 | ||
6386 | /* Construct an atomic state to restore previous display setting */ | |
6387 | ||
6388 | /* | |
6389 | * Attach connectors to drm_atomic_state | |
6390 | */ | |
6391 | conn_state = drm_atomic_get_connector_state(state, connector); | |
6392 | ||
6393 | ret = PTR_ERR_OR_ZERO(conn_state); | |
6394 | if (ret) | |
6395 | goto err; | |
6396 | ||
6397 | /* Attach crtc to drm_atomic_state*/ | |
6398 | crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); | |
6399 | ||
6400 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
6401 | if (ret) | |
6402 | goto err; | |
6403 | ||
6404 | /* force a restore */ | |
6405 | crtc_state->mode_changed = true; | |
6406 | ||
6407 | /* Attach plane to drm_atomic_state */ | |
6408 | plane_state = drm_atomic_get_plane_state(state, plane); | |
6409 | ||
6410 | ret = PTR_ERR_OR_ZERO(plane_state); | |
6411 | if (ret) | |
6412 | goto err; | |
6413 | ||
6414 | ||
6415 | /* Call commit internally with the state we just constructed */ | |
6416 | ret = drm_atomic_commit(state); | |
6417 | if (!ret) | |
6418 | return 0; | |
6419 | ||
6420 | err: | |
6421 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
6422 | drm_atomic_state_put(state); | |
6423 | ||
6424 | return ret; | |
6425 | } | |
6426 | ||
6427 | /* | |
1f6010a9 DF |
6428 | * This function handles all cases when set mode does not come upon hotplug. |
6429 | * This includes when a display is unplugged then plugged back into the | |
6430 | * same port and when running without usermode desktop manager supprot | |
e7b07cee | 6431 | */ |
3ee6b26b AD |
6432 | void dm_restore_drm_connector_state(struct drm_device *dev, |
6433 | struct drm_connector *connector) | |
e7b07cee | 6434 | { |
c84dec2f | 6435 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
6436 | struct amdgpu_crtc *disconnected_acrtc; |
6437 | struct dm_crtc_state *acrtc_state; | |
6438 | ||
6439 | if (!aconnector->dc_sink || !connector->state || !connector->encoder) | |
6440 | return; | |
6441 | ||
6442 | disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
70e8ffc5 HW |
6443 | if (!disconnected_acrtc) |
6444 | return; | |
e7b07cee | 6445 | |
70e8ffc5 HW |
6446 | acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); |
6447 | if (!acrtc_state->stream) | |
e7b07cee HW |
6448 | return; |
6449 | ||
6450 | /* | |
6451 | * If the previous sink is not released and different from the current, | |
6452 | * we deduce we are in a state where we can not rely on usermode call | |
6453 | * to turn on the display, so we do it here | |
6454 | */ | |
6455 | if (acrtc_state->stream->sink != aconnector->dc_sink) | |
6456 | dm_force_atomic_commit(&aconnector->base); | |
6457 | } | |
6458 | ||
1f6010a9 | 6459 | /* |
e7b07cee HW |
6460 | * Grabs all modesetting locks to serialize against any blocking commits, |
6461 | * Waits for completion of all non blocking commits. | |
6462 | */ | |
3ee6b26b AD |
6463 | static int do_aquire_global_lock(struct drm_device *dev, |
6464 | struct drm_atomic_state *state) | |
e7b07cee HW |
6465 | { |
6466 | struct drm_crtc *crtc; | |
6467 | struct drm_crtc_commit *commit; | |
6468 | long ret; | |
6469 | ||
1f6010a9 DF |
6470 | /* |
6471 | * Adding all modeset locks to aquire_ctx will | |
e7b07cee HW |
6472 | * ensure that when the framework release it the |
6473 | * extra locks we are locking here will get released to | |
6474 | */ | |
6475 | ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); | |
6476 | if (ret) | |
6477 | return ret; | |
6478 | ||
6479 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6480 | spin_lock(&crtc->commit_lock); | |
6481 | commit = list_first_entry_or_null(&crtc->commit_list, | |
6482 | struct drm_crtc_commit, commit_entry); | |
6483 | if (commit) | |
6484 | drm_crtc_commit_get(commit); | |
6485 | spin_unlock(&crtc->commit_lock); | |
6486 | ||
6487 | if (!commit) | |
6488 | continue; | |
6489 | ||
1f6010a9 DF |
6490 | /* |
6491 | * Make sure all pending HW programming completed and | |
e7b07cee HW |
6492 | * page flips done |
6493 | */ | |
6494 | ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); | |
6495 | ||
6496 | if (ret > 0) | |
6497 | ret = wait_for_completion_interruptible_timeout( | |
6498 | &commit->flip_done, 10*HZ); | |
6499 | ||
6500 | if (ret == 0) | |
6501 | DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " | |
b830ebc9 | 6502 | "timed out\n", crtc->base.id, crtc->name); |
e7b07cee HW |
6503 | |
6504 | drm_crtc_commit_put(commit); | |
6505 | } | |
6506 | ||
6507 | return ret < 0 ? ret : 0; | |
6508 | } | |
6509 | ||
bb47de73 NK |
6510 | static void get_freesync_config_for_crtc( |
6511 | struct dm_crtc_state *new_crtc_state, | |
6512 | struct dm_connector_state *new_con_state) | |
98e6436d AK |
6513 | { |
6514 | struct mod_freesync_config config = {0}; | |
98e6436d AK |
6515 | struct amdgpu_dm_connector *aconnector = |
6516 | to_amdgpu_dm_connector(new_con_state->base.connector); | |
a057ec46 | 6517 | struct drm_display_mode *mode = &new_crtc_state->base.mode; |
0ab925d3 | 6518 | int vrefresh = drm_mode_vrefresh(mode); |
98e6436d | 6519 | |
a057ec46 | 6520 | new_crtc_state->vrr_supported = new_con_state->freesync_capable && |
0ab925d3 NK |
6521 | vrefresh >= aconnector->min_vfreq && |
6522 | vrefresh <= aconnector->max_vfreq; | |
bb47de73 | 6523 | |
a057ec46 IB |
6524 | if (new_crtc_state->vrr_supported) { |
6525 | new_crtc_state->stream->ignore_msa_timing_param = true; | |
bb47de73 | 6526 | config.state = new_crtc_state->base.vrr_enabled ? |
98e6436d AK |
6527 | VRR_STATE_ACTIVE_VARIABLE : |
6528 | VRR_STATE_INACTIVE; | |
6529 | config.min_refresh_in_uhz = | |
6530 | aconnector->min_vfreq * 1000000; | |
6531 | config.max_refresh_in_uhz = | |
6532 | aconnector->max_vfreq * 1000000; | |
69ff8845 | 6533 | config.vsif_supported = true; |
180db303 | 6534 | config.btr = true; |
98e6436d AK |
6535 | } |
6536 | ||
bb47de73 NK |
6537 | new_crtc_state->freesync_config = config; |
6538 | } | |
98e6436d | 6539 | |
bb47de73 NK |
6540 | static void reset_freesync_config_for_crtc( |
6541 | struct dm_crtc_state *new_crtc_state) | |
6542 | { | |
6543 | new_crtc_state->vrr_supported = false; | |
98e6436d | 6544 | |
180db303 NK |
6545 | memset(&new_crtc_state->vrr_params, 0, |
6546 | sizeof(new_crtc_state->vrr_params)); | |
bb47de73 NK |
6547 | memset(&new_crtc_state->vrr_infopacket, 0, |
6548 | sizeof(new_crtc_state->vrr_infopacket)); | |
98e6436d AK |
6549 | } |
6550 | ||
4b9674e5 LL |
6551 | static int dm_update_crtc_state(struct amdgpu_display_manager *dm, |
6552 | struct drm_atomic_state *state, | |
6553 | struct drm_crtc *crtc, | |
6554 | struct drm_crtc_state *old_crtc_state, | |
6555 | struct drm_crtc_state *new_crtc_state, | |
6556 | bool enable, | |
6557 | bool *lock_and_validation_needed) | |
e7b07cee | 6558 | { |
eb3dc897 | 6559 | struct dm_atomic_state *dm_state = NULL; |
54d76575 | 6560 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
9635b754 | 6561 | struct dc_stream_state *new_stream; |
62f55537 | 6562 | int ret = 0; |
d4d4a645 | 6563 | |
1f6010a9 DF |
6564 | /* |
6565 | * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set | |
6566 | * update changed items | |
6567 | */ | |
4b9674e5 LL |
6568 | struct amdgpu_crtc *acrtc = NULL; |
6569 | struct amdgpu_dm_connector *aconnector = NULL; | |
6570 | struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; | |
6571 | struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; | |
e7b07cee | 6572 | |
4b9674e5 | 6573 | new_stream = NULL; |
9635b754 | 6574 | |
4b9674e5 LL |
6575 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
6576 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
6577 | acrtc = to_amdgpu_crtc(crtc); | |
4b9674e5 | 6578 | aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
19f89e23 | 6579 | |
4b9674e5 LL |
6580 | /* TODO This hack should go away */ |
6581 | if (aconnector && enable) { | |
6582 | /* Make sure fake sink is created in plug-in scenario */ | |
6583 | drm_new_conn_state = drm_atomic_get_new_connector_state(state, | |
6584 | &aconnector->base); | |
6585 | drm_old_conn_state = drm_atomic_get_old_connector_state(state, | |
6586 | &aconnector->base); | |
19f89e23 | 6587 | |
4b9674e5 LL |
6588 | if (IS_ERR(drm_new_conn_state)) { |
6589 | ret = PTR_ERR_OR_ZERO(drm_new_conn_state); | |
6590 | goto fail; | |
6591 | } | |
19f89e23 | 6592 | |
4b9674e5 LL |
6593 | dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); |
6594 | dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); | |
19f89e23 | 6595 | |
02d35a67 JFZ |
6596 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
6597 | goto skip_modeset; | |
6598 | ||
4b9674e5 LL |
6599 | new_stream = create_stream_for_sink(aconnector, |
6600 | &new_crtc_state->mode, | |
6601 | dm_new_conn_state, | |
6602 | dm_old_crtc_state->stream); | |
19f89e23 | 6603 | |
4b9674e5 LL |
6604 | /* |
6605 | * we can have no stream on ACTION_SET if a display | |
6606 | * was disconnected during S3, in this case it is not an | |
6607 | * error, the OS will be updated after detection, and | |
6608 | * will do the right thing on next atomic commit | |
6609 | */ | |
19f89e23 | 6610 | |
4b9674e5 LL |
6611 | if (!new_stream) { |
6612 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", | |
6613 | __func__, acrtc->base.base.id); | |
6614 | ret = -ENOMEM; | |
6615 | goto fail; | |
6616 | } | |
e7b07cee | 6617 | |
4b9674e5 | 6618 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; |
98e6436d | 6619 | |
88694af9 NK |
6620 | ret = fill_hdr_info_packet(drm_new_conn_state, |
6621 | &new_stream->hdr_static_metadata); | |
6622 | if (ret) | |
6623 | goto fail; | |
6624 | ||
7e930949 NK |
6625 | /* |
6626 | * If we already removed the old stream from the context | |
6627 | * (and set the new stream to NULL) then we can't reuse | |
6628 | * the old stream even if the stream and scaling are unchanged. | |
6629 | * We'll hit the BUG_ON and black screen. | |
6630 | * | |
6631 | * TODO: Refactor this function to allow this check to work | |
6632 | * in all conditions. | |
6633 | */ | |
6634 | if (dm_new_crtc_state->stream && | |
6635 | dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && | |
4b9674e5 LL |
6636 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { |
6637 | new_crtc_state->mode_changed = false; | |
6638 | DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", | |
6639 | new_crtc_state->mode_changed); | |
62f55537 | 6640 | } |
4b9674e5 | 6641 | } |
b830ebc9 | 6642 | |
02d35a67 | 6643 | /* mode_changed flag may get updated above, need to check again */ |
4b9674e5 LL |
6644 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
6645 | goto skip_modeset; | |
e7b07cee | 6646 | |
4b9674e5 LL |
6647 | DRM_DEBUG_DRIVER( |
6648 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " | |
6649 | "planes_changed:%d, mode_changed:%d,active_changed:%d," | |
6650 | "connectors_changed:%d\n", | |
6651 | acrtc->crtc_id, | |
6652 | new_crtc_state->enable, | |
6653 | new_crtc_state->active, | |
6654 | new_crtc_state->planes_changed, | |
6655 | new_crtc_state->mode_changed, | |
6656 | new_crtc_state->active_changed, | |
6657 | new_crtc_state->connectors_changed); | |
62f55537 | 6658 | |
4b9674e5 LL |
6659 | /* Remove stream for any changed/disabled CRTC */ |
6660 | if (!enable) { | |
62f55537 | 6661 | |
4b9674e5 LL |
6662 | if (!dm_old_crtc_state->stream) |
6663 | goto skip_modeset; | |
eb3dc897 | 6664 | |
4b9674e5 LL |
6665 | ret = dm_atomic_get_state(state, &dm_state); |
6666 | if (ret) | |
6667 | goto fail; | |
e7b07cee | 6668 | |
4b9674e5 LL |
6669 | DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", |
6670 | crtc->base.id); | |
62f55537 | 6671 | |
4b9674e5 LL |
6672 | /* i.e. reset mode */ |
6673 | if (dc_remove_stream_from_ctx( | |
6674 | dm->dc, | |
6675 | dm_state->context, | |
6676 | dm_old_crtc_state->stream) != DC_OK) { | |
6677 | ret = -EINVAL; | |
6678 | goto fail; | |
6679 | } | |
62f55537 | 6680 | |
4b9674e5 LL |
6681 | dc_stream_release(dm_old_crtc_state->stream); |
6682 | dm_new_crtc_state->stream = NULL; | |
bb47de73 | 6683 | |
4b9674e5 | 6684 | reset_freesync_config_for_crtc(dm_new_crtc_state); |
62f55537 | 6685 | |
4b9674e5 | 6686 | *lock_and_validation_needed = true; |
62f55537 | 6687 | |
4b9674e5 LL |
6688 | } else {/* Add stream for any updated/enabled CRTC */ |
6689 | /* | |
6690 | * Quick fix to prevent NULL pointer on new_stream when | |
6691 | * added MST connectors not found in existing crtc_state in the chained mode | |
6692 | * TODO: need to dig out the root cause of that | |
6693 | */ | |
6694 | if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) | |
6695 | goto skip_modeset; | |
62f55537 | 6696 | |
4b9674e5 LL |
6697 | if (modereset_required(new_crtc_state)) |
6698 | goto skip_modeset; | |
62f55537 | 6699 | |
4b9674e5 LL |
6700 | if (modeset_required(new_crtc_state, new_stream, |
6701 | dm_old_crtc_state->stream)) { | |
62f55537 | 6702 | |
4b9674e5 | 6703 | WARN_ON(dm_new_crtc_state->stream); |
eb3dc897 | 6704 | |
4b9674e5 LL |
6705 | ret = dm_atomic_get_state(state, &dm_state); |
6706 | if (ret) | |
6707 | goto fail; | |
27b3f4fc | 6708 | |
4b9674e5 | 6709 | dm_new_crtc_state->stream = new_stream; |
62f55537 | 6710 | |
4b9674e5 | 6711 | dc_stream_retain(new_stream); |
1dc90497 | 6712 | |
4b9674e5 LL |
6713 | DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", |
6714 | crtc->base.id); | |
1dc90497 | 6715 | |
4b9674e5 LL |
6716 | if (dc_add_stream_to_ctx( |
6717 | dm->dc, | |
6718 | dm_state->context, | |
6719 | dm_new_crtc_state->stream) != DC_OK) { | |
6720 | ret = -EINVAL; | |
6721 | goto fail; | |
9b690ef3 BL |
6722 | } |
6723 | ||
4b9674e5 LL |
6724 | *lock_and_validation_needed = true; |
6725 | } | |
6726 | } | |
e277adc5 | 6727 | |
4b9674e5 LL |
6728 | skip_modeset: |
6729 | /* Release extra reference */ | |
6730 | if (new_stream) | |
6731 | dc_stream_release(new_stream); | |
e277adc5 | 6732 | |
4b9674e5 LL |
6733 | /* |
6734 | * We want to do dc stream updates that do not require a | |
6735 | * full modeset below. | |
6736 | */ | |
6737 | if (!(enable && aconnector && new_crtc_state->enable && | |
6738 | new_crtc_state->active)) | |
6739 | return 0; | |
6740 | /* | |
6741 | * Given above conditions, the dc state cannot be NULL because: | |
6742 | * 1. We're in the process of enabling CRTCs (just been added | |
6743 | * to the dc context, or already is on the context) | |
6744 | * 2. Has a valid connector attached, and | |
6745 | * 3. Is currently active and enabled. | |
6746 | * => The dc stream state currently exists. | |
6747 | */ | |
6748 | BUG_ON(dm_new_crtc_state->stream == NULL); | |
a9e8d275 | 6749 | |
4b9674e5 LL |
6750 | /* Scaling or underscan settings */ |
6751 | if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) | |
6752 | update_stream_scaling_settings( | |
6753 | &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); | |
98e6436d | 6754 | |
b05e2c5e DF |
6755 | /* ABM settings */ |
6756 | dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; | |
6757 | ||
4b9674e5 LL |
6758 | /* |
6759 | * Color management settings. We also update color properties | |
6760 | * when a modeset is needed, to ensure it gets reprogrammed. | |
6761 | */ | |
6762 | if (dm_new_crtc_state->base.color_mgmt_changed || | |
6763 | drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
cf020d49 | 6764 | ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); |
4b9674e5 LL |
6765 | if (ret) |
6766 | goto fail; | |
62f55537 | 6767 | } |
e7b07cee | 6768 | |
4b9674e5 LL |
6769 | /* Update Freesync settings. */ |
6770 | get_freesync_config_for_crtc(dm_new_crtc_state, | |
6771 | dm_new_conn_state); | |
6772 | ||
62f55537 | 6773 | return ret; |
9635b754 DS |
6774 | |
6775 | fail: | |
6776 | if (new_stream) | |
6777 | dc_stream_release(new_stream); | |
6778 | return ret; | |
62f55537 | 6779 | } |
9b690ef3 | 6780 | |
f6ff2a08 NK |
6781 | static bool should_reset_plane(struct drm_atomic_state *state, |
6782 | struct drm_plane *plane, | |
6783 | struct drm_plane_state *old_plane_state, | |
6784 | struct drm_plane_state *new_plane_state) | |
6785 | { | |
6786 | struct drm_plane *other; | |
6787 | struct drm_plane_state *old_other_state, *new_other_state; | |
6788 | struct drm_crtc_state *new_crtc_state; | |
6789 | int i; | |
6790 | ||
70a1efac NK |
6791 | /* |
6792 | * TODO: Remove this hack once the checks below are sufficient | |
6793 | * enough to determine when we need to reset all the planes on | |
6794 | * the stream. | |
6795 | */ | |
6796 | if (state->allow_modeset) | |
6797 | return true; | |
6798 | ||
f6ff2a08 NK |
6799 | /* Exit early if we know that we're adding or removing the plane. */ |
6800 | if (old_plane_state->crtc != new_plane_state->crtc) | |
6801 | return true; | |
6802 | ||
6803 | /* old crtc == new_crtc == NULL, plane not in context. */ | |
6804 | if (!new_plane_state->crtc) | |
6805 | return false; | |
6806 | ||
6807 | new_crtc_state = | |
6808 | drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); | |
6809 | ||
6810 | if (!new_crtc_state) | |
6811 | return true; | |
6812 | ||
7316c4ad NK |
6813 | /* CRTC Degamma changes currently require us to recreate planes. */ |
6814 | if (new_crtc_state->color_mgmt_changed) | |
6815 | return true; | |
6816 | ||
f6ff2a08 NK |
6817 | if (drm_atomic_crtc_needs_modeset(new_crtc_state)) |
6818 | return true; | |
6819 | ||
6820 | /* | |
6821 | * If there are any new primary or overlay planes being added or | |
6822 | * removed then the z-order can potentially change. To ensure | |
6823 | * correct z-order and pipe acquisition the current DC architecture | |
6824 | * requires us to remove and recreate all existing planes. | |
6825 | * | |
6826 | * TODO: Come up with a more elegant solution for this. | |
6827 | */ | |
6828 | for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { | |
6829 | if (other->type == DRM_PLANE_TYPE_CURSOR) | |
6830 | continue; | |
6831 | ||
6832 | if (old_other_state->crtc != new_plane_state->crtc && | |
6833 | new_other_state->crtc != new_plane_state->crtc) | |
6834 | continue; | |
6835 | ||
6836 | if (old_other_state->crtc != new_other_state->crtc) | |
6837 | return true; | |
6838 | ||
6839 | /* TODO: Remove this once we can handle fast format changes. */ | |
6840 | if (old_other_state->fb && new_other_state->fb && | |
6841 | old_other_state->fb->format != new_other_state->fb->format) | |
6842 | return true; | |
6843 | } | |
6844 | ||
6845 | return false; | |
6846 | } | |
6847 | ||
9e869063 LL |
6848 | static int dm_update_plane_state(struct dc *dc, |
6849 | struct drm_atomic_state *state, | |
6850 | struct drm_plane *plane, | |
6851 | struct drm_plane_state *old_plane_state, | |
6852 | struct drm_plane_state *new_plane_state, | |
6853 | bool enable, | |
6854 | bool *lock_and_validation_needed) | |
62f55537 | 6855 | { |
eb3dc897 NK |
6856 | |
6857 | struct dm_atomic_state *dm_state = NULL; | |
62f55537 | 6858 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; |
0bc9706d | 6859 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
54d76575 | 6860 | struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; |
54d76575 | 6861 | struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; |
f6ff2a08 | 6862 | bool needs_reset; |
62f55537 | 6863 | int ret = 0; |
e7b07cee | 6864 | |
9b690ef3 | 6865 | |
9e869063 LL |
6866 | new_plane_crtc = new_plane_state->crtc; |
6867 | old_plane_crtc = old_plane_state->crtc; | |
6868 | dm_new_plane_state = to_dm_plane_state(new_plane_state); | |
6869 | dm_old_plane_state = to_dm_plane_state(old_plane_state); | |
62f55537 | 6870 | |
9e869063 LL |
6871 | /*TODO Implement atomic check for cursor plane */ |
6872 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
6873 | return 0; | |
9b690ef3 | 6874 | |
f6ff2a08 NK |
6875 | needs_reset = should_reset_plane(state, plane, old_plane_state, |
6876 | new_plane_state); | |
6877 | ||
9e869063 LL |
6878 | /* Remove any changed/removed planes */ |
6879 | if (!enable) { | |
f6ff2a08 | 6880 | if (!needs_reset) |
9e869063 | 6881 | return 0; |
a7b06724 | 6882 | |
9e869063 LL |
6883 | if (!old_plane_crtc) |
6884 | return 0; | |
62f55537 | 6885 | |
9e869063 LL |
6886 | old_crtc_state = drm_atomic_get_old_crtc_state( |
6887 | state, old_plane_crtc); | |
6888 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
9b690ef3 | 6889 | |
9e869063 LL |
6890 | if (!dm_old_crtc_state->stream) |
6891 | return 0; | |
62f55537 | 6892 | |
9e869063 LL |
6893 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
6894 | plane->base.id, old_plane_crtc->base.id); | |
9b690ef3 | 6895 | |
9e869063 LL |
6896 | ret = dm_atomic_get_state(state, &dm_state); |
6897 | if (ret) | |
6898 | return ret; | |
eb3dc897 | 6899 | |
9e869063 LL |
6900 | if (!dc_remove_plane_from_context( |
6901 | dc, | |
6902 | dm_old_crtc_state->stream, | |
6903 | dm_old_plane_state->dc_state, | |
6904 | dm_state->context)) { | |
62f55537 | 6905 | |
9e869063 LL |
6906 | ret = EINVAL; |
6907 | return ret; | |
6908 | } | |
e7b07cee | 6909 | |
9b690ef3 | 6910 | |
9e869063 LL |
6911 | dc_plane_state_release(dm_old_plane_state->dc_state); |
6912 | dm_new_plane_state->dc_state = NULL; | |
1dc90497 | 6913 | |
9e869063 | 6914 | *lock_and_validation_needed = true; |
1dc90497 | 6915 | |
9e869063 LL |
6916 | } else { /* Add new planes */ |
6917 | struct dc_plane_state *dc_new_plane_state; | |
1dc90497 | 6918 | |
9e869063 LL |
6919 | if (drm_atomic_plane_disabling(plane->state, new_plane_state)) |
6920 | return 0; | |
e7b07cee | 6921 | |
9e869063 LL |
6922 | if (!new_plane_crtc) |
6923 | return 0; | |
e7b07cee | 6924 | |
9e869063 LL |
6925 | new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); |
6926 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
1dc90497 | 6927 | |
9e869063 LL |
6928 | if (!dm_new_crtc_state->stream) |
6929 | return 0; | |
62f55537 | 6930 | |
f6ff2a08 | 6931 | if (!needs_reset) |
9e869063 | 6932 | return 0; |
62f55537 | 6933 | |
9e869063 | 6934 | WARN_ON(dm_new_plane_state->dc_state); |
9b690ef3 | 6935 | |
9e869063 LL |
6936 | dc_new_plane_state = dc_create_plane_state(dc); |
6937 | if (!dc_new_plane_state) | |
6938 | return -ENOMEM; | |
62f55537 | 6939 | |
9e869063 LL |
6940 | DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", |
6941 | plane->base.id, new_plane_crtc->base.id); | |
8c45c5db | 6942 | |
695af5f9 | 6943 | ret = fill_dc_plane_attributes( |
9e869063 LL |
6944 | new_plane_crtc->dev->dev_private, |
6945 | dc_new_plane_state, | |
6946 | new_plane_state, | |
6947 | new_crtc_state); | |
6948 | if (ret) { | |
6949 | dc_plane_state_release(dc_new_plane_state); | |
6950 | return ret; | |
6951 | } | |
62f55537 | 6952 | |
9e869063 LL |
6953 | ret = dm_atomic_get_state(state, &dm_state); |
6954 | if (ret) { | |
6955 | dc_plane_state_release(dc_new_plane_state); | |
6956 | return ret; | |
6957 | } | |
eb3dc897 | 6958 | |
9e869063 LL |
6959 | /* |
6960 | * Any atomic check errors that occur after this will | |
6961 | * not need a release. The plane state will be attached | |
6962 | * to the stream, and therefore part of the atomic | |
6963 | * state. It'll be released when the atomic state is | |
6964 | * cleaned. | |
6965 | */ | |
6966 | if (!dc_add_plane_to_context( | |
6967 | dc, | |
6968 | dm_new_crtc_state->stream, | |
6969 | dc_new_plane_state, | |
6970 | dm_state->context)) { | |
62f55537 | 6971 | |
9e869063 LL |
6972 | dc_plane_state_release(dc_new_plane_state); |
6973 | return -EINVAL; | |
6974 | } | |
8c45c5db | 6975 | |
9e869063 | 6976 | dm_new_plane_state->dc_state = dc_new_plane_state; |
000b59ea | 6977 | |
9e869063 LL |
6978 | /* Tell DC to do a full surface update every time there |
6979 | * is a plane change. Inefficient, but works for now. | |
6980 | */ | |
6981 | dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; | |
6982 | ||
6983 | *lock_and_validation_needed = true; | |
62f55537 | 6984 | } |
e7b07cee HW |
6985 | |
6986 | ||
62f55537 AG |
6987 | return ret; |
6988 | } | |
a87fa993 | 6989 | |
eb3dc897 | 6990 | static int |
f843b308 | 6991 | dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, |
eb3dc897 NK |
6992 | struct drm_atomic_state *state, |
6993 | enum surface_update_type *out_type) | |
6994 | { | |
f843b308 | 6995 | struct dc *dc = dm->dc; |
eb3dc897 NK |
6996 | struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL; |
6997 | int i, j, num_plane, ret = 0; | |
a87fa993 BL |
6998 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6999 | struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; | |
7000 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; | |
7001 | struct drm_plane *plane; | |
7002 | ||
7003 | struct drm_crtc *crtc; | |
7004 | struct drm_crtc_state *new_crtc_state, *old_crtc_state; | |
7005 | struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; | |
7006 | struct dc_stream_status *status = NULL; | |
7007 | ||
fe96b99d | 7008 | struct dc_surface_update *updates; |
a87fa993 BL |
7009 | enum surface_update_type update_type = UPDATE_TYPE_FAST; |
7010 | ||
fe96b99d | 7011 | updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL); |
fe96b99d | 7012 | |
f843b308 NK |
7013 | if (!updates) { |
7014 | DRM_ERROR("Failed to allocate plane updates\n"); | |
4f712911 BL |
7015 | /* Set type to FULL to avoid crashing in DC*/ |
7016 | update_type = UPDATE_TYPE_FULL; | |
eb3dc897 | 7017 | goto cleanup; |
4f712911 | 7018 | } |
a87fa993 BL |
7019 | |
7020 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { | |
004b3938 | 7021 | struct dc_scaling_info scaling_info; |
2aa632c5 NK |
7022 | struct dc_stream_update stream_update; |
7023 | ||
7024 | memset(&stream_update, 0, sizeof(stream_update)); | |
c448a53a | 7025 | |
a87fa993 BL |
7026 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); |
7027 | old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); | |
7028 | num_plane = 0; | |
7029 | ||
6836d239 NK |
7030 | if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) { |
7031 | update_type = UPDATE_TYPE_FULL; | |
7032 | goto cleanup; | |
7033 | } | |
a87fa993 | 7034 | |
6836d239 | 7035 | if (!new_dm_crtc_state->stream) |
c744e974 | 7036 | continue; |
eb3dc897 | 7037 | |
c744e974 NK |
7038 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { |
7039 | new_plane_crtc = new_plane_state->crtc; | |
7040 | old_plane_crtc = old_plane_state->crtc; | |
7041 | new_dm_plane_state = to_dm_plane_state(new_plane_state); | |
7042 | old_dm_plane_state = to_dm_plane_state(old_plane_state); | |
eb3dc897 | 7043 | |
c744e974 NK |
7044 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
7045 | continue; | |
eb3dc897 | 7046 | |
6836d239 NK |
7047 | if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) { |
7048 | update_type = UPDATE_TYPE_FULL; | |
7049 | goto cleanup; | |
7050 | } | |
7051 | ||
c744e974 NK |
7052 | if (crtc != new_plane_crtc) |
7053 | continue; | |
7054 | ||
f843b308 | 7055 | updates[num_plane].surface = new_dm_plane_state->dc_state; |
c744e974 NK |
7056 | |
7057 | if (new_crtc_state->mode_changed) { | |
c744e974 NK |
7058 | stream_update.dst = new_dm_crtc_state->stream->dst; |
7059 | stream_update.src = new_dm_crtc_state->stream->src; | |
7060 | } | |
7061 | ||
7062 | if (new_crtc_state->color_mgmt_changed) { | |
7063 | updates[num_plane].gamma = | |
7064 | new_dm_plane_state->dc_state->gamma_correction; | |
7065 | updates[num_plane].in_transfer_func = | |
7066 | new_dm_plane_state->dc_state->in_transfer_func; | |
7067 | stream_update.gamut_remap = | |
7068 | &new_dm_crtc_state->stream->gamut_remap_matrix; | |
cf020d49 NK |
7069 | stream_update.output_csc_transform = |
7070 | &new_dm_crtc_state->stream->csc_color_matrix; | |
c744e974 NK |
7071 | stream_update.out_transfer_func = |
7072 | new_dm_crtc_state->stream->out_transfer_func; | |
a87fa993 BL |
7073 | } |
7074 | ||
004b3938 NK |
7075 | ret = fill_dc_scaling_info(new_plane_state, |
7076 | &scaling_info); | |
7077 | if (ret) | |
7078 | goto cleanup; | |
7079 | ||
7080 | updates[num_plane].scaling_info = &scaling_info; | |
7081 | ||
c744e974 NK |
7082 | num_plane++; |
7083 | } | |
7084 | ||
7085 | if (num_plane == 0) | |
7086 | continue; | |
7087 | ||
7088 | ret = dm_atomic_get_state(state, &dm_state); | |
7089 | if (ret) | |
7090 | goto cleanup; | |
7091 | ||
7092 | old_dm_state = dm_atomic_get_old_state(state); | |
7093 | if (!old_dm_state) { | |
7094 | ret = -EINVAL; | |
7095 | goto cleanup; | |
7096 | } | |
7097 | ||
7098 | status = dc_stream_get_status_from_state(old_dm_state->context, | |
7099 | new_dm_crtc_state->stream); | |
7100 | ||
f843b308 NK |
7101 | /* |
7102 | * TODO: DC modifies the surface during this call so we need | |
7103 | * to lock here - find a way to do this without locking. | |
7104 | */ | |
7105 | mutex_lock(&dm->dc_lock); | |
c744e974 NK |
7106 | update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, |
7107 | &stream_update, status); | |
f843b308 | 7108 | mutex_unlock(&dm->dc_lock); |
c744e974 NK |
7109 | |
7110 | if (update_type > UPDATE_TYPE_MED) { | |
a87fa993 | 7111 | update_type = UPDATE_TYPE_FULL; |
eb3dc897 | 7112 | goto cleanup; |
a87fa993 BL |
7113 | } |
7114 | } | |
7115 | ||
eb3dc897 | 7116 | cleanup: |
a87fa993 | 7117 | kfree(updates); |
a87fa993 | 7118 | |
eb3dc897 NK |
7119 | *out_type = update_type; |
7120 | return ret; | |
a87fa993 | 7121 | } |
62f55537 | 7122 | |
b8592b48 LL |
7123 | /** |
7124 | * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. | |
7125 | * @dev: The DRM device | |
7126 | * @state: The atomic state to commit | |
7127 | * | |
7128 | * Validate that the given atomic state is programmable by DC into hardware. | |
7129 | * This involves constructing a &struct dc_state reflecting the new hardware | |
7130 | * state we wish to commit, then querying DC to see if it is programmable. It's | |
7131 | * important not to modify the existing DC state. Otherwise, atomic_check | |
7132 | * may unexpectedly commit hardware changes. | |
7133 | * | |
7134 | * When validating the DC state, it's important that the right locks are | |
7135 | * acquired. For full updates case which removes/adds/updates streams on one | |
7136 | * CRTC while flipping on another CRTC, acquiring global lock will guarantee | |
7137 | * that any such full update commit will wait for completion of any outstanding | |
7138 | * flip using DRMs synchronization events. See | |
7139 | * dm_determine_update_type_for_commit() | |
7140 | * | |
7141 | * Note that DM adds the affected connectors for all CRTCs in state, when that | |
7142 | * might not seem necessary. This is because DC stream creation requires the | |
7143 | * DC sink, which is tied to the DRM connector state. Cleaning this up should | |
7144 | * be possible but non-trivial - a possible TODO item. | |
7145 | * | |
7146 | * Return: -Error code if validation failed. | |
7147 | */ | |
7578ecda AD |
7148 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
7149 | struct drm_atomic_state *state) | |
62f55537 | 7150 | { |
62f55537 | 7151 | struct amdgpu_device *adev = dev->dev_private; |
eb3dc897 | 7152 | struct dm_atomic_state *dm_state = NULL; |
62f55537 | 7153 | struct dc *dc = adev->dm.dc; |
62f55537 | 7154 | struct drm_connector *connector; |
c2cea706 | 7155 | struct drm_connector_state *old_con_state, *new_con_state; |
62f55537 | 7156 | struct drm_crtc *crtc; |
fc9e9920 | 7157 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
9e869063 LL |
7158 | struct drm_plane *plane; |
7159 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
a87fa993 BL |
7160 | enum surface_update_type update_type = UPDATE_TYPE_FAST; |
7161 | enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; | |
7162 | ||
1e88ad0a | 7163 | int ret, i; |
e7b07cee | 7164 | |
62f55537 AG |
7165 | /* |
7166 | * This bool will be set for true for any modeset/reset | |
7167 | * or plane update which implies non fast surface update. | |
7168 | */ | |
7169 | bool lock_and_validation_needed = false; | |
7170 | ||
7171 | ret = drm_atomic_helper_check_modeset(dev, state); | |
01e28f9c MD |
7172 | if (ret) |
7173 | goto fail; | |
62f55537 | 7174 | |
1e88ad0a S |
7175 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
7176 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && | |
98e6436d | 7177 | !new_crtc_state->color_mgmt_changed && |
a93587b3 | 7178 | old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled) |
1e88ad0a | 7179 | continue; |
7bef1af3 | 7180 | |
1e88ad0a S |
7181 | if (!new_crtc_state->enable) |
7182 | continue; | |
fc9e9920 | 7183 | |
1e88ad0a S |
7184 | ret = drm_atomic_add_affected_connectors(state, crtc); |
7185 | if (ret) | |
7186 | return ret; | |
fc9e9920 | 7187 | |
1e88ad0a S |
7188 | ret = drm_atomic_add_affected_planes(state, crtc); |
7189 | if (ret) | |
7190 | goto fail; | |
e7b07cee HW |
7191 | } |
7192 | ||
2d9e6431 NK |
7193 | /* |
7194 | * Add all primary and overlay planes on the CRTC to the state | |
7195 | * whenever a plane is enabled to maintain correct z-ordering | |
7196 | * and to enable fast surface updates. | |
7197 | */ | |
7198 | drm_for_each_crtc(crtc, dev) { | |
7199 | bool modified = false; | |
7200 | ||
7201 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { | |
7202 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
7203 | continue; | |
7204 | ||
7205 | if (new_plane_state->crtc == crtc || | |
7206 | old_plane_state->crtc == crtc) { | |
7207 | modified = true; | |
7208 | break; | |
7209 | } | |
7210 | } | |
7211 | ||
7212 | if (!modified) | |
7213 | continue; | |
7214 | ||
7215 | drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { | |
7216 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
7217 | continue; | |
7218 | ||
7219 | new_plane_state = | |
7220 | drm_atomic_get_plane_state(state, plane); | |
7221 | ||
7222 | if (IS_ERR(new_plane_state)) { | |
7223 | ret = PTR_ERR(new_plane_state); | |
7224 | goto fail; | |
7225 | } | |
7226 | } | |
7227 | } | |
7228 | ||
62f55537 | 7229 | /* Remove exiting planes if they are modified */ |
9e869063 LL |
7230 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
7231 | ret = dm_update_plane_state(dc, state, plane, | |
7232 | old_plane_state, | |
7233 | new_plane_state, | |
7234 | false, | |
7235 | &lock_and_validation_needed); | |
7236 | if (ret) | |
7237 | goto fail; | |
62f55537 AG |
7238 | } |
7239 | ||
7240 | /* Disable all crtcs which require disable */ | |
4b9674e5 LL |
7241 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
7242 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
7243 | old_crtc_state, | |
7244 | new_crtc_state, | |
7245 | false, | |
7246 | &lock_and_validation_needed); | |
7247 | if (ret) | |
7248 | goto fail; | |
62f55537 AG |
7249 | } |
7250 | ||
7251 | /* Enable all crtcs which require enable */ | |
4b9674e5 LL |
7252 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
7253 | ret = dm_update_crtc_state(&adev->dm, state, crtc, | |
7254 | old_crtc_state, | |
7255 | new_crtc_state, | |
7256 | true, | |
7257 | &lock_and_validation_needed); | |
7258 | if (ret) | |
7259 | goto fail; | |
62f55537 AG |
7260 | } |
7261 | ||
7262 | /* Add new/modified planes */ | |
9e869063 LL |
7263 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { |
7264 | ret = dm_update_plane_state(dc, state, plane, | |
7265 | old_plane_state, | |
7266 | new_plane_state, | |
7267 | true, | |
7268 | &lock_and_validation_needed); | |
7269 | if (ret) | |
7270 | goto fail; | |
62f55537 AG |
7271 | } |
7272 | ||
b349f76e ES |
7273 | /* Run this here since we want to validate the streams we created */ |
7274 | ret = drm_atomic_helper_check_planes(dev, state); | |
7275 | if (ret) | |
7276 | goto fail; | |
62f55537 | 7277 | |
43d10d30 NK |
7278 | if (state->legacy_cursor_update) { |
7279 | /* | |
7280 | * This is a fast cursor update coming from the plane update | |
7281 | * helper, check if it can be done asynchronously for better | |
7282 | * performance. | |
7283 | */ | |
7284 | state->async_update = | |
7285 | !drm_atomic_helper_async_check(dev, state); | |
7286 | ||
7287 | /* | |
7288 | * Skip the remaining global validation if this is an async | |
7289 | * update. Cursor updates can be done without affecting | |
7290 | * state or bandwidth calcs and this avoids the performance | |
7291 | * penalty of locking the private state object and | |
7292 | * allocating a new dc_state. | |
7293 | */ | |
7294 | if (state->async_update) | |
7295 | return 0; | |
7296 | } | |
7297 | ||
ebdd27e1 | 7298 | /* Check scaling and underscan changes*/ |
1f6010a9 | 7299 | /* TODO Removed scaling changes validation due to inability to commit |
e7b07cee HW |
7300 | * new stream into context w\o causing full reset. Need to |
7301 | * decide how to handle. | |
7302 | */ | |
c2cea706 | 7303 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
7304 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
7305 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
7306 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
e7b07cee HW |
7307 | |
7308 | /* Skip any modesets/resets */ | |
0bc9706d LSL |
7309 | if (!acrtc || drm_atomic_crtc_needs_modeset( |
7310 | drm_atomic_get_new_crtc_state(state, &acrtc->base))) | |
e7b07cee HW |
7311 | continue; |
7312 | ||
b830ebc9 | 7313 | /* Skip any thing not scale or underscan changes */ |
54d76575 | 7314 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
e7b07cee HW |
7315 | continue; |
7316 | ||
a87fa993 | 7317 | overall_update_type = UPDATE_TYPE_FULL; |
e7b07cee HW |
7318 | lock_and_validation_needed = true; |
7319 | } | |
7320 | ||
f843b308 | 7321 | ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type); |
eb3dc897 NK |
7322 | if (ret) |
7323 | goto fail; | |
a87fa993 BL |
7324 | |
7325 | if (overall_update_type < update_type) | |
7326 | overall_update_type = update_type; | |
7327 | ||
7328 | /* | |
7329 | * lock_and_validation_needed was an old way to determine if we need to set | |
7330 | * the global lock. Leaving it in to check if we broke any corner cases | |
7331 | * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED | |
7332 | * lock_and_validation_needed false = UPDATE_TYPE_FAST | |
7333 | */ | |
7334 | if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) | |
7335 | WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); | |
e7b07cee | 7336 | |
a87fa993 | 7337 | if (overall_update_type > UPDATE_TYPE_FAST) { |
eb3dc897 NK |
7338 | ret = dm_atomic_get_state(state, &dm_state); |
7339 | if (ret) | |
7340 | goto fail; | |
e7b07cee HW |
7341 | |
7342 | ret = do_aquire_global_lock(dev, state); | |
7343 | if (ret) | |
7344 | goto fail; | |
1dc90497 | 7345 | |
afcd526b | 7346 | if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { |
e7b07cee HW |
7347 | ret = -EINVAL; |
7348 | goto fail; | |
7349 | } | |
7350 | } | |
7351 | ||
7352 | /* Must be success */ | |
7353 | WARN_ON(ret); | |
7354 | return ret; | |
7355 | ||
7356 | fail: | |
7357 | if (ret == -EDEADLK) | |
01e28f9c | 7358 | DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); |
e7b07cee | 7359 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
01e28f9c | 7360 | DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); |
e7b07cee | 7361 | else |
01e28f9c | 7362 | DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); |
e7b07cee HW |
7363 | |
7364 | return ret; | |
7365 | } | |
7366 | ||
3ee6b26b AD |
7367 | static bool is_dp_capable_without_timing_msa(struct dc *dc, |
7368 | struct amdgpu_dm_connector *amdgpu_dm_connector) | |
e7b07cee HW |
7369 | { |
7370 | uint8_t dpcd_data; | |
7371 | bool capable = false; | |
7372 | ||
c84dec2f | 7373 | if (amdgpu_dm_connector->dc_link && |
e7b07cee HW |
7374 | dm_helpers_dp_read_dpcd( |
7375 | NULL, | |
c84dec2f | 7376 | amdgpu_dm_connector->dc_link, |
e7b07cee HW |
7377 | DP_DOWN_STREAM_PORT_COUNT, |
7378 | &dpcd_data, | |
7379 | sizeof(dpcd_data))) { | |
7380 | capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; | |
7381 | } | |
7382 | ||
7383 | return capable; | |
7384 | } | |
98e6436d AK |
7385 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
7386 | struct edid *edid) | |
e7b07cee HW |
7387 | { |
7388 | int i; | |
e7b07cee HW |
7389 | bool edid_check_required; |
7390 | struct detailed_timing *timing; | |
7391 | struct detailed_non_pixel *data; | |
7392 | struct detailed_data_monitor_range *range; | |
c84dec2f HW |
7393 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
7394 | to_amdgpu_dm_connector(connector); | |
bb47de73 | 7395 | struct dm_connector_state *dm_con_state = NULL; |
e7b07cee HW |
7396 | |
7397 | struct drm_device *dev = connector->dev; | |
7398 | struct amdgpu_device *adev = dev->dev_private; | |
bb47de73 | 7399 | bool freesync_capable = false; |
b830ebc9 | 7400 | |
8218d7f1 HW |
7401 | if (!connector->state) { |
7402 | DRM_ERROR("%s - Connector has no state", __func__); | |
bb47de73 | 7403 | goto update; |
8218d7f1 HW |
7404 | } |
7405 | ||
98e6436d AK |
7406 | if (!edid) { |
7407 | dm_con_state = to_dm_connector_state(connector->state); | |
7408 | ||
7409 | amdgpu_dm_connector->min_vfreq = 0; | |
7410 | amdgpu_dm_connector->max_vfreq = 0; | |
7411 | amdgpu_dm_connector->pixel_clock_mhz = 0; | |
7412 | ||
bb47de73 | 7413 | goto update; |
98e6436d AK |
7414 | } |
7415 | ||
8218d7f1 HW |
7416 | dm_con_state = to_dm_connector_state(connector->state); |
7417 | ||
e7b07cee | 7418 | edid_check_required = false; |
c84dec2f | 7419 | if (!amdgpu_dm_connector->dc_sink) { |
e7b07cee | 7420 | DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); |
bb47de73 | 7421 | goto update; |
e7b07cee HW |
7422 | } |
7423 | if (!adev->dm.freesync_module) | |
bb47de73 | 7424 | goto update; |
e7b07cee HW |
7425 | /* |
7426 | * if edid non zero restrict freesync only for dp and edp | |
7427 | */ | |
7428 | if (edid) { | |
c84dec2f HW |
7429 | if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT |
7430 | || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { | |
e7b07cee HW |
7431 | edid_check_required = is_dp_capable_without_timing_msa( |
7432 | adev->dm.dc, | |
c84dec2f | 7433 | amdgpu_dm_connector); |
e7b07cee HW |
7434 | } |
7435 | } | |
e7b07cee HW |
7436 | if (edid_check_required == true && (edid->version > 1 || |
7437 | (edid->version == 1 && edid->revision > 1))) { | |
7438 | for (i = 0; i < 4; i++) { | |
7439 | ||
7440 | timing = &edid->detailed_timings[i]; | |
7441 | data = &timing->data.other_data; | |
7442 | range = &data->data.range; | |
7443 | /* | |
7444 | * Check if monitor has continuous frequency mode | |
7445 | */ | |
7446 | if (data->type != EDID_DETAIL_MONITOR_RANGE) | |
7447 | continue; | |
7448 | /* | |
7449 | * Check for flag range limits only. If flag == 1 then | |
7450 | * no additional timing information provided. | |
7451 | * Default GTF, GTF Secondary curve and CVT are not | |
7452 | * supported | |
7453 | */ | |
7454 | if (range->flags != 1) | |
7455 | continue; | |
7456 | ||
c84dec2f HW |
7457 | amdgpu_dm_connector->min_vfreq = range->min_vfreq; |
7458 | amdgpu_dm_connector->max_vfreq = range->max_vfreq; | |
7459 | amdgpu_dm_connector->pixel_clock_mhz = | |
e7b07cee HW |
7460 | range->pixel_clock_mhz * 10; |
7461 | break; | |
7462 | } | |
7463 | ||
c84dec2f | 7464 | if (amdgpu_dm_connector->max_vfreq - |
98e6436d AK |
7465 | amdgpu_dm_connector->min_vfreq > 10) { |
7466 | ||
bb47de73 | 7467 | freesync_capable = true; |
e7b07cee HW |
7468 | } |
7469 | } | |
bb47de73 NK |
7470 | |
7471 | update: | |
7472 | if (dm_con_state) | |
7473 | dm_con_state->freesync_capable = freesync_capable; | |
7474 | ||
7475 | if (connector->vrr_capable_property) | |
7476 | drm_connector_set_vrr_capable_property(connector, | |
7477 | freesync_capable); | |
e7b07cee HW |
7478 | } |
7479 |