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drm/amd/display: Fix no display on Fiji
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
62#include "raven1/DCN/dcn_1_0_offset.h"
63#include "raven1/DCN/dcn_1_0_sh_mask.h"
64#include "vega10/soc15ip.h"
65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
a32e24b4
RL		 347#ifdef ENABLE_FBC
348#include "dal_asic_id.h"
349/* Allocate memory for FBC compressed data */
350/* TODO: Dynamic allocation */
351#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
352
7578ecda 353static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
a32e24b4
RL		 354{
355 int r;
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
357
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
362
363 if (r)
364 DRM_ERROR("DM: Failed to initialize fbc\n");
365 }
366
367}
368#endif
369
370
4562236b
HW		 371/* Init display KMS
372 *
373 * Returns 0 on success
374 */
7578ecda 375static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 376{
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
380
4562236b
HW		 381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
383
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
386
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
389
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
392 goto error;
393 }
394
395 init_data.asic_id.chip_family = adev->family;
396
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
399
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
404
405 init_data.driver = adev;
406
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
408
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
411 goto error;
412 }
413
414 init_data.cgs_device = adev->dm.cgs_device;
415
416 adev->dm.dal = NULL;
417
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
419
f1ad2f5e
HW		 420 if (amdgpu_dc_log)
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
422 else
423 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 424
a32e24b4
RL		 425#ifdef ENABLE_FBC
426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
429#endif
4562236b
HW		 430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
432
f1ad2f5e
HW		 433 if (adev->dm.dc)
434 DRM_INFO("Display Core initialized!\n");
435 else
4562236b
HW		 436 DRM_INFO("Display Core failed to initialize!\n");
437
438 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
439
440 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
441 if (!adev->dm.freesync_module) {
442 DRM_ERROR(
443 "amdgpu: failed to initialize freesync_module.\n");
444 } else
f1ad2f5e 445 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 446 adev->dm.freesync_module);
447
448 if (amdgpu_dm_initialize_drm_device(adev)) {
449 DRM_ERROR(
450 "amdgpu: failed to initialize sw for display support.\n");
451 goto error;
452 }
453
454 /* Update the actual used number of crtc */
455 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
456
457 /* TODO: Add_display_info? */
458
459 /* TODO use dynamic cursor width */
ce75805e
AG		 460 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
461 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 462
463 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
464 DRM_ERROR(
465 "amdgpu: failed to initialize sw for display support.\n");
466 goto error;
467 }
468
f1ad2f5e 469 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 470
471 return 0;
472error:
473 amdgpu_dm_fini(adev);
474
475 return -1;
476}
477
7578ecda 478static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 479{
480 amdgpu_dm_destroy_drm_device(&adev->dm);
481 /*
482 * TODO: pageflip, vlank interrupt
483 *
484 * amdgpu_dm_irq_fini(adev);
485 */
486
487 if (adev->dm.cgs_device) {
488 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
489 adev->dm.cgs_device = NULL;
490 }
491 if (adev->dm.freesync_module) {
492 mod_freesync_destroy(adev->dm.freesync_module);
493 adev->dm.freesync_module = NULL;
494 }
495 /* DC Destroy TODO: Replace destroy DAL */
21de3396 496 if (adev->dm.dc)
4562236b 497 dc_destroy(&adev->dm.dc);
4562236b
HW		 498 return;
499}
500
4562236b
HW		 501static int dm_sw_init(void *handle)
502{
503 return 0;
504}
505
506static int dm_sw_fini(void *handle)
507{
508 return 0;
509}
510
7abcf6b5 511static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 512{
c84dec2f 513 struct amdgpu_dm_connector *aconnector;
4562236b 514 struct drm_connector *connector;
7abcf6b5 515 int ret = 0;
4562236b
HW		 516
517 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
518
519 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 520 aconnector = to_amdgpu_dm_connector(connector);
7abcf6b5 521 if (aconnector->dc_link->type == dc_connection_mst_branch) {
f1ad2f5e 522 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 523 aconnector, aconnector->base.base.id);
524
525 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
526 if (ret < 0) {
527 DRM_ERROR("DM_MST: Failed to start MST\n");
528 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
529 return ret;
4562236b 530 }
7abcf6b5 531 }
4562236b
HW		 532 }
533
534 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 535 return ret;
536}
537
538static int dm_late_init(void *handle)
539{
540 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
7abcf6b5 541
33be2785 542 return detect_mst_link_for_all_connectors(dev);
4562236b
HW		 543}
544
545static void s3_handle_mst(struct drm_device *dev, bool suspend)
546{
c84dec2f 547 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 548 struct drm_connector *connector;
549
550 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
551
552 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 553 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 554 if (aconnector->dc_link->type == dc_connection_mst_branch &&
555 !aconnector->mst_port) {
556
557 if (suspend)
558 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
559 else
560 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
561 }
562 }
563
564 drm_modeset_unlock(&dev->mode_config.connection_mutex);
565}
566
567static int dm_hw_init(void *handle)
568{
569 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
570 /* Create DAL display manager */
571 amdgpu_dm_init(adev);
4562236b
HW		 572 amdgpu_dm_hpd_init(adev);
573
4562236b
HW		 574 return 0;
575}
576
577static int dm_hw_fini(void *handle)
578{
579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
580
581 amdgpu_dm_hpd_fini(adev);
582
583 amdgpu_dm_irq_fini(adev);
21de3396 584 amdgpu_dm_fini(adev);
4562236b
HW		 585 return 0;
586}
587
588static int dm_suspend(void *handle)
589{
590 struct amdgpu_device *adev = handle;
591 struct amdgpu_display_manager *dm = &adev->dm;
592 int ret = 0;
4562236b
HW		 593
594 s3_handle_mst(adev->ddev, true);
595
4562236b
HW		 596 amdgpu_dm_irq_suspend(adev);
597
0a214e2f 598 WARN_ON(adev->dm.cached_state);
a3621485
AG		 599 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
600
32f5062d 601 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 602
603 return ret;
604}
605
1daf8c63
AD		 606static struct amdgpu_dm_connector *
607amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
608 struct drm_crtc *crtc)
4562236b
HW		 609{
610 uint32_t i;
c2cea706 611 struct drm_connector_state *new_con_state;
4562236b
HW		 612 struct drm_connector *connector;
613 struct drm_crtc *crtc_from_state;
614
c2cea706
LSL		 615 for_each_new_connector_in_state(state, connector, new_con_state, i) {
616 crtc_from_state = new_con_state->crtc;
4562236b
HW		 617
618 if (crtc_from_state == crtc)
c84dec2f 619 return to_amdgpu_dm_connector(connector);
4562236b
HW		 620 }
621
622 return NULL;
623}
624
4562236b
HW		 625static int dm_resume(void *handle)
626{
627 struct amdgpu_device *adev = handle;
628 struct amdgpu_display_manager *dm = &adev->dm;
629
630 /* power on hardware */
1fb0c9cc 631 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
4562236b
HW		 632
633 return 0;
634}
635
1ecfc3da 636int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 637{
638 struct drm_device *ddev = adev->ddev;
639 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 640 struct amdgpu_dm_connector *aconnector;
4562236b 641 struct drm_connector *connector;
4562236b 642 struct drm_crtc *crtc;
c2cea706 643 struct drm_crtc_state *new_crtc_state;
a3621485
AG		 644 int ret = 0;
645 int i;
4562236b
HW		 646
647 /* program HPD filter */
648 dc_resume(dm->dc);
649
650 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
651 s3_handle_mst(ddev, false);
652
653 /*
654 * early enable HPD Rx IRQ, should be done before set mode as short
655 * pulse interrupts are used for MST
656 */
657 amdgpu_dm_irq_resume_early(adev);
658
4562236b
HW		 659 /* Do detection*/
660 list_for_each_entry(connector,
661 &ddev->mode_config.connector_list, head) {
c84dec2f 662 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 663
664 /*
665 * this is the case when traversing through already created
666 * MST connectors, should be skipped
667 */
668 if (aconnector->mst_port)
669 continue;
670
03ea364c 671 mutex_lock(&aconnector->hpd_lock);
8f38b66c 672 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4562236b
HW		 673 aconnector->dc_sink = NULL;
674 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 675 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 676 }
677
a3621485 678 /* Force mode set in atomic comit */
c2cea706
LSL		 679 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
680 new_crtc_state->active_changed = true;
4f346e65 681
a3621485 682 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 683
0a214e2f
AG		 684 drm_atomic_state_put(adev->dm.cached_state);
685 adev->dm.cached_state = NULL;
686
9faa4237 687 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 688
689 return ret;
690}
691
692static const struct amd_ip_funcs amdgpu_dm_funcs = {
693 .name = "dm",
694 .early_init = dm_early_init,
7abcf6b5 695 .late_init = dm_late_init,
4562236b
HW		 696 .sw_init = dm_sw_init,
697 .sw_fini = dm_sw_fini,
698 .hw_init = dm_hw_init,
699 .hw_fini = dm_hw_fini,
700 .suspend = dm_suspend,
701 .resume = dm_resume,
702 .is_idle = dm_is_idle,
703 .wait_for_idle = dm_wait_for_idle,
704 .check_soft_reset = dm_check_soft_reset,
705 .soft_reset = dm_soft_reset,
706 .set_clockgating_state = dm_set_clockgating_state,
707 .set_powergating_state = dm_set_powergating_state,
708};
709
710const struct amdgpu_ip_block_version dm_ip_block =
711{
712 .type = AMD_IP_BLOCK_TYPE_DCE,
713 .major = 1,
714 .minor = 0,
715 .rev = 0,
716 .funcs = &amdgpu_dm_funcs,
717};
718
ca3268c4 719
7578ecda 720static struct drm_atomic_state *
ca3268c4
HW		 721dm_atomic_state_alloc(struct drm_device *dev)
722{
723 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
724
1dc90497 725 if (!state)
ca3268c4 726 return NULL;
1dc90497
AG		 727
728 if (drm_atomic_state_init(dev, &state->base) < 0)
729 goto fail;
730
ca3268c4 731 return &state->base;
1dc90497
AG		 732
733fail:
734 kfree(state);
735 return NULL;
ca3268c4
HW		 736}
737
0a323b84
AG		 738static void
739dm_atomic_state_clear(struct drm_atomic_state *state)
740{
741 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
742
743 if (dm_state->context) {
608ac7bb 744 dc_release_state(dm_state->context);
0a323b84
AG		 745 dm_state->context = NULL;
746 }
747
748 drm_atomic_state_default_clear(state);
749}
750
751static void
752dm_atomic_state_alloc_free(struct drm_atomic_state *state)
753{
754 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
755 drm_atomic_state_default_release(state);
756 kfree(dm_state);
757}
758
b3663f70 759static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 760 .fb_create = amdgpu_user_framebuffer_create,
761 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 762 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 763 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 764 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 765 .atomic_state_clear = dm_atomic_state_clear,
766 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 767};
768
769static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
770 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 771};
772
7578ecda 773static void
3ee6b26b 774amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 775{
776 struct drm_connector *connector = &aconnector->base;
777 struct drm_device *dev = connector->dev;
b73a22d3 778 struct dc_sink *sink;
4562236b
HW		 779
780 /* MST handled by drm_mst framework */
781 if (aconnector->mst_mgr.mst_state == true)
782 return;
783
784
785 sink = aconnector->dc_link->local_sink;
786
787 /* Edid mgmt connector gets first update only in mode_valid hook and then
788 * the connector sink is set to either fake or physical sink depends on link status.
789 * don't do it here if u are during boot
790 */
791 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
792 && aconnector->dc_em_sink) {
793
ab2541b6 794 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 795 * because on resume connecotr->sink is set ti NULL
796 */
797 mutex_lock(&dev->mode_config.mutex);
798
799 if (sink) {
922aa1e1 800 if (aconnector->dc_sink) {
4562236b
HW		 801 amdgpu_dm_remove_sink_from_freesync_module(
802 connector);
922aa1e1
AG		 803 /* retain and release bellow are used for
804 * bump up refcount for sink because the link don't point
805 * to it anymore after disconnect so on next crtc to connector
806 * reshuffle by UMD we will get into unwanted dc_sink release
807 */
808 if (aconnector->dc_sink != aconnector->dc_em_sink)
809 dc_sink_release(aconnector->dc_sink);
810 }
4562236b
HW		 811 aconnector->dc_sink = sink;
812 amdgpu_dm_add_sink_to_freesync_module(
813 connector, aconnector->edid);
814 } else {
815 amdgpu_dm_remove_sink_from_freesync_module(connector);
816 if (!aconnector->dc_sink)
817 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 818 else if (aconnector->dc_sink != aconnector->dc_em_sink)
819 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 820 }
821
822 mutex_unlock(&dev->mode_config.mutex);
823 return;
824 }
825
826 /*
827 * TODO: temporary guard to look for proper fix
828 * if this sink is MST sink, we should not do anything
829 */
830 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
831 return;
832
833 if (aconnector->dc_sink == sink) {
834 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
835 * Do nothing!! */
f1ad2f5e 836 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 837 aconnector->connector_id);
838 return;
839 }
840
f1ad2f5e 841 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 842 aconnector->connector_id, aconnector->dc_sink, sink);
843
844 mutex_lock(&dev->mode_config.mutex);
845
846 /* 1. Update status of the drm connector
847 * 2. Send an event and let userspace tell us what to do */
848 if (sink) {
849 /* TODO: check if we still need the S3 mode update workaround.
850 * If yes, put it here. */
851 if (aconnector->dc_sink)
852 amdgpu_dm_remove_sink_from_freesync_module(
853 connector);
854
855 aconnector->dc_sink = sink;
900b3cb1 856 if (sink->dc_edid.length == 0) {
4562236b 857 aconnector->edid = NULL;
900b3cb1 858 } else {
4562236b
HW		 859 aconnector->edid =
860 (struct edid *) sink->dc_edid.raw_edid;
861
862
863 drm_mode_connector_update_edid_property(connector,
864 aconnector->edid);
865 }
866 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
867
868 } else {
869 amdgpu_dm_remove_sink_from_freesync_module(connector);
870 drm_mode_connector_update_edid_property(connector, NULL);
871 aconnector->num_modes = 0;
872 aconnector->dc_sink = NULL;
873 }
874
875 mutex_unlock(&dev->mode_config.mutex);
876}
877
878static void handle_hpd_irq(void *param)
879{
c84dec2f 880 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 881 struct drm_connector *connector = &aconnector->base;
882 struct drm_device *dev = connector->dev;
883
884 /* In case of failure or MST no need to update connector status or notify the OS
885 * since (for MST case) MST does this in it's own context.
886 */
887 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 888
889 if (aconnector->fake_enable)
890 aconnector->fake_enable = false;
891
8f38b66c 892 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 893 amdgpu_dm_update_connector_after_detect(aconnector);
894
895
896 drm_modeset_lock_all(dev);
897 dm_restore_drm_connector_state(dev, connector);
898 drm_modeset_unlock_all(dev);
899
900 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
901 drm_kms_helper_hotplug_event(dev);
902 }
903 mutex_unlock(&aconnector->hpd_lock);
904
905}
906
c84dec2f 907static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 908{
909 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
910 uint8_t dret;
911 bool new_irq_handled = false;
912 int dpcd_addr;
913 int dpcd_bytes_to_read;
914
915 const int max_process_count = 30;
916 int process_count = 0;
917
918 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
919
920 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
921 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
922 /* DPCD 0x200 - 0x201 for downstream IRQ */
923 dpcd_addr = DP_SINK_COUNT;
924 } else {
925 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
926 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
927 dpcd_addr = DP_SINK_COUNT_ESI;
928 }
929
930 dret = drm_dp_dpcd_read(
931 &aconnector->dm_dp_aux.aux,
932 dpcd_addr,
933 esi,
934 dpcd_bytes_to_read);
935
936 while (dret == dpcd_bytes_to_read &&
937 process_count < max_process_count) {
938 uint8_t retry;
939 dret = 0;
940
941 process_count++;
942
f1ad2f5e 943 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 944 /* handle HPD short pulse irq */
945 if (aconnector->mst_mgr.mst_state)
946 drm_dp_mst_hpd_irq(
947 &aconnector->mst_mgr,
948 esi,
949 &new_irq_handled);
4562236b
HW		 950
951 if (new_irq_handled) {
952 /* ACK at DPCD to notify down stream */
953 const int ack_dpcd_bytes_to_write =
954 dpcd_bytes_to_read - 1;
955
956 for (retry = 0; retry < 3; retry++) {
957 uint8_t wret;
958
959 wret = drm_dp_dpcd_write(
960 &aconnector->dm_dp_aux.aux,
961 dpcd_addr + 1,
962 &esi[1],
963 ack_dpcd_bytes_to_write);
964 if (wret == ack_dpcd_bytes_to_write)
965 break;
966 }
967
968 /* check if there is new irq to be handle */
969 dret = drm_dp_dpcd_read(
970 &aconnector->dm_dp_aux.aux,
971 dpcd_addr,
972 esi,
973 dpcd_bytes_to_read);
974
975 new_irq_handled = false;
d4a6e8a9 976 } else {
4562236b 977 break;
d4a6e8a9 978 }
4562236b
HW		 979 }
980
981 if (process_count == max_process_count)
f1ad2f5e 982 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 983}
984
985static void handle_hpd_rx_irq(void *param)
986{
c84dec2f 987 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 988 struct drm_connector *connector = &aconnector->base;
989 struct drm_device *dev = connector->dev;
53cbf65c 990 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 991 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
992
993 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
994 * conflict, after implement i2c helper, this mutex should be
995 * retired.
996 */
53cbf65c 997 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 998 mutex_lock(&aconnector->hpd_lock);
999
53cbf65c 1000 if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
4562236b
HW		 1001 !is_mst_root_connector) {
1002 /* Downstream Port status changed. */
53cbf65c 1003 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
4562236b
HW		 1004 amdgpu_dm_update_connector_after_detect(aconnector);
1005
1006
1007 drm_modeset_lock_all(dev);
1008 dm_restore_drm_connector_state(dev, connector);
1009 drm_modeset_unlock_all(dev);
1010
1011 drm_kms_helper_hotplug_event(dev);
1012 }
1013 }
1014 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1015 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1016 dm_handle_hpd_rx_irq(aconnector);
1017
53cbf65c 1018 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1019 mutex_unlock(&aconnector->hpd_lock);
1020}
1021
1022static void register_hpd_handlers(struct amdgpu_device *adev)
1023{
1024 struct drm_device *dev = adev->ddev;
1025 struct drm_connector *connector;
c84dec2f 1026 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1027 const struct dc_link *dc_link;
1028 struct dc_interrupt_params int_params = {0};
1029
1030 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1031 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1032
1033 list_for_each_entry(connector,
1034 &dev->mode_config.connector_list, head) {
1035
c84dec2f 1036 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1037 dc_link = aconnector->dc_link;
1038
1039 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1040 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1041 int_params.irq_source = dc_link->irq_source_hpd;
1042
1043 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1044 handle_hpd_irq,
1045 (void *) aconnector);
1046 }
1047
1048 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1049
1050 /* Also register for DP short pulse (hpd_rx). */
1051 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1052 int_params.irq_source = dc_link->irq_source_hpd_rx;
1053
1054 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1055 handle_hpd_rx_irq,
1056 (void *) aconnector);
1057 }
1058 }
1059}
1060
1061/* Register IRQ sources and initialize IRQ callbacks */
1062static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1063{
1064 struct dc *dc = adev->dm.dc;
1065 struct common_irq_params *c_irq_params;
1066 struct dc_interrupt_params int_params = {0};
1067 int r;
1068 int i;
2c8ad2d5
AD		 1069 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1070
ff5ef992
AD		 1071 if (adev->asic_type == CHIP_VEGA10 ||
1072 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1073 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1074
1075 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1076 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1077
1078 /* Actions of amdgpu_irq_add_id():
1079 * 1. Register a set() function with base driver.
1080 * Base driver will call set() function to enable/disable an
1081 * interrupt in DC hardware.
1082 * 2. Register amdgpu_dm_irq_handler().
1083 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1084 * coming from DC hardware.
1085 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1086 * for acknowledging and handling. */
1087
b57de80a 1088 /* Use VBLANK interrupt */
e9029155 1089 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1090 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1091 if (r) {
1092 DRM_ERROR("Failed to add crtc irq id!\n");
1093 return r;
1094 }
1095
1096 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1097 int_params.irq_source =
3d761e79 1098 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1099
b57de80a 1100 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1101
1102 c_irq_params->adev = adev;
1103 c_irq_params->irq_src = int_params.irq_source;
1104
1105 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1106 dm_crtc_high_irq, c_irq_params);
1107 }
1108
3d761e79 1109 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1110 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1111 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1112 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1113 if (r) {
1114 DRM_ERROR("Failed to add page flip irq id!\n");
1115 return r;
1116 }
1117
1118 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1119 int_params.irq_source =
1120 dc_interrupt_to_irq_source(dc, i, 0);
1121
1122 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1123
1124 c_irq_params->adev = adev;
1125 c_irq_params->irq_src = int_params.irq_source;
1126
1127 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1128 dm_pflip_high_irq, c_irq_params);
1129
1130 }
1131
1132 /* HPD */
2c8ad2d5
AD		 1133 r = amdgpu_irq_add_id(adev, client_id,
1134 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1135 if (r) {
1136 DRM_ERROR("Failed to add hpd irq id!\n");
1137 return r;
1138 }
1139
1140 register_hpd_handlers(adev);
1141
1142 return 0;
1143}
1144
ff5ef992
AD		 1145#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1146/* Register IRQ sources and initialize IRQ callbacks */
1147static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1148{
1149 struct dc *dc = adev->dm.dc;
1150 struct common_irq_params *c_irq_params;
1151 struct dc_interrupt_params int_params = {0};
1152 int r;
1153 int i;
1154
1155 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1156 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1157
1158 /* Actions of amdgpu_irq_add_id():
1159 * 1. Register a set() function with base driver.
1160 * Base driver will call set() function to enable/disable an
1161 * interrupt in DC hardware.
1162 * 2. Register amdgpu_dm_irq_handler().
1163 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1164 * coming from DC hardware.
1165 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1166 * for acknowledging and handling.
1167 * */
1168
1169 /* Use VSTARTUP interrupt */
1170 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1171 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1172 i++) {
1173 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1174
1175 if (r) {
1176 DRM_ERROR("Failed to add crtc irq id!\n");
1177 return r;
1178 }
1179
1180 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1181 int_params.irq_source =
1182 dc_interrupt_to_irq_source(dc, i, 0);
1183
1184 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1185
1186 c_irq_params->adev = adev;
1187 c_irq_params->irq_src = int_params.irq_source;
1188
1189 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1190 dm_crtc_high_irq, c_irq_params);
1191 }
1192
1193 /* Use GRPH_PFLIP interrupt */
1194 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1195 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1196 i++) {
1197 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1198 if (r) {
1199 DRM_ERROR("Failed to add page flip irq id!\n");
1200 return r;
1201 }
1202
1203 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1204 int_params.irq_source =
1205 dc_interrupt_to_irq_source(dc, i, 0);
1206
1207 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1208
1209 c_irq_params->adev = adev;
1210 c_irq_params->irq_src = int_params.irq_source;
1211
1212 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1213 dm_pflip_high_irq, c_irq_params);
1214
1215 }
1216
1217 /* HPD */
1218 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1219 &adev->hpd_irq);
1220 if (r) {
1221 DRM_ERROR("Failed to add hpd irq id!\n");
1222 return r;
1223 }
1224
1225 register_hpd_handlers(adev);
1226
1227 return 0;
1228}
1229#endif
1230
4562236b
HW		 1231static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1232{
1233 int r;
1234
1235 adev->mode_info.mode_config_initialized = true;
1236
4562236b 1237 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1238 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1239
1240 adev->ddev->mode_config.max_width = 16384;
1241 adev->ddev->mode_config.max_height = 16384;
1242
1243 adev->ddev->mode_config.preferred_depth = 24;
1244 adev->ddev->mode_config.prefer_shadow = 1;
1245 /* indicate support of immediate flip */
1246 adev->ddev->mode_config.async_page_flip = true;
1247
1248 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1249
1250 r = amdgpu_modeset_create_props(adev);
1251 if (r)
1252 return r;
1253
1254 return 0;
1255}
1256
1257#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1258 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1259
1260static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1261{
1262 struct amdgpu_display_manager *dm = bl_get_data(bd);
1263
1264 if (dc_link_set_backlight_level(dm->backlight_link,
1265 bd->props.brightness, 0, 0))
1266 return 0;
1267 else
1268 return 1;
1269}
1270
1271static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1272{
1273 return bd->props.brightness;
1274}
1275
1276static const struct backlight_ops amdgpu_dm_backlight_ops = {
1277 .get_brightness = amdgpu_dm_backlight_get_brightness,
1278 .update_status = amdgpu_dm_backlight_update_status,
1279};
1280
7578ecda
AD		 1281static void
1282amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1283{
1284 char bl_name[16];
1285 struct backlight_properties props = { 0 };
1286
1287 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1288 props.type = BACKLIGHT_RAW;
1289
1290 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1291 dm->adev->ddev->primary->index);
1292
1293 dm->backlight_dev = backlight_device_register(bl_name,
1294 dm->adev->ddev->dev,
1295 dm,
1296 &amdgpu_dm_backlight_ops,
1297 &props);
1298
1299 if (NULL == dm->backlight_dev)
1300 DRM_ERROR("DM: Backlight registration failed!\n");
1301 else
f1ad2f5e 1302 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1303}
1304
1305#endif
1306
1307/* In this architecture, the association
1308 * connector -> encoder -> crtc
1309 * id not really requried. The crtc and connector will hold the
1310 * display_index as an abstraction to use with DAL component
1311 *
1312 * Returns 0 on success
1313 */
7578ecda 1314static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1315{
1316 struct amdgpu_display_manager *dm = &adev->dm;
1317 uint32_t i;
c84dec2f 1318 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1319 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1320 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1321 uint32_t link_cnt;
92f3ac40 1322 unsigned long possible_crtcs;
4562236b
HW		 1323
1324 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1325 if (amdgpu_dm_mode_config_init(dm->adev)) {
1326 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1327 return -1;
4562236b
HW		 1328 }
1329
3be5262e 1330 for (i = 0; i < dm->dc->caps.max_planes; i++) {
d4e13b0d
AD		 1331 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1332 GFP_KERNEL);
1333 if (!mode_info->planes[i]) {
3be5262e 1334 DRM_ERROR("KMS: Failed to allocate plane\n");
d4e13b0d
AD		 1335 goto fail_free_planes;
1336 }
1605b3be 1337 mode_info->planes[i]->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1338
1339 /*
1340 * HACK: IGT tests expect that each plane can only have one
1341 * one possible CRTC. For now, set one CRTC for each
1342 * plane that is not an underlay, but still allow multiple
1343 * CRTCs for underlay planes.
1344 */
1345 possible_crtcs = 1 << i;
1346 if (i >= dm->dc->caps.max_streams)
1347 possible_crtcs = 0xff;
1348
1349 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d
AD		 1350 DRM_ERROR("KMS: Failed to initialize plane\n");
1351 goto fail_free_planes;
1352 }
1353 }
4562236b 1354
d4e13b0d
AD		 1355 for (i = 0; i < dm->dc->caps.max_streams; i++)
1356 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1357 DRM_ERROR("KMS: Failed to initialize crtc\n");
d4e13b0d 1358 goto fail_free_planes;
4562236b 1359 }
4562236b 1360
ab2541b6 1361 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1362
1363 /* loops over all connectors on the board */
1364 for (i = 0; i < link_cnt; i++) {
1365
1366 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1367 DRM_ERROR(
1368 "KMS: Cannot support more than %d display indexes\n",
1369 AMDGPU_DM_MAX_DISPLAY_INDEX);
1370 continue;
1371 }
1372
1373 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1374 if (!aconnector)
f2a0f5e6 1375 goto fail_free_planes;
4562236b
HW		 1376
1377 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1378 if (!aencoder)
4562236b 1379 goto fail_free_connector;
4562236b
HW		 1380
1381 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1382 DRM_ERROR("KMS: Failed to initialize encoder\n");
1383 goto fail_free_encoder;
1384 }
1385
1386 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1387 DRM_ERROR("KMS: Failed to initialize connector\n");
f2a0f5e6 1388 goto fail_free_encoder;
4562236b
HW		 1389 }
1390
8f38b66c
HW		 1391 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1392 DETECT_REASON_BOOT))
4562236b
HW		 1393 amdgpu_dm_update_connector_after_detect(aconnector);
1394 }
1395
1396 /* Software is initialized. Now we can register interrupt handlers. */
1397 switch (adev->asic_type) {
1398 case CHIP_BONAIRE:
1399 case CHIP_HAWAII:
cd4b356f
AD		 1400 case CHIP_KAVERI:
1401 case CHIP_KABINI:
1402 case CHIP_MULLINS:
4562236b
HW		 1403 case CHIP_TONGA:
1404 case CHIP_FIJI:
1405 case CHIP_CARRIZO:
1406 case CHIP_STONEY:
1407 case CHIP_POLARIS11:
1408 case CHIP_POLARIS10:
b264d345 1409 case CHIP_POLARIS12:
2c8ad2d5 1410 case CHIP_VEGA10:
4562236b
HW		 1411 if (dce110_register_irq_handlers(dm->adev)) {
1412 DRM_ERROR("DM: Failed to initialize IRQ\n");
d4e13b0d 1413 goto fail_free_encoder;
4562236b
HW		 1414 }
1415 break;
ff5ef992
AD		 1416#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1417 case CHIP_RAVEN:
1418 if (dcn10_register_irq_handlers(dm->adev)) {
1419 DRM_ERROR("DM: Failed to initialize IRQ\n");
1420 goto fail_free_encoder;
1421 }
79c24086
BL		 1422 /*
1423 * Temporary disable until pplib/smu interaction is implemented
1424 */
1425 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1426 break;
1427#endif
4562236b
HW		 1428 default:
1429 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
d4e13b0d 1430 goto fail_free_encoder;
4562236b
HW		 1431 }
1432
1433 drm_mode_config_reset(dm->ddev);
1434
1435 return 0;
1436fail_free_encoder:
1437 kfree(aencoder);
1438fail_free_connector:
1439 kfree(aconnector);
d4e13b0d 1440fail_free_planes:
3be5262e 1441 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1442 kfree(mode_info->planes[i]);
4562236b
HW		 1443 return -1;
1444}
1445
7578ecda 1446static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1447{
1448 drm_mode_config_cleanup(dm->ddev);
1449 return;
1450}
1451
1452/******************************************************************************
1453 * amdgpu_display_funcs functions
1454 *****************************************************************************/
1455
1456/**
1457 * dm_bandwidth_update - program display watermarks
1458 *
1459 * @adev: amdgpu_device pointer
1460 *
1461 * Calculate and program the display watermarks and line buffer allocation.
1462 */
1463static void dm_bandwidth_update(struct amdgpu_device *adev)
1464{
49c07a99 1465 /* TODO: implement later */
4562236b
HW		 1466}
1467
1468static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1469 u8 level)
1470{
1471 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1472}
1473
1474static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1475{
1476 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1477 return 0;
1478}
1479
4562236b
HW		 1480static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1481 struct drm_file *filp)
1482{
1483 struct mod_freesync_params freesync_params;
ab2541b6 1484 uint8_t num_streams;
4562236b 1485 uint8_t i;
4562236b
HW		 1486
1487 struct amdgpu_device *adev = dev->dev_private;
1488 int r = 0;
1489
1490 /* Get freesync enable flag from DRM */
1491
ab2541b6 1492 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1493
ab2541b6 1494 for (i = 0; i < num_streams; i++) {
0971c40e 1495 struct dc_stream_state *stream;
ab2541b6 1496 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1497
1498 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1499 &stream, 1, &freesync_params);
4562236b
HW		 1500 }
1501
1502 return r;
1503}
1504
39cc5be2 1505static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1506 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1507 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1508 .vblank_wait = NULL,
1509 .backlight_set_level =
1510 dm_set_backlight_level,/* called unconditionally */
1511 .backlight_get_level =
1512 dm_get_backlight_level,/* called unconditionally */
1513 .hpd_sense = NULL,/* called unconditionally */
1514 .hpd_set_polarity = NULL, /* called unconditionally */
1515 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1516 .page_flip_get_scanoutpos =
1517 dm_crtc_get_scanoutpos,/* called unconditionally */
1518 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1519 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1520 .notify_freesync = amdgpu_notify_freesync,
1521
1522};
1523
1524#if defined(CONFIG_DEBUG_KERNEL_DC)
1525
3ee6b26b
AD		 1526static ssize_t s3_debug_store(struct device *device,
1527 struct device_attribute *attr,
1528 const char *buf,
1529 size_t count)
4562236b
HW		 1530{
1531 int ret;
1532 int s3_state;
1533 struct pci_dev *pdev = to_pci_dev(device);
1534 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1535 struct amdgpu_device *adev = drm_dev->dev_private;
1536
1537 ret = kstrtoint(buf, 0, &s3_state);
1538
1539 if (ret == 0) {
1540 if (s3_state) {
1541 dm_resume(adev);
1542 amdgpu_dm_display_resume(adev);
1543 drm_kms_helper_hotplug_event(adev->ddev);
1544 } else
1545 dm_suspend(adev);
1546 }
1547
1548 return ret == 0 ? count : 0;
1549}
1550
1551DEVICE_ATTR_WO(s3_debug);
1552
1553#endif
1554
1555static int dm_early_init(void *handle)
1556{
1557 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1558
d7ec53d9 1559 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1560 amdgpu_dm_set_irq_funcs(adev);
1561
1562 switch (adev->asic_type) {
1563 case CHIP_BONAIRE:
1564 case CHIP_HAWAII:
1565 adev->mode_info.num_crtc = 6;
1566 adev->mode_info.num_hpd = 6;
1567 adev->mode_info.num_dig = 6;
3be5262e 1568 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1569 break;
cd4b356f
AD		 1570 case CHIP_KAVERI:
1571 adev->mode_info.num_crtc = 4;
1572 adev->mode_info.num_hpd = 6;
1573 adev->mode_info.num_dig = 7;
1574 adev->mode_info.plane_type = dm_plane_type_default;
1575 break;
1576 case CHIP_KABINI:
1577 case CHIP_MULLINS:
1578 adev->mode_info.num_crtc = 2;
1579 adev->mode_info.num_hpd = 6;
1580 adev->mode_info.num_dig = 6;
1581 adev->mode_info.plane_type = dm_plane_type_default;
1582 break;
4562236b
HW		 1583 case CHIP_FIJI:
1584 case CHIP_TONGA:
1585 adev->mode_info.num_crtc = 6;
1586 adev->mode_info.num_hpd = 6;
1587 adev->mode_info.num_dig = 7;
3be5262e 1588 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1589 break;
1590 case CHIP_CARRIZO:
1591 adev->mode_info.num_crtc = 3;
1592 adev->mode_info.num_hpd = 6;
1593 adev->mode_info.num_dig = 9;
3be5262e 1594 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1595 break;
1596 case CHIP_STONEY:
1597 adev->mode_info.num_crtc = 2;
1598 adev->mode_info.num_hpd = 6;
1599 adev->mode_info.num_dig = 9;
3be5262e 1600 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1601 break;
1602 case CHIP_POLARIS11:
b264d345 1603 case CHIP_POLARIS12:
4562236b
HW		 1604 adev->mode_info.num_crtc = 5;
1605 adev->mode_info.num_hpd = 5;
1606 adev->mode_info.num_dig = 5;
3be5262e 1607 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1608 break;
1609 case CHIP_POLARIS10:
1610 adev->mode_info.num_crtc = 6;
1611 adev->mode_info.num_hpd = 6;
1612 adev->mode_info.num_dig = 6;
3be5262e 1613 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1614 break;
2c8ad2d5
AD		 1615 case CHIP_VEGA10:
1616 adev->mode_info.num_crtc = 6;
1617 adev->mode_info.num_hpd = 6;
1618 adev->mode_info.num_dig = 6;
3be5262e 1619 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1620 break;
ff5ef992
AD		 1621#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1622 case CHIP_RAVEN:
1623 adev->mode_info.num_crtc = 4;
1624 adev->mode_info.num_hpd = 4;
1625 adev->mode_info.num_dig = 4;
3be5262e 1626 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1627 break;
1628#endif
4562236b
HW		 1629 default:
1630 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1631 return -EINVAL;
1632 }
1633
39cc5be2
AD		 1634 if (adev->mode_info.funcs == NULL)
1635 adev->mode_info.funcs = &dm_display_funcs;
1636
4562236b
HW		 1637 /* Note: Do NOT change adev->audio_endpt_rreg and
1638 * adev->audio_endpt_wreg because they are initialised in
1639 * amdgpu_device_init() */
1640#if defined(CONFIG_DEBUG_KERNEL_DC)
1641 device_create_file(
1642 adev->ddev->dev,
1643 &dev_attr_s3_debug);
1644#endif
1645
1646 return 0;
1647}
1648
e7b07cee
HW		 1649struct dm_connector_state {
1650 struct drm_connector_state base;
1651
1652 enum amdgpu_rmx_type scaling;
1653 uint8_t underscan_vborder;
1654 uint8_t underscan_hborder;
1655 bool underscan_enable;
1656};
1657
1658#define to_dm_connector_state(x)\
1659 container_of((x), struct dm_connector_state, base)
1660
9b690ef3 1661static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1662 struct dc_stream_state *new_stream,
1663 struct dc_stream_state *old_stream)
9b690ef3 1664{
e7b07cee
HW		 1665 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1666 return false;
1667
1668 if (!crtc_state->enable)
1669 return false;
1670
1671 return crtc_state->active;
1672}
1673
1674static bool modereset_required(struct drm_crtc_state *crtc_state)
1675{
1676 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1677 return false;
1678
1679 return !crtc_state->enable || !crtc_state->active;
1680}
1681
7578ecda 1682static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1683{
1684 drm_encoder_cleanup(encoder);
1685 kfree(encoder);
1686}
1687
1688static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1689 .destroy = amdgpu_dm_encoder_destroy,
1690};
1691
3ee6b26b
AD		 1692static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1693 struct dc_plane_state *plane_state)
e7b07cee 1694{
3be5262e
HW		 1695 plane_state->src_rect.x = state->src_x >> 16;
1696 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1697 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1698 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1699
3be5262e 1700 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1701 return false;
1702
3be5262e
HW		 1703 plane_state->src_rect.height = state->src_h >> 16;
1704 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1705 return false;
1706
3be5262e
HW		 1707 plane_state->dst_rect.x = state->crtc_x;
1708 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1709
1710 if (state->crtc_w == 0)
1711 return false;
1712
3be5262e 1713 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1714
1715 if (state->crtc_h == 0)
1716 return false;
1717
3be5262e 1718 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1719
3be5262e 1720 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1721
1722 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1723 case DRM_MODE_ROTATE_0:
3be5262e 1724 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1725 break;
1726 case DRM_MODE_ROTATE_90:
3be5262e 1727 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1728 break;
1729 case DRM_MODE_ROTATE_180:
3be5262e 1730 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1731 break;
1732 case DRM_MODE_ROTATE_270:
3be5262e 1733 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1734 break;
1735 default:
3be5262e 1736 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1737 break;
1738 }
1739
4562236b
HW		 1740 return true;
1741}
3ee6b26b
AD		 1742static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1743 uint64_t *tiling_flags,
1744 uint64_t *fb_location)
e7b07cee
HW		 1745{
1746 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1747 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1748
e7b07cee 1749 if (unlikely(r)) {
9bbc3031
JZ		 1750 // Don't show error msg. when return -ERESTARTSYS
1751 if (r != -ERESTARTSYS)
1752 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1753 return r;
1754 }
1755
1756 if (fb_location)
1757 *fb_location = amdgpu_bo_gpu_offset(rbo);
1758
1759 if (tiling_flags)
1760 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1761
1762 amdgpu_bo_unreserve(rbo);
1763
1764 return r;
1765}
1766
3ee6b26b
AD		 1767static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1768 struct dc_plane_state *plane_state,
1769 const struct amdgpu_framebuffer *amdgpu_fb,
1770 bool addReq)
e7b07cee
HW		 1771{
1772 uint64_t tiling_flags;
1773 uint64_t fb_location = 0;
1774 unsigned int awidth;
1775 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1776 int ret = 0;
1777 struct drm_format_name_buf format_name;
1778
1779 ret = get_fb_info(
1780 amdgpu_fb,
1781 &tiling_flags,
1782 addReq == true ? &fb_location:NULL);
1783
1784 if (ret)
1785 return ret;
1786
1787 switch (fb->format->format) {
1788 case DRM_FORMAT_C8:
3be5262e 1789 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1790 break;
1791 case DRM_FORMAT_RGB565:
3be5262e 1792 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1793 break;
1794 case DRM_FORMAT_XRGB8888:
1795 case DRM_FORMAT_ARGB8888:
3be5262e 1796 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1797 break;
1798 case DRM_FORMAT_XRGB2101010:
1799 case DRM_FORMAT_ARGB2101010:
3be5262e 1800 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1801 break;
1802 case DRM_FORMAT_XBGR2101010:
1803 case DRM_FORMAT_ABGR2101010:
3be5262e 1804 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1805 break;
1806 case DRM_FORMAT_NV21:
3be5262e 1807 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1808 break;
1809 case DRM_FORMAT_NV12:
3be5262e 1810 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1811 break;
1812 default:
1813 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1814 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1815 return -EINVAL;
1816 }
1817
3be5262e
HW		 1818 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1819 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1820 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1821 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1822 plane_state->plane_size.grph.surface_size.x = 0;
1823 plane_state->plane_size.grph.surface_size.y = 0;
1824 plane_state->plane_size.grph.surface_size.width = fb->width;
1825 plane_state->plane_size.grph.surface_size.height = fb->height;
1826 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1827 fb->pitches[0] / fb->format->cpp[0];
1828 /* TODO: unhardcode */
3be5262e 1829 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1830
1831 } else {
1832 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1833 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1834 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1835 = lower_32_bits(fb_location);
3be5262e 1836 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 1837 = lower_32_bits(fb_location) +
1838 (awidth * fb->height);
3be5262e
HW		 1839 plane_state->plane_size.video.luma_size.x = 0;
1840 plane_state->plane_size.video.luma_size.y = 0;
1841 plane_state->plane_size.video.luma_size.width = awidth;
1842 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1843 /* TODO: unhardcode */
3be5262e 1844 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1845
3be5262e
HW		 1846 plane_state->plane_size.video.chroma_size.x = 0;
1847 plane_state->plane_size.video.chroma_size.y = 0;
1848 plane_state->plane_size.video.chroma_size.width = awidth;
1849 plane_state->plane_size.video.chroma_size.height = fb->height;
1850 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1851
1852 /* TODO: unhardcode */
3be5262e 1853 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1854 }
1855
3be5262e 1856 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1857
b830ebc9
HW		 1858 /* Fill GFX8 params */
1859 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1860 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1861
1862 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1863 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1864 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1865 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1866 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1867
1868 /* XXX fix me for VI */
3be5262e
HW		 1869 plane_state->tiling_info.gfx8.num_banks = num_banks;
1870 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1871 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1872 plane_state->tiling_info.gfx8.tile_split = tile_split;
1873 plane_state->tiling_info.gfx8.bank_width = bankw;
1874 plane_state->tiling_info.gfx8.bank_height = bankh;
1875 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1876 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1877 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1878 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1879 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1880 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1881 }
1882
3be5262e 1883 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1884 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1885
1886 if (adev->asic_type == CHIP_VEGA10 ||
1887 adev->asic_type == CHIP_RAVEN) {
1888 /* Fill GFX9 params */
3be5262e 1889 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1890 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1891 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1892 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1893 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1894 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1895 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1896 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1897 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1898 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1899 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1900 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1901 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1902 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1903 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1904 }
1905
3be5262e
HW		 1906 plane_state->visible = true;
1907 plane_state->scaling_quality.h_taps_c = 0;
1908 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1909
3be5262e
HW		 1910 /* is this needed? is plane_state zeroed at allocation? */
1911 plane_state->scaling_quality.h_taps = 0;
1912 plane_state->scaling_quality.v_taps = 0;
1913 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1914
1915 return ret;
1916
1917}
1918
3ee6b26b
AD		 1919static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1920 struct dc_plane_state *plane_state)
e7b07cee
HW		 1921{
1922 int i;
1923 struct dc_gamma *gamma;
d66cf5f5
AK		 1924 struct drm_color_lut *lut =
1925 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1926
1927 gamma = dc_create_gamma();
1928
1929 if (gamma == NULL) {
1930 WARN_ON(1);
1931 return;
1932 }
1933
7483bed4
HW		 1934 gamma->type = GAMMA_RGB_256;
1935 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1936 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1937 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1938 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1939 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1940 }
1941
3be5262e 1942 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1943}
1944
3ee6b26b
AD		 1945static int fill_plane_attributes(struct amdgpu_device *adev,
1946 struct dc_plane_state *dc_plane_state,
1947 struct drm_plane_state *plane_state,
1948 struct drm_crtc_state *crtc_state,
1949 bool addrReq)
e7b07cee
HW		 1950{
1951 const struct amdgpu_framebuffer *amdgpu_fb =
1952 to_amdgpu_framebuffer(plane_state->fb);
1953 const struct drm_crtc *crtc = plane_state->crtc;
1954 struct dc_transfer_func *input_tf;
1955 int ret = 0;
1956
3be5262e 1957 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1958 return -EINVAL;
1959
1960 ret = fill_plane_attributes_from_fb(
1961 crtc->dev->dev_private,
3be5262e 1962 dc_plane_state,
e7b07cee
HW		 1963 amdgpu_fb,
1964 addrReq);
1965
1966 if (ret)
1967 return ret;
1968
1969 input_tf = dc_create_transfer_func();
1970
1971 if (input_tf == NULL)
1972 return -ENOMEM;
1973
1974 input_tf->type = TF_TYPE_PREDEFINED;
1975 input_tf->tf = TRANSFER_FUNCTION_SRGB;
1976
3be5262e 1977 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 1978
1979 /* In case of gamma set, update gamma value */
1980 if (crtc_state->gamma_lut)
3be5262e 1981 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 1982
1983 return ret;
1984}
1985
1986/*****************************************************************************/
1987
3ee6b26b
AD		 1988static void update_stream_scaling_settings(const struct drm_display_mode *mode,
1989 const struct dm_connector_state *dm_state,
1990 struct dc_stream_state *stream)
e7b07cee
HW		 1991{
1992 enum amdgpu_rmx_type rmx_type;
1993
1994 struct rect src = { 0 }; /* viewport in composition space*/
1995 struct rect dst = { 0 }; /* stream addressable area */
1996
1997 /* no mode. nothing to be done */
1998 if (!mode)
1999 return;
2000
2001 /* Full screen scaling by default */
2002 src.width = mode->hdisplay;
2003 src.height = mode->vdisplay;
2004 dst.width = stream->timing.h_addressable;
2005 dst.height = stream->timing.v_addressable;
2006
2007 rmx_type = dm_state->scaling;
2008 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2009 if (src.width * dst.height <
2010 src.height * dst.width) {
2011 /* height needs less upscaling/more downscaling */
2012 dst.width = src.width *
2013 dst.height / src.height;
2014 } else {
2015 /* width needs less upscaling/more downscaling */
2016 dst.height = src.height *
2017 dst.width / src.width;
2018 }
2019 } else if (rmx_type == RMX_CENTER) {
2020 dst = src;
2021 }
2022
2023 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2024 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2025
2026 if (dm_state->underscan_enable) {
2027 dst.x += dm_state->underscan_hborder / 2;
2028 dst.y += dm_state->underscan_vborder / 2;
2029 dst.width -= dm_state->underscan_hborder;
2030 dst.height -= dm_state->underscan_vborder;
2031 }
2032
2033 stream->src = src;
2034 stream->dst = dst;
2035
f1ad2f5e 2036 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2037 dst.x, dst.y, dst.width, dst.height);
2038
2039}
2040
3ee6b26b
AD		 2041static enum dc_color_depth
2042convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2043{
2044 uint32_t bpc = connector->display_info.bpc;
2045
2046 /* Limited color depth to 8bit
b830ebc9
HW		 2047 * TODO: Still need to handle deep color
2048 */
e7b07cee
HW		 2049 if (bpc > 8)
2050 bpc = 8;
2051
2052 switch (bpc) {
2053 case 0:
2054 /* Temporary Work around, DRM don't parse color depth for
2055 * EDID revision before 1.4
2056 * TODO: Fix edid parsing
2057 */
2058 return COLOR_DEPTH_888;
2059 case 6:
2060 return COLOR_DEPTH_666;
2061 case 8:
2062 return COLOR_DEPTH_888;
2063 case 10:
2064 return COLOR_DEPTH_101010;
2065 case 12:
2066 return COLOR_DEPTH_121212;
2067 case 14:
2068 return COLOR_DEPTH_141414;
2069 case 16:
2070 return COLOR_DEPTH_161616;
2071 default:
2072 return COLOR_DEPTH_UNDEFINED;
2073 }
2074}
2075
3ee6b26b
AD		 2076static enum dc_aspect_ratio
2077get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2078{
2079 int32_t width = mode_in->crtc_hdisplay * 9;
2080 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2081
e7b07cee
HW		 2082 if ((width - height) < 10 && (width - height) > -10)
2083 return ASPECT_RATIO_16_9;
2084 else
2085 return ASPECT_RATIO_4_3;
2086}
2087
3ee6b26b
AD		 2088static enum dc_color_space
2089get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2090{
2091 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2092
2093 switch (dc_crtc_timing->pixel_encoding) {
2094 case PIXEL_ENCODING_YCBCR422:
2095 case PIXEL_ENCODING_YCBCR444:
2096 case PIXEL_ENCODING_YCBCR420:
2097 {
2098 /*
2099 * 27030khz is the separation point between HDTV and SDTV
2100 * according to HDMI spec, we use YCbCr709 and YCbCr601
2101 * respectively
2102 */
2103 if (dc_crtc_timing->pix_clk_khz > 27030) {
2104 if (dc_crtc_timing->flags.Y_ONLY)
2105 color_space =
2106 COLOR_SPACE_YCBCR709_LIMITED;
2107 else
2108 color_space = COLOR_SPACE_YCBCR709;
2109 } else {
2110 if (dc_crtc_timing->flags.Y_ONLY)
2111 color_space =
2112 COLOR_SPACE_YCBCR601_LIMITED;
2113 else
2114 color_space = COLOR_SPACE_YCBCR601;
2115 }
2116
2117 }
2118 break;
2119 case PIXEL_ENCODING_RGB:
2120 color_space = COLOR_SPACE_SRGB;
2121 break;
2122
2123 default:
2124 WARN_ON(1);
2125 break;
2126 }
2127
2128 return color_space;
2129}
2130
2131/*****************************************************************************/
2132
3ee6b26b
AD		 2133static void
2134fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2135 const struct drm_display_mode *mode_in,
2136 const struct drm_connector *connector)
e7b07cee
HW		 2137{
2138 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2139
e7b07cee
HW		 2140 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2141
2142 timing_out->h_border_left = 0;
2143 timing_out->h_border_right = 0;
2144 timing_out->v_border_top = 0;
2145 timing_out->v_border_bottom = 0;
2146 /* TODO: un-hardcode */
2147
2148 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2149 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2150 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2151 else
2152 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2153
2154 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2155 timing_out->display_color_depth = convert_color_depth_from_display_info(
2156 connector);
2157 timing_out->scan_type = SCANNING_TYPE_NODATA;
2158 timing_out->hdmi_vic = 0;
2159 timing_out->vic = drm_match_cea_mode(mode_in);
2160
2161 timing_out->h_addressable = mode_in->crtc_hdisplay;
2162 timing_out->h_total = mode_in->crtc_htotal;
2163 timing_out->h_sync_width =
2164 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2165 timing_out->h_front_porch =
2166 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2167 timing_out->v_total = mode_in->crtc_vtotal;
2168 timing_out->v_addressable = mode_in->crtc_vdisplay;
2169 timing_out->v_front_porch =
2170 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2171 timing_out->v_sync_width =
2172 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2173 timing_out->pix_clk_khz = mode_in->crtc_clock;
2174 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2175 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2176 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2177 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2178 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2179
2180 stream->output_color_space = get_output_color_space(timing_out);
2181
2182 {
2183 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2184
e7b07cee
HW		 2185 tf->type = TF_TYPE_PREDEFINED;
2186 tf->tf = TRANSFER_FUNCTION_SRGB;
2187 stream->out_transfer_func = tf;
2188 }
2189}
2190
3ee6b26b
AD		 2191static void fill_audio_info(struct audio_info *audio_info,
2192 const struct drm_connector *drm_connector,
2193 const struct dc_sink *dc_sink)
e7b07cee
HW		 2194{
2195 int i = 0;
2196 int cea_revision = 0;
2197 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2198
2199 audio_info->manufacture_id = edid_caps->manufacturer_id;
2200 audio_info->product_id = edid_caps->product_id;
2201
2202 cea_revision = drm_connector->display_info.cea_rev;
2203
d2b2562c
TSD		 2204 strncpy(audio_info->display_name,
2205 edid_caps->display_name,
2206 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2207
b830ebc9 2208 if (cea_revision >= 3) {
e7b07cee
HW		 2209 audio_info->mode_count = edid_caps->audio_mode_count;
2210
2211 for (i = 0; i < audio_info->mode_count; ++i) {
2212 audio_info->modes[i].format_code =
2213 (enum audio_format_code)
2214 (edid_caps->audio_modes[i].format_code);
2215 audio_info->modes[i].channel_count =
2216 edid_caps->audio_modes[i].channel_count;
2217 audio_info->modes[i].sample_rates.all =
2218 edid_caps->audio_modes[i].sample_rate;
2219 audio_info->modes[i].sample_size =
2220 edid_caps->audio_modes[i].sample_size;
2221 }
2222 }
2223
2224 audio_info->flags.all = edid_caps->speaker_flags;
2225
2226 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2227 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2228 audio_info->video_latency = drm_connector->video_latency[0];
2229 audio_info->audio_latency = drm_connector->audio_latency[0];
2230 }
2231
2232 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2233
2234}
2235
3ee6b26b
AD		 2236static void
2237copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2238 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2239{
2240 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2241 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2242 dst_mode->crtc_clock = src_mode->crtc_clock;
2243 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2244 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2245 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2246 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2247 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2248 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2249 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2250 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2251 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2252 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2253 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2254}
2255
3ee6b26b
AD		 2256static void
2257decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2258 const struct drm_display_mode *native_mode,
2259 bool scale_enabled)
e7b07cee
HW		 2260{
2261 if (scale_enabled) {
2262 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2263 } else if (native_mode->clock == drm_mode->clock &&
2264 native_mode->htotal == drm_mode->htotal &&
2265 native_mode->vtotal == drm_mode->vtotal) {
2266 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2267 } else {
2268 /* no scaling nor amdgpu inserted, no need to patch */
2269 }
2270}
2271
2e0ac3d6
HW		 2272static void create_fake_sink(struct amdgpu_dm_connector *aconnector)
2273{
2274 struct dc_sink *sink = NULL;
2275 struct dc_sink_init_data sink_init_data = { 0 };
2276
2277 sink_init_data.link = aconnector->dc_link;
2278 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2279
2280 sink = dc_sink_create(&sink_init_data);
2281 if (!sink)
2282 DRM_ERROR("Failed to create sink!\n");
2283
2284 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2285 aconnector->fake_enable = true;
2286
2287 aconnector->dc_sink = sink;
2288 aconnector->dc_link->local_sink = sink;
2289}
2290
3ee6b26b
AD		 2291static struct dc_stream_state *
2292create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2293 const struct drm_display_mode *drm_mode,
2294 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2295{
2296 struct drm_display_mode *preferred_mode = NULL;
2297 const struct drm_connector *drm_connector;
0971c40e 2298 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2299 struct drm_display_mode mode = *drm_mode;
2300 bool native_mode_found = false;
2301
b830ebc9 2302 if (aconnector == NULL) {
e7b07cee
HW		 2303 DRM_ERROR("aconnector is NULL!\n");
2304 goto drm_connector_null;
2305 }
2306
b830ebc9 2307 if (dm_state == NULL) {
e7b07cee
HW		 2308 DRM_ERROR("dm_state is NULL!\n");
2309 goto dm_state_null;
2310 }
4562236b 2311
e7b07cee 2312 drm_connector = &aconnector->base;
2e0ac3d6 2313
f4ac176e
JZ		 2314 if (!aconnector->dc_sink) {
2315 /*
2316 * Exclude MST from creating fake_sink
2317 * TODO: need to enable MST into fake_sink feature
2318 */
2319 if (aconnector->mst_port)
2320 goto stream_create_fail;
2321
2e0ac3d6 2322 create_fake_sink(aconnector);
f4ac176e 2323 }
2e0ac3d6 2324
e7b07cee 2325 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2326
b830ebc9 2327 if (stream == NULL) {
e7b07cee
HW		 2328 DRM_ERROR("Failed to create stream for sink!\n");
2329 goto stream_create_fail;
2330 }
2331
2332 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2333 /* Search for preferred mode */
2334 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2335 native_mode_found = true;
2336 break;
2337 }
2338 }
2339 if (!native_mode_found)
2340 preferred_mode = list_first_entry_or_null(
2341 &aconnector->base.modes,
2342 struct drm_display_mode,
2343 head);
2344
b830ebc9 2345 if (preferred_mode == NULL) {
e7b07cee
HW		 2346 /* This may not be an error, the use case is when we we have no
2347 * usermode calls to reset and set mode upon hotplug. In this
2348 * case, we call set mode ourselves to restore the previous mode
2349 * and the modelist may not be filled in in time.
2350 */
f1ad2f5e 2351 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2352 } else {
2353 decide_crtc_timing_for_drm_display_mode(
2354 &mode, preferred_mode,
2355 dm_state->scaling != RMX_OFF);
2356 }
2357
2358 fill_stream_properties_from_drm_display_mode(stream,
2359 &mode, &aconnector->base);
2360 update_stream_scaling_settings(&mode, dm_state, stream);
2361
2362 fill_audio_info(
2363 &stream->audio_info,
2364 drm_connector,
2365 aconnector->dc_sink);
2366
2367stream_create_fail:
2368dm_state_null:
2369drm_connector_null:
2370 return stream;
2371}
2372
7578ecda 2373static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2374{
2375 drm_crtc_cleanup(crtc);
2376 kfree(crtc);
2377}
2378
2379static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2380 struct drm_crtc_state *state)
e7b07cee
HW		 2381{
2382 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2383
2384 /* TODO Destroy dc_stream objects are stream object is flattened */
2385 if (cur->stream)
2386 dc_stream_release(cur->stream);
2387
2388
2389 __drm_atomic_helper_crtc_destroy_state(state);
2390
2391
2392 kfree(state);
2393}
2394
2395static void dm_crtc_reset_state(struct drm_crtc *crtc)
2396{
2397 struct dm_crtc_state *state;
2398
2399 if (crtc->state)
2400 dm_crtc_destroy_state(crtc, crtc->state);
2401
2402 state = kzalloc(sizeof(*state), GFP_KERNEL);
2403 if (WARN_ON(!state))
2404 return;
2405
2406 crtc->state = &state->base;
2407 crtc->state->crtc = crtc;
2408
2409}
2410
2411static struct drm_crtc_state *
2412dm_crtc_duplicate_state(struct drm_crtc *crtc)
2413{
2414 struct dm_crtc_state *state, *cur;
2415
2416 cur = to_dm_crtc_state(crtc->state);
2417
2418 if (WARN_ON(!crtc->state))
2419 return NULL;
2420
2004f45e 2421 state = kzalloc(sizeof(*state), GFP_KERNEL);
e7b07cee
HW		 2422
2423 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2424
2425 if (cur->stream) {
2426 state->stream = cur->stream;
2427 dc_stream_retain(state->stream);
2428 }
2429
2430 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2431
2432 return &state->base;
2433}
2434
2435/* Implemented only the options currently availible for the driver */
2436static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2437 .reset = dm_crtc_reset_state,
2438 .destroy = amdgpu_dm_crtc_destroy,
2439 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2440 .set_config = drm_atomic_helper_set_config,
2441 .page_flip = drm_atomic_helper_page_flip,
2442 .atomic_duplicate_state = dm_crtc_duplicate_state,
2443 .atomic_destroy_state = dm_crtc_destroy_state,
2444};
2445
2446static enum drm_connector_status
2447amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2448{
2449 bool connected;
c84dec2f 2450 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2451
2452 /* Notes:
2453 * 1. This interface is NOT called in context of HPD irq.
2454 * 2. This interface *is called* in context of user-mode ioctl. Which
2455 * makes it a bad place for *any* MST-related activit. */
2456
8580d60b
HW		 2457 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2458 !aconnector->fake_enable)
e7b07cee
HW		 2459 connected = (aconnector->dc_sink != NULL);
2460 else
2461 connected = (aconnector->base.force == DRM_FORCE_ON);
2462
2463 return (connected ? connector_status_connected :
2464 connector_status_disconnected);
2465}
2466
3ee6b26b
AD		 2467int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2468 struct drm_connector_state *connector_state,
2469 struct drm_property *property,
2470 uint64_t val)
e7b07cee
HW		 2471{
2472 struct drm_device *dev = connector->dev;
2473 struct amdgpu_device *adev = dev->dev_private;
2474 struct dm_connector_state *dm_old_state =
2475 to_dm_connector_state(connector->state);
2476 struct dm_connector_state *dm_new_state =
2477 to_dm_connector_state(connector_state);
2478
2479 int ret = -EINVAL;
2480
2481 if (property == dev->mode_config.scaling_mode_property) {
2482 enum amdgpu_rmx_type rmx_type;
2483
2484 switch (val) {
2485 case DRM_MODE_SCALE_CENTER:
2486 rmx_type = RMX_CENTER;
2487 break;
2488 case DRM_MODE_SCALE_ASPECT:
2489 rmx_type = RMX_ASPECT;
2490 break;
2491 case DRM_MODE_SCALE_FULLSCREEN:
2492 rmx_type = RMX_FULL;
2493 break;
2494 case DRM_MODE_SCALE_NONE:
2495 default:
2496 rmx_type = RMX_OFF;
2497 break;
2498 }
2499
2500 if (dm_old_state->scaling == rmx_type)
2501 return 0;
2502
2503 dm_new_state->scaling = rmx_type;
2504 ret = 0;
2505 } else if (property == adev->mode_info.underscan_hborder_property) {
2506 dm_new_state->underscan_hborder = val;
2507 ret = 0;
2508 } else if (property == adev->mode_info.underscan_vborder_property) {
2509 dm_new_state->underscan_vborder = val;
2510 ret = 0;
2511 } else if (property == adev->mode_info.underscan_property) {
2512 dm_new_state->underscan_enable = val;
2513 ret = 0;
2514 }
2515
2516 return ret;
2517}
2518
3ee6b26b
AD		 2519int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2520 const struct drm_connector_state *state,
2521 struct drm_property *property,
2522 uint64_t *val)
e7b07cee
HW		 2523{
2524 struct drm_device *dev = connector->dev;
2525 struct amdgpu_device *adev = dev->dev_private;
2526 struct dm_connector_state *dm_state =
2527 to_dm_connector_state(state);
2528 int ret = -EINVAL;
2529
2530 if (property == dev->mode_config.scaling_mode_property) {
2531 switch (dm_state->scaling) {
2532 case RMX_CENTER:
2533 *val = DRM_MODE_SCALE_CENTER;
2534 break;
2535 case RMX_ASPECT:
2536 *val = DRM_MODE_SCALE_ASPECT;
2537 break;
2538 case RMX_FULL:
2539 *val = DRM_MODE_SCALE_FULLSCREEN;
2540 break;
2541 case RMX_OFF:
2542 default:
2543 *val = DRM_MODE_SCALE_NONE;
2544 break;
2545 }
2546 ret = 0;
2547 } else if (property == adev->mode_info.underscan_hborder_property) {
2548 *val = dm_state->underscan_hborder;
2549 ret = 0;
2550 } else if (property == adev->mode_info.underscan_vborder_property) {
2551 *val = dm_state->underscan_vborder;
2552 ret = 0;
2553 } else if (property == adev->mode_info.underscan_property) {
2554 *val = dm_state->underscan_enable;
2555 ret = 0;
2556 }
2557 return ret;
2558}
2559
7578ecda 2560static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2561{
c84dec2f 2562 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2563 const struct dc_link *link = aconnector->dc_link;
2564 struct amdgpu_device *adev = connector->dev->dev_private;
2565 struct amdgpu_display_manager *dm = &adev->dm;
2566#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2567 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2568
2569 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2570 amdgpu_dm_register_backlight_device(dm);
2571
2572 if (dm->backlight_dev) {
2573 backlight_device_unregister(dm->backlight_dev);
2574 dm->backlight_dev = NULL;
2575 }
2576
2577 }
2578#endif
2579 drm_connector_unregister(connector);
2580 drm_connector_cleanup(connector);
2581 kfree(connector);
2582}
2583
2584void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2585{
2586 struct dm_connector_state *state =
2587 to_dm_connector_state(connector->state);
2588
2589 kfree(state);
2590
2591 state = kzalloc(sizeof(*state), GFP_KERNEL);
2592
2593 if (state) {
2594 state->scaling = RMX_OFF;
2595 state->underscan_enable = false;
2596 state->underscan_hborder = 0;
2597 state->underscan_vborder = 0;
2598
2599 connector->state = &state->base;
2600 connector->state->connector = connector;
2601 }
2602}
2603
3ee6b26b
AD		 2604struct drm_connector_state *
2605amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2606{
2607 struct dm_connector_state *state =
2608 to_dm_connector_state(connector->state);
2609
2610 struct dm_connector_state *new_state =
2611 kmemdup(state, sizeof(*state), GFP_KERNEL);
2612
2613 if (new_state) {
2614 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2615 &new_state->base);
e7b07cee
HW		 2616 return &new_state->base;
2617 }
2618
2619 return NULL;
2620}
2621
2622static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2623 .reset = amdgpu_dm_connector_funcs_reset,
2624 .detect = amdgpu_dm_connector_detect,
2625 .fill_modes = drm_helper_probe_single_connector_modes,
2626 .destroy = amdgpu_dm_connector_destroy,
2627 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2628 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2629 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2630 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2631};
2632
2633static struct drm_encoder *best_encoder(struct drm_connector *connector)
2634{
2635 int enc_id = connector->encoder_ids[0];
2636 struct drm_mode_object *obj;
2637 struct drm_encoder *encoder;
2638
f1ad2f5e 2639 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2640
2641 /* pick the encoder ids */
2642 if (enc_id) {
bd21a37d 2643 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2644 if (!obj) {
2645 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2646 return NULL;
2647 }
2648 encoder = obj_to_encoder(obj);
2649 return encoder;
2650 }
2651 DRM_ERROR("No encoder id\n");
2652 return NULL;
2653}
2654
2655static int get_modes(struct drm_connector *connector)
2656{
2657 return amdgpu_dm_connector_get_modes(connector);
2658}
2659
c84dec2f 2660static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2661{
2662 struct dc_sink_init_data init_params = {
2663 .link = aconnector->dc_link,
2664 .sink_signal = SIGNAL_TYPE_VIRTUAL
2665 };
2666 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2667
2668 if (!aconnector->base.edid_blob_ptr ||
2669 !aconnector->base.edid_blob_ptr->data) {
2670 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2671 aconnector->base.name);
2672
2673 aconnector->base.force = DRM_FORCE_OFF;
2674 aconnector->base.override_edid = false;
2675 return;
2676 }
2677
2678 aconnector->edid = edid;
2679
2680 aconnector->dc_em_sink = dc_link_add_remote_sink(
2681 aconnector->dc_link,
2682 (uint8_t *)edid,
2683 (edid->extensions + 1) * EDID_LENGTH,
2684 &init_params);
2685
a68d90e7 2686 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2687 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2688 aconnector->dc_link->local_sink :
2689 aconnector->dc_em_sink;
2690}
2691
c84dec2f 2692static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2693{
2694 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2695
2696 /* In case of headless boot with force on for DP managed connector
2697 * Those settings have to be != 0 to get initial modeset
2698 */
2699 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2700 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2701 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2702 }
2703
2704
2705 aconnector->base.override_edid = true;
2706 create_eml_sink(aconnector);
2707}
2708
3ee6b26b
AD		 2709int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2710 struct drm_display_mode *mode)
e7b07cee
HW		 2711{
2712 int result = MODE_ERROR;
2713 struct dc_sink *dc_sink;
2714 struct amdgpu_device *adev = connector->dev->dev_private;
2715 /* TODO: Unhardcode stream count */
0971c40e 2716 struct dc_stream_state *stream;
c84dec2f 2717 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2718
2719 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2720 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2721 return result;
2722
2723 /* Only run this the first time mode_valid is called to initilialize
2724 * EDID mgmt
2725 */
2726 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2727 !aconnector->dc_em_sink)
2728 handle_edid_mgmt(aconnector);
2729
c84dec2f 2730 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2731
b830ebc9 2732 if (dc_sink == NULL) {
e7b07cee
HW		 2733 DRM_ERROR("dc_sink is NULL!\n");
2734 goto fail;
2735 }
2736
2737 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2738 if (stream == NULL) {
e7b07cee
HW		 2739 DRM_ERROR("Failed to create stream for sink!\n");
2740 goto fail;
2741 }
2742
2743 drm_mode_set_crtcinfo(mode, 0);
2744 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2745
2746 stream->src.width = mode->hdisplay;
2747 stream->src.height = mode->vdisplay;
2748 stream->dst = stream->src;
2749
62c933f9 2750 if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
e7b07cee
HW		 2751 result = MODE_OK;
2752
2753 dc_stream_release(stream);
2754
2755fail:
2756 /* TODO: error handling*/
2757 return result;
2758}
2759
2760static const struct drm_connector_helper_funcs
2761amdgpu_dm_connector_helper_funcs = {
2762 /*
b830ebc9
HW		 2763 * If hotplug a second bigger display in FB Con mode, bigger resolution
2764 * modes will be filtered by drm_mode_validate_size(), and those modes
2765 * is missing after user start lightdm. So we need to renew modes list.
2766 * in get_modes call back, not just return the modes count
2767 */
e7b07cee
HW		 2768 .get_modes = get_modes,
2769 .mode_valid = amdgpu_dm_connector_mode_valid,
2770 .best_encoder = best_encoder
2771};
2772
2773static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2774{
2775}
2776
3ee6b26b
AD		 2777static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2778 struct drm_crtc_state *state)
e7b07cee
HW		 2779{
2780 struct amdgpu_device *adev = crtc->dev->dev_private;
2781 struct dc *dc = adev->dm.dc;
2782 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2783 int ret = -EINVAL;
2784
9b690ef3
BL		 2785 if (unlikely(!dm_crtc_state->stream &&
2786 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2787 WARN_ON(1);
2788 return ret;
2789 }
2790
2791 /* In some use cases, like reset, no stream is attached */
2792 if (!dm_crtc_state->stream)
2793 return 0;
2794
62c933f9 2795 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2796 return 0;
2797
2798 return ret;
2799}
2800
3ee6b26b
AD		 2801static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2802 const struct drm_display_mode *mode,
2803 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2804{
2805 return true;
2806}
2807
2808static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2809 .disable = dm_crtc_helper_disable,
2810 .atomic_check = dm_crtc_helper_atomic_check,
2811 .mode_fixup = dm_crtc_helper_mode_fixup
2812};
2813
2814static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2815{
2816
2817}
2818
3ee6b26b
AD		 2819static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2820 struct drm_crtc_state *crtc_state,
2821 struct drm_connector_state *conn_state)
e7b07cee
HW		 2822{
2823 return 0;
2824}
2825
2826const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2827 .disable = dm_encoder_helper_disable,
2828 .atomic_check = dm_encoder_helper_atomic_check
2829};
2830
2831static void dm_drm_plane_reset(struct drm_plane *plane)
2832{
2833 struct dm_plane_state *amdgpu_state = NULL;
2834
2835 if (plane->state)
2836 plane->funcs->atomic_destroy_state(plane, plane->state);
2837
2838 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d
TSD		 2839 WARN_ON(amdgpu_state == NULL);
2840
e7b07cee
HW		 2841 if (amdgpu_state) {
2842 plane->state = &amdgpu_state->base;
2843 plane->state->plane = plane;
2844 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 2845 }
e7b07cee
HW		 2846}
2847
2848static struct drm_plane_state *
2849dm_drm_plane_duplicate_state(struct drm_plane *plane)
2850{
2851 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2852
2853 old_dm_plane_state = to_dm_plane_state(plane->state);
2854 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2855 if (!dm_plane_state)
2856 return NULL;
2857
2858 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2859
3be5262e
HW		 2860 if (old_dm_plane_state->dc_state) {
2861 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2862 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2863 }
2864
2865 return &dm_plane_state->base;
2866}
2867
2868void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2869 struct drm_plane_state *state)
e7b07cee
HW		 2870{
2871 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2872
3be5262e
HW		 2873 if (dm_plane_state->dc_state)
2874 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2875
0627bbd3 2876 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2877}
2878
2879static const struct drm_plane_funcs dm_plane_funcs = {
2880 .update_plane = drm_atomic_helper_update_plane,
2881 .disable_plane = drm_atomic_helper_disable_plane,
2882 .destroy = drm_plane_cleanup,
2883 .reset = dm_drm_plane_reset,
2884 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2885 .atomic_destroy_state = dm_drm_plane_destroy_state,
2886};
2887
3ee6b26b
AD		 2888static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2889 struct drm_plane_state *new_state)
e7b07cee
HW		 2890{
2891 struct amdgpu_framebuffer *afb;
2892 struct drm_gem_object *obj;
2893 struct amdgpu_bo *rbo;
2894 int r;
2895 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2896 unsigned int awidth;
2897
2898 dm_plane_state_old = to_dm_plane_state(plane->state);
2899 dm_plane_state_new = to_dm_plane_state(new_state);
2900
2901 if (!new_state->fb) {
f1ad2f5e 2902 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2903 return 0;
2904 }
2905
2906 afb = to_amdgpu_framebuffer(new_state->fb);
2907
2908 obj = afb->obj;
2909 rbo = gem_to_amdgpu_bo(obj);
2910 r = amdgpu_bo_reserve(rbo, false);
2911 if (unlikely(r != 0))
2912 return r;
2913
2914 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2915
2916
2917 amdgpu_bo_unreserve(rbo);
2918
2919 if (unlikely(r != 0)) {
2920 DRM_ERROR("Failed to pin framebuffer\n");
2921 return r;
2922 }
2923
2924 amdgpu_bo_ref(rbo);
2925
3be5262e
HW		 2926 if (dm_plane_state_new->dc_state &&
2927 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2928 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2929
3be5262e
HW		 2930 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2931 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2932 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2933 } else {
2934 awidth = ALIGN(new_state->fb->width, 64);
3be5262e 2935 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2936 = lower_32_bits(afb->address);
3be5262e 2937 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 2938 = lower_32_bits(afb->address) +
2939 (awidth * new_state->fb->height);
2940 }
2941 }
2942
2943 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2944 * prepare and cleanup in drm_atomic_helper_prepare_planes
2945 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2946 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2947 * code touching fram buffers should be avoided for DC.
2948 */
2949 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2950 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2951
2952 acrtc->cursor_bo = obj;
2953 }
2954 return 0;
2955}
2956
3ee6b26b
AD		 2957static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
2958 struct drm_plane_state *old_state)
e7b07cee
HW		 2959{
2960 struct amdgpu_bo *rbo;
2961 struct amdgpu_framebuffer *afb;
2962 int r;
2963
2964 if (!old_state->fb)
2965 return;
2966
2967 afb = to_amdgpu_framebuffer(old_state->fb);
2968 rbo = gem_to_amdgpu_bo(afb->obj);
2969 r = amdgpu_bo_reserve(rbo, false);
2970 if (unlikely(r)) {
2971 DRM_ERROR("failed to reserve rbo before unpin\n");
2972 return;
b830ebc9
HW		 2973 }
2974
2975 amdgpu_bo_unpin(rbo);
2976 amdgpu_bo_unreserve(rbo);
2977 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 2978}
2979
7578ecda
AD		 2980static int dm_plane_atomic_check(struct drm_plane *plane,
2981 struct drm_plane_state *state)
cbd19488
AG		 2982{
2983 struct amdgpu_device *adev = plane->dev->dev_private;
2984 struct dc *dc = adev->dm.dc;
2985 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2986
3be5262e 2987 if (!dm_plane_state->dc_state)
9a3329b1 2988 return 0;
cbd19488 2989
62c933f9 2990 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 2991 return 0;
2992
2993 return -EINVAL;
2994}
2995
e7b07cee
HW		 2996static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
2997 .prepare_fb = dm_plane_helper_prepare_fb,
2998 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 2999 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3000};
3001
3002/*
3003 * TODO: these are currently initialized to rgb formats only.
3004 * For future use cases we should either initialize them dynamically based on
3005 * plane capabilities, or initialize this array to all formats, so internal drm
3006 * check will succeed, and let DC to implement proper check
3007 */
d90371b0 3008static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3009 DRM_FORMAT_RGB888,
3010 DRM_FORMAT_XRGB8888,
3011 DRM_FORMAT_ARGB8888,
3012 DRM_FORMAT_RGBA8888,
3013 DRM_FORMAT_XRGB2101010,
3014 DRM_FORMAT_XBGR2101010,
3015 DRM_FORMAT_ARGB2101010,
3016 DRM_FORMAT_ABGR2101010,
3017};
3018
99d1abf8 3019static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3020 DRM_FORMAT_NV12,
3021 DRM_FORMAT_NV21,
3022};
3023
3024static const u32 cursor_formats[] = {
3025 DRM_FORMAT_ARGB8888
3026};
3027
7578ecda
AD		 3028static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3029 struct amdgpu_plane *aplane,
3030 unsigned long possible_crtcs)
e7b07cee
HW		 3031{
3032 int res = -EPERM;
3033
3034 switch (aplane->base.type) {
3035 case DRM_PLANE_TYPE_PRIMARY:
3036 aplane->base.format_default = true;
3037
3038 res = drm_universal_plane_init(
3039 dm->adev->ddev,
3040 &aplane->base,
3041 possible_crtcs,
3042 &dm_plane_funcs,
3043 rgb_formats,
3044 ARRAY_SIZE(rgb_formats),
3045 NULL, aplane->base.type, NULL);
3046 break;
3047 case DRM_PLANE_TYPE_OVERLAY:
3048 res = drm_universal_plane_init(
3049 dm->adev->ddev,
3050 &aplane->base,
3051 possible_crtcs,
3052 &dm_plane_funcs,
3053 yuv_formats,
3054 ARRAY_SIZE(yuv_formats),
3055 NULL, aplane->base.type, NULL);
3056 break;
3057 case DRM_PLANE_TYPE_CURSOR:
3058 res = drm_universal_plane_init(
3059 dm->adev->ddev,
3060 &aplane->base,
3061 possible_crtcs,
3062 &dm_plane_funcs,
3063 cursor_formats,
3064 ARRAY_SIZE(cursor_formats),
3065 NULL, aplane->base.type, NULL);
3066 break;
3067 }
3068
3069 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3070
3071 return res;
3072}
3073
7578ecda
AD		 3074static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3075 struct drm_plane *plane,
3076 uint32_t crtc_index)
e7b07cee
HW		 3077{
3078 struct amdgpu_crtc *acrtc = NULL;
3079 struct amdgpu_plane *cursor_plane;
3080
3081 int res = -ENOMEM;
3082
3083 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3084 if (!cursor_plane)
3085 goto fail;
3086
3087 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3088 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3089
3090 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3091 if (!acrtc)
3092 goto fail;
3093
3094 res = drm_crtc_init_with_planes(
3095 dm->ddev,
3096 &acrtc->base,
3097 plane,
3098 &cursor_plane->base,
3099 &amdgpu_dm_crtc_funcs, NULL);
3100
3101 if (res)
3102 goto fail;
3103
3104 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3105
3106 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3107 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3108
3109 acrtc->crtc_id = crtc_index;
3110 acrtc->base.enabled = false;
3111
3112 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3113 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3114
3115 return 0;
3116
3117fail:
b830ebc9
HW		 3118 kfree(acrtc);
3119 kfree(cursor_plane);
e7b07cee
HW		 3120 return res;
3121}
3122
3123
3124static int to_drm_connector_type(enum signal_type st)
3125{
3126 switch (st) {
3127 case SIGNAL_TYPE_HDMI_TYPE_A:
3128 return DRM_MODE_CONNECTOR_HDMIA;
3129 case SIGNAL_TYPE_EDP:
3130 return DRM_MODE_CONNECTOR_eDP;
3131 case SIGNAL_TYPE_RGB:
3132 return DRM_MODE_CONNECTOR_VGA;
3133 case SIGNAL_TYPE_DISPLAY_PORT:
3134 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3135 return DRM_MODE_CONNECTOR_DisplayPort;
3136 case SIGNAL_TYPE_DVI_DUAL_LINK:
3137 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3138 return DRM_MODE_CONNECTOR_DVID;
3139 case SIGNAL_TYPE_VIRTUAL:
3140 return DRM_MODE_CONNECTOR_VIRTUAL;
3141
3142 default:
3143 return DRM_MODE_CONNECTOR_Unknown;
3144 }
3145}
3146
3147static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3148{
3149 const struct drm_connector_helper_funcs *helper =
3150 connector->helper_private;
3151 struct drm_encoder *encoder;
3152 struct amdgpu_encoder *amdgpu_encoder;
3153
3154 encoder = helper->best_encoder(connector);
3155
3156 if (encoder == NULL)
3157 return;
3158
3159 amdgpu_encoder = to_amdgpu_encoder(encoder);
3160
3161 amdgpu_encoder->native_mode.clock = 0;
3162
3163 if (!list_empty(&connector->probed_modes)) {
3164 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3165
e7b07cee 3166 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3167 &connector->probed_modes,
3168 head) {
3169 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3170 amdgpu_encoder->native_mode = *preferred_mode;
3171
e7b07cee
HW		 3172 break;
3173 }
3174
3175 }
3176}
3177
3ee6b26b
AD		 3178static struct drm_display_mode *
3179amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3180 char *name,
3181 int hdisplay, int vdisplay)
e7b07cee
HW		 3182{
3183 struct drm_device *dev = encoder->dev;
3184 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3185 struct drm_display_mode *mode = NULL;
3186 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3187
3188 mode = drm_mode_duplicate(dev, native_mode);
3189
b830ebc9 3190 if (mode == NULL)
e7b07cee
HW		 3191 return NULL;
3192
3193 mode->hdisplay = hdisplay;
3194 mode->vdisplay = vdisplay;
3195 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3196 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3197
3198 return mode;
3199
3200}
3201
3202static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3203 struct drm_connector *connector)
e7b07cee
HW		 3204{
3205 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3206 struct drm_display_mode *mode = NULL;
3207 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3208 struct amdgpu_dm_connector *amdgpu_dm_connector =
3209 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3210 int i;
3211 int n;
3212 struct mode_size {
3213 char name[DRM_DISPLAY_MODE_LEN];
3214 int w;
3215 int h;
b830ebc9 3216 } common_modes[] = {
e7b07cee
HW		 3217 { "640x480", 640, 480},
3218 { "800x600", 800, 600},
3219 { "1024x768", 1024, 768},
3220 { "1280x720", 1280, 720},
3221 { "1280x800", 1280, 800},
3222 {"1280x1024", 1280, 1024},
3223 { "1440x900", 1440, 900},
3224 {"1680x1050", 1680, 1050},
3225 {"1600x1200", 1600, 1200},
3226 {"1920x1080", 1920, 1080},
3227 {"1920x1200", 1920, 1200}
3228 };
3229
b830ebc9 3230 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3231
3232 for (i = 0; i < n; i++) {
3233 struct drm_display_mode *curmode = NULL;
3234 bool mode_existed = false;
3235
3236 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3237 common_modes[i].h > native_mode->vdisplay ||
3238 (common_modes[i].w == native_mode->hdisplay &&
3239 common_modes[i].h == native_mode->vdisplay))
3240 continue;
e7b07cee
HW		 3241
3242 list_for_each_entry(curmode, &connector->probed_modes, head) {
3243 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3244 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3245 mode_existed = true;
3246 break;
3247 }
3248 }
3249
3250 if (mode_existed)
3251 continue;
3252
3253 mode = amdgpu_dm_create_common_mode(encoder,
3254 common_modes[i].name, common_modes[i].w,
3255 common_modes[i].h);
3256 drm_mode_probed_add(connector, mode);
c84dec2f 3257 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3258 }
3259}
3260
3ee6b26b
AD		 3261static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3262 struct edid *edid)
e7b07cee 3263{
c84dec2f
HW		 3264 struct amdgpu_dm_connector *amdgpu_dm_connector =
3265 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3266
3267 if (edid) {
3268 /* empty probed_modes */
3269 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3270 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3271 drm_add_edid_modes(connector, edid);
3272
3273 drm_edid_to_eld(connector, edid);
3274
3275 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3276 } else {
c84dec2f 3277 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3278 }
e7b07cee
HW		 3279}
3280
7578ecda 3281static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3282{
3283 const struct drm_connector_helper_funcs *helper =
3284 connector->helper_private;
c84dec2f
HW		 3285 struct amdgpu_dm_connector *amdgpu_dm_connector =
3286 to_amdgpu_dm_connector(connector);
e7b07cee 3287 struct drm_encoder *encoder;
c84dec2f 3288 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3289
3290 encoder = helper->best_encoder(connector);
3291
3292 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3293 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3294 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3295}
3296
3ee6b26b
AD		 3297void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3298 struct amdgpu_dm_connector *aconnector,
3299 int connector_type,
3300 struct dc_link *link,
3301 int link_index)
e7b07cee
HW		 3302{
3303 struct amdgpu_device *adev = dm->ddev->dev_private;
3304
3305 aconnector->connector_id = link_index;
3306 aconnector->dc_link = link;
3307 aconnector->base.interlace_allowed = false;
3308 aconnector->base.doublescan_allowed = false;
3309 aconnector->base.stereo_allowed = false;
3310 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3311 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3312
3313 mutex_init(&aconnector->hpd_lock);
3314
b830ebc9
HW		 3315 /* configure support HPD hot plug connector_>polled default value is 0
3316 * which means HPD hot plug not supported
3317 */
e7b07cee
HW		 3318 switch (connector_type) {
3319 case DRM_MODE_CONNECTOR_HDMIA:
3320 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3321 break;
3322 case DRM_MODE_CONNECTOR_DisplayPort:
3323 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3324 break;
3325 case DRM_MODE_CONNECTOR_DVID:
3326 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3327 break;
3328 default:
3329 break;
3330 }
3331
3332 drm_object_attach_property(&aconnector->base.base,
3333 dm->ddev->mode_config.scaling_mode_property,
3334 DRM_MODE_SCALE_NONE);
3335
3336 drm_object_attach_property(&aconnector->base.base,
3337 adev->mode_info.underscan_property,
3338 UNDERSCAN_OFF);
3339 drm_object_attach_property(&aconnector->base.base,
3340 adev->mode_info.underscan_hborder_property,
3341 0);
3342 drm_object_attach_property(&aconnector->base.base,
3343 adev->mode_info.underscan_vborder_property,
3344 0);
3345
3346}
3347
7578ecda
AD		 3348static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3349 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3350{
3351 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3352 struct ddc_service *ddc_service = i2c->ddc_service;
3353 struct i2c_command cmd;
3354 int i;
3355 int result = -EIO;
3356
b830ebc9 3357 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3358
3359 if (!cmd.payloads)
3360 return result;
3361
3362 cmd.number_of_payloads = num;
3363 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3364 cmd.speed = 100;
3365
3366 for (i = 0; i < num; i++) {
3367 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3368 cmd.payloads[i].address = msgs[i].addr;
3369 cmd.payloads[i].length = msgs[i].len;
3370 cmd.payloads[i].data = msgs[i].buf;
3371 }
3372
3373 if (dal_i2caux_submit_i2c_command(
3374 ddc_service->ctx->i2caux,
3375 ddc_service->ddc_pin,
3376 &cmd))
3377 result = num;
3378
3379 kfree(cmd.payloads);
3380 return result;
3381}
3382
7578ecda 3383static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3384{
3385 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3386}
3387
3388static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3389 .master_xfer = amdgpu_dm_i2c_xfer,
3390 .functionality = amdgpu_dm_i2c_func,
3391};
3392
3ee6b26b
AD		 3393static struct amdgpu_i2c_adapter *
3394create_i2c(struct ddc_service *ddc_service,
3395 int link_index,
3396 int *res)
e7b07cee
HW		 3397{
3398 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3399 struct amdgpu_i2c_adapter *i2c;
3400
b830ebc9 3401 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
e7b07cee
HW		 3402 i2c->base.owner = THIS_MODULE;
3403 i2c->base.class = I2C_CLASS_DDC;
3404 i2c->base.dev.parent = &adev->pdev->dev;
3405 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3406 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3407 i2c_set_adapdata(&i2c->base, i2c);
3408 i2c->ddc_service = ddc_service;
3409
3410 return i2c;
3411}
3412
3413/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3414 * dc_link which will be represented by this aconnector.
3415 */
7578ecda
AD		 3416static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3417 struct amdgpu_dm_connector *aconnector,
3418 uint32_t link_index,
3419 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3420{
3421 int res = 0;
3422 int connector_type;
3423 struct dc *dc = dm->dc;
3424 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3425 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3426
3427 link->priv = aconnector;
e7b07cee 3428
f1ad2f5e 3429 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3430
3431 i2c = create_i2c(link->ddc, link->link_index, &res);
3432 aconnector->i2c = i2c;
3433 res = i2c_add_adapter(&i2c->base);
3434
3435 if (res) {
3436 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3437 goto out_free;
3438 }
3439
3440 connector_type = to_drm_connector_type(link->connector_signal);
3441
3442 res = drm_connector_init(
3443 dm->ddev,
3444 &aconnector->base,
3445 &amdgpu_dm_connector_funcs,
3446 connector_type);
3447
3448 if (res) {
3449 DRM_ERROR("connector_init failed\n");
3450 aconnector->connector_id = -1;
3451 goto out_free;
3452 }
3453
3454 drm_connector_helper_add(
3455 &aconnector->base,
3456 &amdgpu_dm_connector_helper_funcs);
3457
3458 amdgpu_dm_connector_init_helper(
3459 dm,
3460 aconnector,
3461 connector_type,
3462 link,
3463 link_index);
3464
3465 drm_mode_connector_attach_encoder(
3466 &aconnector->base, &aencoder->base);
3467
3468 drm_connector_register(&aconnector->base);
3469
3470 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3471 || connector_type == DRM_MODE_CONNECTOR_eDP)
3472 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3473
3474#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3475 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3476
3477 /* NOTE: this currently will create backlight device even if a panel
3478 * is not connected to the eDP/LVDS connector.
3479 *
3480 * This is less than ideal but we don't have sink information at this
3481 * stage since detection happens after. We can't do detection earlier
3482 * since MST detection needs connectors to be created first.
3483 */
3484 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3485 /* Event if registration failed, we should continue with
3486 * DM initialization because not having a backlight control
b830ebc9
HW		 3487 * is better then a black screen.
3488 */
e7b07cee
HW		 3489 amdgpu_dm_register_backlight_device(dm);
3490
3491 if (dm->backlight_dev)
3492 dm->backlight_link = link;
3493 }
3494#endif
3495
3496out_free:
3497 if (res) {
3498 kfree(i2c);
3499 aconnector->i2c = NULL;
3500 }
3501 return res;
3502}
3503
3504int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3505{
3506 switch (adev->mode_info.num_crtc) {
3507 case 1:
3508 return 0x1;
3509 case 2:
3510 return 0x3;
3511 case 3:
3512 return 0x7;
3513 case 4:
3514 return 0xf;
3515 case 5:
3516 return 0x1f;
3517 case 6:
3518 default:
3519 return 0x3f;
3520 }
3521}
3522
7578ecda
AD		 3523static int amdgpu_dm_encoder_init(struct drm_device *dev,
3524 struct amdgpu_encoder *aencoder,
3525 uint32_t link_index)
e7b07cee
HW		 3526{
3527 struct amdgpu_device *adev = dev->dev_private;
3528
3529 int res = drm_encoder_init(dev,
3530 &aencoder->base,
3531 &amdgpu_dm_encoder_funcs,
3532 DRM_MODE_ENCODER_TMDS,
3533 NULL);
3534
3535 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3536
3537 if (!res)
3538 aencoder->encoder_id = link_index;
3539 else
3540 aencoder->encoder_id = -1;
3541
3542 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3543
3544 return res;
3545}
3546
3ee6b26b
AD		 3547static void manage_dm_interrupts(struct amdgpu_device *adev,
3548 struct amdgpu_crtc *acrtc,
3549 bool enable)
e7b07cee
HW		 3550{
3551 /*
3552 * this is not correct translation but will work as soon as VBLANK
3553 * constant is the same as PFLIP
3554 */
3555 int irq_type =
3556 amdgpu_crtc_idx_to_irq_type(
3557 adev,
3558 acrtc->crtc_id);
3559
3560 if (enable) {
3561 drm_crtc_vblank_on(&acrtc->base);
3562 amdgpu_irq_get(
3563 adev,
3564 &adev->pageflip_irq,
3565 irq_type);
3566 } else {
3567
3568 amdgpu_irq_put(
3569 adev,
3570 &adev->pageflip_irq,
3571 irq_type);
3572 drm_crtc_vblank_off(&acrtc->base);
3573 }
3574}
3575
3ee6b26b
AD		 3576static bool
3577is_scaling_state_different(const struct dm_connector_state *dm_state,
3578 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3579{
3580 if (dm_state->scaling != old_dm_state->scaling)
3581 return true;
3582 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3583 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3584 return true;
3585 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3586 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3587 return true;
b830ebc9
HW		 3588 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3589 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3590 return true;
e7b07cee
HW		 3591 return false;
3592}
3593
3ee6b26b
AD		 3594static void remove_stream(struct amdgpu_device *adev,
3595 struct amdgpu_crtc *acrtc,
3596 struct dc_stream_state *stream)
e7b07cee
HW		 3597{
3598 /* this is the update mode case */
3599 if (adev->dm.freesync_module)
3600 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3601
3602 acrtc->otg_inst = -1;
3603 acrtc->enabled = false;
3604}
3605
7578ecda
AD		 3606static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3607 struct dc_cursor_position *position)
2a8f6ccb
HW		 3608{
3609 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3610 int x, y;
3611 int xorigin = 0, yorigin = 0;
3612
3613 if (!crtc || !plane->state->fb) {
3614 position->enable = false;
3615 position->x = 0;
3616 position->y = 0;
3617 return 0;
3618 }
3619
3620 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3621 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3622 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3623 __func__,
3624 plane->state->crtc_w,
3625 plane->state->crtc_h);
3626 return -EINVAL;
3627 }
3628
3629 x = plane->state->crtc_x;
3630 y = plane->state->crtc_y;
3631 /* avivo cursor are offset into the total surface */
3632 x += crtc->primary->state->src_x >> 16;
3633 y += crtc->primary->state->src_y >> 16;
3634 if (x < 0) {
3635 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3636 x = 0;
3637 }
3638 if (y < 0) {
3639 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3640 y = 0;
3641 }
3642 position->enable = true;
3643 position->x = x;
3644 position->y = y;
3645 position->x_hotspot = xorigin;
3646 position->y_hotspot = yorigin;
3647
3648 return 0;
3649}
3650
3ee6b26b
AD		 3651static void handle_cursor_update(struct drm_plane *plane,
3652 struct drm_plane_state *old_plane_state)
e7b07cee 3653{
2a8f6ccb
HW		 3654 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3655 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3656 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3657 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3658 uint64_t address = afb ? afb->address : 0;
3659 struct dc_cursor_position position;
3660 struct dc_cursor_attributes attributes;
3661 int ret;
3662
e7b07cee
HW		 3663 if (!plane->state->fb && !old_plane_state->fb)
3664 return;
3665
f1ad2f5e 3666 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3667 __func__,
3668 amdgpu_crtc->crtc_id,
3669 plane->state->crtc_w,
3670 plane->state->crtc_h);
2a8f6ccb
HW		 3671
3672 ret = get_cursor_position(plane, crtc, &position);
3673 if (ret)
3674 return;
3675
3676 if (!position.enable) {
3677 /* turn off cursor */
3678 if (crtc_state && crtc_state->stream)
3679 dc_stream_set_cursor_position(crtc_state->stream,
3680 &position);
3681 return;
e7b07cee 3682 }
e7b07cee 3683
2a8f6ccb
HW		 3684 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3685 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3686
3687 attributes.address.high_part = upper_32_bits(address);
3688 attributes.address.low_part = lower_32_bits(address);
3689 attributes.width = plane->state->crtc_w;
3690 attributes.height = plane->state->crtc_h;
3691 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3692 attributes.rotation_angle = 0;
3693 attributes.attribute_flags.value = 0;
3694
3695 attributes.pitch = attributes.width;
3696
886daac9
JZ		 3697 if (crtc_state->stream) {
3698 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3699 &attributes))
3700 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3701
2a8f6ccb
HW		 3702 if (!dc_stream_set_cursor_position(crtc_state->stream,
3703 &position))
3704 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3705 }
2a8f6ccb 3706}
e7b07cee
HW		 3707
3708static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3709{
3710
3711 assert_spin_locked(&acrtc->base.dev->event_lock);
3712 WARN_ON(acrtc->event);
3713
3714 acrtc->event = acrtc->base.state->event;
3715
3716 /* Set the flip status */
3717 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3718
3719 /* Mark this event as consumed */
3720 acrtc->base.state->event = NULL;
3721
3722 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3723 acrtc->crtc_id);
3724}
3725
3726/*
3727 * Executes flip
3728 *
3729 * Waits on all BO's fences and for proper vblank count
3730 */
3ee6b26b
AD		 3731static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3732 struct drm_framebuffer *fb,
bc6828e0
BL		 3733 uint32_t target,
3734 struct dc_state *state)
e7b07cee
HW		 3735{
3736 unsigned long flags;
3737 uint32_t target_vblank;
3738 int r, vpos, hpos;
3739 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3740 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3741 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3742 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3743 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3744 struct dc_flip_addrs addr = { {0} };
3be5262e 3745 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3746 struct dc_surface_update surface_updates[1] = { {0} };
3747 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3748
3749
3750 /* Prepare wait for target vblank early - before the fence-waits */
3751 target_vblank = target - drm_crtc_vblank_count(crtc) +
3752 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3753
b830ebc9 3754 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3755 * explicitly on fences instead
3756 * and in general should be called for
3757 * blocking commit to as per framework helpers
b830ebc9 3758 */
e7b07cee
HW		 3759 r = amdgpu_bo_reserve(abo, true);
3760 if (unlikely(r != 0)) {
3761 DRM_ERROR("failed to reserve buffer before flip\n");
3762 WARN_ON(1);
3763 }
3764
3765 /* Wait for all fences on this FB */
3766 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3767 MAX_SCHEDULE_TIMEOUT) < 0);
3768
3769 amdgpu_bo_unreserve(abo);
3770
3771 /* Wait until we're out of the vertical blank period before the one
3772 * targeted by the flip
3773 */
3774 while ((acrtc->enabled &&
3775 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3776 &vpos, &hpos, NULL, NULL,
3777 &crtc->hwmode)
3778 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3779 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3780 (int)(target_vblank -
3781 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3782 usleep_range(1000, 1100);
3783 }
3784
3785 /* Flip */
3786 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3787 /* update crtc fb */
3788 crtc->primary->fb = fb;
3789
3790 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3791 WARN_ON(!acrtc_state->stream);
3792
3793 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3794 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3795 addr.flip_immediate = async_flip;
3796
3797
3798 if (acrtc->base.state->event)
3799 prepare_flip_isr(acrtc);
3800
3be5262e 3801 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3802 surface_updates->flip_addr = &addr;
3803
3804
bc6828e0
BL		 3805 dc_commit_updates_for_stream(adev->dm.dc,
3806 surface_updates,
3807 1,
3808 acrtc_state->stream,
3809 NULL,
3810 &surface_updates->surface,
3811 state);
e7b07cee
HW		 3812
3813 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3814 __func__,
3815 addr.address.grph.addr.high_part,
3816 addr.address.grph.addr.low_part);
3817
3818
3819 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3820}
3821
3be5262e 3822static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3823 struct drm_device *dev,
3824 struct amdgpu_display_manager *dm,
3825 struct drm_crtc *pcrtc,
3826 bool *wait_for_vblank)
e7b07cee
HW		 3827{
3828 uint32_t i;
3829 struct drm_plane *plane;
0bc9706d 3830 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3831 struct dc_stream_state *dc_stream_attach;
3be5262e 3832 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3833 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3834 struct drm_crtc_state *new_pcrtc_state =
3835 drm_atomic_get_new_crtc_state(state, pcrtc);
3836 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3837 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3838 int planes_count = 0;
3839 unsigned long flags;
3840
3841 /* update planes when needed */
0bc9706d
LSL		 3842 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3843 struct drm_crtc *crtc = new_plane_state->crtc;
3844 struct drm_crtc_state *new_crtc_state =
3845 drm_atomic_get_new_crtc_state(state, crtc);
3846 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3847 bool pflip_needed;
54d76575 3848 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3849
3850 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3851 handle_cursor_update(plane, old_plane_state);
3852 continue;
3853 }
3854
0bc9706d 3855 if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active)
e7b07cee
HW		 3856 continue;
3857
3858 pflip_needed = !state->allow_modeset;
3859
3860 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3861 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3862 DRM_ERROR("%s: acrtc %d, already busy\n",
3863 __func__,
3864 acrtc_attach->crtc_id);
e7b07cee 3865 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
b830ebc9 3866 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3867 WARN_ON(1);
3868 }
3869 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3870
3871 if (!pflip_needed) {
54d76575 3872 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3873
54d76575 3874 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3875
3876 dc_stream_attach = acrtc_state->stream;
3877 planes_count++;
3878
0bc9706d 3879 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3880 /* Assume even ONE crtc with immediate flip means
3881 * entire can't wait for VBLANK
3882 * TODO Check if it's correct
3883 */
3884 *wait_for_vblank =
0bc9706d 3885 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3886 false : true;
3887
3888 /* TODO: Needs rework for multiplane flip */
3889 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3890 drm_crtc_vblank_get(crtc);
3891
3892 amdgpu_dm_do_flip(
3893 crtc,
3894 fb,
bc6828e0
BL		 3895 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3896 dm_state->context);
e7b07cee
HW		 3897 }
3898
3899 }
3900
3901 if (planes_count) {
3902 unsigned long flags;
3903
0bc9706d 3904 if (new_pcrtc_state->event) {
e7b07cee
HW		 3905
3906 drm_crtc_vblank_get(pcrtc);
3907
3908 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3909 prepare_flip_isr(acrtc_attach);
3910 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3911 }
3912
3be5262e
HW		 3913 if (false == dc_commit_planes_to_stream(dm->dc,
3914 plane_states_constructed,
3915 planes_count,
bc6828e0
BL		 3916 dc_stream_attach,
3917 dm_state->context))
3be5262e 3918 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3919 } else {
3920 /*TODO BUG Here should go disable planes on CRTC. */
3921 }
3922}
3923
3924
7578ecda
AD		 3925static int amdgpu_dm_atomic_commit(struct drm_device *dev,
3926 struct drm_atomic_state *state,
3927 bool nonblock)
e7b07cee
HW		 3928{
3929 struct drm_crtc *crtc;
c2cea706 3930 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 3931 struct amdgpu_device *adev = dev->dev_private;
3932 int i;
3933
3934 /*
3935 * We evade vblanks and pflips on crtc that
3936 * should be changed. We do it here to flush & disable
3937 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3938 * it will update crtc->dm_crtc_state->stream pointer which is used in
3939 * the ISRs.
3940 */
c2cea706 3941 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 3942 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 3943 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3944
54d76575 3945 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 3946 manage_dm_interrupts(adev, acrtc, false);
3947 }
fc9e9920
S		 3948 /* Add check here for SoC's that support hardware cursor plane, to
3949 * unset legacy_cursor_update */
e7b07cee
HW		 3950
3951 return drm_atomic_helper_commit(dev, state, nonblock);
3952
3953 /*TODO Handle EINTR, reenable IRQ*/
3954}
3955
7578ecda 3956static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 3957{
3958 struct drm_device *dev = state->dev;
3959 struct amdgpu_device *adev = dev->dev_private;
3960 struct amdgpu_display_manager *dm = &adev->dm;
3961 struct dm_atomic_state *dm_state;
3962 uint32_t i, j;
3963 uint32_t new_crtcs_count = 0;
5cc6dcbd 3964 struct drm_crtc *crtc;
0bc9706d 3965 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 3966 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 3967 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 3968 unsigned long flags;
3969 bool wait_for_vblank = true;
3970 struct drm_connector *connector;
c2cea706 3971 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 3972 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 3973
3974 drm_atomic_helper_update_legacy_modeset_state(dev, state);
3975
3976 dm_state = to_dm_atomic_state(state);
3977
3978 /* update changed items */
0bc9706d 3979 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 3980 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 3981
54d76575
LSL		 3982 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
3983 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 3984
f1ad2f5e 3985 DRM_DEBUG_DRIVER(
e7b07cee
HW		 3986 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
3987 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
3988 "connectors_changed:%d\n",
3989 acrtc->crtc_id,
0bc9706d
LSL		 3990 new_crtc_state->enable,
3991 new_crtc_state->active,
3992 new_crtc_state->planes_changed,
3993 new_crtc_state->mode_changed,
3994 new_crtc_state->active_changed,
3995 new_crtc_state->connectors_changed);
e7b07cee
HW		 3996
3997 /* handles headless hotplug case, updating new_state and
3998 * aconnector as needed
3999 */
4000
54d76575 4001 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4002
f1ad2f5e 4003 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4004
54d76575 4005 if (!dm_new_crtc_state->stream) {
e7b07cee 4006 /*
b830ebc9
HW		 4007 * this could happen because of issues with
4008 * userspace notifications delivery.
4009 * In this case userspace tries to set mode on
4010 * display which is disconnect in fact.
4011 * dc_sink in NULL in this case on aconnector.
4012 * We expect reset mode will come soon.
4013 *
4014 * This can also happen when unplug is done
4015 * during resume sequence ended
4016 *
4017 * In this case, we want to pretend we still
4018 * have a sink to keep the pipe running so that
4019 * hw state is consistent with the sw state
4020 */
f1ad2f5e 4021 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4022 __func__, acrtc->base.base.id);
4023 continue;
4024 }
4025
4026
54d76575
LSL		 4027 if (dm_old_crtc_state->stream)
4028 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4029
4030
4031 /*
4032 * this loop saves set mode crtcs
4033 * we needed to enable vblanks once all
4034 * resources acquired in dc after dc_commit_streams
4035 */
4036
4037 /*TODO move all this into dm_crtc_state, get rid of
4038 * new_crtcs array and use old and new atomic states
4039 * instead
4040 */
4041 new_crtcs[new_crtcs_count] = acrtc;
4042 new_crtcs_count++;
4043
0bc9706d 4044 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
e7b07cee 4045 acrtc->enabled = true;
0bc9706d
LSL		 4046 acrtc->hw_mode = new_crtc_state->mode;
4047 crtc->hwmode = new_crtc_state->mode;
4048 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4049 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4050
4051 /* i.e. reset mode */
54d76575
LSL		 4052 if (dm_old_crtc_state->stream)
4053 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4054 }
4055 } /* for_each_crtc_in_state() */
4056
4057 /*
4058 * Add streams after required streams from new and replaced streams
4059 * are removed from freesync module
4060 */
4061 if (adev->dm.freesync_module) {
4062 for (i = 0; i < new_crtcs_count; i++) {
c84dec2f 4063 struct amdgpu_dm_connector *aconnector = NULL;
b830ebc9 4064
0bc9706d
LSL		 4065 new_crtc_state = drm_atomic_get_new_crtc_state(state,
4066 &new_crtcs[i]->base);
54d76575 4067 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4068
54d76575 4069 new_stream = dm_new_crtc_state->stream;
1daf8c63 4070 aconnector = amdgpu_dm_find_first_crtc_matching_connector(
e7b07cee 4071 state,
9ba29fcb 4072 &new_crtcs[i]->base);
e7b07cee 4073 if (!aconnector) {
f1ad2f5e 4074 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
b830ebc9
HW		 4075 "skipping freesync init\n",
4076 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4077 continue;
4078 }
4079
4080 mod_freesync_add_stream(adev->dm.freesync_module,
4081 new_stream, &aconnector->caps);
4082 }
4083 }
4084
4085 if (dm_state->context)
608ac7bb 4086 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
e7b07cee 4087
0bc9706d 4088 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4089 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4090
54d76575 4091 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4092
54d76575 4093 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4094 const struct dc_stream_status *status =
54d76575 4095 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4096
4097 if (!status)
54d76575 4098 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4099 else
4100 acrtc->otg_inst = status->primary_otg_inst;
4101 }
4102 }
4103
ebdd27e1 4104 /* Handle scaling and underscan changes*/
c2cea706 4105 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4106 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4107 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4108 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4109 struct dc_stream_status *status = NULL;
4110
0bc9706d
LSL		 4111 if (acrtc)
4112 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4113
e7b07cee 4114 /* Skip any modesets/resets */
0bc9706d 4115 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4116 continue;
4117
4118 /* Skip any thing not scale or underscan changes */
54d76575 4119 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4120 continue;
4121
54d76575 4122 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4123
54d76575
LSL		 4124 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4125 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4126
54d76575 4127 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4128 WARN_ON(!status);
3be5262e 4129 WARN_ON(!status->plane_count);
e7b07cee 4130
54d76575 4131 if (!dm_new_crtc_state->stream)
e7b07cee
HW		 4132 continue;
4133
4134 /*TODO How it works with MPO ?*/
3be5262e 4135 if (!dc_commit_planes_to_stream(
e7b07cee 4136 dm->dc,
3be5262e
HW		 4137 status->plane_states,
4138 status->plane_count,
bc6828e0
BL		 4139 dm_new_crtc_state->stream,
4140 dm_state->context))
e7b07cee
HW		 4141 dm_error("%s: Failed to update stream scaling!\n", __func__);
4142 }
4143
4144 for (i = 0; i < new_crtcs_count; i++) {
4145 /*
4146 * loop to enable interrupts on newly arrived crtc
4147 */
4148 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4149
0bc9706d 4150 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
54d76575 4151 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4152
4153 if (adev->dm.freesync_module)
4154 mod_freesync_notify_mode_change(
54d76575 4155 adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4156
4157 manage_dm_interrupts(adev, acrtc, true);
4158 }
4159
4160 /* update planes when needed per crtc*/
5cc6dcbd 4161 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4162 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4163
54d76575 4164 if (dm_new_crtc_state->stream)
5cc6dcbd 4165 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4166 }
4167
4168
4169 /*
4170 * send vblank event on all events not handled in flip and
4171 * mark consumed event for drm_atomic_helper_commit_hw_done
4172 */
4173 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4174 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4175
0bc9706d
LSL		 4176 if (new_crtc_state->event)
4177 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4178
0bc9706d 4179 new_crtc_state->event = NULL;
e7b07cee
HW		 4180 }
4181 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4182
4183 /* Signal HW programming completion */
4184 drm_atomic_helper_commit_hw_done(state);
4185
4186 if (wait_for_vblank)
4187 drm_atomic_helper_wait_for_vblanks(dev, state);
4188
4189 drm_atomic_helper_cleanup_planes(dev, state);
4190}
4191
4192
4193static int dm_force_atomic_commit(struct drm_connector *connector)
4194{
4195 int ret = 0;
4196 struct drm_device *ddev = connector->dev;
4197 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4198 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4199 struct drm_plane *plane = disconnected_acrtc->base.primary;
4200 struct drm_connector_state *conn_state;
4201 struct drm_crtc_state *crtc_state;
4202 struct drm_plane_state *plane_state;
4203
4204 if (!state)
4205 return -ENOMEM;
4206
4207 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4208
4209 /* Construct an atomic state to restore previous display setting */
4210
4211 /*
4212 * Attach connectors to drm_atomic_state
4213 */
4214 conn_state = drm_atomic_get_connector_state(state, connector);
4215
4216 ret = PTR_ERR_OR_ZERO(conn_state);
4217 if (ret)
4218 goto err;
4219
4220 /* Attach crtc to drm_atomic_state*/
4221 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4222
4223 ret = PTR_ERR_OR_ZERO(crtc_state);
4224 if (ret)
4225 goto err;
4226
4227 /* force a restore */
4228 crtc_state->mode_changed = true;
4229
4230 /* Attach plane to drm_atomic_state */
4231 plane_state = drm_atomic_get_plane_state(state, plane);
4232
4233 ret = PTR_ERR_OR_ZERO(plane_state);
4234 if (ret)
4235 goto err;
4236
4237
4238 /* Call commit internally with the state we just constructed */
4239 ret = drm_atomic_commit(state);
4240 if (!ret)
4241 return 0;
4242
4243err:
4244 DRM_ERROR("Restoring old state failed with %i\n", ret);
4245 drm_atomic_state_put(state);
4246
4247 return ret;
4248}
4249
4250/*
4251 * This functions handle all cases when set mode does not come upon hotplug.
4252 * This include when the same display is unplugged then plugged back into the
4253 * same port and when we are running without usermode desktop manager supprot
4254 */
3ee6b26b
AD		 4255void dm_restore_drm_connector_state(struct drm_device *dev,
4256 struct drm_connector *connector)
e7b07cee 4257{
c84dec2f 4258 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4259 struct amdgpu_crtc *disconnected_acrtc;
4260 struct dm_crtc_state *acrtc_state;
4261
4262 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4263 return;
4264
4265 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4266 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4267
4268 if (!disconnected_acrtc || !acrtc_state->stream)
4269 return;
4270
4271 /*
4272 * If the previous sink is not released and different from the current,
4273 * we deduce we are in a state where we can not rely on usermode call
4274 * to turn on the display, so we do it here
4275 */
4276 if (acrtc_state->stream->sink != aconnector->dc_sink)
4277 dm_force_atomic_commit(&aconnector->base);
4278}
4279
e7b07cee
HW		 4280/*`
4281 * Grabs all modesetting locks to serialize against any blocking commits,
4282 * Waits for completion of all non blocking commits.
4283 */
3ee6b26b
AD		 4284static int do_aquire_global_lock(struct drm_device *dev,
4285 struct drm_atomic_state *state)
e7b07cee
HW		 4286{
4287 struct drm_crtc *crtc;
4288 struct drm_crtc_commit *commit;
4289 long ret;
4290
4291 /* Adding all modeset locks to aquire_ctx will
4292 * ensure that when the framework release it the
4293 * extra locks we are locking here will get released to
4294 */
4295 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4296 if (ret)
4297 return ret;
4298
4299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4300 spin_lock(&crtc->commit_lock);
4301 commit = list_first_entry_or_null(&crtc->commit_list,
4302 struct drm_crtc_commit, commit_entry);
4303 if (commit)
4304 drm_crtc_commit_get(commit);
4305 spin_unlock(&crtc->commit_lock);
4306
4307 if (!commit)
4308 continue;
4309
4310 /* Make sure all pending HW programming completed and
4311 * page flips done
4312 */
4313 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4314
4315 if (ret > 0)
4316 ret = wait_for_completion_interruptible_timeout(
4317 &commit->flip_done, 10*HZ);
4318
4319 if (ret == 0)
4320 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4321 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4322
4323 drm_crtc_commit_put(commit);
4324 }
4325
4326 return ret < 0 ? ret : 0;
4327}
4328
3ee6b26b
AD		 4329static int dm_update_crtcs_state(struct dc *dc,
4330 struct drm_atomic_state *state,
4331 bool enable,
4332 bool *lock_and_validation_needed)
e7b07cee 4333{
e7b07cee 4334 struct drm_crtc *crtc;
c2cea706 4335 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4336 int i;
54d76575 4337 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4338 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4339 struct dc_stream_state *new_stream;
62f55537 4340 int ret = 0;
d4d4a645 4341
62f55537
AG		 4342 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4343 /* update changed items */
c2cea706 4344 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4345 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4346 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4347 struct drm_connector_state *new_con_state = NULL;
62f55537 4348 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4349
9635b754
DS		 4350 new_stream = NULL;
4351
54d76575
LSL		 4352 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4353 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4354 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4355
1daf8c63 4356 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4357
62f55537 4358 /* TODO This hack should go away */
f4ac176e
JZ		 4359 if (aconnector && enable) {
4360 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4361 new_con_state = drm_atomic_get_connector_state(state,
4362 &aconnector->base);
19f89e23 4363
c2cea706
LSL		 4364 if (IS_ERR(new_con_state)) {
4365 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4366 break;
4367 }
19f89e23 4368
c2cea706 4369 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4370
62f55537 4371 new_stream = create_stream_for_sink(aconnector,
c2cea706 4372 &new_crtc_state->mode,
62f55537 4373 dm_conn_state);
19f89e23 4374
62f55537
AG		 4375 /*
4376 * we can have no stream on ACTION_SET if a display
4377 * was disconnected during S3, in this case it not and
4378 * error, the OS will be updated after detection, and
4379 * do the right thing on next atomic commit
4380 */
19f89e23 4381
62f55537 4382 if (!new_stream) {
f1ad2f5e 4383 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4384 __func__, acrtc->base.base.id);
4385 break;
19f89e23 4386 }
62f55537 4387 }
19f89e23 4388
9a5d9c48
LSL		 4389 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4390 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
19f89e23 4391
c2cea706 4392 new_crtc_state->mode_changed = false;
e7b07cee 4393
c2cea706 4394 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9a5d9c48 4395 new_crtc_state->mode_changed);
62f55537 4396 }
b830ebc9 4397
e7b07cee 4398
c2cea706 4399 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4400 goto next_crtc;
e7b07cee 4401
f1ad2f5e 4402 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4403 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4404 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4405 "connectors_changed:%d\n",
4406 acrtc->crtc_id,
c2cea706
LSL		 4407 new_crtc_state->enable,
4408 new_crtc_state->active,
4409 new_crtc_state->planes_changed,
4410 new_crtc_state->mode_changed,
4411 new_crtc_state->active_changed,
4412 new_crtc_state->connectors_changed);
e7b07cee 4413
62f55537
AG		 4414 /* Remove stream for any changed/disabled CRTC */
4415 if (!enable) {
4416
54d76575 4417 if (!dm_old_crtc_state->stream)
9635b754 4418 goto next_crtc;
62f55537 4419
f1ad2f5e 4420 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4421 crtc->base.id);
e7b07cee 4422
1dc90497 4423 /* i.e. reset mode */
62c933f9 4424 if (dc_remove_stream_from_ctx(
62f55537
AG		 4425 dc,
4426 dm_state->context,
62c933f9 4427 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4428 ret = -EINVAL;
9635b754 4429 goto fail;
62f55537
AG		 4430 }
4431
54d76575
LSL		 4432 dc_stream_release(dm_old_crtc_state->stream);
4433 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4434
4435 *lock_and_validation_needed = true;
4436
4437 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4438 /*
4439 * Quick fix to prevent NULL pointer on new_stream when
4440 * added MST connectors not found in existing crtc_state in the chained mode
4441 * TODO: need to dig out the root cause of that
4442 */
4443 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4444 goto next_crtc;
62f55537 4445
c2cea706 4446 if (modereset_required(new_crtc_state))
9635b754 4447 goto next_crtc;
62f55537 4448
c2cea706 4449 if (modeset_required(new_crtc_state, new_stream,
54d76575 4450 dm_old_crtc_state->stream)) {
62f55537 4451
54d76575 4452 WARN_ON(dm_new_crtc_state->stream);
62f55537 4453
54d76575 4454 dm_new_crtc_state->stream = new_stream;
62f55537
AG		 4455 dc_stream_retain(new_stream);
4456
f1ad2f5e 4457 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4458 crtc->base.id);
1dc90497 4459
13ab1b44 4460 if (dc_add_stream_to_ctx(
1dc90497
AG		 4461 dc,
4462 dm_state->context,
13ab1b44 4463 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4464 ret = -EINVAL;
9635b754 4465 goto fail;
1dc90497
AG		 4466 }
4467
62f55537 4468 *lock_and_validation_needed = true;
9b690ef3 4469 }
62f55537 4470 }
9b690ef3 4471
9635b754 4472next_crtc:
62f55537
AG		 4473 /* Release extra reference */
4474 if (new_stream)
4475 dc_stream_release(new_stream);
4476 }
e7b07cee 4477
62f55537 4478 return ret;
9635b754
DS		 4479
4480fail:
4481 if (new_stream)
4482 dc_stream_release(new_stream);
4483 return ret;
62f55537 4484}
9b690ef3 4485
3ee6b26b
AD		 4486static int dm_update_planes_state(struct dc *dc,
4487 struct drm_atomic_state *state,
4488 bool enable,
4489 bool *lock_and_validation_needed)
62f55537
AG		 4490{
4491 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4492 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4493 struct drm_plane *plane;
4494 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4495 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4496 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4497 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4498 int i ;
4499 /* TODO return page_flip_needed() function */
4500 bool pflip_needed = !state->allow_modeset;
4501 int ret = 0;
e7b07cee 4502
62f55537
AG		 4503 if (pflip_needed)
4504 return ret;
9b690ef3 4505
62f55537
AG		 4506 /* Add new planes */
4507 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4508 new_plane_crtc = new_plane_state->crtc;
4509 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4510 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4511 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4512
4513 /*TODO Implement atomic check for cursor plane */
4514 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4515 continue;
9b690ef3 4516
62f55537
AG		 4517 /* Remove any changed/removed planes */
4518 if (!enable) {
a7b06724 4519
62f55537
AG		 4520 if (!old_plane_crtc)
4521 continue;
4522
0bc9706d
LSL		 4523 old_crtc_state = drm_atomic_get_old_crtc_state(
4524 state, old_plane_crtc);
54d76575 4525 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4526
54d76575 4527 if (!dm_old_crtc_state->stream)
62f55537
AG		 4528 continue;
4529
f1ad2f5e 4530 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4531 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4532
62f55537
AG		 4533 if (!dc_remove_plane_from_context(
4534 dc,
54d76575
LSL		 4535 dm_old_crtc_state->stream,
4536 dm_old_plane_state->dc_state,
62f55537
AG		 4537 dm_state->context)) {
4538
4539 ret = EINVAL;
4540 return ret;
e7b07cee
HW		 4541 }
4542
9b690ef3 4543
54d76575
LSL		 4544 dc_plane_state_release(dm_old_plane_state->dc_state);
4545 dm_new_plane_state->dc_state = NULL;
1dc90497 4546
62f55537 4547 *lock_and_validation_needed = true;
1dc90497 4548
62f55537 4549 } else { /* Add new planes */
1dc90497 4550
62f55537
AG		 4551 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4552 continue;
e7b07cee 4553
62f55537
AG		 4554 if (!new_plane_crtc)
4555 continue;
e7b07cee 4556
62f55537 4557 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4558 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4559
54d76575 4560 if (!dm_new_crtc_state->stream)
62f55537
AG		 4561 continue;
4562
4563
54d76575 4564 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4565
54d76575 4566 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4567
f1ad2f5e 4568 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4569 plane->base.id, new_plane_crtc->base.id);
4570
54d76575 4571 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4572 ret = -EINVAL;
4573 return ret;
4574 }
4575
4576 ret = fill_plane_attributes(
4577 new_plane_crtc->dev->dev_private,
54d76575 4578 dm_new_plane_state->dc_state,
62f55537
AG		 4579 new_plane_state,
4580 new_crtc_state,
4581 false);
4582 if (ret)
4583 return ret;
4584
4585
4586 if (!dc_add_plane_to_context(
4587 dc,
54d76575
LSL		 4588 dm_new_crtc_state->stream,
4589 dm_new_plane_state->dc_state,
62f55537
AG		 4590 dm_state->context)) {
4591
4592 ret = -EINVAL;
4593 return ret;
e7b07cee 4594 }
62f55537
AG		 4595
4596 *lock_and_validation_needed = true;
e7b07cee 4597 }
62f55537 4598 }
e7b07cee
HW		 4599
4600
62f55537
AG		 4601 return ret;
4602}
4603
7578ecda
AD		 4604static int amdgpu_dm_atomic_check(struct drm_device *dev,
4605 struct drm_atomic_state *state)
62f55537
AG		 4606{
4607 int i;
4608 int ret;
4609 struct amdgpu_device *adev = dev->dev_private;
4610 struct dc *dc = adev->dm.dc;
4611 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4612 struct drm_connector *connector;
c2cea706 4613 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4614 struct drm_crtc *crtc;
fc9e9920 4615 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 4616
62f55537
AG		 4617 /*
4618 * This bool will be set for true for any modeset/reset
4619 * or plane update which implies non fast surface update.
4620 */
4621 bool lock_and_validation_needed = false;
4622
4623 ret = drm_atomic_helper_check_modeset(dev, state);
62f55537
AG		 4624 if (ret) {
4625 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4626 return ret;
4627 }
4628
4629 /*
fc9e9920
S		 4630 * legacy_cursor_update should be made false for SoC's having
4631 * a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(),
4632 * otherwise for software cursor plane,
4633 * we should not add it to list of affected planes.
62f55537 4634 */
fc9e9920
S		 4635 if (state->legacy_cursor_update) {
4636 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4637 if (new_crtc_state->color_mgmt_changed) {
4638 ret = drm_atomic_add_affected_planes(state, crtc);
4639 if (ret)
4640 goto fail;
4641 }
4642 }
4643 } else {
4644 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4645 if (!new_crtc_state->enable)
4646 continue;
4647
4648 ret = drm_atomic_add_affected_connectors(state, crtc);
4649 if (ret)
4650 return ret;
4651
e7b07cee
HW		 4652 ret = drm_atomic_add_affected_planes(state, crtc);
4653 if (ret)
4654 goto fail;
4655 }
4656 }
4657
62f55537
AG		 4658 dm_state->context = dc_create_state();
4659 ASSERT(dm_state->context);
f36cc577 4660 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4661
4662 /* Remove exiting planes if they are modified */
4663 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4664 if (ret) {
4665 goto fail;
4666 }
4667
4668 /* Disable all crtcs which require disable */
4669 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4670 if (ret) {
4671 goto fail;
4672 }
4673
4674 /* Enable all crtcs which require enable */
4675 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4676 if (ret) {
4677 goto fail;
4678 }
4679
4680 /* Add new/modified planes */
4681 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4682 if (ret) {
4683 goto fail;
4684 }
4685
4686 /* Run this here since we want to validate the streams we created */
4687 ret = drm_atomic_helper_check_planes(dev, state);
4688 if (ret)
4689 goto fail;
4690
ebdd27e1 4691 /* Check scaling and underscan changes*/
e7b07cee
HW		 4692 /*TODO Removed scaling changes validation due to inability to commit
4693 * new stream into context w\o causing full reset. Need to
4694 * decide how to handle.
4695 */
c2cea706 4696 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4697 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4698 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4699 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4700
4701 /* Skip any modesets/resets */
0bc9706d
LSL		 4702 if (!acrtc || drm_atomic_crtc_needs_modeset(
4703 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4704 continue;
4705
b830ebc9 4706 /* Skip any thing not scale or underscan changes */
54d76575 4707 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4708 continue;
4709
4710 lock_and_validation_needed = true;
4711 }
4712
e7b07cee
HW		 4713 /*
4714 * For full updates case when
4715 * removing/adding/updating streams on once CRTC while flipping
4716 * on another CRTC,
4717 * acquiring global lock will guarantee that any such full
4718 * update commit
4719 * will wait for completion of any outstanding flip using DRMs
4720 * synchronization events.
4721 */
4722
4723 if (lock_and_validation_needed) {
4724
4725 ret = do_aquire_global_lock(dev, state);
4726 if (ret)
4727 goto fail;
1dc90497 4728
e750d56d 4729 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4730 ret = -EINVAL;
4731 goto fail;
4732 }
4733 }
4734
4735 /* Must be success */
4736 WARN_ON(ret);
4737 return ret;
4738
4739fail:
4740 if (ret == -EDEADLK)
f1ad2f5e 4741 DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n");
e7b07cee 4742 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
f1ad2f5e 4743 DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
e7b07cee 4744 else
62f55537 4745 DRM_ERROR("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4746
4747 return ret;
4748}
4749
3ee6b26b
AD		 4750static bool is_dp_capable_without_timing_msa(struct dc *dc,
4751 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4752{
4753 uint8_t dpcd_data;
4754 bool capable = false;
4755
c84dec2f 4756 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4757 dm_helpers_dp_read_dpcd(
4758 NULL,
c84dec2f 4759 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4760 DP_DOWN_STREAM_PORT_COUNT,
4761 &dpcd_data,
4762 sizeof(dpcd_data))) {
4763 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4764 }
4765
4766 return capable;
4767}
3ee6b26b
AD		 4768void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4769 struct edid *edid)
e7b07cee
HW		 4770{
4771 int i;
4772 uint64_t val_capable;
4773 bool edid_check_required;
4774 struct detailed_timing *timing;
4775 struct detailed_non_pixel *data;
4776 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4777 struct amdgpu_dm_connector *amdgpu_dm_connector =
4778 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4779
4780 struct drm_device *dev = connector->dev;
4781 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4782
e7b07cee 4783 edid_check_required = false;
c84dec2f 4784 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4785 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4786 return;
4787 }
4788 if (!adev->dm.freesync_module)
4789 return;
4790 /*
4791 * if edid non zero restrict freesync only for dp and edp
4792 */
4793 if (edid) {
c84dec2f
HW		 4794 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4795 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4796 edid_check_required = is_dp_capable_without_timing_msa(
4797 adev->dm.dc,
c84dec2f 4798 amdgpu_dm_connector);
e7b07cee
HW		 4799 }
4800 }
4801 val_capable = 0;
4802 if (edid_check_required == true && (edid->version > 1 ||
4803 (edid->version == 1 && edid->revision > 1))) {
4804 for (i = 0; i < 4; i++) {
4805
4806 timing = &edid->detailed_timings[i];
4807 data = &timing->data.other_data;
4808 range = &data->data.range;
4809 /*
4810 * Check if monitor has continuous frequency mode
4811 */
4812 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4813 continue;
4814 /*
4815 * Check for flag range limits only. If flag == 1 then
4816 * no additional timing information provided.
4817 * Default GTF, GTF Secondary curve and CVT are not
4818 * supported
4819 */
4820 if (range->flags != 1)
4821 continue;
4822
c84dec2f
HW		 4823 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4824 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4825 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4826 range->pixel_clock_mhz * 10;
4827 break;
4828 }
4829
c84dec2f
HW		 4830 if (amdgpu_dm_connector->max_vfreq -
4831 amdgpu_dm_connector->min_vfreq > 10) {
4832 amdgpu_dm_connector->caps.supported = true;
4833 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4834 amdgpu_dm_connector->min_vfreq * 1000000;
4835 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4836 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4837 val_capable = 1;
4838 }
4839 }
4840
4841 /*
4842 * TODO figure out how to notify user-mode or DRM of freesync caps
4843 * once we figure out how to deal with freesync in an upstreamable
4844 * fashion
4845 */
4846
4847}
4848
3ee6b26b 4849void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 4850{
4851 /*
4852 * TODO fill in once we figure out how to deal with freesync in
4853 * an upstreamable fashion
4854 */
4855}
Linux 6.x block layer and io_uring tree(s)