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drm/amd/display: Check return value of drm helper
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
a7669aff 32#include "dal_asic_id.h"
743b9786
NK		 33#include "dmub/inc/dmub_srv.h"
34#include "dc/inc/hw/dmcu.h"
35#include "dc/inc/hw/abm.h"
9a71c7d3 36#include "dc/dc_dmub_srv.h"
4562236b
HW		 37
38#include "vid.h"
39#include "amdgpu.h"
a49dcb88 40#include "amdgpu_display.h"
a94d5569 41#include "amdgpu_ucode.h"
4562236b
HW		 42#include "atom.h"
43#include "amdgpu_dm.h"
52704fca
BL		 44#ifdef CONFIG_DRM_AMD_DC_HDCP
45#include "amdgpu_dm_hdcp.h"
53e108aa 46#include <drm/drm_hdcp.h>
52704fca 47#endif
e7b07cee 48#include "amdgpu_pm.h"
4562236b
HW		 49
50#include "amd_shared.h"
51#include "amdgpu_dm_irq.h"
52#include "dm_helpers.h"
e7b07cee 53#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 54#if defined(CONFIG_DEBUG_FS)
55#include "amdgpu_dm_debugfs.h"
56#endif
4562236b
HW		 57
58#include "ivsrcid/ivsrcid_vislands30.h"
59
60#include <linux/module.h>
61#include <linux/moduleparam.h>
62#include <linux/version.h>
e7b07cee 63#include <linux/types.h>
97028037 64#include <linux/pm_runtime.h>
09d21852 65#include <linux/pci.h>
a94d5569 66#include <linux/firmware.h>
6ce8f316 67#include <linux/component.h>
4562236b
HW		 68
69#include <drm/drm_atomic.h>
674e78ac 70#include <drm/drm_atomic_uapi.h>
4562236b
HW		 71#include <drm/drm_atomic_helper.h>
72#include <drm/drm_dp_mst_helper.h>
e7b07cee 73#include <drm/drm_fb_helper.h>
09d21852 74#include <drm/drm_fourcc.h>
e7b07cee 75#include <drm/drm_edid.h>
09d21852 76#include <drm/drm_vblank.h>
6ce8f316 77#include <drm/drm_audio_component.h>
0c8620d6 78#include <drm/drm_hdcp.h>
4562236b 79
b86a1aa3 80#if defined(CONFIG_DRM_AMD_DC_DCN)
5527cd06 81#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
ff5ef992 82
ad941f7a
FX		 83#include "dcn/dcn_1_0_offset.h"
84#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 85#include "soc15_hw_ip.h"
86#include "vega10_ip_offset.h"
ff5ef992
AD		 87
88#include "soc15_common.h"
89#endif
90
e7b07cee 91#include "modules/inc/mod_freesync.h"
bbf854dc 92#include "modules/power/power_helpers.h"
ecd0136b 93#include "modules/inc/mod_info_packet.h"
e7b07cee 94
743b9786
NK		 95#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
96MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
2200eb9e 97
a94d5569
DF		 98#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
99MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 100
8c7aea40
NK		 101/* Number of bytes in PSP header for firmware. */
102#define PSP_HEADER_BYTES 0x100
103
104/* Number of bytes in PSP footer for firmware. */
105#define PSP_FOOTER_BYTES 0x100
106
b8592b48
LL		 107/**
108 * DOC: overview
109 *
110 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
111 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
112 * requests into DC requests, and DC responses into DRM responses.
113 *
114 * The root control structure is &struct amdgpu_display_manager.
115 */
116
7578ecda
AD		 117/* basic init/fini API */
118static int amdgpu_dm_init(struct amdgpu_device *adev);
119static void amdgpu_dm_fini(struct amdgpu_device *adev);
120
1f6010a9
DF		 121/*
122 * initializes drm_device display related structures, based on the information
7578ecda
AD		 123 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
124 * drm_encoder, drm_mode_config
125 *
126 * Returns 0 on success
127 */
128static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
129/* removes and deallocates the drm structures, created by the above function */
130static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
131
132static void
133amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
134
135static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 136 struct drm_plane *plane,
cc1fec57
NK		 137 unsigned long possible_crtcs,
138 const struct dc_plane_cap *plane_cap);
7578ecda
AD		 139static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
140 struct drm_plane *plane,
141 uint32_t link_index);
142static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
143 struct amdgpu_dm_connector *amdgpu_dm_connector,
144 uint32_t link_index,
145 struct amdgpu_encoder *amdgpu_encoder);
146static int amdgpu_dm_encoder_init(struct drm_device *dev,
147 struct amdgpu_encoder *aencoder,
148 uint32_t link_index);
149
150static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
151
152static int amdgpu_dm_atomic_commit(struct drm_device *dev,
153 struct drm_atomic_state *state,
154 bool nonblock);
155
156static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
157
158static int amdgpu_dm_atomic_check(struct drm_device *dev,
159 struct drm_atomic_state *state);
160
674e78ac
NK		 161static void handle_cursor_update(struct drm_plane *plane,
162 struct drm_plane_state *old_plane_state);
7578ecda 163
8c322309
RL		 164static void amdgpu_dm_set_psr_caps(struct dc_link *link);
165static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
166static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
167static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
168
169
4562236b
HW		 170/*
171 * dm_vblank_get_counter
172 *
173 * @brief
174 * Get counter for number of vertical blanks
175 *
176 * @param
177 * struct amdgpu_device *adev - [in] desired amdgpu device
178 * int disp_idx - [in] which CRTC to get the counter from
179 *
180 * @return
181 * Counter for vertical blanks
182 */
183static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
184{
185 if (crtc >= adev->mode_info.num_crtc)
186 return 0;
187 else {
188 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 189 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
190 acrtc->base.state);
4562236b 191
da5c47f6
AG		 192
193 if (acrtc_state->stream == NULL) {
0971c40e
HW		 194 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
195 crtc);
4562236b
HW		 196 return 0;
197 }
198
da5c47f6 199 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 200 }
201}
202
203static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 204 u32 *vbl, u32 *position)
4562236b 205{
81c50963
ST		 206 uint32_t v_blank_start, v_blank_end, h_position, v_position;
207
4562236b
HW		 208 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
209 return -EINVAL;
210 else {
211 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 212 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
213 acrtc->base.state);
4562236b 214
da5c47f6 215 if (acrtc_state->stream == NULL) {
0971c40e
HW		 216 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
217 crtc);
4562236b
HW		 218 return 0;
219 }
220
81c50963
ST		 221 /*
222 * TODO rework base driver to use values directly.
223 * for now parse it back into reg-format
224 */
da5c47f6 225 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 226 &v_blank_start,
227 &v_blank_end,
228 &h_position,
229 &v_position);
230
e806208d
AG		 231 *position = v_position | (h_position << 16);
232 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 233 }
234
235 return 0;
236}
237
238static bool dm_is_idle(void *handle)
239{
240 /* XXX todo */
241 return true;
242}
243
244static int dm_wait_for_idle(void *handle)
245{
246 /* XXX todo */
247 return 0;
248}
249
250static bool dm_check_soft_reset(void *handle)
251{
252 return false;
253}
254
255static int dm_soft_reset(void *handle)
256{
257 /* XXX todo */
258 return 0;
259}
260
3ee6b26b
AD		 261static struct amdgpu_crtc *
262get_crtc_by_otg_inst(struct amdgpu_device *adev,
263 int otg_inst)
4562236b
HW		 264{
265 struct drm_device *dev = adev->ddev;
266 struct drm_crtc *crtc;
267 struct amdgpu_crtc *amdgpu_crtc;
268
4562236b
HW		 269 if (otg_inst == -1) {
270 WARN_ON(1);
271 return adev->mode_info.crtcs[0];
272 }
273
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
275 amdgpu_crtc = to_amdgpu_crtc(crtc);
276
277 if (amdgpu_crtc->otg_inst == otg_inst)
278 return amdgpu_crtc;
279 }
280
281 return NULL;
282}
283
66b0c973
MK		 284static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
285{
286 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
287 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
288}
289
b8e8c934
HW		 290/**
291 * dm_pflip_high_irq() - Handle pageflip interrupt
292 * @interrupt_params: ignored
293 *
294 * Handles the pageflip interrupt by notifying all interested parties
295 * that the pageflip has been completed.
296 */
4562236b
HW		 297static void dm_pflip_high_irq(void *interrupt_params)
298{
4562236b
HW		 299 struct amdgpu_crtc *amdgpu_crtc;
300 struct common_irq_params *irq_params = interrupt_params;
301 struct amdgpu_device *adev = irq_params->adev;
302 unsigned long flags;
71bbe51a
MK		 303 struct drm_pending_vblank_event *e;
304 struct dm_crtc_state *acrtc_state;
305 uint32_t vpos, hpos, v_blank_start, v_blank_end;
306 bool vrr_active;
4562236b
HW		 307
308 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
309
310 /* IRQ could occur when in initial stage */
1f6010a9 311 /* TODO work and BO cleanup */
4562236b
HW		 312 if (amdgpu_crtc == NULL) {
313 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
314 return;
315 }
316
317 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 318
319 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
320 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
321 amdgpu_crtc->pflip_status,
322 AMDGPU_FLIP_SUBMITTED,
323 amdgpu_crtc->crtc_id,
324 amdgpu_crtc);
325 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
326 return;
327 }
328
71bbe51a
MK		 329 /* page flip completed. */
330 e = amdgpu_crtc->event;
331 amdgpu_crtc->event = NULL;
4562236b 332
71bbe51a
MK		 333 if (!e)
334 WARN_ON(1);
1159898a 335
71bbe51a
MK		 336 acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
337 vrr_active = amdgpu_dm_vrr_active(acrtc_state);
338
339 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
340 if (!vrr_active ||
341 !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
342 &v_blank_end, &hpos, &vpos) ||
343 (vpos < v_blank_start)) {
344 /* Update to correct count and vblank timestamp if racing with
345 * vblank irq. This also updates to the correct vblank timestamp
346 * even in VRR mode, as scanout is past the front-porch atm.
347 */
348 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
1159898a 349
71bbe51a
MK		 350 /* Wake up userspace by sending the pageflip event with proper
351 * count and timestamp of vblank of flip completion.
352 */
353 if (e) {
354 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
355
356 /* Event sent, so done with vblank for this flip */
357 drm_crtc_vblank_put(&amdgpu_crtc->base);
358 }
359 } else if (e) {
360 /* VRR active and inside front-porch: vblank count and
361 * timestamp for pageflip event will only be up to date after
362 * drm_crtc_handle_vblank() has been executed from late vblank
363 * irq handler after start of back-porch (vline 0). We queue the
364 * pageflip event for send-out by drm_crtc_handle_vblank() with
365 * updated timestamp and count, once it runs after us.
366 *
367 * We need to open-code this instead of using the helper
368 * drm_crtc_arm_vblank_event(), as that helper would
369 * call drm_crtc_accurate_vblank_count(), which we must
370 * not call in VRR mode while we are in front-porch!
371 */
372
373 /* sequence will be replaced by real count during send-out. */
374 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
375 e->pipe = amdgpu_crtc->crtc_id;
376
377 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
378 e = NULL;
379 }
4562236b 380
fdd1fe57
MK		 381 /* Keep track of vblank of this flip for flip throttling. We use the
382 * cooked hw counter, as that one incremented at start of this vblank
383 * of pageflip completion, so last_flip_vblank is the forbidden count
384 * for queueing new pageflips if vsync + VRR is enabled.
385 */
386 amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
387 amdgpu_crtc->crtc_id);
388
54f5499a 389 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 390 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
391
71bbe51a
MK		 392 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
393 amdgpu_crtc->crtc_id, amdgpu_crtc,
394 vrr_active, (int) !e);
4562236b
HW		 395}
396
d2574c33
MK		 397static void dm_vupdate_high_irq(void *interrupt_params)
398{
399 struct common_irq_params *irq_params = interrupt_params;
400 struct amdgpu_device *adev = irq_params->adev;
401 struct amdgpu_crtc *acrtc;
402 struct dm_crtc_state *acrtc_state;
09aef2c4 403 unsigned long flags;
d2574c33
MK		 404
405 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
406
407 if (acrtc) {
408 acrtc_state = to_dm_crtc_state(acrtc->base.state);
409
410 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
411 amdgpu_dm_vrr_active(acrtc_state));
412
413 /* Core vblank handling is done here after end of front-porch in
414 * vrr mode, as vblank timestamping will give valid results
415 * while now done after front-porch. This will also deliver
416 * page-flip completion events that have been queued to us
417 * if a pageflip happened inside front-porch.
418 */
09aef2c4 419 if (amdgpu_dm_vrr_active(acrtc_state)) {
d2574c33 420 drm_crtc_handle_vblank(&acrtc->base);
09aef2c4
MK		 421
422 /* BTR processing for pre-DCE12 ASICs */
423 if (acrtc_state->stream &&
424 adev->family < AMDGPU_FAMILY_AI) {
425 spin_lock_irqsave(&adev->ddev->event_lock, flags);
426 mod_freesync_handle_v_update(
427 adev->dm.freesync_module,
428 acrtc_state->stream,
429 &acrtc_state->vrr_params);
430
431 dc_stream_adjust_vmin_vmax(
432 adev->dm.dc,
433 acrtc_state->stream,
434 &acrtc_state->vrr_params.adjust);
435 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
436 }
437 }
d2574c33
MK		 438 }
439}
440
b8e8c934
HW		 441/**
442 * dm_crtc_high_irq() - Handles CRTC interrupt
443 * @interrupt_params: ignored
444 *
445 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
446 * event handler.
447 */
4562236b
HW		 448static void dm_crtc_high_irq(void *interrupt_params)
449{
450 struct common_irq_params *irq_params = interrupt_params;
451 struct amdgpu_device *adev = irq_params->adev;
4562236b 452 struct amdgpu_crtc *acrtc;
180db303 453 struct dm_crtc_state *acrtc_state;
09aef2c4 454 unsigned long flags;
4562236b 455
b57de80a 456 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 457
e5d0170e 458 if (acrtc) {
180db303
NK		 459 acrtc_state = to_dm_crtc_state(acrtc->base.state);
460
d2574c33
MK		 461 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
462 amdgpu_dm_vrr_active(acrtc_state));
463
464 /* Core vblank handling at start of front-porch is only possible
465 * in non-vrr mode, as only there vblank timestamping will give
466 * valid results while done in front-porch. Otherwise defer it
467 * to dm_vupdate_high_irq after end of front-porch.
468 */
469 if (!amdgpu_dm_vrr_active(acrtc_state))
470 drm_crtc_handle_vblank(&acrtc->base);
471
472 /* Following stuff must happen at start of vblank, for crc
473 * computation and below-the-range btr support in vrr mode.
474 */
475 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
476
09aef2c4 477 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
180db303
NK		 478 acrtc_state->vrr_params.supported &&
479 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
09aef2c4 480 spin_lock_irqsave(&adev->ddev->event_lock, flags);
180db303
NK		 481 mod_freesync_handle_v_update(
482 adev->dm.freesync_module,
483 acrtc_state->stream,
484 &acrtc_state->vrr_params);
485
486 dc_stream_adjust_vmin_vmax(
487 adev->dm.dc,
488 acrtc_state->stream,
489 &acrtc_state->vrr_params.adjust);
09aef2c4 490 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
180db303 491 }
e5d0170e 492 }
4562236b
HW		 493}
494
b8219745 495#if defined(CONFIG_DRM_AMD_DC_DCN)
16f17eda
LL		 496/**
497 * dm_dcn_crtc_high_irq() - Handles VStartup interrupt for DCN generation ASICs
498 * @interrupt params - interrupt parameters
499 *
500 * Notify DRM's vblank event handler at VSTARTUP
501 *
502 * Unlike DCE hardware, we trigger the handler at VSTARTUP. at which:
503 * * We are close enough to VUPDATE - the point of no return for hw
504 * * We are in the fixed portion of variable front porch when vrr is enabled
505 * * We are before VUPDATE, where double-buffered vrr registers are swapped
506 *
507 * It is therefore the correct place to signal vblank, send user flip events,
508 * and update VRR.
509 */
510static void dm_dcn_crtc_high_irq(void *interrupt_params)
511{
512 struct common_irq_params *irq_params = interrupt_params;
513 struct amdgpu_device *adev = irq_params->adev;
514 struct amdgpu_crtc *acrtc;
515 struct dm_crtc_state *acrtc_state;
516 unsigned long flags;
517
518 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
519
520 if (!acrtc)
521 return;
522
523 acrtc_state = to_dm_crtc_state(acrtc->base.state);
524
525 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
526 amdgpu_dm_vrr_active(acrtc_state));
527
528 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
529 drm_crtc_handle_vblank(&acrtc->base);
530
531 spin_lock_irqsave(&adev->ddev->event_lock, flags);
532
533 if (acrtc_state->vrr_params.supported &&
534 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
535 mod_freesync_handle_v_update(
536 adev->dm.freesync_module,
537 acrtc_state->stream,
538 &acrtc_state->vrr_params);
539
540 dc_stream_adjust_vmin_vmax(
541 adev->dm.dc,
542 acrtc_state->stream,
543 &acrtc_state->vrr_params.adjust);
544 }
545
546 if (acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED) {
547 if (acrtc->event) {
548 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
549 acrtc->event = NULL;
550 drm_crtc_vblank_put(&acrtc->base);
551 }
552 acrtc->pflip_status = AMDGPU_FLIP_NONE;
553 }
554
555 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
556}
b8219745 557#endif
16f17eda 558
4562236b
HW		 559static int dm_set_clockgating_state(void *handle,
560 enum amd_clockgating_state state)
561{
562 return 0;
563}
564
565static int dm_set_powergating_state(void *handle,
566 enum amd_powergating_state state)
567{
568 return 0;
569}
570
571/* Prototypes of private functions */
572static int dm_early_init(void* handle);
573
a32e24b4 574/* Allocate memory for FBC compressed data */
3e332d3a 575static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 576{
3e332d3a
RL		 577 struct drm_device *dev = connector->dev;
578 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 579 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 580 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
581 struct drm_display_mode *mode;
42e67c3b
RL		 582 unsigned long max_size = 0;
583
584 if (adev->dm.dc->fbc_compressor == NULL)
585 return;
a32e24b4 586
3e332d3a 587 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 588 return;
589
3e332d3a
RL		 590 if (compressor->bo_ptr)
591 return;
42e67c3b 592
42e67c3b 593
3e332d3a
RL		 594 list_for_each_entry(mode, &connector->modes, head) {
595 if (max_size < mode->htotal * mode->vtotal)
596 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 597 }
598
599 if (max_size) {
600 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 601 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 602 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 603
604 if (r)
42e67c3b
RL		 605 DRM_ERROR("DM: Failed to initialize FBC\n");
606 else {
607 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
608 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
609 }
610
a32e24b4
RL		 611 }
612
613}
a32e24b4 614
6ce8f316
NK		 615static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
616 int pipe, bool *enabled,
617 unsigned char *buf, int max_bytes)
618{
619 struct drm_device *dev = dev_get_drvdata(kdev);
620 struct amdgpu_device *adev = dev->dev_private;
621 struct drm_connector *connector;
622 struct drm_connector_list_iter conn_iter;
623 struct amdgpu_dm_connector *aconnector;
624 int ret = 0;
625
626 *enabled = false;
627
628 mutex_lock(&adev->dm.audio_lock);
629
630 drm_connector_list_iter_begin(dev, &conn_iter);
631 drm_for_each_connector_iter(connector, &conn_iter) {
632 aconnector = to_amdgpu_dm_connector(connector);
633 if (aconnector->audio_inst != port)
634 continue;
635
636 *enabled = true;
637 ret = drm_eld_size(connector->eld);
638 memcpy(buf, connector->eld, min(max_bytes, ret));
639
640 break;
641 }
642 drm_connector_list_iter_end(&conn_iter);
643
644 mutex_unlock(&adev->dm.audio_lock);
645
646 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
647
648 return ret;
649}
650
651static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
652 .get_eld = amdgpu_dm_audio_component_get_eld,
653};
654
655static int amdgpu_dm_audio_component_bind(struct device *kdev,
656 struct device *hda_kdev, void *data)
657{
658 struct drm_device *dev = dev_get_drvdata(kdev);
659 struct amdgpu_device *adev = dev->dev_private;
660 struct drm_audio_component *acomp = data;
661
662 acomp->ops = &amdgpu_dm_audio_component_ops;
663 acomp->dev = kdev;
664 adev->dm.audio_component = acomp;
665
666 return 0;
667}
668
669static void amdgpu_dm_audio_component_unbind(struct device *kdev,
670 struct device *hda_kdev, void *data)
671{
672 struct drm_device *dev = dev_get_drvdata(kdev);
673 struct amdgpu_device *adev = dev->dev_private;
674 struct drm_audio_component *acomp = data;
675
676 acomp->ops = NULL;
677 acomp->dev = NULL;
678 adev->dm.audio_component = NULL;
679}
680
681static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
682 .bind = amdgpu_dm_audio_component_bind,
683 .unbind = amdgpu_dm_audio_component_unbind,
684};
685
686static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
687{
688 int i, ret;
689
690 if (!amdgpu_audio)
691 return 0;
692
693 adev->mode_info.audio.enabled = true;
694
695 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
696
697 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
698 adev->mode_info.audio.pin[i].channels = -1;
699 adev->mode_info.audio.pin[i].rate = -1;
700 adev->mode_info.audio.pin[i].bits_per_sample = -1;
701 adev->mode_info.audio.pin[i].status_bits = 0;
702 adev->mode_info.audio.pin[i].category_code = 0;
703 adev->mode_info.audio.pin[i].connected = false;
704 adev->mode_info.audio.pin[i].id =
705 adev->dm.dc->res_pool->audios[i]->inst;
706 adev->mode_info.audio.pin[i].offset = 0;
707 }
708
709 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
710 if (ret < 0)
711 return ret;
712
713 adev->dm.audio_registered = true;
714
715 return 0;
716}
717
718static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
719{
720 if (!amdgpu_audio)
721 return;
722
723 if (!adev->mode_info.audio.enabled)
724 return;
725
726 if (adev->dm.audio_registered) {
727 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
728 adev->dm.audio_registered = false;
729 }
730
731 /* TODO: Disable audio? */
732
733 adev->mode_info.audio.enabled = false;
734}
735
736void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
737{
738 struct drm_audio_component *acomp = adev->dm.audio_component;
739
740 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
741 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
742
743 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
744 pin, -1);
745 }
746}
747
743b9786
NK		 748static int dm_dmub_hw_init(struct amdgpu_device *adev)
749{
743b9786
NK		 750 const struct dmcub_firmware_header_v1_0 *hdr;
751 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
8c7aea40 752 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
743b9786
NK		 753 const struct firmware *dmub_fw = adev->dm.dmub_fw;
754 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
755 struct abm *abm = adev->dm.dc->res_pool->abm;
743b9786
NK		 756 struct dmub_srv_hw_params hw_params;
757 enum dmub_status status;
758 const unsigned char *fw_inst_const, *fw_bss_data;
8c7aea40 759 uint32_t i, fw_inst_const_size, fw_bss_data_size;
743b9786
NK		 760 bool has_hw_support;
761
762 if (!dmub_srv)
763 /* DMUB isn't supported on the ASIC. */
764 return 0;
765
8c7aea40
NK		 766 if (!fb_info) {
767 DRM_ERROR("No framebuffer info for DMUB service.\n");
768 return -EINVAL;
769 }
770
743b9786
NK		 771 if (!dmub_fw) {
772 /* Firmware required for DMUB support. */
773 DRM_ERROR("No firmware provided for DMUB.\n");
774 return -EINVAL;
775 }
776
777 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
778 if (status != DMUB_STATUS_OK) {
779 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
780 return -EINVAL;
781 }
782
783 if (!has_hw_support) {
784 DRM_INFO("DMUB unsupported on ASIC\n");
785 return 0;
786 }
787
788 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
789
743b9786
NK		 790 fw_inst_const = dmub_fw->data +
791 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
8c7aea40 792 PSP_HEADER_BYTES;
743b9786
NK		 793
794 fw_bss_data = dmub_fw->data +
795 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
796 le32_to_cpu(hdr->inst_const_bytes);
797
798 /* Copy firmware and bios info into FB memory. */
8c7aea40
NK		 799 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
800 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
801
802 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
803
804 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
805 fw_inst_const_size);
806 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, fw_bss_data,
807 fw_bss_data_size);
808 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
809 adev->bios_size);
810
811 /* Reset regions that need to be reset. */
812 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
813 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
814
815 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
816 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
817
818 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
819 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
743b9786
NK		 820
821 /* Initialize hardware. */
822 memset(&hw_params, 0, sizeof(hw_params));
823 hw_params.fb_base = adev->gmc.fb_start;
824 hw_params.fb_offset = adev->gmc.aper_base;
825
826 if (dmcu)
827 hw_params.psp_version = dmcu->psp_version;
828
8c7aea40
NK		 829 for (i = 0; i < fb_info->num_fb; ++i)
830 hw_params.fb[i] = &fb_info->fb[i];
743b9786
NK		 831
832 status = dmub_srv_hw_init(dmub_srv, &hw_params);
833 if (status != DMUB_STATUS_OK) {
834 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
835 return -EINVAL;
836 }
837
838 /* Wait for firmware load to finish. */
839 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
840 if (status != DMUB_STATUS_OK)
841 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
842
843 /* Init DMCU and ABM if available. */
844 if (dmcu && abm) {
845 dmcu->funcs->dmcu_init(dmcu);
846 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
847 }
848
9a71c7d3
NK		 849 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
850 if (!adev->dm.dc->ctx->dmub_srv) {
851 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
852 return -ENOMEM;
853 }
854
743b9786
NK		 855 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
856 adev->dm.dmcub_fw_version);
857
858 return 0;
859}
860
7578ecda 861static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 862{
863 struct dc_init_data init_data;
52704fca
BL		 864#ifdef CONFIG_DRM_AMD_DC_HDCP
865 struct dc_callback_init init_params;
866#endif
743b9786 867 int r;
52704fca 868
4562236b
HW		 869 adev->dm.ddev = adev->ddev;
870 adev->dm.adev = adev;
871
4562236b
HW		 872 /* Zero all the fields */
873 memset(&init_data, 0, sizeof(init_data));
52704fca
BL		 874#ifdef CONFIG_DRM_AMD_DC_HDCP
875 memset(&init_params, 0, sizeof(init_params));
876#endif
4562236b 877
674e78ac 878 mutex_init(&adev->dm.dc_lock);
6ce8f316 879 mutex_init(&adev->dm.audio_lock);
674e78ac 880
4562236b
HW		 881 if(amdgpu_dm_irq_init(adev)) {
882 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
883 goto error;
884 }
885
886 init_data.asic_id.chip_family = adev->family;
887
888 init_data.asic_id.pci_revision_id = adev->rev_id;
889 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
890
770d13b1 891 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 892 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
893 init_data.asic_id.atombios_base_address =
894 adev->mode_info.atom_context->bios;
895
896 init_data.driver = adev;
897
898 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
899
900 if (!adev->dm.cgs_device) {
901 DRM_ERROR("amdgpu: failed to create cgs device.\n");
902 goto error;
903 }
904
905 init_data.cgs_device = adev->dm.cgs_device;
906
4562236b
HW		 907 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
908
6e227308
HW		 909 /*
910 * TODO debug why this doesn't work on Raven
911 */
912 if (adev->flags & AMD_IS_APU &&
913 adev->asic_type >= CHIP_CARRIZO &&
5e18d2b1 914 adev->asic_type < CHIP_RAVEN)
6e227308
HW		 915 init_data.flags.gpu_vm_support = true;
916
04b94af4
AD		 917 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
918 init_data.flags.fbc_support = true;
919
d99f38ae
AD		 920 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
921 init_data.flags.multi_mon_pp_mclk_switch = true;
922
eaf56410
LL		 923 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
924 init_data.flags.disable_fractional_pwm = true;
925
27eaa492 926 init_data.flags.power_down_display_on_boot = true;
78ad75f8 927
48321c3d 928 init_data.soc_bounding_box = adev->dm.soc_bounding_box;
27eaa492 929
4562236b
HW		 930 /* Display Core create. */
931 adev->dm.dc = dc_create(&init_data);
932
423788c7 933 if (adev->dm.dc) {
76121231 934 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 935 } else {
76121231 936 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 937 goto error;
938 }
4562236b 939
98bf2f52
JP		 940 dc_hardware_init(adev->dm.dc);
941
743b9786
NK		 942 r = dm_dmub_hw_init(adev);
943 if (r) {
944 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
945 goto error;
946 }
947
4562236b
HW		 948 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
949 if (!adev->dm.freesync_module) {
950 DRM_ERROR(
951 "amdgpu: failed to initialize freesync_module.\n");
952 } else
f1ad2f5e 953 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 954 adev->dm.freesync_module);
955
e277adc5
LSL		 956 amdgpu_dm_init_color_mod();
957
52704fca 958#ifdef CONFIG_DRM_AMD_DC_HDCP
96a3b32e
BL		 959 if (adev->asic_type >= CHIP_RAVEN) {
960 adev->dm.hdcp_workqueue = hdcp_create_workqueue(&adev->psp, &init_params.cp_psp, adev->dm.dc);
52704fca 961
96a3b32e
BL		 962 if (!adev->dm.hdcp_workqueue)
963 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
964 else
965 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
52704fca 966
96a3b32e
BL		 967 dc_init_callbacks(adev->dm.dc, &init_params);
968 }
52704fca 969#endif
4562236b
HW		 970 if (amdgpu_dm_initialize_drm_device(adev)) {
971 DRM_ERROR(
972 "amdgpu: failed to initialize sw for display support.\n");
973 goto error;
974 }
975
976 /* Update the actual used number of crtc */
977 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
978
979 /* TODO: Add_display_info? */
980
981 /* TODO use dynamic cursor width */
ce75805e
AG		 982 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
983 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 984
985 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
986 DRM_ERROR(
987 "amdgpu: failed to initialize sw for display support.\n");
988 goto error;
989 }
990
e498eb71
NK		 991#if defined(CONFIG_DEBUG_FS)
992 if (dtn_debugfs_init(adev))
993 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
994#endif
995
f1ad2f5e 996 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 997
998 return 0;
999error:
1000 amdgpu_dm_fini(adev);
1001
59d0f396 1002 return -EINVAL;
4562236b
HW		 1003}
1004
7578ecda 1005static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b 1006{
6ce8f316
NK		 1007 amdgpu_dm_audio_fini(adev);
1008
4562236b 1009 amdgpu_dm_destroy_drm_device(&adev->dm);
c8bdf2b6 1010
52704fca
BL		 1011#ifdef CONFIG_DRM_AMD_DC_HDCP
1012 if (adev->dm.hdcp_workqueue) {
1013 hdcp_destroy(adev->dm.hdcp_workqueue);
1014 adev->dm.hdcp_workqueue = NULL;
1015 }
1016
1017 if (adev->dm.dc)
1018 dc_deinit_callbacks(adev->dm.dc);
1019#endif
9a71c7d3
NK		 1020 if (adev->dm.dc->ctx->dmub_srv) {
1021 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1022 adev->dm.dc->ctx->dmub_srv = NULL;
1023 }
1024
743b9786
NK		 1025 if (adev->dm.dmub_bo)
1026 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1027 &adev->dm.dmub_bo_gpu_addr,
1028 &adev->dm.dmub_bo_cpu_addr);
52704fca 1029
c8bdf2b6
ED		 1030 /* DC Destroy TODO: Replace destroy DAL */
1031 if (adev->dm.dc)
1032 dc_destroy(&adev->dm.dc);
4562236b
HW		 1033 /*
1034 * TODO: pageflip, vlank interrupt
1035 *
1036 * amdgpu_dm_irq_fini(adev);
1037 */
1038
1039 if (adev->dm.cgs_device) {
1040 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1041 adev->dm.cgs_device = NULL;
1042 }
1043 if (adev->dm.freesync_module) {
1044 mod_freesync_destroy(adev->dm.freesync_module);
1045 adev->dm.freesync_module = NULL;
1046 }
674e78ac 1047
6ce8f316 1048 mutex_destroy(&adev->dm.audio_lock);
674e78ac
NK		 1049 mutex_destroy(&adev->dm.dc_lock);
1050
4562236b
HW		 1051 return;
1052}
1053
a94d5569 1054static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 1055{
a7669aff 1056 const char *fw_name_dmcu = NULL;
a94d5569
DF		 1057 int r;
1058 const struct dmcu_firmware_header_v1_0 *hdr;
1059
1060 switch(adev->asic_type) {
1061 case CHIP_BONAIRE:
1062 case CHIP_HAWAII:
1063 case CHIP_KAVERI:
1064 case CHIP_KABINI:
1065 case CHIP_MULLINS:
1066 case CHIP_TONGA:
1067 case CHIP_FIJI:
1068 case CHIP_CARRIZO:
1069 case CHIP_STONEY:
1070 case CHIP_POLARIS11:
1071 case CHIP_POLARIS10:
1072 case CHIP_POLARIS12:
1073 case CHIP_VEGAM:
1074 case CHIP_VEGA10:
1075 case CHIP_VEGA12:
1076 case CHIP_VEGA20:
476e955d 1077 case CHIP_NAVI10:
baebcf2e 1078 case CHIP_NAVI14:
fbd2afe5 1079 case CHIP_NAVI12:
30221ad8 1080 case CHIP_RENOIR:
a94d5569
DF		 1081 return 0;
1082 case CHIP_RAVEN:
a7669aff
HW		 1083 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1084 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1085 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1086 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1087 else
a7669aff 1088 return 0;
a94d5569
DF		 1089 break;
1090 default:
1091 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 1092 return -EINVAL;
a94d5569
DF		 1093 }
1094
1095 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1096 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1097 return 0;
1098 }
1099
1100 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1101 if (r == -ENOENT) {
1102 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1103 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1104 adev->dm.fw_dmcu = NULL;
1105 return 0;
1106 }
1107 if (r) {
1108 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1109 fw_name_dmcu);
1110 return r;
1111 }
1112
1113 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1114 if (r) {
1115 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1116 fw_name_dmcu);
1117 release_firmware(adev->dm.fw_dmcu);
1118 adev->dm.fw_dmcu = NULL;
1119 return r;
1120 }
1121
1122 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1123 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1124 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1125 adev->firmware.fw_size +=
1126 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1127
1128 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1129 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1130 adev->firmware.fw_size +=
1131 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1132
ee6e89c0
DF		 1133 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1134
a94d5569
DF		 1135 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1136
4562236b
HW		 1137 return 0;
1138}
1139
743b9786
NK		 1140static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1141{
1142 struct amdgpu_device *adev = ctx;
1143
1144 return dm_read_reg(adev->dm.dc->ctx, address);
1145}
1146
1147static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1148 uint32_t value)
1149{
1150 struct amdgpu_device *adev = ctx;
1151
1152 return dm_write_reg(adev->dm.dc->ctx, address, value);
1153}
1154
1155static int dm_dmub_sw_init(struct amdgpu_device *adev)
1156{
1157 struct dmub_srv_create_params create_params;
8c7aea40
NK		 1158 struct dmub_srv_region_params region_params;
1159 struct dmub_srv_region_info region_info;
1160 struct dmub_srv_fb_params fb_params;
1161 struct dmub_srv_fb_info *fb_info;
1162 struct dmub_srv *dmub_srv;
743b9786
NK		 1163 const struct dmcub_firmware_header_v1_0 *hdr;
1164 const char *fw_name_dmub;
1165 enum dmub_asic dmub_asic;
1166 enum dmub_status status;
1167 int r;
1168
1169 switch (adev->asic_type) {
1170 case CHIP_RENOIR:
1171 dmub_asic = DMUB_ASIC_DCN21;
1172 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1173 break;
1174
1175 default:
1176 /* ASIC doesn't support DMUB. */
1177 return 0;
1178 }
1179
743b9786
NK		 1180 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1181 if (r) {
1182 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1183 return 0;
1184 }
1185
1186 r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1187 if (r) {
1188 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1189 return 0;
1190 }
1191
1192 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1193 DRM_WARN("Only PSP firmware loading is supported for DMUB\n");
1194 return 0;
1195 }
1196
1197 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1198 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1199 AMDGPU_UCODE_ID_DMCUB;
1200 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = adev->dm.dmub_fw;
1201 adev->firmware.fw_size +=
1202 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1203
1204 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1205
1206 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1207 adev->dm.dmcub_fw_version);
1208
8c7aea40
NK		 1209 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1210 dmub_srv = adev->dm.dmub_srv;
1211
1212 if (!dmub_srv) {
1213 DRM_ERROR("Failed to allocate DMUB service!\n");
1214 return -ENOMEM;
1215 }
1216
1217 memset(&create_params, 0, sizeof(create_params));
1218 create_params.user_ctx = adev;
1219 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1220 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1221 create_params.asic = dmub_asic;
1222
1223 /* Create the DMUB service. */
1224 status = dmub_srv_create(dmub_srv, &create_params);
1225 if (status != DMUB_STATUS_OK) {
1226 DRM_ERROR("Error creating DMUB service: %d\n", status);
1227 return -EINVAL;
1228 }
1229
1230 /* Calculate the size of all the regions for the DMUB service. */
1231 memset(&region_params, 0, sizeof(region_params));
1232
1233 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1234 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1235 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1236 region_params.vbios_size = adev->bios_size;
1f0674fd
NK		 1237 region_params.fw_bss_data =
1238 adev->dm.dmub_fw->data +
1239 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1240 le32_to_cpu(hdr->inst_const_bytes);
8c7aea40
NK		 1241
1242 status = dmub_srv_calc_region_info(dmub_srv, &region_params,
1243 &region_info);
1244
1245 if (status != DMUB_STATUS_OK) {
1246 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
1247 return -EINVAL;
1248 }
1249
1250 /*
1251 * Allocate a framebuffer based on the total size of all the regions.
1252 * TODO: Move this into GART.
1253 */
1254 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
1255 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
1256 &adev->dm.dmub_bo_gpu_addr,
1257 &adev->dm.dmub_bo_cpu_addr);
1258 if (r)
1259 return r;
1260
1261 /* Rebase the regions on the framebuffer address. */
1262 memset(&fb_params, 0, sizeof(fb_params));
1263 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
1264 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
1265 fb_params.region_info = &region_info;
1266
1267 adev->dm.dmub_fb_info =
1268 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
1269 fb_info = adev->dm.dmub_fb_info;
1270
1271 if (!fb_info) {
1272 DRM_ERROR(
1273 "Failed to allocate framebuffer info for DMUB service!\n");
1274 return -ENOMEM;
1275 }
1276
1277 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
1278 if (status != DMUB_STATUS_OK) {
1279 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
1280 return -EINVAL;
1281 }
1282
743b9786
NK		 1283 return 0;
1284}
1285
a94d5569
DF		 1286static int dm_sw_init(void *handle)
1287{
1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743b9786
NK		 1289 int r;
1290
1291 r = dm_dmub_sw_init(adev);
1292 if (r)
1293 return r;
a94d5569
DF		 1294
1295 return load_dmcu_fw(adev);
1296}
1297
4562236b
HW		 1298static int dm_sw_fini(void *handle)
1299{
a94d5569
DF		 1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301
8c7aea40
NK		 1302 kfree(adev->dm.dmub_fb_info);
1303 adev->dm.dmub_fb_info = NULL;
1304
743b9786
NK		 1305 if (adev->dm.dmub_srv) {
1306 dmub_srv_destroy(adev->dm.dmub_srv);
1307 adev->dm.dmub_srv = NULL;
1308 }
1309
1310 if (adev->dm.dmub_fw) {
1311 release_firmware(adev->dm.dmub_fw);
1312 adev->dm.dmub_fw = NULL;
1313 }
1314
a94d5569
DF		 1315 if(adev->dm.fw_dmcu) {
1316 release_firmware(adev->dm.fw_dmcu);
1317 adev->dm.fw_dmcu = NULL;
1318 }
1319
4562236b
HW		 1320 return 0;
1321}
1322
7abcf6b5 1323static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 1324{
c84dec2f 1325 struct amdgpu_dm_connector *aconnector;
4562236b 1326 struct drm_connector *connector;
f8d2d39e 1327 struct drm_connector_list_iter iter;
7abcf6b5 1328 int ret = 0;
4562236b 1329
f8d2d39e
LP		 1330 drm_connector_list_iter_begin(dev, &iter);
1331 drm_for_each_connector_iter(connector, &iter) {
b349f76e 1332 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 1333 if (aconnector->dc_link->type == dc_connection_mst_branch &&
1334 aconnector->mst_mgr.aux) {
f1ad2f5e 1335 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
f8d2d39e
LP		 1336 aconnector,
1337 aconnector->base.base.id);
7abcf6b5
AG		 1338
1339 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
1340 if (ret < 0) {
1341 DRM_ERROR("DM_MST: Failed to start MST\n");
f8d2d39e
LP		 1342 aconnector->dc_link->type =
1343 dc_connection_single;
1344 break;
7abcf6b5 1345 }
f8d2d39e 1346 }
4562236b 1347 }
f8d2d39e 1348 drm_connector_list_iter_end(&iter);
4562236b 1349
7abcf6b5
AG		 1350 return ret;
1351}
1352
1353static int dm_late_init(void *handle)
1354{
42e67c3b 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 1356
bbf854dc
DF		 1357 struct dmcu_iram_parameters params;
1358 unsigned int linear_lut[16];
1359 int i;
1360 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
96cb7cf1 1361 bool ret = false;
bbf854dc
DF		 1362
1363 for (i = 0; i < 16; i++)
1364 linear_lut[i] = 0xFFFF * i / 15;
1365
1366 params.set = 0;
1367 params.backlight_ramping_start = 0xCCCC;
1368 params.backlight_ramping_reduction = 0xCCCCCCCC;
1369 params.backlight_lut_array_size = 16;
1370 params.backlight_lut_array = linear_lut;
1371
2ad0cdf9
AK		 1372 /* Min backlight level after ABM reduction, Don't allow below 1%
1373 * 0xFFFF x 0.01 = 0x28F
1374 */
1375 params.min_abm_backlight = 0x28F;
1376
96cb7cf1 1377 /* todo will enable for navi10 */
1378 if (adev->asic_type <= CHIP_RAVEN) {
1379 ret = dmcu_load_iram(dmcu, params);
bbf854dc 1380
96cb7cf1 1381 if (!ret)
1382 return -EINVAL;
1383 }
bbf854dc 1384
42e67c3b 1385 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 1386}
1387
1388static void s3_handle_mst(struct drm_device *dev, bool suspend)
1389{
c84dec2f 1390 struct amdgpu_dm_connector *aconnector;
4562236b 1391 struct drm_connector *connector;
f8d2d39e 1392 struct drm_connector_list_iter iter;
fe7553be
LP		 1393 struct drm_dp_mst_topology_mgr *mgr;
1394 int ret;
1395 bool need_hotplug = false;
4562236b 1396
f8d2d39e
LP		 1397 drm_connector_list_iter_begin(dev, &iter);
1398 drm_for_each_connector_iter(connector, &iter) {
fe7553be
LP		 1399 aconnector = to_amdgpu_dm_connector(connector);
1400 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1401 aconnector->mst_port)
1402 continue;
1403
1404 mgr = &aconnector->mst_mgr;
1405
1406 if (suspend) {
1407 drm_dp_mst_topology_mgr_suspend(mgr);
1408 } else {
6f85f738 1409 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
fe7553be
LP		 1410 if (ret < 0) {
1411 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1412 need_hotplug = true;
1413 }
1414 }
4562236b 1415 }
f8d2d39e 1416 drm_connector_list_iter_end(&iter);
fe7553be
LP		 1417
1418 if (need_hotplug)
1419 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 1420}
1421
b8592b48
LL		 1422/**
1423 * dm_hw_init() - Initialize DC device
28d687ea 1424 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 1425 *
1426 * Initialize the &struct amdgpu_display_manager device. This involves calling
1427 * the initializers of each DM component, then populating the struct with them.
1428 *
1429 * Although the function implies hardware initialization, both hardware and
1430 * software are initialized here. Splitting them out to their relevant init
1431 * hooks is a future TODO item.
1432 *
1433 * Some notable things that are initialized here:
1434 *
1435 * - Display Core, both software and hardware
1436 * - DC modules that we need (freesync and color management)
1437 * - DRM software states
1438 * - Interrupt sources and handlers
1439 * - Vblank support
1440 * - Debug FS entries, if enabled
1441 */
4562236b
HW		 1442static int dm_hw_init(void *handle)
1443{
1444 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445 /* Create DAL display manager */
1446 amdgpu_dm_init(adev);
4562236b
HW		 1447 amdgpu_dm_hpd_init(adev);
1448
4562236b
HW		 1449 return 0;
1450}
1451
b8592b48
LL		 1452/**
1453 * dm_hw_fini() - Teardown DC device
28d687ea 1454 * @handle: The base driver device containing the amdgpu_dm device.
b8592b48
LL		 1455 *
1456 * Teardown components within &struct amdgpu_display_manager that require
1457 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1458 * were loaded. Also flush IRQ workqueues and disable them.
1459 */
4562236b
HW		 1460static int dm_hw_fini(void *handle)
1461{
1462 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463
1464 amdgpu_dm_hpd_fini(adev);
1465
1466 amdgpu_dm_irq_fini(adev);
21de3396 1467 amdgpu_dm_fini(adev);
4562236b
HW		 1468 return 0;
1469}
1470
1471static int dm_suspend(void *handle)
1472{
1473 struct amdgpu_device *adev = handle;
1474 struct amdgpu_display_manager *dm = &adev->dm;
1475 int ret = 0;
4562236b 1476
d2f0b53b
LHM		 1477 WARN_ON(adev->dm.cached_state);
1478 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1479
4562236b
HW		 1480 s3_handle_mst(adev->ddev, true);
1481
4562236b
HW		 1482 amdgpu_dm_irq_suspend(adev);
1483
a3621485 1484
32f5062d 1485 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 1486
1487 return ret;
1488}
1489
1daf8c63
AD		 1490static struct amdgpu_dm_connector *
1491amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1492 struct drm_crtc *crtc)
4562236b
HW		 1493{
1494 uint32_t i;
c2cea706 1495 struct drm_connector_state *new_con_state;
4562236b
HW		 1496 struct drm_connector *connector;
1497 struct drm_crtc *crtc_from_state;
1498
c2cea706
LSL		 1499 for_each_new_connector_in_state(state, connector, new_con_state, i) {
1500 crtc_from_state = new_con_state->crtc;
4562236b
HW		 1501
1502 if (crtc_from_state == crtc)
c84dec2f 1503 return to_amdgpu_dm_connector(connector);
4562236b
HW		 1504 }
1505
1506 return NULL;
1507}
1508
fbbdadf2
BL		 1509static void emulated_link_detect(struct dc_link *link)
1510{
1511 struct dc_sink_init_data sink_init_data = { 0 };
1512 struct display_sink_capability sink_caps = { 0 };
1513 enum dc_edid_status edid_status;
1514 struct dc_context *dc_ctx = link->ctx;
1515 struct dc_sink *sink = NULL;
1516 struct dc_sink *prev_sink = NULL;
1517
1518 link->type = dc_connection_none;
1519 prev_sink = link->local_sink;
1520
1521 if (prev_sink != NULL)
1522 dc_sink_retain(prev_sink);
1523
1524 switch (link->connector_signal) {
1525 case SIGNAL_TYPE_HDMI_TYPE_A: {
1526 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1527 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1528 break;
1529 }
1530
1531 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1532 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1533 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1534 break;
1535 }
1536
1537 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1538 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1539 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1540 break;
1541 }
1542
1543 case SIGNAL_TYPE_LVDS: {
1544 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1545 sink_caps.signal = SIGNAL_TYPE_LVDS;
1546 break;
1547 }
1548
1549 case SIGNAL_TYPE_EDP: {
1550 sink_caps.transaction_type =
1551 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1552 sink_caps.signal = SIGNAL_TYPE_EDP;
1553 break;
1554 }
1555
1556 case SIGNAL_TYPE_DISPLAY_PORT: {
1557 sink_caps.transaction_type =
1558 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1559 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1560 break;
1561 }
1562
1563 default:
1564 DC_ERROR("Invalid connector type! signal:%d\n",
1565 link->connector_signal);
1566 return;
1567 }
1568
1569 sink_init_data.link = link;
1570 sink_init_data.sink_signal = sink_caps.signal;
1571
1572 sink = dc_sink_create(&sink_init_data);
1573 if (!sink) {
1574 DC_ERROR("Failed to create sink!\n");
1575 return;
1576 }
1577
dcd5fb82 1578 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 1579 link->local_sink = sink;
1580
1581 edid_status = dm_helpers_read_local_edid(
1582 link->ctx,
1583 link,
1584 sink);
1585
1586 if (edid_status != EDID_OK)
1587 DC_ERROR("Failed to read EDID");
1588
1589}
1590
4562236b
HW		 1591static int dm_resume(void *handle)
1592{
1593 struct amdgpu_device *adev = handle;
4562236b
HW		 1594 struct drm_device *ddev = adev->ddev;
1595 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 1596 struct amdgpu_dm_connector *aconnector;
4562236b 1597 struct drm_connector *connector;
f8d2d39e 1598 struct drm_connector_list_iter iter;
4562236b 1599 struct drm_crtc *crtc;
c2cea706 1600 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 1601 struct dm_crtc_state *dm_new_crtc_state;
1602 struct drm_plane *plane;
1603 struct drm_plane_state *new_plane_state;
1604 struct dm_plane_state *dm_new_plane_state;
113b7a01 1605 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
fbbdadf2 1606 enum dc_connection_type new_connection_type = dc_connection_none;
8c7aea40 1607 int i, r;
4562236b 1608
113b7a01
LL		 1609 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1610 dc_release_state(dm_state->context);
1611 dm_state->context = dc_create_state(dm->dc);
1612 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1613 dc_resource_state_construct(dm->dc, dm_state->context);
1614
8c7aea40
NK		 1615 /* Before powering on DC we need to re-initialize DMUB. */
1616 r = dm_dmub_hw_init(adev);
1617 if (r)
1618 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1619
a80aa93d
ML		 1620 /* power on hardware */
1621 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1622
4562236b
HW		 1623 /* program HPD filter */
1624 dc_resume(dm->dc);
1625
4562236b
HW		 1626 /*
1627 * early enable HPD Rx IRQ, should be done before set mode as short
1628 * pulse interrupts are used for MST
1629 */
1630 amdgpu_dm_irq_resume_early(adev);
1631
d20ebea8 1632 /* On resume we need to rewrite the MSTM control bits to enable MST*/
684cd480
LP		 1633 s3_handle_mst(ddev, false);
1634
4562236b 1635 /* Do detection*/
f8d2d39e
LP		 1636 drm_connector_list_iter_begin(ddev, &iter);
1637 drm_for_each_connector_iter(connector, &iter) {
c84dec2f 1638 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1639
1640 /*
1641 * this is the case when traversing through already created
1642 * MST connectors, should be skipped
1643 */
1644 if (aconnector->mst_port)
1645 continue;
1646
03ea364c 1647 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 1648 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1649 DRM_ERROR("KMS: Failed to detect connector\n");
1650
1651 if (aconnector->base.force && new_connection_type == dc_connection_none)
1652 emulated_link_detect(aconnector->dc_link);
1653 else
1654 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 1655
1656 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1657 aconnector->fake_enable = false;
1658
dcd5fb82
MF		 1659 if (aconnector->dc_sink)
1660 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 1661 aconnector->dc_sink = NULL;
1662 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 1663 mutex_unlock(&aconnector->hpd_lock);
4562236b 1664 }
f8d2d39e 1665 drm_connector_list_iter_end(&iter);
4562236b 1666
1f6010a9 1667 /* Force mode set in atomic commit */
a80aa93d 1668 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 1669 new_crtc_state->active_changed = true;
4f346e65 1670
fcb4019e
LSL		 1671 /*
1672 * atomic_check is expected to create the dc states. We need to release
1673 * them here, since they were duplicated as part of the suspend
1674 * procedure.
1675 */
a80aa93d 1676 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 1677 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1678 if (dm_new_crtc_state->stream) {
1679 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1680 dc_stream_release(dm_new_crtc_state->stream);
1681 dm_new_crtc_state->stream = NULL;
1682 }
1683 }
1684
a80aa93d 1685 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 1686 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1687 if (dm_new_plane_state->dc_state) {
1688 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1689 dc_plane_state_release(dm_new_plane_state->dc_state);
1690 dm_new_plane_state->dc_state = NULL;
1691 }
1692 }
1693
2d1af6a1 1694 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 1695
a80aa93d 1696 dm->cached_state = NULL;
0a214e2f 1697
9faa4237 1698 amdgpu_dm_irq_resume_late(adev);
4562236b 1699
2d1af6a1 1700 return 0;
4562236b
HW		 1701}
1702
b8592b48
LL		 1703/**
1704 * DOC: DM Lifecycle
1705 *
1706 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1707 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1708 * the base driver's device list to be initialized and torn down accordingly.
1709 *
1710 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1711 */
1712
4562236b
HW		 1713static const struct amd_ip_funcs amdgpu_dm_funcs = {
1714 .name = "dm",
1715 .early_init = dm_early_init,
7abcf6b5 1716 .late_init = dm_late_init,
4562236b
HW		 1717 .sw_init = dm_sw_init,
1718 .sw_fini = dm_sw_fini,
1719 .hw_init = dm_hw_init,
1720 .hw_fini = dm_hw_fini,
1721 .suspend = dm_suspend,
1722 .resume = dm_resume,
1723 .is_idle = dm_is_idle,
1724 .wait_for_idle = dm_wait_for_idle,
1725 .check_soft_reset = dm_check_soft_reset,
1726 .soft_reset = dm_soft_reset,
1727 .set_clockgating_state = dm_set_clockgating_state,
1728 .set_powergating_state = dm_set_powergating_state,
1729};
1730
1731const struct amdgpu_ip_block_version dm_ip_block =
1732{
1733 .type = AMD_IP_BLOCK_TYPE_DCE,
1734 .major = 1,
1735 .minor = 0,
1736 .rev = 0,
1737 .funcs = &amdgpu_dm_funcs,
1738};
1739
ca3268c4 1740
b8592b48
LL		 1741/**
1742 * DOC: atomic
1743 *
1744 * *WIP*
1745 */
0a323b84 1746
b3663f70 1747static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1748 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1749 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1750 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1751 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1752};
1753
1754static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1755 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1756};
1757
7578ecda 1758static void
3ee6b26b 1759amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1760{
1761 struct drm_connector *connector = &aconnector->base;
1762 struct drm_device *dev = connector->dev;
b73a22d3 1763 struct dc_sink *sink;
4562236b
HW		 1764
1765 /* MST handled by drm_mst framework */
1766 if (aconnector->mst_mgr.mst_state == true)
1767 return;
1768
1769
1770 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 1771 if (sink)
1772 dc_sink_retain(sink);
4562236b 1773
1f6010a9
DF		 1774 /*
1775 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1776 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1777 * Skip if already done during boot.
4562236b
HW		 1778 */
1779 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1780 && aconnector->dc_em_sink) {
1781
1f6010a9
DF		 1782 /*
1783 * For S3 resume with headless use eml_sink to fake stream
1784 * because on resume connector->sink is set to NULL
4562236b
HW		 1785 */
1786 mutex_lock(&dev->mode_config.mutex);
1787
1788 if (sink) {
922aa1e1 1789 if (aconnector->dc_sink) {
98e6436d 1790 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1791 /*
1792 * retain and release below are used to
1793 * bump up refcount for sink because the link doesn't point
1794 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1795 * reshuffle by UMD we will get into unwanted dc_sink release
1796 */
dcd5fb82 1797 dc_sink_release(aconnector->dc_sink);
922aa1e1 1798 }
4562236b 1799 aconnector->dc_sink = sink;
dcd5fb82 1800 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 1801 amdgpu_dm_update_freesync_caps(connector,
1802 aconnector->edid);
4562236b 1803 } else {
98e6436d 1804 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 1805 if (!aconnector->dc_sink) {
4562236b 1806 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 1807 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 1808 }
4562236b
HW		 1809 }
1810
1811 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1812
1813 if (sink)
1814 dc_sink_release(sink);
4562236b
HW		 1815 return;
1816 }
1817
1818 /*
1819 * TODO: temporary guard to look for proper fix
1820 * if this sink is MST sink, we should not do anything
1821 */
dcd5fb82
MF		 1822 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1823 dc_sink_release(sink);
4562236b 1824 return;
dcd5fb82 1825 }
4562236b
HW		 1826
1827 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1828 /*
1829 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1830 * Do nothing!!
1831 */
f1ad2f5e 1832 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 1833 aconnector->connector_id);
dcd5fb82
MF		 1834 if (sink)
1835 dc_sink_release(sink);
4562236b
HW		 1836 return;
1837 }
1838
f1ad2f5e 1839 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1840 aconnector->connector_id, aconnector->dc_sink, sink);
1841
1842 mutex_lock(&dev->mode_config.mutex);
1843
1f6010a9
DF		 1844 /*
1845 * 1. Update status of the drm connector
1846 * 2. Send an event and let userspace tell us what to do
1847 */
4562236b 1848 if (sink) {
1f6010a9
DF		 1849 /*
1850 * TODO: check if we still need the S3 mode update workaround.
1851 * If yes, put it here.
1852 */
4562236b 1853 if (aconnector->dc_sink)
98e6436d 1854 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1855
1856 aconnector->dc_sink = sink;
dcd5fb82 1857 dc_sink_retain(aconnector->dc_sink);
900b3cb1 1858 if (sink->dc_edid.length == 0) {
4562236b 1859 aconnector->edid = NULL;
e86e8947 1860 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1861 } else {
4562236b
HW		 1862 aconnector->edid =
1863 (struct edid *) sink->dc_edid.raw_edid;
1864
1865
c555f023 1866 drm_connector_update_edid_property(connector,
4562236b 1867 aconnector->edid);
e86e8947
HV		 1868 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1869 aconnector->edid);
4562236b 1870 }
98e6436d 1871 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1872
1873 } else {
e86e8947 1874 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1875 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1876 drm_connector_update_edid_property(connector, NULL);
4562236b 1877 aconnector->num_modes = 0;
dcd5fb82 1878 dc_sink_release(aconnector->dc_sink);
4562236b 1879 aconnector->dc_sink = NULL;
5326c452 1880 aconnector->edid = NULL;
0c8620d6
BL		 1881#ifdef CONFIG_DRM_AMD_DC_HDCP
1882 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
1883 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
1884 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
1885#endif
4562236b
HW		 1886 }
1887
1888 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1889
1890 if (sink)
1891 dc_sink_release(sink);
4562236b
HW		 1892}
1893
1894static void handle_hpd_irq(void *param)
1895{
c84dec2f 1896 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1897 struct drm_connector *connector = &aconnector->base;
1898 struct drm_device *dev = connector->dev;
fbbdadf2 1899 enum dc_connection_type new_connection_type = dc_connection_none;
0c8620d6
BL		 1900#ifdef CONFIG_DRM_AMD_DC_HDCP
1901 struct amdgpu_device *adev = dev->dev_private;
1902#endif
4562236b 1903
1f6010a9
DF		 1904 /*
1905 * In case of failure or MST no need to update connector status or notify the OS
1906 * since (for MST case) MST does this in its own context.
4562236b
HW		 1907 */
1908 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6 1909
0c8620d6 1910#ifdef CONFIG_DRM_AMD_DC_HDCP
96a3b32e
BL		 1911 if (adev->asic_type >= CHIP_RAVEN)
1912 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
0c8620d6 1913#endif
2e0ac3d6
HW		 1914 if (aconnector->fake_enable)
1915 aconnector->fake_enable = false;
1916
fbbdadf2
BL		 1917 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1918 DRM_ERROR("KMS: Failed to detect connector\n");
1919
1920 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1921 emulated_link_detect(aconnector->dc_link);
1922
1923
1924 drm_modeset_lock_all(dev);
1925 dm_restore_drm_connector_state(dev, connector);
1926 drm_modeset_unlock_all(dev);
1927
1928 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1929 drm_kms_helper_hotplug_event(dev);
1930
1931 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1932 amdgpu_dm_update_connector_after_detect(aconnector);
1933
1934
1935 drm_modeset_lock_all(dev);
1936 dm_restore_drm_connector_state(dev, connector);
1937 drm_modeset_unlock_all(dev);
1938
1939 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1940 drm_kms_helper_hotplug_event(dev);
1941 }
1942 mutex_unlock(&aconnector->hpd_lock);
1943
1944}
1945
c84dec2f 1946static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1947{
1948 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1949 uint8_t dret;
1950 bool new_irq_handled = false;
1951 int dpcd_addr;
1952 int dpcd_bytes_to_read;
1953
1954 const int max_process_count = 30;
1955 int process_count = 0;
1956
1957 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1958
1959 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1960 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1961 /* DPCD 0x200 - 0x201 for downstream IRQ */
1962 dpcd_addr = DP_SINK_COUNT;
1963 } else {
1964 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1965 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1966 dpcd_addr = DP_SINK_COUNT_ESI;
1967 }
1968
1969 dret = drm_dp_dpcd_read(
1970 &aconnector->dm_dp_aux.aux,
1971 dpcd_addr,
1972 esi,
1973 dpcd_bytes_to_read);
1974
1975 while (dret == dpcd_bytes_to_read &&
1976 process_count < max_process_count) {
1977 uint8_t retry;
1978 dret = 0;
1979
1980 process_count++;
1981
f1ad2f5e 1982 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1983 /* handle HPD short pulse irq */
1984 if (aconnector->mst_mgr.mst_state)
1985 drm_dp_mst_hpd_irq(
1986 &aconnector->mst_mgr,
1987 esi,
1988 &new_irq_handled);
4562236b
HW		 1989
1990 if (new_irq_handled) {
1991 /* ACK at DPCD to notify down stream */
1992 const int ack_dpcd_bytes_to_write =
1993 dpcd_bytes_to_read - 1;
1994
1995 for (retry = 0; retry < 3; retry++) {
1996 uint8_t wret;
1997
1998 wret = drm_dp_dpcd_write(
1999 &aconnector->dm_dp_aux.aux,
2000 dpcd_addr + 1,
2001 &esi[1],
2002 ack_dpcd_bytes_to_write);
2003 if (wret == ack_dpcd_bytes_to_write)
2004 break;
2005 }
2006
1f6010a9 2007 /* check if there is new irq to be handled */
4562236b
HW		 2008 dret = drm_dp_dpcd_read(
2009 &aconnector->dm_dp_aux.aux,
2010 dpcd_addr,
2011 esi,
2012 dpcd_bytes_to_read);
2013
2014 new_irq_handled = false;
d4a6e8a9 2015 } else {
4562236b 2016 break;
d4a6e8a9 2017 }
4562236b
HW		 2018 }
2019
2020 if (process_count == max_process_count)
f1ad2f5e 2021 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 2022}
2023
2024static void handle_hpd_rx_irq(void *param)
2025{
c84dec2f 2026 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 2027 struct drm_connector *connector = &aconnector->base;
2028 struct drm_device *dev = connector->dev;
53cbf65c 2029 struct dc_link *dc_link = aconnector->dc_link;
4562236b 2030 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 2031 enum dc_connection_type new_connection_type = dc_connection_none;
2a0f9270
BL		 2032#ifdef CONFIG_DRM_AMD_DC_HDCP
2033 union hpd_irq_data hpd_irq_data;
2034 struct amdgpu_device *adev = dev->dev_private;
2035
2036 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
2037#endif
4562236b 2038
1f6010a9
DF		 2039 /*
2040 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 2041 * conflict, after implement i2c helper, this mutex should be
2042 * retired.
2043 */
53cbf65c 2044 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 2045 mutex_lock(&aconnector->hpd_lock);
2046
2a0f9270
BL		 2047
2048#ifdef CONFIG_DRM_AMD_DC_HDCP
2049 if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) &&
2050#else
4e18814e 2051 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
2a0f9270 2052#endif
4562236b
HW		 2053 !is_mst_root_connector) {
2054 /* Downstream Port status changed. */
fbbdadf2
BL		 2055 if (!dc_link_detect_sink(dc_link, &new_connection_type))
2056 DRM_ERROR("KMS: Failed to detect connector\n");
2057
2058 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2059 emulated_link_detect(dc_link);
2060
2061 if (aconnector->fake_enable)
2062 aconnector->fake_enable = false;
2063
2064 amdgpu_dm_update_connector_after_detect(aconnector);
2065
2066
2067 drm_modeset_lock_all(dev);
2068 dm_restore_drm_connector_state(dev, connector);
2069 drm_modeset_unlock_all(dev);
2070
2071 drm_kms_helper_hotplug_event(dev);
2072 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 2073
2074 if (aconnector->fake_enable)
2075 aconnector->fake_enable = false;
2076
4562236b
HW		 2077 amdgpu_dm_update_connector_after_detect(aconnector);
2078
2079
2080 drm_modeset_lock_all(dev);
2081 dm_restore_drm_connector_state(dev, connector);
2082 drm_modeset_unlock_all(dev);
2083
2084 drm_kms_helper_hotplug_event(dev);
2085 }
2086 }
2a0f9270
BL		 2087#ifdef CONFIG_DRM_AMD_DC_HDCP
2088 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ)
2089 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
2090#endif
4562236b 2091 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 2092 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 2093 dm_handle_hpd_rx_irq(aconnector);
2094
e86e8947
HV		 2095 if (dc_link->type != dc_connection_mst_branch) {
2096 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 2097 mutex_unlock(&aconnector->hpd_lock);
e86e8947 2098 }
4562236b
HW		 2099}
2100
2101static void register_hpd_handlers(struct amdgpu_device *adev)
2102{
2103 struct drm_device *dev = adev->ddev;
2104 struct drm_connector *connector;
c84dec2f 2105 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 2106 const struct dc_link *dc_link;
2107 struct dc_interrupt_params int_params = {0};
2108
2109 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2110 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2111
2112 list_for_each_entry(connector,
2113 &dev->mode_config.connector_list, head) {
2114
c84dec2f 2115 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 2116 dc_link = aconnector->dc_link;
2117
2118 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
2119 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2120 int_params.irq_source = dc_link->irq_source_hpd;
2121
2122 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2123 handle_hpd_irq,
2124 (void *) aconnector);
2125 }
2126
2127 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
2128
2129 /* Also register for DP short pulse (hpd_rx). */
2130 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2131 int_params.irq_source = dc_link->irq_source_hpd_rx;
2132
2133 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2134 handle_hpd_rx_irq,
2135 (void *) aconnector);
2136 }
2137 }
2138}
2139
2140/* Register IRQ sources and initialize IRQ callbacks */
2141static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2142{
2143 struct dc *dc = adev->dm.dc;
2144 struct common_irq_params *c_irq_params;
2145 struct dc_interrupt_params int_params = {0};
2146 int r;
2147 int i;
1ffdeca6 2148 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 2149
84374725 2150 if (adev->asic_type >= CHIP_VEGA10)
3760f76c 2151 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 2152
2153 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2154 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2155
1f6010a9
DF		 2156 /*
2157 * Actions of amdgpu_irq_add_id():
4562236b
HW		 2158 * 1. Register a set() function with base driver.
2159 * Base driver will call set() function to enable/disable an
2160 * interrupt in DC hardware.
2161 * 2. Register amdgpu_dm_irq_handler().
2162 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2163 * coming from DC hardware.
2164 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2165 * for acknowledging and handling. */
2166
b57de80a 2167 /* Use VBLANK interrupt */
e9029155 2168 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 2169 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 2170 if (r) {
2171 DRM_ERROR("Failed to add crtc irq id!\n");
2172 return r;
2173 }
2174
2175 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2176 int_params.irq_source =
3d761e79 2177 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 2178
b57de80a 2179 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 2180
2181 c_irq_params->adev = adev;
2182 c_irq_params->irq_src = int_params.irq_source;
2183
2184 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2185 dm_crtc_high_irq, c_irq_params);
2186 }
2187
d2574c33
MK		 2188 /* Use VUPDATE interrupt */
2189 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
2190 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
2191 if (r) {
2192 DRM_ERROR("Failed to add vupdate irq id!\n");
2193 return r;
2194 }
2195
2196 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2197 int_params.irq_source =
2198 dc_interrupt_to_irq_source(dc, i, 0);
2199
2200 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2201
2202 c_irq_params->adev = adev;
2203 c_irq_params->irq_src = int_params.irq_source;
2204
2205 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2206 dm_vupdate_high_irq, c_irq_params);
2207 }
2208
3d761e79 2209 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 2210 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2211 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 2212 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 2213 if (r) {
2214 DRM_ERROR("Failed to add page flip irq id!\n");
2215 return r;
2216 }
2217
2218 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2219 int_params.irq_source =
2220 dc_interrupt_to_irq_source(dc, i, 0);
2221
2222 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2223
2224 c_irq_params->adev = adev;
2225 c_irq_params->irq_src = int_params.irq_source;
2226
2227 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2228 dm_pflip_high_irq, c_irq_params);
2229
2230 }
2231
2232 /* HPD */
2c8ad2d5
AD		 2233 r = amdgpu_irq_add_id(adev, client_id,
2234 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 2235 if (r) {
2236 DRM_ERROR("Failed to add hpd irq id!\n");
2237 return r;
2238 }
2239
2240 register_hpd_handlers(adev);
2241
2242 return 0;
2243}
2244
b86a1aa3 2245#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 2246/* Register IRQ sources and initialize IRQ callbacks */
2247static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
2248{
2249 struct dc *dc = adev->dm.dc;
2250 struct common_irq_params *c_irq_params;
2251 struct dc_interrupt_params int_params = {0};
2252 int r;
2253 int i;
2254
2255 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2256 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2257
1f6010a9
DF		 2258 /*
2259 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 2260 * 1. Register a set() function with base driver.
2261 * Base driver will call set() function to enable/disable an
2262 * interrupt in DC hardware.
2263 * 2. Register amdgpu_dm_irq_handler().
2264 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2265 * coming from DC hardware.
2266 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2267 * for acknowledging and handling.
1f6010a9 2268 */
ff5ef992
AD		 2269
2270 /* Use VSTARTUP interrupt */
2271 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
2272 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
2273 i++) {
3760f76c 2274 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 2275
2276 if (r) {
2277 DRM_ERROR("Failed to add crtc irq id!\n");
2278 return r;
2279 }
2280
2281 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2282 int_params.irq_source =
2283 dc_interrupt_to_irq_source(dc, i, 0);
2284
2285 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2286
2287 c_irq_params->adev = adev;
2288 c_irq_params->irq_src = int_params.irq_source;
2289
2290 amdgpu_dm_irq_register_interrupt(adev, &int_params,
16f17eda 2291 dm_dcn_crtc_high_irq, c_irq_params);
d2574c33
MK		 2292 }
2293
ff5ef992
AD		 2294 /* Use GRPH_PFLIP interrupt */
2295 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
2296 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
2297 i++) {
3760f76c 2298 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 2299 if (r) {
2300 DRM_ERROR("Failed to add page flip irq id!\n");
2301 return r;
2302 }
2303
2304 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2305 int_params.irq_source =
2306 dc_interrupt_to_irq_source(dc, i, 0);
2307
2308 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2309
2310 c_irq_params->adev = adev;
2311 c_irq_params->irq_src = int_params.irq_source;
2312
2313 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2314 dm_pflip_high_irq, c_irq_params);
2315
2316 }
2317
2318 /* HPD */
3760f76c 2319 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 2320 &adev->hpd_irq);
2321 if (r) {
2322 DRM_ERROR("Failed to add hpd irq id!\n");
2323 return r;
2324 }
2325
2326 register_hpd_handlers(adev);
2327
2328 return 0;
2329}
2330#endif
2331
eb3dc897
NK		 2332/*
2333 * Acquires the lock for the atomic state object and returns
2334 * the new atomic state.
2335 *
2336 * This should only be called during atomic check.
2337 */
2338static int dm_atomic_get_state(struct drm_atomic_state *state,
2339 struct dm_atomic_state **dm_state)
2340{
2341 struct drm_device *dev = state->dev;
2342 struct amdgpu_device *adev = dev->dev_private;
2343 struct amdgpu_display_manager *dm = &adev->dm;
2344 struct drm_private_state *priv_state;
eb3dc897
NK		 2345
2346 if (*dm_state)
2347 return 0;
2348
eb3dc897
NK		 2349 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
2350 if (IS_ERR(priv_state))
2351 return PTR_ERR(priv_state);
2352
2353 *dm_state = to_dm_atomic_state(priv_state);
2354
2355 return 0;
2356}
2357
2358struct dm_atomic_state *
2359dm_atomic_get_new_state(struct drm_atomic_state *state)
2360{
2361 struct drm_device *dev = state->dev;
2362 struct amdgpu_device *adev = dev->dev_private;
2363 struct amdgpu_display_manager *dm = &adev->dm;
2364 struct drm_private_obj *obj;
2365 struct drm_private_state *new_obj_state;
2366 int i;
2367
2368 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
2369 if (obj->funcs == dm->atomic_obj.funcs)
2370 return to_dm_atomic_state(new_obj_state);
2371 }
2372
2373 return NULL;
2374}
2375
2376struct dm_atomic_state *
2377dm_atomic_get_old_state(struct drm_atomic_state *state)
2378{
2379 struct drm_device *dev = state->dev;
2380 struct amdgpu_device *adev = dev->dev_private;
2381 struct amdgpu_display_manager *dm = &adev->dm;
2382 struct drm_private_obj *obj;
2383 struct drm_private_state *old_obj_state;
2384 int i;
2385
2386 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
2387 if (obj->funcs == dm->atomic_obj.funcs)
2388 return to_dm_atomic_state(old_obj_state);
2389 }
2390
2391 return NULL;
2392}
2393
2394static struct drm_private_state *
2395dm_atomic_duplicate_state(struct drm_private_obj *obj)
2396{
2397 struct dm_atomic_state *old_state, *new_state;
2398
2399 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
2400 if (!new_state)
2401 return NULL;
2402
2403 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
2404
813d20dc
AW		 2405 old_state = to_dm_atomic_state(obj->state);
2406
2407 if (old_state && old_state->context)
2408 new_state->context = dc_copy_state(old_state->context);
2409
eb3dc897
NK		 2410 if (!new_state->context) {
2411 kfree(new_state);
2412 return NULL;
2413 }
2414
eb3dc897
NK		 2415 return &new_state->base;
2416}
2417
2418static void dm_atomic_destroy_state(struct drm_private_obj *obj,
2419 struct drm_private_state *state)
2420{
2421 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
2422
2423 if (dm_state && dm_state->context)
2424 dc_release_state(dm_state->context);
2425
2426 kfree(dm_state);
2427}
2428
2429static struct drm_private_state_funcs dm_atomic_state_funcs = {
2430 .atomic_duplicate_state = dm_atomic_duplicate_state,
2431 .atomic_destroy_state = dm_atomic_destroy_state,
2432};
2433
4562236b
HW		 2434static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2435{
eb3dc897 2436 struct dm_atomic_state *state;
4562236b
HW		 2437 int r;
2438
2439 adev->mode_info.mode_config_initialized = true;
2440
4562236b 2441 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 2442 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 2443
2444 adev->ddev->mode_config.max_width = 16384;
2445 adev->ddev->mode_config.max_height = 16384;
2446
2447 adev->ddev->mode_config.preferred_depth = 24;
2448 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 2449 /* indicates support for immediate flip */
4562236b
HW		 2450 adev->ddev->mode_config.async_page_flip = true;
2451
770d13b1 2452 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 2453
eb3dc897
NK		 2454 state = kzalloc(sizeof(*state), GFP_KERNEL);
2455 if (!state)
2456 return -ENOMEM;
2457
813d20dc 2458 state->context = dc_create_state(adev->dm.dc);
eb3dc897
NK		 2459 if (!state->context) {
2460 kfree(state);
2461 return -ENOMEM;
2462 }
2463
2464 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2465
8c1a765b
DA		 2466 drm_atomic_private_obj_init(adev->ddev,
2467 &adev->dm.atomic_obj,
eb3dc897
NK		 2468 &state->base,
2469 &dm_atomic_state_funcs);
2470
3dc9b1ce 2471 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 2472 if (r)
2473 return r;
2474
6ce8f316
NK		 2475 r = amdgpu_dm_audio_init(adev);
2476 if (r)
2477 return r;
2478
4562236b
HW		 2479 return 0;
2480}
2481
206bbafe
DF		 2482#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2483#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2484
4562236b
HW		 2485#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2486 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2487
206bbafe
DF		 2488static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2489{
2490#if defined(CONFIG_ACPI)
2491 struct amdgpu_dm_backlight_caps caps;
2492
2493 if (dm->backlight_caps.caps_valid)
2494 return;
2495
2496 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2497 if (caps.caps_valid) {
2498 dm->backlight_caps.min_input_signal = caps.min_input_signal;
2499 dm->backlight_caps.max_input_signal = caps.max_input_signal;
2500 dm->backlight_caps.caps_valid = true;
2501 } else {
2502 dm->backlight_caps.min_input_signal =
2503 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2504 dm->backlight_caps.max_input_signal =
2505 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2506 }
2507#else
8bcbc9ef
DF		 2508 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2509 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 2510#endif
2511}
2512
4562236b
HW		 2513static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2514{
2515 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 2516 struct amdgpu_dm_backlight_caps caps;
2517 uint32_t brightness = bd->props.brightness;
4562236b 2518
206bbafe
DF		 2519 amdgpu_dm_update_backlight_caps(dm);
2520 caps = dm->backlight_caps;
0cafc82f 2521 /*
206bbafe
DF		 2522 * The brightness input is in the range 0-255
2523 * It needs to be rescaled to be between the
2524 * requested min and max input signal
2525 *
2526 * It also needs to be scaled up by 0x101 to
2527 * match the DC interface which has a range of
2528 * 0 to 0xffff
0cafc82f 2529 */
206bbafe
DF		 2530 brightness =
2531 brightness
2532 * 0x101
2533 * (caps.max_input_signal - caps.min_input_signal)
2534 / AMDGPU_MAX_BL_LEVEL
2535 + caps.min_input_signal * 0x101;
4562236b
HW		 2536
2537 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 2538 brightness, 0))
4562236b
HW		 2539 return 0;
2540 else
2541 return 1;
2542}
2543
2544static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2545{
620a0d27
DF		 2546 struct amdgpu_display_manager *dm = bl_get_data(bd);
2547 int ret = dc_link_get_backlight_level(dm->backlight_link);
2548
2549 if (ret == DC_ERROR_UNEXPECTED)
2550 return bd->props.brightness;
2551 return ret;
4562236b
HW		 2552}
2553
2554static const struct backlight_ops amdgpu_dm_backlight_ops = {
bb264220 2555 .options = BL_CORE_SUSPENDRESUME,
4562236b
HW		 2556 .get_brightness = amdgpu_dm_backlight_get_brightness,
2557 .update_status = amdgpu_dm_backlight_update_status,
2558};
2559
7578ecda
AD		 2560static void
2561amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2562{
2563 char bl_name[16];
2564 struct backlight_properties props = { 0 };
2565
206bbafe
DF		 2566 amdgpu_dm_update_backlight_caps(dm);
2567
4562236b 2568 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 2569 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 2570 props.type = BACKLIGHT_RAW;
2571
2572 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2573 dm->adev->ddev->primary->index);
2574
2575 dm->backlight_dev = backlight_device_register(bl_name,
2576 dm->adev->ddev->dev,
2577 dm,
2578 &amdgpu_dm_backlight_ops,
2579 &props);
2580
74baea42 2581 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 2582 DRM_ERROR("DM: Backlight registration failed!\n");
2583 else
f1ad2f5e 2584 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 2585}
2586
2587#endif
2588
df534fff 2589static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13 2590 struct amdgpu_mode_info *mode_info, int plane_id,
cc1fec57
NK		 2591 enum drm_plane_type plane_type,
2592 const struct dc_plane_cap *plane_cap)
df534fff 2593{
f180b4bc 2594 struct drm_plane *plane;
df534fff
S		 2595 unsigned long possible_crtcs;
2596 int ret = 0;
2597
f180b4bc 2598 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 2599 if (!plane) {
2600 DRM_ERROR("KMS: Failed to allocate plane\n");
2601 return -ENOMEM;
2602 }
b2fddb13 2603 plane->type = plane_type;
df534fff
S		 2604
2605 /*
b2fddb13
NK		 2606 * HACK: IGT tests expect that the primary plane for a CRTC
2607 * can only have one possible CRTC. Only expose support for
2608 * any CRTC if they're not going to be used as a primary plane
2609 * for a CRTC - like overlay or underlay planes.
df534fff
S		 2610 */
2611 possible_crtcs = 1 << plane_id;
2612 if (plane_id >= dm->dc->caps.max_streams)
2613 possible_crtcs = 0xff;
2614
cc1fec57 2615 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
df534fff
S		 2616
2617 if (ret) {
2618 DRM_ERROR("KMS: Failed to initialize plane\n");
54087768 2619 kfree(plane);
df534fff
S		 2620 return ret;
2621 }
2622
54087768
NK		 2623 if (mode_info)
2624 mode_info->planes[plane_id] = plane;
2625
df534fff
S		 2626 return ret;
2627}
2628
89fc8d4e
HW		 2629
2630static void register_backlight_device(struct amdgpu_display_manager *dm,
2631 struct dc_link *link)
2632{
2633#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2634 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2635
2636 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2637 link->type != dc_connection_none) {
1f6010a9
DF		 2638 /*
2639 * Event if registration failed, we should continue with
89fc8d4e
HW		 2640 * DM initialization because not having a backlight control
2641 * is better then a black screen.
2642 */
2643 amdgpu_dm_register_backlight_device(dm);
2644
2645 if (dm->backlight_dev)
2646 dm->backlight_link = link;
2647 }
2648#endif
2649}
2650
2651
1f6010a9
DF		 2652/*
2653 * In this architecture, the association
4562236b
HW		 2654 * connector -> encoder -> crtc
2655 * id not really requried. The crtc and connector will hold the
2656 * display_index as an abstraction to use with DAL component
2657 *
2658 * Returns 0 on success
2659 */
7578ecda 2660static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 2661{
2662 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 2663 int32_t i;
c84dec2f 2664 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 2665 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 2666 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 2667 uint32_t link_cnt;
cc1fec57 2668 int32_t primary_planes;
fbbdadf2 2669 enum dc_connection_type new_connection_type = dc_connection_none;
cc1fec57 2670 const struct dc_plane_cap *plane;
4562236b
HW		 2671
2672 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 2673 if (amdgpu_dm_mode_config_init(dm->adev)) {
2674 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 2675 return -EINVAL;
4562236b
HW		 2676 }
2677
b2fddb13
NK		 2678 /* There is one primary plane per CRTC */
2679 primary_planes = dm->dc->caps.max_streams;
54087768 2680 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
efa6a8b7 2681
b2fddb13
NK		 2682 /*
2683 * Initialize primary planes, implicit planes for legacy IOCTLS.
2684 * Order is reversed to match iteration order in atomic check.
2685 */
2686 for (i = (primary_planes - 1); i >= 0; i--) {
cc1fec57
NK		 2687 plane = &dm->dc->caps.planes[i];
2688
b2fddb13 2689 if (initialize_plane(dm, mode_info, i,
cc1fec57 2690 DRM_PLANE_TYPE_PRIMARY, plane)) {
df534fff 2691 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 2692 goto fail;
d4e13b0d 2693 }
df534fff 2694 }
92f3ac40 2695
0d579c7e
NK		 2696 /*
2697 * Initialize overlay planes, index starting after primary planes.
2698 * These planes have a higher DRM index than the primary planes since
2699 * they should be considered as having a higher z-order.
2700 * Order is reversed to match iteration order in atomic check.
cc1fec57
NK		 2701 *
2702 * Only support DCN for now, and only expose one so we don't encourage
2703 * userspace to use up all the pipes.
0d579c7e 2704 */
cc1fec57
NK		 2705 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2706 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2707
2708 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2709 continue;
2710
2711 if (!plane->blends_with_above || !plane->blends_with_below)
2712 continue;
2713
ea36ad34 2714 if (!plane->pixel_format_support.argb8888)
cc1fec57
NK		 2715 continue;
2716
54087768 2717 if (initialize_plane(dm, NULL, primary_planes + i,
cc1fec57 2718 DRM_PLANE_TYPE_OVERLAY, plane)) {
0d579c7e 2719 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 2720 goto fail;
d4e13b0d 2721 }
cc1fec57
NK		 2722
2723 /* Only create one overlay plane. */
2724 break;
d4e13b0d 2725 }
4562236b 2726
d4e13b0d 2727 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 2728 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 2729 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 2730 goto fail;
4562236b 2731 }
4562236b 2732
ab2541b6 2733 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 2734
2735 /* loops over all connectors on the board */
2736 for (i = 0; i < link_cnt; i++) {
89fc8d4e 2737 struct dc_link *link = NULL;
4562236b
HW		 2738
2739 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2740 DRM_ERROR(
2741 "KMS: Cannot support more than %d display indexes\n",
2742 AMDGPU_DM_MAX_DISPLAY_INDEX);
2743 continue;
2744 }
2745
2746 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2747 if (!aconnector)
cd8a2ae8 2748 goto fail;
4562236b
HW		 2749
2750 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 2751 if (!aencoder)
cd8a2ae8 2752 goto fail;
4562236b
HW		 2753
2754 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2755 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 2756 goto fail;
4562236b
HW		 2757 }
2758
2759 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2760 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 2761 goto fail;
4562236b
HW		 2762 }
2763
89fc8d4e
HW		 2764 link = dc_get_link_at_index(dm->dc, i);
2765
fbbdadf2
BL		 2766 if (!dc_link_detect_sink(link, &new_connection_type))
2767 DRM_ERROR("KMS: Failed to detect connector\n");
2768
2769 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2770 emulated_link_detect(link);
2771 amdgpu_dm_update_connector_after_detect(aconnector);
2772
2773 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 2774 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e 2775 register_backlight_device(dm, link);
397a9bc5
RL		 2776 if (amdgpu_dc_feature_mask & DC_PSR_MASK)
2777 amdgpu_dm_set_psr_caps(link);
89fc8d4e
HW		 2778 }
2779
2780
4562236b
HW		 2781 }
2782
2783 /* Software is initialized. Now we can register interrupt handlers. */
2784 switch (adev->asic_type) {
2785 case CHIP_BONAIRE:
2786 case CHIP_HAWAII:
cd4b356f
AD		 2787 case CHIP_KAVERI:
2788 case CHIP_KABINI:
2789 case CHIP_MULLINS:
4562236b
HW		 2790 case CHIP_TONGA:
2791 case CHIP_FIJI:
2792 case CHIP_CARRIZO:
2793 case CHIP_STONEY:
2794 case CHIP_POLARIS11:
2795 case CHIP_POLARIS10:
b264d345 2796 case CHIP_POLARIS12:
7737de91 2797 case CHIP_VEGAM:
2c8ad2d5 2798 case CHIP_VEGA10:
2325ff30 2799 case CHIP_VEGA12:
1fe6bf2f 2800 case CHIP_VEGA20:
4562236b
HW		 2801 if (dce110_register_irq_handlers(dm->adev)) {
2802 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2803 goto fail;
4562236b
HW		 2804 }
2805 break;
b86a1aa3 2806#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992 2807 case CHIP_RAVEN:
fbd2afe5 2808 case CHIP_NAVI12:
476e955d 2809 case CHIP_NAVI10:
fce651e3 2810 case CHIP_NAVI14:
30221ad8 2811 case CHIP_RENOIR:
ff5ef992
AD		 2812 if (dcn10_register_irq_handlers(dm->adev)) {
2813 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2814 goto fail;
ff5ef992
AD		 2815 }
2816 break;
2817#endif
4562236b 2818 default:
e63f8673 2819 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2820 goto fail;
4562236b
HW		 2821 }
2822
1bc460a4
HW		 2823 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2824 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2825
4562236b 2826 return 0;
cd8a2ae8 2827fail:
4562236b 2828 kfree(aencoder);
4562236b 2829 kfree(aconnector);
54087768 2830
59d0f396 2831 return -EINVAL;
4562236b
HW		 2832}
2833
7578ecda 2834static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2835{
2836 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2837 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2838 return;
2839}
2840
2841/******************************************************************************
2842 * amdgpu_display_funcs functions
2843 *****************************************************************************/
2844
1f6010a9 2845/*
4562236b
HW		 2846 * dm_bandwidth_update - program display watermarks
2847 *
2848 * @adev: amdgpu_device pointer
2849 *
2850 * Calculate and program the display watermarks and line buffer allocation.
2851 */
2852static void dm_bandwidth_update(struct amdgpu_device *adev)
2853{
49c07a99 2854 /* TODO: implement later */
4562236b
HW		 2855}
2856
39cc5be2 2857static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2858 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2859 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2860 .backlight_set_level = NULL, /* never called for DC */
2861 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2862 .hpd_sense = NULL,/* called unconditionally */
2863 .hpd_set_polarity = NULL, /* called unconditionally */
2864 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2865 .page_flip_get_scanoutpos =
2866 dm_crtc_get_scanoutpos,/* called unconditionally */
2867 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2868 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2869};
2870
2871#if defined(CONFIG_DEBUG_KERNEL_DC)
2872
3ee6b26b
AD		 2873static ssize_t s3_debug_store(struct device *device,
2874 struct device_attribute *attr,
2875 const char *buf,
2876 size_t count)
4562236b
HW		 2877{
2878 int ret;
2879 int s3_state;
ef1de361 2880 struct drm_device *drm_dev = dev_get_drvdata(device);
4562236b
HW		 2881 struct amdgpu_device *adev = drm_dev->dev_private;
2882
2883 ret = kstrtoint(buf, 0, &s3_state);
2884
2885 if (ret == 0) {
2886 if (s3_state) {
2887 dm_resume(adev);
4562236b
HW		 2888 drm_kms_helper_hotplug_event(adev->ddev);
2889 } else
2890 dm_suspend(adev);
2891 }
2892
2893 return ret == 0 ? count : 0;
2894}
2895
2896DEVICE_ATTR_WO(s3_debug);
2897
2898#endif
2899
2900static int dm_early_init(void *handle)
2901{
2902 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2903
4562236b
HW		 2904 switch (adev->asic_type) {
2905 case CHIP_BONAIRE:
2906 case CHIP_HAWAII:
2907 adev->mode_info.num_crtc = 6;
2908 adev->mode_info.num_hpd = 6;
2909 adev->mode_info.num_dig = 6;
4562236b 2910 break;
cd4b356f
AD		 2911 case CHIP_KAVERI:
2912 adev->mode_info.num_crtc = 4;
2913 adev->mode_info.num_hpd = 6;
2914 adev->mode_info.num_dig = 7;
cd4b356f
AD		 2915 break;
2916 case CHIP_KABINI:
2917 case CHIP_MULLINS:
2918 adev->mode_info.num_crtc = 2;
2919 adev->mode_info.num_hpd = 6;
2920 adev->mode_info.num_dig = 6;
cd4b356f 2921 break;
4562236b
HW		 2922 case CHIP_FIJI:
2923 case CHIP_TONGA:
2924 adev->mode_info.num_crtc = 6;
2925 adev->mode_info.num_hpd = 6;
2926 adev->mode_info.num_dig = 7;
4562236b
HW		 2927 break;
2928 case CHIP_CARRIZO:
2929 adev->mode_info.num_crtc = 3;
2930 adev->mode_info.num_hpd = 6;
2931 adev->mode_info.num_dig = 9;
4562236b
HW		 2932 break;
2933 case CHIP_STONEY:
2934 adev->mode_info.num_crtc = 2;
2935 adev->mode_info.num_hpd = 6;
2936 adev->mode_info.num_dig = 9;
4562236b
HW		 2937 break;
2938 case CHIP_POLARIS11:
b264d345 2939 case CHIP_POLARIS12:
4562236b
HW		 2940 adev->mode_info.num_crtc = 5;
2941 adev->mode_info.num_hpd = 5;
2942 adev->mode_info.num_dig = 5;
4562236b
HW		 2943 break;
2944 case CHIP_POLARIS10:
7737de91 2945 case CHIP_VEGAM:
4562236b
HW		 2946 adev->mode_info.num_crtc = 6;
2947 adev->mode_info.num_hpd = 6;
2948 adev->mode_info.num_dig = 6;
4562236b 2949 break;
2c8ad2d5 2950 case CHIP_VEGA10:
2325ff30 2951 case CHIP_VEGA12:
1fe6bf2f 2952 case CHIP_VEGA20:
2c8ad2d5
AD		 2953 adev->mode_info.num_crtc = 6;
2954 adev->mode_info.num_hpd = 6;
2955 adev->mode_info.num_dig = 6;
2956 break;
b86a1aa3 2957#if defined(CONFIG_DRM_AMD_DC_DCN)
ff5ef992
AD		 2958 case CHIP_RAVEN:
2959 adev->mode_info.num_crtc = 4;
2960 adev->mode_info.num_hpd = 4;
2961 adev->mode_info.num_dig = 4;
ff5ef992 2962 break;
476e955d 2963#endif
476e955d 2964 case CHIP_NAVI10:
fbd2afe5 2965 case CHIP_NAVI12:
476e955d
HW		 2966 adev->mode_info.num_crtc = 6;
2967 adev->mode_info.num_hpd = 6;
2968 adev->mode_info.num_dig = 6;
2969 break;
fce651e3
BL		 2970 case CHIP_NAVI14:
2971 adev->mode_info.num_crtc = 5;
2972 adev->mode_info.num_hpd = 5;
2973 adev->mode_info.num_dig = 5;
2974 break;
30221ad8
BL		 2975 case CHIP_RENOIR:
2976 adev->mode_info.num_crtc = 4;
2977 adev->mode_info.num_hpd = 4;
2978 adev->mode_info.num_dig = 4;
2979 break;
4562236b 2980 default:
e63f8673 2981 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2982 return -EINVAL;
2983 }
2984
c8dd5715
MD		 2985 amdgpu_dm_set_irq_funcs(adev);
2986
39cc5be2
AD		 2987 if (adev->mode_info.funcs == NULL)
2988 adev->mode_info.funcs = &dm_display_funcs;
2989
1f6010a9
DF		 2990 /*
2991 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2992 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2993 * amdgpu_device_init()
2994 */
4562236b
HW		 2995#if defined(CONFIG_DEBUG_KERNEL_DC)
2996 device_create_file(
2997 adev->ddev->dev,
2998 &dev_attr_s3_debug);
2999#endif
3000
3001 return 0;
3002}
3003
9b690ef3 3004static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 3005 struct dc_stream_state *new_stream,
3006 struct dc_stream_state *old_stream)
9b690ef3 3007{
e7b07cee
HW		 3008 if (!drm_atomic_crtc_needs_modeset(crtc_state))
3009 return false;
3010
3011 if (!crtc_state->enable)
3012 return false;
3013
3014 return crtc_state->active;
3015}
3016
3017static bool modereset_required(struct drm_crtc_state *crtc_state)
3018{
3019 if (!drm_atomic_crtc_needs_modeset(crtc_state))
3020 return false;
3021
3022 return !crtc_state->enable || !crtc_state->active;
3023}
3024
7578ecda 3025static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 3026{
3027 drm_encoder_cleanup(encoder);
3028 kfree(encoder);
3029}
3030
3031static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
3032 .destroy = amdgpu_dm_encoder_destroy,
3033};
3034
e7b07cee 3035
695af5f9
NK		 3036static int fill_dc_scaling_info(const struct drm_plane_state *state,
3037 struct dc_scaling_info *scaling_info)
e7b07cee 3038{
6491f0c0 3039 int scale_w, scale_h;
e7b07cee 3040
695af5f9 3041 memset(scaling_info, 0, sizeof(*scaling_info));
e7b07cee 3042
695af5f9
NK		 3043 /* Source is fixed 16.16 but we ignore mantissa for now... */
3044 scaling_info->src_rect.x = state->src_x >> 16;
3045 scaling_info->src_rect.y = state->src_y >> 16;
e7b07cee 3046
695af5f9
NK		 3047 scaling_info->src_rect.width = state->src_w >> 16;
3048 if (scaling_info->src_rect.width == 0)
3049 return -EINVAL;
3050
3051 scaling_info->src_rect.height = state->src_h >> 16;
3052 if (scaling_info->src_rect.height == 0)
3053 return -EINVAL;
3054
3055 scaling_info->dst_rect.x = state->crtc_x;
3056 scaling_info->dst_rect.y = state->crtc_y;
e7b07cee
HW		 3057
3058 if (state->crtc_w == 0)
695af5f9 3059 return -EINVAL;
e7b07cee 3060
695af5f9 3061 scaling_info->dst_rect.width = state->crtc_w;
e7b07cee
HW		 3062
3063 if (state->crtc_h == 0)
695af5f9 3064 return -EINVAL;
e7b07cee 3065
695af5f9 3066 scaling_info->dst_rect.height = state->crtc_h;
e7b07cee 3067
695af5f9
NK		 3068 /* DRM doesn't specify clipping on destination output. */
3069 scaling_info->clip_rect = scaling_info->dst_rect;
e7b07cee 3070
6491f0c0
NK		 3071 /* TODO: Validate scaling per-format with DC plane caps */
3072 scale_w = scaling_info->dst_rect.width * 1000 /
3073 scaling_info->src_rect.width;
e7b07cee 3074
6491f0c0
NK		 3075 if (scale_w < 250 || scale_w > 16000)
3076 return -EINVAL;
3077
3078 scale_h = scaling_info->dst_rect.height * 1000 /
3079 scaling_info->src_rect.height;
3080
3081 if (scale_h < 250 || scale_h > 16000)
3082 return -EINVAL;
3083
695af5f9
NK		 3084 /*
3085 * The "scaling_quality" can be ignored for now, quality = 0 has DC
3086 * assume reasonable defaults based on the format.
3087 */
e7b07cee 3088
695af5f9 3089 return 0;
4562236b 3090}
695af5f9 3091
3ee6b26b 3092static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 3093 uint64_t *tiling_flags)
e7b07cee 3094{
e68d14dd 3095 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 3096 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 3097
e7b07cee 3098 if (unlikely(r)) {
1f6010a9 3099 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 3100 if (r != -ERESTARTSYS)
3101 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 3102 return r;
3103 }
3104
e7b07cee
HW		 3105 if (tiling_flags)
3106 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
3107
3108 amdgpu_bo_unreserve(rbo);
3109
3110 return r;
3111}
3112
7df7e505
NK		 3113static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
3114{
3115 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
3116
3117 return offset ? (address + offset * 256) : 0;
3118}
3119
695af5f9
NK		 3120static int
3121fill_plane_dcc_attributes(struct amdgpu_device *adev,
3122 const struct amdgpu_framebuffer *afb,
3123 const enum surface_pixel_format format,
3124 const enum dc_rotation_angle rotation,
12e2b2d4 3125 const struct plane_size *plane_size,
695af5f9
NK		 3126 const union dc_tiling_info *tiling_info,
3127 const uint64_t info,
3128 struct dc_plane_dcc_param *dcc,
3129 struct dc_plane_address *address)
7df7e505
NK		 3130{
3131 struct dc *dc = adev->dm.dc;
8daa1218
NC		 3132 struct dc_dcc_surface_param input;
3133 struct dc_surface_dcc_cap output;
7df7e505
NK		 3134 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
3135 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
3136 uint64_t dcc_address;
3137
8daa1218
NC		 3138 memset(&input, 0, sizeof(input));
3139 memset(&output, 0, sizeof(output));
3140
7df7e505 3141 if (!offset)
09e5665a
NK		 3142 return 0;
3143
695af5f9 3144 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
09e5665a 3145 return 0;
7df7e505
NK		 3146
3147 if (!dc->cap_funcs.get_dcc_compression_cap)
09e5665a 3148 return -EINVAL;
7df7e505 3149
695af5f9 3150 input.format = format;
12e2b2d4
DL		 3151 input.surface_size.width = plane_size->surface_size.width;
3152 input.surface_size.height = plane_size->surface_size.height;
695af5f9 3153 input.swizzle_mode = tiling_info->gfx9.swizzle;
7df7e505 3154
695af5f9 3155 if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
7df7e505 3156 input.scan = SCAN_DIRECTION_HORIZONTAL;
695af5f9 3157 else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
7df7e505
NK		 3158 input.scan = SCAN_DIRECTION_VERTICAL;
3159
3160 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
09e5665a 3161 return -EINVAL;
7df7e505
NK		 3162
3163 if (!output.capable)
09e5665a 3164 return -EINVAL;
7df7e505
NK		 3165
3166 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
09e5665a 3167 return -EINVAL;
7df7e505 3168
09e5665a 3169 dcc->enable = 1;
12e2b2d4 3170 dcc->meta_pitch =
7df7e505 3171 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
12e2b2d4 3172 dcc->independent_64b_blks = i64b;
7df7e505
NK		 3173
3174 dcc_address = get_dcc_address(afb->address, info);
09e5665a
NK		 3175 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
3176 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
7df7e505 3177
09e5665a
NK		 3178 return 0;
3179}
3180
3181static int
320932bf 3182fill_plane_buffer_attributes(struct amdgpu_device *adev,
09e5665a 3183 const struct amdgpu_framebuffer *afb,
695af5f9
NK		 3184 const enum surface_pixel_format format,
3185 const enum dc_rotation_angle rotation,
3186 const uint64_t tiling_flags,
09e5665a 3187 union dc_tiling_info *tiling_info,
12e2b2d4 3188 struct plane_size *plane_size,
09e5665a 3189 struct dc_plane_dcc_param *dcc,
695af5f9 3190 struct dc_plane_address *address)
09e5665a 3191{
320932bf 3192 const struct drm_framebuffer *fb = &afb->base;
09e5665a
NK		 3193 int ret;
3194
3195 memset(tiling_info, 0, sizeof(*tiling_info));
320932bf 3196 memset(plane_size, 0, sizeof(*plane_size));
09e5665a 3197 memset(dcc, 0, sizeof(*dcc));
e0634e8d
NK		 3198 memset(address, 0, sizeof(*address));
3199
695af5f9 3200 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 3201 plane_size->surface_size.x = 0;
3202 plane_size->surface_size.y = 0;
3203 plane_size->surface_size.width = fb->width;
3204 plane_size->surface_size.height = fb->height;
3205 plane_size->surface_pitch =
320932bf
NK		 3206 fb->pitches[0] / fb->format->cpp[0];
3207
e0634e8d
NK		 3208 address->type = PLN_ADDR_TYPE_GRAPHICS;
3209 address->grph.addr.low_part = lower_32_bits(afb->address);
3210 address->grph.addr.high_part = upper_32_bits(afb->address);
1894478a 3211 } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
1791e54f 3212 uint64_t chroma_addr = afb->address + fb->offsets[1];
e0634e8d 3213
12e2b2d4
DL		 3214 plane_size->surface_size.x = 0;
3215 plane_size->surface_size.y = 0;
3216 plane_size->surface_size.width = fb->width;
3217 plane_size->surface_size.height = fb->height;
3218 plane_size->surface_pitch =
320932bf
NK		 3219 fb->pitches[0] / fb->format->cpp[0];
3220
12e2b2d4
DL		 3221 plane_size->chroma_size.x = 0;
3222 plane_size->chroma_size.y = 0;
320932bf 3223 /* TODO: set these based on surface format */
12e2b2d4
DL		 3224 plane_size->chroma_size.width = fb->width / 2;
3225 plane_size->chroma_size.height = fb->height / 2;
320932bf 3226
12e2b2d4 3227 plane_size->chroma_pitch =
320932bf
NK		 3228 fb->pitches[1] / fb->format->cpp[1];
3229
e0634e8d
NK		 3230 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3231 address->video_progressive.luma_addr.low_part =
3232 lower_32_bits(afb->address);
3233 address->video_progressive.luma_addr.high_part =
3234 upper_32_bits(afb->address);
3235 address->video_progressive.chroma_addr.low_part =
3236 lower_32_bits(chroma_addr);
3237 address->video_progressive.chroma_addr.high_part =
3238 upper_32_bits(chroma_addr);
3239 }
09e5665a
NK		 3240
3241 /* Fill GFX8 params */
3242 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3243 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
3244
3245 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
3246 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
3247 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
3248 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
3249 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
3250
3251 /* XXX fix me for VI */
3252 tiling_info->gfx8.num_banks = num_banks;
3253 tiling_info->gfx8.array_mode =
3254 DC_ARRAY_2D_TILED_THIN1;
3255 tiling_info->gfx8.tile_split = tile_split;
3256 tiling_info->gfx8.bank_width = bankw;
3257 tiling_info->gfx8.bank_height = bankh;
3258 tiling_info->gfx8.tile_aspect = mtaspect;
3259 tiling_info->gfx8.tile_mode =
3260 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
3261 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
3262 == DC_ARRAY_1D_TILED_THIN1) {
3263 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
3264 }
3265
3266 tiling_info->gfx8.pipe_config =
3267 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
3268
3269 if (adev->asic_type == CHIP_VEGA10 ||
3270 adev->asic_type == CHIP_VEGA12 ||
3271 adev->asic_type == CHIP_VEGA20 ||
476e955d 3272 adev->asic_type == CHIP_NAVI10 ||
fce651e3 3273 adev->asic_type == CHIP_NAVI14 ||
fbd2afe5 3274 adev->asic_type == CHIP_NAVI12 ||
30221ad8 3275 adev->asic_type == CHIP_RENOIR ||
09e5665a
NK		 3276 adev->asic_type == CHIP_RAVEN) {
3277 /* Fill GFX9 params */
3278 tiling_info->gfx9.num_pipes =
3279 adev->gfx.config.gb_addr_config_fields.num_pipes;
3280 tiling_info->gfx9.num_banks =
3281 adev->gfx.config.gb_addr_config_fields.num_banks;
3282 tiling_info->gfx9.pipe_interleave =
3283 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3284 tiling_info->gfx9.num_shader_engines =
3285 adev->gfx.config.gb_addr_config_fields.num_se;
3286 tiling_info->gfx9.max_compressed_frags =
3287 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3288 tiling_info->gfx9.num_rb_per_se =
3289 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3290 tiling_info->gfx9.swizzle =
3291 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3292 tiling_info->gfx9.shaderEnable = 1;
3293
695af5f9
NK		 3294 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
3295 plane_size, tiling_info,
3296 tiling_flags, dcc, address);
09e5665a
NK		 3297 if (ret)
3298 return ret;
3299 }
3300
3301 return 0;
7df7e505
NK		 3302}
3303
d74004b6 3304static void
695af5f9 3305fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
d74004b6
NK		 3306 bool *per_pixel_alpha, bool *global_alpha,
3307 int *global_alpha_value)
3308{
3309 *per_pixel_alpha = false;
3310 *global_alpha = false;
3311 *global_alpha_value = 0xff;
3312
3313 if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
3314 return;
3315
3316 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
3317 static const uint32_t alpha_formats[] = {
3318 DRM_FORMAT_ARGB8888,
3319 DRM_FORMAT_RGBA8888,
3320 DRM_FORMAT_ABGR8888,
3321 };
3322 uint32_t format = plane_state->fb->format->format;
3323 unsigned int i;
3324
3325 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
3326 if (format == alpha_formats[i]) {
3327 *per_pixel_alpha = true;
3328 break;
3329 }
3330 }
3331 }
3332
3333 if (plane_state->alpha < 0xffff) {
3334 *global_alpha = true;
3335 *global_alpha_value = plane_state->alpha >> 8;
3336 }
3337}
3338
004fefa3
NK		 3339static int
3340fill_plane_color_attributes(const struct drm_plane_state *plane_state,
695af5f9 3341 const enum surface_pixel_format format,
004fefa3
NK		 3342 enum dc_color_space *color_space)
3343{
3344 bool full_range;
3345
3346 *color_space = COLOR_SPACE_SRGB;
3347
3348 /* DRM color properties only affect non-RGB formats. */
695af5f9 3349 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
004fefa3
NK		 3350 return 0;
3351
3352 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
3353
3354 switch (plane_state->color_encoding) {
3355 case DRM_COLOR_YCBCR_BT601:
3356 if (full_range)
3357 *color_space = COLOR_SPACE_YCBCR601;
3358 else
3359 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
3360 break;
3361
3362 case DRM_COLOR_YCBCR_BT709:
3363 if (full_range)
3364 *color_space = COLOR_SPACE_YCBCR709;
3365 else
3366 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
3367 break;
3368
3369 case DRM_COLOR_YCBCR_BT2020:
3370 if (full_range)
3371 *color_space = COLOR_SPACE_2020_YCBCR;
3372 else
3373 return -EINVAL;
3374 break;
3375
3376 default:
3377 return -EINVAL;
3378 }
3379
3380 return 0;
3381}
3382
695af5f9
NK		 3383static int
3384fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
3385 const struct drm_plane_state *plane_state,
3386 const uint64_t tiling_flags,
3387 struct dc_plane_info *plane_info,
3388 struct dc_plane_address *address)
3389{
3390 const struct drm_framebuffer *fb = plane_state->fb;
3391 const struct amdgpu_framebuffer *afb =
3392 to_amdgpu_framebuffer(plane_state->fb);
3393 struct drm_format_name_buf format_name;
3394 int ret;
3395
3396 memset(plane_info, 0, sizeof(*plane_info));
3397
3398 switch (fb->format->format) {
3399 case DRM_FORMAT_C8:
3400 plane_info->format =
3401 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
3402 break;
3403 case DRM_FORMAT_RGB565:
3404 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
3405 break;
3406 case DRM_FORMAT_XRGB8888:
3407 case DRM_FORMAT_ARGB8888:
3408 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
3409 break;
3410 case DRM_FORMAT_XRGB2101010:
3411 case DRM_FORMAT_ARGB2101010:
3412 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
3413 break;
3414 case DRM_FORMAT_XBGR2101010:
3415 case DRM_FORMAT_ABGR2101010:
3416 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
3417 break;
3418 case DRM_FORMAT_XBGR8888:
3419 case DRM_FORMAT_ABGR8888:
3420 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
3421 break;
3422 case DRM_FORMAT_NV21:
3423 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
3424 break;
3425 case DRM_FORMAT_NV12:
3426 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
3427 break;
3428 default:
3429 DRM_ERROR(
3430 "Unsupported screen format %s\n",
3431 drm_get_format_name(fb->format->format, &format_name));
3432 return -EINVAL;
3433 }
3434
3435 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3436 case DRM_MODE_ROTATE_0:
3437 plane_info->rotation = ROTATION_ANGLE_0;
3438 break;
3439 case DRM_MODE_ROTATE_90:
3440 plane_info->rotation = ROTATION_ANGLE_90;
3441 break;
3442 case DRM_MODE_ROTATE_180:
3443 plane_info->rotation = ROTATION_ANGLE_180;
3444 break;
3445 case DRM_MODE_ROTATE_270:
3446 plane_info->rotation = ROTATION_ANGLE_270;
3447 break;
3448 default:
3449 plane_info->rotation = ROTATION_ANGLE_0;
3450 break;
3451 }
3452
3453 plane_info->visible = true;
3454 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3455
6d83a32d
MS		 3456 plane_info->layer_index = 0;
3457
695af5f9
NK		 3458 ret = fill_plane_color_attributes(plane_state, plane_info->format,
3459 &plane_info->color_space);
3460 if (ret)
3461 return ret;
3462
3463 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3464 plane_info->rotation, tiling_flags,
3465 &plane_info->tiling_info,
3466 &plane_info->plane_size,
3467 &plane_info->dcc, address);
3468 if (ret)
3469 return ret;
3470
3471 fill_blending_from_plane_state(
3472 plane_state, &plane_info->per_pixel_alpha,
3473 &plane_info->global_alpha, &plane_info->global_alpha_value);
3474
3475 return 0;
3476}
3477
3478static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3479 struct dc_plane_state *dc_plane_state,
3480 struct drm_plane_state *plane_state,
3481 struct drm_crtc_state *crtc_state)
e7b07cee 3482{
cf020d49 3483 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
e7b07cee
HW		 3484 const struct amdgpu_framebuffer *amdgpu_fb =
3485 to_amdgpu_framebuffer(plane_state->fb);
695af5f9
NK		 3486 struct dc_scaling_info scaling_info;
3487 struct dc_plane_info plane_info;
3488 uint64_t tiling_flags;
3489 int ret;
e7b07cee 3490
695af5f9
NK		 3491 ret = fill_dc_scaling_info(plane_state, &scaling_info);
3492 if (ret)
3493 return ret;
e7b07cee 3494
695af5f9
NK		 3495 dc_plane_state->src_rect = scaling_info.src_rect;
3496 dc_plane_state->dst_rect = scaling_info.dst_rect;
3497 dc_plane_state->clip_rect = scaling_info.clip_rect;
3498 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
e7b07cee 3499
695af5f9 3500 ret = get_fb_info(amdgpu_fb, &tiling_flags);
e7b07cee
HW		 3501 if (ret)
3502 return ret;
3503
695af5f9
NK		 3504 ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3505 &plane_info,
3506 &dc_plane_state->address);
004fefa3
NK		 3507 if (ret)
3508 return ret;
3509
695af5f9
NK		 3510 dc_plane_state->format = plane_info.format;
3511 dc_plane_state->color_space = plane_info.color_space;
3512 dc_plane_state->format = plane_info.format;
3513 dc_plane_state->plane_size = plane_info.plane_size;
3514 dc_plane_state->rotation = plane_info.rotation;
3515 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3516 dc_plane_state->stereo_format = plane_info.stereo_format;
3517 dc_plane_state->tiling_info = plane_info.tiling_info;
3518 dc_plane_state->visible = plane_info.visible;
3519 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3520 dc_plane_state->global_alpha = plane_info.global_alpha;
3521 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3522 dc_plane_state->dcc = plane_info.dcc;
6d83a32d 3523 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
695af5f9 3524
e277adc5
LSL		 3525 /*
3526 * Always set input transfer function, since plane state is refreshed
3527 * every time.
3528 */
cf020d49
NK		 3529 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3530 if (ret)
3531 return ret;
e7b07cee 3532
cf020d49 3533 return 0;
e7b07cee
HW		 3534}
3535
3ee6b26b
AD		 3536static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3537 const struct dm_connector_state *dm_state,
3538 struct dc_stream_state *stream)
e7b07cee
HW		 3539{
3540 enum amdgpu_rmx_type rmx_type;
3541
3542 struct rect src = { 0 }; /* viewport in composition space*/
3543 struct rect dst = { 0 }; /* stream addressable area */
3544
3545 /* no mode. nothing to be done */
3546 if (!mode)
3547 return;
3548
3549 /* Full screen scaling by default */
3550 src.width = mode->hdisplay;
3551 src.height = mode->vdisplay;
3552 dst.width = stream->timing.h_addressable;
3553 dst.height = stream->timing.v_addressable;
3554
f4791779
HW		 3555 if (dm_state) {
3556 rmx_type = dm_state->scaling;
3557 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3558 if (src.width * dst.height <
3559 src.height * dst.width) {
3560 /* height needs less upscaling/more downscaling */
3561 dst.width = src.width *
3562 dst.height / src.height;
3563 } else {
3564 /* width needs less upscaling/more downscaling */
3565 dst.height = src.height *
3566 dst.width / src.width;
3567 }
3568 } else if (rmx_type == RMX_CENTER) {
3569 dst = src;
e7b07cee 3570 }
e7b07cee 3571
f4791779
HW		 3572 dst.x = (stream->timing.h_addressable - dst.width) / 2;
3573 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 3574
f4791779
HW		 3575 if (dm_state->underscan_enable) {
3576 dst.x += dm_state->underscan_hborder / 2;
3577 dst.y += dm_state->underscan_vborder / 2;
3578 dst.width -= dm_state->underscan_hborder;
3579 dst.height -= dm_state->underscan_vborder;
3580 }
e7b07cee
HW		 3581 }
3582
3583 stream->src = src;
3584 stream->dst = dst;
3585
f1ad2f5e 3586 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 3587 dst.x, dst.y, dst.width, dst.height);
3588
3589}
3590
3ee6b26b 3591static enum dc_color_depth
42ba01fc 3592convert_color_depth_from_display_info(const struct drm_connector *connector,
1bc22f20
SW		 3593 const struct drm_connector_state *state,
3594 bool is_y420)
e7b07cee 3595{
1bc22f20 3596 uint8_t bpc;
01c22997 3597
1bc22f20
SW		 3598 if (is_y420) {
3599 bpc = 8;
3600
3601 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
3602 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
3603 bpc = 16;
3604 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
3605 bpc = 12;
3606 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
3607 bpc = 10;
3608 } else {
3609 bpc = (uint8_t)connector->display_info.bpc;
3610 /* Assume 8 bpc by default if no bpc is specified. */
3611 bpc = bpc ? bpc : 8;
3612 }
e7b07cee 3613
01933ba4
NK		 3614 if (!state)
3615 state = connector->state;
3616
42ba01fc 3617 if (state) {
01c22997
NK		 3618 /*
3619 * Cap display bpc based on the user requested value.
3620 *
3621 * The value for state->max_bpc may not correctly updated
3622 * depending on when the connector gets added to the state
3623 * or if this was called outside of atomic check, so it
3624 * can't be used directly.
3625 */
3626 bpc = min(bpc, state->max_requested_bpc);
3627
1825fd34
NK		 3628 /* Round down to the nearest even number. */
3629 bpc = bpc - (bpc & 1);
3630 }
07e3a1cf 3631
e7b07cee
HW		 3632 switch (bpc) {
3633 case 0:
1f6010a9
DF		 3634 /*
3635 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 3636 * EDID revision before 1.4
3637 * TODO: Fix edid parsing
3638 */
3639 return COLOR_DEPTH_888;
3640 case 6:
3641 return COLOR_DEPTH_666;
3642 case 8:
3643 return COLOR_DEPTH_888;
3644 case 10:
3645 return COLOR_DEPTH_101010;
3646 case 12:
3647 return COLOR_DEPTH_121212;
3648 case 14:
3649 return COLOR_DEPTH_141414;
3650 case 16:
3651 return COLOR_DEPTH_161616;
3652 default:
3653 return COLOR_DEPTH_UNDEFINED;
3654 }
3655}
3656
3ee6b26b
AD		 3657static enum dc_aspect_ratio
3658get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 3659{
e11d4147
LSL		 3660 /* 1-1 mapping, since both enums follow the HDMI spec. */
3661 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 3662}
3663
3ee6b26b
AD		 3664static enum dc_color_space
3665get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 3666{
3667 enum dc_color_space color_space = COLOR_SPACE_SRGB;
3668
3669 switch (dc_crtc_timing->pixel_encoding) {
3670 case PIXEL_ENCODING_YCBCR422:
3671 case PIXEL_ENCODING_YCBCR444:
3672 case PIXEL_ENCODING_YCBCR420:
3673 {
3674 /*
3675 * 27030khz is the separation point between HDTV and SDTV
3676 * according to HDMI spec, we use YCbCr709 and YCbCr601
3677 * respectively
3678 */
380604e2 3679 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 3680 if (dc_crtc_timing->flags.Y_ONLY)
3681 color_space =
3682 COLOR_SPACE_YCBCR709_LIMITED;
3683 else
3684 color_space = COLOR_SPACE_YCBCR709;
3685 } else {
3686 if (dc_crtc_timing->flags.Y_ONLY)
3687 color_space =
3688 COLOR_SPACE_YCBCR601_LIMITED;
3689 else
3690 color_space = COLOR_SPACE_YCBCR601;
3691 }
3692
3693 }
3694 break;
3695 case PIXEL_ENCODING_RGB:
3696 color_space = COLOR_SPACE_SRGB;
3697 break;
3698
3699 default:
3700 WARN_ON(1);
3701 break;
3702 }
3703
3704 return color_space;
3705}
3706
ea117312
TA		 3707static bool adjust_colour_depth_from_display_info(
3708 struct dc_crtc_timing *timing_out,
3709 const struct drm_display_info *info)
400443e8 3710{
ea117312 3711 enum dc_color_depth depth = timing_out->display_color_depth;
400443e8 3712 int normalized_clk;
400443e8 3713 do {
380604e2 3714 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 3715 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3716 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3717 normalized_clk /= 2;
3718 /* Adjusting pix clock following on HDMI spec based on colour depth */
ea117312
TA		 3719 switch (depth) {
3720 case COLOR_DEPTH_888:
3721 break;
400443e8
ML		 3722 case COLOR_DEPTH_101010:
3723 normalized_clk = (normalized_clk * 30) / 24;
3724 break;
3725 case COLOR_DEPTH_121212:
3726 normalized_clk = (normalized_clk * 36) / 24;
3727 break;
3728 case COLOR_DEPTH_161616:
3729 normalized_clk = (normalized_clk * 48) / 24;
3730 break;
3731 default:
ea117312
TA		 3732 /* The above depths are the only ones valid for HDMI. */
3733 return false;
400443e8 3734 }
ea117312
TA		 3735 if (normalized_clk <= info->max_tmds_clock) {
3736 timing_out->display_color_depth = depth;
3737 return true;
3738 }
3739 } while (--depth > COLOR_DEPTH_666);
3740 return false;
400443e8 3741}
e7b07cee 3742
42ba01fc
NK		 3743static void fill_stream_properties_from_drm_display_mode(
3744 struct dc_stream_state *stream,
3745 const struct drm_display_mode *mode_in,
3746 const struct drm_connector *connector,
3747 const struct drm_connector_state *connector_state,
3748 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3749{
3750 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 3751 const struct drm_display_info *info = &connector->display_info;
d4252eee 3752 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1cb1d477
WL		 3753 struct hdmi_vendor_infoframe hv_frame;
3754 struct hdmi_avi_infoframe avi_frame;
e7b07cee 3755
acf83f86
WL		 3756 memset(&hv_frame, 0, sizeof(hv_frame));
3757 memset(&avi_frame, 0, sizeof(avi_frame));
3758
e7b07cee
HW		 3759 timing_out->h_border_left = 0;
3760 timing_out->h_border_right = 0;
3761 timing_out->v_border_top = 0;
3762 timing_out->v_border_bottom = 0;
3763 /* TODO: un-hardcode */
fe61a2f1 3764 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 3765 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1 3766 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
d4252eee
SW		 3767 else if (drm_mode_is_420_also(info, mode_in)
3768 && aconnector->force_yuv420_output)
3769 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
fe61a2f1 3770 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 3771 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 3772 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3773 else
3774 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3775
3776 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3777 timing_out->display_color_depth = convert_color_depth_from_display_info(
1bc22f20
SW		 3778 connector, connector_state,
3779 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420));
e7b07cee
HW		 3780 timing_out->scan_type = SCANNING_TYPE_NODATA;
3781 timing_out->hdmi_vic = 0;
b333730d
BL		 3782
3783 if(old_stream) {
3784 timing_out->vic = old_stream->timing.vic;
3785 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3786 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3787 } else {
3788 timing_out->vic = drm_match_cea_mode(mode_in);
3789 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3790 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3791 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3792 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3793 }
e7b07cee 3794
1cb1d477
WL		 3795 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3796 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
3797 timing_out->vic = avi_frame.video_code;
3798 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
3799 timing_out->hdmi_vic = hv_frame.vic;
3800 }
3801
e7b07cee
HW		 3802 timing_out->h_addressable = mode_in->crtc_hdisplay;
3803 timing_out->h_total = mode_in->crtc_htotal;
3804 timing_out->h_sync_width =
3805 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3806 timing_out->h_front_porch =
3807 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3808 timing_out->v_total = mode_in->crtc_vtotal;
3809 timing_out->v_addressable = mode_in->crtc_vdisplay;
3810 timing_out->v_front_porch =
3811 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3812 timing_out->v_sync_width =
3813 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 3814 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 3815 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 3816
3817 stream->output_color_space = get_output_color_space(timing_out);
3818
e43a432c
AK		 3819 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3820 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ea117312
TA		 3821 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3822 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
3823 drm_mode_is_420_also(info, mode_in) &&
3824 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
3825 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3826 adjust_colour_depth_from_display_info(timing_out, info);
3827 }
3828 }
e7b07cee
HW		 3829}
3830
3ee6b26b
AD		 3831static void fill_audio_info(struct audio_info *audio_info,
3832 const struct drm_connector *drm_connector,
3833 const struct dc_sink *dc_sink)
e7b07cee
HW		 3834{
3835 int i = 0;
3836 int cea_revision = 0;
3837 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3838
3839 audio_info->manufacture_id = edid_caps->manufacturer_id;
3840 audio_info->product_id = edid_caps->product_id;
3841
3842 cea_revision = drm_connector->display_info.cea_rev;
3843
090afc1e 3844 strscpy(audio_info->display_name,
d2b2562c 3845 edid_caps->display_name,
090afc1e 3846 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 3847
b830ebc9 3848 if (cea_revision >= 3) {
e7b07cee
HW		 3849 audio_info->mode_count = edid_caps->audio_mode_count;
3850
3851 for (i = 0; i < audio_info->mode_count; ++i) {
3852 audio_info->modes[i].format_code =
3853 (enum audio_format_code)
3854 (edid_caps->audio_modes[i].format_code);
3855 audio_info->modes[i].channel_count =
3856 edid_caps->audio_modes[i].channel_count;
3857 audio_info->modes[i].sample_rates.all =
3858 edid_caps->audio_modes[i].sample_rate;
3859 audio_info->modes[i].sample_size =
3860 edid_caps->audio_modes[i].sample_size;
3861 }
3862 }
3863
3864 audio_info->flags.all = edid_caps->speaker_flags;
3865
3866 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 3867 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 3868 audio_info->video_latency = drm_connector->video_latency[0];
3869 audio_info->audio_latency = drm_connector->audio_latency[0];
3870 }
3871
3872 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3873
3874}
3875
3ee6b26b
AD		 3876static void
3877copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3878 struct drm_display_mode *dst_mode)
e7b07cee
HW		 3879{
3880 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3881 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3882 dst_mode->crtc_clock = src_mode->crtc_clock;
3883 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3884 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 3885 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 3886 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3887 dst_mode->crtc_htotal = src_mode->crtc_htotal;
3888 dst_mode->crtc_hskew = src_mode->crtc_hskew;
3889 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3890 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3891 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3892 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3893 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3894}
3895
3ee6b26b
AD		 3896static void
3897decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3898 const struct drm_display_mode *native_mode,
3899 bool scale_enabled)
e7b07cee
HW		 3900{
3901 if (scale_enabled) {
3902 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3903 } else if (native_mode->clock == drm_mode->clock &&
3904 native_mode->htotal == drm_mode->htotal &&
3905 native_mode->vtotal == drm_mode->vtotal) {
3906 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3907 } else {
3908 /* no scaling nor amdgpu inserted, no need to patch */
3909 }
3910}
3911
aed15309
ML		 3912static struct dc_sink *
3913create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 3914{
2e0ac3d6 3915 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 3916 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 3917 sink_init_data.link = aconnector->dc_link;
3918 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3919
3920 sink = dc_sink_create(&sink_init_data);
423788c7 3921 if (!sink) {
2e0ac3d6 3922 DRM_ERROR("Failed to create sink!\n");
aed15309 3923 return NULL;
423788c7 3924 }
2e0ac3d6 3925 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 3926
aed15309 3927 return sink;
2e0ac3d6
HW		 3928}
3929
fa2123db
ML		 3930static void set_multisync_trigger_params(
3931 struct dc_stream_state *stream)
3932{
3933 if (stream->triggered_crtc_reset.enabled) {
3934 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3935 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3936 }
3937}
3938
3939static void set_master_stream(struct dc_stream_state *stream_set[],
3940 int stream_count)
3941{
3942 int j, highest_rfr = 0, master_stream = 0;
3943
3944 for (j = 0; j < stream_count; j++) {
3945 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3946 int refresh_rate = 0;
3947
380604e2 3948 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 3949 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3950 if (refresh_rate > highest_rfr) {
3951 highest_rfr = refresh_rate;
3952 master_stream = j;
3953 }
3954 }
3955 }
3956 for (j = 0; j < stream_count; j++) {
03736f4c 3957 if (stream_set[j])
fa2123db
ML		 3958 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3959 }
3960}
3961
3962static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3963{
3964 int i = 0;
3965
3966 if (context->stream_count < 2)
3967 return;
3968 for (i = 0; i < context->stream_count ; i++) {
3969 if (!context->streams[i])
3970 continue;
1f6010a9
DF		 3971 /*
3972 * TODO: add a function to read AMD VSDB bits and set
fa2123db 3973 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 3974 * For now it's set to false
fa2123db
ML		 3975 */
3976 set_multisync_trigger_params(context->streams[i]);
3977 }
3978 set_master_stream(context->streams, context->stream_count);
3979}
3980
3ee6b26b
AD		 3981static struct dc_stream_state *
3982create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3983 const struct drm_display_mode *drm_mode,
b333730d
BL		 3984 const struct dm_connector_state *dm_state,
3985 const struct dc_stream_state *old_stream)
e7b07cee
HW		 3986{
3987 struct drm_display_mode *preferred_mode = NULL;
391ef035 3988 struct drm_connector *drm_connector;
42ba01fc
NK		 3989 const struct drm_connector_state *con_state =
3990 dm_state ? &dm_state->base : NULL;
0971c40e 3991 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 3992 struct drm_display_mode mode = *drm_mode;
3993 bool native_mode_found = false;
b333730d
BL		 3994 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3995 int mode_refresh;
58124bf8 3996 int preferred_refresh = 0;
defeb878 3997#if defined(CONFIG_DRM_AMD_DC_DCN)
df2f1015 3998 struct dsc_dec_dpcd_caps dsc_caps;
df2f1015 3999#endif
df2f1015 4000 uint32_t link_bandwidth_kbps;
b333730d 4001
aed15309 4002 struct dc_sink *sink = NULL;
b830ebc9 4003 if (aconnector == NULL) {
e7b07cee 4004 DRM_ERROR("aconnector is NULL!\n");
64245fa7 4005 return stream;
e7b07cee
HW		 4006 }
4007
e7b07cee 4008 drm_connector = &aconnector->base;
2e0ac3d6 4009
f4ac176e 4010 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 4011 sink = create_fake_sink(aconnector);
4012 if (!sink)
4013 return stream;
aed15309
ML		 4014 } else {
4015 sink = aconnector->dc_sink;
dcd5fb82 4016 dc_sink_retain(sink);
f4ac176e 4017 }
2e0ac3d6 4018
aed15309 4019 stream = dc_create_stream_for_sink(sink);
4562236b 4020
b830ebc9 4021 if (stream == NULL) {
e7b07cee 4022 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 4023 goto finish;
e7b07cee
HW		 4024 }
4025
ceb3dbb4
JL		 4026 stream->dm_stream_context = aconnector;
4027
4a36fcba
WL		 4028 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
4029 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
4030
e7b07cee
HW		 4031 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
4032 /* Search for preferred mode */
4033 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
4034 native_mode_found = true;
4035 break;
4036 }
4037 }
4038 if (!native_mode_found)
4039 preferred_mode = list_first_entry_or_null(
4040 &aconnector->base.modes,
4041 struct drm_display_mode,
4042 head);
4043
b333730d
BL		 4044 mode_refresh = drm_mode_vrefresh(&mode);
4045
b830ebc9 4046 if (preferred_mode == NULL) {
1f6010a9
DF		 4047 /*
4048 * This may not be an error, the use case is when we have no
e7b07cee
HW		 4049 * usermode calls to reset and set mode upon hotplug. In this
4050 * case, we call set mode ourselves to restore the previous mode
4051 * and the modelist may not be filled in in time.
4052 */
f1ad2f5e 4053 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 4054 } else {
4055 decide_crtc_timing_for_drm_display_mode(
4056 &mode, preferred_mode,
f4791779 4057 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 4058 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 4059 }
4060
f783577c
JFZ		 4061 if (!dm_state)
4062 drm_mode_set_crtcinfo(&mode, 0);
4063
b333730d
BL		 4064 /*
4065 * If scaling is enabled and refresh rate didn't change
4066 * we copy the vic and polarities of the old timings
4067 */
4068 if (!scale || mode_refresh != preferred_refresh)
4069 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 4070 &mode, &aconnector->base, con_state, NULL);
b333730d
BL		 4071 else
4072 fill_stream_properties_from_drm_display_mode(stream,
42ba01fc 4073 &mode, &aconnector->base, con_state, old_stream);
b333730d 4074
df2f1015
DF		 4075 stream->timing.flags.DSC = 0;
4076
4077 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
defeb878 4078#if defined(CONFIG_DRM_AMD_DC_DCN)
2af0f378
NC		 4079 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
4080 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
df2f1015
DF		 4081 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
4082 &dsc_caps);
defeb878 4083#endif
df2f1015
DF		 4084 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
4085 dc_link_get_link_cap(aconnector->dc_link));
4086
defeb878 4087#if defined(CONFIG_DRM_AMD_DC_DCN)
df2f1015 4088 if (dsc_caps.is_dsc_supported)
0417df16 4089 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
df2f1015 4090 &dsc_caps,
0417df16 4091 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
df2f1015
DF		 4092 link_bandwidth_kbps,
4093 &stream->timing,
4094 &stream->timing.dsc_cfg))
4095 stream->timing.flags.DSC = 1;
39a4eb85 4096#endif
df2f1015 4097 }
39a4eb85 4098
e7b07cee
HW		 4099 update_stream_scaling_settings(&mode, dm_state, stream);
4100
4101 fill_audio_info(
4102 &stream->audio_info,
4103 drm_connector,
aed15309 4104 sink);
e7b07cee 4105
ceb3dbb4 4106 update_stream_signal(stream, sink);
9182b4cb 4107
d832fc3b
WL		 4108 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
4109 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
8c322309
RL		 4110 if (stream->link->psr_feature_enabled) {
4111 struct dc *core_dc = stream->link->ctx->dc;
d832fc3b 4112
8c322309
RL		 4113 if (dc_is_dmcu_initialized(core_dc)) {
4114 struct dmcu *dmcu = core_dc->res_pool->dmcu;
4115
4116 stream->psr_version = dmcu->dmcu_version.psr_version;
5ed78cd6
AK		 4117 mod_build_vsc_infopacket(stream,
4118 &stream->vsc_infopacket,
4119 &stream->use_vsc_sdp_for_colorimetry);
8c322309
RL		 4120 }
4121 }
aed15309 4122finish:
dcd5fb82 4123 dc_sink_release(sink);
9e3efe3e 4124
e7b07cee
HW		 4125 return stream;
4126}
4127
7578ecda 4128static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 4129{
4130 drm_crtc_cleanup(crtc);
4131 kfree(crtc);
4132}
4133
4134static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 4135 struct drm_crtc_state *state)
e7b07cee
HW		 4136{
4137 struct dm_crtc_state *cur = to_dm_crtc_state(state);
4138
4139 /* TODO Destroy dc_stream objects are stream object is flattened */
4140 if (cur->stream)
4141 dc_stream_release(cur->stream);
4142
4143
4144 __drm_atomic_helper_crtc_destroy_state(state);
4145
4146
4147 kfree(state);
4148}
4149
4150static void dm_crtc_reset_state(struct drm_crtc *crtc)
4151{
4152 struct dm_crtc_state *state;
4153
4154 if (crtc->state)
4155 dm_crtc_destroy_state(crtc, crtc->state);
4156
4157 state = kzalloc(sizeof(*state), GFP_KERNEL);
4158 if (WARN_ON(!state))
4159 return;
4160
4161 crtc->state = &state->base;
4162 crtc->state->crtc = crtc;
4163
4164}
4165
4166static struct drm_crtc_state *
4167dm_crtc_duplicate_state(struct drm_crtc *crtc)
4168{
4169 struct dm_crtc_state *state, *cur;
4170
4171 cur = to_dm_crtc_state(crtc->state);
4172
4173 if (WARN_ON(!crtc->state))
4174 return NULL;
4175
2004f45e 4176 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 4177 if (!state)
4178 return NULL;
e7b07cee
HW		 4179
4180 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
4181
4182 if (cur->stream) {
4183 state->stream = cur->stream;
4184 dc_stream_retain(state->stream);
4185 }
4186
d6ef9b41
NK		 4187 state->active_planes = cur->active_planes;
4188 state->interrupts_enabled = cur->interrupts_enabled;
180db303 4189 state->vrr_params = cur->vrr_params;
98e6436d 4190 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 4191 state->abm_level = cur->abm_level;
bb47de73
NK		 4192 state->vrr_supported = cur->vrr_supported;
4193 state->freesync_config = cur->freesync_config;
14b25846 4194 state->crc_src = cur->crc_src;
cf020d49
NK		 4195 state->cm_has_degamma = cur->cm_has_degamma;
4196 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
98e6436d 4197
e7b07cee
HW		 4198 /* TODO Duplicate dc_stream after objects are stream object is flattened */
4199
4200 return &state->base;
4201}
4202
d2574c33
MK		 4203static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
4204{
4205 enum dc_irq_source irq_source;
4206 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4207 struct amdgpu_device *adev = crtc->dev->dev_private;
4208 int rc;
4209
3a2ce8d6
LL		 4210 /* Do not set vupdate for DCN hardware */
4211 if (adev->family > AMDGPU_FAMILY_AI)
4212 return 0;
4213
d2574c33
MK		 4214 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
4215
4216 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4217
4218 DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
4219 acrtc->crtc_id, enable ? "en" : "dis", rc);
4220 return rc;
4221}
589d2739
HW		 4222
4223static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
4224{
4225 enum dc_irq_source irq_source;
4226 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4227 struct amdgpu_device *adev = crtc->dev->dev_private;
d2574c33
MK		 4228 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
4229 int rc = 0;
4230
4231 if (enable) {
4232 /* vblank irq on -> Only need vupdate irq in vrr mode */
4233 if (amdgpu_dm_vrr_active(acrtc_state))
4234 rc = dm_set_vupdate_irq(crtc, true);
4235 } else {
4236 /* vblank irq off -> vupdate irq off */
4237 rc = dm_set_vupdate_irq(crtc, false);
4238 }
4239
4240 if (rc)
4241 return rc;
589d2739
HW		 4242
4243 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 4244 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 4245}
4246
4247static int dm_enable_vblank(struct drm_crtc *crtc)
4248{
4249 return dm_set_vblank(crtc, true);
4250}
4251
4252static void dm_disable_vblank(struct drm_crtc *crtc)
4253{
4254 dm_set_vblank(crtc, false);
4255}
4256
e7b07cee
HW		 4257/* Implemented only the options currently availible for the driver */
4258static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
4259 .reset = dm_crtc_reset_state,
4260 .destroy = amdgpu_dm_crtc_destroy,
4261 .gamma_set = drm_atomic_helper_legacy_gamma_set,
4262 .set_config = drm_atomic_helper_set_config,
4263 .page_flip = drm_atomic_helper_page_flip,
4264 .atomic_duplicate_state = dm_crtc_duplicate_state,
4265 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 4266 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 4267 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
8fb843d1 4268 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
589d2739
HW		 4269 .enable_vblank = dm_enable_vblank,
4270 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 4271};
4272
4273static enum drm_connector_status
4274amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
4275{
4276 bool connected;
c84dec2f 4277 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 4278
1f6010a9
DF		 4279 /*
4280 * Notes:
e7b07cee
HW		 4281 * 1. This interface is NOT called in context of HPD irq.
4282 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 4283 * makes it a bad place for *any* MST-related activity.
4284 */
e7b07cee 4285
8580d60b
HW		 4286 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
4287 !aconnector->fake_enable)
e7b07cee
HW		 4288 connected = (aconnector->dc_sink != NULL);
4289 else
4290 connected = (aconnector->base.force == DRM_FORCE_ON);
4291
4292 return (connected ? connector_status_connected :
4293 connector_status_disconnected);
4294}
4295
3ee6b26b
AD		 4296int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
4297 struct drm_connector_state *connector_state,
4298 struct drm_property *property,
4299 uint64_t val)
e7b07cee
HW		 4300{
4301 struct drm_device *dev = connector->dev;
4302 struct amdgpu_device *adev = dev->dev_private;
4303 struct dm_connector_state *dm_old_state =
4304 to_dm_connector_state(connector->state);
4305 struct dm_connector_state *dm_new_state =
4306 to_dm_connector_state(connector_state);
4307
4308 int ret = -EINVAL;
4309
4310 if (property == dev->mode_config.scaling_mode_property) {
4311 enum amdgpu_rmx_type rmx_type;
4312
4313 switch (val) {
4314 case DRM_MODE_SCALE_CENTER:
4315 rmx_type = RMX_CENTER;
4316 break;
4317 case DRM_MODE_SCALE_ASPECT:
4318 rmx_type = RMX_ASPECT;
4319 break;
4320 case DRM_MODE_SCALE_FULLSCREEN:
4321 rmx_type = RMX_FULL;
4322 break;
4323 case DRM_MODE_SCALE_NONE:
4324 default:
4325 rmx_type = RMX_OFF;
4326 break;
4327 }
4328
4329 if (dm_old_state->scaling == rmx_type)
4330 return 0;
4331
4332 dm_new_state->scaling = rmx_type;
4333 ret = 0;
4334 } else if (property == adev->mode_info.underscan_hborder_property) {
4335 dm_new_state->underscan_hborder = val;
4336 ret = 0;
4337 } else if (property == adev->mode_info.underscan_vborder_property) {
4338 dm_new_state->underscan_vborder = val;
4339 ret = 0;
4340 } else if (property == adev->mode_info.underscan_property) {
4341 dm_new_state->underscan_enable = val;
4342 ret = 0;
c1ee92f9
DF		 4343 } else if (property == adev->mode_info.abm_level_property) {
4344 dm_new_state->abm_level = val;
4345 ret = 0;
e7b07cee
HW		 4346 }
4347
4348 return ret;
4349}
4350
3ee6b26b
AD		 4351int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
4352 const struct drm_connector_state *state,
4353 struct drm_property *property,
4354 uint64_t *val)
e7b07cee
HW		 4355{
4356 struct drm_device *dev = connector->dev;
4357 struct amdgpu_device *adev = dev->dev_private;
4358 struct dm_connector_state *dm_state =
4359 to_dm_connector_state(state);
4360 int ret = -EINVAL;
4361
4362 if (property == dev->mode_config.scaling_mode_property) {
4363 switch (dm_state->scaling) {
4364 case RMX_CENTER:
4365 *val = DRM_MODE_SCALE_CENTER;
4366 break;
4367 case RMX_ASPECT:
4368 *val = DRM_MODE_SCALE_ASPECT;
4369 break;
4370 case RMX_FULL:
4371 *val = DRM_MODE_SCALE_FULLSCREEN;
4372 break;
4373 case RMX_OFF:
4374 default:
4375 *val = DRM_MODE_SCALE_NONE;
4376 break;
4377 }
4378 ret = 0;
4379 } else if (property == adev->mode_info.underscan_hborder_property) {
4380 *val = dm_state->underscan_hborder;
4381 ret = 0;
4382 } else if (property == adev->mode_info.underscan_vborder_property) {
4383 *val = dm_state->underscan_vborder;
4384 ret = 0;
4385 } else if (property == adev->mode_info.underscan_property) {
4386 *val = dm_state->underscan_enable;
4387 ret = 0;
c1ee92f9
DF		 4388 } else if (property == adev->mode_info.abm_level_property) {
4389 *val = dm_state->abm_level;
4390 ret = 0;
e7b07cee 4391 }
c1ee92f9 4392
e7b07cee
HW		 4393 return ret;
4394}
4395
526c654a
ED		 4396static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
4397{
4398 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
4399
4400 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
4401}
4402
7578ecda 4403static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 4404{
c84dec2f 4405 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4406 const struct dc_link *link = aconnector->dc_link;
4407 struct amdgpu_device *adev = connector->dev->dev_private;
4408 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 4409
e7b07cee
HW		 4410#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
4411 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
4412
89fc8d4e 4413 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 4414 link->type != dc_connection_none &&
4415 dm->backlight_dev) {
4416 backlight_device_unregister(dm->backlight_dev);
4417 dm->backlight_dev = NULL;
e7b07cee
HW		 4418 }
4419#endif
dcd5fb82
MF		 4420
4421 if (aconnector->dc_em_sink)
4422 dc_sink_release(aconnector->dc_em_sink);
4423 aconnector->dc_em_sink = NULL;
4424 if (aconnector->dc_sink)
4425 dc_sink_release(aconnector->dc_sink);
4426 aconnector->dc_sink = NULL;
4427
e86e8947 4428 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 4429 drm_connector_unregister(connector);
4430 drm_connector_cleanup(connector);
526c654a
ED		 4431 if (aconnector->i2c) {
4432 i2c_del_adapter(&aconnector->i2c->base);
4433 kfree(aconnector->i2c);
4434 }
4435
e7b07cee
HW		 4436 kfree(connector);
4437}
4438
4439void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
4440{
4441 struct dm_connector_state *state =
4442 to_dm_connector_state(connector->state);
4443
df099b9b
LSL		 4444 if (connector->state)
4445 __drm_atomic_helper_connector_destroy_state(connector->state);
4446
e7b07cee
HW		 4447 kfree(state);
4448
4449 state = kzalloc(sizeof(*state), GFP_KERNEL);
4450
4451 if (state) {
4452 state->scaling = RMX_OFF;
4453 state->underscan_enable = false;
4454 state->underscan_hborder = 0;
4455 state->underscan_vborder = 0;
01933ba4 4456 state->base.max_requested_bpc = 8;
3261e013
ML		 4457 state->vcpi_slots = 0;
4458 state->pbn = 0;
c3e50f89
NK		 4459 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4460 state->abm_level = amdgpu_dm_abm_level;
4461
df099b9b 4462 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 4463 }
4464}
4465
3ee6b26b
AD		 4466struct drm_connector_state *
4467amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 4468{
4469 struct dm_connector_state *state =
4470 to_dm_connector_state(connector->state);
4471
4472 struct dm_connector_state *new_state =
4473 kmemdup(state, sizeof(*state), GFP_KERNEL);
4474
98e6436d
AK		 4475 if (!new_state)
4476 return NULL;
e7b07cee 4477
98e6436d
AK		 4478 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
4479
4480 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 4481 new_state->abm_level = state->abm_level;
922454c2
NK		 4482 new_state->scaling = state->scaling;
4483 new_state->underscan_enable = state->underscan_enable;
4484 new_state->underscan_hborder = state->underscan_hborder;
4485 new_state->underscan_vborder = state->underscan_vborder;
3261e013
ML		 4486 new_state->vcpi_slots = state->vcpi_slots;
4487 new_state->pbn = state->pbn;
98e6436d 4488 return &new_state->base;
e7b07cee
HW		 4489}
4490
4491static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4492 .reset = amdgpu_dm_connector_funcs_reset,
4493 .detect = amdgpu_dm_connector_detect,
4494 .fill_modes = drm_helper_probe_single_connector_modes,
4495 .destroy = amdgpu_dm_connector_destroy,
4496 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4497 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4498 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
526c654a
ED		 4499 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4500 .early_unregister = amdgpu_dm_connector_unregister
e7b07cee
HW		 4501};
4502
e7b07cee
HW		 4503static int get_modes(struct drm_connector *connector)
4504{
4505 return amdgpu_dm_connector_get_modes(connector);
4506}
4507
c84dec2f 4508static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 4509{
4510 struct dc_sink_init_data init_params = {
4511 .link = aconnector->dc_link,
4512 .sink_signal = SIGNAL_TYPE_VIRTUAL
4513 };
70e8ffc5 4514 struct edid *edid;
e7b07cee 4515
a89ff457 4516 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 4517 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4518 aconnector->base.name);
4519
4520 aconnector->base.force = DRM_FORCE_OFF;
4521 aconnector->base.override_edid = false;
4522 return;
4523 }
4524
70e8ffc5
HW		 4525 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4526
e7b07cee
HW		 4527 aconnector->edid = edid;
4528
4529 aconnector->dc_em_sink = dc_link_add_remote_sink(
4530 aconnector->dc_link,
4531 (uint8_t *)edid,
4532 (edid->extensions + 1) * EDID_LENGTH,
4533 &init_params);
4534
dcd5fb82 4535 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 4536 aconnector->dc_sink = aconnector->dc_link->local_sink ?
4537 aconnector->dc_link->local_sink :
4538 aconnector->dc_em_sink;
dcd5fb82
MF		 4539 dc_sink_retain(aconnector->dc_sink);
4540 }
e7b07cee
HW		 4541}
4542
c84dec2f 4543static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 4544{
4545 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4546
1f6010a9
DF		 4547 /*
4548 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 4549 * Those settings have to be != 0 to get initial modeset
4550 */
4551 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4552 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4553 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4554 }
4555
4556
4557 aconnector->base.override_edid = true;
4558 create_eml_sink(aconnector);
4559}
4560
ba9ca088 4561enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 4562 struct drm_display_mode *mode)
e7b07cee
HW		 4563{
4564 int result = MODE_ERROR;
4565 struct dc_sink *dc_sink;
4566 struct amdgpu_device *adev = connector->dev->dev_private;
4567 /* TODO: Unhardcode stream count */
0971c40e 4568 struct dc_stream_state *stream;
c84dec2f 4569 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 4570 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 4571
4572 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4573 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4574 return result;
4575
1f6010a9
DF		 4576 /*
4577 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 4578 * EDID mgmt
4579 */
4580 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4581 !aconnector->dc_em_sink)
4582 handle_edid_mgmt(aconnector);
4583
c84dec2f 4584 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 4585
b830ebc9 4586 if (dc_sink == NULL) {
e7b07cee
HW		 4587 DRM_ERROR("dc_sink is NULL!\n");
4588 goto fail;
4589 }
4590
b333730d 4591 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 4592 if (stream == NULL) {
e7b07cee
HW		 4593 DRM_ERROR("Failed to create stream for sink!\n");
4594 goto fail;
4595 }
4596
a39438f0
HW		 4597 dc_result = dc_validate_stream(adev->dm.dc, stream);
4598
4599 if (dc_result == DC_OK)
e7b07cee 4600 result = MODE_OK;
a39438f0 4601 else
9f921b14 4602 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0 4603 mode->hdisplay,
26e99ba6 4604 mode->vdisplay,
9f921b14
HW		 4605 mode->clock,
4606 dc_result);
e7b07cee
HW		 4607
4608 dc_stream_release(stream);
4609
4610fail:
4611 /* TODO: error handling*/
4612 return result;
4613}
4614
88694af9
NK		 4615static int fill_hdr_info_packet(const struct drm_connector_state *state,
4616 struct dc_info_packet *out)
4617{
4618 struct hdmi_drm_infoframe frame;
4619 unsigned char buf[30]; /* 26 + 4 */
4620 ssize_t len;
4621 int ret, i;
4622
4623 memset(out, 0, sizeof(*out));
4624
4625 if (!state->hdr_output_metadata)
4626 return 0;
4627
4628 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4629 if (ret)
4630 return ret;
4631
4632 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4633 if (len < 0)
4634 return (int)len;
4635
4636 /* Static metadata is a fixed 26 bytes + 4 byte header. */
4637 if (len != 30)
4638 return -EINVAL;
4639
4640 /* Prepare the infopacket for DC. */
4641 switch (state->connector->connector_type) {
4642 case DRM_MODE_CONNECTOR_HDMIA:
4643 out->hb0 = 0x87; /* type */
4644 out->hb1 = 0x01; /* version */
4645 out->hb2 = 0x1A; /* length */
4646 out->sb[0] = buf[3]; /* checksum */
4647 i = 1;
4648 break;
4649
4650 case DRM_MODE_CONNECTOR_DisplayPort:
4651 case DRM_MODE_CONNECTOR_eDP:
4652 out->hb0 = 0x00; /* sdp id, zero */
4653 out->hb1 = 0x87; /* type */
4654 out->hb2 = 0x1D; /* payload len - 1 */
4655 out->hb3 = (0x13 << 2); /* sdp version */
4656 out->sb[0] = 0x01; /* version */
4657 out->sb[1] = 0x1A; /* length */
4658 i = 2;
4659 break;
4660
4661 default:
4662 return -EINVAL;
4663 }
4664
4665 memcpy(&out->sb[i], &buf[4], 26);
4666 out->valid = true;
4667
4668 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4669 sizeof(out->sb), false);
4670
4671 return 0;
4672}
4673
4674static bool
4675is_hdr_metadata_different(const struct drm_connector_state *old_state,
4676 const struct drm_connector_state *new_state)
4677{
4678 struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4679 struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4680
4681 if (old_blob != new_blob) {
4682 if (old_blob && new_blob &&
4683 old_blob->length == new_blob->length)
4684 return memcmp(old_blob->data, new_blob->data,
4685 old_blob->length);
4686
4687 return true;
4688 }
4689
4690 return false;
4691}
4692
4693static int
4694amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
51e857af 4695 struct drm_atomic_state *state)
88694af9 4696{
51e857af
SP		 4697 struct drm_connector_state *new_con_state =
4698 drm_atomic_get_new_connector_state(state, conn);
88694af9
NK		 4699 struct drm_connector_state *old_con_state =
4700 drm_atomic_get_old_connector_state(state, conn);
4701 struct drm_crtc *crtc = new_con_state->crtc;
4702 struct drm_crtc_state *new_crtc_state;
4703 int ret;
4704
4705 if (!crtc)
4706 return 0;
4707
4708 if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4709 struct dc_info_packet hdr_infopacket;
4710
4711 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4712 if (ret)
4713 return ret;
4714
4715 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4716 if (IS_ERR(new_crtc_state))
4717 return PTR_ERR(new_crtc_state);
4718
4719 /*
4720 * DC considers the stream backends changed if the
4721 * static metadata changes. Forcing the modeset also
4722 * gives a simple way for userspace to switch from
b232d4ed
NK		 4723 * 8bpc to 10bpc when setting the metadata to enter
4724 * or exit HDR.
4725 *
4726 * Changing the static metadata after it's been
4727 * set is permissible, however. So only force a
4728 * modeset if we're entering or exiting HDR.
88694af9 4729 */
b232d4ed
NK		 4730 new_crtc_state->mode_changed =
4731 !old_con_state->hdr_output_metadata ||
4732 !new_con_state->hdr_output_metadata;
88694af9
NK		 4733 }
4734
4735 return 0;
4736}
4737
e7b07cee
HW		 4738static const struct drm_connector_helper_funcs
4739amdgpu_dm_connector_helper_funcs = {
4740 /*
1f6010a9 4741 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 4742 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 4743 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 4744 * in get_modes call back, not just return the modes count
4745 */
e7b07cee
HW		 4746 .get_modes = get_modes,
4747 .mode_valid = amdgpu_dm_connector_mode_valid,
88694af9 4748 .atomic_check = amdgpu_dm_connector_atomic_check,
e7b07cee
HW		 4749};
4750
4751static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4752{
4753}
4754
bc92c065
NK		 4755static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4756{
4757 struct drm_device *dev = new_crtc_state->crtc->dev;
4758 struct drm_plane *plane;
4759
4760 drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4761 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4762 return true;
4763 }
4764
4765 return false;
4766}
4767
d6ef9b41 4768static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
c14a005c
NK		 4769{
4770 struct drm_atomic_state *state = new_crtc_state->state;
4771 struct drm_plane *plane;
4772 int num_active = 0;
4773
4774 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4775 struct drm_plane_state *new_plane_state;
4776
4777 /* Cursor planes are "fake". */
4778 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4779 continue;
4780
4781 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4782
4783 if (!new_plane_state) {
4784 /*
4785 * The plane is enable on the CRTC and hasn't changed
4786 * state. This means that it previously passed
4787 * validation and is therefore enabled.
4788 */
4789 num_active += 1;
4790 continue;
4791 }
4792
4793 /* We need a framebuffer to be considered enabled. */
4794 num_active += (new_plane_state->fb != NULL);
4795 }
4796
d6ef9b41
NK		 4797 return num_active;
4798}
4799
4800/*
4801 * Sets whether interrupts should be enabled on a specific CRTC.
4802 * We require that the stream be enabled and that there exist active
4803 * DC planes on the stream.
4804 */
4805static void
4806dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4807 struct drm_crtc_state *new_crtc_state)
4808{
4809 struct dm_crtc_state *dm_new_crtc_state =
4810 to_dm_crtc_state(new_crtc_state);
4811
4812 dm_new_crtc_state->active_planes = 0;
4813 dm_new_crtc_state->interrupts_enabled = false;
4814
4815 if (!dm_new_crtc_state->stream)
4816 return;
4817
4818 dm_new_crtc_state->active_planes =
4819 count_crtc_active_planes(new_crtc_state);
4820
4821 dm_new_crtc_state->interrupts_enabled =
4822 dm_new_crtc_state->active_planes > 0;
c14a005c
NK		 4823}
4824
3ee6b26b
AD		 4825static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4826 struct drm_crtc_state *state)
e7b07cee
HW		 4827{
4828 struct amdgpu_device *adev = crtc->dev->dev_private;
4829 struct dc *dc = adev->dm.dc;
4830 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4831 int ret = -EINVAL;
4832
d6ef9b41
NK		 4833 /*
4834 * Update interrupt state for the CRTC. This needs to happen whenever
4835 * the CRTC has changed or whenever any of its planes have changed.
4836 * Atomic check satisfies both of these requirements since the CRTC
4837 * is added to the state by DRM during drm_atomic_helper_check_planes.
4838 */
4839 dm_update_crtc_interrupt_state(crtc, state);
4840
9b690ef3
BL		 4841 if (unlikely(!dm_crtc_state->stream &&
4842 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 4843 WARN_ON(1);
4844 return ret;
4845 }
4846
1f6010a9 4847 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 4848 if (!dm_crtc_state->stream)
4849 return 0;
4850
bc92c065
NK		 4851 /*
4852 * We want at least one hardware plane enabled to use
4853 * the stream with a cursor enabled.
4854 */
c14a005c 4855 if (state->enable && state->active &&
bc92c065 4856 does_crtc_have_active_cursor(state) &&
d6ef9b41 4857 dm_crtc_state->active_planes == 0)
c14a005c
NK		 4858 return -EINVAL;
4859
62c933f9 4860 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 4861 return 0;
4862
4863 return ret;
4864}
4865
3ee6b26b
AD		 4866static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4867 const struct drm_display_mode *mode,
4868 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 4869{
4870 return true;
4871}
4872
4873static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4874 .disable = dm_crtc_helper_disable,
4875 .atomic_check = dm_crtc_helper_atomic_check,
4876 .mode_fixup = dm_crtc_helper_mode_fixup
4877};
4878
4879static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4880{
4881
4882}
4883
3261e013
ML		 4884static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
4885{
4886 switch (display_color_depth) {
4887 case COLOR_DEPTH_666:
4888 return 6;
4889 case COLOR_DEPTH_888:
4890 return 8;
4891 case COLOR_DEPTH_101010:
4892 return 10;
4893 case COLOR_DEPTH_121212:
4894 return 12;
4895 case COLOR_DEPTH_141414:
4896 return 14;
4897 case COLOR_DEPTH_161616:
4898 return 16;
4899 default:
4900 break;
4901 }
4902 return 0;
4903}
4904
3ee6b26b
AD		 4905static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4906 struct drm_crtc_state *crtc_state,
4907 struct drm_connector_state *conn_state)
e7b07cee 4908{
3261e013
ML		 4909 struct drm_atomic_state *state = crtc_state->state;
4910 struct drm_connector *connector = conn_state->connector;
4911 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4912 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
4913 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
4914 struct drm_dp_mst_topology_mgr *mst_mgr;
4915 struct drm_dp_mst_port *mst_port;
4916 enum dc_color_depth color_depth;
4917 int clock, bpp = 0;
1bc22f20 4918 bool is_y420 = false;
3261e013
ML		 4919
4920 if (!aconnector->port || !aconnector->dc_sink)
4921 return 0;
4922
4923 mst_port = aconnector->port;
4924 mst_mgr = &aconnector->mst_port->mst_mgr;
4925
4926 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
4927 return 0;
4928
4929 if (!state->duplicated) {
1bc22f20
SW		 4930 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
4931 aconnector->force_yuv420_output;
4932 color_depth = convert_color_depth_from_display_info(connector, conn_state,
4933 is_y420);
3261e013
ML		 4934 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
4935 clock = adjusted_mode->clock;
dc48529f 4936 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
3261e013
ML		 4937 }
4938 dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
4939 mst_mgr,
4940 mst_port,
1c6c1cb5
ML		 4941 dm_new_connector_state->pbn,
4942 0);
3261e013
ML		 4943 if (dm_new_connector_state->vcpi_slots < 0) {
4944 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
4945 return dm_new_connector_state->vcpi_slots;
4946 }
e7b07cee
HW		 4947 return 0;
4948}
4949
4950const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4951 .disable = dm_encoder_helper_disable,
4952 .atomic_check = dm_encoder_helper_atomic_check
4953};
4954
4955static void dm_drm_plane_reset(struct drm_plane *plane)
4956{
4957 struct dm_plane_state *amdgpu_state = NULL;
4958
4959 if (plane->state)
4960 plane->funcs->atomic_destroy_state(plane, plane->state);
4961
4962 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 4963 WARN_ON(amdgpu_state == NULL);
1f6010a9 4964
7ddaef96
NK		 4965 if (amdgpu_state)
4966 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
e7b07cee
HW		 4967}
4968
4969static struct drm_plane_state *
4970dm_drm_plane_duplicate_state(struct drm_plane *plane)
4971{
4972 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4973
4974 old_dm_plane_state = to_dm_plane_state(plane->state);
4975 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4976 if (!dm_plane_state)
4977 return NULL;
4978
4979 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4980
3be5262e
HW		 4981 if (old_dm_plane_state->dc_state) {
4982 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4983 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 4984 }
4985
4986 return &dm_plane_state->base;
4987}
4988
4989void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 4990 struct drm_plane_state *state)
e7b07cee
HW		 4991{
4992 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4993
3be5262e
HW		 4994 if (dm_plane_state->dc_state)
4995 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 4996
0627bbd3 4997 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 4998}
4999
5000static const struct drm_plane_funcs dm_plane_funcs = {
5001 .update_plane = drm_atomic_helper_update_plane,
5002 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 5003 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 5004 .reset = dm_drm_plane_reset,
5005 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
5006 .atomic_destroy_state = dm_drm_plane_destroy_state,
5007};
5008
3ee6b26b
AD		 5009static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
5010 struct drm_plane_state *new_state)
e7b07cee
HW		 5011{
5012 struct amdgpu_framebuffer *afb;
5013 struct drm_gem_object *obj;
5d43be0c 5014 struct amdgpu_device *adev;
e7b07cee 5015 struct amdgpu_bo *rbo;
e7b07cee 5016 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
0f257b09
CZ		 5017 struct list_head list;
5018 struct ttm_validate_buffer tv;
5019 struct ww_acquire_ctx ticket;
e0634e8d 5020 uint64_t tiling_flags;
5d43be0c
CK		 5021 uint32_t domain;
5022 int r;
e7b07cee
HW		 5023
5024 dm_plane_state_old = to_dm_plane_state(plane->state);
5025 dm_plane_state_new = to_dm_plane_state(new_state);
5026
5027 if (!new_state->fb) {
f1ad2f5e 5028 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 5029 return 0;
5030 }
5031
5032 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 5033 obj = new_state->fb->obj[0];
e7b07cee 5034 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 5035 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
0f257b09
CZ		 5036 INIT_LIST_HEAD(&list);
5037
5038 tv.bo = &rbo->tbo;
5039 tv.num_shared = 1;
5040 list_add(&tv.head, &list);
5041
9165fb87 5042 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
0f257b09
CZ		 5043 if (r) {
5044 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
e7b07cee 5045 return r;
0f257b09 5046 }
e7b07cee 5047
5d43be0c 5048 if (plane->type != DRM_PLANE_TYPE_CURSOR)
f2bd8a0e 5049 domain = amdgpu_display_supported_domains(adev, rbo->flags);
5d43be0c
CK		 5050 else
5051 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 5052
7b7c6c81 5053 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 5054 if (unlikely(r != 0)) {
30b7c614
HW		 5055 if (r != -ERESTARTSYS)
5056 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
0f257b09 5057 ttm_eu_backoff_reservation(&ticket, &list);
e7b07cee
HW		 5058 return r;
5059 }
5060
bb812f1e
JZ		 5061 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
5062 if (unlikely(r != 0)) {
5063 amdgpu_bo_unpin(rbo);
0f257b09 5064 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 5065 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 5066 return r;
5067 }
7df7e505
NK		 5068
5069 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
5070
0f257b09 5071 ttm_eu_backoff_reservation(&ticket, &list);
bb812f1e 5072
7b7c6c81 5073 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 5074
5075 amdgpu_bo_ref(rbo);
5076
3be5262e
HW		 5077 if (dm_plane_state_new->dc_state &&
5078 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
5079 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 5080
320932bf 5081 fill_plane_buffer_attributes(
695af5f9
NK		 5082 adev, afb, plane_state->format, plane_state->rotation,
5083 tiling_flags, &plane_state->tiling_info,
320932bf 5084 &plane_state->plane_size, &plane_state->dcc,
695af5f9 5085 &plane_state->address);
e7b07cee
HW		 5086 }
5087
e7b07cee
HW		 5088 return 0;
5089}
5090
3ee6b26b
AD		 5091static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
5092 struct drm_plane_state *old_state)
e7b07cee
HW		 5093{
5094 struct amdgpu_bo *rbo;
e7b07cee
HW		 5095 int r;
5096
5097 if (!old_state->fb)
5098 return;
5099
e68d14dd 5100 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 5101 r = amdgpu_bo_reserve(rbo, false);
5102 if (unlikely(r)) {
5103 DRM_ERROR("failed to reserve rbo before unpin\n");
5104 return;
b830ebc9
HW		 5105 }
5106
5107 amdgpu_bo_unpin(rbo);
5108 amdgpu_bo_unreserve(rbo);
5109 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 5110}
5111
7578ecda
AD		 5112static int dm_plane_atomic_check(struct drm_plane *plane,
5113 struct drm_plane_state *state)
cbd19488
AG		 5114{
5115 struct amdgpu_device *adev = plane->dev->dev_private;
5116 struct dc *dc = adev->dm.dc;
78171832 5117 struct dm_plane_state *dm_plane_state;
695af5f9
NK		 5118 struct dc_scaling_info scaling_info;
5119 int ret;
78171832
NK		 5120
5121 dm_plane_state = to_dm_plane_state(state);
cbd19488 5122
3be5262e 5123 if (!dm_plane_state->dc_state)
9a3329b1 5124 return 0;
cbd19488 5125
695af5f9
NK		 5126 ret = fill_dc_scaling_info(state, &scaling_info);
5127 if (ret)
5128 return ret;
a05bcff1 5129
62c933f9 5130 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 5131 return 0;
5132
5133 return -EINVAL;
5134}
5135
674e78ac
NK		 5136static int dm_plane_atomic_async_check(struct drm_plane *plane,
5137 struct drm_plane_state *new_plane_state)
5138{
5139 /* Only support async updates on cursor planes. */
5140 if (plane->type != DRM_PLANE_TYPE_CURSOR)
5141 return -EINVAL;
5142
5143 return 0;
5144}
5145
5146static void dm_plane_atomic_async_update(struct drm_plane *plane,
5147 struct drm_plane_state *new_state)
5148{
5149 struct drm_plane_state *old_state =
5150 drm_atomic_get_old_plane_state(new_state->state, plane);
5151
332af874 5152 swap(plane->state->fb, new_state->fb);
674e78ac
NK		 5153
5154 plane->state->src_x = new_state->src_x;
5155 plane->state->src_y = new_state->src_y;
5156 plane->state->src_w = new_state->src_w;
5157 plane->state->src_h = new_state->src_h;
5158 plane->state->crtc_x = new_state->crtc_x;
5159 plane->state->crtc_y = new_state->crtc_y;
5160 plane->state->crtc_w = new_state->crtc_w;
5161 plane->state->crtc_h = new_state->crtc_h;
5162
5163 handle_cursor_update(plane, old_state);
5164}
5165
e7b07cee
HW		 5166static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
5167 .prepare_fb = dm_plane_helper_prepare_fb,
5168 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 5169 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 5170 .atomic_async_check = dm_plane_atomic_async_check,
5171 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 5172};
5173
5174/*
5175 * TODO: these are currently initialized to rgb formats only.
5176 * For future use cases we should either initialize them dynamically based on
5177 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 5178 * check will succeed, and let DC implement proper check
e7b07cee 5179 */
d90371b0 5180static const uint32_t rgb_formats[] = {
e7b07cee
HW		 5181 DRM_FORMAT_XRGB8888,
5182 DRM_FORMAT_ARGB8888,
5183 DRM_FORMAT_RGBA8888,
5184 DRM_FORMAT_XRGB2101010,
5185 DRM_FORMAT_XBGR2101010,
5186 DRM_FORMAT_ARGB2101010,
5187 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 5188 DRM_FORMAT_XBGR8888,
5189 DRM_FORMAT_ABGR8888,
46dd9ff7 5190 DRM_FORMAT_RGB565,
e7b07cee
HW		 5191};
5192
0d579c7e
NK		 5193static const uint32_t overlay_formats[] = {
5194 DRM_FORMAT_XRGB8888,
5195 DRM_FORMAT_ARGB8888,
5196 DRM_FORMAT_RGBA8888,
5197 DRM_FORMAT_XBGR8888,
5198 DRM_FORMAT_ABGR8888,
7267a1a9 5199 DRM_FORMAT_RGB565
e7b07cee
HW		 5200};
5201
5202static const u32 cursor_formats[] = {
5203 DRM_FORMAT_ARGB8888
5204};
5205
37c6a93b
NK		 5206static int get_plane_formats(const struct drm_plane *plane,
5207 const struct dc_plane_cap *plane_cap,
5208 uint32_t *formats, int max_formats)
e7b07cee 5209{
37c6a93b
NK		 5210 int i, num_formats = 0;
5211
5212 /*
5213 * TODO: Query support for each group of formats directly from
5214 * DC plane caps. This will require adding more formats to the
5215 * caps list.
5216 */
e7b07cee 5217
f180b4bc 5218 switch (plane->type) {
e7b07cee 5219 case DRM_PLANE_TYPE_PRIMARY:
37c6a93b
NK		 5220 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
5221 if (num_formats >= max_formats)
5222 break;
5223
5224 formats[num_formats++] = rgb_formats[i];
5225 }
5226
ea36ad34 5227 if (plane_cap && plane_cap->pixel_format_support.nv12)
37c6a93b 5228 formats[num_formats++] = DRM_FORMAT_NV12;
e7b07cee 5229 break;
37c6a93b 5230
e7b07cee 5231 case DRM_PLANE_TYPE_OVERLAY:
37c6a93b
NK		 5232 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
5233 if (num_formats >= max_formats)
5234 break;
5235
5236 formats[num_formats++] = overlay_formats[i];
5237 }
e7b07cee 5238 break;
37c6a93b 5239
e7b07cee 5240 case DRM_PLANE_TYPE_CURSOR:
37c6a93b
NK		 5241 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
5242 if (num_formats >= max_formats)
5243 break;
5244
5245 formats[num_formats++] = cursor_formats[i];
5246 }
e7b07cee
HW		 5247 break;
5248 }
5249
37c6a93b
NK		 5250 return num_formats;
5251}
5252
5253static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
5254 struct drm_plane *plane,
5255 unsigned long possible_crtcs,
5256 const struct dc_plane_cap *plane_cap)
5257{
5258 uint32_t formats[32];
5259 int num_formats;
5260 int res = -EPERM;
5261
5262 num_formats = get_plane_formats(plane, plane_cap, formats,
5263 ARRAY_SIZE(formats));
5264
5265 res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
5266 &dm_plane_funcs, formats, num_formats,
5267 NULL, plane->type, NULL);
5268 if (res)
5269 return res;
5270
cc1fec57
NK		 5271 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
5272 plane_cap && plane_cap->per_pixel_alpha) {
d74004b6
NK		 5273 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
5274 BIT(DRM_MODE_BLEND_PREMULTI);
5275
5276 drm_plane_create_alpha_property(plane);
5277 drm_plane_create_blend_mode_property(plane, blend_caps);
5278 }
5279
fc8e5230 5280 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
ea36ad34 5281 plane_cap && plane_cap->pixel_format_support.nv12) {
fc8e5230
NK		 5282 /* This only affects YUV formats. */
5283 drm_plane_create_color_properties(
5284 plane,
5285 BIT(DRM_COLOR_YCBCR_BT601) |
5286 BIT(DRM_COLOR_YCBCR_BT709),
5287 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
5288 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
5289 DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
5290 }
5291
f180b4bc 5292 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 5293
96719c54 5294 /* Create (reset) the plane state */
f180b4bc
HW		 5295 if (plane->funcs->reset)
5296 plane->funcs->reset(plane);
96719c54 5297
37c6a93b 5298 return 0;
e7b07cee
HW		 5299}
5300
7578ecda
AD		 5301static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
5302 struct drm_plane *plane,
5303 uint32_t crtc_index)
e7b07cee
HW		 5304{
5305 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 5306 struct drm_plane *cursor_plane;
e7b07cee
HW		 5307
5308 int res = -ENOMEM;
5309
5310 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
5311 if (!cursor_plane)
5312 goto fail;
5313
f180b4bc 5314 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
cc1fec57 5315 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
e7b07cee
HW		 5316
5317 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
5318 if (!acrtc)
5319 goto fail;
5320
5321 res = drm_crtc_init_with_planes(
5322 dm->ddev,
5323 &acrtc->base,
5324 plane,
f180b4bc 5325 cursor_plane,
e7b07cee
HW		 5326 &amdgpu_dm_crtc_funcs, NULL);
5327
5328 if (res)
5329 goto fail;
5330
5331 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
5332
96719c54
HW		 5333 /* Create (reset) the plane state */
5334 if (acrtc->base.funcs->reset)
5335 acrtc->base.funcs->reset(&acrtc->base);
5336
e7b07cee
HW		 5337 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
5338 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
5339
5340 acrtc->crtc_id = crtc_index;
5341 acrtc->base.enabled = false;
c37e2d29 5342 acrtc->otg_inst = -1;
e7b07cee
HW		 5343
5344 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 5345 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
5346 true, MAX_COLOR_LUT_ENTRIES);
086247a4 5347 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 5348
5349 return 0;
5350
5351fail:
b830ebc9
HW		 5352 kfree(acrtc);
5353 kfree(cursor_plane);
e7b07cee
HW		 5354 return res;
5355}
5356
5357
5358static int to_drm_connector_type(enum signal_type st)
5359{
5360 switch (st) {
5361 case SIGNAL_TYPE_HDMI_TYPE_A:
5362 return DRM_MODE_CONNECTOR_HDMIA;
5363 case SIGNAL_TYPE_EDP:
5364 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 5365 case SIGNAL_TYPE_LVDS:
5366 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 5367 case SIGNAL_TYPE_RGB:
5368 return DRM_MODE_CONNECTOR_VGA;
5369 case SIGNAL_TYPE_DISPLAY_PORT:
5370 case SIGNAL_TYPE_DISPLAY_PORT_MST:
5371 return DRM_MODE_CONNECTOR_DisplayPort;
5372 case SIGNAL_TYPE_DVI_DUAL_LINK:
5373 case SIGNAL_TYPE_DVI_SINGLE_LINK:
5374 return DRM_MODE_CONNECTOR_DVID;
5375 case SIGNAL_TYPE_VIRTUAL:
5376 return DRM_MODE_CONNECTOR_VIRTUAL;
5377
5378 default:
5379 return DRM_MODE_CONNECTOR_Unknown;
5380 }
5381}
5382
2b4c1c05
DV		 5383static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
5384{
62afb4ad
JRS		 5385 struct drm_encoder *encoder;
5386
5387 /* There is only one encoder per connector */
5388 drm_connector_for_each_possible_encoder(connector, encoder)
5389 return encoder;
5390
5391 return NULL;
2b4c1c05
DV		 5392}
5393
e7b07cee
HW		 5394static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
5395{
e7b07cee
HW		 5396 struct drm_encoder *encoder;
5397 struct amdgpu_encoder *amdgpu_encoder;
5398
2b4c1c05 5399 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 5400
5401 if (encoder == NULL)
5402 return;
5403
5404 amdgpu_encoder = to_amdgpu_encoder(encoder);
5405
5406 amdgpu_encoder->native_mode.clock = 0;
5407
5408 if (!list_empty(&connector->probed_modes)) {
5409 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 5410
e7b07cee 5411 list_for_each_entry(preferred_mode,
b830ebc9
HW		 5412 &connector->probed_modes,
5413 head) {
5414 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
5415 amdgpu_encoder->native_mode = *preferred_mode;
5416
e7b07cee
HW		 5417 break;
5418 }
5419
5420 }
5421}
5422
3ee6b26b
AD		 5423static struct drm_display_mode *
5424amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
5425 char *name,
5426 int hdisplay, int vdisplay)
e7b07cee
HW		 5427{
5428 struct drm_device *dev = encoder->dev;
5429 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5430 struct drm_display_mode *mode = NULL;
5431 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
5432
5433 mode = drm_mode_duplicate(dev, native_mode);
5434
b830ebc9 5435 if (mode == NULL)
e7b07cee
HW		 5436 return NULL;
5437
5438 mode->hdisplay = hdisplay;
5439 mode->vdisplay = vdisplay;
5440 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 5441 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 5442
5443 return mode;
5444
5445}
5446
5447static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 5448 struct drm_connector *connector)
e7b07cee
HW		 5449{
5450 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
5451 struct drm_display_mode *mode = NULL;
5452 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 5453 struct amdgpu_dm_connector *amdgpu_dm_connector =
5454 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5455 int i;
5456 int n;
5457 struct mode_size {
5458 char name[DRM_DISPLAY_MODE_LEN];
5459 int w;
5460 int h;
b830ebc9 5461 } common_modes[] = {
e7b07cee
HW		 5462 { "640x480", 640, 480},
5463 { "800x600", 800, 600},
5464 { "1024x768", 1024, 768},
5465 { "1280x720", 1280, 720},
5466 { "1280x800", 1280, 800},
5467 {"1280x1024", 1280, 1024},
5468 { "1440x900", 1440, 900},
5469 {"1680x1050", 1680, 1050},
5470 {"1600x1200", 1600, 1200},
5471 {"1920x1080", 1920, 1080},
5472 {"1920x1200", 1920, 1200}
5473 };
5474
b830ebc9 5475 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 5476
5477 for (i = 0; i < n; i++) {
5478 struct drm_display_mode *curmode = NULL;
5479 bool mode_existed = false;
5480
5481 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 5482 common_modes[i].h > native_mode->vdisplay ||
5483 (common_modes[i].w == native_mode->hdisplay &&
5484 common_modes[i].h == native_mode->vdisplay))
5485 continue;
e7b07cee
HW		 5486
5487 list_for_each_entry(curmode, &connector->probed_modes, head) {
5488 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 5489 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 5490 mode_existed = true;
5491 break;
5492 }
5493 }
5494
5495 if (mode_existed)
5496 continue;
5497
5498 mode = amdgpu_dm_create_common_mode(encoder,
5499 common_modes[i].name, common_modes[i].w,
5500 common_modes[i].h);
5501 drm_mode_probed_add(connector, mode);
c84dec2f 5502 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 5503 }
5504}
5505
3ee6b26b
AD		 5506static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
5507 struct edid *edid)
e7b07cee 5508{
c84dec2f
HW		 5509 struct amdgpu_dm_connector *amdgpu_dm_connector =
5510 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5511
5512 if (edid) {
5513 /* empty probed_modes */
5514 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 5515 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 5516 drm_add_edid_modes(connector, edid);
5517
f1e5e913
YMM		 5518 /* sorting the probed modes before calling function
5519 * amdgpu_dm_get_native_mode() since EDID can have
5520 * more than one preferred mode. The modes that are
5521 * later in the probed mode list could be of higher
5522 * and preferred resolution. For example, 3840x2160
5523 * resolution in base EDID preferred timing and 4096x2160
5524 * preferred resolution in DID extension block later.
5525 */
5526 drm_mode_sort(&connector->probed_modes);
e7b07cee 5527 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 5528 } else {
c84dec2f 5529 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 5530 }
e7b07cee
HW		 5531}
5532
7578ecda 5533static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 5534{
c84dec2f
HW		 5535 struct amdgpu_dm_connector *amdgpu_dm_connector =
5536 to_amdgpu_dm_connector(connector);
e7b07cee 5537 struct drm_encoder *encoder;
c84dec2f 5538 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 5539
2b4c1c05 5540 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 5541
85ee15d6 5542 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 5543 amdgpu_dm_connector->num_modes =
5544 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 5545 } else {
5546 amdgpu_dm_connector_ddc_get_modes(connector, edid);
5547 amdgpu_dm_connector_add_common_modes(encoder, connector);
5548 }
3e332d3a 5549 amdgpu_dm_fbc_init(connector);
5099114b 5550
c84dec2f 5551 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 5552}
5553
3ee6b26b
AD		 5554void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
5555 struct amdgpu_dm_connector *aconnector,
5556 int connector_type,
5557 struct dc_link *link,
5558 int link_index)
e7b07cee
HW		 5559{
5560 struct amdgpu_device *adev = dm->ddev->dev_private;
5561
f04bee34
NK		 5562 /*
5563 * Some of the properties below require access to state, like bpc.
5564 * Allocate some default initial connector state with our reset helper.
5565 */
5566 if (aconnector->base.funcs->reset)
5567 aconnector->base.funcs->reset(&aconnector->base);
5568
e7b07cee
HW		 5569 aconnector->connector_id = link_index;
5570 aconnector->dc_link = link;
5571 aconnector->base.interlace_allowed = false;
5572 aconnector->base.doublescan_allowed = false;
5573 aconnector->base.stereo_allowed = false;
5574 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
5575 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6ce8f316 5576 aconnector->audio_inst = -1;
e7b07cee
HW		 5577 mutex_init(&aconnector->hpd_lock);
5578
1f6010a9
DF		 5579 /*
5580 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 5581 * which means HPD hot plug not supported
5582 */
e7b07cee
HW		 5583 switch (connector_type) {
5584 case DRM_MODE_CONNECTOR_HDMIA:
5585 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 5586 aconnector->base.ycbcr_420_allowed =
9ea59d5a 5587 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 5588 break;
5589 case DRM_MODE_CONNECTOR_DisplayPort:
5590 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 5591 aconnector->base.ycbcr_420_allowed =
9ea59d5a 5592 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 5593 break;
5594 case DRM_MODE_CONNECTOR_DVID:
5595 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
5596 break;
5597 default:
5598 break;
5599 }
5600
5601 drm_object_attach_property(&aconnector->base.base,
5602 dm->ddev->mode_config.scaling_mode_property,
5603 DRM_MODE_SCALE_NONE);
5604
5605 drm_object_attach_property(&aconnector->base.base,
5606 adev->mode_info.underscan_property,
5607 UNDERSCAN_OFF);
5608 drm_object_attach_property(&aconnector->base.base,
5609 adev->mode_info.underscan_hborder_property,
5610 0);
5611 drm_object_attach_property(&aconnector->base.base,
5612 adev->mode_info.underscan_vborder_property,
5613 0);
1825fd34
NK		 5614
5615 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
5616
4a8ca46b
RL		 5617 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
5618 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
5619 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
e7b07cee 5620
c1ee92f9
DF		 5621 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
5622 dc_is_dmcu_initialized(adev->dm.dc)) {
5623 drm_object_attach_property(&aconnector->base.base,
5624 adev->mode_info.abm_level_property, 0);
5625 }
bb47de73
NK		 5626
5627 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 5628 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5629 connector_type == DRM_MODE_CONNECTOR_eDP) {
88694af9
NK		 5630 drm_object_attach_property(
5631 &aconnector->base.base,
5632 dm->ddev->mode_config.hdr_output_metadata_property, 0);
5633
bb47de73
NK		 5634 drm_connector_attach_vrr_capable_property(
5635 &aconnector->base);
0c8620d6 5636#ifdef CONFIG_DRM_AMD_DC_HDCP
96a3b32e 5637 if (adev->asic_type >= CHIP_RAVEN)
53e108aa 5638 drm_connector_attach_content_protection_property(&aconnector->base, true);
0c8620d6 5639#endif
bb47de73 5640 }
e7b07cee
HW		 5641}
5642
7578ecda
AD		 5643static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
5644 struct i2c_msg *msgs, int num)
e7b07cee
HW		 5645{
5646 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
5647 struct ddc_service *ddc_service = i2c->ddc_service;
5648 struct i2c_command cmd;
5649 int i;
5650 int result = -EIO;
5651
b830ebc9 5652 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 5653
5654 if (!cmd.payloads)
5655 return result;
5656
5657 cmd.number_of_payloads = num;
5658 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
5659 cmd.speed = 100;
5660
5661 for (i = 0; i < num; i++) {
5662 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
5663 cmd.payloads[i].address = msgs[i].addr;
5664 cmd.payloads[i].length = msgs[i].len;
5665 cmd.payloads[i].data = msgs[i].buf;
5666 }
5667
c85e6e54
DF		 5668 if (dc_submit_i2c(
5669 ddc_service->ctx->dc,
5670 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 5671 &cmd))
5672 result = num;
5673
5674 kfree(cmd.payloads);
5675 return result;
5676}
5677
7578ecda 5678static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 5679{
5680 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
5681}
5682
5683static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
5684 .master_xfer = amdgpu_dm_i2c_xfer,
5685 .functionality = amdgpu_dm_i2c_func,
5686};
5687
3ee6b26b
AD		 5688static struct amdgpu_i2c_adapter *
5689create_i2c(struct ddc_service *ddc_service,
5690 int link_index,
5691 int *res)
e7b07cee
HW		 5692{
5693 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
5694 struct amdgpu_i2c_adapter *i2c;
5695
b830ebc9 5696 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 5697 if (!i2c)
5698 return NULL;
e7b07cee
HW		 5699 i2c->base.owner = THIS_MODULE;
5700 i2c->base.class = I2C_CLASS_DDC;
5701 i2c->base.dev.parent = &adev->pdev->dev;
5702 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 5703 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 5704 i2c_set_adapdata(&i2c->base, i2c);
5705 i2c->ddc_service = ddc_service;
c85e6e54 5706 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 5707
5708 return i2c;
5709}
5710
89fc8d4e 5711
1f6010a9
DF		 5712/*
5713 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 5714 * dc_link which will be represented by this aconnector.
5715 */
7578ecda
AD		 5716static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
5717 struct amdgpu_dm_connector *aconnector,
5718 uint32_t link_index,
5719 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 5720{
5721 int res = 0;
5722 int connector_type;
5723 struct dc *dc = dm->dc;
5724 struct dc_link *link = dc_get_link_at_index(dc, link_index);
5725 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 5726
5727 link->priv = aconnector;
e7b07cee 5728
f1ad2f5e 5729 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 5730
5731 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 5732 if (!i2c) {
5733 DRM_ERROR("Failed to create i2c adapter data\n");
5734 return -ENOMEM;
5735 }
5736
e7b07cee
HW		 5737 aconnector->i2c = i2c;
5738 res = i2c_add_adapter(&i2c->base);
5739
5740 if (res) {
5741 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
5742 goto out_free;
5743 }
5744
5745 connector_type = to_drm_connector_type(link->connector_signal);
5746
17165de2 5747 res = drm_connector_init_with_ddc(
e7b07cee
HW		 5748 dm->ddev,
5749 &aconnector->base,
5750 &amdgpu_dm_connector_funcs,
17165de2
AP		 5751 connector_type,
5752 &i2c->base);
e7b07cee
HW		 5753
5754 if (res) {
5755 DRM_ERROR("connector_init failed\n");
5756 aconnector->connector_id = -1;
5757 goto out_free;
5758 }
5759
5760 drm_connector_helper_add(
5761 &aconnector->base,
5762 &amdgpu_dm_connector_helper_funcs);
5763
5764 amdgpu_dm_connector_init_helper(
5765 dm,
5766 aconnector,
5767 connector_type,
5768 link,
5769 link_index);
5770
cde4c44d 5771 drm_connector_attach_encoder(
e7b07cee
HW		 5772 &aconnector->base, &aencoder->base);
5773
5774 drm_connector_register(&aconnector->base);
dc38fd9d 5775#if defined(CONFIG_DEBUG_FS)
4be8be78 5776 connector_debugfs_init(aconnector);
f258fee6
DF		 5777 aconnector->debugfs_dpcd_address = 0;
5778 aconnector->debugfs_dpcd_size = 0;
dc38fd9d 5779#endif
e7b07cee
HW		 5780
5781 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
5782 || connector_type == DRM_MODE_CONNECTOR_eDP)
5783 amdgpu_dm_initialize_dp_connector(dm, aconnector);
5784
e7b07cee
HW		 5785out_free:
5786 if (res) {
5787 kfree(i2c);
5788 aconnector->i2c = NULL;
5789 }
5790 return res;
5791}
5792
5793int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
5794{
5795 switch (adev->mode_info.num_crtc) {
5796 case 1:
5797 return 0x1;
5798 case 2:
5799 return 0x3;
5800 case 3:
5801 return 0x7;
5802 case 4:
5803 return 0xf;
5804 case 5:
5805 return 0x1f;
5806 case 6:
5807 default:
5808 return 0x3f;
5809 }
5810}
5811
7578ecda
AD		 5812static int amdgpu_dm_encoder_init(struct drm_device *dev,
5813 struct amdgpu_encoder *aencoder,
5814 uint32_t link_index)
e7b07cee
HW		 5815{
5816 struct amdgpu_device *adev = dev->dev_private;
5817
5818 int res = drm_encoder_init(dev,
5819 &aencoder->base,
5820 &amdgpu_dm_encoder_funcs,
5821 DRM_MODE_ENCODER_TMDS,
5822 NULL);
5823
5824 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
5825
5826 if (!res)
5827 aencoder->encoder_id = link_index;
5828 else
5829 aencoder->encoder_id = -1;
5830
5831 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
5832
5833 return res;
5834}
5835
3ee6b26b
AD		 5836static void manage_dm_interrupts(struct amdgpu_device *adev,
5837 struct amdgpu_crtc *acrtc,
5838 bool enable)
e7b07cee
HW		 5839{
5840 /*
5841 * this is not correct translation but will work as soon as VBLANK
5842 * constant is the same as PFLIP
5843 */
5844 int irq_type =
734dd01d 5845 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 5846 adev,
5847 acrtc->crtc_id);
5848
5849 if (enable) {
5850 drm_crtc_vblank_on(&acrtc->base);
5851 amdgpu_irq_get(
5852 adev,
5853 &adev->pageflip_irq,
5854 irq_type);
5855 } else {
5856
5857 amdgpu_irq_put(
5858 adev,
5859 &adev->pageflip_irq,
5860 irq_type);
5861 drm_crtc_vblank_off(&acrtc->base);
5862 }
5863}
5864
3ee6b26b
AD		 5865static bool
5866is_scaling_state_different(const struct dm_connector_state *dm_state,
5867 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 5868{
5869 if (dm_state->scaling != old_dm_state->scaling)
5870 return true;
5871 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
5872 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
5873 return true;
5874 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
5875 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
5876 return true;
b830ebc9
HW		 5877 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
5878 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
5879 return true;
e7b07cee
HW		 5880 return false;
5881}
5882
0c8620d6
BL		 5883#ifdef CONFIG_DRM_AMD_DC_HDCP
5884static bool is_content_protection_different(struct drm_connector_state *state,
5885 const struct drm_connector_state *old_state,
5886 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
5887{
5888 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5889
53e108aa
BL		 5890 if (old_state->hdcp_content_type != state->hdcp_content_type &&
5891 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
5892 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5893 return true;
5894 }
5895
0c8620d6
BL		 5896 /* CP is being re enabled, ignore this */
5897 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
5898 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
5899 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
5900 return false;
5901 }
5902
5903 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
5904 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
5905 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
5906 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
5907
5908 /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
5909 * hot-plug, headless s3, dpms
5910 */
5911 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON &&
5912 aconnector->dc_sink != NULL)
5913 return true;
5914
5915 if (old_state->content_protection == state->content_protection)
5916 return false;
5917
5918 if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
5919 return true;
5920
5921 return false;
5922}
5923
0c8620d6 5924#endif
3ee6b26b
AD		 5925static void remove_stream(struct amdgpu_device *adev,
5926 struct amdgpu_crtc *acrtc,
5927 struct dc_stream_state *stream)
e7b07cee
HW		 5928{
5929 /* this is the update mode case */
e7b07cee
HW		 5930
5931 acrtc->otg_inst = -1;
5932 acrtc->enabled = false;
5933}
5934
7578ecda
AD		 5935static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
5936 struct dc_cursor_position *position)
2a8f6ccb 5937{
f4c2cc43 5938 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 5939 int x, y;
5940 int xorigin = 0, yorigin = 0;
5941
e371e19c
NK		 5942 position->enable = false;
5943 position->x = 0;
5944 position->y = 0;
5945
5946 if (!crtc || !plane->state->fb)
2a8f6ccb 5947 return 0;
2a8f6ccb
HW		 5948
5949 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
5950 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
5951 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
5952 __func__,
5953 plane->state->crtc_w,
5954 plane->state->crtc_h);
5955 return -EINVAL;
5956 }
5957
5958 x = plane->state->crtc_x;
5959 y = plane->state->crtc_y;
c14a005c 5960
e371e19c
NK		 5961 if (x <= -amdgpu_crtc->max_cursor_width ||
5962 y <= -amdgpu_crtc->max_cursor_height)
5963 return 0;
5964
c14a005c
NK		 5965 if (crtc->primary->state) {
5966 /* avivo cursor are offset into the total surface */
5967 x += crtc->primary->state->src_x >> 16;
5968 y += crtc->primary->state->src_y >> 16;
5969 }
5970
2a8f6ccb
HW		 5971 if (x < 0) {
5972 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
5973 x = 0;
5974 }
5975 if (y < 0) {
5976 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
5977 y = 0;
5978 }
5979 position->enable = true;
5980 position->x = x;
5981 position->y = y;
5982 position->x_hotspot = xorigin;
5983 position->y_hotspot = yorigin;
5984
5985 return 0;
5986}
5987
3ee6b26b
AD		 5988static void handle_cursor_update(struct drm_plane *plane,
5989 struct drm_plane_state *old_plane_state)
e7b07cee 5990{
674e78ac 5991 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 5992 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
5993 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
5994 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
5995 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5996 uint64_t address = afb ? afb->address : 0;
5997 struct dc_cursor_position position;
5998 struct dc_cursor_attributes attributes;
5999 int ret;
6000
e7b07cee
HW		 6001 if (!plane->state->fb && !old_plane_state->fb)
6002 return;
6003
f1ad2f5e 6004 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 6005 __func__,
6006 amdgpu_crtc->crtc_id,
6007 plane->state->crtc_w,
6008 plane->state->crtc_h);
2a8f6ccb
HW		 6009
6010 ret = get_cursor_position(plane, crtc, &position);
6011 if (ret)
6012 return;
6013
6014 if (!position.enable) {
6015 /* turn off cursor */
674e78ac
NK		 6016 if (crtc_state && crtc_state->stream) {
6017 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 6018 dc_stream_set_cursor_position(crtc_state->stream,
6019 &position);
674e78ac
NK		 6020 mutex_unlock(&adev->dm.dc_lock);
6021 }
2a8f6ccb 6022 return;
e7b07cee 6023 }
e7b07cee 6024
2a8f6ccb
HW		 6025 amdgpu_crtc->cursor_width = plane->state->crtc_w;
6026 amdgpu_crtc->cursor_height = plane->state->crtc_h;
6027
c1cefe11 6028 memset(&attributes, 0, sizeof(attributes));
2a8f6ccb
HW		 6029 attributes.address.high_part = upper_32_bits(address);
6030 attributes.address.low_part = lower_32_bits(address);
6031 attributes.width = plane->state->crtc_w;
6032 attributes.height = plane->state->crtc_h;
6033 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
6034 attributes.rotation_angle = 0;
6035 attributes.attribute_flags.value = 0;
6036
6037 attributes.pitch = attributes.width;
6038
886daac9 6039 if (crtc_state->stream) {
674e78ac 6040 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 6041 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
6042 &attributes))
6043 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 6044
2a8f6ccb
HW		 6045 if (!dc_stream_set_cursor_position(crtc_state->stream,
6046 &position))
6047 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 6048 mutex_unlock(&adev->dm.dc_lock);
886daac9 6049 }
2a8f6ccb 6050}
e7b07cee
HW		 6051
6052static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
6053{
6054
6055 assert_spin_locked(&acrtc->base.dev->event_lock);
6056 WARN_ON(acrtc->event);
6057
6058 acrtc->event = acrtc->base.state->event;
6059
6060 /* Set the flip status */
6061 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
6062
6063 /* Mark this event as consumed */
6064 acrtc->base.state->event = NULL;
6065
6066 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
6067 acrtc->crtc_id);
6068}
6069
bb47de73
NK		 6070static void update_freesync_state_on_stream(
6071 struct amdgpu_display_manager *dm,
6072 struct dm_crtc_state *new_crtc_state,
180db303
NK		 6073 struct dc_stream_state *new_stream,
6074 struct dc_plane_state *surface,
6075 u32 flip_timestamp_in_us)
bb47de73 6076{
09aef2c4 6077 struct mod_vrr_params vrr_params;
bb47de73 6078 struct dc_info_packet vrr_infopacket = {0};
09aef2c4
MK		 6079 struct amdgpu_device *adev = dm->adev;
6080 unsigned long flags;
bb47de73
NK		 6081
6082 if (!new_stream)
6083 return;
6084
6085 /*
6086 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6087 * For now it's sufficient to just guard against these conditions.
6088 */
6089
6090 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
6091 return;
6092
09aef2c4
MK		 6093 spin_lock_irqsave(&adev->ddev->event_lock, flags);
6094 vrr_params = new_crtc_state->vrr_params;
6095
180db303
NK		 6096 if (surface) {
6097 mod_freesync_handle_preflip(
6098 dm->freesync_module,
6099 surface,
6100 new_stream,
6101 flip_timestamp_in_us,
6102 &vrr_params);
09aef2c4
MK		 6103
6104 if (adev->family < AMDGPU_FAMILY_AI &&
6105 amdgpu_dm_vrr_active(new_crtc_state)) {
6106 mod_freesync_handle_v_update(dm->freesync_module,
6107 new_stream, &vrr_params);
e63e2491
EB		 6108
6109 /* Need to call this before the frame ends. */
6110 dc_stream_adjust_vmin_vmax(dm->dc,
6111 new_crtc_state->stream,
6112 &vrr_params.adjust);
09aef2c4 6113 }
180db303 6114 }
bb47de73
NK		 6115
6116 mod_freesync_build_vrr_infopacket(
6117 dm->freesync_module,
6118 new_stream,
180db303 6119 &vrr_params,
ecd0136b
HT		 6120 PACKET_TYPE_VRR,
6121 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 6122 &vrr_infopacket);
6123
8a48b44c 6124 new_crtc_state->freesync_timing_changed |=
180db303
NK		 6125 (memcmp(&new_crtc_state->vrr_params.adjust,
6126 &vrr_params.adjust,
6127 sizeof(vrr_params.adjust)) != 0);
bb47de73 6128
8a48b44c 6129 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 6130 (memcmp(&new_crtc_state->vrr_infopacket,
6131 &vrr_infopacket,
6132 sizeof(vrr_infopacket)) != 0);
6133
180db303 6134 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 6135 new_crtc_state->vrr_infopacket = vrr_infopacket;
6136
180db303 6137 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 6138 new_stream->vrr_infopacket = vrr_infopacket;
6139
6140 if (new_crtc_state->freesync_vrr_info_changed)
6141 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
6142 new_crtc_state->base.crtc->base.id,
6143 (int)new_crtc_state->base.vrr_enabled,
180db303 6144 (int)vrr_params.state);
09aef2c4
MK		 6145
6146 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
bb47de73
NK		 6147}
6148
e854194c
MK		 6149static void pre_update_freesync_state_on_stream(
6150 struct amdgpu_display_manager *dm,
6151 struct dm_crtc_state *new_crtc_state)
6152{
6153 struct dc_stream_state *new_stream = new_crtc_state->stream;
09aef2c4 6154 struct mod_vrr_params vrr_params;
e854194c 6155 struct mod_freesync_config config = new_crtc_state->freesync_config;
09aef2c4
MK		 6156 struct amdgpu_device *adev = dm->adev;
6157 unsigned long flags;
e854194c
MK		 6158
6159 if (!new_stream)
6160 return;
6161
6162 /*
6163 * TODO: Determine why min/max totals and vrefresh can be 0 here.
6164 * For now it's sufficient to just guard against these conditions.
6165 */
6166 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
6167 return;
6168
09aef2c4
MK		 6169 spin_lock_irqsave(&adev->ddev->event_lock, flags);
6170 vrr_params = new_crtc_state->vrr_params;
6171
e854194c
MK		 6172 if (new_crtc_state->vrr_supported &&
6173 config.min_refresh_in_uhz &&
6174 config.max_refresh_in_uhz) {
6175 config.state = new_crtc_state->base.vrr_enabled ?
6176 VRR_STATE_ACTIVE_VARIABLE :
6177 VRR_STATE_INACTIVE;
6178 } else {
6179 config.state = VRR_STATE_UNSUPPORTED;
6180 }
6181
6182 mod_freesync_build_vrr_params(dm->freesync_module,
6183 new_stream,
6184 &config, &vrr_params);
6185
6186 new_crtc_state->freesync_timing_changed |=
6187 (memcmp(&new_crtc_state->vrr_params.adjust,
6188 &vrr_params.adjust,
6189 sizeof(vrr_params.adjust)) != 0);
6190
6191 new_crtc_state->vrr_params = vrr_params;
09aef2c4 6192 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
e854194c
MK		 6193}
6194
66b0c973
MK		 6195static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
6196 struct dm_crtc_state *new_state)
6197{
6198 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
6199 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
6200
6201 if (!old_vrr_active && new_vrr_active) {
6202 /* Transition VRR inactive -> active:
6203 * While VRR is active, we must not disable vblank irq, as a
6204 * reenable after disable would compute bogus vblank/pflip
6205 * timestamps if it likely happened inside display front-porch.
d2574c33
MK		 6206 *
6207 * We also need vupdate irq for the actual core vblank handling
6208 * at end of vblank.
66b0c973 6209 */
d2574c33 6210 dm_set_vupdate_irq(new_state->base.crtc, true);
66b0c973
MK		 6211 drm_crtc_vblank_get(new_state->base.crtc);
6212 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
6213 __func__, new_state->base.crtc->base.id);
6214 } else if (old_vrr_active && !new_vrr_active) {
6215 /* Transition VRR active -> inactive:
6216 * Allow vblank irq disable again for fixed refresh rate.
6217 */
d2574c33 6218 dm_set_vupdate_irq(new_state->base.crtc, false);
66b0c973
MK		 6219 drm_crtc_vblank_put(new_state->base.crtc);
6220 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
6221 __func__, new_state->base.crtc->base.id);
6222 }
6223}
6224
8ad27806
NK		 6225static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
6226{
6227 struct drm_plane *plane;
6228 struct drm_plane_state *old_plane_state, *new_plane_state;
6229 int i;
6230
6231 /*
6232 * TODO: Make this per-stream so we don't issue redundant updates for
6233 * commits with multiple streams.
6234 */
6235 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
6236 new_plane_state, i)
6237 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6238 handle_cursor_update(plane, old_plane_state);
6239}
6240
3be5262e 6241static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 6242 struct dc_state *dc_state,
3ee6b26b
AD		 6243 struct drm_device *dev,
6244 struct amdgpu_display_manager *dm,
6245 struct drm_crtc *pcrtc,
420cd472 6246 bool wait_for_vblank)
e7b07cee 6247{
570c91d5 6248 uint32_t i;
8a48b44c 6249 uint64_t timestamp_ns;
e7b07cee 6250 struct drm_plane *plane;
0bc9706d 6251 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 6252 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 6253 struct drm_crtc_state *new_pcrtc_state =
6254 drm_atomic_get_new_crtc_state(state, pcrtc);
6255 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 6256 struct dm_crtc_state *dm_old_crtc_state =
6257 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 6258 int planes_count = 0, vpos, hpos;
570c91d5 6259 long r;
e7b07cee 6260 unsigned long flags;
8a48b44c 6261 struct amdgpu_bo *abo;
09e5665a 6262 uint64_t tiling_flags;
fdd1fe57
MK		 6263 uint32_t target_vblank, last_flip_vblank;
6264 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
74aa7bd4 6265 bool pflip_present = false;
8c322309 6266 bool swizzle = true;
bc7f670e
DF		 6267 struct {
6268 struct dc_surface_update surface_updates[MAX_SURFACES];
6269 struct dc_plane_info plane_infos[MAX_SURFACES];
6270 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 6271 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 6272 struct dc_stream_update stream_update;
74aa7bd4 6273 } *bundle;
bc7f670e 6274
74aa7bd4 6275 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 6276
74aa7bd4
DF		 6277 if (!bundle) {
6278 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 6279 goto cleanup;
6280 }
e7b07cee 6281
8ad27806
NK		 6282 /*
6283 * Disable the cursor first if we're disabling all the planes.
6284 * It'll remain on the screen after the planes are re-enabled
6285 * if we don't.
6286 */
6287 if (acrtc_state->active_planes == 0)
6288 amdgpu_dm_commit_cursors(state);
6289
e7b07cee 6290 /* update planes when needed */
0bc9706d
LSL		 6291 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6292 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 6293 struct drm_crtc_state *new_crtc_state;
0bc9706d 6294 struct drm_framebuffer *fb = new_plane_state->fb;
34bafd27 6295 bool plane_needs_flip;
c7af5f77 6296 struct dc_plane_state *dc_plane;
54d76575 6297 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 6298
80c218d5
NK		 6299 /* Cursor plane is handled after stream updates */
6300 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 6301 continue;
e7b07cee 6302
f5ba60fe
DD		 6303 if (!fb || !crtc || pcrtc != crtc)
6304 continue;
6305
6306 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
6307 if (!new_crtc_state->active)
e7b07cee
HW		 6308 continue;
6309
bc7f670e 6310 dc_plane = dm_new_plane_state->dc_state;
e7b07cee 6311
8c322309
RL		 6312 if (dc_plane && !dc_plane->tiling_info.gfx9.swizzle)
6313 swizzle = false;
6314
74aa7bd4 6315 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 6316 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 6317 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
6318 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
bc7f670e 6319 }
8a48b44c 6320
695af5f9
NK		 6321 fill_dc_scaling_info(new_plane_state,
6322 &bundle->scaling_infos[planes_count]);
8a48b44c 6323
695af5f9
NK		 6324 bundle->surface_updates[planes_count].scaling_info =
6325 &bundle->scaling_infos[planes_count];
8a48b44c 6326
f5031000 6327 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8a48b44c 6328
f5031000 6329 pflip_present = pflip_present || plane_needs_flip;
8a48b44c 6330
f5031000
DF		 6331 if (!plane_needs_flip) {
6332 planes_count += 1;
6333 continue;
6334 }
8a48b44c 6335
2fac0f53
CK		 6336 abo = gem_to_amdgpu_bo(fb->obj[0]);
6337
f8308898
AG		 6338 /*
6339 * Wait for all fences on this FB. Do limited wait to avoid
6340 * deadlock during GPU reset when this fence will not signal
6341 * but we hold reservation lock for the BO.
6342 */
52791eee 6343 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
2fac0f53 6344 false,
f8308898
AG		 6345 msecs_to_jiffies(5000));
6346 if (unlikely(r <= 0))
ed8a5fb2 6347 DRM_ERROR("Waiting for fences timed out!");
2fac0f53 6348
f5031000
DF		 6349 /*
6350 * TODO This might fail and hence better not used, wait
6351 * explicitly on fences instead
6352 * and in general should be called for
6353 * blocking commit to as per framework helpers
6354 */
f5031000 6355 r = amdgpu_bo_reserve(abo, true);
f8308898 6356 if (unlikely(r != 0))
f5031000 6357 DRM_ERROR("failed to reserve buffer before flip\n");
8a48b44c 6358
f5031000 6359 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
8a48b44c 6360
f5031000 6361 amdgpu_bo_unreserve(abo);
8a48b44c 6362
695af5f9
NK		 6363 fill_dc_plane_info_and_addr(
6364 dm->adev, new_plane_state, tiling_flags,
6365 &bundle->plane_infos[planes_count],
6366 &bundle->flip_addrs[planes_count].address);
6367
6368 bundle->surface_updates[planes_count].plane_info =
6369 &bundle->plane_infos[planes_count];
8a48b44c 6370
caff0e66
NK		 6371 /*
6372 * Only allow immediate flips for fast updates that don't
6373 * change FB pitch, DCC state, rotation or mirroing.
6374 */
f5031000 6375 bundle->flip_addrs[planes_count].flip_immediate =
4d85f45c 6376 crtc->state->async_flip &&
caff0e66 6377 acrtc_state->update_type == UPDATE_TYPE_FAST;
8a48b44c 6378
f5031000
DF		 6379 timestamp_ns = ktime_get_ns();
6380 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
6381 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
6382 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 6383
f5031000
DF		 6384 if (!bundle->surface_updates[planes_count].surface) {
6385 DRM_ERROR("No surface for CRTC: id=%d\n",
6386 acrtc_attach->crtc_id);
6387 continue;
bc7f670e
DF		 6388 }
6389
f5031000
DF		 6390 if (plane == pcrtc->primary)
6391 update_freesync_state_on_stream(
6392 dm,
6393 acrtc_state,
6394 acrtc_state->stream,
6395 dc_plane,
6396 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
bc7f670e 6397
f5031000
DF		 6398 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
6399 __func__,
6400 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
6401 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
bc7f670e
DF		 6402
6403 planes_count += 1;
6404
8a48b44c
DF		 6405 }
6406
74aa7bd4 6407 if (pflip_present) {
634092b1
MK		 6408 if (!vrr_active) {
6409 /* Use old throttling in non-vrr fixed refresh rate mode
6410 * to keep flip scheduling based on target vblank counts
6411 * working in a backwards compatible way, e.g., for
6412 * clients using the GLX_OML_sync_control extension or
6413 * DRI3/Present extension with defined target_msc.
6414 */
fdd1fe57 6415 last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
634092b1
MK		 6416 }
6417 else {
6418 /* For variable refresh rate mode only:
6419 * Get vblank of last completed flip to avoid > 1 vrr
6420 * flips per video frame by use of throttling, but allow
6421 * flip programming anywhere in the possibly large
6422 * variable vrr vblank interval for fine-grained flip
6423 * timing control and more opportunity to avoid stutter
6424 * on late submission of flips.
6425 */
6426 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6427 last_flip_vblank = acrtc_attach->last_flip_vblank;
6428 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6429 }
6430
fdd1fe57 6431 target_vblank = last_flip_vblank + wait_for_vblank;
8a48b44c
DF		 6432
6433 /*
6434 * Wait until we're out of the vertical blank period before the one
6435 * targeted by the flip
6436 */
6437 while ((acrtc_attach->enabled &&
6438 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
6439 0, &vpos, &hpos, NULL,
6440 NULL, &pcrtc->hwmode)
6441 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
6442 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
6443 (int)(target_vblank -
6444 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
6445 usleep_range(1000, 1100);
6446 }
6447
6448 if (acrtc_attach->base.state->event) {
6449 drm_crtc_vblank_get(pcrtc);
6450
6451 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6452
6453 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
6454 prepare_flip_isr(acrtc_attach);
6455
6456 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6457 }
6458
6459 if (acrtc_state->stream) {
8a48b44c 6460 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 6461 bundle->stream_update.vrr_infopacket =
8a48b44c 6462 &acrtc_state->stream->vrr_infopacket;
e7b07cee 6463 }
e7b07cee
HW		 6464 }
6465
bc92c065 6466 /* Update the planes if changed or disable if we don't have any. */
ed9656fb
ES		 6467 if ((planes_count || acrtc_state->active_planes == 0) &&
6468 acrtc_state->stream) {
b6e881c9 6469 bundle->stream_update.stream = acrtc_state->stream;
bc7f670e 6470 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 6471 bundle->stream_update.src = acrtc_state->stream->src;
6472 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 6473 }
6474
cf020d49
NK		 6475 if (new_pcrtc_state->color_mgmt_changed) {
6476 /*
6477 * TODO: This isn't fully correct since we've actually
6478 * already modified the stream in place.
6479 */
6480 bundle->stream_update.gamut_remap =
6481 &acrtc_state->stream->gamut_remap_matrix;
6482 bundle->stream_update.output_csc_transform =
6483 &acrtc_state->stream->csc_color_matrix;
6484 bundle->stream_update.out_transfer_func =
6485 acrtc_state->stream->out_transfer_func;
6486 }
bc7f670e 6487
8a48b44c 6488 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 6489 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 6490 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 6491
e63e2491
EB		 6492 /*
6493 * If FreeSync state on the stream has changed then we need to
6494 * re-adjust the min/max bounds now that DC doesn't handle this
6495 * as part of commit.
6496 */
6497 if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
6498 amdgpu_dm_vrr_active(acrtc_state)) {
6499 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
6500 dc_stream_adjust_vmin_vmax(
6501 dm->dc, acrtc_state->stream,
6502 &acrtc_state->vrr_params.adjust);
6503 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
6504 }
bc7f670e 6505 mutex_lock(&dm->dc_lock);
8c322309
RL		 6506 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6507 acrtc_state->stream->link->psr_allow_active)
6508 amdgpu_dm_psr_disable(acrtc_state->stream);
6509
bc7f670e 6510 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 6511 bundle->surface_updates,
bc7f670e
DF		 6512 planes_count,
6513 acrtc_state->stream,
74aa7bd4 6514 &bundle->stream_update,
bc7f670e 6515 dc_state);
8c322309
RL		 6516
6517 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
6518 acrtc_state->stream->psr_version &&
6519 !acrtc_state->stream->link->psr_feature_enabled)
6520 amdgpu_dm_link_setup_psr(acrtc_state->stream);
6521 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
6522 acrtc_state->stream->link->psr_feature_enabled &&
6523 !acrtc_state->stream->link->psr_allow_active &&
6524 swizzle) {
6525 amdgpu_dm_psr_enable(acrtc_state->stream);
6526 }
6527
bc7f670e 6528 mutex_unlock(&dm->dc_lock);
e7b07cee 6529 }
4b510503 6530
8ad27806
NK		 6531 /*
6532 * Update cursor state *after* programming all the planes.
6533 * This avoids redundant programming in the case where we're going
6534 * to be disabling a single plane - those pipes are being disabled.
6535 */
6536 if (acrtc_state->active_planes)
6537 amdgpu_dm_commit_cursors(state);
80c218d5 6538
4b510503 6539cleanup:
74aa7bd4 6540 kfree(bundle);
e7b07cee
HW		 6541}
6542
6ce8f316
NK		 6543static void amdgpu_dm_commit_audio(struct drm_device *dev,
6544 struct drm_atomic_state *state)
6545{
6546 struct amdgpu_device *adev = dev->dev_private;
6547 struct amdgpu_dm_connector *aconnector;
6548 struct drm_connector *connector;
6549 struct drm_connector_state *old_con_state, *new_con_state;
6550 struct drm_crtc_state *new_crtc_state;
6551 struct dm_crtc_state *new_dm_crtc_state;
6552 const struct dc_stream_status *status;
6553 int i, inst;
6554
6555 /* Notify device removals. */
6556 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6557 if (old_con_state->crtc != new_con_state->crtc) {
6558 /* CRTC changes require notification. */
6559 goto notify;
6560 }
6561
6562 if (!new_con_state->crtc)
6563 continue;
6564
6565 new_crtc_state = drm_atomic_get_new_crtc_state(
6566 state, new_con_state->crtc);
6567
6568 if (!new_crtc_state)
6569 continue;
6570
6571 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6572 continue;
6573
6574 notify:
6575 aconnector = to_amdgpu_dm_connector(connector);
6576
6577 mutex_lock(&adev->dm.audio_lock);
6578 inst = aconnector->audio_inst;
6579 aconnector->audio_inst = -1;
6580 mutex_unlock(&adev->dm.audio_lock);
6581
6582 amdgpu_dm_audio_eld_notify(adev, inst);
6583 }
6584
6585 /* Notify audio device additions. */
6586 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6587 if (!new_con_state->crtc)
6588 continue;
6589
6590 new_crtc_state = drm_atomic_get_new_crtc_state(
6591 state, new_con_state->crtc);
6592
6593 if (!new_crtc_state)
6594 continue;
6595
6596 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6597 continue;
6598
6599 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6600 if (!new_dm_crtc_state->stream)
6601 continue;
6602
6603 status = dc_stream_get_status(new_dm_crtc_state->stream);
6604 if (!status)
6605 continue;
6606
6607 aconnector = to_amdgpu_dm_connector(connector);
6608
6609 mutex_lock(&adev->dm.audio_lock);
6610 inst = status->audio_inst;
6611 aconnector->audio_inst = inst;
6612 mutex_unlock(&adev->dm.audio_lock);
6613
6614 amdgpu_dm_audio_eld_notify(adev, inst);
6615 }
6616}
6617
b5e83f6f
NK		 6618/*
6619 * Enable interrupts on CRTCs that are newly active, undergone
6620 * a modeset, or have active planes again.
6621 *
6622 * Done in two passes, based on the for_modeset flag:
6623 * Pass 1: For CRTCs going through modeset
6624 * Pass 2: For CRTCs going from 0 to n active planes
6625 *
6626 * Interrupts can only be enabled after the planes are programmed,
6627 * so this requires a two-pass approach since we don't want to
6628 * just defer the interrupts until after commit planes every time.
6629 */
6630static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
6631 struct drm_atomic_state *state,
6632 bool for_modeset)
6633{
6634 struct amdgpu_device *adev = dev->dev_private;
6635 struct drm_crtc *crtc;
6636 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6637 int i;
148d31e3 6638#ifdef CONFIG_DEBUG_FS
14b25846 6639 enum amdgpu_dm_pipe_crc_source source;
148d31e3 6640#endif
b5e83f6f
NK		 6641
6642 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
6643 new_crtc_state, i) {
6644 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6645 struct dm_crtc_state *dm_new_crtc_state =
6646 to_dm_crtc_state(new_crtc_state);
6647 struct dm_crtc_state *dm_old_crtc_state =
6648 to_dm_crtc_state(old_crtc_state);
6649 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
6650 bool run_pass;
6651
6652 run_pass = (for_modeset && modeset) ||
6653 (!for_modeset && !modeset &&
6654 !dm_old_crtc_state->interrupts_enabled);
6655
6656 if (!run_pass)
6657 continue;
6658
b5e83f6f
NK		 6659 if (!dm_new_crtc_state->interrupts_enabled)
6660 continue;
6661
6662 manage_dm_interrupts(adev, acrtc, true);
6663
6664#ifdef CONFIG_DEBUG_FS
6665 /* The stream has changed so CRC capture needs to re-enabled. */
14b25846
DZ		 6666 source = dm_new_crtc_state->crc_src;
6667 if (amdgpu_dm_is_valid_crc_source(source)) {
57638021
NK		 6668 amdgpu_dm_crtc_configure_crc_source(
6669 crtc, dm_new_crtc_state,
6670 dm_new_crtc_state->crc_src);
b5e83f6f
NK		 6671 }
6672#endif
6673 }
6674}
6675
1f6010a9 6676/*
27b3f4fc
LSL		 6677 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
6678 * @crtc_state: the DRM CRTC state
6679 * @stream_state: the DC stream state.
6680 *
6681 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
6682 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
6683 */
6684static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
6685 struct dc_stream_state *stream_state)
6686{
b9952f93 6687 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 6688}
e7b07cee 6689
7578ecda
AD		 6690static int amdgpu_dm_atomic_commit(struct drm_device *dev,
6691 struct drm_atomic_state *state,
6692 bool nonblock)
e7b07cee
HW		 6693{
6694 struct drm_crtc *crtc;
c2cea706 6695 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 6696 struct amdgpu_device *adev = dev->dev_private;
6697 int i;
6698
6699 /*
d6ef9b41
NK		 6700 * We evade vblank and pflip interrupts on CRTCs that are undergoing
6701 * a modeset, being disabled, or have no active planes.
6702 *
6703 * It's done in atomic commit rather than commit tail for now since
6704 * some of these interrupt handlers access the current CRTC state and
6705 * potentially the stream pointer itself.
6706 *
6707 * Since the atomic state is swapped within atomic commit and not within
6708 * commit tail this would leave to new state (that hasn't been committed yet)
6709 * being accesssed from within the handlers.
6710 *
6711 * TODO: Fix this so we can do this in commit tail and not have to block
6712 * in atomic check.
e7b07cee 6713 */
c2cea706 6714 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 6715 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
428da2bd 6716 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 6717 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
6718
d6ef9b41
NK		 6719 if (dm_old_crtc_state->interrupts_enabled &&
6720 (!dm_new_crtc_state->interrupts_enabled ||
57638021 6721 drm_atomic_crtc_needs_modeset(new_crtc_state)))
e7b07cee
HW		 6722 manage_dm_interrupts(adev, acrtc, false);
6723 }
1f6010a9
DF		 6724 /*
6725 * Add check here for SoC's that support hardware cursor plane, to
6726 * unset legacy_cursor_update
6727 */
e7b07cee
HW		 6728
6729 return drm_atomic_helper_commit(dev, state, nonblock);
6730
6731 /*TODO Handle EINTR, reenable IRQ*/
6732}
6733
b8592b48
LL		 6734/**
6735 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
6736 * @state: The atomic state to commit
6737 *
6738 * This will tell DC to commit the constructed DC state from atomic_check,
6739 * programming the hardware. Any failures here implies a hardware failure, since
6740 * atomic check should have filtered anything non-kosher.
6741 */
7578ecda 6742static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 6743{
6744 struct drm_device *dev = state->dev;
6745 struct amdgpu_device *adev = dev->dev_private;
6746 struct amdgpu_display_manager *dm = &adev->dm;
6747 struct dm_atomic_state *dm_state;
eb3dc897 6748 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 6749 uint32_t i, j;
5cc6dcbd 6750 struct drm_crtc *crtc;
0bc9706d 6751 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 6752 unsigned long flags;
6753 bool wait_for_vblank = true;
6754 struct drm_connector *connector;
c2cea706 6755 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 6756 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 6757 int crtc_disable_count = 0;
e7b07cee
HW		 6758
6759 drm_atomic_helper_update_legacy_modeset_state(dev, state);
6760
eb3dc897
NK		 6761 dm_state = dm_atomic_get_new_state(state);
6762 if (dm_state && dm_state->context) {
6763 dc_state = dm_state->context;
6764 } else {
6765 /* No state changes, retain current state. */
813d20dc 6766 dc_state_temp = dc_create_state(dm->dc);
eb3dc897
NK		 6767 ASSERT(dc_state_temp);
6768 dc_state = dc_state_temp;
6769 dc_resource_state_copy_construct_current(dm->dc, dc_state);
6770 }
e7b07cee
HW		 6771
6772 /* update changed items */
0bc9706d 6773 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 6774 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 6775
54d76575
LSL		 6776 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6777 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 6778
f1ad2f5e 6779 DRM_DEBUG_DRIVER(
e7b07cee
HW		 6780 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6781 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6782 "connectors_changed:%d\n",
6783 acrtc->crtc_id,
0bc9706d
LSL		 6784 new_crtc_state->enable,
6785 new_crtc_state->active,
6786 new_crtc_state->planes_changed,
6787 new_crtc_state->mode_changed,
6788 new_crtc_state->active_changed,
6789 new_crtc_state->connectors_changed);
e7b07cee 6790
27b3f4fc
LSL		 6791 /* Copy all transient state flags into dc state */
6792 if (dm_new_crtc_state->stream) {
6793 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
6794 dm_new_crtc_state->stream);
6795 }
6796
e7b07cee
HW		 6797 /* handles headless hotplug case, updating new_state and
6798 * aconnector as needed
6799 */
6800
54d76575 6801 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 6802
f1ad2f5e 6803 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 6804
54d76575 6805 if (!dm_new_crtc_state->stream) {
e7b07cee 6806 /*
b830ebc9
HW		 6807 * this could happen because of issues with
6808 * userspace notifications delivery.
6809 * In this case userspace tries to set mode on
1f6010a9
DF		 6810 * display which is disconnected in fact.
6811 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 6812 * We expect reset mode will come soon.
6813 *
6814 * This can also happen when unplug is done
6815 * during resume sequence ended
6816 *
6817 * In this case, we want to pretend we still
6818 * have a sink to keep the pipe running so that
6819 * hw state is consistent with the sw state
6820 */
f1ad2f5e 6821 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 6822 __func__, acrtc->base.base.id);
6823 continue;
6824 }
6825
54d76575
LSL		 6826 if (dm_old_crtc_state->stream)
6827 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 6828
97028037
LP		 6829 pm_runtime_get_noresume(dev->dev);
6830
e7b07cee 6831 acrtc->enabled = true;
0bc9706d
LSL		 6832 acrtc->hw_mode = new_crtc_state->mode;
6833 crtc->hwmode = new_crtc_state->mode;
6834 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 6835 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 6836 /* i.e. reset mode */
8c322309
RL		 6837 if (dm_old_crtc_state->stream) {
6838 if (dm_old_crtc_state->stream->link->psr_allow_active)
6839 amdgpu_dm_psr_disable(dm_old_crtc_state->stream);
6840
54d76575 6841 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8c322309 6842 }
e7b07cee
HW		 6843 }
6844 } /* for_each_crtc_in_state() */
6845
eb3dc897
NK		 6846 if (dc_state) {
6847 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 6848 mutex_lock(&dm->dc_lock);
eb3dc897 6849 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 6850 mutex_unlock(&dm->dc_lock);
fa2123db 6851 }
e7b07cee 6852
0bc9706d 6853 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 6854 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 6855
54d76575 6856 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 6857
54d76575 6858 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 6859 const struct dc_stream_status *status =
54d76575 6860 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 6861
eb3dc897 6862 if (!status)
09f609c3
LL		 6863 status = dc_stream_get_status_from_state(dc_state,
6864 dm_new_crtc_state->stream);
eb3dc897 6865
e7b07cee 6866 if (!status)
54d76575 6867 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 6868 else
6869 acrtc->otg_inst = status->primary_otg_inst;
6870 }
6871 }
0c8620d6
BL		 6872#ifdef CONFIG_DRM_AMD_DC_HDCP
6873 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6874 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6875 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6876 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6877
6878 new_crtc_state = NULL;
6879
6880 if (acrtc)
6881 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
6882
6883 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6884
6885 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
6886 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
6887 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
6888 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
6889 continue;
6890 }
6891
6892 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
b1abe558
BL		 6893 hdcp_update_display(
6894 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
23eb4191 6895 new_con_state->hdcp_content_type,
b1abe558
BL		 6896 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
6897 : false);
0c8620d6
BL		 6898 }
6899#endif
e7b07cee 6900
02d6a6fc 6901 /* Handle connector state changes */
c2cea706 6902 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 6903 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6904 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6905 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
19afd799
NC		 6906 struct dc_surface_update dummy_updates[MAX_SURFACES];
6907 struct dc_stream_update stream_update;
b232d4ed 6908 struct dc_info_packet hdr_packet;
e7b07cee 6909 struct dc_stream_status *status = NULL;
b232d4ed 6910 bool abm_changed, hdr_changed, scaling_changed;
e7b07cee 6911
19afd799
NC		 6912 memset(&dummy_updates, 0, sizeof(dummy_updates));
6913 memset(&stream_update, 0, sizeof(stream_update));
6914
44d09c6a 6915 if (acrtc) {
0bc9706d 6916 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 6917 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
6918 }
0bc9706d 6919
e7b07cee 6920 /* Skip any modesets/resets */
0bc9706d 6921 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 6922 continue;
6923
54d76575 6924 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 6925 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6926
b232d4ed
NK		 6927 scaling_changed = is_scaling_state_different(dm_new_con_state,
6928 dm_old_con_state);
6929
6930 abm_changed = dm_new_crtc_state->abm_level !=
6931 dm_old_crtc_state->abm_level;
6932
6933 hdr_changed =
6934 is_hdr_metadata_different(old_con_state, new_con_state);
6935
6936 if (!scaling_changed && !abm_changed && !hdr_changed)
c1ee92f9 6937 continue;
e7b07cee 6938
b6e881c9 6939 stream_update.stream = dm_new_crtc_state->stream;
b232d4ed 6940 if (scaling_changed) {
02d6a6fc 6941 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
b6e881c9 6942 dm_new_con_state, dm_new_crtc_state->stream);
e7b07cee 6943
02d6a6fc
DF		 6944 stream_update.src = dm_new_crtc_state->stream->src;
6945 stream_update.dst = dm_new_crtc_state->stream->dst;
6946 }
6947
b232d4ed 6948 if (abm_changed) {
02d6a6fc
DF		 6949 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
6950
6951 stream_update.abm_level = &dm_new_crtc_state->abm_level;
6952 }
70e8ffc5 6953
b232d4ed
NK		 6954 if (hdr_changed) {
6955 fill_hdr_info_packet(new_con_state, &hdr_packet);
6956 stream_update.hdr_static_metadata = &hdr_packet;
6957 }
6958
54d76575 6959 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 6960 WARN_ON(!status);
3be5262e 6961 WARN_ON(!status->plane_count);
e7b07cee 6962
02d6a6fc
DF		 6963 /*
6964 * TODO: DC refuses to perform stream updates without a dc_surface_update.
6965 * Here we create an empty update on each plane.
6966 * To fix this, DC should permit updating only stream properties.
6967 */
6968 for (j = 0; j < status->plane_count; j++)
6969 dummy_updates[j].surface = status->plane_states[0];
6970
6971
6972 mutex_lock(&dm->dc_lock);
6973 dc_commit_updates_for_stream(dm->dc,
6974 dummy_updates,
6975 status->plane_count,
6976 dm_new_crtc_state->stream,
6977 &stream_update,
6978 dc_state);
6979 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 6980 }
6981
b5e83f6f 6982 /* Count number of newly disabled CRTCs for dropping PM refs later. */
e1fc2dca 6983 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
057be086 6984 new_crtc_state, i) {
fe2a1965
LP		 6985 if (old_crtc_state->active && !new_crtc_state->active)
6986 crtc_disable_count++;
6987
54d76575 6988 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca 6989 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
66b0c973 6990
057be086
NK		 6991 /* Update freesync active state. */
6992 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
6993
66b0c973
MK		 6994 /* Handle vrr on->off / off->on transitions */
6995 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
6996 dm_new_crtc_state);
e7b07cee
HW		 6997 }
6998
b5e83f6f
NK		 6999 /* Enable interrupts for CRTCs going through a modeset. */
7000 amdgpu_dm_enable_crtc_interrupts(dev, state, true);
e7b07cee 7001
420cd472 7002 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
4d85f45c 7003 if (new_crtc_state->async_flip)
420cd472
DF		 7004 wait_for_vblank = false;
7005
e7b07cee 7006 /* update planes when needed per crtc*/
5cc6dcbd 7007 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 7008 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 7009
54d76575 7010 if (dm_new_crtc_state->stream)
eb3dc897 7011 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 7012 dm, crtc, wait_for_vblank);
e7b07cee
HW		 7013 }
7014
b5e83f6f
NK		 7015 /* Enable interrupts for CRTCs going from 0 to n active planes. */
7016 amdgpu_dm_enable_crtc_interrupts(dev, state, false);
e7b07cee 7017
6ce8f316
NK		 7018 /* Update audio instances for each connector. */
7019 amdgpu_dm_commit_audio(dev, state);
7020
e7b07cee
HW		 7021 /*
7022 * send vblank event on all events not handled in flip and
7023 * mark consumed event for drm_atomic_helper_commit_hw_done
7024 */
7025 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 7026 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 7027
0bc9706d
LSL		 7028 if (new_crtc_state->event)
7029 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 7030
0bc9706d 7031 new_crtc_state->event = NULL;
e7b07cee
HW		 7032 }
7033 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
7034
29c8f234
LL		 7035 /* Signal HW programming completion */
7036 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 7037
7038 if (wait_for_vblank)
320a1274 7039 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 7040
7041 drm_atomic_helper_cleanup_planes(dev, state);
97028037 7042
1f6010a9
DF		 7043 /*
7044 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 7045 * so we can put the GPU into runtime suspend if we're not driving any
7046 * displays anymore
7047 */
fe2a1965
LP		 7048 for (i = 0; i < crtc_disable_count; i++)
7049 pm_runtime_put_autosuspend(dev->dev);
97028037 7050 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 7051
7052 if (dc_state_temp)
7053 dc_release_state(dc_state_temp);
e7b07cee
HW		 7054}
7055
7056
7057static int dm_force_atomic_commit(struct drm_connector *connector)
7058{
7059 int ret = 0;
7060 struct drm_device *ddev = connector->dev;
7061 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
7062 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
7063 struct drm_plane *plane = disconnected_acrtc->base.primary;
7064 struct drm_connector_state *conn_state;
7065 struct drm_crtc_state *crtc_state;
7066 struct drm_plane_state *plane_state;
7067
7068 if (!state)
7069 return -ENOMEM;
7070
7071 state->acquire_ctx = ddev->mode_config.acquire_ctx;
7072
7073 /* Construct an atomic state to restore previous display setting */
7074
7075 /*
7076 * Attach connectors to drm_atomic_state
7077 */
7078 conn_state = drm_atomic_get_connector_state(state, connector);
7079
7080 ret = PTR_ERR_OR_ZERO(conn_state);
7081 if (ret)
7082 goto err;
7083
7084 /* Attach crtc to drm_atomic_state*/
7085 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
7086
7087 ret = PTR_ERR_OR_ZERO(crtc_state);
7088 if (ret)
7089 goto err;
7090
7091 /* force a restore */
7092 crtc_state->mode_changed = true;
7093
7094 /* Attach plane to drm_atomic_state */
7095 plane_state = drm_atomic_get_plane_state(state, plane);
7096
7097 ret = PTR_ERR_OR_ZERO(plane_state);
7098 if (ret)
7099 goto err;
7100
7101
7102 /* Call commit internally with the state we just constructed */
7103 ret = drm_atomic_commit(state);
7104 if (!ret)
7105 return 0;
7106
7107err:
7108 DRM_ERROR("Restoring old state failed with %i\n", ret);
7109 drm_atomic_state_put(state);
7110
7111 return ret;
7112}
7113
7114/*
1f6010a9
DF		 7115 * This function handles all cases when set mode does not come upon hotplug.
7116 * This includes when a display is unplugged then plugged back into the
7117 * same port and when running without usermode desktop manager supprot
e7b07cee 7118 */
3ee6b26b
AD		 7119void dm_restore_drm_connector_state(struct drm_device *dev,
7120 struct drm_connector *connector)
e7b07cee 7121{
c84dec2f 7122 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 7123 struct amdgpu_crtc *disconnected_acrtc;
7124 struct dm_crtc_state *acrtc_state;
7125
7126 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
7127 return;
7128
7129 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 7130 if (!disconnected_acrtc)
7131 return;
e7b07cee 7132
70e8ffc5
HW		 7133 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
7134 if (!acrtc_state->stream)
e7b07cee
HW		 7135 return;
7136
7137 /*
7138 * If the previous sink is not released and different from the current,
7139 * we deduce we are in a state where we can not rely on usermode call
7140 * to turn on the display, so we do it here
7141 */
7142 if (acrtc_state->stream->sink != aconnector->dc_sink)
7143 dm_force_atomic_commit(&aconnector->base);
7144}
7145
1f6010a9 7146/*
e7b07cee
HW		 7147 * Grabs all modesetting locks to serialize against any blocking commits,
7148 * Waits for completion of all non blocking commits.
7149 */
3ee6b26b
AD		 7150static int do_aquire_global_lock(struct drm_device *dev,
7151 struct drm_atomic_state *state)
e7b07cee
HW		 7152{
7153 struct drm_crtc *crtc;
7154 struct drm_crtc_commit *commit;
7155 long ret;
7156
1f6010a9
DF		 7157 /*
7158 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 7159 * ensure that when the framework release it the
7160 * extra locks we are locking here will get released to
7161 */
7162 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
7163 if (ret)
7164 return ret;
7165
7166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7167 spin_lock(&crtc->commit_lock);
7168 commit = list_first_entry_or_null(&crtc->commit_list,
7169 struct drm_crtc_commit, commit_entry);
7170 if (commit)
7171 drm_crtc_commit_get(commit);
7172 spin_unlock(&crtc->commit_lock);
7173
7174 if (!commit)
7175 continue;
7176
1f6010a9
DF		 7177 /*
7178 * Make sure all pending HW programming completed and
e7b07cee
HW		 7179 * page flips done
7180 */
7181 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
7182
7183 if (ret > 0)
7184 ret = wait_for_completion_interruptible_timeout(
7185 &commit->flip_done, 10*HZ);
7186
7187 if (ret == 0)
7188 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 7189 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 7190
7191 drm_crtc_commit_put(commit);
7192 }
7193
7194 return ret < 0 ? ret : 0;
7195}
7196
bb47de73
NK		 7197static void get_freesync_config_for_crtc(
7198 struct dm_crtc_state *new_crtc_state,
7199 struct dm_connector_state *new_con_state)
98e6436d
AK		 7200{
7201 struct mod_freesync_config config = {0};
98e6436d
AK		 7202 struct amdgpu_dm_connector *aconnector =
7203 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 7204 struct drm_display_mode *mode = &new_crtc_state->base.mode;
0ab925d3 7205 int vrefresh = drm_mode_vrefresh(mode);
98e6436d 7206
a057ec46 7207 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
0ab925d3
NK		 7208 vrefresh >= aconnector->min_vfreq &&
7209 vrefresh <= aconnector->max_vfreq;
bb47de73 7210
a057ec46
IB		 7211 if (new_crtc_state->vrr_supported) {
7212 new_crtc_state->stream->ignore_msa_timing_param = true;
bb47de73 7213 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 7214 VRR_STATE_ACTIVE_VARIABLE :
7215 VRR_STATE_INACTIVE;
7216 config.min_refresh_in_uhz =
7217 aconnector->min_vfreq * 1000000;
7218 config.max_refresh_in_uhz =
7219 aconnector->max_vfreq * 1000000;
69ff8845 7220 config.vsif_supported = true;
180db303 7221 config.btr = true;
98e6436d
AK		 7222 }
7223
bb47de73
NK		 7224 new_crtc_state->freesync_config = config;
7225}
98e6436d 7226
bb47de73
NK		 7227static void reset_freesync_config_for_crtc(
7228 struct dm_crtc_state *new_crtc_state)
7229{
7230 new_crtc_state->vrr_supported = false;
98e6436d 7231
180db303
NK		 7232 memset(&new_crtc_state->vrr_params, 0,
7233 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 7234 memset(&new_crtc_state->vrr_infopacket, 0,
7235 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 7236}
7237
4b9674e5
LL		 7238static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
7239 struct drm_atomic_state *state,
7240 struct drm_crtc *crtc,
7241 struct drm_crtc_state *old_crtc_state,
7242 struct drm_crtc_state *new_crtc_state,
7243 bool enable,
7244 bool *lock_and_validation_needed)
e7b07cee 7245{
eb3dc897 7246 struct dm_atomic_state *dm_state = NULL;
54d76575 7247 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 7248 struct dc_stream_state *new_stream;
62f55537 7249 int ret = 0;
d4d4a645 7250
1f6010a9
DF		 7251 /*
7252 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
7253 * update changed items
7254 */
4b9674e5
LL		 7255 struct amdgpu_crtc *acrtc = NULL;
7256 struct amdgpu_dm_connector *aconnector = NULL;
7257 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
7258 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
e7b07cee 7259
4b9674e5 7260 new_stream = NULL;
9635b754 7261
4b9674e5
LL		 7262 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7263 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7264 acrtc = to_amdgpu_crtc(crtc);
4b9674e5 7265 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 7266
4b9674e5
LL		 7267 /* TODO This hack should go away */
7268 if (aconnector && enable) {
7269 /* Make sure fake sink is created in plug-in scenario */
7270 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
7271 &aconnector->base);
7272 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
7273 &aconnector->base);
19f89e23 7274
4b9674e5
LL		 7275 if (IS_ERR(drm_new_conn_state)) {
7276 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
7277 goto fail;
7278 }
19f89e23 7279
4b9674e5
LL		 7280 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
7281 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 7282
02d35a67
JFZ		 7283 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7284 goto skip_modeset;
7285
4b9674e5
LL		 7286 new_stream = create_stream_for_sink(aconnector,
7287 &new_crtc_state->mode,
7288 dm_new_conn_state,
7289 dm_old_crtc_state->stream);
19f89e23 7290
4b9674e5
LL		 7291 /*
7292 * we can have no stream on ACTION_SET if a display
7293 * was disconnected during S3, in this case it is not an
7294 * error, the OS will be updated after detection, and
7295 * will do the right thing on next atomic commit
7296 */
19f89e23 7297
4b9674e5
LL		 7298 if (!new_stream) {
7299 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
7300 __func__, acrtc->base.base.id);
7301 ret = -ENOMEM;
7302 goto fail;
7303 }
e7b07cee 7304
4b9674e5 7305 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 7306
88694af9
NK		 7307 ret = fill_hdr_info_packet(drm_new_conn_state,
7308 &new_stream->hdr_static_metadata);
7309 if (ret)
7310 goto fail;
7311
7e930949
NK		 7312 /*
7313 * If we already removed the old stream from the context
7314 * (and set the new stream to NULL) then we can't reuse
7315 * the old stream even if the stream and scaling are unchanged.
7316 * We'll hit the BUG_ON and black screen.
7317 *
7318 * TODO: Refactor this function to allow this check to work
7319 * in all conditions.
7320 */
7321 if (dm_new_crtc_state->stream &&
7322 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4b9674e5
LL		 7323 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
7324 new_crtc_state->mode_changed = false;
7325 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
7326 new_crtc_state->mode_changed);
62f55537 7327 }
4b9674e5 7328 }
b830ebc9 7329
02d35a67 7330 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 7331 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7332 goto skip_modeset;
e7b07cee 7333
4b9674e5
LL		 7334 DRM_DEBUG_DRIVER(
7335 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
7336 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
7337 "connectors_changed:%d\n",
7338 acrtc->crtc_id,
7339 new_crtc_state->enable,
7340 new_crtc_state->active,
7341 new_crtc_state->planes_changed,
7342 new_crtc_state->mode_changed,
7343 new_crtc_state->active_changed,
7344 new_crtc_state->connectors_changed);
62f55537 7345
4b9674e5
LL		 7346 /* Remove stream for any changed/disabled CRTC */
7347 if (!enable) {
62f55537 7348
4b9674e5
LL		 7349 if (!dm_old_crtc_state->stream)
7350 goto skip_modeset;
eb3dc897 7351
4b9674e5
LL		 7352 ret = dm_atomic_get_state(state, &dm_state);
7353 if (ret)
7354 goto fail;
e7b07cee 7355
4b9674e5
LL		 7356 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
7357 crtc->base.id);
62f55537 7358
4b9674e5
LL		 7359 /* i.e. reset mode */
7360 if (dc_remove_stream_from_ctx(
7361 dm->dc,
7362 dm_state->context,
7363 dm_old_crtc_state->stream) != DC_OK) {
7364 ret = -EINVAL;
7365 goto fail;
7366 }
62f55537 7367
4b9674e5
LL		 7368 dc_stream_release(dm_old_crtc_state->stream);
7369 dm_new_crtc_state->stream = NULL;
bb47de73 7370
4b9674e5 7371 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 7372
4b9674e5 7373 *lock_and_validation_needed = true;
62f55537 7374
4b9674e5
LL		 7375 } else {/* Add stream for any updated/enabled CRTC */
7376 /*
7377 * Quick fix to prevent NULL pointer on new_stream when
7378 * added MST connectors not found in existing crtc_state in the chained mode
7379 * TODO: need to dig out the root cause of that
7380 */
7381 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
7382 goto skip_modeset;
62f55537 7383
4b9674e5
LL		 7384 if (modereset_required(new_crtc_state))
7385 goto skip_modeset;
62f55537 7386
4b9674e5
LL		 7387 if (modeset_required(new_crtc_state, new_stream,
7388 dm_old_crtc_state->stream)) {
62f55537 7389
4b9674e5 7390 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 7391
4b9674e5
LL		 7392 ret = dm_atomic_get_state(state, &dm_state);
7393 if (ret)
7394 goto fail;
27b3f4fc 7395
4b9674e5 7396 dm_new_crtc_state->stream = new_stream;
62f55537 7397
4b9674e5 7398 dc_stream_retain(new_stream);
1dc90497 7399
4b9674e5
LL		 7400 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
7401 crtc->base.id);
1dc90497 7402
4b9674e5
LL		 7403 if (dc_add_stream_to_ctx(
7404 dm->dc,
7405 dm_state->context,
7406 dm_new_crtc_state->stream) != DC_OK) {
7407 ret = -EINVAL;
7408 goto fail;
9b690ef3
BL		 7409 }
7410
4b9674e5
LL		 7411 *lock_and_validation_needed = true;
7412 }
7413 }
e277adc5 7414
4b9674e5
LL		 7415skip_modeset:
7416 /* Release extra reference */
7417 if (new_stream)
7418 dc_stream_release(new_stream);
e277adc5 7419
4b9674e5
LL		 7420 /*
7421 * We want to do dc stream updates that do not require a
7422 * full modeset below.
7423 */
7424 if (!(enable && aconnector && new_crtc_state->enable &&
7425 new_crtc_state->active))
7426 return 0;
7427 /*
7428 * Given above conditions, the dc state cannot be NULL because:
7429 * 1. We're in the process of enabling CRTCs (just been added
7430 * to the dc context, or already is on the context)
7431 * 2. Has a valid connector attached, and
7432 * 3. Is currently active and enabled.
7433 * => The dc stream state currently exists.
7434 */
7435 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 7436
4b9674e5
LL		 7437 /* Scaling or underscan settings */
7438 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
7439 update_stream_scaling_settings(
7440 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 7441
b05e2c5e
DF		 7442 /* ABM settings */
7443 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
7444
4b9674e5
LL		 7445 /*
7446 * Color management settings. We also update color properties
7447 * when a modeset is needed, to ensure it gets reprogrammed.
7448 */
7449 if (dm_new_crtc_state->base.color_mgmt_changed ||
7450 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
cf020d49 7451 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
4b9674e5
LL		 7452 if (ret)
7453 goto fail;
62f55537 7454 }
e7b07cee 7455
4b9674e5
LL		 7456 /* Update Freesync settings. */
7457 get_freesync_config_for_crtc(dm_new_crtc_state,
7458 dm_new_conn_state);
7459
62f55537 7460 return ret;
9635b754
DS		 7461
7462fail:
7463 if (new_stream)
7464 dc_stream_release(new_stream);
7465 return ret;
62f55537 7466}
9b690ef3 7467
f6ff2a08
NK		 7468static bool should_reset_plane(struct drm_atomic_state *state,
7469 struct drm_plane *plane,
7470 struct drm_plane_state *old_plane_state,
7471 struct drm_plane_state *new_plane_state)
7472{
7473 struct drm_plane *other;
7474 struct drm_plane_state *old_other_state, *new_other_state;
7475 struct drm_crtc_state *new_crtc_state;
7476 int i;
7477
70a1efac
NK		 7478 /*
7479 * TODO: Remove this hack once the checks below are sufficient
7480 * enough to determine when we need to reset all the planes on
7481 * the stream.
7482 */
7483 if (state->allow_modeset)
7484 return true;
7485
f6ff2a08
NK		 7486 /* Exit early if we know that we're adding or removing the plane. */
7487 if (old_plane_state->crtc != new_plane_state->crtc)
7488 return true;
7489
7490 /* old crtc == new_crtc == NULL, plane not in context. */
7491 if (!new_plane_state->crtc)
7492 return false;
7493
7494 new_crtc_state =
7495 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
7496
7497 if (!new_crtc_state)
7498 return true;
7499
7316c4ad
NK		 7500 /* CRTC Degamma changes currently require us to recreate planes. */
7501 if (new_crtc_state->color_mgmt_changed)
7502 return true;
7503
f6ff2a08
NK		 7504 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
7505 return true;
7506
7507 /*
7508 * If there are any new primary or overlay planes being added or
7509 * removed then the z-order can potentially change. To ensure
7510 * correct z-order and pipe acquisition the current DC architecture
7511 * requires us to remove and recreate all existing planes.
7512 *
7513 * TODO: Come up with a more elegant solution for this.
7514 */
7515 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
7516 if (other->type == DRM_PLANE_TYPE_CURSOR)
7517 continue;
7518
7519 if (old_other_state->crtc != new_plane_state->crtc &&
7520 new_other_state->crtc != new_plane_state->crtc)
7521 continue;
7522
7523 if (old_other_state->crtc != new_other_state->crtc)
7524 return true;
7525
7526 /* TODO: Remove this once we can handle fast format changes. */
7527 if (old_other_state->fb && new_other_state->fb &&
7528 old_other_state->fb->format != new_other_state->fb->format)
7529 return true;
7530 }
7531
7532 return false;
7533}
7534
9e869063
LL		 7535static int dm_update_plane_state(struct dc *dc,
7536 struct drm_atomic_state *state,
7537 struct drm_plane *plane,
7538 struct drm_plane_state *old_plane_state,
7539 struct drm_plane_state *new_plane_state,
7540 bool enable,
7541 bool *lock_and_validation_needed)
62f55537 7542{
eb3dc897
NK		 7543
7544 struct dm_atomic_state *dm_state = NULL;
62f55537 7545 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 7546 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 7547 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 7548 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
f6ff2a08 7549 bool needs_reset;
62f55537 7550 int ret = 0;
e7b07cee 7551
9b690ef3 7552
9e869063
LL		 7553 new_plane_crtc = new_plane_state->crtc;
7554 old_plane_crtc = old_plane_state->crtc;
7555 dm_new_plane_state = to_dm_plane_state(new_plane_state);
7556 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 7557
9e869063
LL		 7558 /*TODO Implement atomic check for cursor plane */
7559 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7560 return 0;
9b690ef3 7561
f6ff2a08
NK		 7562 needs_reset = should_reset_plane(state, plane, old_plane_state,
7563 new_plane_state);
7564
9e869063
LL		 7565 /* Remove any changed/removed planes */
7566 if (!enable) {
f6ff2a08 7567 if (!needs_reset)
9e869063 7568 return 0;
a7b06724 7569
9e869063
LL		 7570 if (!old_plane_crtc)
7571 return 0;
62f55537 7572
9e869063
LL		 7573 old_crtc_state = drm_atomic_get_old_crtc_state(
7574 state, old_plane_crtc);
7575 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 7576
9e869063
LL		 7577 if (!dm_old_crtc_state->stream)
7578 return 0;
62f55537 7579
9e869063
LL		 7580 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
7581 plane->base.id, old_plane_crtc->base.id);
9b690ef3 7582
9e869063
LL		 7583 ret = dm_atomic_get_state(state, &dm_state);
7584 if (ret)
7585 return ret;
eb3dc897 7586
9e869063
LL		 7587 if (!dc_remove_plane_from_context(
7588 dc,
7589 dm_old_crtc_state->stream,
7590 dm_old_plane_state->dc_state,
7591 dm_state->context)) {
62f55537 7592
9e869063
LL		 7593 ret = EINVAL;
7594 return ret;
7595 }
e7b07cee 7596
9b690ef3 7597
9e869063
LL		 7598 dc_plane_state_release(dm_old_plane_state->dc_state);
7599 dm_new_plane_state->dc_state = NULL;
1dc90497 7600
9e869063 7601 *lock_and_validation_needed = true;
1dc90497 7602
9e869063
LL		 7603 } else { /* Add new planes */
7604 struct dc_plane_state *dc_new_plane_state;
1dc90497 7605
9e869063
LL		 7606 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
7607 return 0;
e7b07cee 7608
9e869063
LL		 7609 if (!new_plane_crtc)
7610 return 0;
e7b07cee 7611
9e869063
LL		 7612 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
7613 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 7614
9e869063
LL		 7615 if (!dm_new_crtc_state->stream)
7616 return 0;
62f55537 7617
f6ff2a08 7618 if (!needs_reset)
9e869063 7619 return 0;
62f55537 7620
9e869063 7621 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 7622
9e869063
LL		 7623 dc_new_plane_state = dc_create_plane_state(dc);
7624 if (!dc_new_plane_state)
7625 return -ENOMEM;
62f55537 7626
9e869063
LL		 7627 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
7628 plane->base.id, new_plane_crtc->base.id);
8c45c5db 7629
695af5f9 7630 ret = fill_dc_plane_attributes(
9e869063
LL		 7631 new_plane_crtc->dev->dev_private,
7632 dc_new_plane_state,
7633 new_plane_state,
7634 new_crtc_state);
7635 if (ret) {
7636 dc_plane_state_release(dc_new_plane_state);
7637 return ret;
7638 }
62f55537 7639
9e869063
LL		 7640 ret = dm_atomic_get_state(state, &dm_state);
7641 if (ret) {
7642 dc_plane_state_release(dc_new_plane_state);
7643 return ret;
7644 }
eb3dc897 7645
9e869063
LL		 7646 /*
7647 * Any atomic check errors that occur after this will
7648 * not need a release. The plane state will be attached
7649 * to the stream, and therefore part of the atomic
7650 * state. It'll be released when the atomic state is
7651 * cleaned.
7652 */
7653 if (!dc_add_plane_to_context(
7654 dc,
7655 dm_new_crtc_state->stream,
7656 dc_new_plane_state,
7657 dm_state->context)) {
62f55537 7658
9e869063
LL		 7659 dc_plane_state_release(dc_new_plane_state);
7660 return -EINVAL;
7661 }
8c45c5db 7662
9e869063 7663 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 7664
9e869063
LL		 7665 /* Tell DC to do a full surface update every time there
7666 * is a plane change. Inefficient, but works for now.
7667 */
7668 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
7669
7670 *lock_and_validation_needed = true;
62f55537 7671 }
e7b07cee
HW		 7672
7673
62f55537
AG		 7674 return ret;
7675}
a87fa993 7676
eb3dc897 7677static int
f843b308 7678dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
eb3dc897
NK		 7679 struct drm_atomic_state *state,
7680 enum surface_update_type *out_type)
7681{
f843b308 7682 struct dc *dc = dm->dc;
eb3dc897
NK		 7683 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
7684 int i, j, num_plane, ret = 0;
a87fa993
BL		 7685 struct drm_plane_state *old_plane_state, *new_plane_state;
7686 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
d3b65841 7687 struct drm_crtc *new_plane_crtc;
a87fa993
BL		 7688 struct drm_plane *plane;
7689
7690 struct drm_crtc *crtc;
7691 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
7692 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
7693 struct dc_stream_status *status = NULL;
7694
fe96b99d 7695 struct dc_surface_update *updates;
a87fa993
BL		 7696 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7697
fe96b99d 7698 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
fe96b99d 7699
f843b308
NK		 7700 if (!updates) {
7701 DRM_ERROR("Failed to allocate plane updates\n");
4f712911
BL		 7702 /* Set type to FULL to avoid crashing in DC*/
7703 update_type = UPDATE_TYPE_FULL;
eb3dc897 7704 goto cleanup;
4f712911 7705 }
a87fa993
BL		 7706
7707 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
004b3938 7708 struct dc_scaling_info scaling_info;
2aa632c5
NK		 7709 struct dc_stream_update stream_update;
7710
7711 memset(&stream_update, 0, sizeof(stream_update));
c448a53a 7712
a87fa993
BL		 7713 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7714 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
7715 num_plane = 0;
7716
6836d239
NK		 7717 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
7718 update_type = UPDATE_TYPE_FULL;
7719 goto cleanup;
7720 }
a87fa993 7721
6836d239 7722 if (!new_dm_crtc_state->stream)
c744e974 7723 continue;
eb3dc897 7724
c744e974 7725 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
2cc450ce
NK		 7726 const struct amdgpu_framebuffer *amdgpu_fb =
7727 to_amdgpu_framebuffer(new_plane_state->fb);
7728 struct dc_plane_info plane_info;
7729 struct dc_flip_addrs flip_addr;
7730 uint64_t tiling_flags;
7731
c744e974 7732 new_plane_crtc = new_plane_state->crtc;
c744e974
NK		 7733 new_dm_plane_state = to_dm_plane_state(new_plane_state);
7734 old_dm_plane_state = to_dm_plane_state(old_plane_state);
eb3dc897 7735
c744e974
NK		 7736 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7737 continue;
eb3dc897 7738
6836d239
NK		 7739 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
7740 update_type = UPDATE_TYPE_FULL;
7741 goto cleanup;
7742 }
7743
c744e974
NK		 7744 if (crtc != new_plane_crtc)
7745 continue;
7746
f843b308 7747 updates[num_plane].surface = new_dm_plane_state->dc_state;
c744e974
NK		 7748
7749 if (new_crtc_state->mode_changed) {
c744e974
NK		 7750 stream_update.dst = new_dm_crtc_state->stream->dst;
7751 stream_update.src = new_dm_crtc_state->stream->src;
7752 }
7753
7754 if (new_crtc_state->color_mgmt_changed) {
7755 updates[num_plane].gamma =
7756 new_dm_plane_state->dc_state->gamma_correction;
7757 updates[num_plane].in_transfer_func =
7758 new_dm_plane_state->dc_state->in_transfer_func;
7759 stream_update.gamut_remap =
7760 &new_dm_crtc_state->stream->gamut_remap_matrix;
cf020d49
NK		 7761 stream_update.output_csc_transform =
7762 &new_dm_crtc_state->stream->csc_color_matrix;
c744e974
NK		 7763 stream_update.out_transfer_func =
7764 new_dm_crtc_state->stream->out_transfer_func;
a87fa993
BL		 7765 }
7766
004b3938
NK		 7767 ret = fill_dc_scaling_info(new_plane_state,
7768 &scaling_info);
7769 if (ret)
7770 goto cleanup;
7771
7772 updates[num_plane].scaling_info = &scaling_info;
7773
2cc450ce
NK		 7774 if (amdgpu_fb) {
7775 ret = get_fb_info(amdgpu_fb, &tiling_flags);
7776 if (ret)
7777 goto cleanup;
7778
7779 memset(&flip_addr, 0, sizeof(flip_addr));
7780
7781 ret = fill_dc_plane_info_and_addr(
7782 dm->adev, new_plane_state, tiling_flags,
7783 &plane_info,
7784 &flip_addr.address);
7785 if (ret)
7786 goto cleanup;
7787
7788 updates[num_plane].plane_info = &plane_info;
7789 updates[num_plane].flip_addr = &flip_addr;
7790 }
7791
c744e974
NK		 7792 num_plane++;
7793 }
7794
7795 if (num_plane == 0)
7796 continue;
7797
7798 ret = dm_atomic_get_state(state, &dm_state);
7799 if (ret)
7800 goto cleanup;
7801
7802 old_dm_state = dm_atomic_get_old_state(state);
7803 if (!old_dm_state) {
7804 ret = -EINVAL;
7805 goto cleanup;
7806 }
7807
7808 status = dc_stream_get_status_from_state(old_dm_state->context,
7809 new_dm_crtc_state->stream);
b6e881c9 7810 stream_update.stream = new_dm_crtc_state->stream;
f843b308
NK		 7811 /*
7812 * TODO: DC modifies the surface during this call so we need
7813 * to lock here - find a way to do this without locking.
7814 */
7815 mutex_lock(&dm->dc_lock);
c744e974
NK		 7816 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
7817 &stream_update, status);
f843b308 7818 mutex_unlock(&dm->dc_lock);
c744e974
NK		 7819
7820 if (update_type > UPDATE_TYPE_MED) {
a87fa993 7821 update_type = UPDATE_TYPE_FULL;
eb3dc897 7822 goto cleanup;
a87fa993
BL		 7823 }
7824 }
7825
eb3dc897 7826cleanup:
a87fa993 7827 kfree(updates);
a87fa993 7828
eb3dc897
NK		 7829 *out_type = update_type;
7830 return ret;
a87fa993 7831}
62f55537 7832
b8592b48
LL		 7833/**
7834 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
7835 * @dev: The DRM device
7836 * @state: The atomic state to commit
7837 *
7838 * Validate that the given atomic state is programmable by DC into hardware.
7839 * This involves constructing a &struct dc_state reflecting the new hardware
7840 * state we wish to commit, then querying DC to see if it is programmable. It's
7841 * important not to modify the existing DC state. Otherwise, atomic_check
7842 * may unexpectedly commit hardware changes.
7843 *
7844 * When validating the DC state, it's important that the right locks are
7845 * acquired. For full updates case which removes/adds/updates streams on one
7846 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
7847 * that any such full update commit will wait for completion of any outstanding
7848 * flip using DRMs synchronization events. See
7849 * dm_determine_update_type_for_commit()
7850 *
7851 * Note that DM adds the affected connectors for all CRTCs in state, when that
7852 * might not seem necessary. This is because DC stream creation requires the
7853 * DC sink, which is tied to the DRM connector state. Cleaning this up should
7854 * be possible but non-trivial - a possible TODO item.
7855 *
7856 * Return: -Error code if validation failed.
7857 */
7578ecda
AD		 7858static int amdgpu_dm_atomic_check(struct drm_device *dev,
7859 struct drm_atomic_state *state)
62f55537 7860{
62f55537 7861 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 7862 struct dm_atomic_state *dm_state = NULL;
62f55537 7863 struct dc *dc = adev->dm.dc;
62f55537 7864 struct drm_connector *connector;
c2cea706 7865 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 7866 struct drm_crtc *crtc;
fc9e9920 7867 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 7868 struct drm_plane *plane;
7869 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 7870 enum surface_update_type update_type = UPDATE_TYPE_FAST;
7871 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
7872
1e88ad0a 7873 int ret, i;
e7b07cee 7874
62f55537
AG		 7875 /*
7876 * This bool will be set for true for any modeset/reset
7877 * or plane update which implies non fast surface update.
7878 */
7879 bool lock_and_validation_needed = false;
7880
7881 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 7882 if (ret)
7883 goto fail;
62f55537 7884
1e88ad0a
S		 7885 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7886 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 7887 !new_crtc_state->color_mgmt_changed &&
a93587b3 7888 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 7889 continue;
7bef1af3 7890
1e88ad0a
S		 7891 if (!new_crtc_state->enable)
7892 continue;
fc9e9920 7893
1e88ad0a
S		 7894 ret = drm_atomic_add_affected_connectors(state, crtc);
7895 if (ret)
7896 return ret;
fc9e9920 7897
1e88ad0a
S		 7898 ret = drm_atomic_add_affected_planes(state, crtc);
7899 if (ret)
7900 goto fail;
e7b07cee
HW		 7901 }
7902
2d9e6431
NK		 7903 /*
7904 * Add all primary and overlay planes on the CRTC to the state
7905 * whenever a plane is enabled to maintain correct z-ordering
7906 * and to enable fast surface updates.
7907 */
7908 drm_for_each_crtc(crtc, dev) {
7909 bool modified = false;
7910
7911 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7912 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7913 continue;
7914
7915 if (new_plane_state->crtc == crtc ||
7916 old_plane_state->crtc == crtc) {
7917 modified = true;
7918 break;
7919 }
7920 }
7921
7922 if (!modified)
7923 continue;
7924
7925 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
7926 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7927 continue;
7928
7929 new_plane_state =
7930 drm_atomic_get_plane_state(state, plane);
7931
7932 if (IS_ERR(new_plane_state)) {
7933 ret = PTR_ERR(new_plane_state);
7934 goto fail;
7935 }
7936 }
7937 }
7938
62f55537 7939 /* Remove exiting planes if they are modified */
9e869063
LL		 7940 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7941 ret = dm_update_plane_state(dc, state, plane,
7942 old_plane_state,
7943 new_plane_state,
7944 false,
7945 &lock_and_validation_needed);
7946 if (ret)
7947 goto fail;
62f55537
AG		 7948 }
7949
7950 /* Disable all crtcs which require disable */
4b9674e5
LL		 7951 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7952 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7953 old_crtc_state,
7954 new_crtc_state,
7955 false,
7956 &lock_and_validation_needed);
7957 if (ret)
7958 goto fail;
62f55537
AG		 7959 }
7960
7961 /* Enable all crtcs which require enable */
4b9674e5
LL		 7962 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7963 ret = dm_update_crtc_state(&adev->dm, state, crtc,
7964 old_crtc_state,
7965 new_crtc_state,
7966 true,
7967 &lock_and_validation_needed);
7968 if (ret)
7969 goto fail;
62f55537
AG		 7970 }
7971
7972 /* Add new/modified planes */
9e869063
LL		 7973 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
7974 ret = dm_update_plane_state(dc, state, plane,
7975 old_plane_state,
7976 new_plane_state,
7977 true,
7978 &lock_and_validation_needed);
7979 if (ret)
7980 goto fail;
62f55537
AG		 7981 }
7982
b349f76e
ES		 7983 /* Run this here since we want to validate the streams we created */
7984 ret = drm_atomic_helper_check_planes(dev, state);
7985 if (ret)
7986 goto fail;
62f55537 7987
3261e013
ML		 7988 /* Perform validation of MST topology in the state*/
7989 ret = drm_dp_mst_atomic_check(state);
7990 if (ret)
7991 goto fail;
7992
43d10d30
NK		 7993 if (state->legacy_cursor_update) {
7994 /*
7995 * This is a fast cursor update coming from the plane update
7996 * helper, check if it can be done asynchronously for better
7997 * performance.
7998 */
7999 state->async_update =
8000 !drm_atomic_helper_async_check(dev, state);
8001
8002 /*
8003 * Skip the remaining global validation if this is an async
8004 * update. Cursor updates can be done without affecting
8005 * state or bandwidth calcs and this avoids the performance
8006 * penalty of locking the private state object and
8007 * allocating a new dc_state.
8008 */
8009 if (state->async_update)
8010 return 0;
8011 }
8012
ebdd27e1 8013 /* Check scaling and underscan changes*/
1f6010a9 8014 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 8015 * new stream into context w\o causing full reset. Need to
8016 * decide how to handle.
8017 */
c2cea706 8018 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 8019 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8020 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8021 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 8022
8023 /* Skip any modesets/resets */
0bc9706d
LSL		 8024 if (!acrtc || drm_atomic_crtc_needs_modeset(
8025 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 8026 continue;
8027
b830ebc9 8028 /* Skip any thing not scale or underscan changes */
54d76575 8029 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 8030 continue;
8031
a87fa993 8032 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 8033 lock_and_validation_needed = true;
8034 }
8035
f843b308 8036 ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
eb3dc897
NK		 8037 if (ret)
8038 goto fail;
a87fa993
BL		 8039
8040 if (overall_update_type < update_type)
8041 overall_update_type = update_type;
8042
8043 /*
8044 * lock_and_validation_needed was an old way to determine if we need to set
8045 * the global lock. Leaving it in to check if we broke any corner cases
8046 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
8047 * lock_and_validation_needed false = UPDATE_TYPE_FAST
8048 */
8049 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
8050 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
e7b07cee 8051
a87fa993 8052 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 8053 ret = dm_atomic_get_state(state, &dm_state);
8054 if (ret)
8055 goto fail;
e7b07cee
HW		 8056
8057 ret = do_aquire_global_lock(dev, state);
8058 if (ret)
8059 goto fail;
1dc90497 8060
8c20a1ed
DF		 8061 if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
8062 goto fail;
8063
afcd526b 8064 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
e7b07cee
HW		 8065 ret = -EINVAL;
8066 goto fail;
8067 }
bd200d19 8068 } else {
674e78ac 8069 /*
bd200d19
NK		 8070 * The commit is a fast update. Fast updates shouldn't change
8071 * the DC context, affect global validation, and can have their
8072 * commit work done in parallel with other commits not touching
8073 * the same resource. If we have a new DC context as part of
8074 * the DM atomic state from validation we need to free it and
8075 * retain the existing one instead.
674e78ac 8076 */
bd200d19
NK		 8077 struct dm_atomic_state *new_dm_state, *old_dm_state;
8078
8079 new_dm_state = dm_atomic_get_new_state(state);
8080 old_dm_state = dm_atomic_get_old_state(state);
8081
8082 if (new_dm_state && old_dm_state) {
8083 if (new_dm_state->context)
8084 dc_release_state(new_dm_state->context);
8085
8086 new_dm_state->context = old_dm_state->context;
8087
8088 if (old_dm_state->context)
8089 dc_retain_state(old_dm_state->context);
8090 }
e7b07cee
HW		 8091 }
8092
caff0e66
NK		 8093 /* Store the overall update type for use later in atomic check. */
8094 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
8095 struct dm_crtc_state *dm_new_crtc_state =
8096 to_dm_crtc_state(new_crtc_state);
8097
8098 dm_new_crtc_state->update_type = (int)overall_update_type;
e7b07cee
HW		 8099 }
8100
8101 /* Must be success */
8102 WARN_ON(ret);
8103 return ret;
8104
8105fail:
8106 if (ret == -EDEADLK)
01e28f9c 8107 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 8108 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 8109 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 8110 else
01e28f9c 8111 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 8112
8113 return ret;
8114}
8115
3ee6b26b
AD		 8116static bool is_dp_capable_without_timing_msa(struct dc *dc,
8117 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 8118{
8119 uint8_t dpcd_data;
8120 bool capable = false;
8121
c84dec2f 8122 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 8123 dm_helpers_dp_read_dpcd(
8124 NULL,
c84dec2f 8125 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 8126 DP_DOWN_STREAM_PORT_COUNT,
8127 &dpcd_data,
8128 sizeof(dpcd_data))) {
8129 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
8130 }
8131
8132 return capable;
8133}
98e6436d
AK		 8134void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
8135 struct edid *edid)
e7b07cee
HW		 8136{
8137 int i;
e7b07cee
HW		 8138 bool edid_check_required;
8139 struct detailed_timing *timing;
8140 struct detailed_non_pixel *data;
8141 struct detailed_data_monitor_range *range;
c84dec2f
HW		 8142 struct amdgpu_dm_connector *amdgpu_dm_connector =
8143 to_amdgpu_dm_connector(connector);
bb47de73 8144 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 8145
8146 struct drm_device *dev = connector->dev;
8147 struct amdgpu_device *adev = dev->dev_private;
bb47de73 8148 bool freesync_capable = false;
b830ebc9 8149
8218d7f1
HW		 8150 if (!connector->state) {
8151 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 8152 goto update;
8218d7f1
HW		 8153 }
8154
98e6436d
AK		 8155 if (!edid) {
8156 dm_con_state = to_dm_connector_state(connector->state);
8157
8158 amdgpu_dm_connector->min_vfreq = 0;
8159 amdgpu_dm_connector->max_vfreq = 0;
8160 amdgpu_dm_connector->pixel_clock_mhz = 0;
8161
bb47de73 8162 goto update;
98e6436d
AK		 8163 }
8164
8218d7f1
HW		 8165 dm_con_state = to_dm_connector_state(connector->state);
8166
e7b07cee 8167 edid_check_required = false;
c84dec2f 8168 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 8169 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 8170 goto update;
e7b07cee
HW		 8171 }
8172 if (!adev->dm.freesync_module)
bb47de73 8173 goto update;
e7b07cee
HW		 8174 /*
8175 * if edid non zero restrict freesync only for dp and edp
8176 */
8177 if (edid) {
c84dec2f
HW		 8178 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
8179 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 8180 edid_check_required = is_dp_capable_without_timing_msa(
8181 adev->dm.dc,
c84dec2f 8182 amdgpu_dm_connector);
e7b07cee
HW		 8183 }
8184 }
e7b07cee
HW		 8185 if (edid_check_required == true && (edid->version > 1 ||
8186 (edid->version == 1 && edid->revision > 1))) {
8187 for (i = 0; i < 4; i++) {
8188
8189 timing = &edid->detailed_timings[i];
8190 data = &timing->data.other_data;
8191 range = &data->data.range;
8192 /*
8193 * Check if monitor has continuous frequency mode
8194 */
8195 if (data->type != EDID_DETAIL_MONITOR_RANGE)
8196 continue;
8197 /*
8198 * Check for flag range limits only. If flag == 1 then
8199 * no additional timing information provided.
8200 * Default GTF, GTF Secondary curve and CVT are not
8201 * supported
8202 */
8203 if (range->flags != 1)
8204 continue;
8205
c84dec2f
HW		 8206 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
8207 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
8208 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 8209 range->pixel_clock_mhz * 10;
8210 break;
8211 }
8212
c84dec2f 8213 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 8214 amdgpu_dm_connector->min_vfreq > 10) {
8215
bb47de73 8216 freesync_capable = true;
e7b07cee
HW		 8217 }
8218 }
bb47de73
NK		 8219
8220update:
8221 if (dm_con_state)
8222 dm_con_state->freesync_capable = freesync_capable;
8223
8224 if (connector->vrr_capable_property)
8225 drm_connector_set_vrr_capable_property(connector,
8226 freesync_capable);
e7b07cee
HW		 8227}
8228
8c322309
RL		 8229static void amdgpu_dm_set_psr_caps(struct dc_link *link)
8230{
8231 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
8232
8233 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
8234 return;
8235 if (link->type == dc_connection_none)
8236 return;
8237 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
8238 dpcd_data, sizeof(dpcd_data))) {
8239 link->psr_feature_enabled = dpcd_data[0] ? true:false;
8240 DRM_INFO("PSR support:%d\n", link->psr_feature_enabled);
8241 }
8242}
8243
8244/*
8245 * amdgpu_dm_link_setup_psr() - configure psr link
8246 * @stream: stream state
8247 *
8248 * Return: true if success
8249 */
8250static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
8251{
8252 struct dc_link *link = NULL;
8253 struct psr_config psr_config = {0};
8254 struct psr_context psr_context = {0};
8255 struct dc *dc = NULL;
8256 bool ret = false;
8257
8258 if (stream == NULL)
8259 return false;
8260
8261 link = stream->link;
8262 dc = link->ctx->dc;
8263
8264 psr_config.psr_version = dc->res_pool->dmcu->dmcu_version.psr_version;
8265
8266 if (psr_config.psr_version > 0) {
8267 psr_config.psr_exit_link_training_required = 0x1;
8268 psr_config.psr_frame_capture_indication_req = 0;
8269 psr_config.psr_rfb_setup_time = 0x37;
8270 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
8271 psr_config.allow_smu_optimizations = 0x0;
8272
8273 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
8274
8275 }
8276 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_feature_enabled);
8277
8278 return ret;
8279}
8280
8281/*
8282 * amdgpu_dm_psr_enable() - enable psr f/w
8283 * @stream: stream state
8284 *
8285 * Return: true if success
8286 */
8287bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
8288{
8289 struct dc_link *link = stream->link;
8290 struct dc_static_screen_events triggers = {0};
8291
8292 DRM_DEBUG_DRIVER("Enabling psr...\n");
8293
8294 triggers.cursor_update = true;
8295 triggers.overlay_update = true;
8296 triggers.surface_update = true;
8297
8298 dc_stream_set_static_screen_events(link->ctx->dc,
8299 &stream, 1,
8300 &triggers);
8301
8302 return dc_link_set_psr_allow_active(link, true, false);
8303}
8304
8305/*
8306 * amdgpu_dm_psr_disable() - disable psr f/w
8307 * @stream: stream state
8308 *
8309 * Return: true if success
8310 */
8311static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
8312{
8313
8314 DRM_DEBUG_DRIVER("Disabling psr...\n");
8315
8316 return dc_link_set_psr_allow_active(stream->link, false, true);
8317}
Linux 6.x block layer and io_uring tree(s)