Commit | Line | Data |
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4562236b HW |
1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: AMD | |
23 | * | |
24 | */ | |
25 | ||
26 | #include "dm_services_types.h" | |
27 | #include "dc.h" | |
1dc90497 | 28 | #include "dc/inc/core_types.h" |
4562236b HW |
29 | |
30 | #include "vid.h" | |
31 | #include "amdgpu.h" | |
a49dcb88 | 32 | #include "amdgpu_display.h" |
a94d5569 | 33 | #include "amdgpu_ucode.h" |
4562236b HW |
34 | #include "atom.h" |
35 | #include "amdgpu_dm.h" | |
e7b07cee | 36 | #include "amdgpu_pm.h" |
4562236b HW |
37 | |
38 | #include "amd_shared.h" | |
39 | #include "amdgpu_dm_irq.h" | |
40 | #include "dm_helpers.h" | |
e7b07cee HW |
41 | #include "dm_services_types.h" |
42 | #include "amdgpu_dm_mst_types.h" | |
dc38fd9d DF |
43 | #if defined(CONFIG_DEBUG_FS) |
44 | #include "amdgpu_dm_debugfs.h" | |
45 | #endif | |
4562236b HW |
46 | |
47 | #include "ivsrcid/ivsrcid_vislands30.h" | |
48 | ||
49 | #include <linux/module.h> | |
50 | #include <linux/moduleparam.h> | |
51 | #include <linux/version.h> | |
e7b07cee | 52 | #include <linux/types.h> |
97028037 | 53 | #include <linux/pm_runtime.h> |
a94d5569 | 54 | #include <linux/firmware.h> |
4562236b | 55 | |
e7b07cee | 56 | #include <drm/drmP.h> |
4562236b HW |
57 | #include <drm/drm_atomic.h> |
58 | #include <drm/drm_atomic_helper.h> | |
59 | #include <drm/drm_dp_mst_helper.h> | |
e7b07cee HW |
60 | #include <drm/drm_fb_helper.h> |
61 | #include <drm/drm_edid.h> | |
4562236b | 62 | |
ff5ef992 AD |
63 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
64 | #include "ivsrcid/irqsrcs_dcn_1_0.h" | |
65 | ||
ad941f7a FX |
66 | #include "dcn/dcn_1_0_offset.h" |
67 | #include "dcn/dcn_1_0_sh_mask.h" | |
407e7517 HZ |
68 | #include "soc15_hw_ip.h" |
69 | #include "vega10_ip_offset.h" | |
ff5ef992 AD |
70 | |
71 | #include "soc15_common.h" | |
72 | #endif | |
73 | ||
e7b07cee HW |
74 | #include "modules/inc/mod_freesync.h" |
75 | ||
a94d5569 DF |
76 | #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" |
77 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); | |
e7b07cee | 78 | |
7578ecda AD |
79 | /* basic init/fini API */ |
80 | static int amdgpu_dm_init(struct amdgpu_device *adev); | |
81 | static void amdgpu_dm_fini(struct amdgpu_device *adev); | |
82 | ||
1f6010a9 DF |
83 | /* |
84 | * initializes drm_device display related structures, based on the information | |
7578ecda AD |
85 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
86 | * drm_encoder, drm_mode_config | |
87 | * | |
88 | * Returns 0 on success | |
89 | */ | |
90 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); | |
91 | /* removes and deallocates the drm structures, created by the above function */ | |
92 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); | |
93 | ||
94 | static void | |
95 | amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); | |
96 | ||
97 | static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, | |
98 | struct amdgpu_plane *aplane, | |
99 | unsigned long possible_crtcs); | |
100 | static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, | |
101 | struct drm_plane *plane, | |
102 | uint32_t link_index); | |
103 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, | |
104 | struct amdgpu_dm_connector *amdgpu_dm_connector, | |
105 | uint32_t link_index, | |
106 | struct amdgpu_encoder *amdgpu_encoder); | |
107 | static int amdgpu_dm_encoder_init(struct drm_device *dev, | |
108 | struct amdgpu_encoder *aencoder, | |
109 | uint32_t link_index); | |
110 | ||
111 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); | |
112 | ||
113 | static int amdgpu_dm_atomic_commit(struct drm_device *dev, | |
114 | struct drm_atomic_state *state, | |
115 | bool nonblock); | |
116 | ||
117 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); | |
118 | ||
119 | static int amdgpu_dm_atomic_check(struct drm_device *dev, | |
120 | struct drm_atomic_state *state); | |
121 | ||
122 | ||
123 | ||
e7b07cee | 124 | |
e04a6123 | 125 | static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { |
d4e13b0d AD |
126 | DRM_PLANE_TYPE_PRIMARY, |
127 | DRM_PLANE_TYPE_PRIMARY, | |
128 | DRM_PLANE_TYPE_PRIMARY, | |
129 | DRM_PLANE_TYPE_PRIMARY, | |
130 | DRM_PLANE_TYPE_PRIMARY, | |
131 | DRM_PLANE_TYPE_PRIMARY, | |
132 | }; | |
133 | ||
e04a6123 | 134 | static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { |
d4e13b0d AD |
135 | DRM_PLANE_TYPE_PRIMARY, |
136 | DRM_PLANE_TYPE_PRIMARY, | |
137 | DRM_PLANE_TYPE_PRIMARY, | |
138 | DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ | |
139 | }; | |
140 | ||
e04a6123 | 141 | static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { |
d4e13b0d AD |
142 | DRM_PLANE_TYPE_PRIMARY, |
143 | DRM_PLANE_TYPE_PRIMARY, | |
144 | DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ | |
145 | }; | |
146 | ||
4562236b HW |
147 | /* |
148 | * dm_vblank_get_counter | |
149 | * | |
150 | * @brief | |
151 | * Get counter for number of vertical blanks | |
152 | * | |
153 | * @param | |
154 | * struct amdgpu_device *adev - [in] desired amdgpu device | |
155 | * int disp_idx - [in] which CRTC to get the counter from | |
156 | * | |
157 | * @return | |
158 | * Counter for vertical blanks | |
159 | */ | |
160 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) | |
161 | { | |
162 | if (crtc >= adev->mode_info.num_crtc) | |
163 | return 0; | |
164 | else { | |
165 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
da5c47f6 AG |
166 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state( |
167 | acrtc->base.state); | |
4562236b | 168 | |
da5c47f6 AG |
169 | |
170 | if (acrtc_state->stream == NULL) { | |
0971c40e HW |
171 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
172 | crtc); | |
4562236b HW |
173 | return 0; |
174 | } | |
175 | ||
da5c47f6 | 176 | return dc_stream_get_vblank_counter(acrtc_state->stream); |
4562236b HW |
177 | } |
178 | } | |
179 | ||
180 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, | |
3ee6b26b | 181 | u32 *vbl, u32 *position) |
4562236b | 182 | { |
81c50963 ST |
183 | uint32_t v_blank_start, v_blank_end, h_position, v_position; |
184 | ||
4562236b HW |
185 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
186 | return -EINVAL; | |
187 | else { | |
188 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; | |
da5c47f6 AG |
189 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state( |
190 | acrtc->base.state); | |
4562236b | 191 | |
da5c47f6 | 192 | if (acrtc_state->stream == NULL) { |
0971c40e HW |
193 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", |
194 | crtc); | |
4562236b HW |
195 | return 0; |
196 | } | |
197 | ||
81c50963 ST |
198 | /* |
199 | * TODO rework base driver to use values directly. | |
200 | * for now parse it back into reg-format | |
201 | */ | |
da5c47f6 | 202 | dc_stream_get_scanoutpos(acrtc_state->stream, |
81c50963 ST |
203 | &v_blank_start, |
204 | &v_blank_end, | |
205 | &h_position, | |
206 | &v_position); | |
207 | ||
e806208d AG |
208 | *position = v_position | (h_position << 16); |
209 | *vbl = v_blank_start | (v_blank_end << 16); | |
4562236b HW |
210 | } |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
215 | static bool dm_is_idle(void *handle) | |
216 | { | |
217 | /* XXX todo */ | |
218 | return true; | |
219 | } | |
220 | ||
221 | static int dm_wait_for_idle(void *handle) | |
222 | { | |
223 | /* XXX todo */ | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static bool dm_check_soft_reset(void *handle) | |
228 | { | |
229 | return false; | |
230 | } | |
231 | ||
232 | static int dm_soft_reset(void *handle) | |
233 | { | |
234 | /* XXX todo */ | |
235 | return 0; | |
236 | } | |
237 | ||
3ee6b26b AD |
238 | static struct amdgpu_crtc * |
239 | get_crtc_by_otg_inst(struct amdgpu_device *adev, | |
240 | int otg_inst) | |
4562236b HW |
241 | { |
242 | struct drm_device *dev = adev->ddev; | |
243 | struct drm_crtc *crtc; | |
244 | struct amdgpu_crtc *amdgpu_crtc; | |
245 | ||
4562236b HW |
246 | if (otg_inst == -1) { |
247 | WARN_ON(1); | |
248 | return adev->mode_info.crtcs[0]; | |
249 | } | |
250 | ||
251 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
252 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
253 | ||
254 | if (amdgpu_crtc->otg_inst == otg_inst) | |
255 | return amdgpu_crtc; | |
256 | } | |
257 | ||
258 | return NULL; | |
259 | } | |
260 | ||
261 | static void dm_pflip_high_irq(void *interrupt_params) | |
262 | { | |
4562236b HW |
263 | struct amdgpu_crtc *amdgpu_crtc; |
264 | struct common_irq_params *irq_params = interrupt_params; | |
265 | struct amdgpu_device *adev = irq_params->adev; | |
266 | unsigned long flags; | |
267 | ||
268 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); | |
269 | ||
270 | /* IRQ could occur when in initial stage */ | |
1f6010a9 | 271 | /* TODO work and BO cleanup */ |
4562236b HW |
272 | if (amdgpu_crtc == NULL) { |
273 | DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); | |
274 | return; | |
275 | } | |
276 | ||
277 | spin_lock_irqsave(&adev->ddev->event_lock, flags); | |
4562236b HW |
278 | |
279 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ | |
280 | DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", | |
281 | amdgpu_crtc->pflip_status, | |
282 | AMDGPU_FLIP_SUBMITTED, | |
283 | amdgpu_crtc->crtc_id, | |
284 | amdgpu_crtc); | |
285 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
286 | return; | |
287 | } | |
288 | ||
4562236b | 289 | |
1f6010a9 | 290 | /* wake up userspace */ |
1159898a | 291 | if (amdgpu_crtc->event) { |
1f6010a9 | 292 | /* Update to correct count(s) if racing with vblank irq */ |
753c66c9 MK |
293 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); |
294 | ||
54f5499a | 295 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); |
1159898a | 296 | |
54f5499a AG |
297 | /* page flip completed. clean up */ |
298 | amdgpu_crtc->event = NULL; | |
1159898a | 299 | |
54f5499a AG |
300 | } else |
301 | WARN_ON(1); | |
4562236b | 302 | |
54f5499a | 303 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
4562236b HW |
304 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); |
305 | ||
54f5499a AG |
306 | DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n", |
307 | __func__, amdgpu_crtc->crtc_id, amdgpu_crtc); | |
4562236b HW |
308 | |
309 | drm_crtc_vblank_put(&amdgpu_crtc->base); | |
4562236b HW |
310 | } |
311 | ||
312 | static void dm_crtc_high_irq(void *interrupt_params) | |
313 | { | |
314 | struct common_irq_params *irq_params = interrupt_params; | |
315 | struct amdgpu_device *adev = irq_params->adev; | |
4562236b HW |
316 | struct amdgpu_crtc *acrtc; |
317 | ||
b57de80a | 318 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
4562236b | 319 | |
e5d0170e LSL |
320 | if (acrtc) { |
321 | drm_crtc_handle_vblank(&acrtc->base); | |
322 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); | |
323 | } | |
4562236b HW |
324 | } |
325 | ||
326 | static int dm_set_clockgating_state(void *handle, | |
327 | enum amd_clockgating_state state) | |
328 | { | |
329 | return 0; | |
330 | } | |
331 | ||
332 | static int dm_set_powergating_state(void *handle, | |
333 | enum amd_powergating_state state) | |
334 | { | |
335 | return 0; | |
336 | } | |
337 | ||
338 | /* Prototypes of private functions */ | |
339 | static int dm_early_init(void* handle); | |
340 | ||
a32e24b4 | 341 | /* Allocate memory for FBC compressed data */ |
3e332d3a | 342 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
a32e24b4 | 343 | { |
3e332d3a RL |
344 | struct drm_device *dev = connector->dev; |
345 | struct amdgpu_device *adev = dev->dev_private; | |
a32e24b4 | 346 | struct dm_comressor_info *compressor = &adev->dm.compressor; |
3e332d3a RL |
347 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); |
348 | struct drm_display_mode *mode; | |
42e67c3b RL |
349 | unsigned long max_size = 0; |
350 | ||
351 | if (adev->dm.dc->fbc_compressor == NULL) | |
352 | return; | |
a32e24b4 | 353 | |
3e332d3a | 354 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
42e67c3b RL |
355 | return; |
356 | ||
3e332d3a RL |
357 | if (compressor->bo_ptr) |
358 | return; | |
42e67c3b | 359 | |
42e67c3b | 360 | |
3e332d3a RL |
361 | list_for_each_entry(mode, &connector->modes, head) { |
362 | if (max_size < mode->htotal * mode->vtotal) | |
363 | max_size = mode->htotal * mode->vtotal; | |
42e67c3b RL |
364 | } |
365 | ||
366 | if (max_size) { | |
367 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, | |
0e5916ff | 368 | AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, |
42e67c3b | 369 | &compressor->gpu_addr, &compressor->cpu_addr); |
a32e24b4 RL |
370 | |
371 | if (r) | |
42e67c3b RL |
372 | DRM_ERROR("DM: Failed to initialize FBC\n"); |
373 | else { | |
374 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; | |
375 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4); | |
376 | } | |
377 | ||
a32e24b4 RL |
378 | } |
379 | ||
380 | } | |
a32e24b4 | 381 | |
1f6010a9 DF |
382 | /* |
383 | * Init display KMS | |
4562236b HW |
384 | * |
385 | * Returns 0 on success | |
386 | */ | |
7578ecda | 387 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
4562236b HW |
388 | { |
389 | struct dc_init_data init_data; | |
390 | adev->dm.ddev = adev->ddev; | |
391 | adev->dm.adev = adev; | |
392 | ||
4562236b HW |
393 | /* Zero all the fields */ |
394 | memset(&init_data, 0, sizeof(init_data)); | |
395 | ||
4562236b HW |
396 | if(amdgpu_dm_irq_init(adev)) { |
397 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); | |
398 | goto error; | |
399 | } | |
400 | ||
401 | init_data.asic_id.chip_family = adev->family; | |
402 | ||
403 | init_data.asic_id.pci_revision_id = adev->rev_id; | |
404 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; | |
405 | ||
770d13b1 | 406 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
4562236b HW |
407 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
408 | init_data.asic_id.atombios_base_address = | |
409 | adev->mode_info.atom_context->bios; | |
410 | ||
411 | init_data.driver = adev; | |
412 | ||
413 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); | |
414 | ||
415 | if (!adev->dm.cgs_device) { | |
416 | DRM_ERROR("amdgpu: failed to create cgs device.\n"); | |
417 | goto error; | |
418 | } | |
419 | ||
420 | init_data.cgs_device = adev->dm.cgs_device; | |
421 | ||
4562236b HW |
422 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
423 | ||
6e227308 HW |
424 | /* |
425 | * TODO debug why this doesn't work on Raven | |
426 | */ | |
427 | if (adev->flags & AMD_IS_APU && | |
428 | adev->asic_type >= CHIP_CARRIZO && | |
429 | adev->asic_type < CHIP_RAVEN) | |
430 | init_data.flags.gpu_vm_support = true; | |
431 | ||
4562236b HW |
432 | /* Display Core create. */ |
433 | adev->dm.dc = dc_create(&init_data); | |
434 | ||
423788c7 | 435 | if (adev->dm.dc) { |
76121231 | 436 | DRM_INFO("Display Core initialized with v%s!\n", DC_VER); |
423788c7 | 437 | } else { |
76121231 | 438 | DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); |
423788c7 ES |
439 | goto error; |
440 | } | |
4562236b | 441 | |
4562236b HW |
442 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
443 | if (!adev->dm.freesync_module) { | |
444 | DRM_ERROR( | |
445 | "amdgpu: failed to initialize freesync_module.\n"); | |
446 | } else | |
f1ad2f5e | 447 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", |
4562236b HW |
448 | adev->dm.freesync_module); |
449 | ||
e277adc5 LSL |
450 | amdgpu_dm_init_color_mod(); |
451 | ||
4562236b HW |
452 | if (amdgpu_dm_initialize_drm_device(adev)) { |
453 | DRM_ERROR( | |
454 | "amdgpu: failed to initialize sw for display support.\n"); | |
455 | goto error; | |
456 | } | |
457 | ||
458 | /* Update the actual used number of crtc */ | |
459 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; | |
460 | ||
461 | /* TODO: Add_display_info? */ | |
462 | ||
463 | /* TODO use dynamic cursor width */ | |
ce75805e AG |
464 | adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
465 | adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; | |
4562236b HW |
466 | |
467 | if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { | |
468 | DRM_ERROR( | |
469 | "amdgpu: failed to initialize sw for display support.\n"); | |
470 | goto error; | |
471 | } | |
472 | ||
e498eb71 NK |
473 | #if defined(CONFIG_DEBUG_FS) |
474 | if (dtn_debugfs_init(adev)) | |
475 | DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); | |
476 | #endif | |
477 | ||
f1ad2f5e | 478 | DRM_DEBUG_DRIVER("KMS initialized.\n"); |
4562236b HW |
479 | |
480 | return 0; | |
481 | error: | |
482 | amdgpu_dm_fini(adev); | |
483 | ||
59d0f396 | 484 | return -EINVAL; |
4562236b HW |
485 | } |
486 | ||
7578ecda | 487 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
4562236b HW |
488 | { |
489 | amdgpu_dm_destroy_drm_device(&adev->dm); | |
490 | /* | |
491 | * TODO: pageflip, vlank interrupt | |
492 | * | |
493 | * amdgpu_dm_irq_fini(adev); | |
494 | */ | |
495 | ||
496 | if (adev->dm.cgs_device) { | |
497 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); | |
498 | adev->dm.cgs_device = NULL; | |
499 | } | |
500 | if (adev->dm.freesync_module) { | |
501 | mod_freesync_destroy(adev->dm.freesync_module); | |
502 | adev->dm.freesync_module = NULL; | |
503 | } | |
504 | /* DC Destroy TODO: Replace destroy DAL */ | |
21de3396 | 505 | if (adev->dm.dc) |
4562236b | 506 | dc_destroy(&adev->dm.dc); |
4562236b HW |
507 | return; |
508 | } | |
509 | ||
a94d5569 | 510 | static int load_dmcu_fw(struct amdgpu_device *adev) |
4562236b | 511 | { |
a94d5569 DF |
512 | const char *fw_name_dmcu; |
513 | int r; | |
514 | const struct dmcu_firmware_header_v1_0 *hdr; | |
515 | ||
516 | switch(adev->asic_type) { | |
517 | case CHIP_BONAIRE: | |
518 | case CHIP_HAWAII: | |
519 | case CHIP_KAVERI: | |
520 | case CHIP_KABINI: | |
521 | case CHIP_MULLINS: | |
522 | case CHIP_TONGA: | |
523 | case CHIP_FIJI: | |
524 | case CHIP_CARRIZO: | |
525 | case CHIP_STONEY: | |
526 | case CHIP_POLARIS11: | |
527 | case CHIP_POLARIS10: | |
528 | case CHIP_POLARIS12: | |
529 | case CHIP_VEGAM: | |
530 | case CHIP_VEGA10: | |
531 | case CHIP_VEGA12: | |
532 | case CHIP_VEGA20: | |
533 | return 0; | |
534 | case CHIP_RAVEN: | |
535 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU; | |
536 | break; | |
537 | default: | |
538 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); | |
59d0f396 | 539 | return -EINVAL; |
a94d5569 DF |
540 | } |
541 | ||
542 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { | |
543 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); | |
544 | return 0; | |
545 | } | |
546 | ||
547 | r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); | |
548 | if (r == -ENOENT) { | |
549 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ | |
550 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); | |
551 | adev->dm.fw_dmcu = NULL; | |
552 | return 0; | |
553 | } | |
554 | if (r) { | |
555 | dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n", | |
556 | fw_name_dmcu); | |
557 | return r; | |
558 | } | |
559 | ||
560 | r = amdgpu_ucode_validate(adev->dm.fw_dmcu); | |
561 | if (r) { | |
562 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", | |
563 | fw_name_dmcu); | |
564 | release_firmware(adev->dm.fw_dmcu); | |
565 | adev->dm.fw_dmcu = NULL; | |
566 | return r; | |
567 | } | |
568 | ||
569 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; | |
570 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; | |
571 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; | |
572 | adev->firmware.fw_size += | |
573 | ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
574 | ||
575 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; | |
576 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; | |
577 | adev->firmware.fw_size += | |
578 | ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); | |
579 | ||
ee6e89c0 DF |
580 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); |
581 | ||
a94d5569 DF |
582 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); |
583 | ||
4562236b HW |
584 | return 0; |
585 | } | |
586 | ||
a94d5569 DF |
587 | static int dm_sw_init(void *handle) |
588 | { | |
589 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
590 | ||
591 | return load_dmcu_fw(adev); | |
592 | } | |
593 | ||
4562236b HW |
594 | static int dm_sw_fini(void *handle) |
595 | { | |
a94d5569 DF |
596 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
597 | ||
598 | if(adev->dm.fw_dmcu) { | |
599 | release_firmware(adev->dm.fw_dmcu); | |
600 | adev->dm.fw_dmcu = NULL; | |
601 | } | |
602 | ||
4562236b HW |
603 | return 0; |
604 | } | |
605 | ||
7abcf6b5 | 606 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
4562236b | 607 | { |
c84dec2f | 608 | struct amdgpu_dm_connector *aconnector; |
4562236b | 609 | struct drm_connector *connector; |
7abcf6b5 | 610 | int ret = 0; |
4562236b HW |
611 | |
612 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
613 | ||
614 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
b349f76e | 615 | aconnector = to_amdgpu_dm_connector(connector); |
30ec2b97 JFZ |
616 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
617 | aconnector->mst_mgr.aux) { | |
f1ad2f5e | 618 | DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", |
7abcf6b5 AG |
619 | aconnector, aconnector->base.base.id); |
620 | ||
621 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); | |
622 | if (ret < 0) { | |
623 | DRM_ERROR("DM_MST: Failed to start MST\n"); | |
624 | ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; | |
625 | return ret; | |
4562236b | 626 | } |
7abcf6b5 | 627 | } |
4562236b HW |
628 | } |
629 | ||
630 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
7abcf6b5 AG |
631 | return ret; |
632 | } | |
633 | ||
634 | static int dm_late_init(void *handle) | |
635 | { | |
42e67c3b | 636 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7abcf6b5 | 637 | |
42e67c3b | 638 | return detect_mst_link_for_all_connectors(adev->ddev); |
4562236b HW |
639 | } |
640 | ||
641 | static void s3_handle_mst(struct drm_device *dev, bool suspend) | |
642 | { | |
c84dec2f | 643 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
644 | struct drm_connector *connector; |
645 | ||
646 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
647 | ||
648 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
c84dec2f | 649 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
650 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
651 | !aconnector->mst_port) { | |
652 | ||
653 | if (suspend) | |
654 | drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr); | |
655 | else | |
656 | drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr); | |
657 | } | |
658 | } | |
659 | ||
660 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
661 | } | |
662 | ||
663 | static int dm_hw_init(void *handle) | |
664 | { | |
665 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
666 | /* Create DAL display manager */ | |
667 | amdgpu_dm_init(adev); | |
4562236b HW |
668 | amdgpu_dm_hpd_init(adev); |
669 | ||
4562236b HW |
670 | return 0; |
671 | } | |
672 | ||
673 | static int dm_hw_fini(void *handle) | |
674 | { | |
675 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
676 | ||
677 | amdgpu_dm_hpd_fini(adev); | |
678 | ||
679 | amdgpu_dm_irq_fini(adev); | |
21de3396 | 680 | amdgpu_dm_fini(adev); |
4562236b HW |
681 | return 0; |
682 | } | |
683 | ||
684 | static int dm_suspend(void *handle) | |
685 | { | |
686 | struct amdgpu_device *adev = handle; | |
687 | struct amdgpu_display_manager *dm = &adev->dm; | |
688 | int ret = 0; | |
4562236b HW |
689 | |
690 | s3_handle_mst(adev->ddev, true); | |
691 | ||
4562236b HW |
692 | amdgpu_dm_irq_suspend(adev); |
693 | ||
0a214e2f | 694 | WARN_ON(adev->dm.cached_state); |
a3621485 AG |
695 | adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); |
696 | ||
32f5062d | 697 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
4562236b HW |
698 | |
699 | return ret; | |
700 | } | |
701 | ||
1daf8c63 AD |
702 | static struct amdgpu_dm_connector * |
703 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, | |
704 | struct drm_crtc *crtc) | |
4562236b HW |
705 | { |
706 | uint32_t i; | |
c2cea706 | 707 | struct drm_connector_state *new_con_state; |
4562236b HW |
708 | struct drm_connector *connector; |
709 | struct drm_crtc *crtc_from_state; | |
710 | ||
c2cea706 LSL |
711 | for_each_new_connector_in_state(state, connector, new_con_state, i) { |
712 | crtc_from_state = new_con_state->crtc; | |
4562236b HW |
713 | |
714 | if (crtc_from_state == crtc) | |
c84dec2f | 715 | return to_amdgpu_dm_connector(connector); |
4562236b HW |
716 | } |
717 | ||
718 | return NULL; | |
719 | } | |
720 | ||
fbbdadf2 BL |
721 | static void emulated_link_detect(struct dc_link *link) |
722 | { | |
723 | struct dc_sink_init_data sink_init_data = { 0 }; | |
724 | struct display_sink_capability sink_caps = { 0 }; | |
725 | enum dc_edid_status edid_status; | |
726 | struct dc_context *dc_ctx = link->ctx; | |
727 | struct dc_sink *sink = NULL; | |
728 | struct dc_sink *prev_sink = NULL; | |
729 | ||
730 | link->type = dc_connection_none; | |
731 | prev_sink = link->local_sink; | |
732 | ||
733 | if (prev_sink != NULL) | |
734 | dc_sink_retain(prev_sink); | |
735 | ||
736 | switch (link->connector_signal) { | |
737 | case SIGNAL_TYPE_HDMI_TYPE_A: { | |
738 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
739 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; | |
740 | break; | |
741 | } | |
742 | ||
743 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { | |
744 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
745 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; | |
746 | break; | |
747 | } | |
748 | ||
749 | case SIGNAL_TYPE_DVI_DUAL_LINK: { | |
750 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
751 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; | |
752 | break; | |
753 | } | |
754 | ||
755 | case SIGNAL_TYPE_LVDS: { | |
756 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; | |
757 | sink_caps.signal = SIGNAL_TYPE_LVDS; | |
758 | break; | |
759 | } | |
760 | ||
761 | case SIGNAL_TYPE_EDP: { | |
762 | sink_caps.transaction_type = | |
763 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
764 | sink_caps.signal = SIGNAL_TYPE_EDP; | |
765 | break; | |
766 | } | |
767 | ||
768 | case SIGNAL_TYPE_DISPLAY_PORT: { | |
769 | sink_caps.transaction_type = | |
770 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | |
771 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; | |
772 | break; | |
773 | } | |
774 | ||
775 | default: | |
776 | DC_ERROR("Invalid connector type! signal:%d\n", | |
777 | link->connector_signal); | |
778 | return; | |
779 | } | |
780 | ||
781 | sink_init_data.link = link; | |
782 | sink_init_data.sink_signal = sink_caps.signal; | |
783 | ||
784 | sink = dc_sink_create(&sink_init_data); | |
785 | if (!sink) { | |
786 | DC_ERROR("Failed to create sink!\n"); | |
787 | return; | |
788 | } | |
789 | ||
790 | link->local_sink = sink; | |
791 | ||
792 | edid_status = dm_helpers_read_local_edid( | |
793 | link->ctx, | |
794 | link, | |
795 | sink); | |
796 | ||
797 | if (edid_status != EDID_OK) | |
798 | DC_ERROR("Failed to read EDID"); | |
799 | ||
800 | } | |
801 | ||
4562236b HW |
802 | static int dm_resume(void *handle) |
803 | { | |
804 | struct amdgpu_device *adev = handle; | |
4562236b HW |
805 | struct drm_device *ddev = adev->ddev; |
806 | struct amdgpu_display_manager *dm = &adev->dm; | |
c84dec2f | 807 | struct amdgpu_dm_connector *aconnector; |
4562236b | 808 | struct drm_connector *connector; |
4562236b | 809 | struct drm_crtc *crtc; |
c2cea706 | 810 | struct drm_crtc_state *new_crtc_state; |
fcb4019e LSL |
811 | struct dm_crtc_state *dm_new_crtc_state; |
812 | struct drm_plane *plane; | |
813 | struct drm_plane_state *new_plane_state; | |
814 | struct dm_plane_state *dm_new_plane_state; | |
fbbdadf2 | 815 | enum dc_connection_type new_connection_type = dc_connection_none; |
a80aa93d | 816 | int ret; |
a3621485 | 817 | int i; |
4562236b | 818 | |
a80aa93d ML |
819 | /* power on hardware */ |
820 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); | |
821 | ||
4562236b HW |
822 | /* program HPD filter */ |
823 | dc_resume(dm->dc); | |
824 | ||
825 | /* On resume we need to rewrite the MSTM control bits to enamble MST*/ | |
826 | s3_handle_mst(ddev, false); | |
827 | ||
828 | /* | |
829 | * early enable HPD Rx IRQ, should be done before set mode as short | |
830 | * pulse interrupts are used for MST | |
831 | */ | |
832 | amdgpu_dm_irq_resume_early(adev); | |
833 | ||
4562236b | 834 | /* Do detection*/ |
a80aa93d | 835 | list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { |
c84dec2f | 836 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
837 | |
838 | /* | |
839 | * this is the case when traversing through already created | |
840 | * MST connectors, should be skipped | |
841 | */ | |
842 | if (aconnector->mst_port) | |
843 | continue; | |
844 | ||
03ea364c | 845 | mutex_lock(&aconnector->hpd_lock); |
fbbdadf2 BL |
846 | if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) |
847 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
848 | ||
849 | if (aconnector->base.force && new_connection_type == dc_connection_none) | |
850 | emulated_link_detect(aconnector->dc_link); | |
851 | else | |
852 | dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); | |
3eb4eba4 RL |
853 | |
854 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) | |
855 | aconnector->fake_enable = false; | |
856 | ||
4562236b HW |
857 | aconnector->dc_sink = NULL; |
858 | amdgpu_dm_update_connector_after_detect(aconnector); | |
03ea364c | 859 | mutex_unlock(&aconnector->hpd_lock); |
4562236b HW |
860 | } |
861 | ||
1f6010a9 | 862 | /* Force mode set in atomic commit */ |
a80aa93d | 863 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) |
c2cea706 | 864 | new_crtc_state->active_changed = true; |
4f346e65 | 865 | |
fcb4019e LSL |
866 | /* |
867 | * atomic_check is expected to create the dc states. We need to release | |
868 | * them here, since they were duplicated as part of the suspend | |
869 | * procedure. | |
870 | */ | |
a80aa93d | 871 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { |
fcb4019e LSL |
872 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
873 | if (dm_new_crtc_state->stream) { | |
874 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); | |
875 | dc_stream_release(dm_new_crtc_state->stream); | |
876 | dm_new_crtc_state->stream = NULL; | |
877 | } | |
878 | } | |
879 | ||
a80aa93d | 880 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { |
fcb4019e LSL |
881 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
882 | if (dm_new_plane_state->dc_state) { | |
883 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); | |
884 | dc_plane_state_release(dm_new_plane_state->dc_state); | |
885 | dm_new_plane_state->dc_state = NULL; | |
886 | } | |
887 | } | |
888 | ||
a80aa93d | 889 | ret = drm_atomic_helper_resume(ddev, dm->cached_state); |
4562236b | 890 | |
a80aa93d | 891 | dm->cached_state = NULL; |
0a214e2f | 892 | |
9faa4237 | 893 | amdgpu_dm_irq_resume_late(adev); |
4562236b HW |
894 | |
895 | return ret; | |
896 | } | |
897 | ||
898 | static const struct amd_ip_funcs amdgpu_dm_funcs = { | |
899 | .name = "dm", | |
900 | .early_init = dm_early_init, | |
7abcf6b5 | 901 | .late_init = dm_late_init, |
4562236b HW |
902 | .sw_init = dm_sw_init, |
903 | .sw_fini = dm_sw_fini, | |
904 | .hw_init = dm_hw_init, | |
905 | .hw_fini = dm_hw_fini, | |
906 | .suspend = dm_suspend, | |
907 | .resume = dm_resume, | |
908 | .is_idle = dm_is_idle, | |
909 | .wait_for_idle = dm_wait_for_idle, | |
910 | .check_soft_reset = dm_check_soft_reset, | |
911 | .soft_reset = dm_soft_reset, | |
912 | .set_clockgating_state = dm_set_clockgating_state, | |
913 | .set_powergating_state = dm_set_powergating_state, | |
914 | }; | |
915 | ||
916 | const struct amdgpu_ip_block_version dm_ip_block = | |
917 | { | |
918 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
919 | .major = 1, | |
920 | .minor = 0, | |
921 | .rev = 0, | |
922 | .funcs = &amdgpu_dm_funcs, | |
923 | }; | |
924 | ||
ca3268c4 | 925 | |
7578ecda | 926 | static struct drm_atomic_state * |
ca3268c4 HW |
927 | dm_atomic_state_alloc(struct drm_device *dev) |
928 | { | |
929 | struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); | |
930 | ||
1dc90497 | 931 | if (!state) |
ca3268c4 | 932 | return NULL; |
1dc90497 AG |
933 | |
934 | if (drm_atomic_state_init(dev, &state->base) < 0) | |
935 | goto fail; | |
936 | ||
ca3268c4 | 937 | return &state->base; |
1dc90497 AG |
938 | |
939 | fail: | |
940 | kfree(state); | |
941 | return NULL; | |
ca3268c4 HW |
942 | } |
943 | ||
0a323b84 AG |
944 | static void |
945 | dm_atomic_state_clear(struct drm_atomic_state *state) | |
946 | { | |
947 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
948 | ||
949 | if (dm_state->context) { | |
608ac7bb | 950 | dc_release_state(dm_state->context); |
0a323b84 AG |
951 | dm_state->context = NULL; |
952 | } | |
953 | ||
954 | drm_atomic_state_default_clear(state); | |
955 | } | |
956 | ||
957 | static void | |
958 | dm_atomic_state_alloc_free(struct drm_atomic_state *state) | |
959 | { | |
960 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
961 | drm_atomic_state_default_release(state); | |
962 | kfree(dm_state); | |
963 | } | |
964 | ||
b3663f70 | 965 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
4d4772f6 | 966 | .fb_create = amdgpu_display_user_framebuffer_create, |
366c1baa | 967 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
4562236b | 968 | .atomic_check = amdgpu_dm_atomic_check, |
da5c47f6 | 969 | .atomic_commit = amdgpu_dm_atomic_commit, |
ca3268c4 | 970 | .atomic_state_alloc = dm_atomic_state_alloc, |
0a323b84 AG |
971 | .atomic_state_clear = dm_atomic_state_clear, |
972 | .atomic_state_free = dm_atomic_state_alloc_free | |
54f5499a AG |
973 | }; |
974 | ||
975 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { | |
976 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail | |
4562236b HW |
977 | }; |
978 | ||
7578ecda | 979 | static void |
3ee6b26b | 980 | amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) |
4562236b HW |
981 | { |
982 | struct drm_connector *connector = &aconnector->base; | |
983 | struct drm_device *dev = connector->dev; | |
b73a22d3 | 984 | struct dc_sink *sink; |
4562236b HW |
985 | |
986 | /* MST handled by drm_mst framework */ | |
987 | if (aconnector->mst_mgr.mst_state == true) | |
988 | return; | |
989 | ||
990 | ||
991 | sink = aconnector->dc_link->local_sink; | |
992 | ||
1f6010a9 DF |
993 | /* |
994 | * Edid mgmt connector gets first update only in mode_valid hook and then | |
4562236b | 995 | * the connector sink is set to either fake or physical sink depends on link status. |
1f6010a9 | 996 | * Skip if already done during boot. |
4562236b HW |
997 | */ |
998 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED | |
999 | && aconnector->dc_em_sink) { | |
1000 | ||
1f6010a9 DF |
1001 | /* |
1002 | * For S3 resume with headless use eml_sink to fake stream | |
1003 | * because on resume connector->sink is set to NULL | |
4562236b HW |
1004 | */ |
1005 | mutex_lock(&dev->mode_config.mutex); | |
1006 | ||
1007 | if (sink) { | |
922aa1e1 | 1008 | if (aconnector->dc_sink) { |
98e6436d | 1009 | amdgpu_dm_update_freesync_caps(connector, NULL); |
1f6010a9 DF |
1010 | /* |
1011 | * retain and release below are used to | |
1012 | * bump up refcount for sink because the link doesn't point | |
1013 | * to it anymore after disconnect, so on next crtc to connector | |
922aa1e1 AG |
1014 | * reshuffle by UMD we will get into unwanted dc_sink release |
1015 | */ | |
1016 | if (aconnector->dc_sink != aconnector->dc_em_sink) | |
1017 | dc_sink_release(aconnector->dc_sink); | |
1018 | } | |
4562236b | 1019 | aconnector->dc_sink = sink; |
98e6436d AK |
1020 | amdgpu_dm_update_freesync_caps(connector, |
1021 | aconnector->edid); | |
4562236b | 1022 | } else { |
98e6436d | 1023 | amdgpu_dm_update_freesync_caps(connector, NULL); |
4562236b HW |
1024 | if (!aconnector->dc_sink) |
1025 | aconnector->dc_sink = aconnector->dc_em_sink; | |
922aa1e1 AG |
1026 | else if (aconnector->dc_sink != aconnector->dc_em_sink) |
1027 | dc_sink_retain(aconnector->dc_sink); | |
4562236b HW |
1028 | } |
1029 | ||
1030 | mutex_unlock(&dev->mode_config.mutex); | |
1031 | return; | |
1032 | } | |
1033 | ||
1034 | /* | |
1035 | * TODO: temporary guard to look for proper fix | |
1036 | * if this sink is MST sink, we should not do anything | |
1037 | */ | |
1038 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) | |
1039 | return; | |
1040 | ||
1041 | if (aconnector->dc_sink == sink) { | |
1f6010a9 DF |
1042 | /* |
1043 | * We got a DP short pulse (Link Loss, DP CTS, etc...). | |
1044 | * Do nothing!! | |
1045 | */ | |
f1ad2f5e | 1046 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", |
4562236b HW |
1047 | aconnector->connector_id); |
1048 | return; | |
1049 | } | |
1050 | ||
f1ad2f5e | 1051 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", |
4562236b HW |
1052 | aconnector->connector_id, aconnector->dc_sink, sink); |
1053 | ||
1054 | mutex_lock(&dev->mode_config.mutex); | |
1055 | ||
1f6010a9 DF |
1056 | /* |
1057 | * 1. Update status of the drm connector | |
1058 | * 2. Send an event and let userspace tell us what to do | |
1059 | */ | |
4562236b | 1060 | if (sink) { |
1f6010a9 DF |
1061 | /* |
1062 | * TODO: check if we still need the S3 mode update workaround. | |
1063 | * If yes, put it here. | |
1064 | */ | |
4562236b | 1065 | if (aconnector->dc_sink) |
98e6436d | 1066 | amdgpu_dm_update_freesync_caps(connector, NULL); |
4562236b HW |
1067 | |
1068 | aconnector->dc_sink = sink; | |
900b3cb1 | 1069 | if (sink->dc_edid.length == 0) { |
4562236b | 1070 | aconnector->edid = NULL; |
e86e8947 | 1071 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
900b3cb1 | 1072 | } else { |
4562236b HW |
1073 | aconnector->edid = |
1074 | (struct edid *) sink->dc_edid.raw_edid; | |
1075 | ||
1076 | ||
c555f023 | 1077 | drm_connector_update_edid_property(connector, |
4562236b | 1078 | aconnector->edid); |
e86e8947 HV |
1079 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, |
1080 | aconnector->edid); | |
4562236b | 1081 | } |
98e6436d | 1082 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
4562236b HW |
1083 | |
1084 | } else { | |
e86e8947 | 1085 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
98e6436d | 1086 | amdgpu_dm_update_freesync_caps(connector, NULL); |
c555f023 | 1087 | drm_connector_update_edid_property(connector, NULL); |
4562236b HW |
1088 | aconnector->num_modes = 0; |
1089 | aconnector->dc_sink = NULL; | |
5326c452 | 1090 | aconnector->edid = NULL; |
4562236b HW |
1091 | } |
1092 | ||
1093 | mutex_unlock(&dev->mode_config.mutex); | |
1094 | } | |
1095 | ||
1096 | static void handle_hpd_irq(void *param) | |
1097 | { | |
c84dec2f | 1098 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
1099 | struct drm_connector *connector = &aconnector->base; |
1100 | struct drm_device *dev = connector->dev; | |
fbbdadf2 | 1101 | enum dc_connection_type new_connection_type = dc_connection_none; |
4562236b | 1102 | |
1f6010a9 DF |
1103 | /* |
1104 | * In case of failure or MST no need to update connector status or notify the OS | |
1105 | * since (for MST case) MST does this in its own context. | |
4562236b HW |
1106 | */ |
1107 | mutex_lock(&aconnector->hpd_lock); | |
2e0ac3d6 HW |
1108 | |
1109 | if (aconnector->fake_enable) | |
1110 | aconnector->fake_enable = false; | |
1111 | ||
fbbdadf2 BL |
1112 | if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) |
1113 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
1114 | ||
1115 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
1116 | emulated_link_detect(aconnector->dc_link); | |
1117 | ||
1118 | ||
1119 | drm_modeset_lock_all(dev); | |
1120 | dm_restore_drm_connector_state(dev, connector); | |
1121 | drm_modeset_unlock_all(dev); | |
1122 | ||
1123 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
1124 | drm_kms_helper_hotplug_event(dev); | |
1125 | ||
1126 | } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { | |
4562236b HW |
1127 | amdgpu_dm_update_connector_after_detect(aconnector); |
1128 | ||
1129 | ||
1130 | drm_modeset_lock_all(dev); | |
1131 | dm_restore_drm_connector_state(dev, connector); | |
1132 | drm_modeset_unlock_all(dev); | |
1133 | ||
1134 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) | |
1135 | drm_kms_helper_hotplug_event(dev); | |
1136 | } | |
1137 | mutex_unlock(&aconnector->hpd_lock); | |
1138 | ||
1139 | } | |
1140 | ||
c84dec2f | 1141 | static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) |
4562236b HW |
1142 | { |
1143 | uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; | |
1144 | uint8_t dret; | |
1145 | bool new_irq_handled = false; | |
1146 | int dpcd_addr; | |
1147 | int dpcd_bytes_to_read; | |
1148 | ||
1149 | const int max_process_count = 30; | |
1150 | int process_count = 0; | |
1151 | ||
1152 | const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); | |
1153 | ||
1154 | if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { | |
1155 | dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; | |
1156 | /* DPCD 0x200 - 0x201 for downstream IRQ */ | |
1157 | dpcd_addr = DP_SINK_COUNT; | |
1158 | } else { | |
1159 | dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; | |
1160 | /* DPCD 0x2002 - 0x2005 for downstream IRQ */ | |
1161 | dpcd_addr = DP_SINK_COUNT_ESI; | |
1162 | } | |
1163 | ||
1164 | dret = drm_dp_dpcd_read( | |
1165 | &aconnector->dm_dp_aux.aux, | |
1166 | dpcd_addr, | |
1167 | esi, | |
1168 | dpcd_bytes_to_read); | |
1169 | ||
1170 | while (dret == dpcd_bytes_to_read && | |
1171 | process_count < max_process_count) { | |
1172 | uint8_t retry; | |
1173 | dret = 0; | |
1174 | ||
1175 | process_count++; | |
1176 | ||
f1ad2f5e | 1177 | DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
4562236b HW |
1178 | /* handle HPD short pulse irq */ |
1179 | if (aconnector->mst_mgr.mst_state) | |
1180 | drm_dp_mst_hpd_irq( | |
1181 | &aconnector->mst_mgr, | |
1182 | esi, | |
1183 | &new_irq_handled); | |
4562236b HW |
1184 | |
1185 | if (new_irq_handled) { | |
1186 | /* ACK at DPCD to notify down stream */ | |
1187 | const int ack_dpcd_bytes_to_write = | |
1188 | dpcd_bytes_to_read - 1; | |
1189 | ||
1190 | for (retry = 0; retry < 3; retry++) { | |
1191 | uint8_t wret; | |
1192 | ||
1193 | wret = drm_dp_dpcd_write( | |
1194 | &aconnector->dm_dp_aux.aux, | |
1195 | dpcd_addr + 1, | |
1196 | &esi[1], | |
1197 | ack_dpcd_bytes_to_write); | |
1198 | if (wret == ack_dpcd_bytes_to_write) | |
1199 | break; | |
1200 | } | |
1201 | ||
1f6010a9 | 1202 | /* check if there is new irq to be handled */ |
4562236b HW |
1203 | dret = drm_dp_dpcd_read( |
1204 | &aconnector->dm_dp_aux.aux, | |
1205 | dpcd_addr, | |
1206 | esi, | |
1207 | dpcd_bytes_to_read); | |
1208 | ||
1209 | new_irq_handled = false; | |
d4a6e8a9 | 1210 | } else { |
4562236b | 1211 | break; |
d4a6e8a9 | 1212 | } |
4562236b HW |
1213 | } |
1214 | ||
1215 | if (process_count == max_process_count) | |
f1ad2f5e | 1216 | DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); |
4562236b HW |
1217 | } |
1218 | ||
1219 | static void handle_hpd_rx_irq(void *param) | |
1220 | { | |
c84dec2f | 1221 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
4562236b HW |
1222 | struct drm_connector *connector = &aconnector->base; |
1223 | struct drm_device *dev = connector->dev; | |
53cbf65c | 1224 | struct dc_link *dc_link = aconnector->dc_link; |
4562236b | 1225 | bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
fbbdadf2 | 1226 | enum dc_connection_type new_connection_type = dc_connection_none; |
4562236b | 1227 | |
1f6010a9 DF |
1228 | /* |
1229 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio | |
4562236b HW |
1230 | * conflict, after implement i2c helper, this mutex should be |
1231 | * retired. | |
1232 | */ | |
53cbf65c | 1233 | if (dc_link->type != dc_connection_mst_branch) |
4562236b HW |
1234 | mutex_lock(&aconnector->hpd_lock); |
1235 | ||
4e18814e | 1236 | if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) && |
4562236b HW |
1237 | !is_mst_root_connector) { |
1238 | /* Downstream Port status changed. */ | |
fbbdadf2 BL |
1239 | if (!dc_link_detect_sink(dc_link, &new_connection_type)) |
1240 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
1241 | ||
1242 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
1243 | emulated_link_detect(dc_link); | |
1244 | ||
1245 | if (aconnector->fake_enable) | |
1246 | aconnector->fake_enable = false; | |
1247 | ||
1248 | amdgpu_dm_update_connector_after_detect(aconnector); | |
1249 | ||
1250 | ||
1251 | drm_modeset_lock_all(dev); | |
1252 | dm_restore_drm_connector_state(dev, connector); | |
1253 | drm_modeset_unlock_all(dev); | |
1254 | ||
1255 | drm_kms_helper_hotplug_event(dev); | |
1256 | } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { | |
88ac3dda RL |
1257 | |
1258 | if (aconnector->fake_enable) | |
1259 | aconnector->fake_enable = false; | |
1260 | ||
4562236b HW |
1261 | amdgpu_dm_update_connector_after_detect(aconnector); |
1262 | ||
1263 | ||
1264 | drm_modeset_lock_all(dev); | |
1265 | dm_restore_drm_connector_state(dev, connector); | |
1266 | drm_modeset_unlock_all(dev); | |
1267 | ||
1268 | drm_kms_helper_hotplug_event(dev); | |
1269 | } | |
1270 | } | |
1271 | if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || | |
53cbf65c | 1272 | (dc_link->type == dc_connection_mst_branch)) |
4562236b HW |
1273 | dm_handle_hpd_rx_irq(aconnector); |
1274 | ||
e86e8947 HV |
1275 | if (dc_link->type != dc_connection_mst_branch) { |
1276 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); | |
4562236b | 1277 | mutex_unlock(&aconnector->hpd_lock); |
e86e8947 | 1278 | } |
4562236b HW |
1279 | } |
1280 | ||
1281 | static void register_hpd_handlers(struct amdgpu_device *adev) | |
1282 | { | |
1283 | struct drm_device *dev = adev->ddev; | |
1284 | struct drm_connector *connector; | |
c84dec2f | 1285 | struct amdgpu_dm_connector *aconnector; |
4562236b HW |
1286 | const struct dc_link *dc_link; |
1287 | struct dc_interrupt_params int_params = {0}; | |
1288 | ||
1289 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1290 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1291 | ||
1292 | list_for_each_entry(connector, | |
1293 | &dev->mode_config.connector_list, head) { | |
1294 | ||
c84dec2f | 1295 | aconnector = to_amdgpu_dm_connector(connector); |
4562236b HW |
1296 | dc_link = aconnector->dc_link; |
1297 | ||
1298 | if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { | |
1299 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
1300 | int_params.irq_source = dc_link->irq_source_hpd; | |
1301 | ||
1302 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1303 | handle_hpd_irq, | |
1304 | (void *) aconnector); | |
1305 | } | |
1306 | ||
1307 | if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { | |
1308 | ||
1309 | /* Also register for DP short pulse (hpd_rx). */ | |
1310 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; | |
1311 | int_params.irq_source = dc_link->irq_source_hpd_rx; | |
1312 | ||
1313 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1314 | handle_hpd_rx_irq, | |
1315 | (void *) aconnector); | |
1316 | } | |
1317 | } | |
1318 | } | |
1319 | ||
1320 | /* Register IRQ sources and initialize IRQ callbacks */ | |
1321 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) | |
1322 | { | |
1323 | struct dc *dc = adev->dm.dc; | |
1324 | struct common_irq_params *c_irq_params; | |
1325 | struct dc_interrupt_params int_params = {0}; | |
1326 | int r; | |
1327 | int i; | |
1ffdeca6 | 1328 | unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; |
2c8ad2d5 | 1329 | |
ff5ef992 | 1330 | if (adev->asic_type == CHIP_VEGA10 || |
2325ff30 | 1331 | adev->asic_type == CHIP_VEGA12 || |
1fe6bf2f | 1332 | adev->asic_type == CHIP_VEGA20 || |
ff5ef992 | 1333 | adev->asic_type == CHIP_RAVEN) |
3760f76c | 1334 | client_id = SOC15_IH_CLIENTID_DCE; |
4562236b HW |
1335 | |
1336 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1337 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1338 | ||
1f6010a9 DF |
1339 | /* |
1340 | * Actions of amdgpu_irq_add_id(): | |
4562236b HW |
1341 | * 1. Register a set() function with base driver. |
1342 | * Base driver will call set() function to enable/disable an | |
1343 | * interrupt in DC hardware. | |
1344 | * 2. Register amdgpu_dm_irq_handler(). | |
1345 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
1346 | * coming from DC hardware. | |
1347 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
1348 | * for acknowledging and handling. */ | |
1349 | ||
b57de80a | 1350 | /* Use VBLANK interrupt */ |
e9029155 | 1351 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { |
2c8ad2d5 | 1352 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
4562236b HW |
1353 | if (r) { |
1354 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
1355 | return r; | |
1356 | } | |
1357 | ||
1358 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1359 | int_params.irq_source = | |
3d761e79 | 1360 | dc_interrupt_to_irq_source(dc, i, 0); |
4562236b | 1361 | |
b57de80a | 1362 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
4562236b HW |
1363 | |
1364 | c_irq_params->adev = adev; | |
1365 | c_irq_params->irq_src = int_params.irq_source; | |
1366 | ||
1367 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1368 | dm_crtc_high_irq, c_irq_params); | |
1369 | } | |
1370 | ||
3d761e79 | 1371 | /* Use GRPH_PFLIP interrupt */ |
4562236b HW |
1372 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; |
1373 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { | |
2c8ad2d5 | 1374 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
4562236b HW |
1375 | if (r) { |
1376 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
1377 | return r; | |
1378 | } | |
1379 | ||
1380 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1381 | int_params.irq_source = | |
1382 | dc_interrupt_to_irq_source(dc, i, 0); | |
1383 | ||
1384 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
1385 | ||
1386 | c_irq_params->adev = adev; | |
1387 | c_irq_params->irq_src = int_params.irq_source; | |
1388 | ||
1389 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1390 | dm_pflip_high_irq, c_irq_params); | |
1391 | ||
1392 | } | |
1393 | ||
1394 | /* HPD */ | |
2c8ad2d5 AD |
1395 | r = amdgpu_irq_add_id(adev, client_id, |
1396 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); | |
4562236b HW |
1397 | if (r) { |
1398 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
1399 | return r; | |
1400 | } | |
1401 | ||
1402 | register_hpd_handlers(adev); | |
1403 | ||
1404 | return 0; | |
1405 | } | |
1406 | ||
ff5ef992 AD |
1407 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1408 | /* Register IRQ sources and initialize IRQ callbacks */ | |
1409 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) | |
1410 | { | |
1411 | struct dc *dc = adev->dm.dc; | |
1412 | struct common_irq_params *c_irq_params; | |
1413 | struct dc_interrupt_params int_params = {0}; | |
1414 | int r; | |
1415 | int i; | |
1416 | ||
1417 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1418 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; | |
1419 | ||
1f6010a9 DF |
1420 | /* |
1421 | * Actions of amdgpu_irq_add_id(): | |
ff5ef992 AD |
1422 | * 1. Register a set() function with base driver. |
1423 | * Base driver will call set() function to enable/disable an | |
1424 | * interrupt in DC hardware. | |
1425 | * 2. Register amdgpu_dm_irq_handler(). | |
1426 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts | |
1427 | * coming from DC hardware. | |
1428 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC | |
1429 | * for acknowledging and handling. | |
1f6010a9 | 1430 | */ |
ff5ef992 AD |
1431 | |
1432 | /* Use VSTARTUP interrupt */ | |
1433 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; | |
1434 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; | |
1435 | i++) { | |
3760f76c | 1436 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
ff5ef992 AD |
1437 | |
1438 | if (r) { | |
1439 | DRM_ERROR("Failed to add crtc irq id!\n"); | |
1440 | return r; | |
1441 | } | |
1442 | ||
1443 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1444 | int_params.irq_source = | |
1445 | dc_interrupt_to_irq_source(dc, i, 0); | |
1446 | ||
1447 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; | |
1448 | ||
1449 | c_irq_params->adev = adev; | |
1450 | c_irq_params->irq_src = int_params.irq_source; | |
1451 | ||
1452 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1453 | dm_crtc_high_irq, c_irq_params); | |
1454 | } | |
1455 | ||
1456 | /* Use GRPH_PFLIP interrupt */ | |
1457 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; | |
1458 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; | |
1459 | i++) { | |
3760f76c | 1460 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
ff5ef992 AD |
1461 | if (r) { |
1462 | DRM_ERROR("Failed to add page flip irq id!\n"); | |
1463 | return r; | |
1464 | } | |
1465 | ||
1466 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; | |
1467 | int_params.irq_source = | |
1468 | dc_interrupt_to_irq_source(dc, i, 0); | |
1469 | ||
1470 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; | |
1471 | ||
1472 | c_irq_params->adev = adev; | |
1473 | c_irq_params->irq_src = int_params.irq_source; | |
1474 | ||
1475 | amdgpu_dm_irq_register_interrupt(adev, &int_params, | |
1476 | dm_pflip_high_irq, c_irq_params); | |
1477 | ||
1478 | } | |
1479 | ||
1480 | /* HPD */ | |
3760f76c | 1481 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, |
ff5ef992 AD |
1482 | &adev->hpd_irq); |
1483 | if (r) { | |
1484 | DRM_ERROR("Failed to add hpd irq id!\n"); | |
1485 | return r; | |
1486 | } | |
1487 | ||
1488 | register_hpd_handlers(adev); | |
1489 | ||
1490 | return 0; | |
1491 | } | |
1492 | #endif | |
1493 | ||
4562236b HW |
1494 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
1495 | { | |
1496 | int r; | |
1497 | ||
1498 | adev->mode_info.mode_config_initialized = true; | |
1499 | ||
4562236b | 1500 | adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
54f5499a | 1501 | adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; |
4562236b HW |
1502 | |
1503 | adev->ddev->mode_config.max_width = 16384; | |
1504 | adev->ddev->mode_config.max_height = 16384; | |
1505 | ||
1506 | adev->ddev->mode_config.preferred_depth = 24; | |
1507 | adev->ddev->mode_config.prefer_shadow = 1; | |
1f6010a9 | 1508 | /* indicates support for immediate flip */ |
4562236b HW |
1509 | adev->ddev->mode_config.async_page_flip = true; |
1510 | ||
770d13b1 | 1511 | adev->ddev->mode_config.fb_base = adev->gmc.aper_base; |
4562236b | 1512 | |
3dc9b1ce | 1513 | r = amdgpu_display_modeset_create_props(adev); |
4562236b HW |
1514 | if (r) |
1515 | return r; | |
1516 | ||
1517 | return 0; | |
1518 | } | |
1519 | ||
1520 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ | |
1521 | defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) | |
1522 | ||
1523 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) | |
1524 | { | |
1525 | struct amdgpu_display_manager *dm = bl_get_data(bd); | |
1526 | ||
0cafc82f GS |
1527 | /* |
1528 | * PWM interperts 0 as 100% rather than 0% because of HW | |
1529 | * limitation for level 0.So limiting minimum brightness level | |
1530 | * to 1. | |
1531 | */ | |
1532 | if (bd->props.brightness < 1) | |
1533 | return 1; | |
4562236b HW |
1534 | if (dc_link_set_backlight_level(dm->backlight_link, |
1535 | bd->props.brightness, 0, 0)) | |
1536 | return 0; | |
1537 | else | |
1538 | return 1; | |
1539 | } | |
1540 | ||
1541 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) | |
1542 | { | |
620a0d27 DF |
1543 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
1544 | int ret = dc_link_get_backlight_level(dm->backlight_link); | |
1545 | ||
1546 | if (ret == DC_ERROR_UNEXPECTED) | |
1547 | return bd->props.brightness; | |
1548 | return ret; | |
4562236b HW |
1549 | } |
1550 | ||
1551 | static const struct backlight_ops amdgpu_dm_backlight_ops = { | |
1552 | .get_brightness = amdgpu_dm_backlight_get_brightness, | |
1553 | .update_status = amdgpu_dm_backlight_update_status, | |
1554 | }; | |
1555 | ||
7578ecda AD |
1556 | static void |
1557 | amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) | |
4562236b HW |
1558 | { |
1559 | char bl_name[16]; | |
1560 | struct backlight_properties props = { 0 }; | |
1561 | ||
1562 | props.max_brightness = AMDGPU_MAX_BL_LEVEL; | |
53a53f86 | 1563 | props.brightness = AMDGPU_MAX_BL_LEVEL; |
4562236b HW |
1564 | props.type = BACKLIGHT_RAW; |
1565 | ||
1566 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", | |
1567 | dm->adev->ddev->primary->index); | |
1568 | ||
1569 | dm->backlight_dev = backlight_device_register(bl_name, | |
1570 | dm->adev->ddev->dev, | |
1571 | dm, | |
1572 | &amdgpu_dm_backlight_ops, | |
1573 | &props); | |
1574 | ||
74baea42 | 1575 | if (IS_ERR(dm->backlight_dev)) |
4562236b HW |
1576 | DRM_ERROR("DM: Backlight registration failed!\n"); |
1577 | else | |
f1ad2f5e | 1578 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); |
4562236b HW |
1579 | } |
1580 | ||
1581 | #endif | |
1582 | ||
df534fff S |
1583 | static int initialize_plane(struct amdgpu_display_manager *dm, |
1584 | struct amdgpu_mode_info *mode_info, | |
1585 | int plane_id) | |
1586 | { | |
1587 | struct amdgpu_plane *plane; | |
1588 | unsigned long possible_crtcs; | |
1589 | int ret = 0; | |
1590 | ||
1591 | plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); | |
1592 | mode_info->planes[plane_id] = plane; | |
1593 | ||
1594 | if (!plane) { | |
1595 | DRM_ERROR("KMS: Failed to allocate plane\n"); | |
1596 | return -ENOMEM; | |
1597 | } | |
1598 | plane->base.type = mode_info->plane_type[plane_id]; | |
1599 | ||
1600 | /* | |
1f6010a9 | 1601 | * HACK: IGT tests expect that each plane can only have |
df534fff S |
1602 | * one possible CRTC. For now, set one CRTC for each |
1603 | * plane that is not an underlay, but still allow multiple | |
1604 | * CRTCs for underlay planes. | |
1605 | */ | |
1606 | possible_crtcs = 1 << plane_id; | |
1607 | if (plane_id >= dm->dc->caps.max_streams) | |
1608 | possible_crtcs = 0xff; | |
1609 | ||
1610 | ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs); | |
1611 | ||
1612 | if (ret) { | |
1613 | DRM_ERROR("KMS: Failed to initialize plane\n"); | |
1614 | return ret; | |
1615 | } | |
1616 | ||
1617 | return ret; | |
1618 | } | |
1619 | ||
89fc8d4e HW |
1620 | |
1621 | static void register_backlight_device(struct amdgpu_display_manager *dm, | |
1622 | struct dc_link *link) | |
1623 | { | |
1624 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ | |
1625 | defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) | |
1626 | ||
1627 | if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && | |
1628 | link->type != dc_connection_none) { | |
1f6010a9 DF |
1629 | /* |
1630 | * Event if registration failed, we should continue with | |
89fc8d4e HW |
1631 | * DM initialization because not having a backlight control |
1632 | * is better then a black screen. | |
1633 | */ | |
1634 | amdgpu_dm_register_backlight_device(dm); | |
1635 | ||
1636 | if (dm->backlight_dev) | |
1637 | dm->backlight_link = link; | |
1638 | } | |
1639 | #endif | |
1640 | } | |
1641 | ||
1642 | ||
1f6010a9 DF |
1643 | /* |
1644 | * In this architecture, the association | |
4562236b HW |
1645 | * connector -> encoder -> crtc |
1646 | * id not really requried. The crtc and connector will hold the | |
1647 | * display_index as an abstraction to use with DAL component | |
1648 | * | |
1649 | * Returns 0 on success | |
1650 | */ | |
7578ecda | 1651 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
4562236b HW |
1652 | { |
1653 | struct amdgpu_display_manager *dm = &adev->dm; | |
df534fff | 1654 | int32_t i; |
c84dec2f | 1655 | struct amdgpu_dm_connector *aconnector = NULL; |
f2a0f5e6 | 1656 | struct amdgpu_encoder *aencoder = NULL; |
d4e13b0d | 1657 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
4562236b | 1658 | uint32_t link_cnt; |
df534fff | 1659 | int32_t total_overlay_planes, total_primary_planes; |
fbbdadf2 | 1660 | enum dc_connection_type new_connection_type = dc_connection_none; |
4562236b HW |
1661 | |
1662 | link_cnt = dm->dc->caps.max_links; | |
4562236b HW |
1663 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
1664 | DRM_ERROR("DM: Failed to initialize mode config\n"); | |
59d0f396 | 1665 | return -EINVAL; |
4562236b HW |
1666 | } |
1667 | ||
df534fff S |
1668 | /* Identify the number of planes to be initialized */ |
1669 | total_overlay_planes = dm->dc->caps.max_slave_planes; | |
1670 | total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes; | |
efa6a8b7 | 1671 | |
df534fff S |
1672 | /* First initialize overlay planes, index starting after primary planes */ |
1673 | for (i = (total_overlay_planes - 1); i >= 0; i--) { | |
1674 | if (initialize_plane(dm, mode_info, (total_primary_planes + i))) { | |
1675 | DRM_ERROR("KMS: Failed to initialize overlay plane\n"); | |
cd8a2ae8 | 1676 | goto fail; |
d4e13b0d | 1677 | } |
df534fff | 1678 | } |
92f3ac40 | 1679 | |
df534fff S |
1680 | /* Initialize primary planes */ |
1681 | for (i = (total_primary_planes - 1); i >= 0; i--) { | |
1682 | if (initialize_plane(dm, mode_info, i)) { | |
1683 | DRM_ERROR("KMS: Failed to initialize primary plane\n"); | |
cd8a2ae8 | 1684 | goto fail; |
d4e13b0d AD |
1685 | } |
1686 | } | |
4562236b | 1687 | |
d4e13b0d AD |
1688 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
1689 | if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { | |
4562236b | 1690 | DRM_ERROR("KMS: Failed to initialize crtc\n"); |
cd8a2ae8 | 1691 | goto fail; |
4562236b | 1692 | } |
4562236b | 1693 | |
ab2541b6 | 1694 | dm->display_indexes_num = dm->dc->caps.max_streams; |
4562236b HW |
1695 | |
1696 | /* loops over all connectors on the board */ | |
1697 | for (i = 0; i < link_cnt; i++) { | |
89fc8d4e | 1698 | struct dc_link *link = NULL; |
4562236b HW |
1699 | |
1700 | if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { | |
1701 | DRM_ERROR( | |
1702 | "KMS: Cannot support more than %d display indexes\n", | |
1703 | AMDGPU_DM_MAX_DISPLAY_INDEX); | |
1704 | continue; | |
1705 | } | |
1706 | ||
1707 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); | |
1708 | if (!aconnector) | |
cd8a2ae8 | 1709 | goto fail; |
4562236b HW |
1710 | |
1711 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); | |
8440c304 | 1712 | if (!aencoder) |
cd8a2ae8 | 1713 | goto fail; |
4562236b HW |
1714 | |
1715 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { | |
1716 | DRM_ERROR("KMS: Failed to initialize encoder\n"); | |
cd8a2ae8 | 1717 | goto fail; |
4562236b HW |
1718 | } |
1719 | ||
1720 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { | |
1721 | DRM_ERROR("KMS: Failed to initialize connector\n"); | |
cd8a2ae8 | 1722 | goto fail; |
4562236b HW |
1723 | } |
1724 | ||
89fc8d4e HW |
1725 | link = dc_get_link_at_index(dm->dc, i); |
1726 | ||
fbbdadf2 BL |
1727 | if (!dc_link_detect_sink(link, &new_connection_type)) |
1728 | DRM_ERROR("KMS: Failed to detect connector\n"); | |
1729 | ||
1730 | if (aconnector->base.force && new_connection_type == dc_connection_none) { | |
1731 | emulated_link_detect(link); | |
1732 | amdgpu_dm_update_connector_after_detect(aconnector); | |
1733 | ||
1734 | } else if (dc_link_detect(link, DETECT_REASON_BOOT)) { | |
4562236b | 1735 | amdgpu_dm_update_connector_after_detect(aconnector); |
89fc8d4e HW |
1736 | register_backlight_device(dm, link); |
1737 | } | |
1738 | ||
1739 | ||
4562236b HW |
1740 | } |
1741 | ||
1742 | /* Software is initialized. Now we can register interrupt handlers. */ | |
1743 | switch (adev->asic_type) { | |
1744 | case CHIP_BONAIRE: | |
1745 | case CHIP_HAWAII: | |
cd4b356f AD |
1746 | case CHIP_KAVERI: |
1747 | case CHIP_KABINI: | |
1748 | case CHIP_MULLINS: | |
4562236b HW |
1749 | case CHIP_TONGA: |
1750 | case CHIP_FIJI: | |
1751 | case CHIP_CARRIZO: | |
1752 | case CHIP_STONEY: | |
1753 | case CHIP_POLARIS11: | |
1754 | case CHIP_POLARIS10: | |
b264d345 | 1755 | case CHIP_POLARIS12: |
7737de91 | 1756 | case CHIP_VEGAM: |
2c8ad2d5 | 1757 | case CHIP_VEGA10: |
2325ff30 | 1758 | case CHIP_VEGA12: |
1fe6bf2f | 1759 | case CHIP_VEGA20: |
4562236b HW |
1760 | if (dce110_register_irq_handlers(dm->adev)) { |
1761 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 1762 | goto fail; |
4562236b HW |
1763 | } |
1764 | break; | |
ff5ef992 AD |
1765 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1766 | case CHIP_RAVEN: | |
1767 | if (dcn10_register_irq_handlers(dm->adev)) { | |
1768 | DRM_ERROR("DM: Failed to initialize IRQ\n"); | |
cd8a2ae8 | 1769 | goto fail; |
ff5ef992 AD |
1770 | } |
1771 | break; | |
1772 | #endif | |
4562236b | 1773 | default: |
e63f8673 | 1774 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
cd8a2ae8 | 1775 | goto fail; |
4562236b HW |
1776 | } |
1777 | ||
1bc460a4 HW |
1778 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
1779 | dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; | |
1780 | ||
4562236b | 1781 | return 0; |
cd8a2ae8 | 1782 | fail: |
4562236b | 1783 | kfree(aencoder); |
4562236b | 1784 | kfree(aconnector); |
3be5262e | 1785 | for (i = 0; i < dm->dc->caps.max_planes; i++) |
d4e13b0d | 1786 | kfree(mode_info->planes[i]); |
59d0f396 | 1787 | return -EINVAL; |
4562236b HW |
1788 | } |
1789 | ||
7578ecda | 1790 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
4562236b HW |
1791 | { |
1792 | drm_mode_config_cleanup(dm->ddev); | |
1793 | return; | |
1794 | } | |
1795 | ||
1796 | /****************************************************************************** | |
1797 | * amdgpu_display_funcs functions | |
1798 | *****************************************************************************/ | |
1799 | ||
1f6010a9 | 1800 | /* |
4562236b HW |
1801 | * dm_bandwidth_update - program display watermarks |
1802 | * | |
1803 | * @adev: amdgpu_device pointer | |
1804 | * | |
1805 | * Calculate and program the display watermarks and line buffer allocation. | |
1806 | */ | |
1807 | static void dm_bandwidth_update(struct amdgpu_device *adev) | |
1808 | { | |
49c07a99 | 1809 | /* TODO: implement later */ |
4562236b HW |
1810 | } |
1811 | ||
4562236b HW |
1812 | static int amdgpu_notify_freesync(struct drm_device *dev, void *data, |
1813 | struct drm_file *filp) | |
1814 | { | |
98e6436d AK |
1815 | struct drm_atomic_state *state; |
1816 | struct drm_modeset_acquire_ctx ctx; | |
1817 | struct drm_crtc *crtc; | |
1818 | struct drm_connector *connector; | |
1819 | struct drm_connector_state *old_con_state, *new_con_state; | |
1820 | int ret = 0; | |
4562236b | 1821 | uint8_t i; |
98e6436d | 1822 | bool enable = false; |
4562236b | 1823 | |
98e6436d | 1824 | drm_modeset_acquire_init(&ctx, 0); |
4562236b | 1825 | |
98e6436d AK |
1826 | state = drm_atomic_state_alloc(dev); |
1827 | if (!state) { | |
1828 | ret = -ENOMEM; | |
1829 | goto out; | |
1830 | } | |
1831 | state->acquire_ctx = &ctx; | |
1832 | ||
1833 | retry: | |
1834 | drm_for_each_crtc(crtc, dev) { | |
1835 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
1836 | if (ret) | |
1837 | goto fail; | |
1838 | ||
1839 | /* TODO rework amdgpu_dm_commit_planes so we don't need this */ | |
1840 | ret = drm_atomic_add_affected_planes(state, crtc); | |
1841 | if (ret) | |
1842 | goto fail; | |
1843 | } | |
4562236b | 1844 | |
98e6436d AK |
1845 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
1846 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
1847 | struct drm_crtc_state *new_crtc_state; | |
1848 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
1849 | struct dm_crtc_state *dm_new_crtc_state; | |
4562236b | 1850 | |
98e6436d AK |
1851 | if (!acrtc) { |
1852 | ASSERT(0); | |
1853 | continue; | |
1854 | } | |
4562236b | 1855 | |
98e6436d AK |
1856 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
1857 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
4562236b | 1858 | |
98e6436d | 1859 | dm_new_crtc_state->freesync_enabled = enable; |
4562236b HW |
1860 | } |
1861 | ||
98e6436d AK |
1862 | ret = drm_atomic_commit(state); |
1863 | ||
1864 | fail: | |
1865 | if (ret == -EDEADLK) { | |
1866 | drm_atomic_state_clear(state); | |
1867 | drm_modeset_backoff(&ctx); | |
1868 | goto retry; | |
1869 | } | |
1870 | ||
1871 | drm_atomic_state_put(state); | |
1872 | ||
1873 | out: | |
1874 | drm_modeset_drop_locks(&ctx); | |
1875 | drm_modeset_acquire_fini(&ctx); | |
1876 | return ret; | |
4562236b HW |
1877 | } |
1878 | ||
39cc5be2 | 1879 | static const struct amdgpu_display_funcs dm_display_funcs = { |
4562236b HW |
1880 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
1881 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ | |
7b42573b HW |
1882 | .backlight_set_level = NULL, /* never called for DC */ |
1883 | .backlight_get_level = NULL, /* never called for DC */ | |
4562236b HW |
1884 | .hpd_sense = NULL,/* called unconditionally */ |
1885 | .hpd_set_polarity = NULL, /* called unconditionally */ | |
1886 | .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ | |
4562236b HW |
1887 | .page_flip_get_scanoutpos = |
1888 | dm_crtc_get_scanoutpos,/* called unconditionally */ | |
1889 | .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ | |
1890 | .add_connector = NULL, /* VBIOS parsing. DAL does it. */ | |
1891 | .notify_freesync = amdgpu_notify_freesync, | |
1892 | ||
1893 | }; | |
1894 | ||
1895 | #if defined(CONFIG_DEBUG_KERNEL_DC) | |
1896 | ||
3ee6b26b AD |
1897 | static ssize_t s3_debug_store(struct device *device, |
1898 | struct device_attribute *attr, | |
1899 | const char *buf, | |
1900 | size_t count) | |
4562236b HW |
1901 | { |
1902 | int ret; | |
1903 | int s3_state; | |
1904 | struct pci_dev *pdev = to_pci_dev(device); | |
1905 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1906 | struct amdgpu_device *adev = drm_dev->dev_private; | |
1907 | ||
1908 | ret = kstrtoint(buf, 0, &s3_state); | |
1909 | ||
1910 | if (ret == 0) { | |
1911 | if (s3_state) { | |
1912 | dm_resume(adev); | |
4562236b HW |
1913 | drm_kms_helper_hotplug_event(adev->ddev); |
1914 | } else | |
1915 | dm_suspend(adev); | |
1916 | } | |
1917 | ||
1918 | return ret == 0 ? count : 0; | |
1919 | } | |
1920 | ||
1921 | DEVICE_ATTR_WO(s3_debug); | |
1922 | ||
1923 | #endif | |
1924 | ||
1925 | static int dm_early_init(void *handle) | |
1926 | { | |
1927 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1928 | ||
4562236b HW |
1929 | switch (adev->asic_type) { |
1930 | case CHIP_BONAIRE: | |
1931 | case CHIP_HAWAII: | |
1932 | adev->mode_info.num_crtc = 6; | |
1933 | adev->mode_info.num_hpd = 6; | |
1934 | adev->mode_info.num_dig = 6; | |
3be5262e | 1935 | adev->mode_info.plane_type = dm_plane_type_default; |
4562236b | 1936 | break; |
cd4b356f AD |
1937 | case CHIP_KAVERI: |
1938 | adev->mode_info.num_crtc = 4; | |
1939 | adev->mode_info.num_hpd = 6; | |
1940 | adev->mode_info.num_dig = 7; | |
1941 | adev->mode_info.plane_type = dm_plane_type_default; | |
1942 | break; | |
1943 | case CHIP_KABINI: | |
1944 | case CHIP_MULLINS: | |
1945 | adev->mode_info.num_crtc = 2; | |
1946 | adev->mode_info.num_hpd = 6; | |
1947 | adev->mode_info.num_dig = 6; | |
1948 | adev->mode_info.plane_type = dm_plane_type_default; | |
1949 | break; | |
4562236b HW |
1950 | case CHIP_FIJI: |
1951 | case CHIP_TONGA: | |
1952 | adev->mode_info.num_crtc = 6; | |
1953 | adev->mode_info.num_hpd = 6; | |
1954 | adev->mode_info.num_dig = 7; | |
3be5262e | 1955 | adev->mode_info.plane_type = dm_plane_type_default; |
4562236b HW |
1956 | break; |
1957 | case CHIP_CARRIZO: | |
1958 | adev->mode_info.num_crtc = 3; | |
1959 | adev->mode_info.num_hpd = 6; | |
1960 | adev->mode_info.num_dig = 9; | |
3be5262e | 1961 | adev->mode_info.plane_type = dm_plane_type_carizzo; |
4562236b HW |
1962 | break; |
1963 | case CHIP_STONEY: | |
1964 | adev->mode_info.num_crtc = 2; | |
1965 | adev->mode_info.num_hpd = 6; | |
1966 | adev->mode_info.num_dig = 9; | |
3be5262e | 1967 | adev->mode_info.plane_type = dm_plane_type_stoney; |
4562236b HW |
1968 | break; |
1969 | case CHIP_POLARIS11: | |
b264d345 | 1970 | case CHIP_POLARIS12: |
4562236b HW |
1971 | adev->mode_info.num_crtc = 5; |
1972 | adev->mode_info.num_hpd = 5; | |
1973 | adev->mode_info.num_dig = 5; | |
3be5262e | 1974 | adev->mode_info.plane_type = dm_plane_type_default; |
4562236b HW |
1975 | break; |
1976 | case CHIP_POLARIS10: | |
7737de91 | 1977 | case CHIP_VEGAM: |
4562236b HW |
1978 | adev->mode_info.num_crtc = 6; |
1979 | adev->mode_info.num_hpd = 6; | |
1980 | adev->mode_info.num_dig = 6; | |
3be5262e | 1981 | adev->mode_info.plane_type = dm_plane_type_default; |
4562236b | 1982 | break; |
2c8ad2d5 | 1983 | case CHIP_VEGA10: |
2325ff30 | 1984 | case CHIP_VEGA12: |
1fe6bf2f | 1985 | case CHIP_VEGA20: |
2c8ad2d5 AD |
1986 | adev->mode_info.num_crtc = 6; |
1987 | adev->mode_info.num_hpd = 6; | |
1988 | adev->mode_info.num_dig = 6; | |
3be5262e | 1989 | adev->mode_info.plane_type = dm_plane_type_default; |
2c8ad2d5 | 1990 | break; |
ff5ef992 AD |
1991 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
1992 | case CHIP_RAVEN: | |
1993 | adev->mode_info.num_crtc = 4; | |
1994 | adev->mode_info.num_hpd = 4; | |
1995 | adev->mode_info.num_dig = 4; | |
3be5262e | 1996 | adev->mode_info.plane_type = dm_plane_type_default; |
ff5ef992 AD |
1997 | break; |
1998 | #endif | |
4562236b | 1999 | default: |
e63f8673 | 2000 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); |
4562236b HW |
2001 | return -EINVAL; |
2002 | } | |
2003 | ||
c8dd5715 MD |
2004 | amdgpu_dm_set_irq_funcs(adev); |
2005 | ||
39cc5be2 AD |
2006 | if (adev->mode_info.funcs == NULL) |
2007 | adev->mode_info.funcs = &dm_display_funcs; | |
2008 | ||
1f6010a9 DF |
2009 | /* |
2010 | * Note: Do NOT change adev->audio_endpt_rreg and | |
4562236b | 2011 | * adev->audio_endpt_wreg because they are initialised in |
1f6010a9 DF |
2012 | * amdgpu_device_init() |
2013 | */ | |
4562236b HW |
2014 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
2015 | device_create_file( | |
2016 | adev->ddev->dev, | |
2017 | &dev_attr_s3_debug); | |
2018 | #endif | |
2019 | ||
2020 | return 0; | |
2021 | } | |
2022 | ||
9b690ef3 | 2023 | static bool modeset_required(struct drm_crtc_state *crtc_state, |
0971c40e HW |
2024 | struct dc_stream_state *new_stream, |
2025 | struct dc_stream_state *old_stream) | |
9b690ef3 | 2026 | { |
e7b07cee HW |
2027 | if (!drm_atomic_crtc_needs_modeset(crtc_state)) |
2028 | return false; | |
2029 | ||
2030 | if (!crtc_state->enable) | |
2031 | return false; | |
2032 | ||
2033 | return crtc_state->active; | |
2034 | } | |
2035 | ||
2036 | static bool modereset_required(struct drm_crtc_state *crtc_state) | |
2037 | { | |
2038 | if (!drm_atomic_crtc_needs_modeset(crtc_state)) | |
2039 | return false; | |
2040 | ||
2041 | return !crtc_state->enable || !crtc_state->active; | |
2042 | } | |
2043 | ||
7578ecda | 2044 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
e7b07cee HW |
2045 | { |
2046 | drm_encoder_cleanup(encoder); | |
2047 | kfree(encoder); | |
2048 | } | |
2049 | ||
2050 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { | |
2051 | .destroy = amdgpu_dm_encoder_destroy, | |
2052 | }; | |
2053 | ||
3ee6b26b AD |
2054 | static bool fill_rects_from_plane_state(const struct drm_plane_state *state, |
2055 | struct dc_plane_state *plane_state) | |
e7b07cee | 2056 | { |
3be5262e HW |
2057 | plane_state->src_rect.x = state->src_x >> 16; |
2058 | plane_state->src_rect.y = state->src_y >> 16; | |
1f6010a9 | 2059 | /* we ignore the mantissa for now and do not deal with floating pixels :( */ |
3be5262e | 2060 | plane_state->src_rect.width = state->src_w >> 16; |
e7b07cee | 2061 | |
3be5262e | 2062 | if (plane_state->src_rect.width == 0) |
e7b07cee HW |
2063 | return false; |
2064 | ||
3be5262e HW |
2065 | plane_state->src_rect.height = state->src_h >> 16; |
2066 | if (plane_state->src_rect.height == 0) | |
e7b07cee HW |
2067 | return false; |
2068 | ||
3be5262e HW |
2069 | plane_state->dst_rect.x = state->crtc_x; |
2070 | plane_state->dst_rect.y = state->crtc_y; | |
e7b07cee HW |
2071 | |
2072 | if (state->crtc_w == 0) | |
2073 | return false; | |
2074 | ||
3be5262e | 2075 | plane_state->dst_rect.width = state->crtc_w; |
e7b07cee HW |
2076 | |
2077 | if (state->crtc_h == 0) | |
2078 | return false; | |
2079 | ||
3be5262e | 2080 | plane_state->dst_rect.height = state->crtc_h; |
e7b07cee | 2081 | |
3be5262e | 2082 | plane_state->clip_rect = plane_state->dst_rect; |
e7b07cee HW |
2083 | |
2084 | switch (state->rotation & DRM_MODE_ROTATE_MASK) { | |
2085 | case DRM_MODE_ROTATE_0: | |
3be5262e | 2086 | plane_state->rotation = ROTATION_ANGLE_0; |
e7b07cee HW |
2087 | break; |
2088 | case DRM_MODE_ROTATE_90: | |
3be5262e | 2089 | plane_state->rotation = ROTATION_ANGLE_90; |
e7b07cee HW |
2090 | break; |
2091 | case DRM_MODE_ROTATE_180: | |
3be5262e | 2092 | plane_state->rotation = ROTATION_ANGLE_180; |
e7b07cee HW |
2093 | break; |
2094 | case DRM_MODE_ROTATE_270: | |
3be5262e | 2095 | plane_state->rotation = ROTATION_ANGLE_270; |
e7b07cee HW |
2096 | break; |
2097 | default: | |
3be5262e | 2098 | plane_state->rotation = ROTATION_ANGLE_0; |
e7b07cee HW |
2099 | break; |
2100 | } | |
2101 | ||
4562236b HW |
2102 | return true; |
2103 | } | |
3ee6b26b | 2104 | static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, |
9817d5f5 | 2105 | uint64_t *tiling_flags) |
e7b07cee | 2106 | { |
e68d14dd | 2107 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); |
e7b07cee | 2108 | int r = amdgpu_bo_reserve(rbo, false); |
b830ebc9 | 2109 | |
e7b07cee | 2110 | if (unlikely(r)) { |
1f6010a9 | 2111 | /* Don't show error message when returning -ERESTARTSYS */ |
9bbc3031 JZ |
2112 | if (r != -ERESTARTSYS) |
2113 | DRM_ERROR("Unable to reserve buffer: %d\n", r); | |
e7b07cee HW |
2114 | return r; |
2115 | } | |
2116 | ||
e7b07cee HW |
2117 | if (tiling_flags) |
2118 | amdgpu_bo_get_tiling_flags(rbo, tiling_flags); | |
2119 | ||
2120 | amdgpu_bo_unreserve(rbo); | |
2121 | ||
2122 | return r; | |
2123 | } | |
2124 | ||
3ee6b26b AD |
2125 | static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, |
2126 | struct dc_plane_state *plane_state, | |
9817d5f5 | 2127 | const struct amdgpu_framebuffer *amdgpu_fb) |
e7b07cee HW |
2128 | { |
2129 | uint64_t tiling_flags; | |
e7b07cee HW |
2130 | unsigned int awidth; |
2131 | const struct drm_framebuffer *fb = &amdgpu_fb->base; | |
2132 | int ret = 0; | |
2133 | struct drm_format_name_buf format_name; | |
2134 | ||
2135 | ret = get_fb_info( | |
2136 | amdgpu_fb, | |
9817d5f5 | 2137 | &tiling_flags); |
e7b07cee HW |
2138 | |
2139 | if (ret) | |
2140 | return ret; | |
2141 | ||
2142 | switch (fb->format->format) { | |
2143 | case DRM_FORMAT_C8: | |
3be5262e | 2144 | plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; |
e7b07cee HW |
2145 | break; |
2146 | case DRM_FORMAT_RGB565: | |
3be5262e | 2147 | plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; |
e7b07cee HW |
2148 | break; |
2149 | case DRM_FORMAT_XRGB8888: | |
2150 | case DRM_FORMAT_ARGB8888: | |
3be5262e | 2151 | plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
e7b07cee HW |
2152 | break; |
2153 | case DRM_FORMAT_XRGB2101010: | |
2154 | case DRM_FORMAT_ARGB2101010: | |
3be5262e | 2155 | plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; |
e7b07cee HW |
2156 | break; |
2157 | case DRM_FORMAT_XBGR2101010: | |
2158 | case DRM_FORMAT_ABGR2101010: | |
3be5262e | 2159 | plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; |
e7b07cee | 2160 | break; |
bcd47f60 MR |
2161 | case DRM_FORMAT_XBGR8888: |
2162 | case DRM_FORMAT_ABGR8888: | |
2163 | plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; | |
2164 | break; | |
e7b07cee | 2165 | case DRM_FORMAT_NV21: |
3be5262e | 2166 | plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; |
e7b07cee HW |
2167 | break; |
2168 | case DRM_FORMAT_NV12: | |
3be5262e | 2169 | plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; |
e7b07cee HW |
2170 | break; |
2171 | default: | |
2172 | DRM_ERROR("Unsupported screen format %s\n", | |
1ecfc3da | 2173 | drm_get_format_name(fb->format->format, &format_name)); |
e7b07cee HW |
2174 | return -EINVAL; |
2175 | } | |
2176 | ||
3be5262e HW |
2177 | if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { |
2178 | plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; | |
3be5262e HW |
2179 | plane_state->plane_size.grph.surface_size.x = 0; |
2180 | plane_state->plane_size.grph.surface_size.y = 0; | |
2181 | plane_state->plane_size.grph.surface_size.width = fb->width; | |
2182 | plane_state->plane_size.grph.surface_size.height = fb->height; | |
2183 | plane_state->plane_size.grph.surface_pitch = | |
e7b07cee HW |
2184 | fb->pitches[0] / fb->format->cpp[0]; |
2185 | /* TODO: unhardcode */ | |
3be5262e | 2186 | plane_state->color_space = COLOR_SPACE_SRGB; |
e7b07cee HW |
2187 | |
2188 | } else { | |
2189 | awidth = ALIGN(fb->width, 64); | |
3be5262e | 2190 | plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; |
3be5262e HW |
2191 | plane_state->plane_size.video.luma_size.x = 0; |
2192 | plane_state->plane_size.video.luma_size.y = 0; | |
2193 | plane_state->plane_size.video.luma_size.width = awidth; | |
2194 | plane_state->plane_size.video.luma_size.height = fb->height; | |
e7b07cee | 2195 | /* TODO: unhardcode */ |
3be5262e | 2196 | plane_state->plane_size.video.luma_pitch = awidth; |
e7b07cee | 2197 | |
3be5262e HW |
2198 | plane_state->plane_size.video.chroma_size.x = 0; |
2199 | plane_state->plane_size.video.chroma_size.y = 0; | |
2200 | plane_state->plane_size.video.chroma_size.width = awidth; | |
2201 | plane_state->plane_size.video.chroma_size.height = fb->height; | |
2202 | plane_state->plane_size.video.chroma_pitch = awidth / 2; | |
e7b07cee HW |
2203 | |
2204 | /* TODO: unhardcode */ | |
3be5262e | 2205 | plane_state->color_space = COLOR_SPACE_YCBCR709; |
e7b07cee HW |
2206 | } |
2207 | ||
3be5262e | 2208 | memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); |
e7b07cee | 2209 | |
b830ebc9 HW |
2210 | /* Fill GFX8 params */ |
2211 | if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { | |
2212 | unsigned int bankw, bankh, mtaspect, tile_split, num_banks; | |
e7b07cee HW |
2213 | |
2214 | bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); | |
2215 | bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); | |
2216 | mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); | |
2217 | tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); | |
2218 | num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); | |
2219 | ||
2220 | /* XXX fix me for VI */ | |
3be5262e HW |
2221 | plane_state->tiling_info.gfx8.num_banks = num_banks; |
2222 | plane_state->tiling_info.gfx8.array_mode = | |
e7b07cee | 2223 | DC_ARRAY_2D_TILED_THIN1; |
3be5262e HW |
2224 | plane_state->tiling_info.gfx8.tile_split = tile_split; |
2225 | plane_state->tiling_info.gfx8.bank_width = bankw; | |
2226 | plane_state->tiling_info.gfx8.bank_height = bankh; | |
2227 | plane_state->tiling_info.gfx8.tile_aspect = mtaspect; | |
2228 | plane_state->tiling_info.gfx8.tile_mode = | |
e7b07cee HW |
2229 | DC_ADDR_SURF_MICRO_TILING_DISPLAY; |
2230 | } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) | |
2231 | == DC_ARRAY_1D_TILED_THIN1) { | |
3be5262e | 2232 | plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; |
e7b07cee HW |
2233 | } |
2234 | ||
3be5262e | 2235 | plane_state->tiling_info.gfx8.pipe_config = |
e7b07cee HW |
2236 | AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); |
2237 | ||
2238 | if (adev->asic_type == CHIP_VEGA10 || | |
2325ff30 | 2239 | adev->asic_type == CHIP_VEGA12 || |
1fe6bf2f | 2240 | adev->asic_type == CHIP_VEGA20 || |
e7b07cee HW |
2241 | adev->asic_type == CHIP_RAVEN) { |
2242 | /* Fill GFX9 params */ | |
3be5262e | 2243 | plane_state->tiling_info.gfx9.num_pipes = |
e7b07cee | 2244 | adev->gfx.config.gb_addr_config_fields.num_pipes; |
3be5262e | 2245 | plane_state->tiling_info.gfx9.num_banks = |
e7b07cee | 2246 | adev->gfx.config.gb_addr_config_fields.num_banks; |
3be5262e | 2247 | plane_state->tiling_info.gfx9.pipe_interleave = |
e7b07cee | 2248 | adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; |
3be5262e | 2249 | plane_state->tiling_info.gfx9.num_shader_engines = |
e7b07cee | 2250 | adev->gfx.config.gb_addr_config_fields.num_se; |
3be5262e | 2251 | plane_state->tiling_info.gfx9.max_compressed_frags = |
e7b07cee | 2252 | adev->gfx.config.gb_addr_config_fields.max_compress_frags; |
3be5262e | 2253 | plane_state->tiling_info.gfx9.num_rb_per_se = |
e7b07cee | 2254 | adev->gfx.config.gb_addr_config_fields.num_rb_per_se; |
3be5262e | 2255 | plane_state->tiling_info.gfx9.swizzle = |
e7b07cee | 2256 | AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); |
3be5262e | 2257 | plane_state->tiling_info.gfx9.shaderEnable = 1; |
e7b07cee HW |
2258 | } |
2259 | ||
3be5262e HW |
2260 | plane_state->visible = true; |
2261 | plane_state->scaling_quality.h_taps_c = 0; | |
2262 | plane_state->scaling_quality.v_taps_c = 0; | |
e7b07cee | 2263 | |
3be5262e HW |
2264 | /* is this needed? is plane_state zeroed at allocation? */ |
2265 | plane_state->scaling_quality.h_taps = 0; | |
2266 | plane_state->scaling_quality.v_taps = 0; | |
2267 | plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; | |
e7b07cee HW |
2268 | |
2269 | return ret; | |
2270 | ||
2271 | } | |
2272 | ||
3ee6b26b AD |
2273 | static int fill_plane_attributes(struct amdgpu_device *adev, |
2274 | struct dc_plane_state *dc_plane_state, | |
2275 | struct drm_plane_state *plane_state, | |
9817d5f5 | 2276 | struct drm_crtc_state *crtc_state) |
e7b07cee HW |
2277 | { |
2278 | const struct amdgpu_framebuffer *amdgpu_fb = | |
2279 | to_amdgpu_framebuffer(plane_state->fb); | |
2280 | const struct drm_crtc *crtc = plane_state->crtc; | |
e7b07cee HW |
2281 | int ret = 0; |
2282 | ||
3be5262e | 2283 | if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) |
e7b07cee HW |
2284 | return -EINVAL; |
2285 | ||
2286 | ret = fill_plane_attributes_from_fb( | |
2287 | crtc->dev->dev_private, | |
3be5262e | 2288 | dc_plane_state, |
9817d5f5 | 2289 | amdgpu_fb); |
e7b07cee HW |
2290 | |
2291 | if (ret) | |
2292 | return ret; | |
2293 | ||
e277adc5 LSL |
2294 | /* |
2295 | * Always set input transfer function, since plane state is refreshed | |
2296 | * every time. | |
2297 | */ | |
2298 | ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); | |
8c45c5db LSL |
2299 | if (ret) { |
2300 | dc_transfer_func_release(dc_plane_state->in_transfer_func); | |
2301 | dc_plane_state->in_transfer_func = NULL; | |
2302 | } | |
e7b07cee HW |
2303 | |
2304 | return ret; | |
2305 | } | |
2306 | ||
3ee6b26b AD |
2307 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
2308 | const struct dm_connector_state *dm_state, | |
2309 | struct dc_stream_state *stream) | |
e7b07cee HW |
2310 | { |
2311 | enum amdgpu_rmx_type rmx_type; | |
2312 | ||
2313 | struct rect src = { 0 }; /* viewport in composition space*/ | |
2314 | struct rect dst = { 0 }; /* stream addressable area */ | |
2315 | ||
2316 | /* no mode. nothing to be done */ | |
2317 | if (!mode) | |
2318 | return; | |
2319 | ||
2320 | /* Full screen scaling by default */ | |
2321 | src.width = mode->hdisplay; | |
2322 | src.height = mode->vdisplay; | |
2323 | dst.width = stream->timing.h_addressable; | |
2324 | dst.height = stream->timing.v_addressable; | |
2325 | ||
f4791779 HW |
2326 | if (dm_state) { |
2327 | rmx_type = dm_state->scaling; | |
2328 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { | |
2329 | if (src.width * dst.height < | |
2330 | src.height * dst.width) { | |
2331 | /* height needs less upscaling/more downscaling */ | |
2332 | dst.width = src.width * | |
2333 | dst.height / src.height; | |
2334 | } else { | |
2335 | /* width needs less upscaling/more downscaling */ | |
2336 | dst.height = src.height * | |
2337 | dst.width / src.width; | |
2338 | } | |
2339 | } else if (rmx_type == RMX_CENTER) { | |
2340 | dst = src; | |
e7b07cee | 2341 | } |
e7b07cee | 2342 | |
f4791779 HW |
2343 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
2344 | dst.y = (stream->timing.v_addressable - dst.height) / 2; | |
e7b07cee | 2345 | |
f4791779 HW |
2346 | if (dm_state->underscan_enable) { |
2347 | dst.x += dm_state->underscan_hborder / 2; | |
2348 | dst.y += dm_state->underscan_vborder / 2; | |
2349 | dst.width -= dm_state->underscan_hborder; | |
2350 | dst.height -= dm_state->underscan_vborder; | |
2351 | } | |
e7b07cee HW |
2352 | } |
2353 | ||
2354 | stream->src = src; | |
2355 | stream->dst = dst; | |
2356 | ||
f1ad2f5e | 2357 | DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", |
e7b07cee HW |
2358 | dst.x, dst.y, dst.width, dst.height); |
2359 | ||
2360 | } | |
2361 | ||
3ee6b26b AD |
2362 | static enum dc_color_depth |
2363 | convert_color_depth_from_display_info(const struct drm_connector *connector) | |
e7b07cee HW |
2364 | { |
2365 | uint32_t bpc = connector->display_info.bpc; | |
2366 | ||
e7b07cee HW |
2367 | switch (bpc) { |
2368 | case 0: | |
1f6010a9 DF |
2369 | /* |
2370 | * Temporary Work around, DRM doesn't parse color depth for | |
e7b07cee HW |
2371 | * EDID revision before 1.4 |
2372 | * TODO: Fix edid parsing | |
2373 | */ | |
2374 | return COLOR_DEPTH_888; | |
2375 | case 6: | |
2376 | return COLOR_DEPTH_666; | |
2377 | case 8: | |
2378 | return COLOR_DEPTH_888; | |
2379 | case 10: | |
2380 | return COLOR_DEPTH_101010; | |
2381 | case 12: | |
2382 | return COLOR_DEPTH_121212; | |
2383 | case 14: | |
2384 | return COLOR_DEPTH_141414; | |
2385 | case 16: | |
2386 | return COLOR_DEPTH_161616; | |
2387 | default: | |
2388 | return COLOR_DEPTH_UNDEFINED; | |
2389 | } | |
2390 | } | |
2391 | ||
3ee6b26b AD |
2392 | static enum dc_aspect_ratio |
2393 | get_aspect_ratio(const struct drm_display_mode *mode_in) | |
e7b07cee | 2394 | { |
e11d4147 LSL |
2395 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
2396 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; | |
e7b07cee HW |
2397 | } |
2398 | ||
3ee6b26b AD |
2399 | static enum dc_color_space |
2400 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) | |
e7b07cee HW |
2401 | { |
2402 | enum dc_color_space color_space = COLOR_SPACE_SRGB; | |
2403 | ||
2404 | switch (dc_crtc_timing->pixel_encoding) { | |
2405 | case PIXEL_ENCODING_YCBCR422: | |
2406 | case PIXEL_ENCODING_YCBCR444: | |
2407 | case PIXEL_ENCODING_YCBCR420: | |
2408 | { | |
2409 | /* | |
2410 | * 27030khz is the separation point between HDTV and SDTV | |
2411 | * according to HDMI spec, we use YCbCr709 and YCbCr601 | |
2412 | * respectively | |
2413 | */ | |
2414 | if (dc_crtc_timing->pix_clk_khz > 27030) { | |
2415 | if (dc_crtc_timing->flags.Y_ONLY) | |
2416 | color_space = | |
2417 | COLOR_SPACE_YCBCR709_LIMITED; | |
2418 | else | |
2419 | color_space = COLOR_SPACE_YCBCR709; | |
2420 | } else { | |
2421 | if (dc_crtc_timing->flags.Y_ONLY) | |
2422 | color_space = | |
2423 | COLOR_SPACE_YCBCR601_LIMITED; | |
2424 | else | |
2425 | color_space = COLOR_SPACE_YCBCR601; | |
2426 | } | |
2427 | ||
2428 | } | |
2429 | break; | |
2430 | case PIXEL_ENCODING_RGB: | |
2431 | color_space = COLOR_SPACE_SRGB; | |
2432 | break; | |
2433 | ||
2434 | default: | |
2435 | WARN_ON(1); | |
2436 | break; | |
2437 | } | |
2438 | ||
2439 | return color_space; | |
2440 | } | |
2441 | ||
400443e8 ML |
2442 | static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) |
2443 | { | |
2444 | if (timing_out->display_color_depth <= COLOR_DEPTH_888) | |
2445 | return; | |
2446 | ||
2447 | timing_out->display_color_depth--; | |
2448 | } | |
2449 | ||
2450 | static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, | |
2451 | const struct drm_display_info *info) | |
2452 | { | |
2453 | int normalized_clk; | |
2454 | if (timing_out->display_color_depth <= COLOR_DEPTH_888) | |
2455 | return; | |
2456 | do { | |
2457 | normalized_clk = timing_out->pix_clk_khz; | |
2458 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ | |
2459 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) | |
2460 | normalized_clk /= 2; | |
2461 | /* Adjusting pix clock following on HDMI spec based on colour depth */ | |
2462 | switch (timing_out->display_color_depth) { | |
2463 | case COLOR_DEPTH_101010: | |
2464 | normalized_clk = (normalized_clk * 30) / 24; | |
2465 | break; | |
2466 | case COLOR_DEPTH_121212: | |
2467 | normalized_clk = (normalized_clk * 36) / 24; | |
2468 | break; | |
2469 | case COLOR_DEPTH_161616: | |
2470 | normalized_clk = (normalized_clk * 48) / 24; | |
2471 | break; | |
2472 | default: | |
2473 | return; | |
2474 | } | |
2475 | if (normalized_clk <= info->max_tmds_clock) | |
2476 | return; | |
2477 | reduce_mode_colour_depth(timing_out); | |
2478 | ||
2479 | } while (timing_out->display_color_depth > COLOR_DEPTH_888); | |
2480 | ||
2481 | } | |
e7b07cee | 2482 | |
3ee6b26b AD |
2483 | static void |
2484 | fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, | |
2485 | const struct drm_display_mode *mode_in, | |
2486 | const struct drm_connector *connector) | |
e7b07cee HW |
2487 | { |
2488 | struct dc_crtc_timing *timing_out = &stream->timing; | |
fe61a2f1 | 2489 | const struct drm_display_info *info = &connector->display_info; |
b830ebc9 | 2490 | |
e7b07cee HW |
2491 | memset(timing_out, 0, sizeof(struct dc_crtc_timing)); |
2492 | ||
2493 | timing_out->h_border_left = 0; | |
2494 | timing_out->h_border_right = 0; | |
2495 | timing_out->v_border_top = 0; | |
2496 | timing_out->v_border_bottom = 0; | |
2497 | /* TODO: un-hardcode */ | |
fe61a2f1 ML |
2498 | if (drm_mode_is_420_only(info, mode_in) |
2499 | && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) | |
2500 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; | |
2501 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) | |
e7b07cee HW |
2502 | && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) |
2503 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; | |
2504 | else | |
2505 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; | |
2506 | ||
2507 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; | |
2508 | timing_out->display_color_depth = convert_color_depth_from_display_info( | |
2509 | connector); | |
2510 | timing_out->scan_type = SCANNING_TYPE_NODATA; | |
2511 | timing_out->hdmi_vic = 0; | |
2512 | timing_out->vic = drm_match_cea_mode(mode_in); | |
2513 | ||
2514 | timing_out->h_addressable = mode_in->crtc_hdisplay; | |
2515 | timing_out->h_total = mode_in->crtc_htotal; | |
2516 | timing_out->h_sync_width = | |
2517 | mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; | |
2518 | timing_out->h_front_porch = | |
2519 | mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; | |
2520 | timing_out->v_total = mode_in->crtc_vtotal; | |
2521 | timing_out->v_addressable = mode_in->crtc_vdisplay; | |
2522 | timing_out->v_front_porch = | |
2523 | mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; | |
2524 | timing_out->v_sync_width = | |
2525 | mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; | |
2526 | timing_out->pix_clk_khz = mode_in->crtc_clock; | |
2527 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); | |
2528 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) | |
2529 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; | |
2530 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) | |
2531 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; | |
2532 | ||
2533 | stream->output_color_space = get_output_color_space(timing_out); | |
2534 | ||
e43a432c AK |
2535 | stream->out_transfer_func->type = TF_TYPE_PREDEFINED; |
2536 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; | |
400443e8 ML |
2537 | if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) |
2538 | adjust_colour_depth_from_display_info(timing_out, info); | |
e7b07cee HW |
2539 | } |
2540 | ||
3ee6b26b AD |
2541 | static void fill_audio_info(struct audio_info *audio_info, |
2542 | const struct drm_connector *drm_connector, | |
2543 | const struct dc_sink *dc_sink) | |
e7b07cee HW |
2544 | { |
2545 | int i = 0; | |
2546 | int cea_revision = 0; | |
2547 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; | |
2548 | ||
2549 | audio_info->manufacture_id = edid_caps->manufacturer_id; | |
2550 | audio_info->product_id = edid_caps->product_id; | |
2551 | ||
2552 | cea_revision = drm_connector->display_info.cea_rev; | |
2553 | ||
d2b2562c TSD |
2554 | strncpy(audio_info->display_name, |
2555 | edid_caps->display_name, | |
2556 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); | |
e7b07cee | 2557 | |
b830ebc9 | 2558 | if (cea_revision >= 3) { |
e7b07cee HW |
2559 | audio_info->mode_count = edid_caps->audio_mode_count; |
2560 | ||
2561 | for (i = 0; i < audio_info->mode_count; ++i) { | |
2562 | audio_info->modes[i].format_code = | |
2563 | (enum audio_format_code) | |
2564 | (edid_caps->audio_modes[i].format_code); | |
2565 | audio_info->modes[i].channel_count = | |
2566 | edid_caps->audio_modes[i].channel_count; | |
2567 | audio_info->modes[i].sample_rates.all = | |
2568 | edid_caps->audio_modes[i].sample_rate; | |
2569 | audio_info->modes[i].sample_size = | |
2570 | edid_caps->audio_modes[i].sample_size; | |
2571 | } | |
2572 | } | |
2573 | ||
2574 | audio_info->flags.all = edid_caps->speaker_flags; | |
2575 | ||
2576 | /* TODO: We only check for the progressive mode, check for interlace mode too */ | |
b830ebc9 | 2577 | if (drm_connector->latency_present[0]) { |
e7b07cee HW |
2578 | audio_info->video_latency = drm_connector->video_latency[0]; |
2579 | audio_info->audio_latency = drm_connector->audio_latency[0]; | |
2580 | } | |
2581 | ||
2582 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ | |
2583 | ||
2584 | } | |
2585 | ||
3ee6b26b AD |
2586 | static void |
2587 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, | |
2588 | struct drm_display_mode *dst_mode) | |
e7b07cee HW |
2589 | { |
2590 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; | |
2591 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; | |
2592 | dst_mode->crtc_clock = src_mode->crtc_clock; | |
2593 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; | |
2594 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; | |
b830ebc9 | 2595 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
e7b07cee HW |
2596 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
2597 | dst_mode->crtc_htotal = src_mode->crtc_htotal; | |
2598 | dst_mode->crtc_hskew = src_mode->crtc_hskew; | |
2599 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; | |
2600 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; | |
2601 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; | |
2602 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; | |
2603 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; | |
2604 | } | |
2605 | ||
3ee6b26b AD |
2606 | static void |
2607 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, | |
2608 | const struct drm_display_mode *native_mode, | |
2609 | bool scale_enabled) | |
e7b07cee HW |
2610 | { |
2611 | if (scale_enabled) { | |
2612 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
2613 | } else if (native_mode->clock == drm_mode->clock && | |
2614 | native_mode->htotal == drm_mode->htotal && | |
2615 | native_mode->vtotal == drm_mode->vtotal) { | |
2616 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); | |
2617 | } else { | |
2618 | /* no scaling nor amdgpu inserted, no need to patch */ | |
2619 | } | |
2620 | } | |
2621 | ||
aed15309 ML |
2622 | static struct dc_sink * |
2623 | create_fake_sink(struct amdgpu_dm_connector *aconnector) | |
2e0ac3d6 | 2624 | { |
2e0ac3d6 | 2625 | struct dc_sink_init_data sink_init_data = { 0 }; |
aed15309 | 2626 | struct dc_sink *sink = NULL; |
2e0ac3d6 HW |
2627 | sink_init_data.link = aconnector->dc_link; |
2628 | sink_init_data.sink_signal = aconnector->dc_link->connector_signal; | |
2629 | ||
2630 | sink = dc_sink_create(&sink_init_data); | |
423788c7 | 2631 | if (!sink) { |
2e0ac3d6 | 2632 | DRM_ERROR("Failed to create sink!\n"); |
aed15309 | 2633 | return NULL; |
423788c7 | 2634 | } |
2e0ac3d6 | 2635 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
423788c7 | 2636 | |
aed15309 | 2637 | return sink; |
2e0ac3d6 HW |
2638 | } |
2639 | ||
fa2123db ML |
2640 | static void set_multisync_trigger_params( |
2641 | struct dc_stream_state *stream) | |
2642 | { | |
2643 | if (stream->triggered_crtc_reset.enabled) { | |
2644 | stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; | |
2645 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; | |
2646 | } | |
2647 | } | |
2648 | ||
2649 | static void set_master_stream(struct dc_stream_state *stream_set[], | |
2650 | int stream_count) | |
2651 | { | |
2652 | int j, highest_rfr = 0, master_stream = 0; | |
2653 | ||
2654 | for (j = 0; j < stream_count; j++) { | |
2655 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { | |
2656 | int refresh_rate = 0; | |
2657 | ||
2658 | refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/ | |
2659 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); | |
2660 | if (refresh_rate > highest_rfr) { | |
2661 | highest_rfr = refresh_rate; | |
2662 | master_stream = j; | |
2663 | } | |
2664 | } | |
2665 | } | |
2666 | for (j = 0; j < stream_count; j++) { | |
03736f4c | 2667 | if (stream_set[j]) |
fa2123db ML |
2668 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
2669 | } | |
2670 | } | |
2671 | ||
2672 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) | |
2673 | { | |
2674 | int i = 0; | |
2675 | ||
2676 | if (context->stream_count < 2) | |
2677 | return; | |
2678 | for (i = 0; i < context->stream_count ; i++) { | |
2679 | if (!context->streams[i]) | |
2680 | continue; | |
1f6010a9 DF |
2681 | /* |
2682 | * TODO: add a function to read AMD VSDB bits and set | |
fa2123db | 2683 | * crtc_sync_master.multi_sync_enabled flag |
1f6010a9 | 2684 | * For now it's set to false |
fa2123db ML |
2685 | */ |
2686 | set_multisync_trigger_params(context->streams[i]); | |
2687 | } | |
2688 | set_master_stream(context->streams, context->stream_count); | |
2689 | } | |
2690 | ||
3ee6b26b AD |
2691 | static struct dc_stream_state * |
2692 | create_stream_for_sink(struct amdgpu_dm_connector *aconnector, | |
2693 | const struct drm_display_mode *drm_mode, | |
2694 | const struct dm_connector_state *dm_state) | |
e7b07cee HW |
2695 | { |
2696 | struct drm_display_mode *preferred_mode = NULL; | |
391ef035 | 2697 | struct drm_connector *drm_connector; |
0971c40e | 2698 | struct dc_stream_state *stream = NULL; |
e7b07cee HW |
2699 | struct drm_display_mode mode = *drm_mode; |
2700 | bool native_mode_found = false; | |
aed15309 | 2701 | struct dc_sink *sink = NULL; |
b830ebc9 | 2702 | if (aconnector == NULL) { |
e7b07cee | 2703 | DRM_ERROR("aconnector is NULL!\n"); |
64245fa7 | 2704 | return stream; |
e7b07cee HW |
2705 | } |
2706 | ||
e7b07cee | 2707 | drm_connector = &aconnector->base; |
2e0ac3d6 | 2708 | |
f4ac176e JZ |
2709 | if (!aconnector->dc_sink) { |
2710 | /* | |
391ef035 JFZ |
2711 | * Create dc_sink when necessary to MST |
2712 | * Don't apply fake_sink to MST | |
f4ac176e | 2713 | */ |
391ef035 JFZ |
2714 | if (aconnector->mst_port) { |
2715 | dm_dp_mst_dc_sink_create(drm_connector); | |
64245fa7 | 2716 | return stream; |
391ef035 | 2717 | } |
f4ac176e | 2718 | |
aed15309 ML |
2719 | sink = create_fake_sink(aconnector); |
2720 | if (!sink) | |
64245fa7 | 2721 | return stream; |
aed15309 ML |
2722 | } else { |
2723 | sink = aconnector->dc_sink; | |
f4ac176e | 2724 | } |
2e0ac3d6 | 2725 | |
aed15309 | 2726 | stream = dc_create_stream_for_sink(sink); |
4562236b | 2727 | |
b830ebc9 | 2728 | if (stream == NULL) { |
e7b07cee | 2729 | DRM_ERROR("Failed to create stream for sink!\n"); |
aed15309 | 2730 | goto finish; |
e7b07cee HW |
2731 | } |
2732 | ||
2733 | list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { | |
2734 | /* Search for preferred mode */ | |
2735 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { | |
2736 | native_mode_found = true; | |
2737 | break; | |
2738 | } | |
2739 | } | |
2740 | if (!native_mode_found) | |
2741 | preferred_mode = list_first_entry_or_null( | |
2742 | &aconnector->base.modes, | |
2743 | struct drm_display_mode, | |
2744 | head); | |
2745 | ||
b830ebc9 | 2746 | if (preferred_mode == NULL) { |
1f6010a9 DF |
2747 | /* |
2748 | * This may not be an error, the use case is when we have no | |
e7b07cee HW |
2749 | * usermode calls to reset and set mode upon hotplug. In this |
2750 | * case, we call set mode ourselves to restore the previous mode | |
2751 | * and the modelist may not be filled in in time. | |
2752 | */ | |
f1ad2f5e | 2753 | DRM_DEBUG_DRIVER("No preferred mode found\n"); |
e7b07cee HW |
2754 | } else { |
2755 | decide_crtc_timing_for_drm_display_mode( | |
2756 | &mode, preferred_mode, | |
f4791779 | 2757 | dm_state ? (dm_state->scaling != RMX_OFF) : false); |
e7b07cee HW |
2758 | } |
2759 | ||
f783577c JFZ |
2760 | if (!dm_state) |
2761 | drm_mode_set_crtcinfo(&mode, 0); | |
2762 | ||
e7b07cee HW |
2763 | fill_stream_properties_from_drm_display_mode(stream, |
2764 | &mode, &aconnector->base); | |
2765 | update_stream_scaling_settings(&mode, dm_state, stream); | |
2766 | ||
2767 | fill_audio_info( | |
2768 | &stream->audio_info, | |
2769 | drm_connector, | |
aed15309 | 2770 | sink); |
e7b07cee | 2771 | |
9182b4cb HW |
2772 | update_stream_signal(stream); |
2773 | ||
9e3efe3e HW |
2774 | if (dm_state && dm_state->freesync_capable) |
2775 | stream->ignore_msa_timing_param = true; | |
aed15309 | 2776 | finish: |
fbbdadf2 | 2777 | if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL && aconnector->base.force != DRM_FORCE_ON) |
aed15309 | 2778 | dc_sink_release(sink); |
9e3efe3e | 2779 | |
e7b07cee HW |
2780 | return stream; |
2781 | } | |
2782 | ||
7578ecda | 2783 | static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) |
e7b07cee HW |
2784 | { |
2785 | drm_crtc_cleanup(crtc); | |
2786 | kfree(crtc); | |
2787 | } | |
2788 | ||
2789 | static void dm_crtc_destroy_state(struct drm_crtc *crtc, | |
3ee6b26b | 2790 | struct drm_crtc_state *state) |
e7b07cee HW |
2791 | { |
2792 | struct dm_crtc_state *cur = to_dm_crtc_state(state); | |
2793 | ||
2794 | /* TODO Destroy dc_stream objects are stream object is flattened */ | |
2795 | if (cur->stream) | |
2796 | dc_stream_release(cur->stream); | |
2797 | ||
2798 | ||
2799 | __drm_atomic_helper_crtc_destroy_state(state); | |
2800 | ||
2801 | ||
2802 | kfree(state); | |
2803 | } | |
2804 | ||
2805 | static void dm_crtc_reset_state(struct drm_crtc *crtc) | |
2806 | { | |
2807 | struct dm_crtc_state *state; | |
2808 | ||
2809 | if (crtc->state) | |
2810 | dm_crtc_destroy_state(crtc, crtc->state); | |
2811 | ||
2812 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
2813 | if (WARN_ON(!state)) | |
2814 | return; | |
2815 | ||
2816 | crtc->state = &state->base; | |
2817 | crtc->state->crtc = crtc; | |
2818 | ||
2819 | } | |
2820 | ||
2821 | static struct drm_crtc_state * | |
2822 | dm_crtc_duplicate_state(struct drm_crtc *crtc) | |
2823 | { | |
2824 | struct dm_crtc_state *state, *cur; | |
2825 | ||
2826 | cur = to_dm_crtc_state(crtc->state); | |
2827 | ||
2828 | if (WARN_ON(!crtc->state)) | |
2829 | return NULL; | |
2830 | ||
2004f45e | 2831 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
2a55f096 ES |
2832 | if (!state) |
2833 | return NULL; | |
e7b07cee HW |
2834 | |
2835 | __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); | |
2836 | ||
2837 | if (cur->stream) { | |
2838 | state->stream = cur->stream; | |
2839 | dc_stream_retain(state->stream); | |
2840 | } | |
2841 | ||
98e6436d AK |
2842 | state->adjust = cur->adjust; |
2843 | state->vrr_infopacket = cur->vrr_infopacket; | |
2844 | state->freesync_enabled = cur->freesync_enabled; | |
2845 | ||
e7b07cee HW |
2846 | /* TODO Duplicate dc_stream after objects are stream object is flattened */ |
2847 | ||
2848 | return &state->base; | |
2849 | } | |
2850 | ||
589d2739 HW |
2851 | |
2852 | static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) | |
2853 | { | |
2854 | enum dc_irq_source irq_source; | |
2855 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
2856 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
2857 | ||
2858 | irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; | |
a0e30392 | 2859 | return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; |
589d2739 HW |
2860 | } |
2861 | ||
2862 | static int dm_enable_vblank(struct drm_crtc *crtc) | |
2863 | { | |
2864 | return dm_set_vblank(crtc, true); | |
2865 | } | |
2866 | ||
2867 | static void dm_disable_vblank(struct drm_crtc *crtc) | |
2868 | { | |
2869 | dm_set_vblank(crtc, false); | |
2870 | } | |
2871 | ||
e7b07cee HW |
2872 | /* Implemented only the options currently availible for the driver */ |
2873 | static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { | |
2874 | .reset = dm_crtc_reset_state, | |
2875 | .destroy = amdgpu_dm_crtc_destroy, | |
2876 | .gamma_set = drm_atomic_helper_legacy_gamma_set, | |
2877 | .set_config = drm_atomic_helper_set_config, | |
2878 | .page_flip = drm_atomic_helper_page_flip, | |
2879 | .atomic_duplicate_state = dm_crtc_duplicate_state, | |
2880 | .atomic_destroy_state = dm_crtc_destroy_state, | |
31aec354 | 2881 | .set_crc_source = amdgpu_dm_crtc_set_crc_source, |
3b3b8448 | 2882 | .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, |
589d2739 HW |
2883 | .enable_vblank = dm_enable_vblank, |
2884 | .disable_vblank = dm_disable_vblank, | |
e7b07cee HW |
2885 | }; |
2886 | ||
2887 | static enum drm_connector_status | |
2888 | amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) | |
2889 | { | |
2890 | bool connected; | |
c84dec2f | 2891 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee | 2892 | |
1f6010a9 DF |
2893 | /* |
2894 | * Notes: | |
e7b07cee HW |
2895 | * 1. This interface is NOT called in context of HPD irq. |
2896 | * 2. This interface *is called* in context of user-mode ioctl. Which | |
1f6010a9 DF |
2897 | * makes it a bad place for *any* MST-related activity. |
2898 | */ | |
e7b07cee | 2899 | |
8580d60b HW |
2900 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && |
2901 | !aconnector->fake_enable) | |
e7b07cee HW |
2902 | connected = (aconnector->dc_sink != NULL); |
2903 | else | |
2904 | connected = (aconnector->base.force == DRM_FORCE_ON); | |
2905 | ||
2906 | return (connected ? connector_status_connected : | |
2907 | connector_status_disconnected); | |
2908 | } | |
2909 | ||
3ee6b26b AD |
2910 | int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, |
2911 | struct drm_connector_state *connector_state, | |
2912 | struct drm_property *property, | |
2913 | uint64_t val) | |
e7b07cee HW |
2914 | { |
2915 | struct drm_device *dev = connector->dev; | |
2916 | struct amdgpu_device *adev = dev->dev_private; | |
2917 | struct dm_connector_state *dm_old_state = | |
2918 | to_dm_connector_state(connector->state); | |
2919 | struct dm_connector_state *dm_new_state = | |
2920 | to_dm_connector_state(connector_state); | |
2921 | ||
2922 | int ret = -EINVAL; | |
2923 | ||
2924 | if (property == dev->mode_config.scaling_mode_property) { | |
2925 | enum amdgpu_rmx_type rmx_type; | |
2926 | ||
2927 | switch (val) { | |
2928 | case DRM_MODE_SCALE_CENTER: | |
2929 | rmx_type = RMX_CENTER; | |
2930 | break; | |
2931 | case DRM_MODE_SCALE_ASPECT: | |
2932 | rmx_type = RMX_ASPECT; | |
2933 | break; | |
2934 | case DRM_MODE_SCALE_FULLSCREEN: | |
2935 | rmx_type = RMX_FULL; | |
2936 | break; | |
2937 | case DRM_MODE_SCALE_NONE: | |
2938 | default: | |
2939 | rmx_type = RMX_OFF; | |
2940 | break; | |
2941 | } | |
2942 | ||
2943 | if (dm_old_state->scaling == rmx_type) | |
2944 | return 0; | |
2945 | ||
2946 | dm_new_state->scaling = rmx_type; | |
2947 | ret = 0; | |
2948 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
2949 | dm_new_state->underscan_hborder = val; | |
2950 | ret = 0; | |
2951 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
2952 | dm_new_state->underscan_vborder = val; | |
2953 | ret = 0; | |
2954 | } else if (property == adev->mode_info.underscan_property) { | |
2955 | dm_new_state->underscan_enable = val; | |
2956 | ret = 0; | |
2957 | } | |
2958 | ||
2959 | return ret; | |
2960 | } | |
2961 | ||
3ee6b26b AD |
2962 | int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, |
2963 | const struct drm_connector_state *state, | |
2964 | struct drm_property *property, | |
2965 | uint64_t *val) | |
e7b07cee HW |
2966 | { |
2967 | struct drm_device *dev = connector->dev; | |
2968 | struct amdgpu_device *adev = dev->dev_private; | |
2969 | struct dm_connector_state *dm_state = | |
2970 | to_dm_connector_state(state); | |
2971 | int ret = -EINVAL; | |
2972 | ||
2973 | if (property == dev->mode_config.scaling_mode_property) { | |
2974 | switch (dm_state->scaling) { | |
2975 | case RMX_CENTER: | |
2976 | *val = DRM_MODE_SCALE_CENTER; | |
2977 | break; | |
2978 | case RMX_ASPECT: | |
2979 | *val = DRM_MODE_SCALE_ASPECT; | |
2980 | break; | |
2981 | case RMX_FULL: | |
2982 | *val = DRM_MODE_SCALE_FULLSCREEN; | |
2983 | break; | |
2984 | case RMX_OFF: | |
2985 | default: | |
2986 | *val = DRM_MODE_SCALE_NONE; | |
2987 | break; | |
2988 | } | |
2989 | ret = 0; | |
2990 | } else if (property == adev->mode_info.underscan_hborder_property) { | |
2991 | *val = dm_state->underscan_hborder; | |
2992 | ret = 0; | |
2993 | } else if (property == adev->mode_info.underscan_vborder_property) { | |
2994 | *val = dm_state->underscan_vborder; | |
2995 | ret = 0; | |
2996 | } else if (property == adev->mode_info.underscan_property) { | |
2997 | *val = dm_state->underscan_enable; | |
2998 | ret = 0; | |
2999 | } | |
3000 | return ret; | |
3001 | } | |
3002 | ||
7578ecda | 3003 | static void amdgpu_dm_connector_destroy(struct drm_connector *connector) |
e7b07cee | 3004 | { |
c84dec2f | 3005 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
3006 | const struct dc_link *link = aconnector->dc_link; |
3007 | struct amdgpu_device *adev = connector->dev->dev_private; | |
3008 | struct amdgpu_display_manager *dm = &adev->dm; | |
ada8ce15 | 3009 | |
e7b07cee HW |
3010 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ |
3011 | defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) | |
3012 | ||
89fc8d4e | 3013 | if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && |
5cd29ed0 HW |
3014 | link->type != dc_connection_none && |
3015 | dm->backlight_dev) { | |
3016 | backlight_device_unregister(dm->backlight_dev); | |
3017 | dm->backlight_dev = NULL; | |
e7b07cee HW |
3018 | } |
3019 | #endif | |
e86e8947 | 3020 | drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); |
e7b07cee HW |
3021 | drm_connector_unregister(connector); |
3022 | drm_connector_cleanup(connector); | |
3023 | kfree(connector); | |
3024 | } | |
3025 | ||
3026 | void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) | |
3027 | { | |
3028 | struct dm_connector_state *state = | |
3029 | to_dm_connector_state(connector->state); | |
3030 | ||
df099b9b LSL |
3031 | if (connector->state) |
3032 | __drm_atomic_helper_connector_destroy_state(connector->state); | |
3033 | ||
e7b07cee HW |
3034 | kfree(state); |
3035 | ||
3036 | state = kzalloc(sizeof(*state), GFP_KERNEL); | |
3037 | ||
3038 | if (state) { | |
3039 | state->scaling = RMX_OFF; | |
3040 | state->underscan_enable = false; | |
3041 | state->underscan_hborder = 0; | |
3042 | state->underscan_vborder = 0; | |
3043 | ||
df099b9b | 3044 | __drm_atomic_helper_connector_reset(connector, &state->base); |
e7b07cee HW |
3045 | } |
3046 | } | |
3047 | ||
3ee6b26b AD |
3048 | struct drm_connector_state * |
3049 | amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) | |
e7b07cee HW |
3050 | { |
3051 | struct dm_connector_state *state = | |
3052 | to_dm_connector_state(connector->state); | |
3053 | ||
3054 | struct dm_connector_state *new_state = | |
3055 | kmemdup(state, sizeof(*state), GFP_KERNEL); | |
3056 | ||
98e6436d AK |
3057 | if (!new_state) |
3058 | return NULL; | |
e7b07cee | 3059 | |
98e6436d AK |
3060 | __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); |
3061 | ||
3062 | new_state->freesync_capable = state->freesync_capable; | |
3063 | new_state->freesync_enable = state->freesync_enable; | |
3064 | ||
3065 | return &new_state->base; | |
e7b07cee HW |
3066 | } |
3067 | ||
3068 | static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { | |
3069 | .reset = amdgpu_dm_connector_funcs_reset, | |
3070 | .detect = amdgpu_dm_connector_detect, | |
3071 | .fill_modes = drm_helper_probe_single_connector_modes, | |
3072 | .destroy = amdgpu_dm_connector_destroy, | |
3073 | .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, | |
3074 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
3075 | .atomic_set_property = amdgpu_dm_connector_atomic_set_property, | |
3076 | .atomic_get_property = amdgpu_dm_connector_atomic_get_property | |
3077 | }; | |
3078 | ||
e7b07cee HW |
3079 | static int get_modes(struct drm_connector *connector) |
3080 | { | |
3081 | return amdgpu_dm_connector_get_modes(connector); | |
3082 | } | |
3083 | ||
c84dec2f | 3084 | static void create_eml_sink(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
3085 | { |
3086 | struct dc_sink_init_data init_params = { | |
3087 | .link = aconnector->dc_link, | |
3088 | .sink_signal = SIGNAL_TYPE_VIRTUAL | |
3089 | }; | |
70e8ffc5 | 3090 | struct edid *edid; |
e7b07cee | 3091 | |
a89ff457 | 3092 | if (!aconnector->base.edid_blob_ptr) { |
e7b07cee HW |
3093 | DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", |
3094 | aconnector->base.name); | |
3095 | ||
3096 | aconnector->base.force = DRM_FORCE_OFF; | |
3097 | aconnector->base.override_edid = false; | |
3098 | return; | |
3099 | } | |
3100 | ||
70e8ffc5 HW |
3101 | edid = (struct edid *) aconnector->base.edid_blob_ptr->data; |
3102 | ||
e7b07cee HW |
3103 | aconnector->edid = edid; |
3104 | ||
3105 | aconnector->dc_em_sink = dc_link_add_remote_sink( | |
3106 | aconnector->dc_link, | |
3107 | (uint8_t *)edid, | |
3108 | (edid->extensions + 1) * EDID_LENGTH, | |
3109 | &init_params); | |
3110 | ||
a68d90e7 | 3111 | if (aconnector->base.force == DRM_FORCE_ON) |
e7b07cee HW |
3112 | aconnector->dc_sink = aconnector->dc_link->local_sink ? |
3113 | aconnector->dc_link->local_sink : | |
3114 | aconnector->dc_em_sink; | |
3115 | } | |
3116 | ||
c84dec2f | 3117 | static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) |
e7b07cee HW |
3118 | { |
3119 | struct dc_link *link = (struct dc_link *)aconnector->dc_link; | |
3120 | ||
1f6010a9 DF |
3121 | /* |
3122 | * In case of headless boot with force on for DP managed connector | |
e7b07cee HW |
3123 | * Those settings have to be != 0 to get initial modeset |
3124 | */ | |
3125 | if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { | |
3126 | link->verified_link_cap.lane_count = LANE_COUNT_FOUR; | |
3127 | link->verified_link_cap.link_rate = LINK_RATE_HIGH2; | |
3128 | } | |
3129 | ||
3130 | ||
3131 | aconnector->base.override_edid = true; | |
3132 | create_eml_sink(aconnector); | |
3133 | } | |
3134 | ||
ba9ca088 | 3135 | enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, |
3ee6b26b | 3136 | struct drm_display_mode *mode) |
e7b07cee HW |
3137 | { |
3138 | int result = MODE_ERROR; | |
3139 | struct dc_sink *dc_sink; | |
3140 | struct amdgpu_device *adev = connector->dev->dev_private; | |
3141 | /* TODO: Unhardcode stream count */ | |
0971c40e | 3142 | struct dc_stream_state *stream; |
c84dec2f | 3143 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
a39438f0 | 3144 | enum dc_status dc_result = DC_OK; |
e7b07cee HW |
3145 | |
3146 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
3147 | (mode->flags & DRM_MODE_FLAG_DBLSCAN)) | |
3148 | return result; | |
3149 | ||
1f6010a9 DF |
3150 | /* |
3151 | * Only run this the first time mode_valid is called to initilialize | |
e7b07cee HW |
3152 | * EDID mgmt |
3153 | */ | |
3154 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && | |
3155 | !aconnector->dc_em_sink) | |
3156 | handle_edid_mgmt(aconnector); | |
3157 | ||
c84dec2f | 3158 | dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; |
e7b07cee | 3159 | |
b830ebc9 | 3160 | if (dc_sink == NULL) { |
e7b07cee HW |
3161 | DRM_ERROR("dc_sink is NULL!\n"); |
3162 | goto fail; | |
3163 | } | |
3164 | ||
f4791779 | 3165 | stream = create_stream_for_sink(aconnector, mode, NULL); |
b830ebc9 | 3166 | if (stream == NULL) { |
e7b07cee HW |
3167 | DRM_ERROR("Failed to create stream for sink!\n"); |
3168 | goto fail; | |
3169 | } | |
3170 | ||
a39438f0 HW |
3171 | dc_result = dc_validate_stream(adev->dm.dc, stream); |
3172 | ||
3173 | if (dc_result == DC_OK) | |
e7b07cee | 3174 | result = MODE_OK; |
a39438f0 | 3175 | else |
9f921b14 | 3176 | DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n", |
a39438f0 HW |
3177 | mode->vdisplay, |
3178 | mode->hdisplay, | |
9f921b14 HW |
3179 | mode->clock, |
3180 | dc_result); | |
e7b07cee HW |
3181 | |
3182 | dc_stream_release(stream); | |
3183 | ||
3184 | fail: | |
3185 | /* TODO: error handling*/ | |
3186 | return result; | |
3187 | } | |
3188 | ||
3189 | static const struct drm_connector_helper_funcs | |
3190 | amdgpu_dm_connector_helper_funcs = { | |
3191 | /* | |
1f6010a9 | 3192 | * If hotplugging a second bigger display in FB Con mode, bigger resolution |
b830ebc9 | 3193 | * modes will be filtered by drm_mode_validate_size(), and those modes |
1f6010a9 | 3194 | * are missing after user start lightdm. So we need to renew modes list. |
b830ebc9 HW |
3195 | * in get_modes call back, not just return the modes count |
3196 | */ | |
e7b07cee HW |
3197 | .get_modes = get_modes, |
3198 | .mode_valid = amdgpu_dm_connector_mode_valid, | |
a487411a | 3199 | .best_encoder = drm_atomic_helper_best_encoder |
e7b07cee HW |
3200 | }; |
3201 | ||
3202 | static void dm_crtc_helper_disable(struct drm_crtc *crtc) | |
3203 | { | |
3204 | } | |
3205 | ||
3ee6b26b AD |
3206 | static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, |
3207 | struct drm_crtc_state *state) | |
e7b07cee HW |
3208 | { |
3209 | struct amdgpu_device *adev = crtc->dev->dev_private; | |
3210 | struct dc *dc = adev->dm.dc; | |
3211 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); | |
3212 | int ret = -EINVAL; | |
3213 | ||
9b690ef3 BL |
3214 | if (unlikely(!dm_crtc_state->stream && |
3215 | modeset_required(state, NULL, dm_crtc_state->stream))) { | |
e7b07cee HW |
3216 | WARN_ON(1); |
3217 | return ret; | |
3218 | } | |
3219 | ||
1f6010a9 | 3220 | /* In some use cases, like reset, no stream is attached */ |
e7b07cee HW |
3221 | if (!dm_crtc_state->stream) |
3222 | return 0; | |
3223 | ||
62c933f9 | 3224 | if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) |
e7b07cee HW |
3225 | return 0; |
3226 | ||
3227 | return ret; | |
3228 | } | |
3229 | ||
3ee6b26b AD |
3230 | static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, |
3231 | const struct drm_display_mode *mode, | |
3232 | struct drm_display_mode *adjusted_mode) | |
e7b07cee HW |
3233 | { |
3234 | return true; | |
3235 | } | |
3236 | ||
3237 | static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { | |
3238 | .disable = dm_crtc_helper_disable, | |
3239 | .atomic_check = dm_crtc_helper_atomic_check, | |
3240 | .mode_fixup = dm_crtc_helper_mode_fixup | |
3241 | }; | |
3242 | ||
3243 | static void dm_encoder_helper_disable(struct drm_encoder *encoder) | |
3244 | { | |
3245 | ||
3246 | } | |
3247 | ||
3ee6b26b AD |
3248 | static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, |
3249 | struct drm_crtc_state *crtc_state, | |
3250 | struct drm_connector_state *conn_state) | |
e7b07cee HW |
3251 | { |
3252 | return 0; | |
3253 | } | |
3254 | ||
3255 | const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { | |
3256 | .disable = dm_encoder_helper_disable, | |
3257 | .atomic_check = dm_encoder_helper_atomic_check | |
3258 | }; | |
3259 | ||
3260 | static void dm_drm_plane_reset(struct drm_plane *plane) | |
3261 | { | |
3262 | struct dm_plane_state *amdgpu_state = NULL; | |
3263 | ||
3264 | if (plane->state) | |
3265 | plane->funcs->atomic_destroy_state(plane, plane->state); | |
3266 | ||
3267 | amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); | |
f922237d | 3268 | WARN_ON(amdgpu_state == NULL); |
1f6010a9 | 3269 | |
e7b07cee HW |
3270 | if (amdgpu_state) { |
3271 | plane->state = &amdgpu_state->base; | |
3272 | plane->state->plane = plane; | |
3273 | plane->state->rotation = DRM_MODE_ROTATE_0; | |
f922237d | 3274 | } |
e7b07cee HW |
3275 | } |
3276 | ||
3277 | static struct drm_plane_state * | |
3278 | dm_drm_plane_duplicate_state(struct drm_plane *plane) | |
3279 | { | |
3280 | struct dm_plane_state *dm_plane_state, *old_dm_plane_state; | |
3281 | ||
3282 | old_dm_plane_state = to_dm_plane_state(plane->state); | |
3283 | dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); | |
3284 | if (!dm_plane_state) | |
3285 | return NULL; | |
3286 | ||
3287 | __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); | |
3288 | ||
3be5262e HW |
3289 | if (old_dm_plane_state->dc_state) { |
3290 | dm_plane_state->dc_state = old_dm_plane_state->dc_state; | |
3291 | dc_plane_state_retain(dm_plane_state->dc_state); | |
e7b07cee HW |
3292 | } |
3293 | ||
3294 | return &dm_plane_state->base; | |
3295 | } | |
3296 | ||
3297 | void dm_drm_plane_destroy_state(struct drm_plane *plane, | |
3ee6b26b | 3298 | struct drm_plane_state *state) |
e7b07cee HW |
3299 | { |
3300 | struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); | |
3301 | ||
3be5262e HW |
3302 | if (dm_plane_state->dc_state) |
3303 | dc_plane_state_release(dm_plane_state->dc_state); | |
e7b07cee | 3304 | |
0627bbd3 | 3305 | drm_atomic_helper_plane_destroy_state(plane, state); |
e7b07cee HW |
3306 | } |
3307 | ||
3308 | static const struct drm_plane_funcs dm_plane_funcs = { | |
3309 | .update_plane = drm_atomic_helper_update_plane, | |
3310 | .disable_plane = drm_atomic_helper_disable_plane, | |
3311 | .destroy = drm_plane_cleanup, | |
3312 | .reset = dm_drm_plane_reset, | |
3313 | .atomic_duplicate_state = dm_drm_plane_duplicate_state, | |
3314 | .atomic_destroy_state = dm_drm_plane_destroy_state, | |
3315 | }; | |
3316 | ||
3ee6b26b AD |
3317 | static int dm_plane_helper_prepare_fb(struct drm_plane *plane, |
3318 | struct drm_plane_state *new_state) | |
e7b07cee HW |
3319 | { |
3320 | struct amdgpu_framebuffer *afb; | |
3321 | struct drm_gem_object *obj; | |
5d43be0c | 3322 | struct amdgpu_device *adev; |
e7b07cee | 3323 | struct amdgpu_bo *rbo; |
56087b31 | 3324 | uint64_t chroma_addr = 0; |
e7b07cee HW |
3325 | struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; |
3326 | unsigned int awidth; | |
5d43be0c CK |
3327 | uint32_t domain; |
3328 | int r; | |
e7b07cee HW |
3329 | |
3330 | dm_plane_state_old = to_dm_plane_state(plane->state); | |
3331 | dm_plane_state_new = to_dm_plane_state(new_state); | |
3332 | ||
3333 | if (!new_state->fb) { | |
f1ad2f5e | 3334 | DRM_DEBUG_DRIVER("No FB bound\n"); |
e7b07cee HW |
3335 | return 0; |
3336 | } | |
3337 | ||
3338 | afb = to_amdgpu_framebuffer(new_state->fb); | |
e68d14dd | 3339 | obj = new_state->fb->obj[0]; |
e7b07cee | 3340 | rbo = gem_to_amdgpu_bo(obj); |
5d43be0c | 3341 | adev = amdgpu_ttm_adev(rbo->tbo.bdev); |
e7b07cee HW |
3342 | r = amdgpu_bo_reserve(rbo, false); |
3343 | if (unlikely(r != 0)) | |
3344 | return r; | |
3345 | ||
5d43be0c | 3346 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
1d2361e5 | 3347 | domain = amdgpu_display_supported_domains(adev); |
5d43be0c CK |
3348 | else |
3349 | domain = AMDGPU_GEM_DOMAIN_VRAM; | |
e7b07cee | 3350 | |
7b7c6c81 | 3351 | r = amdgpu_bo_pin(rbo, domain); |
e7b07cee | 3352 | if (unlikely(r != 0)) { |
30b7c614 HW |
3353 | if (r != -ERESTARTSYS) |
3354 | DRM_ERROR("Failed to pin framebuffer with error %d\n", r); | |
bb812f1e | 3355 | amdgpu_bo_unreserve(rbo); |
e7b07cee HW |
3356 | return r; |
3357 | } | |
3358 | ||
bb812f1e JZ |
3359 | r = amdgpu_ttm_alloc_gart(&rbo->tbo); |
3360 | if (unlikely(r != 0)) { | |
3361 | amdgpu_bo_unpin(rbo); | |
3362 | amdgpu_bo_unreserve(rbo); | |
3363 | DRM_ERROR("%p bind failed\n", rbo); | |
e7b07cee HW |
3364 | return r; |
3365 | } | |
bb812f1e JZ |
3366 | amdgpu_bo_unreserve(rbo); |
3367 | ||
7b7c6c81 | 3368 | afb->address = amdgpu_bo_gpu_offset(rbo); |
e7b07cee HW |
3369 | |
3370 | amdgpu_bo_ref(rbo); | |
3371 | ||
3be5262e HW |
3372 | if (dm_plane_state_new->dc_state && |
3373 | dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { | |
3374 | struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; | |
e7b07cee | 3375 | |
3be5262e HW |
3376 | if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { |
3377 | plane_state->address.grph.addr.low_part = lower_32_bits(afb->address); | |
3378 | plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); | |
e7b07cee HW |
3379 | } else { |
3380 | awidth = ALIGN(new_state->fb->width, 64); | |
56087b31 | 3381 | plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; |
3be5262e | 3382 | plane_state->address.video_progressive.luma_addr.low_part |
e7b07cee | 3383 | = lower_32_bits(afb->address); |
56087b31 S |
3384 | plane_state->address.video_progressive.luma_addr.high_part |
3385 | = upper_32_bits(afb->address); | |
35888630 | 3386 | chroma_addr = afb->address + (u64)awidth * new_state->fb->height; |
3be5262e | 3387 | plane_state->address.video_progressive.chroma_addr.low_part |
56087b31 S |
3388 | = lower_32_bits(chroma_addr); |
3389 | plane_state->address.video_progressive.chroma_addr.high_part | |
3390 | = upper_32_bits(chroma_addr); | |
e7b07cee HW |
3391 | } |
3392 | } | |
3393 | ||
e7b07cee HW |
3394 | return 0; |
3395 | } | |
3396 | ||
3ee6b26b AD |
3397 | static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, |
3398 | struct drm_plane_state *old_state) | |
e7b07cee HW |
3399 | { |
3400 | struct amdgpu_bo *rbo; | |
e7b07cee HW |
3401 | int r; |
3402 | ||
3403 | if (!old_state->fb) | |
3404 | return; | |
3405 | ||
e68d14dd | 3406 | rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); |
e7b07cee HW |
3407 | r = amdgpu_bo_reserve(rbo, false); |
3408 | if (unlikely(r)) { | |
3409 | DRM_ERROR("failed to reserve rbo before unpin\n"); | |
3410 | return; | |
b830ebc9 HW |
3411 | } |
3412 | ||
3413 | amdgpu_bo_unpin(rbo); | |
3414 | amdgpu_bo_unreserve(rbo); | |
3415 | amdgpu_bo_unref(&rbo); | |
e7b07cee HW |
3416 | } |
3417 | ||
7578ecda AD |
3418 | static int dm_plane_atomic_check(struct drm_plane *plane, |
3419 | struct drm_plane_state *state) | |
cbd19488 AG |
3420 | { |
3421 | struct amdgpu_device *adev = plane->dev->dev_private; | |
3422 | struct dc *dc = adev->dm.dc; | |
3423 | struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); | |
3424 | ||
3be5262e | 3425 | if (!dm_plane_state->dc_state) |
9a3329b1 | 3426 | return 0; |
cbd19488 | 3427 | |
a05bcff1 S |
3428 | if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state)) |
3429 | return -EINVAL; | |
3430 | ||
62c933f9 | 3431 | if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) |
cbd19488 AG |
3432 | return 0; |
3433 | ||
3434 | return -EINVAL; | |
3435 | } | |
3436 | ||
e7b07cee HW |
3437 | static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { |
3438 | .prepare_fb = dm_plane_helper_prepare_fb, | |
3439 | .cleanup_fb = dm_plane_helper_cleanup_fb, | |
cbd19488 | 3440 | .atomic_check = dm_plane_atomic_check, |
e7b07cee HW |
3441 | }; |
3442 | ||
3443 | /* | |
3444 | * TODO: these are currently initialized to rgb formats only. | |
3445 | * For future use cases we should either initialize them dynamically based on | |
3446 | * plane capabilities, or initialize this array to all formats, so internal drm | |
1f6010a9 | 3447 | * check will succeed, and let DC implement proper check |
e7b07cee | 3448 | */ |
d90371b0 | 3449 | static const uint32_t rgb_formats[] = { |
e7b07cee HW |
3450 | DRM_FORMAT_RGB888, |
3451 | DRM_FORMAT_XRGB8888, | |
3452 | DRM_FORMAT_ARGB8888, | |
3453 | DRM_FORMAT_RGBA8888, | |
3454 | DRM_FORMAT_XRGB2101010, | |
3455 | DRM_FORMAT_XBGR2101010, | |
3456 | DRM_FORMAT_ARGB2101010, | |
3457 | DRM_FORMAT_ABGR2101010, | |
bcd47f60 MR |
3458 | DRM_FORMAT_XBGR8888, |
3459 | DRM_FORMAT_ABGR8888, | |
e7b07cee HW |
3460 | }; |
3461 | ||
99d1abf8 | 3462 | static const uint32_t yuv_formats[] = { |
e7b07cee HW |
3463 | DRM_FORMAT_NV12, |
3464 | DRM_FORMAT_NV21, | |
3465 | }; | |
3466 | ||
3467 | static const u32 cursor_formats[] = { | |
3468 | DRM_FORMAT_ARGB8888 | |
3469 | }; | |
3470 | ||
7578ecda AD |
3471 | static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, |
3472 | struct amdgpu_plane *aplane, | |
3473 | unsigned long possible_crtcs) | |
e7b07cee HW |
3474 | { |
3475 | int res = -EPERM; | |
3476 | ||
3477 | switch (aplane->base.type) { | |
3478 | case DRM_PLANE_TYPE_PRIMARY: | |
e7b07cee HW |
3479 | res = drm_universal_plane_init( |
3480 | dm->adev->ddev, | |
3481 | &aplane->base, | |
3482 | possible_crtcs, | |
3483 | &dm_plane_funcs, | |
3484 | rgb_formats, | |
3485 | ARRAY_SIZE(rgb_formats), | |
3486 | NULL, aplane->base.type, NULL); | |
3487 | break; | |
3488 | case DRM_PLANE_TYPE_OVERLAY: | |
3489 | res = drm_universal_plane_init( | |
3490 | dm->adev->ddev, | |
3491 | &aplane->base, | |
3492 | possible_crtcs, | |
3493 | &dm_plane_funcs, | |
3494 | yuv_formats, | |
3495 | ARRAY_SIZE(yuv_formats), | |
3496 | NULL, aplane->base.type, NULL); | |
3497 | break; | |
3498 | case DRM_PLANE_TYPE_CURSOR: | |
3499 | res = drm_universal_plane_init( | |
3500 | dm->adev->ddev, | |
3501 | &aplane->base, | |
3502 | possible_crtcs, | |
3503 | &dm_plane_funcs, | |
3504 | cursor_formats, | |
3505 | ARRAY_SIZE(cursor_formats), | |
3506 | NULL, aplane->base.type, NULL); | |
3507 | break; | |
3508 | } | |
3509 | ||
3510 | drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); | |
3511 | ||
96719c54 HW |
3512 | /* Create (reset) the plane state */ |
3513 | if (aplane->base.funcs->reset) | |
3514 | aplane->base.funcs->reset(&aplane->base); | |
3515 | ||
3516 | ||
e7b07cee HW |
3517 | return res; |
3518 | } | |
3519 | ||
7578ecda AD |
3520 | static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, |
3521 | struct drm_plane *plane, | |
3522 | uint32_t crtc_index) | |
e7b07cee HW |
3523 | { |
3524 | struct amdgpu_crtc *acrtc = NULL; | |
3525 | struct amdgpu_plane *cursor_plane; | |
3526 | ||
3527 | int res = -ENOMEM; | |
3528 | ||
3529 | cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); | |
3530 | if (!cursor_plane) | |
3531 | goto fail; | |
3532 | ||
3533 | cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR; | |
3534 | res = amdgpu_dm_plane_init(dm, cursor_plane, 0); | |
3535 | ||
3536 | acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); | |
3537 | if (!acrtc) | |
3538 | goto fail; | |
3539 | ||
3540 | res = drm_crtc_init_with_planes( | |
3541 | dm->ddev, | |
3542 | &acrtc->base, | |
3543 | plane, | |
3544 | &cursor_plane->base, | |
3545 | &amdgpu_dm_crtc_funcs, NULL); | |
3546 | ||
3547 | if (res) | |
3548 | goto fail; | |
3549 | ||
3550 | drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); | |
3551 | ||
96719c54 HW |
3552 | /* Create (reset) the plane state */ |
3553 | if (acrtc->base.funcs->reset) | |
3554 | acrtc->base.funcs->reset(&acrtc->base); | |
3555 | ||
e7b07cee HW |
3556 | acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; |
3557 | acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; | |
3558 | ||
3559 | acrtc->crtc_id = crtc_index; | |
3560 | acrtc->base.enabled = false; | |
c37e2d29 | 3561 | acrtc->otg_inst = -1; |
e7b07cee HW |
3562 | |
3563 | dm->adev->mode_info.crtcs[crtc_index] = acrtc; | |
236d0e4f LSL |
3564 | drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES, |
3565 | true, MAX_COLOR_LUT_ENTRIES); | |
086247a4 | 3566 | drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); |
e7b07cee HW |
3567 | |
3568 | return 0; | |
3569 | ||
3570 | fail: | |
b830ebc9 HW |
3571 | kfree(acrtc); |
3572 | kfree(cursor_plane); | |
e7b07cee HW |
3573 | return res; |
3574 | } | |
3575 | ||
3576 | ||
3577 | static int to_drm_connector_type(enum signal_type st) | |
3578 | { | |
3579 | switch (st) { | |
3580 | case SIGNAL_TYPE_HDMI_TYPE_A: | |
3581 | return DRM_MODE_CONNECTOR_HDMIA; | |
3582 | case SIGNAL_TYPE_EDP: | |
3583 | return DRM_MODE_CONNECTOR_eDP; | |
11c3ee48 AD |
3584 | case SIGNAL_TYPE_LVDS: |
3585 | return DRM_MODE_CONNECTOR_LVDS; | |
e7b07cee HW |
3586 | case SIGNAL_TYPE_RGB: |
3587 | return DRM_MODE_CONNECTOR_VGA; | |
3588 | case SIGNAL_TYPE_DISPLAY_PORT: | |
3589 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |
3590 | return DRM_MODE_CONNECTOR_DisplayPort; | |
3591 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |
3592 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |
3593 | return DRM_MODE_CONNECTOR_DVID; | |
3594 | case SIGNAL_TYPE_VIRTUAL: | |
3595 | return DRM_MODE_CONNECTOR_VIRTUAL; | |
3596 | ||
3597 | default: | |
3598 | return DRM_MODE_CONNECTOR_Unknown; | |
3599 | } | |
3600 | } | |
3601 | ||
3602 | static void amdgpu_dm_get_native_mode(struct drm_connector *connector) | |
3603 | { | |
3604 | const struct drm_connector_helper_funcs *helper = | |
3605 | connector->helper_private; | |
3606 | struct drm_encoder *encoder; | |
3607 | struct amdgpu_encoder *amdgpu_encoder; | |
3608 | ||
3609 | encoder = helper->best_encoder(connector); | |
3610 | ||
3611 | if (encoder == NULL) | |
3612 | return; | |
3613 | ||
3614 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3615 | ||
3616 | amdgpu_encoder->native_mode.clock = 0; | |
3617 | ||
3618 | if (!list_empty(&connector->probed_modes)) { | |
3619 | struct drm_display_mode *preferred_mode = NULL; | |
b830ebc9 | 3620 | |
e7b07cee | 3621 | list_for_each_entry(preferred_mode, |
b830ebc9 HW |
3622 | &connector->probed_modes, |
3623 | head) { | |
3624 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) | |
3625 | amdgpu_encoder->native_mode = *preferred_mode; | |
3626 | ||
e7b07cee HW |
3627 | break; |
3628 | } | |
3629 | ||
3630 | } | |
3631 | } | |
3632 | ||
3ee6b26b AD |
3633 | static struct drm_display_mode * |
3634 | amdgpu_dm_create_common_mode(struct drm_encoder *encoder, | |
3635 | char *name, | |
3636 | int hdisplay, int vdisplay) | |
e7b07cee HW |
3637 | { |
3638 | struct drm_device *dev = encoder->dev; | |
3639 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3640 | struct drm_display_mode *mode = NULL; | |
3641 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
3642 | ||
3643 | mode = drm_mode_duplicate(dev, native_mode); | |
3644 | ||
b830ebc9 | 3645 | if (mode == NULL) |
e7b07cee HW |
3646 | return NULL; |
3647 | ||
3648 | mode->hdisplay = hdisplay; | |
3649 | mode->vdisplay = vdisplay; | |
3650 | mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
3651 | strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); | |
3652 | ||
3653 | return mode; | |
3654 | ||
3655 | } | |
3656 | ||
3657 | static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, | |
3ee6b26b | 3658 | struct drm_connector *connector) |
e7b07cee HW |
3659 | { |
3660 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); | |
3661 | struct drm_display_mode *mode = NULL; | |
3662 | struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; | |
c84dec2f HW |
3663 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
3664 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
3665 | int i; |
3666 | int n; | |
3667 | struct mode_size { | |
3668 | char name[DRM_DISPLAY_MODE_LEN]; | |
3669 | int w; | |
3670 | int h; | |
b830ebc9 | 3671 | } common_modes[] = { |
e7b07cee HW |
3672 | { "640x480", 640, 480}, |
3673 | { "800x600", 800, 600}, | |
3674 | { "1024x768", 1024, 768}, | |
3675 | { "1280x720", 1280, 720}, | |
3676 | { "1280x800", 1280, 800}, | |
3677 | {"1280x1024", 1280, 1024}, | |
3678 | { "1440x900", 1440, 900}, | |
3679 | {"1680x1050", 1680, 1050}, | |
3680 | {"1600x1200", 1600, 1200}, | |
3681 | {"1920x1080", 1920, 1080}, | |
3682 | {"1920x1200", 1920, 1200} | |
3683 | }; | |
3684 | ||
b830ebc9 | 3685 | n = ARRAY_SIZE(common_modes); |
e7b07cee HW |
3686 | |
3687 | for (i = 0; i < n; i++) { | |
3688 | struct drm_display_mode *curmode = NULL; | |
3689 | bool mode_existed = false; | |
3690 | ||
3691 | if (common_modes[i].w > native_mode->hdisplay || | |
b830ebc9 HW |
3692 | common_modes[i].h > native_mode->vdisplay || |
3693 | (common_modes[i].w == native_mode->hdisplay && | |
3694 | common_modes[i].h == native_mode->vdisplay)) | |
3695 | continue; | |
e7b07cee HW |
3696 | |
3697 | list_for_each_entry(curmode, &connector->probed_modes, head) { | |
3698 | if (common_modes[i].w == curmode->hdisplay && | |
b830ebc9 | 3699 | common_modes[i].h == curmode->vdisplay) { |
e7b07cee HW |
3700 | mode_existed = true; |
3701 | break; | |
3702 | } | |
3703 | } | |
3704 | ||
3705 | if (mode_existed) | |
3706 | continue; | |
3707 | ||
3708 | mode = amdgpu_dm_create_common_mode(encoder, | |
3709 | common_modes[i].name, common_modes[i].w, | |
3710 | common_modes[i].h); | |
3711 | drm_mode_probed_add(connector, mode); | |
c84dec2f | 3712 | amdgpu_dm_connector->num_modes++; |
e7b07cee HW |
3713 | } |
3714 | } | |
3715 | ||
3ee6b26b AD |
3716 | static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, |
3717 | struct edid *edid) | |
e7b07cee | 3718 | { |
c84dec2f HW |
3719 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
3720 | to_amdgpu_dm_connector(connector); | |
e7b07cee HW |
3721 | |
3722 | if (edid) { | |
3723 | /* empty probed_modes */ | |
3724 | INIT_LIST_HEAD(&connector->probed_modes); | |
c84dec2f | 3725 | amdgpu_dm_connector->num_modes = |
e7b07cee HW |
3726 | drm_add_edid_modes(connector, edid); |
3727 | ||
e7b07cee | 3728 | amdgpu_dm_get_native_mode(connector); |
a8d8d3dc | 3729 | } else { |
c84dec2f | 3730 | amdgpu_dm_connector->num_modes = 0; |
a8d8d3dc | 3731 | } |
e7b07cee HW |
3732 | } |
3733 | ||
7578ecda | 3734 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) |
e7b07cee HW |
3735 | { |
3736 | const struct drm_connector_helper_funcs *helper = | |
3737 | connector->helper_private; | |
c84dec2f HW |
3738 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
3739 | to_amdgpu_dm_connector(connector); | |
e7b07cee | 3740 | struct drm_encoder *encoder; |
c84dec2f | 3741 | struct edid *edid = amdgpu_dm_connector->edid; |
e7b07cee HW |
3742 | |
3743 | encoder = helper->best_encoder(connector); | |
3e332d3a | 3744 | |
85ee15d6 | 3745 | if (!edid || !drm_edid_is_valid(edid)) { |
1b369d3c ML |
3746 | amdgpu_dm_connector->num_modes = |
3747 | drm_add_modes_noedid(connector, 640, 480); | |
85ee15d6 ML |
3748 | } else { |
3749 | amdgpu_dm_connector_ddc_get_modes(connector, edid); | |
3750 | amdgpu_dm_connector_add_common_modes(encoder, connector); | |
3751 | } | |
3e332d3a | 3752 | amdgpu_dm_fbc_init(connector); |
5099114b | 3753 | |
c84dec2f | 3754 | return amdgpu_dm_connector->num_modes; |
e7b07cee HW |
3755 | } |
3756 | ||
3ee6b26b AD |
3757 | void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, |
3758 | struct amdgpu_dm_connector *aconnector, | |
3759 | int connector_type, | |
3760 | struct dc_link *link, | |
3761 | int link_index) | |
e7b07cee HW |
3762 | { |
3763 | struct amdgpu_device *adev = dm->ddev->dev_private; | |
3764 | ||
3765 | aconnector->connector_id = link_index; | |
3766 | aconnector->dc_link = link; | |
3767 | aconnector->base.interlace_allowed = false; | |
3768 | aconnector->base.doublescan_allowed = false; | |
3769 | aconnector->base.stereo_allowed = false; | |
3770 | aconnector->base.dpms = DRM_MODE_DPMS_OFF; | |
3771 | aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ | |
e7b07cee HW |
3772 | mutex_init(&aconnector->hpd_lock); |
3773 | ||
1f6010a9 DF |
3774 | /* |
3775 | * configure support HPD hot plug connector_>polled default value is 0 | |
b830ebc9 HW |
3776 | * which means HPD hot plug not supported |
3777 | */ | |
e7b07cee HW |
3778 | switch (connector_type) { |
3779 | case DRM_MODE_CONNECTOR_HDMIA: | |
3780 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 3781 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 3782 | link->link_enc->features.hdmi_ycbcr420_supported ? true : false; |
e7b07cee HW |
3783 | break; |
3784 | case DRM_MODE_CONNECTOR_DisplayPort: | |
3785 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
e7baae1c | 3786 | aconnector->base.ycbcr_420_allowed = |
9ea59d5a | 3787 | link->link_enc->features.dp_ycbcr420_supported ? true : false; |
e7b07cee HW |
3788 | break; |
3789 | case DRM_MODE_CONNECTOR_DVID: | |
3790 | aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; | |
3791 | break; | |
3792 | default: | |
3793 | break; | |
3794 | } | |
3795 | ||
3796 | drm_object_attach_property(&aconnector->base.base, | |
3797 | dm->ddev->mode_config.scaling_mode_property, | |
3798 | DRM_MODE_SCALE_NONE); | |
3799 | ||
3800 | drm_object_attach_property(&aconnector->base.base, | |
3801 | adev->mode_info.underscan_property, | |
3802 | UNDERSCAN_OFF); | |
3803 | drm_object_attach_property(&aconnector->base.base, | |
3804 | adev->mode_info.underscan_hborder_property, | |
3805 | 0); | |
3806 | drm_object_attach_property(&aconnector->base.base, | |
3807 | adev->mode_info.underscan_vborder_property, | |
3808 | 0); | |
3809 | ||
3810 | } | |
3811 | ||
7578ecda AD |
3812 | static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, |
3813 | struct i2c_msg *msgs, int num) | |
e7b07cee HW |
3814 | { |
3815 | struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); | |
3816 | struct ddc_service *ddc_service = i2c->ddc_service; | |
3817 | struct i2c_command cmd; | |
3818 | int i; | |
3819 | int result = -EIO; | |
3820 | ||
b830ebc9 | 3821 | cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); |
e7b07cee HW |
3822 | |
3823 | if (!cmd.payloads) | |
3824 | return result; | |
3825 | ||
3826 | cmd.number_of_payloads = num; | |
3827 | cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; | |
3828 | cmd.speed = 100; | |
3829 | ||
3830 | for (i = 0; i < num; i++) { | |
3831 | cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); | |
3832 | cmd.payloads[i].address = msgs[i].addr; | |
3833 | cmd.payloads[i].length = msgs[i].len; | |
3834 | cmd.payloads[i].data = msgs[i].buf; | |
3835 | } | |
3836 | ||
c85e6e54 DF |
3837 | if (dc_submit_i2c( |
3838 | ddc_service->ctx->dc, | |
3839 | ddc_service->ddc_pin->hw_info.ddc_channel, | |
e7b07cee HW |
3840 | &cmd)) |
3841 | result = num; | |
3842 | ||
3843 | kfree(cmd.payloads); | |
3844 | return result; | |
3845 | } | |
3846 | ||
7578ecda | 3847 | static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) |
e7b07cee HW |
3848 | { |
3849 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
3850 | } | |
3851 | ||
3852 | static const struct i2c_algorithm amdgpu_dm_i2c_algo = { | |
3853 | .master_xfer = amdgpu_dm_i2c_xfer, | |
3854 | .functionality = amdgpu_dm_i2c_func, | |
3855 | }; | |
3856 | ||
3ee6b26b AD |
3857 | static struct amdgpu_i2c_adapter * |
3858 | create_i2c(struct ddc_service *ddc_service, | |
3859 | int link_index, | |
3860 | int *res) | |
e7b07cee HW |
3861 | { |
3862 | struct amdgpu_device *adev = ddc_service->ctx->driver_context; | |
3863 | struct amdgpu_i2c_adapter *i2c; | |
3864 | ||
b830ebc9 | 3865 | i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); |
2a55f096 ES |
3866 | if (!i2c) |
3867 | return NULL; | |
e7b07cee HW |
3868 | i2c->base.owner = THIS_MODULE; |
3869 | i2c->base.class = I2C_CLASS_DDC; | |
3870 | i2c->base.dev.parent = &adev->pdev->dev; | |
3871 | i2c->base.algo = &amdgpu_dm_i2c_algo; | |
b830ebc9 | 3872 | snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); |
e7b07cee HW |
3873 | i2c_set_adapdata(&i2c->base, i2c); |
3874 | i2c->ddc_service = ddc_service; | |
c85e6e54 | 3875 | i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index; |
e7b07cee HW |
3876 | |
3877 | return i2c; | |
3878 | } | |
3879 | ||
89fc8d4e | 3880 | |
1f6010a9 DF |
3881 | /* |
3882 | * Note: this function assumes that dc_link_detect() was called for the | |
b830ebc9 HW |
3883 | * dc_link which will be represented by this aconnector. |
3884 | */ | |
7578ecda AD |
3885 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
3886 | struct amdgpu_dm_connector *aconnector, | |
3887 | uint32_t link_index, | |
3888 | struct amdgpu_encoder *aencoder) | |
e7b07cee HW |
3889 | { |
3890 | int res = 0; | |
3891 | int connector_type; | |
3892 | struct dc *dc = dm->dc; | |
3893 | struct dc_link *link = dc_get_link_at_index(dc, link_index); | |
3894 | struct amdgpu_i2c_adapter *i2c; | |
9a227d26 TSD |
3895 | |
3896 | link->priv = aconnector; | |
e7b07cee | 3897 | |
f1ad2f5e | 3898 | DRM_DEBUG_DRIVER("%s()\n", __func__); |
e7b07cee HW |
3899 | |
3900 | i2c = create_i2c(link->ddc, link->link_index, &res); | |
2a55f096 ES |
3901 | if (!i2c) { |
3902 | DRM_ERROR("Failed to create i2c adapter data\n"); | |
3903 | return -ENOMEM; | |
3904 | } | |
3905 | ||
e7b07cee HW |
3906 | aconnector->i2c = i2c; |
3907 | res = i2c_add_adapter(&i2c->base); | |
3908 | ||
3909 | if (res) { | |
3910 | DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); | |
3911 | goto out_free; | |
3912 | } | |
3913 | ||
3914 | connector_type = to_drm_connector_type(link->connector_signal); | |
3915 | ||
3916 | res = drm_connector_init( | |
3917 | dm->ddev, | |
3918 | &aconnector->base, | |
3919 | &amdgpu_dm_connector_funcs, | |
3920 | connector_type); | |
3921 | ||
3922 | if (res) { | |
3923 | DRM_ERROR("connector_init failed\n"); | |
3924 | aconnector->connector_id = -1; | |
3925 | goto out_free; | |
3926 | } | |
3927 | ||
3928 | drm_connector_helper_add( | |
3929 | &aconnector->base, | |
3930 | &amdgpu_dm_connector_helper_funcs); | |
3931 | ||
96719c54 HW |
3932 | if (aconnector->base.funcs->reset) |
3933 | aconnector->base.funcs->reset(&aconnector->base); | |
3934 | ||
e7b07cee HW |
3935 | amdgpu_dm_connector_init_helper( |
3936 | dm, | |
3937 | aconnector, | |
3938 | connector_type, | |
3939 | link, | |
3940 | link_index); | |
3941 | ||
cde4c44d | 3942 | drm_connector_attach_encoder( |
e7b07cee HW |
3943 | &aconnector->base, &aencoder->base); |
3944 | ||
3945 | drm_connector_register(&aconnector->base); | |
dc38fd9d DF |
3946 | #if defined(CONFIG_DEBUG_FS) |
3947 | res = connector_debugfs_init(aconnector); | |
3948 | if (res) { | |
3949 | DRM_ERROR("Failed to create debugfs for connector"); | |
3950 | goto out_free; | |
3951 | } | |
3952 | #endif | |
e7b07cee HW |
3953 | |
3954 | if (connector_type == DRM_MODE_CONNECTOR_DisplayPort | |
3955 | || connector_type == DRM_MODE_CONNECTOR_eDP) | |
3956 | amdgpu_dm_initialize_dp_connector(dm, aconnector); | |
3957 | ||
e7b07cee HW |
3958 | out_free: |
3959 | if (res) { | |
3960 | kfree(i2c); | |
3961 | aconnector->i2c = NULL; | |
3962 | } | |
3963 | return res; | |
3964 | } | |
3965 | ||
3966 | int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) | |
3967 | { | |
3968 | switch (adev->mode_info.num_crtc) { | |
3969 | case 1: | |
3970 | return 0x1; | |
3971 | case 2: | |
3972 | return 0x3; | |
3973 | case 3: | |
3974 | return 0x7; | |
3975 | case 4: | |
3976 | return 0xf; | |
3977 | case 5: | |
3978 | return 0x1f; | |
3979 | case 6: | |
3980 | default: | |
3981 | return 0x3f; | |
3982 | } | |
3983 | } | |
3984 | ||
7578ecda AD |
3985 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
3986 | struct amdgpu_encoder *aencoder, | |
3987 | uint32_t link_index) | |
e7b07cee HW |
3988 | { |
3989 | struct amdgpu_device *adev = dev->dev_private; | |
3990 | ||
3991 | int res = drm_encoder_init(dev, | |
3992 | &aencoder->base, | |
3993 | &amdgpu_dm_encoder_funcs, | |
3994 | DRM_MODE_ENCODER_TMDS, | |
3995 | NULL); | |
3996 | ||
3997 | aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); | |
3998 | ||
3999 | if (!res) | |
4000 | aencoder->encoder_id = link_index; | |
4001 | else | |
4002 | aencoder->encoder_id = -1; | |
4003 | ||
4004 | drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); | |
4005 | ||
4006 | return res; | |
4007 | } | |
4008 | ||
3ee6b26b AD |
4009 | static void manage_dm_interrupts(struct amdgpu_device *adev, |
4010 | struct amdgpu_crtc *acrtc, | |
4011 | bool enable) | |
e7b07cee HW |
4012 | { |
4013 | /* | |
4014 | * this is not correct translation but will work as soon as VBLANK | |
4015 | * constant is the same as PFLIP | |
4016 | */ | |
4017 | int irq_type = | |
734dd01d | 4018 | amdgpu_display_crtc_idx_to_irq_type( |
e7b07cee HW |
4019 | adev, |
4020 | acrtc->crtc_id); | |
4021 | ||
4022 | if (enable) { | |
4023 | drm_crtc_vblank_on(&acrtc->base); | |
4024 | amdgpu_irq_get( | |
4025 | adev, | |
4026 | &adev->pageflip_irq, | |
4027 | irq_type); | |
4028 | } else { | |
4029 | ||
4030 | amdgpu_irq_put( | |
4031 | adev, | |
4032 | &adev->pageflip_irq, | |
4033 | irq_type); | |
4034 | drm_crtc_vblank_off(&acrtc->base); | |
4035 | } | |
4036 | } | |
4037 | ||
3ee6b26b AD |
4038 | static bool |
4039 | is_scaling_state_different(const struct dm_connector_state *dm_state, | |
4040 | const struct dm_connector_state *old_dm_state) | |
e7b07cee HW |
4041 | { |
4042 | if (dm_state->scaling != old_dm_state->scaling) | |
4043 | return true; | |
4044 | if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { | |
4045 | if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) | |
4046 | return true; | |
4047 | } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { | |
4048 | if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) | |
4049 | return true; | |
b830ebc9 HW |
4050 | } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || |
4051 | dm_state->underscan_vborder != old_dm_state->underscan_vborder) | |
4052 | return true; | |
e7b07cee HW |
4053 | return false; |
4054 | } | |
4055 | ||
3ee6b26b AD |
4056 | static void remove_stream(struct amdgpu_device *adev, |
4057 | struct amdgpu_crtc *acrtc, | |
4058 | struct dc_stream_state *stream) | |
e7b07cee HW |
4059 | { |
4060 | /* this is the update mode case */ | |
e7b07cee HW |
4061 | |
4062 | acrtc->otg_inst = -1; | |
4063 | acrtc->enabled = false; | |
4064 | } | |
4065 | ||
7578ecda AD |
4066 | static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, |
4067 | struct dc_cursor_position *position) | |
2a8f6ccb | 4068 | { |
f4c2cc43 | 4069 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
2a8f6ccb HW |
4070 | int x, y; |
4071 | int xorigin = 0, yorigin = 0; | |
4072 | ||
4073 | if (!crtc || !plane->state->fb) { | |
4074 | position->enable = false; | |
4075 | position->x = 0; | |
4076 | position->y = 0; | |
4077 | return 0; | |
4078 | } | |
4079 | ||
4080 | if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || | |
4081 | (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { | |
4082 | DRM_ERROR("%s: bad cursor width or height %d x %d\n", | |
4083 | __func__, | |
4084 | plane->state->crtc_w, | |
4085 | plane->state->crtc_h); | |
4086 | return -EINVAL; | |
4087 | } | |
4088 | ||
4089 | x = plane->state->crtc_x; | |
4090 | y = plane->state->crtc_y; | |
4091 | /* avivo cursor are offset into the total surface */ | |
4092 | x += crtc->primary->state->src_x >> 16; | |
4093 | y += crtc->primary->state->src_y >> 16; | |
4094 | if (x < 0) { | |
4095 | xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); | |
4096 | x = 0; | |
4097 | } | |
4098 | if (y < 0) { | |
4099 | yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); | |
4100 | y = 0; | |
4101 | } | |
4102 | position->enable = true; | |
4103 | position->x = x; | |
4104 | position->y = y; | |
4105 | position->x_hotspot = xorigin; | |
4106 | position->y_hotspot = yorigin; | |
4107 | ||
4108 | return 0; | |
4109 | } | |
4110 | ||
3ee6b26b AD |
4111 | static void handle_cursor_update(struct drm_plane *plane, |
4112 | struct drm_plane_state *old_plane_state) | |
e7b07cee | 4113 | { |
2a8f6ccb HW |
4114 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); |
4115 | struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; | |
4116 | struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; | |
4117 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
4118 | uint64_t address = afb ? afb->address : 0; | |
4119 | struct dc_cursor_position position; | |
4120 | struct dc_cursor_attributes attributes; | |
4121 | int ret; | |
4122 | ||
e7b07cee HW |
4123 | if (!plane->state->fb && !old_plane_state->fb) |
4124 | return; | |
4125 | ||
f1ad2f5e | 4126 | DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", |
c12a7ba5 HW |
4127 | __func__, |
4128 | amdgpu_crtc->crtc_id, | |
4129 | plane->state->crtc_w, | |
4130 | plane->state->crtc_h); | |
2a8f6ccb HW |
4131 | |
4132 | ret = get_cursor_position(plane, crtc, &position); | |
4133 | if (ret) | |
4134 | return; | |
4135 | ||
4136 | if (!position.enable) { | |
4137 | /* turn off cursor */ | |
4138 | if (crtc_state && crtc_state->stream) | |
4139 | dc_stream_set_cursor_position(crtc_state->stream, | |
4140 | &position); | |
4141 | return; | |
e7b07cee | 4142 | } |
e7b07cee | 4143 | |
2a8f6ccb HW |
4144 | amdgpu_crtc->cursor_width = plane->state->crtc_w; |
4145 | amdgpu_crtc->cursor_height = plane->state->crtc_h; | |
4146 | ||
4147 | attributes.address.high_part = upper_32_bits(address); | |
4148 | attributes.address.low_part = lower_32_bits(address); | |
4149 | attributes.width = plane->state->crtc_w; | |
4150 | attributes.height = plane->state->crtc_h; | |
4151 | attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; | |
4152 | attributes.rotation_angle = 0; | |
4153 | attributes.attribute_flags.value = 0; | |
4154 | ||
4155 | attributes.pitch = attributes.width; | |
4156 | ||
886daac9 JZ |
4157 | if (crtc_state->stream) { |
4158 | if (!dc_stream_set_cursor_attributes(crtc_state->stream, | |
4159 | &attributes)) | |
4160 | DRM_ERROR("DC failed to set cursor attributes\n"); | |
2a8f6ccb | 4161 | |
2a8f6ccb HW |
4162 | if (!dc_stream_set_cursor_position(crtc_state->stream, |
4163 | &position)) | |
4164 | DRM_ERROR("DC failed to set cursor position\n"); | |
886daac9 | 4165 | } |
2a8f6ccb | 4166 | } |
e7b07cee HW |
4167 | |
4168 | static void prepare_flip_isr(struct amdgpu_crtc *acrtc) | |
4169 | { | |
4170 | ||
4171 | assert_spin_locked(&acrtc->base.dev->event_lock); | |
4172 | WARN_ON(acrtc->event); | |
4173 | ||
4174 | acrtc->event = acrtc->base.state->event; | |
4175 | ||
4176 | /* Set the flip status */ | |
4177 | acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; | |
4178 | ||
4179 | /* Mark this event as consumed */ | |
4180 | acrtc->base.state->event = NULL; | |
4181 | ||
4182 | DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", | |
4183 | acrtc->crtc_id); | |
4184 | } | |
4185 | ||
4186 | /* | |
4187 | * Executes flip | |
4188 | * | |
4189 | * Waits on all BO's fences and for proper vblank count | |
4190 | */ | |
3ee6b26b AD |
4191 | static void amdgpu_dm_do_flip(struct drm_crtc *crtc, |
4192 | struct drm_framebuffer *fb, | |
bc6828e0 BL |
4193 | uint32_t target, |
4194 | struct dc_state *state) | |
e7b07cee HW |
4195 | { |
4196 | unsigned long flags; | |
4197 | uint32_t target_vblank; | |
4198 | int r, vpos, hpos; | |
4199 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); | |
4200 | struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); | |
e68d14dd | 4201 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); |
e7b07cee | 4202 | struct amdgpu_device *adev = crtc->dev->dev_private; |
aac6a07e | 4203 | bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; |
e7b07cee | 4204 | struct dc_flip_addrs addr = { {0} }; |
3be5262e | 4205 | /* TODO eliminate or rename surface_update */ |
e7b07cee HW |
4206 | struct dc_surface_update surface_updates[1] = { {0} }; |
4207 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); | |
d999853e | 4208 | struct dc_stream_status *stream_status; |
e7b07cee HW |
4209 | |
4210 | ||
4211 | /* Prepare wait for target vblank early - before the fence-waits */ | |
23effc11 | 4212 | target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + |
e7b07cee HW |
4213 | amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); |
4214 | ||
1f6010a9 DF |
4215 | /* |
4216 | * TODO This might fail and hence better not used, wait | |
e7b07cee HW |
4217 | * explicitly on fences instead |
4218 | * and in general should be called for | |
4219 | * blocking commit to as per framework helpers | |
b830ebc9 | 4220 | */ |
e7b07cee HW |
4221 | r = amdgpu_bo_reserve(abo, true); |
4222 | if (unlikely(r != 0)) { | |
4223 | DRM_ERROR("failed to reserve buffer before flip\n"); | |
4224 | WARN_ON(1); | |
4225 | } | |
4226 | ||
4227 | /* Wait for all fences on this FB */ | |
4228 | WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, | |
4229 | MAX_SCHEDULE_TIMEOUT) < 0); | |
4230 | ||
4231 | amdgpu_bo_unreserve(abo); | |
4232 | ||
1f6010a9 DF |
4233 | /* |
4234 | * Wait until we're out of the vertical blank period before the one | |
e7b07cee HW |
4235 | * targeted by the flip |
4236 | */ | |
4237 | while ((acrtc->enabled && | |
aa8e286a SL |
4238 | (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, |
4239 | 0, &vpos, &hpos, NULL, | |
4240 | NULL, &crtc->hwmode) | |
e7b07cee HW |
4241 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == |
4242 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
4243 | (int)(target_vblank - | |
4244 | amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) { | |
4245 | usleep_range(1000, 1100); | |
4246 | } | |
4247 | ||
4248 | /* Flip */ | |
4249 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
e7b07cee HW |
4250 | |
4251 | WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); | |
4252 | WARN_ON(!acrtc_state->stream); | |
4253 | ||
4254 | addr.address.grph.addr.low_part = lower_32_bits(afb->address); | |
4255 | addr.address.grph.addr.high_part = upper_32_bits(afb->address); | |
4256 | addr.flip_immediate = async_flip; | |
4257 | ||
4258 | ||
4259 | if (acrtc->base.state->event) | |
4260 | prepare_flip_isr(acrtc); | |
4261 | ||
4de9f38b S |
4262 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
4263 | ||
d999853e NK |
4264 | stream_status = dc_stream_get_status(acrtc_state->stream); |
4265 | if (!stream_status) { | |
4266 | DRM_ERROR("No stream status for CRTC: id=%d\n", | |
4267 | acrtc->crtc_id); | |
4268 | return; | |
4269 | } | |
4270 | ||
4271 | surface_updates->surface = stream_status->plane_states[0]; | |
4272 | if (!surface_updates->surface) { | |
4273 | DRM_ERROR("No surface for CRTC: id=%d\n", | |
4274 | acrtc->crtc_id); | |
4275 | return; | |
4276 | } | |
e7b07cee HW |
4277 | surface_updates->flip_addr = &addr; |
4278 | ||
bc6828e0 BL |
4279 | dc_commit_updates_for_stream(adev->dm.dc, |
4280 | surface_updates, | |
4281 | 1, | |
4282 | acrtc_state->stream, | |
4283 | NULL, | |
4284 | &surface_updates->surface, | |
4285 | state); | |
e7b07cee HW |
4286 | |
4287 | DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", | |
4288 | __func__, | |
4289 | addr.address.grph.addr.high_part, | |
4290 | addr.address.grph.addr.low_part); | |
e7b07cee HW |
4291 | } |
4292 | ||
44d09c6a HW |
4293 | /* |
4294 | * TODO this whole function needs to go | |
4295 | * | |
4296 | * dc_surface_update is needlessly complex. See if we can just replace this | |
4297 | * with a dc_plane_state and follow the atomic model a bit more closely here. | |
4298 | */ | |
4299 | static bool commit_planes_to_stream( | |
4300 | struct dc *dc, | |
4301 | struct dc_plane_state **plane_states, | |
4302 | uint8_t new_plane_count, | |
4303 | struct dm_crtc_state *dm_new_crtc_state, | |
4304 | struct dm_crtc_state *dm_old_crtc_state, | |
4305 | struct dc_state *state) | |
4306 | { | |
4307 | /* no need to dynamically allocate this. it's pretty small */ | |
4308 | struct dc_surface_update updates[MAX_SURFACES]; | |
4309 | struct dc_flip_addrs *flip_addr; | |
4310 | struct dc_plane_info *plane_info; | |
4311 | struct dc_scaling_info *scaling_info; | |
4312 | int i; | |
4313 | struct dc_stream_state *dc_stream = dm_new_crtc_state->stream; | |
4314 | struct dc_stream_update *stream_update = | |
4315 | kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); | |
4316 | ||
4317 | if (!stream_update) { | |
4318 | BREAK_TO_DEBUGGER(); | |
4319 | return false; | |
4320 | } | |
4321 | ||
4322 | flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs), | |
4323 | GFP_KERNEL); | |
4324 | plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info), | |
4325 | GFP_KERNEL); | |
4326 | scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info), | |
4327 | GFP_KERNEL); | |
4328 | ||
4329 | if (!flip_addr || !plane_info || !scaling_info) { | |
4330 | kfree(flip_addr); | |
4331 | kfree(plane_info); | |
4332 | kfree(scaling_info); | |
4333 | kfree(stream_update); | |
4334 | return false; | |
4335 | } | |
4336 | ||
4337 | memset(updates, 0, sizeof(updates)); | |
4338 | ||
4339 | stream_update->src = dc_stream->src; | |
4340 | stream_update->dst = dc_stream->dst; | |
4341 | stream_update->out_transfer_func = dc_stream->out_transfer_func; | |
4342 | ||
98e6436d AK |
4343 | if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) { |
4344 | stream_update->vrr_infopacket = &dc_stream->vrr_infopacket; | |
4345 | stream_update->adjust = &dc_stream->adjust; | |
4346 | } | |
4347 | ||
44d09c6a HW |
4348 | for (i = 0; i < new_plane_count; i++) { |
4349 | updates[i].surface = plane_states[i]; | |
4350 | updates[i].gamma = | |
4351 | (struct dc_gamma *)plane_states[i]->gamma_correction; | |
4352 | updates[i].in_transfer_func = plane_states[i]->in_transfer_func; | |
4353 | flip_addr[i].address = plane_states[i]->address; | |
4354 | flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; | |
4355 | plane_info[i].color_space = plane_states[i]->color_space; | |
44d09c6a HW |
4356 | plane_info[i].format = plane_states[i]->format; |
4357 | plane_info[i].plane_size = plane_states[i]->plane_size; | |
4358 | plane_info[i].rotation = plane_states[i]->rotation; | |
4359 | plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; | |
4360 | plane_info[i].stereo_format = plane_states[i]->stereo_format; | |
4361 | plane_info[i].tiling_info = plane_states[i]->tiling_info; | |
4362 | plane_info[i].visible = plane_states[i]->visible; | |
4363 | plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; | |
4364 | plane_info[i].dcc = plane_states[i]->dcc; | |
4365 | scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; | |
4366 | scaling_info[i].src_rect = plane_states[i]->src_rect; | |
4367 | scaling_info[i].dst_rect = plane_states[i]->dst_rect; | |
4368 | scaling_info[i].clip_rect = plane_states[i]->clip_rect; | |
4369 | ||
4370 | updates[i].flip_addr = &flip_addr[i]; | |
4371 | updates[i].plane_info = &plane_info[i]; | |
4372 | updates[i].scaling_info = &scaling_info[i]; | |
4373 | } | |
4374 | ||
4375 | dc_commit_updates_for_stream( | |
4376 | dc, | |
4377 | updates, | |
4378 | new_plane_count, | |
4379 | dc_stream, stream_update, plane_states, state); | |
4380 | ||
4381 | kfree(flip_addr); | |
4382 | kfree(plane_info); | |
4383 | kfree(scaling_info); | |
4384 | kfree(stream_update); | |
4385 | return true; | |
4386 | } | |
4387 | ||
3be5262e | 4388 | static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, |
3ee6b26b AD |
4389 | struct drm_device *dev, |
4390 | struct amdgpu_display_manager *dm, | |
4391 | struct drm_crtc *pcrtc, | |
4392 | bool *wait_for_vblank) | |
e7b07cee HW |
4393 | { |
4394 | uint32_t i; | |
4395 | struct drm_plane *plane; | |
0bc9706d | 4396 | struct drm_plane_state *old_plane_state, *new_plane_state; |
0971c40e | 4397 | struct dc_stream_state *dc_stream_attach; |
3be5262e | 4398 | struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; |
e7b07cee | 4399 | struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); |
0bc9706d LSL |
4400 | struct drm_crtc_state *new_pcrtc_state = |
4401 | drm_atomic_get_new_crtc_state(state, pcrtc); | |
4402 | struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); | |
44d09c6a HW |
4403 | struct dm_crtc_state *dm_old_crtc_state = |
4404 | to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); | |
bc6828e0 | 4405 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); |
e7b07cee HW |
4406 | int planes_count = 0; |
4407 | unsigned long flags; | |
4408 | ||
4409 | /* update planes when needed */ | |
0bc9706d LSL |
4410 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { |
4411 | struct drm_crtc *crtc = new_plane_state->crtc; | |
f5ba60fe | 4412 | struct drm_crtc_state *new_crtc_state; |
0bc9706d | 4413 | struct drm_framebuffer *fb = new_plane_state->fb; |
e7b07cee | 4414 | bool pflip_needed; |
54d76575 | 4415 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
e7b07cee HW |
4416 | |
4417 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { | |
4418 | handle_cursor_update(plane, old_plane_state); | |
4419 | continue; | |
4420 | } | |
4421 | ||
f5ba60fe DD |
4422 | if (!fb || !crtc || pcrtc != crtc) |
4423 | continue; | |
4424 | ||
4425 | new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); | |
4426 | if (!new_crtc_state->active) | |
e7b07cee HW |
4427 | continue; |
4428 | ||
4429 | pflip_needed = !state->allow_modeset; | |
4430 | ||
4431 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
4432 | if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { | |
3be5262e HW |
4433 | DRM_ERROR("%s: acrtc %d, already busy\n", |
4434 | __func__, | |
4435 | acrtc_attach->crtc_id); | |
b830ebc9 | 4436 | /* In commit tail framework this cannot happen */ |
e7b07cee HW |
4437 | WARN_ON(1); |
4438 | } | |
4439 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
4440 | ||
a2a330ad | 4441 | if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) { |
54d76575 | 4442 | WARN_ON(!dm_new_plane_state->dc_state); |
e7b07cee | 4443 | |
54d76575 | 4444 | plane_states_constructed[planes_count] = dm_new_plane_state->dc_state; |
e7b07cee HW |
4445 | |
4446 | dc_stream_attach = acrtc_state->stream; | |
4447 | planes_count++; | |
4448 | ||
0bc9706d | 4449 | } else if (new_crtc_state->planes_changed) { |
e7b07cee HW |
4450 | /* Assume even ONE crtc with immediate flip means |
4451 | * entire can't wait for VBLANK | |
4452 | * TODO Check if it's correct | |
4453 | */ | |
4454 | *wait_for_vblank = | |
0bc9706d | 4455 | new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? |
e7b07cee HW |
4456 | false : true; |
4457 | ||
4458 | /* TODO: Needs rework for multiplane flip */ | |
4459 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) | |
4460 | drm_crtc_vblank_get(crtc); | |
4461 | ||
4462 | amdgpu_dm_do_flip( | |
4463 | crtc, | |
4464 | fb, | |
23effc11 | 4465 | (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank, |
bc6828e0 | 4466 | dm_state->context); |
e7b07cee HW |
4467 | } |
4468 | ||
4469 | } | |
4470 | ||
4471 | if (planes_count) { | |
4472 | unsigned long flags; | |
4473 | ||
0bc9706d | 4474 | if (new_pcrtc_state->event) { |
e7b07cee HW |
4475 | |
4476 | drm_crtc_vblank_get(pcrtc); | |
4477 | ||
4478 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); | |
4479 | prepare_flip_isr(acrtc_attach); | |
4480 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); | |
4481 | } | |
4482 | ||
98e6436d AK |
4483 | dc_stream_attach->adjust = acrtc_state->adjust; |
4484 | dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket; | |
44d09c6a HW |
4485 | |
4486 | if (false == commit_planes_to_stream(dm->dc, | |
3be5262e HW |
4487 | plane_states_constructed, |
4488 | planes_count, | |
44d09c6a HW |
4489 | acrtc_state, |
4490 | dm_old_crtc_state, | |
bc6828e0 | 4491 | dm_state->context)) |
3be5262e | 4492 | dm_error("%s: Failed to attach plane!\n", __func__); |
e7b07cee HW |
4493 | } else { |
4494 | /*TODO BUG Here should go disable planes on CRTC. */ | |
4495 | } | |
4496 | } | |
4497 | ||
1f6010a9 | 4498 | /* |
27b3f4fc LSL |
4499 | * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC |
4500 | * @crtc_state: the DRM CRTC state | |
4501 | * @stream_state: the DC stream state. | |
4502 | * | |
4503 | * Copy the mirrored transient state flags from DRM, to DC. It is used to bring | |
4504 | * a dc_stream_state's flags in sync with a drm_crtc_state's flags. | |
4505 | */ | |
4506 | static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, | |
4507 | struct dc_stream_state *stream_state) | |
4508 | { | |
4509 | stream_state->mode_changed = crtc_state->mode_changed; | |
4510 | } | |
e7b07cee | 4511 | |
7578ecda AD |
4512 | static int amdgpu_dm_atomic_commit(struct drm_device *dev, |
4513 | struct drm_atomic_state *state, | |
4514 | bool nonblock) | |
e7b07cee HW |
4515 | { |
4516 | struct drm_crtc *crtc; | |
c2cea706 | 4517 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
e7b07cee HW |
4518 | struct amdgpu_device *adev = dev->dev_private; |
4519 | int i; | |
4520 | ||
4521 | /* | |
4522 | * We evade vblanks and pflips on crtc that | |
4523 | * should be changed. We do it here to flush & disable | |
4524 | * interrupts before drm_swap_state is called in drm_atomic_helper_commit | |
4525 | * it will update crtc->dm_crtc_state->stream pointer which is used in | |
4526 | * the ISRs. | |
4527 | */ | |
c2cea706 | 4528 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
54d76575 | 4529 | struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
e7b07cee HW |
4530 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
4531 | ||
54d76575 | 4532 | if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream) |
e7b07cee HW |
4533 | manage_dm_interrupts(adev, acrtc, false); |
4534 | } | |
1f6010a9 DF |
4535 | /* |
4536 | * Add check here for SoC's that support hardware cursor plane, to | |
4537 | * unset legacy_cursor_update | |
4538 | */ | |
e7b07cee HW |
4539 | |
4540 | return drm_atomic_helper_commit(dev, state, nonblock); | |
4541 | ||
4542 | /*TODO Handle EINTR, reenable IRQ*/ | |
4543 | } | |
4544 | ||
7578ecda | 4545 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) |
e7b07cee HW |
4546 | { |
4547 | struct drm_device *dev = state->dev; | |
4548 | struct amdgpu_device *adev = dev->dev_private; | |
4549 | struct amdgpu_display_manager *dm = &adev->dm; | |
4550 | struct dm_atomic_state *dm_state; | |
4551 | uint32_t i, j; | |
5cc6dcbd | 4552 | struct drm_crtc *crtc; |
0bc9706d | 4553 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
e7b07cee HW |
4554 | unsigned long flags; |
4555 | bool wait_for_vblank = true; | |
4556 | struct drm_connector *connector; | |
c2cea706 | 4557 | struct drm_connector_state *old_con_state, *new_con_state; |
54d76575 | 4558 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
fe2a1965 | 4559 | int crtc_disable_count = 0; |
e7b07cee HW |
4560 | |
4561 | drm_atomic_helper_update_legacy_modeset_state(dev, state); | |
4562 | ||
4563 | dm_state = to_dm_atomic_state(state); | |
4564 | ||
4565 | /* update changed items */ | |
0bc9706d | 4566 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
e7b07cee | 4567 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 4568 | |
54d76575 LSL |
4569 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
4570 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
e7b07cee | 4571 | |
f1ad2f5e | 4572 | DRM_DEBUG_DRIVER( |
e7b07cee HW |
4573 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " |
4574 | "planes_changed:%d, mode_changed:%d,active_changed:%d," | |
4575 | "connectors_changed:%d\n", | |
4576 | acrtc->crtc_id, | |
0bc9706d LSL |
4577 | new_crtc_state->enable, |
4578 | new_crtc_state->active, | |
4579 | new_crtc_state->planes_changed, | |
4580 | new_crtc_state->mode_changed, | |
4581 | new_crtc_state->active_changed, | |
4582 | new_crtc_state->connectors_changed); | |
e7b07cee | 4583 | |
27b3f4fc LSL |
4584 | /* Copy all transient state flags into dc state */ |
4585 | if (dm_new_crtc_state->stream) { | |
4586 | amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, | |
4587 | dm_new_crtc_state->stream); | |
4588 | } | |
4589 | ||
e7b07cee HW |
4590 | /* handles headless hotplug case, updating new_state and |
4591 | * aconnector as needed | |
4592 | */ | |
4593 | ||
54d76575 | 4594 | if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { |
e7b07cee | 4595 | |
f1ad2f5e | 4596 | DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee | 4597 | |
54d76575 | 4598 | if (!dm_new_crtc_state->stream) { |
e7b07cee | 4599 | /* |
b830ebc9 HW |
4600 | * this could happen because of issues with |
4601 | * userspace notifications delivery. | |
4602 | * In this case userspace tries to set mode on | |
1f6010a9 DF |
4603 | * display which is disconnected in fact. |
4604 | * dc_sink is NULL in this case on aconnector. | |
b830ebc9 HW |
4605 | * We expect reset mode will come soon. |
4606 | * | |
4607 | * This can also happen when unplug is done | |
4608 | * during resume sequence ended | |
4609 | * | |
4610 | * In this case, we want to pretend we still | |
4611 | * have a sink to keep the pipe running so that | |
4612 | * hw state is consistent with the sw state | |
4613 | */ | |
f1ad2f5e | 4614 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
e7b07cee HW |
4615 | __func__, acrtc->base.base.id); |
4616 | continue; | |
4617 | } | |
4618 | ||
54d76575 LSL |
4619 | if (dm_old_crtc_state->stream) |
4620 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee | 4621 | |
97028037 LP |
4622 | pm_runtime_get_noresume(dev->dev); |
4623 | ||
e7b07cee | 4624 | acrtc->enabled = true; |
0bc9706d LSL |
4625 | acrtc->hw_mode = new_crtc_state->mode; |
4626 | crtc->hwmode = new_crtc_state->mode; | |
4627 | } else if (modereset_required(new_crtc_state)) { | |
f1ad2f5e | 4628 | DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); |
e7b07cee HW |
4629 | |
4630 | /* i.e. reset mode */ | |
54d76575 LSL |
4631 | if (dm_old_crtc_state->stream) |
4632 | remove_stream(adev, acrtc, dm_old_crtc_state->stream); | |
e7b07cee HW |
4633 | } |
4634 | } /* for_each_crtc_in_state() */ | |
4635 | ||
fa2123db ML |
4636 | if (dm_state->context) { |
4637 | dm_enable_per_frame_crtc_master_sync(dm_state->context); | |
608ac7bb | 4638 | WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); |
fa2123db | 4639 | } |
e7b07cee | 4640 | |
0bc9706d | 4641 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 4642 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
b830ebc9 | 4643 | |
54d76575 | 4644 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 4645 | |
54d76575 | 4646 | if (dm_new_crtc_state->stream != NULL) { |
e7b07cee | 4647 | const struct dc_stream_status *status = |
54d76575 | 4648 | dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee HW |
4649 | |
4650 | if (!status) | |
54d76575 | 4651 | DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); |
e7b07cee HW |
4652 | else |
4653 | acrtc->otg_inst = status->primary_otg_inst; | |
4654 | } | |
4655 | } | |
4656 | ||
ebdd27e1 | 4657 | /* Handle scaling and underscan changes*/ |
c2cea706 | 4658 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
4659 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); |
4660 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); | |
4661 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
e7b07cee HW |
4662 | struct dc_stream_status *status = NULL; |
4663 | ||
44d09c6a | 4664 | if (acrtc) { |
0bc9706d | 4665 | new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); |
44d09c6a HW |
4666 | old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); |
4667 | } | |
0bc9706d | 4668 | |
e7b07cee | 4669 | /* Skip any modesets/resets */ |
0bc9706d | 4670 | if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) |
e7b07cee HW |
4671 | continue; |
4672 | ||
1f6010a9 | 4673 | /* Skip anything that is not scaling or underscan changes */ |
54d76575 | 4674 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
e7b07cee HW |
4675 | continue; |
4676 | ||
54d76575 | 4677 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 4678 | |
54d76575 LSL |
4679 | update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, |
4680 | dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); | |
e7b07cee | 4681 | |
70e8ffc5 HW |
4682 | if (!dm_new_crtc_state->stream) |
4683 | continue; | |
4684 | ||
54d76575 | 4685 | status = dc_stream_get_status(dm_new_crtc_state->stream); |
e7b07cee | 4686 | WARN_ON(!status); |
3be5262e | 4687 | WARN_ON(!status->plane_count); |
e7b07cee | 4688 | |
98e6436d AK |
4689 | dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust; |
4690 | dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket; | |
4691 | ||
e7b07cee | 4692 | /*TODO How it works with MPO ?*/ |
44d09c6a | 4693 | if (!commit_planes_to_stream( |
e7b07cee | 4694 | dm->dc, |
3be5262e HW |
4695 | status->plane_states, |
4696 | status->plane_count, | |
44d09c6a HW |
4697 | dm_new_crtc_state, |
4698 | to_dm_crtc_state(old_crtc_state), | |
bc6828e0 | 4699 | dm_state->context)) |
e7b07cee HW |
4700 | dm_error("%s: Failed to update stream scaling!\n", __func__); |
4701 | } | |
4702 | ||
e1fc2dca LSL |
4703 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, |
4704 | new_crtc_state, i) { | |
e7b07cee HW |
4705 | /* |
4706 | * loop to enable interrupts on newly arrived crtc | |
4707 | */ | |
e1fc2dca LSL |
4708 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); |
4709 | bool modeset_needed; | |
b830ebc9 | 4710 | |
fe2a1965 LP |
4711 | if (old_crtc_state->active && !new_crtc_state->active) |
4712 | crtc_disable_count++; | |
4713 | ||
54d76575 | 4714 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e1fc2dca LSL |
4715 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
4716 | modeset_needed = modeset_required( | |
4717 | new_crtc_state, | |
4718 | dm_new_crtc_state->stream, | |
4719 | dm_old_crtc_state->stream); | |
4720 | ||
4721 | if (dm_new_crtc_state->stream == NULL || !modeset_needed) | |
4722 | continue; | |
e7b07cee | 4723 | |
e7b07cee HW |
4724 | manage_dm_interrupts(adev, acrtc, true); |
4725 | } | |
4726 | ||
4727 | /* update planes when needed per crtc*/ | |
5cc6dcbd | 4728 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { |
54d76575 | 4729 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
e7b07cee | 4730 | |
54d76575 | 4731 | if (dm_new_crtc_state->stream) |
5cc6dcbd | 4732 | amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank); |
e7b07cee HW |
4733 | } |
4734 | ||
4735 | ||
4736 | /* | |
4737 | * send vblank event on all events not handled in flip and | |
4738 | * mark consumed event for drm_atomic_helper_commit_hw_done | |
4739 | */ | |
4740 | spin_lock_irqsave(&adev->ddev->event_lock, flags); | |
0bc9706d | 4741 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
e7b07cee | 4742 | |
0bc9706d LSL |
4743 | if (new_crtc_state->event) |
4744 | drm_send_event_locked(dev, &new_crtc_state->event->base); | |
e7b07cee | 4745 | |
0bc9706d | 4746 | new_crtc_state->event = NULL; |
e7b07cee HW |
4747 | } |
4748 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); | |
4749 | ||
e7b07cee HW |
4750 | |
4751 | if (wait_for_vblank) | |
320a1274 | 4752 | drm_atomic_helper_wait_for_flip_done(dev, state); |
e7b07cee | 4753 | |
717276b9 S |
4754 | /* |
4755 | * FIXME: | |
4756 | * Delay hw_done() until flip_done() is signaled. This is to block | |
4757 | * another commit from freeing the CRTC state while we're still | |
4758 | * waiting on flip_done. | |
4759 | */ | |
4760 | drm_atomic_helper_commit_hw_done(state); | |
4761 | ||
e7b07cee | 4762 | drm_atomic_helper_cleanup_planes(dev, state); |
97028037 | 4763 | |
1f6010a9 DF |
4764 | /* |
4765 | * Finally, drop a runtime PM reference for each newly disabled CRTC, | |
97028037 LP |
4766 | * so we can put the GPU into runtime suspend if we're not driving any |
4767 | * displays anymore | |
4768 | */ | |
fe2a1965 LP |
4769 | for (i = 0; i < crtc_disable_count; i++) |
4770 | pm_runtime_put_autosuspend(dev->dev); | |
97028037 | 4771 | pm_runtime_mark_last_busy(dev->dev); |
e7b07cee HW |
4772 | } |
4773 | ||
4774 | ||
4775 | static int dm_force_atomic_commit(struct drm_connector *connector) | |
4776 | { | |
4777 | int ret = 0; | |
4778 | struct drm_device *ddev = connector->dev; | |
4779 | struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); | |
4780 | struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
4781 | struct drm_plane *plane = disconnected_acrtc->base.primary; | |
4782 | struct drm_connector_state *conn_state; | |
4783 | struct drm_crtc_state *crtc_state; | |
4784 | struct drm_plane_state *plane_state; | |
4785 | ||
4786 | if (!state) | |
4787 | return -ENOMEM; | |
4788 | ||
4789 | state->acquire_ctx = ddev->mode_config.acquire_ctx; | |
4790 | ||
4791 | /* Construct an atomic state to restore previous display setting */ | |
4792 | ||
4793 | /* | |
4794 | * Attach connectors to drm_atomic_state | |
4795 | */ | |
4796 | conn_state = drm_atomic_get_connector_state(state, connector); | |
4797 | ||
4798 | ret = PTR_ERR_OR_ZERO(conn_state); | |
4799 | if (ret) | |
4800 | goto err; | |
4801 | ||
4802 | /* Attach crtc to drm_atomic_state*/ | |
4803 | crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); | |
4804 | ||
4805 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
4806 | if (ret) | |
4807 | goto err; | |
4808 | ||
4809 | /* force a restore */ | |
4810 | crtc_state->mode_changed = true; | |
4811 | ||
4812 | /* Attach plane to drm_atomic_state */ | |
4813 | plane_state = drm_atomic_get_plane_state(state, plane); | |
4814 | ||
4815 | ret = PTR_ERR_OR_ZERO(plane_state); | |
4816 | if (ret) | |
4817 | goto err; | |
4818 | ||
4819 | ||
4820 | /* Call commit internally with the state we just constructed */ | |
4821 | ret = drm_atomic_commit(state); | |
4822 | if (!ret) | |
4823 | return 0; | |
4824 | ||
4825 | err: | |
4826 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
4827 | drm_atomic_state_put(state); | |
4828 | ||
4829 | return ret; | |
4830 | } | |
4831 | ||
4832 | /* | |
1f6010a9 DF |
4833 | * This function handles all cases when set mode does not come upon hotplug. |
4834 | * This includes when a display is unplugged then plugged back into the | |
4835 | * same port and when running without usermode desktop manager supprot | |
e7b07cee | 4836 | */ |
3ee6b26b AD |
4837 | void dm_restore_drm_connector_state(struct drm_device *dev, |
4838 | struct drm_connector *connector) | |
e7b07cee | 4839 | { |
c84dec2f | 4840 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); |
e7b07cee HW |
4841 | struct amdgpu_crtc *disconnected_acrtc; |
4842 | struct dm_crtc_state *acrtc_state; | |
4843 | ||
4844 | if (!aconnector->dc_sink || !connector->state || !connector->encoder) | |
4845 | return; | |
4846 | ||
4847 | disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); | |
70e8ffc5 HW |
4848 | if (!disconnected_acrtc) |
4849 | return; | |
e7b07cee | 4850 | |
70e8ffc5 HW |
4851 | acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); |
4852 | if (!acrtc_state->stream) | |
e7b07cee HW |
4853 | return; |
4854 | ||
4855 | /* | |
4856 | * If the previous sink is not released and different from the current, | |
4857 | * we deduce we are in a state where we can not rely on usermode call | |
4858 | * to turn on the display, so we do it here | |
4859 | */ | |
4860 | if (acrtc_state->stream->sink != aconnector->dc_sink) | |
4861 | dm_force_atomic_commit(&aconnector->base); | |
4862 | } | |
4863 | ||
1f6010a9 | 4864 | /* |
e7b07cee HW |
4865 | * Grabs all modesetting locks to serialize against any blocking commits, |
4866 | * Waits for completion of all non blocking commits. | |
4867 | */ | |
3ee6b26b AD |
4868 | static int do_aquire_global_lock(struct drm_device *dev, |
4869 | struct drm_atomic_state *state) | |
e7b07cee HW |
4870 | { |
4871 | struct drm_crtc *crtc; | |
4872 | struct drm_crtc_commit *commit; | |
4873 | long ret; | |
4874 | ||
1f6010a9 DF |
4875 | /* |
4876 | * Adding all modeset locks to aquire_ctx will | |
e7b07cee HW |
4877 | * ensure that when the framework release it the |
4878 | * extra locks we are locking here will get released to | |
4879 | */ | |
4880 | ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); | |
4881 | if (ret) | |
4882 | return ret; | |
4883 | ||
4884 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
4885 | spin_lock(&crtc->commit_lock); | |
4886 | commit = list_first_entry_or_null(&crtc->commit_list, | |
4887 | struct drm_crtc_commit, commit_entry); | |
4888 | if (commit) | |
4889 | drm_crtc_commit_get(commit); | |
4890 | spin_unlock(&crtc->commit_lock); | |
4891 | ||
4892 | if (!commit) | |
4893 | continue; | |
4894 | ||
1f6010a9 DF |
4895 | /* |
4896 | * Make sure all pending HW programming completed and | |
e7b07cee HW |
4897 | * page flips done |
4898 | */ | |
4899 | ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); | |
4900 | ||
4901 | if (ret > 0) | |
4902 | ret = wait_for_completion_interruptible_timeout( | |
4903 | &commit->flip_done, 10*HZ); | |
4904 | ||
4905 | if (ret == 0) | |
4906 | DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " | |
b830ebc9 | 4907 | "timed out\n", crtc->base.id, crtc->name); |
e7b07cee HW |
4908 | |
4909 | drm_crtc_commit_put(commit); | |
4910 | } | |
4911 | ||
4912 | return ret < 0 ? ret : 0; | |
4913 | } | |
4914 | ||
98e6436d AK |
4915 | void set_freesync_on_stream(struct amdgpu_display_manager *dm, |
4916 | struct dm_crtc_state *new_crtc_state, | |
4917 | struct dm_connector_state *new_con_state, | |
4918 | struct dc_stream_state *new_stream) | |
4919 | { | |
4920 | struct mod_freesync_config config = {0}; | |
4921 | struct mod_vrr_params vrr = {0}; | |
4922 | struct dc_info_packet vrr_infopacket = {0}; | |
4923 | struct amdgpu_dm_connector *aconnector = | |
4924 | to_amdgpu_dm_connector(new_con_state->base.connector); | |
4925 | ||
4926 | if (new_con_state->freesync_capable && | |
4927 | new_con_state->freesync_enable) { | |
4928 | config.state = new_crtc_state->freesync_enabled ? | |
4929 | VRR_STATE_ACTIVE_VARIABLE : | |
4930 | VRR_STATE_INACTIVE; | |
4931 | config.min_refresh_in_uhz = | |
4932 | aconnector->min_vfreq * 1000000; | |
4933 | config.max_refresh_in_uhz = | |
4934 | aconnector->max_vfreq * 1000000; | |
69ff8845 | 4935 | config.vsif_supported = true; |
98e6436d AK |
4936 | } |
4937 | ||
4938 | mod_freesync_build_vrr_params(dm->freesync_module, | |
4939 | new_stream, | |
4940 | &config, &vrr); | |
4941 | ||
4942 | mod_freesync_build_vrr_infopacket(dm->freesync_module, | |
4943 | new_stream, | |
4944 | &vrr, | |
c2791297 S |
4945 | packet_type_fs1, |
4946 | NULL, | |
98e6436d AK |
4947 | &vrr_infopacket); |
4948 | ||
4949 | new_crtc_state->adjust = vrr.adjust; | |
4950 | new_crtc_state->vrr_infopacket = vrr_infopacket; | |
4951 | } | |
4952 | ||
4953 | static int dm_update_crtcs_state(struct amdgpu_display_manager *dm, | |
3ee6b26b AD |
4954 | struct drm_atomic_state *state, |
4955 | bool enable, | |
4956 | bool *lock_and_validation_needed) | |
e7b07cee | 4957 | { |
e7b07cee | 4958 | struct drm_crtc *crtc; |
c2cea706 | 4959 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
62f55537 | 4960 | int i; |
54d76575 | 4961 | struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; |
1dc90497 | 4962 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); |
9635b754 | 4963 | struct dc_stream_state *new_stream; |
62f55537 | 4964 | int ret = 0; |
d4d4a645 | 4965 | |
1f6010a9 DF |
4966 | /* |
4967 | * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set | |
4968 | * update changed items | |
4969 | */ | |
c2cea706 | 4970 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
62f55537 | 4971 | struct amdgpu_crtc *acrtc = NULL; |
c84dec2f | 4972 | struct amdgpu_dm_connector *aconnector = NULL; |
a9e8d275 DF |
4973 | struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; |
4974 | struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; | |
f2877656 | 4975 | struct drm_plane_state *new_plane_state = NULL; |
e7b07cee | 4976 | |
9635b754 DS |
4977 | new_stream = NULL; |
4978 | ||
54d76575 LSL |
4979 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
4980 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); | |
62f55537 | 4981 | acrtc = to_amdgpu_crtc(crtc); |
e7b07cee | 4982 | |
f2877656 HW |
4983 | new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary); |
4984 | ||
4985 | if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) { | |
4986 | ret = -EINVAL; | |
4987 | goto fail; | |
4988 | } | |
4989 | ||
1daf8c63 | 4990 | aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); |
19f89e23 | 4991 | |
62f55537 | 4992 | /* TODO This hack should go away */ |
f4ac176e | 4993 | if (aconnector && enable) { |
1f6010a9 | 4994 | /* Make sure fake sink is created in plug-in scenario */ |
a9e8d275 | 4995 | drm_new_conn_state = drm_atomic_get_new_connector_state(state, |
c2cea706 | 4996 | &aconnector->base); |
a9e8d275 DF |
4997 | drm_old_conn_state = drm_atomic_get_old_connector_state(state, |
4998 | &aconnector->base); | |
19f89e23 | 4999 | |
a9e8d275 DF |
5000 | if (IS_ERR(drm_new_conn_state)) { |
5001 | ret = PTR_ERR_OR_ZERO(drm_new_conn_state); | |
62f55537 AG |
5002 | break; |
5003 | } | |
19f89e23 | 5004 | |
a9e8d275 DF |
5005 | dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); |
5006 | dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); | |
19f89e23 | 5007 | |
62f55537 | 5008 | new_stream = create_stream_for_sink(aconnector, |
c2cea706 | 5009 | &new_crtc_state->mode, |
a9e8d275 | 5010 | dm_new_conn_state); |
19f89e23 | 5011 | |
62f55537 AG |
5012 | /* |
5013 | * we can have no stream on ACTION_SET if a display | |
1f6010a9 | 5014 | * was disconnected during S3, in this case it is not an |
62f55537 | 5015 | * error, the OS will be updated after detection, and |
1f6010a9 | 5016 | * will do the right thing on next atomic commit |
62f55537 | 5017 | */ |
19f89e23 | 5018 | |
62f55537 | 5019 | if (!new_stream) { |
f1ad2f5e | 5020 | DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", |
62f55537 AG |
5021 | __func__, acrtc->base.base.id); |
5022 | break; | |
19f89e23 | 5023 | } |
e7b07cee | 5024 | |
98e6436d AK |
5025 | set_freesync_on_stream(dm, dm_new_crtc_state, |
5026 | dm_new_conn_state, new_stream); | |
5027 | ||
a97599a4 LSL |
5028 | if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && |
5029 | dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { | |
5030 | new_crtc_state->mode_changed = false; | |
5031 | DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", | |
5032 | new_crtc_state->mode_changed); | |
5033 | } | |
62f55537 | 5034 | } |
b830ebc9 | 5035 | |
98e6436d AK |
5036 | if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled) |
5037 | new_crtc_state->mode_changed = true; | |
5038 | ||
c2cea706 | 5039 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) |
9635b754 | 5040 | goto next_crtc; |
e7b07cee | 5041 | |
f1ad2f5e | 5042 | DRM_DEBUG_DRIVER( |
e7b07cee HW |
5043 | "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " |
5044 | "planes_changed:%d, mode_changed:%d,active_changed:%d," | |
5045 | "connectors_changed:%d\n", | |
5046 | acrtc->crtc_id, | |
c2cea706 LSL |
5047 | new_crtc_state->enable, |
5048 | new_crtc_state->active, | |
5049 | new_crtc_state->planes_changed, | |
5050 | new_crtc_state->mode_changed, | |
5051 | new_crtc_state->active_changed, | |
5052 | new_crtc_state->connectors_changed); | |
e7b07cee | 5053 | |
62f55537 AG |
5054 | /* Remove stream for any changed/disabled CRTC */ |
5055 | if (!enable) { | |
5056 | ||
54d76575 | 5057 | if (!dm_old_crtc_state->stream) |
9635b754 | 5058 | goto next_crtc; |
62f55537 | 5059 | |
f1ad2f5e | 5060 | DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", |
62f55537 | 5061 | crtc->base.id); |
e7b07cee | 5062 | |
1dc90497 | 5063 | /* i.e. reset mode */ |
62c933f9 | 5064 | if (dc_remove_stream_from_ctx( |
98e6436d | 5065 | dm->dc, |
62f55537 | 5066 | dm_state->context, |
62c933f9 | 5067 | dm_old_crtc_state->stream) != DC_OK) { |
62f55537 | 5068 | ret = -EINVAL; |
9635b754 | 5069 | goto fail; |
62f55537 AG |
5070 | } |
5071 | ||
54d76575 LSL |
5072 | dc_stream_release(dm_old_crtc_state->stream); |
5073 | dm_new_crtc_state->stream = NULL; | |
62f55537 AG |
5074 | |
5075 | *lock_and_validation_needed = true; | |
5076 | ||
5077 | } else {/* Add stream for any updated/enabled CRTC */ | |
fc17235f JZ |
5078 | /* |
5079 | * Quick fix to prevent NULL pointer on new_stream when | |
5080 | * added MST connectors not found in existing crtc_state in the chained mode | |
5081 | * TODO: need to dig out the root cause of that | |
5082 | */ | |
5083 | if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) | |
1bed4d09 | 5084 | goto next_crtc; |
62f55537 | 5085 | |
c2cea706 | 5086 | if (modereset_required(new_crtc_state)) |
9635b754 | 5087 | goto next_crtc; |
62f55537 | 5088 | |
c2cea706 | 5089 | if (modeset_required(new_crtc_state, new_stream, |
54d76575 | 5090 | dm_old_crtc_state->stream)) { |
62f55537 | 5091 | |
54d76575 | 5092 | WARN_ON(dm_new_crtc_state->stream); |
62f55537 | 5093 | |
54d76575 | 5094 | dm_new_crtc_state->stream = new_stream; |
27b3f4fc | 5095 | |
62f55537 AG |
5096 | dc_stream_retain(new_stream); |
5097 | ||
f1ad2f5e | 5098 | DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", |
62f55537 | 5099 | crtc->base.id); |
1dc90497 | 5100 | |
13ab1b44 | 5101 | if (dc_add_stream_to_ctx( |
98e6436d | 5102 | dm->dc, |
1dc90497 | 5103 | dm_state->context, |
13ab1b44 | 5104 | dm_new_crtc_state->stream) != DC_OK) { |
1dc90497 | 5105 | ret = -EINVAL; |
9635b754 | 5106 | goto fail; |
1dc90497 AG |
5107 | } |
5108 | ||
62f55537 | 5109 | *lock_and_validation_needed = true; |
9b690ef3 | 5110 | } |
62f55537 | 5111 | } |
9b690ef3 | 5112 | |
9635b754 | 5113 | next_crtc: |
62f55537 AG |
5114 | /* Release extra reference */ |
5115 | if (new_stream) | |
5116 | dc_stream_release(new_stream); | |
e277adc5 LSL |
5117 | |
5118 | /* | |
5119 | * We want to do dc stream updates that do not require a | |
5120 | * full modeset below. | |
5121 | */ | |
20fa2ff0 LSL |
5122 | if (!(enable && aconnector && new_crtc_state->enable && |
5123 | new_crtc_state->active)) | |
e277adc5 LSL |
5124 | continue; |
5125 | /* | |
5126 | * Given above conditions, the dc state cannot be NULL because: | |
20fa2ff0 LSL |
5127 | * 1. We're in the process of enabling CRTCs (just been added |
5128 | * to the dc context, or already is on the context) | |
5129 | * 2. Has a valid connector attached, and | |
5130 | * 3. Is currently active and enabled. | |
5131 | * => The dc stream state currently exists. | |
e277adc5 LSL |
5132 | */ |
5133 | BUG_ON(dm_new_crtc_state->stream == NULL); | |
5134 | ||
a9e8d275 DF |
5135 | /* Scaling or underscan settings */ |
5136 | if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state)) | |
5137 | update_stream_scaling_settings( | |
5138 | &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); | |
5139 | ||
bc13f2f8 LSL |
5140 | /* |
5141 | * Color management settings. We also update color properties | |
5142 | * when a modeset is needed, to ensure it gets reprogrammed. | |
5143 | */ | |
5144 | if (dm_new_crtc_state->base.color_mgmt_changed || | |
5145 | drm_atomic_crtc_needs_modeset(new_crtc_state)) { | |
e277adc5 LSL |
5146 | ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); |
5147 | if (ret) | |
5148 | goto fail; | |
5149 | amdgpu_dm_set_ctm(dm_new_crtc_state); | |
5150 | } | |
98e6436d AK |
5151 | |
5152 | ||
62f55537 | 5153 | } |
e7b07cee | 5154 | |
62f55537 | 5155 | return ret; |
9635b754 DS |
5156 | |
5157 | fail: | |
5158 | if (new_stream) | |
5159 | dc_stream_release(new_stream); | |
5160 | return ret; | |
62f55537 | 5161 | } |
9b690ef3 | 5162 | |
3ee6b26b AD |
5163 | static int dm_update_planes_state(struct dc *dc, |
5164 | struct drm_atomic_state *state, | |
5165 | bool enable, | |
5166 | bool *lock_and_validation_needed) | |
62f55537 AG |
5167 | { |
5168 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; | |
0bc9706d | 5169 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
62f55537 AG |
5170 | struct drm_plane *plane; |
5171 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
54d76575 | 5172 | struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; |
62f55537 | 5173 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); |
54d76575 | 5174 | struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; |
62f55537 AG |
5175 | int i ; |
5176 | /* TODO return page_flip_needed() function */ | |
5177 | bool pflip_needed = !state->allow_modeset; | |
5178 | int ret = 0; | |
e7b07cee | 5179 | |
9b690ef3 | 5180 | |
df534fff S |
5181 | /* Add new planes, in reverse order as DC expectation */ |
5182 | for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { | |
62f55537 AG |
5183 | new_plane_crtc = new_plane_state->crtc; |
5184 | old_plane_crtc = old_plane_state->crtc; | |
54d76575 LSL |
5185 | dm_new_plane_state = to_dm_plane_state(new_plane_state); |
5186 | dm_old_plane_state = to_dm_plane_state(old_plane_state); | |
62f55537 AG |
5187 | |
5188 | /*TODO Implement atomic check for cursor plane */ | |
5189 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
5190 | continue; | |
9b690ef3 | 5191 | |
62f55537 AG |
5192 | /* Remove any changed/removed planes */ |
5193 | if (!enable) { | |
a2a330ad S |
5194 | if (pflip_needed && |
5195 | plane->type != DRM_PLANE_TYPE_OVERLAY) | |
c21b68c5 | 5196 | continue; |
a7b06724 | 5197 | |
62f55537 AG |
5198 | if (!old_plane_crtc) |
5199 | continue; | |
5200 | ||
0bc9706d LSL |
5201 | old_crtc_state = drm_atomic_get_old_crtc_state( |
5202 | state, old_plane_crtc); | |
54d76575 | 5203 | dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); |
9b690ef3 | 5204 | |
54d76575 | 5205 | if (!dm_old_crtc_state->stream) |
62f55537 AG |
5206 | continue; |
5207 | ||
f2877656 | 5208 | DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", |
62f55537 | 5209 | plane->base.id, old_plane_crtc->base.id); |
9b690ef3 | 5210 | |
62f55537 AG |
5211 | if (!dc_remove_plane_from_context( |
5212 | dc, | |
54d76575 LSL |
5213 | dm_old_crtc_state->stream, |
5214 | dm_old_plane_state->dc_state, | |
62f55537 AG |
5215 | dm_state->context)) { |
5216 | ||
5217 | ret = EINVAL; | |
5218 | return ret; | |
e7b07cee HW |
5219 | } |
5220 | ||
9b690ef3 | 5221 | |
54d76575 LSL |
5222 | dc_plane_state_release(dm_old_plane_state->dc_state); |
5223 | dm_new_plane_state->dc_state = NULL; | |
1dc90497 | 5224 | |
62f55537 | 5225 | *lock_and_validation_needed = true; |
1dc90497 | 5226 | |
62f55537 | 5227 | } else { /* Add new planes */ |
8c45c5db | 5228 | struct dc_plane_state *dc_new_plane_state; |
1dc90497 | 5229 | |
62f55537 AG |
5230 | if (drm_atomic_plane_disabling(plane->state, new_plane_state)) |
5231 | continue; | |
e7b07cee | 5232 | |
62f55537 AG |
5233 | if (!new_plane_crtc) |
5234 | continue; | |
e7b07cee | 5235 | |
62f55537 | 5236 | new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); |
54d76575 | 5237 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
1dc90497 | 5238 | |
54d76575 | 5239 | if (!dm_new_crtc_state->stream) |
62f55537 AG |
5240 | continue; |
5241 | ||
a2a330ad S |
5242 | if (pflip_needed && |
5243 | plane->type != DRM_PLANE_TYPE_OVERLAY) | |
c21b68c5 | 5244 | continue; |
62f55537 | 5245 | |
54d76575 | 5246 | WARN_ON(dm_new_plane_state->dc_state); |
9b690ef3 | 5247 | |
8c45c5db | 5248 | dc_new_plane_state = dc_create_plane_state(dc); |
d5400aab LSL |
5249 | if (!dc_new_plane_state) |
5250 | return -ENOMEM; | |
62f55537 | 5251 | |
8c45c5db LSL |
5252 | DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", |
5253 | plane->base.id, new_plane_crtc->base.id); | |
5254 | ||
62f55537 AG |
5255 | ret = fill_plane_attributes( |
5256 | new_plane_crtc->dev->dev_private, | |
8c45c5db | 5257 | dc_new_plane_state, |
62f55537 | 5258 | new_plane_state, |
9817d5f5 | 5259 | new_crtc_state); |
8c45c5db LSL |
5260 | if (ret) { |
5261 | dc_plane_state_release(dc_new_plane_state); | |
62f55537 | 5262 | return ret; |
8c45c5db | 5263 | } |
62f55537 | 5264 | |
8c45c5db LSL |
5265 | /* |
5266 | * Any atomic check errors that occur after this will | |
5267 | * not need a release. The plane state will be attached | |
5268 | * to the stream, and therefore part of the atomic | |
5269 | * state. It'll be released when the atomic state is | |
5270 | * cleaned. | |
5271 | */ | |
62f55537 AG |
5272 | if (!dc_add_plane_to_context( |
5273 | dc, | |
54d76575 | 5274 | dm_new_crtc_state->stream, |
8c45c5db | 5275 | dc_new_plane_state, |
62f55537 AG |
5276 | dm_state->context)) { |
5277 | ||
8c45c5db | 5278 | dc_plane_state_release(dc_new_plane_state); |
d5400aab | 5279 | return -EINVAL; |
e7b07cee | 5280 | } |
62f55537 | 5281 | |
8c45c5db LSL |
5282 | dm_new_plane_state->dc_state = dc_new_plane_state; |
5283 | ||
000b59ea LSL |
5284 | /* Tell DC to do a full surface update every time there |
5285 | * is a plane change. Inefficient, but works for now. | |
5286 | */ | |
5287 | dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; | |
5288 | ||
62f55537 | 5289 | *lock_and_validation_needed = true; |
e7b07cee | 5290 | } |
62f55537 | 5291 | } |
e7b07cee HW |
5292 | |
5293 | ||
62f55537 AG |
5294 | return ret; |
5295 | } | |
a87fa993 BL |
5296 | enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, struct drm_atomic_state *state) |
5297 | { | |
5298 | ||
5299 | ||
5300 | int i, j, num_plane; | |
5301 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
5302 | struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; | |
5303 | struct drm_crtc *new_plane_crtc, *old_plane_crtc; | |
5304 | struct drm_plane *plane; | |
5305 | ||
5306 | struct drm_crtc *crtc; | |
5307 | struct drm_crtc_state *new_crtc_state, *old_crtc_state; | |
5308 | struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state; | |
5309 | struct dc_stream_status *status = NULL; | |
5310 | ||
5311 | struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL); | |
5312 | struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL); | |
5313 | struct dc_stream_update stream_update; | |
5314 | enum surface_update_type update_type = UPDATE_TYPE_FAST; | |
5315 | ||
5316 | ||
5317 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { | |
5318 | new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); | |
5319 | old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); | |
5320 | num_plane = 0; | |
5321 | ||
5322 | if (new_dm_crtc_state->stream) { | |
5323 | ||
5324 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) { | |
5325 | new_plane_crtc = new_plane_state->crtc; | |
5326 | old_plane_crtc = old_plane_state->crtc; | |
5327 | new_dm_plane_state = to_dm_plane_state(new_plane_state); | |
5328 | old_dm_plane_state = to_dm_plane_state(old_plane_state); | |
5329 | ||
5330 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
5331 | continue; | |
5332 | ||
5333 | if (!state->allow_modeset) | |
5334 | continue; | |
5335 | ||
5336 | if (crtc == new_plane_crtc) { | |
5337 | updates[num_plane].surface = &surface[num_plane]; | |
5338 | ||
5339 | if (new_crtc_state->mode_changed) { | |
5340 | updates[num_plane].surface->src_rect = | |
5341 | new_dm_plane_state->dc_state->src_rect; | |
5342 | updates[num_plane].surface->dst_rect = | |
5343 | new_dm_plane_state->dc_state->dst_rect; | |
5344 | updates[num_plane].surface->rotation = | |
5345 | new_dm_plane_state->dc_state->rotation; | |
5346 | updates[num_plane].surface->in_transfer_func = | |
5347 | new_dm_plane_state->dc_state->in_transfer_func; | |
5348 | stream_update.dst = new_dm_crtc_state->stream->dst; | |
5349 | stream_update.src = new_dm_crtc_state->stream->src; | |
5350 | } | |
5351 | ||
5352 | if (new_crtc_state->color_mgmt_changed) { | |
5353 | updates[num_plane].gamma = | |
5354 | new_dm_plane_state->dc_state->gamma_correction; | |
5355 | updates[num_plane].in_transfer_func = | |
5356 | new_dm_plane_state->dc_state->in_transfer_func; | |
5357 | stream_update.gamut_remap = | |
5358 | &new_dm_crtc_state->stream->gamut_remap_matrix; | |
5359 | stream_update.out_transfer_func = | |
5360 | new_dm_crtc_state->stream->out_transfer_func; | |
5361 | } | |
5362 | ||
5363 | num_plane++; | |
5364 | } | |
5365 | } | |
5366 | ||
5367 | if (num_plane > 0) { | |
5368 | status = dc_stream_get_status(new_dm_crtc_state->stream); | |
5369 | update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane, | |
5370 | &stream_update, status); | |
5371 | ||
5372 | if (update_type > UPDATE_TYPE_MED) { | |
5373 | update_type = UPDATE_TYPE_FULL; | |
5374 | goto ret; | |
5375 | } | |
5376 | } | |
5377 | ||
5378 | } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) { | |
5379 | update_type = UPDATE_TYPE_FULL; | |
5380 | goto ret; | |
5381 | } | |
5382 | } | |
5383 | ||
5384 | ret: | |
5385 | kfree(updates); | |
5386 | kfree(surface); | |
5387 | ||
5388 | return update_type; | |
5389 | } | |
62f55537 | 5390 | |
7578ecda AD |
5391 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
5392 | struct drm_atomic_state *state) | |
62f55537 | 5393 | { |
62f55537 AG |
5394 | struct amdgpu_device *adev = dev->dev_private; |
5395 | struct dc *dc = adev->dm.dc; | |
5396 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state); | |
5397 | struct drm_connector *connector; | |
c2cea706 | 5398 | struct drm_connector_state *old_con_state, *new_con_state; |
62f55537 | 5399 | struct drm_crtc *crtc; |
fc9e9920 | 5400 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
a87fa993 BL |
5401 | enum surface_update_type update_type = UPDATE_TYPE_FAST; |
5402 | enum surface_update_type overall_update_type = UPDATE_TYPE_FAST; | |
5403 | ||
1e88ad0a | 5404 | int ret, i; |
e7b07cee | 5405 | |
62f55537 AG |
5406 | /* |
5407 | * This bool will be set for true for any modeset/reset | |
5408 | * or plane update which implies non fast surface update. | |
5409 | */ | |
5410 | bool lock_and_validation_needed = false; | |
5411 | ||
5412 | ret = drm_atomic_helper_check_modeset(dev, state); | |
01e28f9c MD |
5413 | if (ret) |
5414 | goto fail; | |
62f55537 | 5415 | |
1e88ad0a | 5416 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
98e6436d AK |
5417 | struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); |
5418 | struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); | |
5419 | ||
1e88ad0a | 5420 | if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && |
98e6436d AK |
5421 | !new_crtc_state->color_mgmt_changed && |
5422 | (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled)) | |
1e88ad0a | 5423 | continue; |
7bef1af3 | 5424 | |
1e88ad0a S |
5425 | if (!new_crtc_state->enable) |
5426 | continue; | |
fc9e9920 | 5427 | |
1e88ad0a S |
5428 | ret = drm_atomic_add_affected_connectors(state, crtc); |
5429 | if (ret) | |
5430 | return ret; | |
fc9e9920 | 5431 | |
1e88ad0a S |
5432 | ret = drm_atomic_add_affected_planes(state, crtc); |
5433 | if (ret) | |
5434 | goto fail; | |
e7b07cee HW |
5435 | } |
5436 | ||
62f55537 AG |
5437 | dm_state->context = dc_create_state(); |
5438 | ASSERT(dm_state->context); | |
f36cc577 | 5439 | dc_resource_state_copy_construct_current(dc, dm_state->context); |
62f55537 AG |
5440 | |
5441 | /* Remove exiting planes if they are modified */ | |
5442 | ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed); | |
5443 | if (ret) { | |
5444 | goto fail; | |
5445 | } | |
5446 | ||
5447 | /* Disable all crtcs which require disable */ | |
98e6436d | 5448 | ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed); |
62f55537 AG |
5449 | if (ret) { |
5450 | goto fail; | |
5451 | } | |
5452 | ||
5453 | /* Enable all crtcs which require enable */ | |
98e6436d | 5454 | ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed); |
62f55537 AG |
5455 | if (ret) { |
5456 | goto fail; | |
5457 | } | |
5458 | ||
5459 | /* Add new/modified planes */ | |
5460 | ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed); | |
5461 | if (ret) { | |
5462 | goto fail; | |
5463 | } | |
5464 | ||
b349f76e ES |
5465 | /* Run this here since we want to validate the streams we created */ |
5466 | ret = drm_atomic_helper_check_planes(dev, state); | |
5467 | if (ret) | |
5468 | goto fail; | |
62f55537 | 5469 | |
ebdd27e1 | 5470 | /* Check scaling and underscan changes*/ |
1f6010a9 | 5471 | /* TODO Removed scaling changes validation due to inability to commit |
e7b07cee HW |
5472 | * new stream into context w\o causing full reset. Need to |
5473 | * decide how to handle. | |
5474 | */ | |
c2cea706 | 5475 | for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { |
54d76575 LSL |
5476 | struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); |
5477 | struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); | |
5478 | struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); | |
e7b07cee HW |
5479 | |
5480 | /* Skip any modesets/resets */ | |
0bc9706d LSL |
5481 | if (!acrtc || drm_atomic_crtc_needs_modeset( |
5482 | drm_atomic_get_new_crtc_state(state, &acrtc->base))) | |
e7b07cee HW |
5483 | continue; |
5484 | ||
b830ebc9 | 5485 | /* Skip any thing not scale or underscan changes */ |
54d76575 | 5486 | if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) |
e7b07cee HW |
5487 | continue; |
5488 | ||
a87fa993 | 5489 | overall_update_type = UPDATE_TYPE_FULL; |
e7b07cee HW |
5490 | lock_and_validation_needed = true; |
5491 | } | |
5492 | ||
e7b07cee HW |
5493 | /* |
5494 | * For full updates case when | |
1f6010a9 | 5495 | * removing/adding/updating streams on one CRTC while flipping |
e7b07cee HW |
5496 | * on another CRTC, |
5497 | * acquiring global lock will guarantee that any such full | |
5498 | * update commit | |
5499 | * will wait for completion of any outstanding flip using DRMs | |
5500 | * synchronization events. | |
5501 | */ | |
a87fa993 BL |
5502 | update_type = dm_determine_update_type_for_commit(dc, state); |
5503 | ||
5504 | if (overall_update_type < update_type) | |
5505 | overall_update_type = update_type; | |
5506 | ||
5507 | /* | |
5508 | * lock_and_validation_needed was an old way to determine if we need to set | |
5509 | * the global lock. Leaving it in to check if we broke any corner cases | |
5510 | * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED | |
5511 | * lock_and_validation_needed false = UPDATE_TYPE_FAST | |
5512 | */ | |
5513 | if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST) | |
5514 | WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL"); | |
5515 | else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST) | |
5516 | WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST"); | |
e7b07cee | 5517 | |
e7b07cee | 5518 | |
a87fa993 | 5519 | if (overall_update_type > UPDATE_TYPE_FAST) { |
e7b07cee HW |
5520 | |
5521 | ret = do_aquire_global_lock(dev, state); | |
5522 | if (ret) | |
5523 | goto fail; | |
1dc90497 | 5524 | |
e750d56d | 5525 | if (dc_validate_global_state(dc, dm_state->context) != DC_OK) { |
e7b07cee HW |
5526 | ret = -EINVAL; |
5527 | goto fail; | |
5528 | } | |
5529 | } | |
5530 | ||
5531 | /* Must be success */ | |
5532 | WARN_ON(ret); | |
5533 | return ret; | |
5534 | ||
5535 | fail: | |
5536 | if (ret == -EDEADLK) | |
01e28f9c | 5537 | DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); |
e7b07cee | 5538 | else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) |
01e28f9c | 5539 | DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); |
e7b07cee | 5540 | else |
01e28f9c | 5541 | DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); |
e7b07cee HW |
5542 | |
5543 | return ret; | |
5544 | } | |
5545 | ||
3ee6b26b AD |
5546 | static bool is_dp_capable_without_timing_msa(struct dc *dc, |
5547 | struct amdgpu_dm_connector *amdgpu_dm_connector) | |
e7b07cee HW |
5548 | { |
5549 | uint8_t dpcd_data; | |
5550 | bool capable = false; | |
5551 | ||
c84dec2f | 5552 | if (amdgpu_dm_connector->dc_link && |
e7b07cee HW |
5553 | dm_helpers_dp_read_dpcd( |
5554 | NULL, | |
c84dec2f | 5555 | amdgpu_dm_connector->dc_link, |
e7b07cee HW |
5556 | DP_DOWN_STREAM_PORT_COUNT, |
5557 | &dpcd_data, | |
5558 | sizeof(dpcd_data))) { | |
5559 | capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; | |
5560 | } | |
5561 | ||
5562 | return capable; | |
5563 | } | |
98e6436d AK |
5564 | void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, |
5565 | struct edid *edid) | |
e7b07cee HW |
5566 | { |
5567 | int i; | |
e7b07cee HW |
5568 | bool edid_check_required; |
5569 | struct detailed_timing *timing; | |
5570 | struct detailed_non_pixel *data; | |
5571 | struct detailed_data_monitor_range *range; | |
c84dec2f HW |
5572 | struct amdgpu_dm_connector *amdgpu_dm_connector = |
5573 | to_amdgpu_dm_connector(connector); | |
8218d7f1 | 5574 | struct dm_connector_state *dm_con_state; |
e7b07cee HW |
5575 | |
5576 | struct drm_device *dev = connector->dev; | |
5577 | struct amdgpu_device *adev = dev->dev_private; | |
b830ebc9 | 5578 | |
8218d7f1 HW |
5579 | if (!connector->state) { |
5580 | DRM_ERROR("%s - Connector has no state", __func__); | |
5581 | return; | |
5582 | } | |
5583 | ||
98e6436d AK |
5584 | if (!edid) { |
5585 | dm_con_state = to_dm_connector_state(connector->state); | |
5586 | ||
5587 | amdgpu_dm_connector->min_vfreq = 0; | |
5588 | amdgpu_dm_connector->max_vfreq = 0; | |
5589 | amdgpu_dm_connector->pixel_clock_mhz = 0; | |
5590 | ||
5591 | dm_con_state->freesync_capable = false; | |
5592 | dm_con_state->freesync_enable = false; | |
5593 | return; | |
5594 | } | |
5595 | ||
8218d7f1 HW |
5596 | dm_con_state = to_dm_connector_state(connector->state); |
5597 | ||
e7b07cee | 5598 | edid_check_required = false; |
c84dec2f | 5599 | if (!amdgpu_dm_connector->dc_sink) { |
e7b07cee HW |
5600 | DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); |
5601 | return; | |
5602 | } | |
5603 | if (!adev->dm.freesync_module) | |
5604 | return; | |
5605 | /* | |
5606 | * if edid non zero restrict freesync only for dp and edp | |
5607 | */ | |
5608 | if (edid) { | |
c84dec2f HW |
5609 | if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT |
5610 | || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { | |
e7b07cee HW |
5611 | edid_check_required = is_dp_capable_without_timing_msa( |
5612 | adev->dm.dc, | |
c84dec2f | 5613 | amdgpu_dm_connector); |
e7b07cee HW |
5614 | } |
5615 | } | |
8218d7f1 | 5616 | dm_con_state->freesync_capable = false; |
e7b07cee HW |
5617 | if (edid_check_required == true && (edid->version > 1 || |
5618 | (edid->version == 1 && edid->revision > 1))) { | |
5619 | for (i = 0; i < 4; i++) { | |
5620 | ||
5621 | timing = &edid->detailed_timings[i]; | |
5622 | data = &timing->data.other_data; | |
5623 | range = &data->data.range; | |
5624 | /* | |
5625 | * Check if monitor has continuous frequency mode | |
5626 | */ | |
5627 | if (data->type != EDID_DETAIL_MONITOR_RANGE) | |
5628 | continue; | |
5629 | /* | |
5630 | * Check for flag range limits only. If flag == 1 then | |
5631 | * no additional timing information provided. | |
5632 | * Default GTF, GTF Secondary curve and CVT are not | |
5633 | * supported | |
5634 | */ | |
5635 | if (range->flags != 1) | |
5636 | continue; | |
5637 | ||
c84dec2f HW |
5638 | amdgpu_dm_connector->min_vfreq = range->min_vfreq; |
5639 | amdgpu_dm_connector->max_vfreq = range->max_vfreq; | |
5640 | amdgpu_dm_connector->pixel_clock_mhz = | |
e7b07cee HW |
5641 | range->pixel_clock_mhz * 10; |
5642 | break; | |
5643 | } | |
5644 | ||
c84dec2f | 5645 | if (amdgpu_dm_connector->max_vfreq - |
98e6436d AK |
5646 | amdgpu_dm_connector->min_vfreq > 10) { |
5647 | ||
8218d7f1 | 5648 | dm_con_state->freesync_capable = true; |
e7b07cee HW |
5649 | } |
5650 | } | |
e7b07cee HW |
5651 | } |
5652 |