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drm/amd/display: Fix indentation in dm_suspend()
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
4562236b
HW		 33#include "atom.h"
34#include "amdgpu_dm.h"
e7b07cee 35#include "amdgpu_pm.h"
4562236b
HW		 36
37#include "amd_shared.h"
38#include "amdgpu_dm_irq.h"
39#include "dm_helpers.h"
e7b07cee
HW		 40#include "dm_services_types.h"
41#include "amdgpu_dm_mst_types.h"
4562236b
HW		 42
43#include "ivsrcid/ivsrcid_vislands30.h"
44
45#include <linux/module.h>
46#include <linux/moduleparam.h>
47#include <linux/version.h>
e7b07cee 48#include <linux/types.h>
4562236b 49
e7b07cee 50#include <drm/drmP.h>
4562236b
HW		 51#include <drm/drm_atomic.h>
52#include <drm/drm_atomic_helper.h>
53#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 54#include <drm/drm_fb_helper.h>
55#include <drm/drm_edid.h>
4562236b
HW		 56
57#include "modules/inc/mod_freesync.h"
58
ff5ef992
AD		 59#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
60#include "ivsrcid/irqsrcs_dcn_1_0.h"
61
62#include "raven1/DCN/dcn_1_0_offset.h"
63#include "raven1/DCN/dcn_1_0_sh_mask.h"
64#include "vega10/soc15ip.h"
65
66#include "soc15_common.h"
67#endif
68
e7b07cee
HW		 69#include "modules/inc/mod_freesync.h"
70
71#include "i2caux_interface.h"
72
7578ecda
AD		 73/* basic init/fini API */
74static int amdgpu_dm_init(struct amdgpu_device *adev);
75static void amdgpu_dm_fini(struct amdgpu_device *adev);
76
77/* initializes drm_device display related structures, based on the information
78 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
79 * drm_encoder, drm_mode_config
80 *
81 * Returns 0 on success
82 */
83static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
84/* removes and deallocates the drm structures, created by the above function */
85static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
86
87static void
88amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
89
90static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
91 struct amdgpu_plane *aplane,
92 unsigned long possible_crtcs);
93static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
94 struct drm_plane *plane,
95 uint32_t link_index);
96static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
97 struct amdgpu_dm_connector *amdgpu_dm_connector,
98 uint32_t link_index,
99 struct amdgpu_encoder *amdgpu_encoder);
100static int amdgpu_dm_encoder_init(struct drm_device *dev,
101 struct amdgpu_encoder *aencoder,
102 uint32_t link_index);
103
104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
105
106static int amdgpu_dm_atomic_commit(struct drm_device *dev,
107 struct drm_atomic_state *state,
108 bool nonblock);
109
110static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
111
112static int amdgpu_dm_atomic_check(struct drm_device *dev,
113 struct drm_atomic_state *state);
114
115
116
e7b07cee 117
e04a6123 118static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 119 DRM_PLANE_TYPE_PRIMARY,
120 DRM_PLANE_TYPE_PRIMARY,
121 DRM_PLANE_TYPE_PRIMARY,
122 DRM_PLANE_TYPE_PRIMARY,
123 DRM_PLANE_TYPE_PRIMARY,
124 DRM_PLANE_TYPE_PRIMARY,
125};
126
e04a6123 127static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
138};
139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
239 /*
240 * following if is check inherited from both functions where this one is
241 * used now. Need to be checked why it could happen.
242 */
243 if (otg_inst == -1) {
244 WARN_ON(1);
245 return adev->mode_info.crtcs[0];
246 }
247
248 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
249 amdgpu_crtc = to_amdgpu_crtc(crtc);
250
251 if (amdgpu_crtc->otg_inst == otg_inst)
252 return amdgpu_crtc;
253 }
254
255 return NULL;
256}
257
258static void dm_pflip_high_irq(void *interrupt_params)
259{
4562236b
HW		 260 struct amdgpu_crtc *amdgpu_crtc;
261 struct common_irq_params *irq_params = interrupt_params;
262 struct amdgpu_device *adev = irq_params->adev;
263 unsigned long flags;
264
265 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
266
267 /* IRQ could occur when in initial stage */
268 /*TODO work and BO cleanup */
269 if (amdgpu_crtc == NULL) {
270 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
271 return;
272 }
273
274 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 275
276 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
277 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
278 amdgpu_crtc->pflip_status,
279 AMDGPU_FLIP_SUBMITTED,
280 amdgpu_crtc->crtc_id,
281 amdgpu_crtc);
282 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
283 return;
284 }
285
4562236b
HW		 286
287 /* wakeup usersapce */
1159898a 288 if (amdgpu_crtc->event) {
753c66c9
MK		 289 /* Update to correct count/ts if racing with vblank irq */
290 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
291
54f5499a 292 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 293
54f5499a
AG		 294 /* page flip completed. clean up */
295 amdgpu_crtc->event = NULL;
1159898a 296
54f5499a
AG		 297 } else
298 WARN_ON(1);
4562236b 299
54f5499a 300 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 301 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
302
54f5499a
AG		 303 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
304 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 305
306 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 307}
308
309static void dm_crtc_high_irq(void *interrupt_params)
310{
311 struct common_irq_params *irq_params = interrupt_params;
312 struct amdgpu_device *adev = irq_params->adev;
313 uint8_t crtc_index = 0;
314 struct amdgpu_crtc *acrtc;
315
b57de80a 316 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b
HW		 317
318 if (acrtc)
319 crtc_index = acrtc->crtc_id;
320
321 drm_handle_vblank(adev->ddev, crtc_index);
322}
323
324static int dm_set_clockgating_state(void *handle,
325 enum amd_clockgating_state state)
326{
327 return 0;
328}
329
330static int dm_set_powergating_state(void *handle,
331 enum amd_powergating_state state)
332{
333 return 0;
334}
335
336/* Prototypes of private functions */
337static int dm_early_init(void* handle);
338
339static void hotplug_notify_work_func(struct work_struct *work)
340{
341 struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
342 struct drm_device *dev = dm->ddev;
343
344 drm_kms_helper_hotplug_event(dev);
345}
346
a32e24b4
RL		 347#ifdef ENABLE_FBC
348#include "dal_asic_id.h"
349/* Allocate memory for FBC compressed data */
350/* TODO: Dynamic allocation */
351#define AMDGPU_FBC_SIZE (3840 * 2160 * 4)
352
7578ecda 353static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
a32e24b4
RL		 354{
355 int r;
356 struct dm_comressor_info *compressor = &adev->dm.compressor;
357
358 if (!compressor->bo_ptr) {
359 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
360 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
361 &compressor->gpu_addr, &compressor->cpu_addr);
362
363 if (r)
364 DRM_ERROR("DM: Failed to initialize fbc\n");
365 }
366
367}
368#endif
369
370
4562236b
HW		 371/* Init display KMS
372 *
373 * Returns 0 on success
374 */
7578ecda 375static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 376{
377 struct dc_init_data init_data;
378 adev->dm.ddev = adev->ddev;
379 adev->dm.adev = adev;
380
4562236b
HW		 381 /* Zero all the fields */
382 memset(&init_data, 0, sizeof(init_data));
383
384 /* initialize DAL's lock (for SYNC context use) */
385 spin_lock_init(&adev->dm.dal_lock);
386
387 /* initialize DAL's mutex */
388 mutex_init(&adev->dm.dal_mutex);
389
390 if(amdgpu_dm_irq_init(adev)) {
391 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
392 goto error;
393 }
394
395 init_data.asic_id.chip_family = adev->family;
396
397 init_data.asic_id.pci_revision_id = adev->rev_id;
398 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
399
400 init_data.asic_id.vram_width = adev->mc.vram_width;
401 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
402 init_data.asic_id.atombios_base_address =
403 adev->mode_info.atom_context->bios;
404
405 init_data.driver = adev;
406
407 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
408
409 if (!adev->dm.cgs_device) {
410 DRM_ERROR("amdgpu: failed to create cgs device.\n");
411 goto error;
412 }
413
414 init_data.cgs_device = adev->dm.cgs_device;
415
416 adev->dm.dal = NULL;
417
418 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
419
f1ad2f5e
HW		 420 if (amdgpu_dc_log)
421 init_data.log_mask = DC_DEFAULT_LOG_MASK;
422 else
423 init_data.log_mask = DC_MIN_LOG_MASK;
01a526f3 424
a32e24b4
RL		 425#ifdef ENABLE_FBC
426 if (adev->family == FAMILY_CZ)
427 amdgpu_dm_initialize_fbc(adev);
428 init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
429#endif
4562236b
HW		 430 /* Display Core create. */
431 adev->dm.dc = dc_create(&init_data);
432
f1ad2f5e
HW		 433 if (adev->dm.dc)
434 DRM_INFO("Display Core initialized!\n");
435 else
4562236b
HW		 436 DRM_INFO("Display Core failed to initialize!\n");
437
438 INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
439
440 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
441 if (!adev->dm.freesync_module) {
442 DRM_ERROR(
443 "amdgpu: failed to initialize freesync_module.\n");
444 } else
f1ad2f5e 445 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 446 adev->dm.freesync_module);
447
448 if (amdgpu_dm_initialize_drm_device(adev)) {
449 DRM_ERROR(
450 "amdgpu: failed to initialize sw for display support.\n");
451 goto error;
452 }
453
454 /* Update the actual used number of crtc */
455 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
456
457 /* TODO: Add_display_info? */
458
459 /* TODO use dynamic cursor width */
ce75805e
AG		 460 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
461 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 462
463 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
464 DRM_ERROR(
465 "amdgpu: failed to initialize sw for display support.\n");
466 goto error;
467 }
468
f1ad2f5e 469 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 470
471 return 0;
472error:
473 amdgpu_dm_fini(adev);
474
475 return -1;
476}
477
7578ecda 478static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 479{
480 amdgpu_dm_destroy_drm_device(&adev->dm);
481 /*
482 * TODO: pageflip, vlank interrupt
483 *
484 * amdgpu_dm_irq_fini(adev);
485 */
486
487 if (adev->dm.cgs_device) {
488 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
489 adev->dm.cgs_device = NULL;
490 }
491 if (adev->dm.freesync_module) {
492 mod_freesync_destroy(adev->dm.freesync_module);
493 adev->dm.freesync_module = NULL;
494 }
495 /* DC Destroy TODO: Replace destroy DAL */
21de3396 496 if (adev->dm.dc)
4562236b 497 dc_destroy(&adev->dm.dc);
4562236b
HW		 498 return;
499}
500
4562236b
HW		 501static int dm_sw_init(void *handle)
502{
503 return 0;
504}
505
506static int dm_sw_fini(void *handle)
507{
508 return 0;
509}
510
7abcf6b5 511static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 512{
c84dec2f 513 struct amdgpu_dm_connector *aconnector;
4562236b 514 struct drm_connector *connector;
7abcf6b5 515 int ret = 0;
4562236b
HW		 516
517 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
518
519 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 520 aconnector = to_amdgpu_dm_connector(connector);
7abcf6b5 521 if (aconnector->dc_link->type == dc_connection_mst_branch) {
f1ad2f5e 522 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 523 aconnector, aconnector->base.base.id);
524
525 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
526 if (ret < 0) {
527 DRM_ERROR("DM_MST: Failed to start MST\n");
528 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
529 return ret;
4562236b 530 }
7abcf6b5 531 }
4562236b
HW		 532 }
533
534 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 535 return ret;
536}
537
538static int dm_late_init(void *handle)
539{
540 struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
7abcf6b5 541
33be2785 542 return detect_mst_link_for_all_connectors(dev);
4562236b
HW		 543}
544
545static void s3_handle_mst(struct drm_device *dev, bool suspend)
546{
c84dec2f 547 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 548 struct drm_connector *connector;
549
550 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
551
552 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 553 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 554 if (aconnector->dc_link->type == dc_connection_mst_branch &&
555 !aconnector->mst_port) {
556
557 if (suspend)
558 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
559 else
560 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
561 }
562 }
563
564 drm_modeset_unlock(&dev->mode_config.connection_mutex);
565}
566
567static int dm_hw_init(void *handle)
568{
569 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
570 /* Create DAL display manager */
571 amdgpu_dm_init(adev);
4562236b
HW		 572 amdgpu_dm_hpd_init(adev);
573
4562236b
HW		 574 return 0;
575}
576
577static int dm_hw_fini(void *handle)
578{
579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
580
581 amdgpu_dm_hpd_fini(adev);
582
583 amdgpu_dm_irq_fini(adev);
21de3396 584 amdgpu_dm_fini(adev);
4562236b
HW		 585 return 0;
586}
587
588static int dm_suspend(void *handle)
589{
590 struct amdgpu_device *adev = handle;
591 struct amdgpu_display_manager *dm = &adev->dm;
592 int ret = 0;
4562236b
HW		 593
594 s3_handle_mst(adev->ddev, true);
595
4562236b
HW		 596 amdgpu_dm_irq_suspend(adev);
597
0a214e2f 598 WARN_ON(adev->dm.cached_state);
a3621485
AG		 599 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
600
32f5062d 601 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 602
603 return ret;
604}
605
1daf8c63
AD		 606static struct amdgpu_dm_connector *
607amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
608 struct drm_crtc *crtc)
4562236b
HW		 609{
610 uint32_t i;
c2cea706 611 struct drm_connector_state *new_con_state;
4562236b
HW		 612 struct drm_connector *connector;
613 struct drm_crtc *crtc_from_state;
614
c2cea706
LSL		 615 for_each_new_connector_in_state(state, connector, new_con_state, i) {
616 crtc_from_state = new_con_state->crtc;
4562236b
HW		 617
618 if (crtc_from_state == crtc)
c84dec2f 619 return to_amdgpu_dm_connector(connector);
4562236b
HW		 620 }
621
622 return NULL;
623}
624
4562236b
HW		 625static int dm_resume(void *handle)
626{
627 struct amdgpu_device *adev = handle;
628 struct amdgpu_display_manager *dm = &adev->dm;
629
630 /* power on hardware */
631 dc_set_power_state(
632 dm->dc,
a3621485
AG		 633 DC_ACPI_CM_POWER_STATE_D0
634 );
4562236b
HW		 635
636 return 0;
637}
638
1ecfc3da 639int amdgpu_dm_display_resume(struct amdgpu_device *adev)
4562236b
HW		 640{
641 struct drm_device *ddev = adev->ddev;
642 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 643 struct amdgpu_dm_connector *aconnector;
4562236b 644 struct drm_connector *connector;
4562236b 645 struct drm_crtc *crtc;
c2cea706 646 struct drm_crtc_state *new_crtc_state;
4f346e65
LSL		 647 struct dm_crtc_state *dm_crtc_state;
648 struct drm_plane *plane;
649 struct drm_plane_state *plane_state;
650 struct dm_plane_state *dm_plane_state;
651 struct dm_atomic_state *cached_state;
a3621485
AG		 652 int ret = 0;
653 int i;
4562236b
HW		 654
655 /* program HPD filter */
656 dc_resume(dm->dc);
657
658 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
659 s3_handle_mst(ddev, false);
660
661 /*
662 * early enable HPD Rx IRQ, should be done before set mode as short
663 * pulse interrupts are used for MST
664 */
665 amdgpu_dm_irq_resume_early(adev);
666
4562236b
HW		 667 /* Do detection*/
668 list_for_each_entry(connector,
669 &ddev->mode_config.connector_list, head) {
c84dec2f 670 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 671
672 /*
673 * this is the case when traversing through already created
674 * MST connectors, should be skipped
675 */
676 if (aconnector->mst_port)
677 continue;
678
03ea364c 679 mutex_lock(&aconnector->hpd_lock);
8f38b66c 680 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4562236b
HW		 681 aconnector->dc_sink = NULL;
682 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 683 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 684 }
685
a3621485 686 /* Force mode set in atomic comit */
c2cea706
LSL		 687 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
688 new_crtc_state->active_changed = true;
a3621485 689
4f346e65
LSL		 690 cached_state = to_dm_atomic_state(adev->dm.cached_state);
691
692 /*
693 * During suspend, the cached state is saved before all streams are
694 * disabled. Refresh cached state to match actual current state before
695 * restoring it.
696 */
697 WARN_ON(kref_read(&cached_state->context->refcount) > 1);
698 dc_release_state(cached_state->context);
699
700 cached_state->context = dc_create_state();
5771ec8f 701 ASSERT(cached_state->context);
4f346e65
LSL		 702 dc_resource_state_copy_construct_current(adev->dm.dc, cached_state->context);
703
704 for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
705 dm_crtc_state = to_dm_crtc_state(new_crtc_state);
706 if (dm_crtc_state->stream) {
707 WARN_ON(kref_read(&dm_crtc_state->stream->refcount) > 1);
708 dc_stream_release(dm_crtc_state->stream);
709 dm_crtc_state->stream = NULL;
710 }
711 }
712
713 for_each_new_plane_in_state(adev->dm.cached_state, plane, plane_state, i) {
714 dm_plane_state = to_dm_plane_state(plane_state);
715 if (dm_plane_state->dc_state) {
716 WARN_ON(kref_read(&dm_plane_state->dc_state->refcount) > 1);
717 dc_plane_state_release(dm_plane_state->dc_state);
718 dm_plane_state->dc_state = NULL;
719 }
720 }
721
a3621485 722 ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
4562236b 723
0a214e2f
AG		 724 drm_atomic_state_put(adev->dm.cached_state);
725 adev->dm.cached_state = NULL;
726
9faa4237 727 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 728
729 return ret;
730}
731
732static const struct amd_ip_funcs amdgpu_dm_funcs = {
733 .name = "dm",
734 .early_init = dm_early_init,
7abcf6b5 735 .late_init = dm_late_init,
4562236b
HW		 736 .sw_init = dm_sw_init,
737 .sw_fini = dm_sw_fini,
738 .hw_init = dm_hw_init,
739 .hw_fini = dm_hw_fini,
740 .suspend = dm_suspend,
741 .resume = dm_resume,
742 .is_idle = dm_is_idle,
743 .wait_for_idle = dm_wait_for_idle,
744 .check_soft_reset = dm_check_soft_reset,
745 .soft_reset = dm_soft_reset,
746 .set_clockgating_state = dm_set_clockgating_state,
747 .set_powergating_state = dm_set_powergating_state,
748};
749
750const struct amdgpu_ip_block_version dm_ip_block =
751{
752 .type = AMD_IP_BLOCK_TYPE_DCE,
753 .major = 1,
754 .minor = 0,
755 .rev = 0,
756 .funcs = &amdgpu_dm_funcs,
757};
758
ca3268c4 759
7578ecda 760static struct drm_atomic_state *
ca3268c4
HW		 761dm_atomic_state_alloc(struct drm_device *dev)
762{
763 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
764
1dc90497 765 if (!state)
ca3268c4 766 return NULL;
1dc90497
AG		 767
768 if (drm_atomic_state_init(dev, &state->base) < 0)
769 goto fail;
770
ca3268c4 771 return &state->base;
1dc90497
AG		 772
773fail:
774 kfree(state);
775 return NULL;
ca3268c4
HW		 776}
777
0a323b84
AG		 778static void
779dm_atomic_state_clear(struct drm_atomic_state *state)
780{
781 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
782
783 if (dm_state->context) {
608ac7bb 784 dc_release_state(dm_state->context);
0a323b84
AG		 785 dm_state->context = NULL;
786 }
787
788 drm_atomic_state_default_clear(state);
789}
790
791static void
792dm_atomic_state_alloc_free(struct drm_atomic_state *state)
793{
794 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
795 drm_atomic_state_default_release(state);
796 kfree(dm_state);
797}
798
b3663f70 799static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
a49dcb88
HW		 800 .fb_create = amdgpu_user_framebuffer_create,
801 .output_poll_changed = amdgpu_output_poll_changed,
4562236b 802 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 803 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 804 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 805 .atomic_state_clear = dm_atomic_state_clear,
806 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 807};
808
809static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
810 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 811};
812
7578ecda 813static void
3ee6b26b 814amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 815{
816 struct drm_connector *connector = &aconnector->base;
817 struct drm_device *dev = connector->dev;
b73a22d3 818 struct dc_sink *sink;
4562236b
HW		 819
820 /* MST handled by drm_mst framework */
821 if (aconnector->mst_mgr.mst_state == true)
822 return;
823
824
825 sink = aconnector->dc_link->local_sink;
826
827 /* Edid mgmt connector gets first update only in mode_valid hook and then
828 * the connector sink is set to either fake or physical sink depends on link status.
829 * don't do it here if u are during boot
830 */
831 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
832 && aconnector->dc_em_sink) {
833
ab2541b6 834 /* For S3 resume with headless use eml_sink to fake stream
4562236b
HW		 835 * because on resume connecotr->sink is set ti NULL
836 */
837 mutex_lock(&dev->mode_config.mutex);
838
839 if (sink) {
922aa1e1 840 if (aconnector->dc_sink) {
4562236b
HW		 841 amdgpu_dm_remove_sink_from_freesync_module(
842 connector);
922aa1e1
AG		 843 /* retain and release bellow are used for
844 * bump up refcount for sink because the link don't point
845 * to it anymore after disconnect so on next crtc to connector
846 * reshuffle by UMD we will get into unwanted dc_sink release
847 */
848 if (aconnector->dc_sink != aconnector->dc_em_sink)
849 dc_sink_release(aconnector->dc_sink);
850 }
4562236b
HW		 851 aconnector->dc_sink = sink;
852 amdgpu_dm_add_sink_to_freesync_module(
853 connector, aconnector->edid);
854 } else {
855 amdgpu_dm_remove_sink_from_freesync_module(connector);
856 if (!aconnector->dc_sink)
857 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 858 else if (aconnector->dc_sink != aconnector->dc_em_sink)
859 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 860 }
861
862 mutex_unlock(&dev->mode_config.mutex);
863 return;
864 }
865
866 /*
867 * TODO: temporary guard to look for proper fix
868 * if this sink is MST sink, we should not do anything
869 */
870 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
871 return;
872
873 if (aconnector->dc_sink == sink) {
874 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
875 * Do nothing!! */
f1ad2f5e 876 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 877 aconnector->connector_id);
878 return;
879 }
880
f1ad2f5e 881 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 882 aconnector->connector_id, aconnector->dc_sink, sink);
883
884 mutex_lock(&dev->mode_config.mutex);
885
886 /* 1. Update status of the drm connector
887 * 2. Send an event and let userspace tell us what to do */
888 if (sink) {
889 /* TODO: check if we still need the S3 mode update workaround.
890 * If yes, put it here. */
891 if (aconnector->dc_sink)
892 amdgpu_dm_remove_sink_from_freesync_module(
893 connector);
894
895 aconnector->dc_sink = sink;
896 if (sink->dc_edid.length == 0)
897 aconnector->edid = NULL;
898 else {
899 aconnector->edid =
900 (struct edid *) sink->dc_edid.raw_edid;
901
902
903 drm_mode_connector_update_edid_property(connector,
904 aconnector->edid);
905 }
906 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
907
908 } else {
909 amdgpu_dm_remove_sink_from_freesync_module(connector);
910 drm_mode_connector_update_edid_property(connector, NULL);
911 aconnector->num_modes = 0;
912 aconnector->dc_sink = NULL;
913 }
914
915 mutex_unlock(&dev->mode_config.mutex);
916}
917
918static void handle_hpd_irq(void *param)
919{
c84dec2f 920 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 921 struct drm_connector *connector = &aconnector->base;
922 struct drm_device *dev = connector->dev;
923
924 /* In case of failure or MST no need to update connector status or notify the OS
925 * since (for MST case) MST does this in it's own context.
926 */
927 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 928
929 if (aconnector->fake_enable)
930 aconnector->fake_enable = false;
931
8f38b66c 932 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 933 amdgpu_dm_update_connector_after_detect(aconnector);
934
935
936 drm_modeset_lock_all(dev);
937 dm_restore_drm_connector_state(dev, connector);
938 drm_modeset_unlock_all(dev);
939
940 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
941 drm_kms_helper_hotplug_event(dev);
942 }
943 mutex_unlock(&aconnector->hpd_lock);
944
945}
946
c84dec2f 947static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 948{
949 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
950 uint8_t dret;
951 bool new_irq_handled = false;
952 int dpcd_addr;
953 int dpcd_bytes_to_read;
954
955 const int max_process_count = 30;
956 int process_count = 0;
957
958 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
959
960 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
961 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
962 /* DPCD 0x200 - 0x201 for downstream IRQ */
963 dpcd_addr = DP_SINK_COUNT;
964 } else {
965 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
966 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
967 dpcd_addr = DP_SINK_COUNT_ESI;
968 }
969
970 dret = drm_dp_dpcd_read(
971 &aconnector->dm_dp_aux.aux,
972 dpcd_addr,
973 esi,
974 dpcd_bytes_to_read);
975
976 while (dret == dpcd_bytes_to_read &&
977 process_count < max_process_count) {
978 uint8_t retry;
979 dret = 0;
980
981 process_count++;
982
f1ad2f5e 983 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 984 /* handle HPD short pulse irq */
985 if (aconnector->mst_mgr.mst_state)
986 drm_dp_mst_hpd_irq(
987 &aconnector->mst_mgr,
988 esi,
989 &new_irq_handled);
4562236b
HW		 990
991 if (new_irq_handled) {
992 /* ACK at DPCD to notify down stream */
993 const int ack_dpcd_bytes_to_write =
994 dpcd_bytes_to_read - 1;
995
996 for (retry = 0; retry < 3; retry++) {
997 uint8_t wret;
998
999 wret = drm_dp_dpcd_write(
1000 &aconnector->dm_dp_aux.aux,
1001 dpcd_addr + 1,
1002 &esi[1],
1003 ack_dpcd_bytes_to_write);
1004 if (wret == ack_dpcd_bytes_to_write)
1005 break;
1006 }
1007
1008 /* check if there is new irq to be handle */
1009 dret = drm_dp_dpcd_read(
1010 &aconnector->dm_dp_aux.aux,
1011 dpcd_addr,
1012 esi,
1013 dpcd_bytes_to_read);
1014
1015 new_irq_handled = false;
1016 } else
1017 break;
1018 }
1019
1020 if (process_count == max_process_count)
f1ad2f5e 1021 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1022}
1023
1024static void handle_hpd_rx_irq(void *param)
1025{
c84dec2f 1026 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1027 struct drm_connector *connector = &aconnector->base;
1028 struct drm_device *dev = connector->dev;
1029 const struct dc_link *dc_link = aconnector->dc_link;
1030 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1031
1032 /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1033 * conflict, after implement i2c helper, this mutex should be
1034 * retired.
1035 */
1036 if (aconnector->dc_link->type != dc_connection_mst_branch)
1037 mutex_lock(&aconnector->hpd_lock);
1038
8ee65d7c 1039 if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
4562236b
HW		 1040 !is_mst_root_connector) {
1041 /* Downstream Port status changed. */
8f38b66c 1042 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPDRX)) {
4562236b
HW		 1043 amdgpu_dm_update_connector_after_detect(aconnector);
1044
1045
1046 drm_modeset_lock_all(dev);
1047 dm_restore_drm_connector_state(dev, connector);
1048 drm_modeset_unlock_all(dev);
1049
1050 drm_kms_helper_hotplug_event(dev);
1051 }
1052 }
1053 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1054 (dc_link->type == dc_connection_mst_branch))
1055 dm_handle_hpd_rx_irq(aconnector);
1056
1057 if (aconnector->dc_link->type != dc_connection_mst_branch)
1058 mutex_unlock(&aconnector->hpd_lock);
1059}
1060
1061static void register_hpd_handlers(struct amdgpu_device *adev)
1062{
1063 struct drm_device *dev = adev->ddev;
1064 struct drm_connector *connector;
c84dec2f 1065 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1066 const struct dc_link *dc_link;
1067 struct dc_interrupt_params int_params = {0};
1068
1069 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1070 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1071
1072 list_for_each_entry(connector,
1073 &dev->mode_config.connector_list, head) {
1074
c84dec2f 1075 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1076 dc_link = aconnector->dc_link;
1077
1078 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1079 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1080 int_params.irq_source = dc_link->irq_source_hpd;
1081
1082 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1083 handle_hpd_irq,
1084 (void *) aconnector);
1085 }
1086
1087 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1088
1089 /* Also register for DP short pulse (hpd_rx). */
1090 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1091 int_params.irq_source = dc_link->irq_source_hpd_rx;
1092
1093 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1094 handle_hpd_rx_irq,
1095 (void *) aconnector);
1096 }
1097 }
1098}
1099
1100/* Register IRQ sources and initialize IRQ callbacks */
1101static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1102{
1103 struct dc *dc = adev->dm.dc;
1104 struct common_irq_params *c_irq_params;
1105 struct dc_interrupt_params int_params = {0};
1106 int r;
1107 int i;
2c8ad2d5
AD		 1108 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1109
ff5ef992
AD		 1110 if (adev->asic_type == CHIP_VEGA10 ||
1111 adev->asic_type == CHIP_RAVEN)
2c8ad2d5 1112 client_id = AMDGPU_IH_CLIENTID_DCE;
4562236b
HW		 1113
1114 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1115 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1116
1117 /* Actions of amdgpu_irq_add_id():
1118 * 1. Register a set() function with base driver.
1119 * Base driver will call set() function to enable/disable an
1120 * interrupt in DC hardware.
1121 * 2. Register amdgpu_dm_irq_handler().
1122 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1123 * coming from DC hardware.
1124 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1125 * for acknowledging and handling. */
1126
b57de80a 1127 /* Use VBLANK interrupt */
e9029155 1128 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1129 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1130 if (r) {
1131 DRM_ERROR("Failed to add crtc irq id!\n");
1132 return r;
1133 }
1134
1135 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1136 int_params.irq_source =
3d761e79 1137 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1138
b57de80a 1139 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1140
1141 c_irq_params->adev = adev;
1142 c_irq_params->irq_src = int_params.irq_source;
1143
1144 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1145 dm_crtc_high_irq, c_irq_params);
1146 }
1147
3d761e79 1148 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1149 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1150 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1151 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1152 if (r) {
1153 DRM_ERROR("Failed to add page flip irq id!\n");
1154 return r;
1155 }
1156
1157 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1158 int_params.irq_source =
1159 dc_interrupt_to_irq_source(dc, i, 0);
1160
1161 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1162
1163 c_irq_params->adev = adev;
1164 c_irq_params->irq_src = int_params.irq_source;
1165
1166 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1167 dm_pflip_high_irq, c_irq_params);
1168
1169 }
1170
1171 /* HPD */
2c8ad2d5
AD		 1172 r = amdgpu_irq_add_id(adev, client_id,
1173 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1174 if (r) {
1175 DRM_ERROR("Failed to add hpd irq id!\n");
1176 return r;
1177 }
1178
1179 register_hpd_handlers(adev);
1180
1181 return 0;
1182}
1183
ff5ef992
AD		 1184#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1185/* Register IRQ sources and initialize IRQ callbacks */
1186static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1187{
1188 struct dc *dc = adev->dm.dc;
1189 struct common_irq_params *c_irq_params;
1190 struct dc_interrupt_params int_params = {0};
1191 int r;
1192 int i;
1193
1194 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1195 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1196
1197 /* Actions of amdgpu_irq_add_id():
1198 * 1. Register a set() function with base driver.
1199 * Base driver will call set() function to enable/disable an
1200 * interrupt in DC hardware.
1201 * 2. Register amdgpu_dm_irq_handler().
1202 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1203 * coming from DC hardware.
1204 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1205 * for acknowledging and handling.
1206 * */
1207
1208 /* Use VSTARTUP interrupt */
1209 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1210 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1211 i++) {
1212 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1213
1214 if (r) {
1215 DRM_ERROR("Failed to add crtc irq id!\n");
1216 return r;
1217 }
1218
1219 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1220 int_params.irq_source =
1221 dc_interrupt_to_irq_source(dc, i, 0);
1222
1223 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1224
1225 c_irq_params->adev = adev;
1226 c_irq_params->irq_src = int_params.irq_source;
1227
1228 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1229 dm_crtc_high_irq, c_irq_params);
1230 }
1231
1232 /* Use GRPH_PFLIP interrupt */
1233 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1234 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1235 i++) {
1236 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1237 if (r) {
1238 DRM_ERROR("Failed to add page flip irq id!\n");
1239 return r;
1240 }
1241
1242 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1243 int_params.irq_source =
1244 dc_interrupt_to_irq_source(dc, i, 0);
1245
1246 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1247
1248 c_irq_params->adev = adev;
1249 c_irq_params->irq_src = int_params.irq_source;
1250
1251 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1252 dm_pflip_high_irq, c_irq_params);
1253
1254 }
1255
1256 /* HPD */
1257 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1258 &adev->hpd_irq);
1259 if (r) {
1260 DRM_ERROR("Failed to add hpd irq id!\n");
1261 return r;
1262 }
1263
1264 register_hpd_handlers(adev);
1265
1266 return 0;
1267}
1268#endif
1269
4562236b
HW		 1270static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1271{
1272 int r;
1273
1274 adev->mode_info.mode_config_initialized = true;
1275
4562236b 1276 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1277 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1278
1279 adev->ddev->mode_config.max_width = 16384;
1280 adev->ddev->mode_config.max_height = 16384;
1281
1282 adev->ddev->mode_config.preferred_depth = 24;
1283 adev->ddev->mode_config.prefer_shadow = 1;
1284 /* indicate support of immediate flip */
1285 adev->ddev->mode_config.async_page_flip = true;
1286
1287 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1288
1289 r = amdgpu_modeset_create_props(adev);
1290 if (r)
1291 return r;
1292
1293 return 0;
1294}
1295
1296#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1297 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1298
1299static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1300{
1301 struct amdgpu_display_manager *dm = bl_get_data(bd);
1302
1303 if (dc_link_set_backlight_level(dm->backlight_link,
1304 bd->props.brightness, 0, 0))
1305 return 0;
1306 else
1307 return 1;
1308}
1309
1310static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1311{
1312 return bd->props.brightness;
1313}
1314
1315static const struct backlight_ops amdgpu_dm_backlight_ops = {
1316 .get_brightness = amdgpu_dm_backlight_get_brightness,
1317 .update_status = amdgpu_dm_backlight_update_status,
1318};
1319
7578ecda
AD		 1320static void
1321amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1322{
1323 char bl_name[16];
1324 struct backlight_properties props = { 0 };
1325
1326 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1327 props.type = BACKLIGHT_RAW;
1328
1329 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1330 dm->adev->ddev->primary->index);
1331
1332 dm->backlight_dev = backlight_device_register(bl_name,
1333 dm->adev->ddev->dev,
1334 dm,
1335 &amdgpu_dm_backlight_ops,
1336 &props);
1337
1338 if (NULL == dm->backlight_dev)
1339 DRM_ERROR("DM: Backlight registration failed!\n");
1340 else
f1ad2f5e 1341 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1342}
1343
1344#endif
1345
1346/* In this architecture, the association
1347 * connector -> encoder -> crtc
1348 * id not really requried. The crtc and connector will hold the
1349 * display_index as an abstraction to use with DAL component
1350 *
1351 * Returns 0 on success
1352 */
7578ecda 1353static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1354{
1355 struct amdgpu_display_manager *dm = &adev->dm;
1356 uint32_t i;
c84dec2f 1357 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1358 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1359 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1360 uint32_t link_cnt;
92f3ac40 1361 unsigned long possible_crtcs;
4562236b
HW		 1362
1363 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1364 if (amdgpu_dm_mode_config_init(dm->adev)) {
1365 DRM_ERROR("DM: Failed to initialize mode config\n");
f2a0f5e6 1366 return -1;
4562236b
HW		 1367 }
1368
3be5262e 1369 for (i = 0; i < dm->dc->caps.max_planes; i++) {
d4e13b0d
AD		 1370 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1371 GFP_KERNEL);
1372 if (!mode_info->planes[i]) {
3be5262e 1373 DRM_ERROR("KMS: Failed to allocate plane\n");
d4e13b0d
AD		 1374 goto fail_free_planes;
1375 }
1605b3be 1376 mode_info->planes[i]->base.type = mode_info->plane_type[i];
92f3ac40
LSL		 1377
1378 /*
1379 * HACK: IGT tests expect that each plane can only have one
1380 * one possible CRTC. For now, set one CRTC for each
1381 * plane that is not an underlay, but still allow multiple
1382 * CRTCs for underlay planes.
1383 */
1384 possible_crtcs = 1 << i;
1385 if (i >= dm->dc->caps.max_streams)
1386 possible_crtcs = 0xff;
1387
1388 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
d4e13b0d
AD		 1389 DRM_ERROR("KMS: Failed to initialize plane\n");
1390 goto fail_free_planes;
1391 }
1392 }
4562236b 1393
d4e13b0d
AD		 1394 for (i = 0; i < dm->dc->caps.max_streams; i++)
1395 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1396 DRM_ERROR("KMS: Failed to initialize crtc\n");
d4e13b0d 1397 goto fail_free_planes;
4562236b 1398 }
4562236b 1399
ab2541b6 1400 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1401
1402 /* loops over all connectors on the board */
1403 for (i = 0; i < link_cnt; i++) {
1404
1405 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1406 DRM_ERROR(
1407 "KMS: Cannot support more than %d display indexes\n",
1408 AMDGPU_DM_MAX_DISPLAY_INDEX);
1409 continue;
1410 }
1411
1412 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1413 if (!aconnector)
f2a0f5e6 1414 goto fail_free_planes;
4562236b
HW		 1415
1416 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1417 if (!aencoder) {
1418 goto fail_free_connector;
1419 }
1420
1421 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1422 DRM_ERROR("KMS: Failed to initialize encoder\n");
1423 goto fail_free_encoder;
1424 }
1425
1426 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1427 DRM_ERROR("KMS: Failed to initialize connector\n");
f2a0f5e6 1428 goto fail_free_encoder;
4562236b
HW		 1429 }
1430
8f38b66c
HW		 1431 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1432 DETECT_REASON_BOOT))
4562236b
HW		 1433 amdgpu_dm_update_connector_after_detect(aconnector);
1434 }
1435
1436 /* Software is initialized. Now we can register interrupt handlers. */
1437 switch (adev->asic_type) {
1438 case CHIP_BONAIRE:
1439 case CHIP_HAWAII:
cd4b356f
AD		 1440 case CHIP_KAVERI:
1441 case CHIP_KABINI:
1442 case CHIP_MULLINS:
4562236b
HW		 1443 case CHIP_TONGA:
1444 case CHIP_FIJI:
1445 case CHIP_CARRIZO:
1446 case CHIP_STONEY:
1447 case CHIP_POLARIS11:
1448 case CHIP_POLARIS10:
b264d345 1449 case CHIP_POLARIS12:
2c8ad2d5 1450 case CHIP_VEGA10:
4562236b
HW		 1451 if (dce110_register_irq_handlers(dm->adev)) {
1452 DRM_ERROR("DM: Failed to initialize IRQ\n");
d4e13b0d 1453 goto fail_free_encoder;
4562236b
HW		 1454 }
1455 break;
ff5ef992
AD		 1456#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1457 case CHIP_RAVEN:
1458 if (dcn10_register_irq_handlers(dm->adev)) {
1459 DRM_ERROR("DM: Failed to initialize IRQ\n");
1460 goto fail_free_encoder;
1461 }
79c24086
BL		 1462 /*
1463 * Temporary disable until pplib/smu interaction is implemented
1464 */
1465 dm->dc->debug.disable_stutter = true;
ff5ef992
AD		 1466 break;
1467#endif
4562236b
HW		 1468 default:
1469 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
d4e13b0d 1470 goto fail_free_encoder;
4562236b
HW		 1471 }
1472
1473 drm_mode_config_reset(dm->ddev);
1474
1475 return 0;
1476fail_free_encoder:
1477 kfree(aencoder);
1478fail_free_connector:
1479 kfree(aconnector);
d4e13b0d 1480fail_free_planes:
3be5262e 1481 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1482 kfree(mode_info->planes[i]);
4562236b
HW		 1483 return -1;
1484}
1485
7578ecda 1486static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1487{
1488 drm_mode_config_cleanup(dm->ddev);
1489 return;
1490}
1491
1492/******************************************************************************
1493 * amdgpu_display_funcs functions
1494 *****************************************************************************/
1495
1496/**
1497 * dm_bandwidth_update - program display watermarks
1498 *
1499 * @adev: amdgpu_device pointer
1500 *
1501 * Calculate and program the display watermarks and line buffer allocation.
1502 */
1503static void dm_bandwidth_update(struct amdgpu_device *adev)
1504{
49c07a99 1505 /* TODO: implement later */
4562236b
HW		 1506}
1507
1508static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1509 u8 level)
1510{
1511 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1512}
1513
1514static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1515{
1516 /* TODO: translate amdgpu_encoder to display_index and call DAL */
4562236b
HW		 1517 return 0;
1518}
1519
4562236b
HW		 1520static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1521 struct drm_file *filp)
1522{
1523 struct mod_freesync_params freesync_params;
ab2541b6 1524 uint8_t num_streams;
4562236b 1525 uint8_t i;
4562236b
HW		 1526
1527 struct amdgpu_device *adev = dev->dev_private;
1528 int r = 0;
1529
1530 /* Get freesync enable flag from DRM */
1531
ab2541b6 1532 num_streams = dc_get_current_stream_count(adev->dm.dc);
4562236b 1533
ab2541b6 1534 for (i = 0; i < num_streams; i++) {
0971c40e 1535 struct dc_stream_state *stream;
ab2541b6 1536 stream = dc_get_stream_at_index(adev->dm.dc, i);
4562236b
HW		 1537
1538 mod_freesync_update_state(adev->dm.freesync_module,
ab2541b6 1539 &stream, 1, &freesync_params);
4562236b
HW		 1540 }
1541
1542 return r;
1543}
1544
39cc5be2 1545static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1546 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1547 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1548 .vblank_wait = NULL,
1549 .backlight_set_level =
1550 dm_set_backlight_level,/* called unconditionally */
1551 .backlight_get_level =
1552 dm_get_backlight_level,/* called unconditionally */
1553 .hpd_sense = NULL,/* called unconditionally */
1554 .hpd_set_polarity = NULL, /* called unconditionally */
1555 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1556 .page_flip_get_scanoutpos =
1557 dm_crtc_get_scanoutpos,/* called unconditionally */
1558 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1559 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1560 .notify_freesync = amdgpu_notify_freesync,
1561
1562};
1563
1564#if defined(CONFIG_DEBUG_KERNEL_DC)
1565
3ee6b26b
AD		 1566static ssize_t s3_debug_store(struct device *device,
1567 struct device_attribute *attr,
1568 const char *buf,
1569 size_t count)
4562236b
HW		 1570{
1571 int ret;
1572 int s3_state;
1573 struct pci_dev *pdev = to_pci_dev(device);
1574 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1575 struct amdgpu_device *adev = drm_dev->dev_private;
1576
1577 ret = kstrtoint(buf, 0, &s3_state);
1578
1579 if (ret == 0) {
1580 if (s3_state) {
1581 dm_resume(adev);
1582 amdgpu_dm_display_resume(adev);
1583 drm_kms_helper_hotplug_event(adev->ddev);
1584 } else
1585 dm_suspend(adev);
1586 }
1587
1588 return ret == 0 ? count : 0;
1589}
1590
1591DEVICE_ATTR_WO(s3_debug);
1592
1593#endif
1594
1595static int dm_early_init(void *handle)
1596{
1597 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1598
d7ec53d9 1599 adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
4562236b
HW		 1600 amdgpu_dm_set_irq_funcs(adev);
1601
1602 switch (adev->asic_type) {
1603 case CHIP_BONAIRE:
1604 case CHIP_HAWAII:
1605 adev->mode_info.num_crtc = 6;
1606 adev->mode_info.num_hpd = 6;
1607 adev->mode_info.num_dig = 6;
3be5262e 1608 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1609 break;
cd4b356f
AD		 1610 case CHIP_KAVERI:
1611 adev->mode_info.num_crtc = 4;
1612 adev->mode_info.num_hpd = 6;
1613 adev->mode_info.num_dig = 7;
1614 adev->mode_info.plane_type = dm_plane_type_default;
1615 break;
1616 case CHIP_KABINI:
1617 case CHIP_MULLINS:
1618 adev->mode_info.num_crtc = 2;
1619 adev->mode_info.num_hpd = 6;
1620 adev->mode_info.num_dig = 6;
1621 adev->mode_info.plane_type = dm_plane_type_default;
1622 break;
4562236b
HW		 1623 case CHIP_FIJI:
1624 case CHIP_TONGA:
1625 adev->mode_info.num_crtc = 6;
1626 adev->mode_info.num_hpd = 6;
1627 adev->mode_info.num_dig = 7;
3be5262e 1628 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1629 break;
1630 case CHIP_CARRIZO:
1631 adev->mode_info.num_crtc = 3;
1632 adev->mode_info.num_hpd = 6;
1633 adev->mode_info.num_dig = 9;
3be5262e 1634 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1635 break;
1636 case CHIP_STONEY:
1637 adev->mode_info.num_crtc = 2;
1638 adev->mode_info.num_hpd = 6;
1639 adev->mode_info.num_dig = 9;
3be5262e 1640 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1641 break;
1642 case CHIP_POLARIS11:
b264d345 1643 case CHIP_POLARIS12:
4562236b
HW		 1644 adev->mode_info.num_crtc = 5;
1645 adev->mode_info.num_hpd = 5;
1646 adev->mode_info.num_dig = 5;
3be5262e 1647 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1648 break;
1649 case CHIP_POLARIS10:
1650 adev->mode_info.num_crtc = 6;
1651 adev->mode_info.num_hpd = 6;
1652 adev->mode_info.num_dig = 6;
3be5262e 1653 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1654 break;
2c8ad2d5
AD		 1655 case CHIP_VEGA10:
1656 adev->mode_info.num_crtc = 6;
1657 adev->mode_info.num_hpd = 6;
1658 adev->mode_info.num_dig = 6;
3be5262e 1659 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1660 break;
ff5ef992
AD		 1661#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1662 case CHIP_RAVEN:
1663 adev->mode_info.num_crtc = 4;
1664 adev->mode_info.num_hpd = 4;
1665 adev->mode_info.num_dig = 4;
3be5262e 1666 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1667 break;
1668#endif
4562236b
HW		 1669 default:
1670 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1671 return -EINVAL;
1672 }
1673
39cc5be2
AD		 1674 if (adev->mode_info.funcs == NULL)
1675 adev->mode_info.funcs = &dm_display_funcs;
1676
4562236b
HW		 1677 /* Note: Do NOT change adev->audio_endpt_rreg and
1678 * adev->audio_endpt_wreg because they are initialised in
1679 * amdgpu_device_init() */
1680#if defined(CONFIG_DEBUG_KERNEL_DC)
1681 device_create_file(
1682 adev->ddev->dev,
1683 &dev_attr_s3_debug);
1684#endif
1685
1686 return 0;
1687}
1688
e7b07cee
HW		 1689struct dm_connector_state {
1690 struct drm_connector_state base;
1691
1692 enum amdgpu_rmx_type scaling;
1693 uint8_t underscan_vborder;
1694 uint8_t underscan_hborder;
1695 bool underscan_enable;
1696};
1697
1698#define to_dm_connector_state(x)\
1699 container_of((x), struct dm_connector_state, base)
1700
9b690ef3 1701static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1702 struct dc_stream_state *new_stream,
1703 struct dc_stream_state *old_stream)
9b690ef3 1704{
e7b07cee
HW		 1705 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1706 return false;
1707
1708 if (!crtc_state->enable)
1709 return false;
1710
1711 return crtc_state->active;
1712}
1713
1714static bool modereset_required(struct drm_crtc_state *crtc_state)
1715{
1716 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1717 return false;
1718
1719 return !crtc_state->enable || !crtc_state->active;
1720}
1721
7578ecda 1722static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1723{
1724 drm_encoder_cleanup(encoder);
1725 kfree(encoder);
1726}
1727
1728static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1729 .destroy = amdgpu_dm_encoder_destroy,
1730};
1731
3ee6b26b
AD		 1732static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1733 struct dc_plane_state *plane_state)
e7b07cee 1734{
3be5262e
HW		 1735 plane_state->src_rect.x = state->src_x >> 16;
1736 plane_state->src_rect.y = state->src_y >> 16;
e7b07cee 1737 /*we ignore for now mantissa and do not to deal with floating pixels :(*/
3be5262e 1738 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1739
3be5262e 1740 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1741 return false;
1742
3be5262e
HW		 1743 plane_state->src_rect.height = state->src_h >> 16;
1744 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1745 return false;
1746
3be5262e
HW		 1747 plane_state->dst_rect.x = state->crtc_x;
1748 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1749
1750 if (state->crtc_w == 0)
1751 return false;
1752
3be5262e 1753 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1754
1755 if (state->crtc_h == 0)
1756 return false;
1757
3be5262e 1758 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1759
3be5262e 1760 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1761
1762 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1763 case DRM_MODE_ROTATE_0:
3be5262e 1764 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1765 break;
1766 case DRM_MODE_ROTATE_90:
3be5262e 1767 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1768 break;
1769 case DRM_MODE_ROTATE_180:
3be5262e 1770 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1771 break;
1772 case DRM_MODE_ROTATE_270:
3be5262e 1773 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1774 break;
1775 default:
3be5262e 1776 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1777 break;
1778 }
1779
4562236b
HW		 1780 return true;
1781}
3ee6b26b
AD		 1782static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1783 uint64_t *tiling_flags,
1784 uint64_t *fb_location)
e7b07cee
HW		 1785{
1786 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1787 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1788
e7b07cee 1789 if (unlikely(r)) {
9bbc3031
JZ		 1790 // Don't show error msg. when return -ERESTARTSYS
1791 if (r != -ERESTARTSYS)
1792 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1793 return r;
1794 }
1795
1796 if (fb_location)
1797 *fb_location = amdgpu_bo_gpu_offset(rbo);
1798
1799 if (tiling_flags)
1800 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1801
1802 amdgpu_bo_unreserve(rbo);
1803
1804 return r;
1805}
1806
3ee6b26b
AD		 1807static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1808 struct dc_plane_state *plane_state,
1809 const struct amdgpu_framebuffer *amdgpu_fb,
1810 bool addReq)
e7b07cee
HW		 1811{
1812 uint64_t tiling_flags;
1813 uint64_t fb_location = 0;
1814 unsigned int awidth;
1815 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1816 int ret = 0;
1817 struct drm_format_name_buf format_name;
1818
1819 ret = get_fb_info(
1820 amdgpu_fb,
1821 &tiling_flags,
1822 addReq == true ? &fb_location:NULL);
1823
1824 if (ret)
1825 return ret;
1826
1827 switch (fb->format->format) {
1828 case DRM_FORMAT_C8:
3be5262e 1829 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 1830 break;
1831 case DRM_FORMAT_RGB565:
3be5262e 1832 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 1833 break;
1834 case DRM_FORMAT_XRGB8888:
1835 case DRM_FORMAT_ARGB8888:
3be5262e 1836 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 1837 break;
1838 case DRM_FORMAT_XRGB2101010:
1839 case DRM_FORMAT_ARGB2101010:
3be5262e 1840 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 1841 break;
1842 case DRM_FORMAT_XBGR2101010:
1843 case DRM_FORMAT_ABGR2101010:
3be5262e 1844 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee
HW		 1845 break;
1846 case DRM_FORMAT_NV21:
3be5262e 1847 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 1848 break;
1849 case DRM_FORMAT_NV12:
3be5262e 1850 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 1851 break;
1852 default:
1853 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 1854 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 1855 return -EINVAL;
1856 }
1857
3be5262e
HW		 1858 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1859 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1860 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1861 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1862 plane_state->plane_size.grph.surface_size.x = 0;
1863 plane_state->plane_size.grph.surface_size.y = 0;
1864 plane_state->plane_size.grph.surface_size.width = fb->width;
1865 plane_state->plane_size.grph.surface_size.height = fb->height;
1866 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 1867 fb->pitches[0] / fb->format->cpp[0];
1868 /* TODO: unhardcode */
3be5262e 1869 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 1870
1871 } else {
1872 awidth = ALIGN(fb->width, 64);
3be5262e
HW		 1873 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1874 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 1875 = lower_32_bits(fb_location);
3be5262e 1876 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 1877 = lower_32_bits(fb_location) +
1878 (awidth * fb->height);
3be5262e
HW		 1879 plane_state->plane_size.video.luma_size.x = 0;
1880 plane_state->plane_size.video.luma_size.y = 0;
1881 plane_state->plane_size.video.luma_size.width = awidth;
1882 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 1883 /* TODO: unhardcode */
3be5262e 1884 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 1885
3be5262e
HW		 1886 plane_state->plane_size.video.chroma_size.x = 0;
1887 plane_state->plane_size.video.chroma_size.y = 0;
1888 plane_state->plane_size.video.chroma_size.width = awidth;
1889 plane_state->plane_size.video.chroma_size.height = fb->height;
1890 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 1891
1892 /* TODO: unhardcode */
3be5262e 1893 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 1894 }
1895
3be5262e 1896 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 1897
b830ebc9
HW		 1898 /* Fill GFX8 params */
1899 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1900 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 1901
1902 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1903 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1904 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1905 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1906 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1907
1908 /* XXX fix me for VI */
3be5262e
HW		 1909 plane_state->tiling_info.gfx8.num_banks = num_banks;
1910 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 1911 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 1912 plane_state->tiling_info.gfx8.tile_split = tile_split;
1913 plane_state->tiling_info.gfx8.bank_width = bankw;
1914 plane_state->tiling_info.gfx8.bank_height = bankh;
1915 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1916 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 1917 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1918 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1919 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 1920 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 1921 }
1922
3be5262e 1923 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 1924 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1925
1926 if (adev->asic_type == CHIP_VEGA10 ||
1927 adev->asic_type == CHIP_RAVEN) {
1928 /* Fill GFX9 params */
3be5262e 1929 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 1930 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 1931 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 1932 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 1933 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 1934 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 1935 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 1936 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 1937 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 1938 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 1939 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 1940 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 1941 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 1942 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 1943 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 1944 }
1945
3be5262e
HW		 1946 plane_state->visible = true;
1947 plane_state->scaling_quality.h_taps_c = 0;
1948 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 1949
3be5262e
HW		 1950 /* is this needed? is plane_state zeroed at allocation? */
1951 plane_state->scaling_quality.h_taps = 0;
1952 plane_state->scaling_quality.v_taps = 0;
1953 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 1954
1955 return ret;
1956
1957}
1958
3ee6b26b
AD		 1959static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
1960 struct dc_plane_state *plane_state)
e7b07cee
HW		 1961{
1962 int i;
1963 struct dc_gamma *gamma;
d66cf5f5
AK		 1964 struct drm_color_lut *lut =
1965 (struct drm_color_lut *) crtc_state->gamma_lut->data;
e7b07cee
HW		 1966
1967 gamma = dc_create_gamma();
1968
1969 if (gamma == NULL) {
1970 WARN_ON(1);
1971 return;
1972 }
1973
7483bed4
HW		 1974 gamma->type = GAMMA_RGB_256;
1975 gamma->num_entries = GAMMA_RGB_256_ENTRIES;
d66cf5f5
AK		 1976 for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
1977 gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
1978 gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
1979 gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
e7b07cee
HW		 1980 }
1981
3be5262e 1982 plane_state->gamma_correction = gamma;
e7b07cee
HW		 1983}
1984
3ee6b26b
AD		 1985static int fill_plane_attributes(struct amdgpu_device *adev,
1986 struct dc_plane_state *dc_plane_state,
1987 struct drm_plane_state *plane_state,
1988 struct drm_crtc_state *crtc_state,
1989 bool addrReq)
e7b07cee
HW		 1990{
1991 const struct amdgpu_framebuffer *amdgpu_fb =
1992 to_amdgpu_framebuffer(plane_state->fb);
1993 const struct drm_crtc *crtc = plane_state->crtc;
1994 struct dc_transfer_func *input_tf;
1995 int ret = 0;
1996
3be5262e 1997 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 1998 return -EINVAL;
1999
2000 ret = fill_plane_attributes_from_fb(
2001 crtc->dev->dev_private,
3be5262e 2002 dc_plane_state,
e7b07cee
HW		 2003 amdgpu_fb,
2004 addrReq);
2005
2006 if (ret)
2007 return ret;
2008
2009 input_tf = dc_create_transfer_func();
2010
2011 if (input_tf == NULL)
2012 return -ENOMEM;
2013
2014 input_tf->type = TF_TYPE_PREDEFINED;
2015 input_tf->tf = TRANSFER_FUNCTION_SRGB;
2016
3be5262e 2017 dc_plane_state->in_transfer_func = input_tf;
e7b07cee
HW		 2018
2019 /* In case of gamma set, update gamma value */
2020 if (crtc_state->gamma_lut)
3be5262e 2021 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
e7b07cee
HW		 2022
2023 return ret;
2024}
2025
2026/*****************************************************************************/
2027
3ee6b26b
AD		 2028static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2029 const struct dm_connector_state *dm_state,
2030 struct dc_stream_state *stream)
e7b07cee
HW		 2031{
2032 enum amdgpu_rmx_type rmx_type;
2033
2034 struct rect src = { 0 }; /* viewport in composition space*/
2035 struct rect dst = { 0 }; /* stream addressable area */
2036
2037 /* no mode. nothing to be done */
2038 if (!mode)
2039 return;
2040
2041 /* Full screen scaling by default */
2042 src.width = mode->hdisplay;
2043 src.height = mode->vdisplay;
2044 dst.width = stream->timing.h_addressable;
2045 dst.height = stream->timing.v_addressable;
2046
2047 rmx_type = dm_state->scaling;
2048 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2049 if (src.width * dst.height <
2050 src.height * dst.width) {
2051 /* height needs less upscaling/more downscaling */
2052 dst.width = src.width *
2053 dst.height / src.height;
2054 } else {
2055 /* width needs less upscaling/more downscaling */
2056 dst.height = src.height *
2057 dst.width / src.width;
2058 }
2059 } else if (rmx_type == RMX_CENTER) {
2060 dst = src;
2061 }
2062
2063 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2064 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2065
2066 if (dm_state->underscan_enable) {
2067 dst.x += dm_state->underscan_hborder / 2;
2068 dst.y += dm_state->underscan_vborder / 2;
2069 dst.width -= dm_state->underscan_hborder;
2070 dst.height -= dm_state->underscan_vborder;
2071 }
2072
2073 stream->src = src;
2074 stream->dst = dst;
2075
f1ad2f5e 2076 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2077 dst.x, dst.y, dst.width, dst.height);
2078
2079}
2080
3ee6b26b
AD		 2081static enum dc_color_depth
2082convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2083{
2084 uint32_t bpc = connector->display_info.bpc;
2085
2086 /* Limited color depth to 8bit
b830ebc9
HW		 2087 * TODO: Still need to handle deep color
2088 */
e7b07cee
HW		 2089 if (bpc > 8)
2090 bpc = 8;
2091
2092 switch (bpc) {
2093 case 0:
2094 /* Temporary Work around, DRM don't parse color depth for
2095 * EDID revision before 1.4
2096 * TODO: Fix edid parsing
2097 */
2098 return COLOR_DEPTH_888;
2099 case 6:
2100 return COLOR_DEPTH_666;
2101 case 8:
2102 return COLOR_DEPTH_888;
2103 case 10:
2104 return COLOR_DEPTH_101010;
2105 case 12:
2106 return COLOR_DEPTH_121212;
2107 case 14:
2108 return COLOR_DEPTH_141414;
2109 case 16:
2110 return COLOR_DEPTH_161616;
2111 default:
2112 return COLOR_DEPTH_UNDEFINED;
2113 }
2114}
2115
3ee6b26b
AD		 2116static enum dc_aspect_ratio
2117get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee
HW		 2118{
2119 int32_t width = mode_in->crtc_hdisplay * 9;
2120 int32_t height = mode_in->crtc_vdisplay * 16;
b830ebc9 2121
e7b07cee
HW		 2122 if ((width - height) < 10 && (width - height) > -10)
2123 return ASPECT_RATIO_16_9;
2124 else
2125 return ASPECT_RATIO_4_3;
2126}
2127
3ee6b26b
AD		 2128static enum dc_color_space
2129get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2130{
2131 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2132
2133 switch (dc_crtc_timing->pixel_encoding) {
2134 case PIXEL_ENCODING_YCBCR422:
2135 case PIXEL_ENCODING_YCBCR444:
2136 case PIXEL_ENCODING_YCBCR420:
2137 {
2138 /*
2139 * 27030khz is the separation point between HDTV and SDTV
2140 * according to HDMI spec, we use YCbCr709 and YCbCr601
2141 * respectively
2142 */
2143 if (dc_crtc_timing->pix_clk_khz > 27030) {
2144 if (dc_crtc_timing->flags.Y_ONLY)
2145 color_space =
2146 COLOR_SPACE_YCBCR709_LIMITED;
2147 else
2148 color_space = COLOR_SPACE_YCBCR709;
2149 } else {
2150 if (dc_crtc_timing->flags.Y_ONLY)
2151 color_space =
2152 COLOR_SPACE_YCBCR601_LIMITED;
2153 else
2154 color_space = COLOR_SPACE_YCBCR601;
2155 }
2156
2157 }
2158 break;
2159 case PIXEL_ENCODING_RGB:
2160 color_space = COLOR_SPACE_SRGB;
2161 break;
2162
2163 default:
2164 WARN_ON(1);
2165 break;
2166 }
2167
2168 return color_space;
2169}
2170
2171/*****************************************************************************/
2172
3ee6b26b
AD		 2173static void
2174fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2175 const struct drm_display_mode *mode_in,
2176 const struct drm_connector *connector)
e7b07cee
HW		 2177{
2178 struct dc_crtc_timing *timing_out = &stream->timing;
b830ebc9 2179
e7b07cee
HW		 2180 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2181
2182 timing_out->h_border_left = 0;
2183 timing_out->h_border_right = 0;
2184 timing_out->v_border_top = 0;
2185 timing_out->v_border_bottom = 0;
2186 /* TODO: un-hardcode */
2187
2188 if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2189 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2190 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2191 else
2192 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2193
2194 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2195 timing_out->display_color_depth = convert_color_depth_from_display_info(
2196 connector);
2197 timing_out->scan_type = SCANNING_TYPE_NODATA;
2198 timing_out->hdmi_vic = 0;
2199 timing_out->vic = drm_match_cea_mode(mode_in);
2200
2201 timing_out->h_addressable = mode_in->crtc_hdisplay;
2202 timing_out->h_total = mode_in->crtc_htotal;
2203 timing_out->h_sync_width =
2204 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2205 timing_out->h_front_porch =
2206 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2207 timing_out->v_total = mode_in->crtc_vtotal;
2208 timing_out->v_addressable = mode_in->crtc_vdisplay;
2209 timing_out->v_front_porch =
2210 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2211 timing_out->v_sync_width =
2212 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2213 timing_out->pix_clk_khz = mode_in->crtc_clock;
2214 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2215 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2216 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2217 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2218 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2219
2220 stream->output_color_space = get_output_color_space(timing_out);
2221
2222 {
2223 struct dc_transfer_func *tf = dc_create_transfer_func();
b830ebc9 2224
e7b07cee
HW		 2225 tf->type = TF_TYPE_PREDEFINED;
2226 tf->tf = TRANSFER_FUNCTION_SRGB;
2227 stream->out_transfer_func = tf;
2228 }
2229}
2230
3ee6b26b
AD		 2231static void fill_audio_info(struct audio_info *audio_info,
2232 const struct drm_connector *drm_connector,
2233 const struct dc_sink *dc_sink)
e7b07cee
HW		 2234{
2235 int i = 0;
2236 int cea_revision = 0;
2237 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2238
2239 audio_info->manufacture_id = edid_caps->manufacturer_id;
2240 audio_info->product_id = edid_caps->product_id;
2241
2242 cea_revision = drm_connector->display_info.cea_rev;
2243
2244 while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
2245 edid_caps->display_name[i]) {
2246 audio_info->display_name[i] = edid_caps->display_name[i];
2247 i++;
2248 }
2249
b830ebc9 2250 if (cea_revision >= 3) {
e7b07cee
HW		 2251 audio_info->mode_count = edid_caps->audio_mode_count;
2252
2253 for (i = 0; i < audio_info->mode_count; ++i) {
2254 audio_info->modes[i].format_code =
2255 (enum audio_format_code)
2256 (edid_caps->audio_modes[i].format_code);
2257 audio_info->modes[i].channel_count =
2258 edid_caps->audio_modes[i].channel_count;
2259 audio_info->modes[i].sample_rates.all =
2260 edid_caps->audio_modes[i].sample_rate;
2261 audio_info->modes[i].sample_size =
2262 edid_caps->audio_modes[i].sample_size;
2263 }
2264 }
2265
2266 audio_info->flags.all = edid_caps->speaker_flags;
2267
2268 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2269 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2270 audio_info->video_latency = drm_connector->video_latency[0];
2271 audio_info->audio_latency = drm_connector->audio_latency[0];
2272 }
2273
2274 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2275
2276}
2277
3ee6b26b
AD		 2278static void
2279copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2280 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2281{
2282 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2283 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2284 dst_mode->crtc_clock = src_mode->crtc_clock;
2285 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2286 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2287 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2288 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2289 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2290 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2291 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2292 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2293 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2294 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2295 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2296}
2297
3ee6b26b
AD		 2298static void
2299decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2300 const struct drm_display_mode *native_mode,
2301 bool scale_enabled)
e7b07cee
HW		 2302{
2303 if (scale_enabled) {
2304 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2305 } else if (native_mode->clock == drm_mode->clock &&
2306 native_mode->htotal == drm_mode->htotal &&
2307 native_mode->vtotal == drm_mode->vtotal) {
2308 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2309 } else {
2310 /* no scaling nor amdgpu inserted, no need to patch */
2311 }
2312}
2313
2e0ac3d6
HW		 2314static void create_fake_sink(struct amdgpu_dm_connector *aconnector)
2315{
2316 struct dc_sink *sink = NULL;
2317 struct dc_sink_init_data sink_init_data = { 0 };
2318
2319 sink_init_data.link = aconnector->dc_link;
2320 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2321
2322 sink = dc_sink_create(&sink_init_data);
2323 if (!sink)
2324 DRM_ERROR("Failed to create sink!\n");
2325
2326 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2327 aconnector->fake_enable = true;
2328
2329 aconnector->dc_sink = sink;
2330 aconnector->dc_link->local_sink = sink;
2331}
2332
3ee6b26b
AD		 2333static struct dc_stream_state *
2334create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2335 const struct drm_display_mode *drm_mode,
2336 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2337{
2338 struct drm_display_mode *preferred_mode = NULL;
2339 const struct drm_connector *drm_connector;
0971c40e 2340 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2341 struct drm_display_mode mode = *drm_mode;
2342 bool native_mode_found = false;
2343
b830ebc9 2344 if (aconnector == NULL) {
e7b07cee
HW		 2345 DRM_ERROR("aconnector is NULL!\n");
2346 goto drm_connector_null;
2347 }
2348
b830ebc9 2349 if (dm_state == NULL) {
e7b07cee
HW		 2350 DRM_ERROR("dm_state is NULL!\n");
2351 goto dm_state_null;
2352 }
4562236b 2353
e7b07cee 2354 drm_connector = &aconnector->base;
2e0ac3d6 2355
f4ac176e
JZ		 2356 if (!aconnector->dc_sink) {
2357 /*
2358 * Exclude MST from creating fake_sink
2359 * TODO: need to enable MST into fake_sink feature
2360 */
2361 if (aconnector->mst_port)
2362 goto stream_create_fail;
2363
2e0ac3d6 2364 create_fake_sink(aconnector);
f4ac176e 2365 }
2e0ac3d6 2366
e7b07cee 2367 stream = dc_create_stream_for_sink(aconnector->dc_sink);
4562236b 2368
b830ebc9 2369 if (stream == NULL) {
e7b07cee
HW		 2370 DRM_ERROR("Failed to create stream for sink!\n");
2371 goto stream_create_fail;
2372 }
2373
2374 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2375 /* Search for preferred mode */
2376 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2377 native_mode_found = true;
2378 break;
2379 }
2380 }
2381 if (!native_mode_found)
2382 preferred_mode = list_first_entry_or_null(
2383 &aconnector->base.modes,
2384 struct drm_display_mode,
2385 head);
2386
b830ebc9 2387 if (preferred_mode == NULL) {
e7b07cee
HW		 2388 /* This may not be an error, the use case is when we we have no
2389 * usermode calls to reset and set mode upon hotplug. In this
2390 * case, we call set mode ourselves to restore the previous mode
2391 * and the modelist may not be filled in in time.
2392 */
f1ad2f5e 2393 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2394 } else {
2395 decide_crtc_timing_for_drm_display_mode(
2396 &mode, preferred_mode,
2397 dm_state->scaling != RMX_OFF);
2398 }
2399
2400 fill_stream_properties_from_drm_display_mode(stream,
2401 &mode, &aconnector->base);
2402 update_stream_scaling_settings(&mode, dm_state, stream);
2403
2404 fill_audio_info(
2405 &stream->audio_info,
2406 drm_connector,
2407 aconnector->dc_sink);
2408
2409stream_create_fail:
2410dm_state_null:
2411drm_connector_null:
2412 return stream;
2413}
2414
7578ecda 2415static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2416{
2417 drm_crtc_cleanup(crtc);
2418 kfree(crtc);
2419}
2420
2421static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2422 struct drm_crtc_state *state)
e7b07cee
HW		 2423{
2424 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2425
2426 /* TODO Destroy dc_stream objects are stream object is flattened */
2427 if (cur->stream)
2428 dc_stream_release(cur->stream);
2429
2430
2431 __drm_atomic_helper_crtc_destroy_state(state);
2432
2433
2434 kfree(state);
2435}
2436
2437static void dm_crtc_reset_state(struct drm_crtc *crtc)
2438{
2439 struct dm_crtc_state *state;
2440
2441 if (crtc->state)
2442 dm_crtc_destroy_state(crtc, crtc->state);
2443
2444 state = kzalloc(sizeof(*state), GFP_KERNEL);
2445 if (WARN_ON(!state))
2446 return;
2447
2448 crtc->state = &state->base;
2449 crtc->state->crtc = crtc;
2450
2451}
2452
2453static struct drm_crtc_state *
2454dm_crtc_duplicate_state(struct drm_crtc *crtc)
2455{
2456 struct dm_crtc_state *state, *cur;
2457
2458 cur = to_dm_crtc_state(crtc->state);
2459
2460 if (WARN_ON(!crtc->state))
2461 return NULL;
2462
2004f45e 2463 state = kzalloc(sizeof(*state), GFP_KERNEL);
e7b07cee
HW		 2464
2465 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2466
2467 if (cur->stream) {
2468 state->stream = cur->stream;
2469 dc_stream_retain(state->stream);
2470 }
2471
2472 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2473
2474 return &state->base;
2475}
2476
2477/* Implemented only the options currently availible for the driver */
2478static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2479 .reset = dm_crtc_reset_state,
2480 .destroy = amdgpu_dm_crtc_destroy,
2481 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2482 .set_config = drm_atomic_helper_set_config,
2483 .page_flip = drm_atomic_helper_page_flip,
2484 .atomic_duplicate_state = dm_crtc_duplicate_state,
2485 .atomic_destroy_state = dm_crtc_destroy_state,
2486};
2487
2488static enum drm_connector_status
2489amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2490{
2491 bool connected;
c84dec2f 2492 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2493
2494 /* Notes:
2495 * 1. This interface is NOT called in context of HPD irq.
2496 * 2. This interface *is called* in context of user-mode ioctl. Which
2497 * makes it a bad place for *any* MST-related activit. */
2498
8580d60b
HW		 2499 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2500 !aconnector->fake_enable)
e7b07cee
HW		 2501 connected = (aconnector->dc_sink != NULL);
2502 else
2503 connected = (aconnector->base.force == DRM_FORCE_ON);
2504
2505 return (connected ? connector_status_connected :
2506 connector_status_disconnected);
2507}
2508
3ee6b26b
AD		 2509int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2510 struct drm_connector_state *connector_state,
2511 struct drm_property *property,
2512 uint64_t val)
e7b07cee
HW		 2513{
2514 struct drm_device *dev = connector->dev;
2515 struct amdgpu_device *adev = dev->dev_private;
2516 struct dm_connector_state *dm_old_state =
2517 to_dm_connector_state(connector->state);
2518 struct dm_connector_state *dm_new_state =
2519 to_dm_connector_state(connector_state);
2520
2521 int ret = -EINVAL;
2522
2523 if (property == dev->mode_config.scaling_mode_property) {
2524 enum amdgpu_rmx_type rmx_type;
2525
2526 switch (val) {
2527 case DRM_MODE_SCALE_CENTER:
2528 rmx_type = RMX_CENTER;
2529 break;
2530 case DRM_MODE_SCALE_ASPECT:
2531 rmx_type = RMX_ASPECT;
2532 break;
2533 case DRM_MODE_SCALE_FULLSCREEN:
2534 rmx_type = RMX_FULL;
2535 break;
2536 case DRM_MODE_SCALE_NONE:
2537 default:
2538 rmx_type = RMX_OFF;
2539 break;
2540 }
2541
2542 if (dm_old_state->scaling == rmx_type)
2543 return 0;
2544
2545 dm_new_state->scaling = rmx_type;
2546 ret = 0;
2547 } else if (property == adev->mode_info.underscan_hborder_property) {
2548 dm_new_state->underscan_hborder = val;
2549 ret = 0;
2550 } else if (property == adev->mode_info.underscan_vborder_property) {
2551 dm_new_state->underscan_vborder = val;
2552 ret = 0;
2553 } else if (property == adev->mode_info.underscan_property) {
2554 dm_new_state->underscan_enable = val;
2555 ret = 0;
2556 }
2557
2558 return ret;
2559}
2560
3ee6b26b
AD		 2561int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2562 const struct drm_connector_state *state,
2563 struct drm_property *property,
2564 uint64_t *val)
e7b07cee
HW		 2565{
2566 struct drm_device *dev = connector->dev;
2567 struct amdgpu_device *adev = dev->dev_private;
2568 struct dm_connector_state *dm_state =
2569 to_dm_connector_state(state);
2570 int ret = -EINVAL;
2571
2572 if (property == dev->mode_config.scaling_mode_property) {
2573 switch (dm_state->scaling) {
2574 case RMX_CENTER:
2575 *val = DRM_MODE_SCALE_CENTER;
2576 break;
2577 case RMX_ASPECT:
2578 *val = DRM_MODE_SCALE_ASPECT;
2579 break;
2580 case RMX_FULL:
2581 *val = DRM_MODE_SCALE_FULLSCREEN;
2582 break;
2583 case RMX_OFF:
2584 default:
2585 *val = DRM_MODE_SCALE_NONE;
2586 break;
2587 }
2588 ret = 0;
2589 } else if (property == adev->mode_info.underscan_hborder_property) {
2590 *val = dm_state->underscan_hborder;
2591 ret = 0;
2592 } else if (property == adev->mode_info.underscan_vborder_property) {
2593 *val = dm_state->underscan_vborder;
2594 ret = 0;
2595 } else if (property == adev->mode_info.underscan_property) {
2596 *val = dm_state->underscan_enable;
2597 ret = 0;
2598 }
2599 return ret;
2600}
2601
7578ecda 2602static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2603{
c84dec2f 2604 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2605 const struct dc_link *link = aconnector->dc_link;
2606 struct amdgpu_device *adev = connector->dev->dev_private;
2607 struct amdgpu_display_manager *dm = &adev->dm;
2608#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2609 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2610
2611 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2612 amdgpu_dm_register_backlight_device(dm);
2613
2614 if (dm->backlight_dev) {
2615 backlight_device_unregister(dm->backlight_dev);
2616 dm->backlight_dev = NULL;
2617 }
2618
2619 }
2620#endif
2621 drm_connector_unregister(connector);
2622 drm_connector_cleanup(connector);
2623 kfree(connector);
2624}
2625
2626void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2627{
2628 struct dm_connector_state *state =
2629 to_dm_connector_state(connector->state);
2630
2631 kfree(state);
2632
2633 state = kzalloc(sizeof(*state), GFP_KERNEL);
2634
2635 if (state) {
2636 state->scaling = RMX_OFF;
2637 state->underscan_enable = false;
2638 state->underscan_hborder = 0;
2639 state->underscan_vborder = 0;
2640
2641 connector->state = &state->base;
2642 connector->state->connector = connector;
2643 }
2644}
2645
3ee6b26b
AD		 2646struct drm_connector_state *
2647amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2648{
2649 struct dm_connector_state *state =
2650 to_dm_connector_state(connector->state);
2651
2652 struct dm_connector_state *new_state =
2653 kmemdup(state, sizeof(*state), GFP_KERNEL);
2654
2655 if (new_state) {
2656 __drm_atomic_helper_connector_duplicate_state(connector,
1ecfc3da 2657 &new_state->base);
e7b07cee
HW		 2658 return &new_state->base;
2659 }
2660
2661 return NULL;
2662}
2663
2664static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2665 .reset = amdgpu_dm_connector_funcs_reset,
2666 .detect = amdgpu_dm_connector_detect,
2667 .fill_modes = drm_helper_probe_single_connector_modes,
2668 .destroy = amdgpu_dm_connector_destroy,
2669 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2670 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2671 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2672 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2673};
2674
2675static struct drm_encoder *best_encoder(struct drm_connector *connector)
2676{
2677 int enc_id = connector->encoder_ids[0];
2678 struct drm_mode_object *obj;
2679 struct drm_encoder *encoder;
2680
f1ad2f5e 2681 DRM_DEBUG_DRIVER("Finding the best encoder\n");
e7b07cee
HW		 2682
2683 /* pick the encoder ids */
2684 if (enc_id) {
bd21a37d 2685 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
e7b07cee
HW		 2686 if (!obj) {
2687 DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2688 return NULL;
2689 }
2690 encoder = obj_to_encoder(obj);
2691 return encoder;
2692 }
2693 DRM_ERROR("No encoder id\n");
2694 return NULL;
2695}
2696
2697static int get_modes(struct drm_connector *connector)
2698{
2699 return amdgpu_dm_connector_get_modes(connector);
2700}
2701
c84dec2f 2702static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2703{
2704 struct dc_sink_init_data init_params = {
2705 .link = aconnector->dc_link,
2706 .sink_signal = SIGNAL_TYPE_VIRTUAL
2707 };
2708 struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2709
2710 if (!aconnector->base.edid_blob_ptr ||
2711 !aconnector->base.edid_blob_ptr->data) {
2712 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2713 aconnector->base.name);
2714
2715 aconnector->base.force = DRM_FORCE_OFF;
2716 aconnector->base.override_edid = false;
2717 return;
2718 }
2719
2720 aconnector->edid = edid;
2721
2722 aconnector->dc_em_sink = dc_link_add_remote_sink(
2723 aconnector->dc_link,
2724 (uint8_t *)edid,
2725 (edid->extensions + 1) * EDID_LENGTH,
2726 &init_params);
2727
2728 if (aconnector->base.force
2729 == DRM_FORCE_ON)
2730 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2731 aconnector->dc_link->local_sink :
2732 aconnector->dc_em_sink;
2733}
2734
c84dec2f 2735static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2736{
2737 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2738
2739 /* In case of headless boot with force on for DP managed connector
2740 * Those settings have to be != 0 to get initial modeset
2741 */
2742 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2743 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2744 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2745 }
2746
2747
2748 aconnector->base.override_edid = true;
2749 create_eml_sink(aconnector);
2750}
2751
3ee6b26b
AD		 2752int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2753 struct drm_display_mode *mode)
e7b07cee
HW		 2754{
2755 int result = MODE_ERROR;
2756 struct dc_sink *dc_sink;
2757 struct amdgpu_device *adev = connector->dev->dev_private;
2758 /* TODO: Unhardcode stream count */
0971c40e 2759 struct dc_stream_state *stream;
c84dec2f 2760 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2761
2762 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2763 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2764 return result;
2765
2766 /* Only run this the first time mode_valid is called to initilialize
2767 * EDID mgmt
2768 */
2769 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2770 !aconnector->dc_em_sink)
2771 handle_edid_mgmt(aconnector);
2772
c84dec2f 2773 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 2774
b830ebc9 2775 if (dc_sink == NULL) {
e7b07cee
HW		 2776 DRM_ERROR("dc_sink is NULL!\n");
2777 goto fail;
2778 }
2779
2780 stream = dc_create_stream_for_sink(dc_sink);
b830ebc9 2781 if (stream == NULL) {
e7b07cee
HW		 2782 DRM_ERROR("Failed to create stream for sink!\n");
2783 goto fail;
2784 }
2785
2786 drm_mode_set_crtcinfo(mode, 0);
2787 fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2788
2789 stream->src.width = mode->hdisplay;
2790 stream->src.height = mode->vdisplay;
2791 stream->dst = stream->src;
2792
62c933f9 2793 if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
e7b07cee
HW		 2794 result = MODE_OK;
2795
2796 dc_stream_release(stream);
2797
2798fail:
2799 /* TODO: error handling*/
2800 return result;
2801}
2802
2803static const struct drm_connector_helper_funcs
2804amdgpu_dm_connector_helper_funcs = {
2805 /*
b830ebc9
HW		 2806 * If hotplug a second bigger display in FB Con mode, bigger resolution
2807 * modes will be filtered by drm_mode_validate_size(), and those modes
2808 * is missing after user start lightdm. So we need to renew modes list.
2809 * in get_modes call back, not just return the modes count
2810 */
e7b07cee
HW		 2811 .get_modes = get_modes,
2812 .mode_valid = amdgpu_dm_connector_mode_valid,
2813 .best_encoder = best_encoder
2814};
2815
2816static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2817{
2818}
2819
3ee6b26b
AD		 2820static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2821 struct drm_crtc_state *state)
e7b07cee
HW		 2822{
2823 struct amdgpu_device *adev = crtc->dev->dev_private;
2824 struct dc *dc = adev->dm.dc;
2825 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2826 int ret = -EINVAL;
2827
9b690ef3
BL		 2828 if (unlikely(!dm_crtc_state->stream &&
2829 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 2830 WARN_ON(1);
2831 return ret;
2832 }
2833
2834 /* In some use cases, like reset, no stream is attached */
2835 if (!dm_crtc_state->stream)
2836 return 0;
2837
62c933f9 2838 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 2839 return 0;
2840
2841 return ret;
2842}
2843
3ee6b26b
AD		 2844static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2845 const struct drm_display_mode *mode,
2846 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 2847{
2848 return true;
2849}
2850
2851static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2852 .disable = dm_crtc_helper_disable,
2853 .atomic_check = dm_crtc_helper_atomic_check,
2854 .mode_fixup = dm_crtc_helper_mode_fixup
2855};
2856
2857static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2858{
2859
2860}
2861
3ee6b26b
AD		 2862static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2863 struct drm_crtc_state *crtc_state,
2864 struct drm_connector_state *conn_state)
e7b07cee
HW		 2865{
2866 return 0;
2867}
2868
2869const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2870 .disable = dm_encoder_helper_disable,
2871 .atomic_check = dm_encoder_helper_atomic_check
2872};
2873
2874static void dm_drm_plane_reset(struct drm_plane *plane)
2875{
2876 struct dm_plane_state *amdgpu_state = NULL;
2877
2878 if (plane->state)
2879 plane->funcs->atomic_destroy_state(plane, plane->state);
2880
2881 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2882
2883 if (amdgpu_state) {
2884 plane->state = &amdgpu_state->base;
2885 plane->state->plane = plane;
2886 plane->state->rotation = DRM_MODE_ROTATE_0;
2887 } else
2888 WARN_ON(1);
2889}
2890
2891static struct drm_plane_state *
2892dm_drm_plane_duplicate_state(struct drm_plane *plane)
2893{
2894 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2895
2896 old_dm_plane_state = to_dm_plane_state(plane->state);
2897 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2898 if (!dm_plane_state)
2899 return NULL;
2900
2901 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2902
3be5262e
HW		 2903 if (old_dm_plane_state->dc_state) {
2904 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2905 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 2906 }
2907
2908 return &dm_plane_state->base;
2909}
2910
2911void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 2912 struct drm_plane_state *state)
e7b07cee
HW		 2913{
2914 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2915
3be5262e
HW		 2916 if (dm_plane_state->dc_state)
2917 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 2918
0627bbd3 2919 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 2920}
2921
2922static const struct drm_plane_funcs dm_plane_funcs = {
2923 .update_plane = drm_atomic_helper_update_plane,
2924 .disable_plane = drm_atomic_helper_disable_plane,
2925 .destroy = drm_plane_cleanup,
2926 .reset = dm_drm_plane_reset,
2927 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2928 .atomic_destroy_state = dm_drm_plane_destroy_state,
2929};
2930
3ee6b26b
AD		 2931static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2932 struct drm_plane_state *new_state)
e7b07cee
HW		 2933{
2934 struct amdgpu_framebuffer *afb;
2935 struct drm_gem_object *obj;
2936 struct amdgpu_bo *rbo;
2937 int r;
2938 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2939 unsigned int awidth;
2940
2941 dm_plane_state_old = to_dm_plane_state(plane->state);
2942 dm_plane_state_new = to_dm_plane_state(new_state);
2943
2944 if (!new_state->fb) {
f1ad2f5e 2945 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 2946 return 0;
2947 }
2948
2949 afb = to_amdgpu_framebuffer(new_state->fb);
2950
2951 obj = afb->obj;
2952 rbo = gem_to_amdgpu_bo(obj);
2953 r = amdgpu_bo_reserve(rbo, false);
2954 if (unlikely(r != 0))
2955 return r;
2956
2957 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
2958
2959
2960 amdgpu_bo_unreserve(rbo);
2961
2962 if (unlikely(r != 0)) {
2963 DRM_ERROR("Failed to pin framebuffer\n");
2964 return r;
2965 }
2966
2967 amdgpu_bo_ref(rbo);
2968
3be5262e
HW		 2969 if (dm_plane_state_new->dc_state &&
2970 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2971 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 2972
3be5262e
HW		 2973 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2974 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2975 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 2976 } else {
2977 awidth = ALIGN(new_state->fb->width, 64);
3be5262e 2978 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 2979 = lower_32_bits(afb->address);
3be5262e 2980 plane_state->address.video_progressive.chroma_addr.low_part
e7b07cee
HW		 2981 = lower_32_bits(afb->address) +
2982 (awidth * new_state->fb->height);
2983 }
2984 }
2985
2986 /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
2987 * prepare and cleanup in drm_atomic_helper_prepare_planes
2988 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
2989 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
2990 * code touching fram buffers should be avoided for DC.
2991 */
2992 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
2993 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
2994
2995 acrtc->cursor_bo = obj;
2996 }
2997 return 0;
2998}
2999
3ee6b26b
AD		 3000static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3001 struct drm_plane_state *old_state)
e7b07cee
HW		 3002{
3003 struct amdgpu_bo *rbo;
3004 struct amdgpu_framebuffer *afb;
3005 int r;
3006
3007 if (!old_state->fb)
3008 return;
3009
3010 afb = to_amdgpu_framebuffer(old_state->fb);
3011 rbo = gem_to_amdgpu_bo(afb->obj);
3012 r = amdgpu_bo_reserve(rbo, false);
3013 if (unlikely(r)) {
3014 DRM_ERROR("failed to reserve rbo before unpin\n");
3015 return;
b830ebc9
HW		 3016 }
3017
3018 amdgpu_bo_unpin(rbo);
3019 amdgpu_bo_unreserve(rbo);
3020 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3021}
3022
7578ecda
AD		 3023static int dm_plane_atomic_check(struct drm_plane *plane,
3024 struct drm_plane_state *state)
cbd19488
AG		 3025{
3026 struct amdgpu_device *adev = plane->dev->dev_private;
3027 struct dc *dc = adev->dm.dc;
3028 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3029
3be5262e 3030 if (!dm_plane_state->dc_state)
9a3329b1 3031 return 0;
cbd19488 3032
62c933f9 3033 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3034 return 0;
3035
3036 return -EINVAL;
3037}
3038
e7b07cee
HW		 3039static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3040 .prepare_fb = dm_plane_helper_prepare_fb,
3041 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3042 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3043};
3044
3045/*
3046 * TODO: these are currently initialized to rgb formats only.
3047 * For future use cases we should either initialize them dynamically based on
3048 * plane capabilities, or initialize this array to all formats, so internal drm
3049 * check will succeed, and let DC to implement proper check
3050 */
d90371b0 3051static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3052 DRM_FORMAT_RGB888,
3053 DRM_FORMAT_XRGB8888,
3054 DRM_FORMAT_ARGB8888,
3055 DRM_FORMAT_RGBA8888,
3056 DRM_FORMAT_XRGB2101010,
3057 DRM_FORMAT_XBGR2101010,
3058 DRM_FORMAT_ARGB2101010,
3059 DRM_FORMAT_ABGR2101010,
3060};
3061
99d1abf8 3062static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3063 DRM_FORMAT_NV12,
3064 DRM_FORMAT_NV21,
3065};
3066
3067static const u32 cursor_formats[] = {
3068 DRM_FORMAT_ARGB8888
3069};
3070
7578ecda
AD		 3071static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3072 struct amdgpu_plane *aplane,
3073 unsigned long possible_crtcs)
e7b07cee
HW		 3074{
3075 int res = -EPERM;
3076
3077 switch (aplane->base.type) {
3078 case DRM_PLANE_TYPE_PRIMARY:
3079 aplane->base.format_default = true;
3080
3081 res = drm_universal_plane_init(
3082 dm->adev->ddev,
3083 &aplane->base,
3084 possible_crtcs,
3085 &dm_plane_funcs,
3086 rgb_formats,
3087 ARRAY_SIZE(rgb_formats),
3088 NULL, aplane->base.type, NULL);
3089 break;
3090 case DRM_PLANE_TYPE_OVERLAY:
3091 res = drm_universal_plane_init(
3092 dm->adev->ddev,
3093 &aplane->base,
3094 possible_crtcs,
3095 &dm_plane_funcs,
3096 yuv_formats,
3097 ARRAY_SIZE(yuv_formats),
3098 NULL, aplane->base.type, NULL);
3099 break;
3100 case DRM_PLANE_TYPE_CURSOR:
3101 res = drm_universal_plane_init(
3102 dm->adev->ddev,
3103 &aplane->base,
3104 possible_crtcs,
3105 &dm_plane_funcs,
3106 cursor_formats,
3107 ARRAY_SIZE(cursor_formats),
3108 NULL, aplane->base.type, NULL);
3109 break;
3110 }
3111
3112 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3113
3114 return res;
3115}
3116
7578ecda
AD		 3117static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3118 struct drm_plane *plane,
3119 uint32_t crtc_index)
e7b07cee
HW		 3120{
3121 struct amdgpu_crtc *acrtc = NULL;
3122 struct amdgpu_plane *cursor_plane;
3123
3124 int res = -ENOMEM;
3125
3126 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3127 if (!cursor_plane)
3128 goto fail;
3129
3130 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3131 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3132
3133 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3134 if (!acrtc)
3135 goto fail;
3136
3137 res = drm_crtc_init_with_planes(
3138 dm->ddev,
3139 &acrtc->base,
3140 plane,
3141 &cursor_plane->base,
3142 &amdgpu_dm_crtc_funcs, NULL);
3143
3144 if (res)
3145 goto fail;
3146
3147 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3148
3149 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3150 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3151
3152 acrtc->crtc_id = crtc_index;
3153 acrtc->base.enabled = false;
3154
3155 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3156 drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3157
3158 return 0;
3159
3160fail:
b830ebc9
HW		 3161 kfree(acrtc);
3162 kfree(cursor_plane);
e7b07cee
HW		 3163 return res;
3164}
3165
3166
3167static int to_drm_connector_type(enum signal_type st)
3168{
3169 switch (st) {
3170 case SIGNAL_TYPE_HDMI_TYPE_A:
3171 return DRM_MODE_CONNECTOR_HDMIA;
3172 case SIGNAL_TYPE_EDP:
3173 return DRM_MODE_CONNECTOR_eDP;
3174 case SIGNAL_TYPE_RGB:
3175 return DRM_MODE_CONNECTOR_VGA;
3176 case SIGNAL_TYPE_DISPLAY_PORT:
3177 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3178 return DRM_MODE_CONNECTOR_DisplayPort;
3179 case SIGNAL_TYPE_DVI_DUAL_LINK:
3180 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3181 return DRM_MODE_CONNECTOR_DVID;
3182 case SIGNAL_TYPE_VIRTUAL:
3183 return DRM_MODE_CONNECTOR_VIRTUAL;
3184
3185 default:
3186 return DRM_MODE_CONNECTOR_Unknown;
3187 }
3188}
3189
3190static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3191{
3192 const struct drm_connector_helper_funcs *helper =
3193 connector->helper_private;
3194 struct drm_encoder *encoder;
3195 struct amdgpu_encoder *amdgpu_encoder;
3196
3197 encoder = helper->best_encoder(connector);
3198
3199 if (encoder == NULL)
3200 return;
3201
3202 amdgpu_encoder = to_amdgpu_encoder(encoder);
3203
3204 amdgpu_encoder->native_mode.clock = 0;
3205
3206 if (!list_empty(&connector->probed_modes)) {
3207 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3208
e7b07cee 3209 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3210 &connector->probed_modes,
3211 head) {
3212 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3213 amdgpu_encoder->native_mode = *preferred_mode;
3214
e7b07cee
HW		 3215 break;
3216 }
3217
3218 }
3219}
3220
3ee6b26b
AD		 3221static struct drm_display_mode *
3222amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3223 char *name,
3224 int hdisplay, int vdisplay)
e7b07cee
HW		 3225{
3226 struct drm_device *dev = encoder->dev;
3227 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3228 struct drm_display_mode *mode = NULL;
3229 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3230
3231 mode = drm_mode_duplicate(dev, native_mode);
3232
b830ebc9 3233 if (mode == NULL)
e7b07cee
HW		 3234 return NULL;
3235
3236 mode->hdisplay = hdisplay;
3237 mode->vdisplay = vdisplay;
3238 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3239 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3240
3241 return mode;
3242
3243}
3244
3245static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3246 struct drm_connector *connector)
e7b07cee
HW		 3247{
3248 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3249 struct drm_display_mode *mode = NULL;
3250 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3251 struct amdgpu_dm_connector *amdgpu_dm_connector =
3252 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3253 int i;
3254 int n;
3255 struct mode_size {
3256 char name[DRM_DISPLAY_MODE_LEN];
3257 int w;
3258 int h;
b830ebc9 3259 } common_modes[] = {
e7b07cee
HW		 3260 { "640x480", 640, 480},
3261 { "800x600", 800, 600},
3262 { "1024x768", 1024, 768},
3263 { "1280x720", 1280, 720},
3264 { "1280x800", 1280, 800},
3265 {"1280x1024", 1280, 1024},
3266 { "1440x900", 1440, 900},
3267 {"1680x1050", 1680, 1050},
3268 {"1600x1200", 1600, 1200},
3269 {"1920x1080", 1920, 1080},
3270 {"1920x1200", 1920, 1200}
3271 };
3272
b830ebc9 3273 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3274
3275 for (i = 0; i < n; i++) {
3276 struct drm_display_mode *curmode = NULL;
3277 bool mode_existed = false;
3278
3279 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3280 common_modes[i].h > native_mode->vdisplay ||
3281 (common_modes[i].w == native_mode->hdisplay &&
3282 common_modes[i].h == native_mode->vdisplay))
3283 continue;
e7b07cee
HW		 3284
3285 list_for_each_entry(curmode, &connector->probed_modes, head) {
3286 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3287 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3288 mode_existed = true;
3289 break;
3290 }
3291 }
3292
3293 if (mode_existed)
3294 continue;
3295
3296 mode = amdgpu_dm_create_common_mode(encoder,
3297 common_modes[i].name, common_modes[i].w,
3298 common_modes[i].h);
3299 drm_mode_probed_add(connector, mode);
c84dec2f 3300 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3301 }
3302}
3303
3ee6b26b
AD		 3304static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3305 struct edid *edid)
e7b07cee 3306{
c84dec2f
HW		 3307 struct amdgpu_dm_connector *amdgpu_dm_connector =
3308 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3309
3310 if (edid) {
3311 /* empty probed_modes */
3312 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3313 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3314 drm_add_edid_modes(connector, edid);
3315
3316 drm_edid_to_eld(connector, edid);
3317
3318 amdgpu_dm_get_native_mode(connector);
3319 } else
c84dec2f 3320 amdgpu_dm_connector->num_modes = 0;
e7b07cee
HW		 3321}
3322
7578ecda 3323static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3324{
3325 const struct drm_connector_helper_funcs *helper =
3326 connector->helper_private;
c84dec2f
HW		 3327 struct amdgpu_dm_connector *amdgpu_dm_connector =
3328 to_amdgpu_dm_connector(connector);
e7b07cee 3329 struct drm_encoder *encoder;
c84dec2f 3330 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3331
3332 encoder = helper->best_encoder(connector);
3333
3334 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3335 amdgpu_dm_connector_add_common_modes(encoder, connector);
c84dec2f 3336 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3337}
3338
3ee6b26b
AD		 3339void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3340 struct amdgpu_dm_connector *aconnector,
3341 int connector_type,
3342 struct dc_link *link,
3343 int link_index)
e7b07cee
HW		 3344{
3345 struct amdgpu_device *adev = dm->ddev->dev_private;
3346
3347 aconnector->connector_id = link_index;
3348 aconnector->dc_link = link;
3349 aconnector->base.interlace_allowed = false;
3350 aconnector->base.doublescan_allowed = false;
3351 aconnector->base.stereo_allowed = false;
3352 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3353 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3354
3355 mutex_init(&aconnector->hpd_lock);
3356
b830ebc9
HW		 3357 /* configure support HPD hot plug connector_>polled default value is 0
3358 * which means HPD hot plug not supported
3359 */
e7b07cee
HW		 3360 switch (connector_type) {
3361 case DRM_MODE_CONNECTOR_HDMIA:
3362 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3363 break;
3364 case DRM_MODE_CONNECTOR_DisplayPort:
3365 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3366 break;
3367 case DRM_MODE_CONNECTOR_DVID:
3368 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3369 break;
3370 default:
3371 break;
3372 }
3373
3374 drm_object_attach_property(&aconnector->base.base,
3375 dm->ddev->mode_config.scaling_mode_property,
3376 DRM_MODE_SCALE_NONE);
3377
3378 drm_object_attach_property(&aconnector->base.base,
3379 adev->mode_info.underscan_property,
3380 UNDERSCAN_OFF);
3381 drm_object_attach_property(&aconnector->base.base,
3382 adev->mode_info.underscan_hborder_property,
3383 0);
3384 drm_object_attach_property(&aconnector->base.base,
3385 adev->mode_info.underscan_vborder_property,
3386 0);
3387
3388}
3389
7578ecda
AD		 3390static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3391 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3392{
3393 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3394 struct ddc_service *ddc_service = i2c->ddc_service;
3395 struct i2c_command cmd;
3396 int i;
3397 int result = -EIO;
3398
b830ebc9 3399 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3400
3401 if (!cmd.payloads)
3402 return result;
3403
3404 cmd.number_of_payloads = num;
3405 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3406 cmd.speed = 100;
3407
3408 for (i = 0; i < num; i++) {
3409 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3410 cmd.payloads[i].address = msgs[i].addr;
3411 cmd.payloads[i].length = msgs[i].len;
3412 cmd.payloads[i].data = msgs[i].buf;
3413 }
3414
3415 if (dal_i2caux_submit_i2c_command(
3416 ddc_service->ctx->i2caux,
3417 ddc_service->ddc_pin,
3418 &cmd))
3419 result = num;
3420
3421 kfree(cmd.payloads);
3422 return result;
3423}
3424
7578ecda 3425static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3426{
3427 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3428}
3429
3430static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3431 .master_xfer = amdgpu_dm_i2c_xfer,
3432 .functionality = amdgpu_dm_i2c_func,
3433};
3434
3ee6b26b
AD		 3435static struct amdgpu_i2c_adapter *
3436create_i2c(struct ddc_service *ddc_service,
3437 int link_index,
3438 int *res)
e7b07cee
HW		 3439{
3440 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3441 struct amdgpu_i2c_adapter *i2c;
3442
b830ebc9 3443 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
e7b07cee
HW		 3444 i2c->base.owner = THIS_MODULE;
3445 i2c->base.class = I2C_CLASS_DDC;
3446 i2c->base.dev.parent = &adev->pdev->dev;
3447 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3448 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3449 i2c_set_adapdata(&i2c->base, i2c);
3450 i2c->ddc_service = ddc_service;
3451
3452 return i2c;
3453}
3454
3455/* Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3456 * dc_link which will be represented by this aconnector.
3457 */
7578ecda
AD		 3458static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3459 struct amdgpu_dm_connector *aconnector,
3460 uint32_t link_index,
3461 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3462{
3463 int res = 0;
3464 int connector_type;
3465 struct dc *dc = dm->dc;
3466 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3467 struct amdgpu_i2c_adapter *i2c;
3468 ((struct dc_link *)link)->priv = aconnector;
3469
f1ad2f5e 3470 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3471
3472 i2c = create_i2c(link->ddc, link->link_index, &res);
3473 aconnector->i2c = i2c;
3474 res = i2c_add_adapter(&i2c->base);
3475
3476 if (res) {
3477 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3478 goto out_free;
3479 }
3480
3481 connector_type = to_drm_connector_type(link->connector_signal);
3482
3483 res = drm_connector_init(
3484 dm->ddev,
3485 &aconnector->base,
3486 &amdgpu_dm_connector_funcs,
3487 connector_type);
3488
3489 if (res) {
3490 DRM_ERROR("connector_init failed\n");
3491 aconnector->connector_id = -1;
3492 goto out_free;
3493 }
3494
3495 drm_connector_helper_add(
3496 &aconnector->base,
3497 &amdgpu_dm_connector_helper_funcs);
3498
3499 amdgpu_dm_connector_init_helper(
3500 dm,
3501 aconnector,
3502 connector_type,
3503 link,
3504 link_index);
3505
3506 drm_mode_connector_attach_encoder(
3507 &aconnector->base, &aencoder->base);
3508
3509 drm_connector_register(&aconnector->base);
3510
3511 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3512 || connector_type == DRM_MODE_CONNECTOR_eDP)
3513 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3514
3515#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3516 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3517
3518 /* NOTE: this currently will create backlight device even if a panel
3519 * is not connected to the eDP/LVDS connector.
3520 *
3521 * This is less than ideal but we don't have sink information at this
3522 * stage since detection happens after. We can't do detection earlier
3523 * since MST detection needs connectors to be created first.
3524 */
3525 if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3526 /* Event if registration failed, we should continue with
3527 * DM initialization because not having a backlight control
b830ebc9
HW		 3528 * is better then a black screen.
3529 */
e7b07cee
HW		 3530 amdgpu_dm_register_backlight_device(dm);
3531
3532 if (dm->backlight_dev)
3533 dm->backlight_link = link;
3534 }
3535#endif
3536
3537out_free:
3538 if (res) {
3539 kfree(i2c);
3540 aconnector->i2c = NULL;
3541 }
3542 return res;
3543}
3544
3545int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3546{
3547 switch (adev->mode_info.num_crtc) {
3548 case 1:
3549 return 0x1;
3550 case 2:
3551 return 0x3;
3552 case 3:
3553 return 0x7;
3554 case 4:
3555 return 0xf;
3556 case 5:
3557 return 0x1f;
3558 case 6:
3559 default:
3560 return 0x3f;
3561 }
3562}
3563
7578ecda
AD		 3564static int amdgpu_dm_encoder_init(struct drm_device *dev,
3565 struct amdgpu_encoder *aencoder,
3566 uint32_t link_index)
e7b07cee
HW		 3567{
3568 struct amdgpu_device *adev = dev->dev_private;
3569
3570 int res = drm_encoder_init(dev,
3571 &aencoder->base,
3572 &amdgpu_dm_encoder_funcs,
3573 DRM_MODE_ENCODER_TMDS,
3574 NULL);
3575
3576 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3577
3578 if (!res)
3579 aencoder->encoder_id = link_index;
3580 else
3581 aencoder->encoder_id = -1;
3582
3583 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3584
3585 return res;
3586}
3587
3ee6b26b
AD		 3588static void manage_dm_interrupts(struct amdgpu_device *adev,
3589 struct amdgpu_crtc *acrtc,
3590 bool enable)
e7b07cee
HW		 3591{
3592 /*
3593 * this is not correct translation but will work as soon as VBLANK
3594 * constant is the same as PFLIP
3595 */
3596 int irq_type =
3597 amdgpu_crtc_idx_to_irq_type(
3598 adev,
3599 acrtc->crtc_id);
3600
3601 if (enable) {
3602 drm_crtc_vblank_on(&acrtc->base);
3603 amdgpu_irq_get(
3604 adev,
3605 &adev->pageflip_irq,
3606 irq_type);
3607 } else {
3608
3609 amdgpu_irq_put(
3610 adev,
3611 &adev->pageflip_irq,
3612 irq_type);
3613 drm_crtc_vblank_off(&acrtc->base);
3614 }
3615}
3616
3ee6b26b
AD		 3617static bool
3618is_scaling_state_different(const struct dm_connector_state *dm_state,
3619 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3620{
3621 if (dm_state->scaling != old_dm_state->scaling)
3622 return true;
3623 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3624 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3625 return true;
3626 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3627 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3628 return true;
b830ebc9
HW		 3629 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3630 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3631 return true;
e7b07cee
HW		 3632 return false;
3633}
3634
3ee6b26b
AD		 3635static void remove_stream(struct amdgpu_device *adev,
3636 struct amdgpu_crtc *acrtc,
3637 struct dc_stream_state *stream)
e7b07cee
HW		 3638{
3639 /* this is the update mode case */
3640 if (adev->dm.freesync_module)
3641 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3642
3643 acrtc->otg_inst = -1;
3644 acrtc->enabled = false;
3645}
3646
7578ecda
AD		 3647static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3648 struct dc_cursor_position *position)
2a8f6ccb
HW		 3649{
3650 struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3651 int x, y;
3652 int xorigin = 0, yorigin = 0;
3653
3654 if (!crtc || !plane->state->fb) {
3655 position->enable = false;
3656 position->x = 0;
3657 position->y = 0;
3658 return 0;
3659 }
3660
3661 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3662 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3663 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3664 __func__,
3665 plane->state->crtc_w,
3666 plane->state->crtc_h);
3667 return -EINVAL;
3668 }
3669
3670 x = plane->state->crtc_x;
3671 y = plane->state->crtc_y;
3672 /* avivo cursor are offset into the total surface */
3673 x += crtc->primary->state->src_x >> 16;
3674 y += crtc->primary->state->src_y >> 16;
3675 if (x < 0) {
3676 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3677 x = 0;
3678 }
3679 if (y < 0) {
3680 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3681 y = 0;
3682 }
3683 position->enable = true;
3684 position->x = x;
3685 position->y = y;
3686 position->x_hotspot = xorigin;
3687 position->y_hotspot = yorigin;
3688
3689 return 0;
3690}
3691
3ee6b26b
AD		 3692static void handle_cursor_update(struct drm_plane *plane,
3693 struct drm_plane_state *old_plane_state)
e7b07cee 3694{
2a8f6ccb
HW		 3695 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3696 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3697 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3699 uint64_t address = afb ? afb->address : 0;
3700 struct dc_cursor_position position;
3701 struct dc_cursor_attributes attributes;
3702 int ret;
3703
e7b07cee
HW		 3704 if (!plane->state->fb && !old_plane_state->fb)
3705 return;
3706
f1ad2f5e 3707 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3708 __func__,
3709 amdgpu_crtc->crtc_id,
3710 plane->state->crtc_w,
3711 plane->state->crtc_h);
2a8f6ccb
HW		 3712
3713 ret = get_cursor_position(plane, crtc, &position);
3714 if (ret)
3715 return;
3716
3717 if (!position.enable) {
3718 /* turn off cursor */
3719 if (crtc_state && crtc_state->stream)
3720 dc_stream_set_cursor_position(crtc_state->stream,
3721 &position);
3722 return;
e7b07cee 3723 }
e7b07cee 3724
2a8f6ccb
HW		 3725 amdgpu_crtc->cursor_width = plane->state->crtc_w;
3726 amdgpu_crtc->cursor_height = plane->state->crtc_h;
3727
3728 attributes.address.high_part = upper_32_bits(address);
3729 attributes.address.low_part = lower_32_bits(address);
3730 attributes.width = plane->state->crtc_w;
3731 attributes.height = plane->state->crtc_h;
3732 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3733 attributes.rotation_angle = 0;
3734 attributes.attribute_flags.value = 0;
3735
3736 attributes.pitch = attributes.width;
3737
886daac9
JZ		 3738 if (crtc_state->stream) {
3739 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3740 &attributes))
3741 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 3742
2a8f6ccb
HW		 3743 if (!dc_stream_set_cursor_position(crtc_state->stream,
3744 &position))
3745 DRM_ERROR("DC failed to set cursor position\n");
886daac9 3746 }
2a8f6ccb 3747}
e7b07cee
HW		 3748
3749static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3750{
3751
3752 assert_spin_locked(&acrtc->base.dev->event_lock);
3753 WARN_ON(acrtc->event);
3754
3755 acrtc->event = acrtc->base.state->event;
3756
3757 /* Set the flip status */
3758 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3759
3760 /* Mark this event as consumed */
3761 acrtc->base.state->event = NULL;
3762
3763 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3764 acrtc->crtc_id);
3765}
3766
3767/*
3768 * Executes flip
3769 *
3770 * Waits on all BO's fences and for proper vblank count
3771 */
3ee6b26b
AD		 3772static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3773 struct drm_framebuffer *fb,
bc6828e0
BL		 3774 uint32_t target,
3775 struct dc_state *state)
e7b07cee
HW		 3776{
3777 unsigned long flags;
3778 uint32_t target_vblank;
3779 int r, vpos, hpos;
3780 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3781 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3782 struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3783 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 3784 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 3785 struct dc_flip_addrs addr = { {0} };
3be5262e 3786 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 3787 struct dc_surface_update surface_updates[1] = { {0} };
3788 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3789
3790
3791 /* Prepare wait for target vblank early - before the fence-waits */
3792 target_vblank = target - drm_crtc_vblank_count(crtc) +
3793 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3794
b830ebc9 3795 /* TODO This might fail and hence better not used, wait
e7b07cee
HW		 3796 * explicitly on fences instead
3797 * and in general should be called for
3798 * blocking commit to as per framework helpers
b830ebc9 3799 */
e7b07cee
HW		 3800 r = amdgpu_bo_reserve(abo, true);
3801 if (unlikely(r != 0)) {
3802 DRM_ERROR("failed to reserve buffer before flip\n");
3803 WARN_ON(1);
3804 }
3805
3806 /* Wait for all fences on this FB */
3807 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3808 MAX_SCHEDULE_TIMEOUT) < 0);
3809
3810 amdgpu_bo_unreserve(abo);
3811
3812 /* Wait until we're out of the vertical blank period before the one
3813 * targeted by the flip
3814 */
3815 while ((acrtc->enabled &&
3816 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3817 &vpos, &hpos, NULL, NULL,
3818 &crtc->hwmode)
3819 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3820 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3821 (int)(target_vblank -
3822 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3823 usleep_range(1000, 1100);
3824 }
3825
3826 /* Flip */
3827 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3828 /* update crtc fb */
3829 crtc->primary->fb = fb;
3830
3831 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3832 WARN_ON(!acrtc_state->stream);
3833
3834 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3835 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3836 addr.flip_immediate = async_flip;
3837
3838
3839 if (acrtc->base.state->event)
3840 prepare_flip_isr(acrtc);
3841
3be5262e 3842 surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
e7b07cee
HW		 3843 surface_updates->flip_addr = &addr;
3844
3845
bc6828e0
BL		 3846 dc_commit_updates_for_stream(adev->dm.dc,
3847 surface_updates,
3848 1,
3849 acrtc_state->stream,
3850 NULL,
3851 &surface_updates->surface,
3852 state);
e7b07cee
HW		 3853
3854 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3855 __func__,
3856 addr.address.grph.addr.high_part,
3857 addr.address.grph.addr.low_part);
3858
3859
3860 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3861}
3862
3be5262e 3863static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 3864 struct drm_device *dev,
3865 struct amdgpu_display_manager *dm,
3866 struct drm_crtc *pcrtc,
3867 bool *wait_for_vblank)
e7b07cee
HW		 3868{
3869 uint32_t i;
3870 struct drm_plane *plane;
0bc9706d 3871 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 3872 struct dc_stream_state *dc_stream_attach;
3be5262e 3873 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 3874 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 3875 struct drm_crtc_state *new_pcrtc_state =
3876 drm_atomic_get_new_crtc_state(state, pcrtc);
3877 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
bc6828e0 3878 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 3879 int planes_count = 0;
3880 unsigned long flags;
3881
3882 /* update planes when needed */
0bc9706d
LSL		 3883 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3884 struct drm_crtc *crtc = new_plane_state->crtc;
3885 struct drm_crtc_state *new_crtc_state =
3886 drm_atomic_get_new_crtc_state(state, crtc);
3887 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 3888 bool pflip_needed;
54d76575 3889 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 3890
3891 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3892 handle_cursor_update(plane, old_plane_state);
3893 continue;
3894 }
3895
0bc9706d 3896 if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active)
e7b07cee
HW		 3897 continue;
3898
3899 pflip_needed = !state->allow_modeset;
3900
3901 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3902 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 3903 DRM_ERROR("%s: acrtc %d, already busy\n",
3904 __func__,
3905 acrtc_attach->crtc_id);
e7b07cee 3906 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
b830ebc9 3907 /* In commit tail framework this cannot happen */
e7b07cee
HW		 3908 WARN_ON(1);
3909 }
3910 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3911
3912 if (!pflip_needed) {
54d76575 3913 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 3914
54d76575 3915 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 3916
3917 dc_stream_attach = acrtc_state->stream;
3918 planes_count++;
3919
0bc9706d 3920 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 3921 /* Assume even ONE crtc with immediate flip means
3922 * entire can't wait for VBLANK
3923 * TODO Check if it's correct
3924 */
3925 *wait_for_vblank =
0bc9706d 3926 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 3927 false : true;
3928
3929 /* TODO: Needs rework for multiplane flip */
3930 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3931 drm_crtc_vblank_get(crtc);
3932
3933 amdgpu_dm_do_flip(
3934 crtc,
3935 fb,
bc6828e0
BL		 3936 drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3937 dm_state->context);
e7b07cee
HW		 3938 }
3939
3940 }
3941
3942 if (planes_count) {
3943 unsigned long flags;
3944
0bc9706d 3945 if (new_pcrtc_state->event) {
e7b07cee
HW		 3946
3947 drm_crtc_vblank_get(pcrtc);
3948
3949 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
3950 prepare_flip_isr(acrtc_attach);
3951 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
3952 }
3953
3be5262e
HW		 3954 if (false == dc_commit_planes_to_stream(dm->dc,
3955 plane_states_constructed,
3956 planes_count,
bc6828e0
BL		 3957 dc_stream_attach,
3958 dm_state->context))
3be5262e 3959 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 3960 } else {
3961 /*TODO BUG Here should go disable planes on CRTC. */
3962 }
3963}
3964
3965
7578ecda
AD		 3966static int amdgpu_dm_atomic_commit(struct drm_device *dev,
3967 struct drm_atomic_state *state,
3968 bool nonblock)
e7b07cee
HW		 3969{
3970 struct drm_crtc *crtc;
c2cea706 3971 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 3972 struct amdgpu_device *adev = dev->dev_private;
3973 int i;
3974
3975 /*
3976 * We evade vblanks and pflips on crtc that
3977 * should be changed. We do it here to flush & disable
3978 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
3979 * it will update crtc->dm_crtc_state->stream pointer which is used in
3980 * the ISRs.
3981 */
c2cea706 3982 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 3983 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 3984 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3985
54d76575 3986 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 3987 manage_dm_interrupts(adev, acrtc, false);
3988 }
3989
3990 return drm_atomic_helper_commit(dev, state, nonblock);
3991
3992 /*TODO Handle EINTR, reenable IRQ*/
3993}
3994
7578ecda 3995static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 3996{
3997 struct drm_device *dev = state->dev;
3998 struct amdgpu_device *adev = dev->dev_private;
3999 struct amdgpu_display_manager *dm = &adev->dm;
4000 struct dm_atomic_state *dm_state;
4001 uint32_t i, j;
4002 uint32_t new_crtcs_count = 0;
5cc6dcbd 4003 struct drm_crtc *crtc;
0bc9706d 4004 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee 4005 struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
0971c40e 4006 struct dc_stream_state *new_stream = NULL;
e7b07cee
HW		 4007 unsigned long flags;
4008 bool wait_for_vblank = true;
4009 struct drm_connector *connector;
c2cea706 4010 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4011 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
e7b07cee
HW		 4012
4013 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4014
4015 dm_state = to_dm_atomic_state(state);
4016
4017 /* update changed items */
0bc9706d 4018 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4019 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4020
54d76575
LSL		 4021 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4022 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4023
f1ad2f5e 4024 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4025 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4026 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4027 "connectors_changed:%d\n",
4028 acrtc->crtc_id,
0bc9706d
LSL		 4029 new_crtc_state->enable,
4030 new_crtc_state->active,
4031 new_crtc_state->planes_changed,
4032 new_crtc_state->mode_changed,
4033 new_crtc_state->active_changed,
4034 new_crtc_state->connectors_changed);
e7b07cee
HW		 4035
4036 /* handles headless hotplug case, updating new_state and
4037 * aconnector as needed
4038 */
4039
54d76575 4040 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4041
f1ad2f5e 4042 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4043
54d76575 4044 if (!dm_new_crtc_state->stream) {
e7b07cee 4045 /*
b830ebc9
HW		 4046 * this could happen because of issues with
4047 * userspace notifications delivery.
4048 * In this case userspace tries to set mode on
4049 * display which is disconnect in fact.
4050 * dc_sink in NULL in this case on aconnector.
4051 * We expect reset mode will come soon.
4052 *
4053 * This can also happen when unplug is done
4054 * during resume sequence ended
4055 *
4056 * In this case, we want to pretend we still
4057 * have a sink to keep the pipe running so that
4058 * hw state is consistent with the sw state
4059 */
f1ad2f5e 4060 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4061 __func__, acrtc->base.base.id);
4062 continue;
4063 }
4064
4065
54d76575
LSL		 4066 if (dm_old_crtc_state->stream)
4067 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4068
4069
4070 /*
4071 * this loop saves set mode crtcs
4072 * we needed to enable vblanks once all
4073 * resources acquired in dc after dc_commit_streams
4074 */
4075
4076 /*TODO move all this into dm_crtc_state, get rid of
4077 * new_crtcs array and use old and new atomic states
4078 * instead
4079 */
4080 new_crtcs[new_crtcs_count] = acrtc;
4081 new_crtcs_count++;
4082
0bc9706d 4083 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
e7b07cee 4084 acrtc->enabled = true;
0bc9706d
LSL		 4085 acrtc->hw_mode = new_crtc_state->mode;
4086 crtc->hwmode = new_crtc_state->mode;
4087 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4088 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4089
4090 /* i.e. reset mode */
54d76575
LSL		 4091 if (dm_old_crtc_state->stream)
4092 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4093 }
4094 } /* for_each_crtc_in_state() */
4095
4096 /*
4097 * Add streams after required streams from new and replaced streams
4098 * are removed from freesync module
4099 */
4100 if (adev->dm.freesync_module) {
4101 for (i = 0; i < new_crtcs_count; i++) {
c84dec2f 4102 struct amdgpu_dm_connector *aconnector = NULL;
b830ebc9 4103
0bc9706d
LSL		 4104 new_crtc_state = drm_atomic_get_new_crtc_state(state,
4105 &new_crtcs[i]->base);
54d76575 4106 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4107
54d76575 4108 new_stream = dm_new_crtc_state->stream;
1daf8c63 4109 aconnector = amdgpu_dm_find_first_crtc_matching_connector(
e7b07cee 4110 state,
9ba29fcb 4111 &new_crtcs[i]->base);
e7b07cee 4112 if (!aconnector) {
f1ad2f5e 4113 DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d "
b830ebc9
HW		 4114 "skipping freesync init\n",
4115 new_crtcs[i]->crtc_id);
e7b07cee
HW		 4116 continue;
4117 }
4118
4119 mod_freesync_add_stream(adev->dm.freesync_module,
4120 new_stream, &aconnector->caps);
4121 }
4122 }
4123
4124 if (dm_state->context)
608ac7bb 4125 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
e7b07cee 4126
0bc9706d 4127 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4128 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4129
54d76575 4130 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4131
54d76575 4132 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4133 const struct dc_stream_status *status =
54d76575 4134 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4135
4136 if (!status)
54d76575 4137 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4138 else
4139 acrtc->otg_inst = status->primary_otg_inst;
4140 }
4141 }
4142
ebdd27e1 4143 /* Handle scaling and underscan changes*/
c2cea706 4144 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4145 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4146 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4147 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4148 struct dc_stream_status *status = NULL;
4149
0bc9706d
LSL		 4150 if (acrtc)
4151 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4152
e7b07cee 4153 /* Skip any modesets/resets */
0bc9706d 4154 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4155 continue;
4156
4157 /* Skip any thing not scale or underscan changes */
54d76575 4158 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4159 continue;
4160
54d76575 4161 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4162
54d76575
LSL		 4163 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4164 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4165
54d76575 4166 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4167 WARN_ON(!status);
3be5262e 4168 WARN_ON(!status->plane_count);
e7b07cee 4169
54d76575 4170 if (!dm_new_crtc_state->stream)
e7b07cee
HW		 4171 continue;
4172
4173 /*TODO How it works with MPO ?*/
3be5262e 4174 if (!dc_commit_planes_to_stream(
e7b07cee 4175 dm->dc,
3be5262e
HW		 4176 status->plane_states,
4177 status->plane_count,
bc6828e0
BL		 4178 dm_new_crtc_state->stream,
4179 dm_state->context))
e7b07cee
HW		 4180 dm_error("%s: Failed to update stream scaling!\n", __func__);
4181 }
4182
4183 for (i = 0; i < new_crtcs_count; i++) {
4184 /*
4185 * loop to enable interrupts on newly arrived crtc
4186 */
4187 struct amdgpu_crtc *acrtc = new_crtcs[i];
b830ebc9 4188
0bc9706d 4189 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
54d76575 4190 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4191
4192 if (adev->dm.freesync_module)
4193 mod_freesync_notify_mode_change(
54d76575 4194 adev->dm.freesync_module, &dm_new_crtc_state->stream, 1);
e7b07cee
HW		 4195
4196 manage_dm_interrupts(adev, acrtc, true);
4197 }
4198
4199 /* update planes when needed per crtc*/
5cc6dcbd 4200 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4201 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4202
54d76575 4203 if (dm_new_crtc_state->stream)
5cc6dcbd 4204 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4205 }
4206
4207
4208 /*
4209 * send vblank event on all events not handled in flip and
4210 * mark consumed event for drm_atomic_helper_commit_hw_done
4211 */
4212 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4213 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4214
0bc9706d
LSL		 4215 if (new_crtc_state->event)
4216 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4217
0bc9706d 4218 new_crtc_state->event = NULL;
e7b07cee
HW		 4219 }
4220 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4221
4222 /* Signal HW programming completion */
4223 drm_atomic_helper_commit_hw_done(state);
4224
4225 if (wait_for_vblank)
4226 drm_atomic_helper_wait_for_vblanks(dev, state);
4227
4228 drm_atomic_helper_cleanup_planes(dev, state);
4229}
4230
4231
4232static int dm_force_atomic_commit(struct drm_connector *connector)
4233{
4234 int ret = 0;
4235 struct drm_device *ddev = connector->dev;
4236 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4237 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4238 struct drm_plane *plane = disconnected_acrtc->base.primary;
4239 struct drm_connector_state *conn_state;
4240 struct drm_crtc_state *crtc_state;
4241 struct drm_plane_state *plane_state;
4242
4243 if (!state)
4244 return -ENOMEM;
4245
4246 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4247
4248 /* Construct an atomic state to restore previous display setting */
4249
4250 /*
4251 * Attach connectors to drm_atomic_state
4252 */
4253 conn_state = drm_atomic_get_connector_state(state, connector);
4254
4255 ret = PTR_ERR_OR_ZERO(conn_state);
4256 if (ret)
4257 goto err;
4258
4259 /* Attach crtc to drm_atomic_state*/
4260 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4261
4262 ret = PTR_ERR_OR_ZERO(crtc_state);
4263 if (ret)
4264 goto err;
4265
4266 /* force a restore */
4267 crtc_state->mode_changed = true;
4268
4269 /* Attach plane to drm_atomic_state */
4270 plane_state = drm_atomic_get_plane_state(state, plane);
4271
4272 ret = PTR_ERR_OR_ZERO(plane_state);
4273 if (ret)
4274 goto err;
4275
4276
4277 /* Call commit internally with the state we just constructed */
4278 ret = drm_atomic_commit(state);
4279 if (!ret)
4280 return 0;
4281
4282err:
4283 DRM_ERROR("Restoring old state failed with %i\n", ret);
4284 drm_atomic_state_put(state);
4285
4286 return ret;
4287}
4288
4289/*
4290 * This functions handle all cases when set mode does not come upon hotplug.
4291 * This include when the same display is unplugged then plugged back into the
4292 * same port and when we are running without usermode desktop manager supprot
4293 */
3ee6b26b
AD		 4294void dm_restore_drm_connector_state(struct drm_device *dev,
4295 struct drm_connector *connector)
e7b07cee 4296{
c84dec2f 4297 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4298 struct amdgpu_crtc *disconnected_acrtc;
4299 struct dm_crtc_state *acrtc_state;
4300
4301 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4302 return;
4303
4304 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4305 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4306
4307 if (!disconnected_acrtc || !acrtc_state->stream)
4308 return;
4309
4310 /*
4311 * If the previous sink is not released and different from the current,
4312 * we deduce we are in a state where we can not rely on usermode call
4313 * to turn on the display, so we do it here
4314 */
4315 if (acrtc_state->stream->sink != aconnector->dc_sink)
4316 dm_force_atomic_commit(&aconnector->base);
4317}
4318
e7b07cee
HW		 4319/*`
4320 * Grabs all modesetting locks to serialize against any blocking commits,
4321 * Waits for completion of all non blocking commits.
4322 */
3ee6b26b
AD		 4323static int do_aquire_global_lock(struct drm_device *dev,
4324 struct drm_atomic_state *state)
e7b07cee
HW		 4325{
4326 struct drm_crtc *crtc;
4327 struct drm_crtc_commit *commit;
4328 long ret;
4329
4330 /* Adding all modeset locks to aquire_ctx will
4331 * ensure that when the framework release it the
4332 * extra locks we are locking here will get released to
4333 */
4334 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4335 if (ret)
4336 return ret;
4337
4338 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4339 spin_lock(&crtc->commit_lock);
4340 commit = list_first_entry_or_null(&crtc->commit_list,
4341 struct drm_crtc_commit, commit_entry);
4342 if (commit)
4343 drm_crtc_commit_get(commit);
4344 spin_unlock(&crtc->commit_lock);
4345
4346 if (!commit)
4347 continue;
4348
4349 /* Make sure all pending HW programming completed and
4350 * page flips done
4351 */
4352 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4353
4354 if (ret > 0)
4355 ret = wait_for_completion_interruptible_timeout(
4356 &commit->flip_done, 10*HZ);
4357
4358 if (ret == 0)
4359 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4360 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4361
4362 drm_crtc_commit_put(commit);
4363 }
4364
4365 return ret < 0 ? ret : 0;
4366}
4367
3ee6b26b
AD		 4368static int dm_update_crtcs_state(struct dc *dc,
4369 struct drm_atomic_state *state,
4370 bool enable,
4371 bool *lock_and_validation_needed)
e7b07cee 4372{
e7b07cee 4373 struct drm_crtc *crtc;
c2cea706 4374 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4375 int i;
54d76575 4376 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4377 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4378 struct dc_stream_state *new_stream;
62f55537 4379 int ret = 0;
d4d4a645 4380
62f55537
AG		 4381 /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4382 /* update changed items */
c2cea706 4383 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4384 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4385 struct amdgpu_dm_connector *aconnector = NULL;
c2cea706 4386 struct drm_connector_state *new_con_state = NULL;
62f55537 4387 struct dm_connector_state *dm_conn_state = NULL;
e7b07cee 4388
9635b754
DS		 4389 new_stream = NULL;
4390
54d76575
LSL		 4391 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4392 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4393 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4394
1daf8c63 4395 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4396
62f55537 4397 /* TODO This hack should go away */
f4ac176e
JZ		 4398 if (aconnector && enable) {
4399 // Make sure fake sink is created in plug-in scenario
c2cea706
LSL		 4400 new_con_state = drm_atomic_get_connector_state(state,
4401 &aconnector->base);
19f89e23 4402
c2cea706
LSL		 4403 if (IS_ERR(new_con_state)) {
4404 ret = PTR_ERR_OR_ZERO(new_con_state);
62f55537
AG		 4405 break;
4406 }
19f89e23 4407
c2cea706 4408 dm_conn_state = to_dm_connector_state(new_con_state);
19f89e23 4409
62f55537 4410 new_stream = create_stream_for_sink(aconnector,
c2cea706 4411 &new_crtc_state->mode,
62f55537 4412 dm_conn_state);
19f89e23 4413
62f55537
AG		 4414 /*
4415 * we can have no stream on ACTION_SET if a display
4416 * was disconnected during S3, in this case it not and
4417 * error, the OS will be updated after detection, and
4418 * do the right thing on next atomic commit
4419 */
19f89e23 4420
62f55537 4421 if (!new_stream) {
f1ad2f5e 4422 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4423 __func__, acrtc->base.base.id);
4424 break;
19f89e23 4425 }
62f55537 4426 }
19f89e23 4427
9a5d9c48
LSL		 4428 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4429 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
19f89e23 4430
c2cea706 4431 new_crtc_state->mode_changed = false;
e7b07cee 4432
c2cea706 4433 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9a5d9c48 4434 new_crtc_state->mode_changed);
62f55537 4435 }
b830ebc9 4436
e7b07cee 4437
c2cea706 4438 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4439 goto next_crtc;
e7b07cee 4440
f1ad2f5e 4441 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4442 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4443 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4444 "connectors_changed:%d\n",
4445 acrtc->crtc_id,
c2cea706
LSL		 4446 new_crtc_state->enable,
4447 new_crtc_state->active,
4448 new_crtc_state->planes_changed,
4449 new_crtc_state->mode_changed,
4450 new_crtc_state->active_changed,
4451 new_crtc_state->connectors_changed);
e7b07cee 4452
62f55537
AG		 4453 /* Remove stream for any changed/disabled CRTC */
4454 if (!enable) {
4455
54d76575 4456 if (!dm_old_crtc_state->stream)
9635b754 4457 goto next_crtc;
62f55537 4458
f1ad2f5e 4459 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4460 crtc->base.id);
e7b07cee 4461
1dc90497 4462 /* i.e. reset mode */
62c933f9 4463 if (dc_remove_stream_from_ctx(
62f55537
AG		 4464 dc,
4465 dm_state->context,
62c933f9 4466 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4467 ret = -EINVAL;
9635b754 4468 goto fail;
62f55537
AG		 4469 }
4470
54d76575
LSL		 4471 dc_stream_release(dm_old_crtc_state->stream);
4472 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4473
4474 *lock_and_validation_needed = true;
4475
4476 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4477 /*
4478 * Quick fix to prevent NULL pointer on new_stream when
4479 * added MST connectors not found in existing crtc_state in the chained mode
4480 * TODO: need to dig out the root cause of that
4481 */
4482 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4483 goto next_crtc;
62f55537 4484
c2cea706 4485 if (modereset_required(new_crtc_state))
9635b754 4486 goto next_crtc;
62f55537 4487
c2cea706 4488 if (modeset_required(new_crtc_state, new_stream,
54d76575 4489 dm_old_crtc_state->stream)) {
62f55537 4490
54d76575 4491 WARN_ON(dm_new_crtc_state->stream);
62f55537 4492
54d76575 4493 dm_new_crtc_state->stream = new_stream;
62f55537
AG		 4494 dc_stream_retain(new_stream);
4495
f1ad2f5e 4496 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4497 crtc->base.id);
1dc90497 4498
13ab1b44 4499 if (dc_add_stream_to_ctx(
1dc90497
AG		 4500 dc,
4501 dm_state->context,
13ab1b44 4502 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4503 ret = -EINVAL;
9635b754 4504 goto fail;
1dc90497
AG		 4505 }
4506
62f55537 4507 *lock_and_validation_needed = true;
9b690ef3 4508 }
62f55537 4509 }
9b690ef3 4510
9635b754 4511next_crtc:
62f55537
AG		 4512 /* Release extra reference */
4513 if (new_stream)
4514 dc_stream_release(new_stream);
4515 }
e7b07cee 4516
62f55537 4517 return ret;
9635b754
DS		 4518
4519fail:
4520 if (new_stream)
4521 dc_stream_release(new_stream);
4522 return ret;
62f55537 4523}
9b690ef3 4524
3ee6b26b
AD		 4525static int dm_update_planes_state(struct dc *dc,
4526 struct drm_atomic_state *state,
4527 bool enable,
4528 bool *lock_and_validation_needed)
62f55537
AG		 4529{
4530 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 4531 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 4532 struct drm_plane *plane;
4533 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 4534 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 4535 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 4536 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 4537 int i ;
4538 /* TODO return page_flip_needed() function */
4539 bool pflip_needed = !state->allow_modeset;
4540 int ret = 0;
e7b07cee 4541
62f55537
AG		 4542 if (pflip_needed)
4543 return ret;
9b690ef3 4544
62f55537
AG		 4545 /* Add new planes */
4546 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4547 new_plane_crtc = new_plane_state->crtc;
4548 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 4549 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4550 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 4551
4552 /*TODO Implement atomic check for cursor plane */
4553 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4554 continue;
9b690ef3 4555
62f55537
AG		 4556 /* Remove any changed/removed planes */
4557 if (!enable) {
a7b06724 4558
62f55537
AG		 4559 if (!old_plane_crtc)
4560 continue;
4561
0bc9706d
LSL		 4562 old_crtc_state = drm_atomic_get_old_crtc_state(
4563 state, old_plane_crtc);
54d76575 4564 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 4565
54d76575 4566 if (!dm_old_crtc_state->stream)
62f55537
AG		 4567 continue;
4568
f1ad2f5e 4569 DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 4570 plane->base.id, old_plane_crtc->base.id);
9b690ef3 4571
62f55537
AG		 4572 if (!dc_remove_plane_from_context(
4573 dc,
54d76575
LSL		 4574 dm_old_crtc_state->stream,
4575 dm_old_plane_state->dc_state,
62f55537
AG		 4576 dm_state->context)) {
4577
4578 ret = EINVAL;
4579 return ret;
e7b07cee
HW		 4580 }
4581
9b690ef3 4582
54d76575
LSL		 4583 dc_plane_state_release(dm_old_plane_state->dc_state);
4584 dm_new_plane_state->dc_state = NULL;
1dc90497 4585
62f55537 4586 *lock_and_validation_needed = true;
1dc90497 4587
62f55537 4588 } else { /* Add new planes */
1dc90497 4589
62f55537
AG		 4590 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4591 continue;
e7b07cee 4592
62f55537
AG		 4593 if (!new_plane_crtc)
4594 continue;
e7b07cee 4595
62f55537 4596 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 4597 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 4598
54d76575 4599 if (!dm_new_crtc_state->stream)
62f55537
AG		 4600 continue;
4601
4602
54d76575 4603 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 4604
54d76575 4605 dm_new_plane_state->dc_state = dc_create_plane_state(dc);
62f55537 4606
f1ad2f5e 4607 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
62f55537
AG		 4608 plane->base.id, new_plane_crtc->base.id);
4609
54d76575 4610 if (!dm_new_plane_state->dc_state) {
62f55537
AG		 4611 ret = -EINVAL;
4612 return ret;
4613 }
4614
4615 ret = fill_plane_attributes(
4616 new_plane_crtc->dev->dev_private,
54d76575 4617 dm_new_plane_state->dc_state,
62f55537
AG		 4618 new_plane_state,
4619 new_crtc_state,
4620 false);
4621 if (ret)
4622 return ret;
4623
4624
4625 if (!dc_add_plane_to_context(
4626 dc,
54d76575
LSL		 4627 dm_new_crtc_state->stream,
4628 dm_new_plane_state->dc_state,
62f55537
AG		 4629 dm_state->context)) {
4630
4631 ret = -EINVAL;
4632 return ret;
e7b07cee 4633 }
62f55537
AG		 4634
4635 *lock_and_validation_needed = true;
e7b07cee 4636 }
62f55537 4637 }
e7b07cee
HW		 4638
4639
62f55537
AG		 4640 return ret;
4641}
4642
7578ecda
AD		 4643static int amdgpu_dm_atomic_check(struct drm_device *dev,
4644 struct drm_atomic_state *state)
62f55537
AG		 4645{
4646 int i;
4647 int ret;
4648 struct amdgpu_device *adev = dev->dev_private;
4649 struct dc *dc = adev->dm.dc;
4650 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4651 struct drm_connector *connector;
c2cea706 4652 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 4653 struct drm_crtc *crtc;
c2cea706 4654 struct drm_crtc_state *new_crtc_state;
e7b07cee 4655
62f55537
AG		 4656 /*
4657 * This bool will be set for true for any modeset/reset
4658 * or plane update which implies non fast surface update.
4659 */
4660 bool lock_and_validation_needed = false;
4661
4662 ret = drm_atomic_helper_check_modeset(dev, state);
4663
4664 if (ret) {
4665 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4666 return ret;
4667 }
4668
4669 /*
4670 * Hack: Commit needs planes right now, specifically for gamma
4671 * TODO rework commit to check CRTC for gamma change
4672 */
c2cea706
LSL		 4673 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4674 if (new_crtc_state->color_mgmt_changed) {
e7b07cee
HW		 4675 ret = drm_atomic_add_affected_planes(state, crtc);
4676 if (ret)
4677 goto fail;
4678 }
4679 }
4680
62f55537
AG		 4681 dm_state->context = dc_create_state();
4682 ASSERT(dm_state->context);
f36cc577 4683 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 4684
4685 /* Remove exiting planes if they are modified */
4686 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4687 if (ret) {
4688 goto fail;
4689 }
4690
4691 /* Disable all crtcs which require disable */
4692 ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4693 if (ret) {
4694 goto fail;
4695 }
4696
4697 /* Enable all crtcs which require enable */
4698 ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4699 if (ret) {
4700 goto fail;
4701 }
4702
4703 /* Add new/modified planes */
4704 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4705 if (ret) {
4706 goto fail;
4707 }
4708
4709 /* Run this here since we want to validate the streams we created */
4710 ret = drm_atomic_helper_check_planes(dev, state);
4711 if (ret)
4712 goto fail;
4713
ebdd27e1 4714 /* Check scaling and underscan changes*/
e7b07cee
HW		 4715 /*TODO Removed scaling changes validation due to inability to commit
4716 * new stream into context w\o causing full reset. Need to
4717 * decide how to handle.
4718 */
c2cea706 4719 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4720 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4721 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4722 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4723
4724 /* Skip any modesets/resets */
0bc9706d
LSL		 4725 if (!acrtc || drm_atomic_crtc_needs_modeset(
4726 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 4727 continue;
4728
b830ebc9 4729 /* Skip any thing not scale or underscan changes */
54d76575 4730 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4731 continue;
4732
4733 lock_and_validation_needed = true;
4734 }
4735
e7b07cee
HW		 4736 /*
4737 * For full updates case when
4738 * removing/adding/updating streams on once CRTC while flipping
4739 * on another CRTC,
4740 * acquiring global lock will guarantee that any such full
4741 * update commit
4742 * will wait for completion of any outstanding flip using DRMs
4743 * synchronization events.
4744 */
4745
4746 if (lock_and_validation_needed) {
4747
4748 ret = do_aquire_global_lock(dev, state);
4749 if (ret)
4750 goto fail;
1dc90497 4751
e750d56d 4752 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 4753 ret = -EINVAL;
4754 goto fail;
4755 }
4756 }
4757
4758 /* Must be success */
4759 WARN_ON(ret);
4760 return ret;
4761
4762fail:
4763 if (ret == -EDEADLK)
f1ad2f5e 4764 DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n");
e7b07cee 4765 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
f1ad2f5e 4766 DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n");
e7b07cee 4767 else
62f55537 4768 DRM_ERROR("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 4769
4770 return ret;
4771}
4772
3ee6b26b
AD		 4773static bool is_dp_capable_without_timing_msa(struct dc *dc,
4774 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 4775{
4776 uint8_t dpcd_data;
4777 bool capable = false;
4778
c84dec2f 4779 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 4780 dm_helpers_dp_read_dpcd(
4781 NULL,
c84dec2f 4782 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 4783 DP_DOWN_STREAM_PORT_COUNT,
4784 &dpcd_data,
4785 sizeof(dpcd_data))) {
4786 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4787 }
4788
4789 return capable;
4790}
3ee6b26b
AD		 4791void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4792 struct edid *edid)
e7b07cee
HW		 4793{
4794 int i;
4795 uint64_t val_capable;
4796 bool edid_check_required;
4797 struct detailed_timing *timing;
4798 struct detailed_non_pixel *data;
4799 struct detailed_data_monitor_range *range;
c84dec2f
HW		 4800 struct amdgpu_dm_connector *amdgpu_dm_connector =
4801 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4802
4803 struct drm_device *dev = connector->dev;
4804 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 4805
e7b07cee 4806 edid_check_required = false;
c84dec2f 4807 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 4808 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4809 return;
4810 }
4811 if (!adev->dm.freesync_module)
4812 return;
4813 /*
4814 * if edid non zero restrict freesync only for dp and edp
4815 */
4816 if (edid) {
c84dec2f
HW		 4817 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4818 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 4819 edid_check_required = is_dp_capable_without_timing_msa(
4820 adev->dm.dc,
c84dec2f 4821 amdgpu_dm_connector);
e7b07cee
HW		 4822 }
4823 }
4824 val_capable = 0;
4825 if (edid_check_required == true && (edid->version > 1 ||
4826 (edid->version == 1 && edid->revision > 1))) {
4827 for (i = 0; i < 4; i++) {
4828
4829 timing = &edid->detailed_timings[i];
4830 data = &timing->data.other_data;
4831 range = &data->data.range;
4832 /*
4833 * Check if monitor has continuous frequency mode
4834 */
4835 if (data->type != EDID_DETAIL_MONITOR_RANGE)
4836 continue;
4837 /*
4838 * Check for flag range limits only. If flag == 1 then
4839 * no additional timing information provided.
4840 * Default GTF, GTF Secondary curve and CVT are not
4841 * supported
4842 */
4843 if (range->flags != 1)
4844 continue;
4845
c84dec2f
HW		 4846 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4847 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4848 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 4849 range->pixel_clock_mhz * 10;
4850 break;
4851 }
4852
c84dec2f
HW		 4853 if (amdgpu_dm_connector->max_vfreq -
4854 amdgpu_dm_connector->min_vfreq > 10) {
4855 amdgpu_dm_connector->caps.supported = true;
4856 amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4857 amdgpu_dm_connector->min_vfreq * 1000000;
4858 amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4859 amdgpu_dm_connector->max_vfreq * 1000000;
e7b07cee
HW		 4860 val_capable = 1;
4861 }
4862 }
4863
4864 /*
4865 * TODO figure out how to notify user-mode or DRM of freesync caps
4866 * once we figure out how to deal with freesync in an upstreamable
4867 * fashion
4868 */
4869
4870}
4871
3ee6b26b 4872void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
e7b07cee
HW		 4873{
4874 /*
4875 * TODO fill in once we figure out how to deal with freesync in
4876 * an upstreamable fashion
4877 */
4878}
Linux 6.x block layer and io_uring tree(s)