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drm/amdgpu: move more interrupt processing into amdgpu_irq.c
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services_types.h"
27#include "dc.h"
1dc90497 28#include "dc/inc/core_types.h"
4562236b
HW		 29
30#include "vid.h"
31#include "amdgpu.h"
a49dcb88 32#include "amdgpu_display.h"
a94d5569 33#include "amdgpu_ucode.h"
4562236b
HW		 34#include "atom.h"
35#include "amdgpu_dm.h"
e7b07cee 36#include "amdgpu_pm.h"
4562236b
HW		 37
38#include "amd_shared.h"
39#include "amdgpu_dm_irq.h"
40#include "dm_helpers.h"
e7b07cee
HW		 41#include "dm_services_types.h"
42#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 43#if defined(CONFIG_DEBUG_FS)
44#include "amdgpu_dm_debugfs.h"
45#endif
4562236b
HW		 46
47#include "ivsrcid/ivsrcid_vislands30.h"
48
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/version.h>
e7b07cee 52#include <linux/types.h>
97028037 53#include <linux/pm_runtime.h>
a94d5569 54#include <linux/firmware.h>
4562236b 55
e7b07cee 56#include <drm/drmP.h>
4562236b
HW		 57#include <drm/drm_atomic.h>
58#include <drm/drm_atomic_helper.h>
59#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 60#include <drm/drm_fb_helper.h>
61#include <drm/drm_edid.h>
4562236b 62
ff5ef992
AD		 63#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
64#include "ivsrcid/irqsrcs_dcn_1_0.h"
65
ad941f7a
FX		 66#include "dcn/dcn_1_0_offset.h"
67#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 68#include "soc15_hw_ip.h"
69#include "vega10_ip_offset.h"
ff5ef992
AD		 70
71#include "soc15_common.h"
72#endif
73
e7b07cee
HW		 74#include "modules/inc/mod_freesync.h"
75
a94d5569
DF		 76#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
77MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 78
7578ecda
AD		 79/* basic init/fini API */
80static int amdgpu_dm_init(struct amdgpu_device *adev);
81static void amdgpu_dm_fini(struct amdgpu_device *adev);
82
1f6010a9
DF		 83/*
84 * initializes drm_device display related structures, based on the information
7578ecda
AD		 85 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
86 * drm_encoder, drm_mode_config
87 *
88 * Returns 0 on success
89 */
90static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
91/* removes and deallocates the drm structures, created by the above function */
92static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
93
94static void
95amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
96
97static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
98 struct amdgpu_plane *aplane,
99 unsigned long possible_crtcs);
100static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
101 struct drm_plane *plane,
102 uint32_t link_index);
103static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
104 struct amdgpu_dm_connector *amdgpu_dm_connector,
105 uint32_t link_index,
106 struct amdgpu_encoder *amdgpu_encoder);
107static int amdgpu_dm_encoder_init(struct drm_device *dev,
108 struct amdgpu_encoder *aencoder,
109 uint32_t link_index);
110
111static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
112
113static int amdgpu_dm_atomic_commit(struct drm_device *dev,
114 struct drm_atomic_state *state,
115 bool nonblock);
116
117static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
118
119static int amdgpu_dm_atomic_check(struct drm_device *dev,
120 struct drm_atomic_state *state);
121
122
123
e7b07cee 124
e04a6123 125static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 126 DRM_PLANE_TYPE_PRIMARY,
127 DRM_PLANE_TYPE_PRIMARY,
128 DRM_PLANE_TYPE_PRIMARY,
129 DRM_PLANE_TYPE_PRIMARY,
130 DRM_PLANE_TYPE_PRIMARY,
131 DRM_PLANE_TYPE_PRIMARY,
132};
133
e04a6123 134static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 135 DRM_PLANE_TYPE_PRIMARY,
136 DRM_PLANE_TYPE_PRIMARY,
137 DRM_PLANE_TYPE_PRIMARY,
138 DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
139};
140
e04a6123 141static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
d4e13b0d
AD		 142 DRM_PLANE_TYPE_PRIMARY,
143 DRM_PLANE_TYPE_PRIMARY,
144 DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
145};
146
4562236b
HW		 147/*
148 * dm_vblank_get_counter
149 *
150 * @brief
151 * Get counter for number of vertical blanks
152 *
153 * @param
154 * struct amdgpu_device *adev - [in] desired amdgpu device
155 * int disp_idx - [in] which CRTC to get the counter from
156 *
157 * @return
158 * Counter for vertical blanks
159 */
160static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
161{
162 if (crtc >= adev->mode_info.num_crtc)
163 return 0;
164 else {
165 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 166 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
167 acrtc->base.state);
4562236b 168
da5c47f6
AG		 169
170 if (acrtc_state->stream == NULL) {
0971c40e
HW		 171 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
172 crtc);
4562236b
HW		 173 return 0;
174 }
175
da5c47f6 176 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 177 }
178}
179
180static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 181 u32 *vbl, u32 *position)
4562236b 182{
81c50963
ST		 183 uint32_t v_blank_start, v_blank_end, h_position, v_position;
184
4562236b
HW		 185 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
186 return -EINVAL;
187 else {
188 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 189 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
190 acrtc->base.state);
4562236b 191
da5c47f6 192 if (acrtc_state->stream == NULL) {
0971c40e
HW		 193 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
194 crtc);
4562236b
HW		 195 return 0;
196 }
197
81c50963
ST		 198 /*
199 * TODO rework base driver to use values directly.
200 * for now parse it back into reg-format
201 */
da5c47f6 202 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 203 &v_blank_start,
204 &v_blank_end,
205 &h_position,
206 &v_position);
207
e806208d
AG		 208 *position = v_position | (h_position << 16);
209 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 210 }
211
212 return 0;
213}
214
215static bool dm_is_idle(void *handle)
216{
217 /* XXX todo */
218 return true;
219}
220
221static int dm_wait_for_idle(void *handle)
222{
223 /* XXX todo */
224 return 0;
225}
226
227static bool dm_check_soft_reset(void *handle)
228{
229 return false;
230}
231
232static int dm_soft_reset(void *handle)
233{
234 /* XXX todo */
235 return 0;
236}
237
3ee6b26b
AD		 238static struct amdgpu_crtc *
239get_crtc_by_otg_inst(struct amdgpu_device *adev,
240 int otg_inst)
4562236b
HW		 241{
242 struct drm_device *dev = adev->ddev;
243 struct drm_crtc *crtc;
244 struct amdgpu_crtc *amdgpu_crtc;
245
4562236b
HW		 246 if (otg_inst == -1) {
247 WARN_ON(1);
248 return adev->mode_info.crtcs[0];
249 }
250
251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
252 amdgpu_crtc = to_amdgpu_crtc(crtc);
253
254 if (amdgpu_crtc->otg_inst == otg_inst)
255 return amdgpu_crtc;
256 }
257
258 return NULL;
259}
260
261static void dm_pflip_high_irq(void *interrupt_params)
262{
4562236b
HW		 263 struct amdgpu_crtc *amdgpu_crtc;
264 struct common_irq_params *irq_params = interrupt_params;
265 struct amdgpu_device *adev = irq_params->adev;
266 unsigned long flags;
267
268 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
269
270 /* IRQ could occur when in initial stage */
1f6010a9 271 /* TODO work and BO cleanup */
4562236b
HW		 272 if (amdgpu_crtc == NULL) {
273 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
274 return;
275 }
276
277 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 278
279 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
280 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
281 amdgpu_crtc->pflip_status,
282 AMDGPU_FLIP_SUBMITTED,
283 amdgpu_crtc->crtc_id,
284 amdgpu_crtc);
285 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
286 return;
287 }
288
4562236b 289
1f6010a9 290 /* wake up userspace */
1159898a 291 if (amdgpu_crtc->event) {
1f6010a9 292 /* Update to correct count(s) if racing with vblank irq */
753c66c9
MK		 293 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
294
54f5499a 295 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 296
54f5499a
AG		 297 /* page flip completed. clean up */
298 amdgpu_crtc->event = NULL;
1159898a 299
54f5499a
AG		 300 } else
301 WARN_ON(1);
4562236b 302
54f5499a 303 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 304 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
305
54f5499a
AG		 306 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
307 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 308
309 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 310}
311
312static void dm_crtc_high_irq(void *interrupt_params)
313{
314 struct common_irq_params *irq_params = interrupt_params;
315 struct amdgpu_device *adev = irq_params->adev;
4562236b
HW		 316 struct amdgpu_crtc *acrtc;
317
b57de80a 318 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 319
e5d0170e
LSL		 320 if (acrtc) {
321 drm_crtc_handle_vblank(&acrtc->base);
322 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
323 }
4562236b
HW		 324}
325
326static int dm_set_clockgating_state(void *handle,
327 enum amd_clockgating_state state)
328{
329 return 0;
330}
331
332static int dm_set_powergating_state(void *handle,
333 enum amd_powergating_state state)
334{
335 return 0;
336}
337
338/* Prototypes of private functions */
339static int dm_early_init(void* handle);
340
a32e24b4 341/* Allocate memory for FBC compressed data */
3e332d3a 342static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 343{
3e332d3a
RL		 344 struct drm_device *dev = connector->dev;
345 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 346 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 347 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
348 struct drm_display_mode *mode;
42e67c3b
RL		 349 unsigned long max_size = 0;
350
351 if (adev->dm.dc->fbc_compressor == NULL)
352 return;
a32e24b4 353
3e332d3a 354 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 355 return;
356
3e332d3a
RL		 357 if (compressor->bo_ptr)
358 return;
42e67c3b 359
42e67c3b 360
3e332d3a
RL		 361 list_for_each_entry(mode, &connector->modes, head) {
362 if (max_size < mode->htotal * mode->vtotal)
363 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 364 }
365
366 if (max_size) {
367 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 368 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 369 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 370
371 if (r)
42e67c3b
RL		 372 DRM_ERROR("DM: Failed to initialize FBC\n");
373 else {
374 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
375 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
376 }
377
a32e24b4
RL		 378 }
379
380}
a32e24b4 381
1f6010a9
DF		 382/*
383 * Init display KMS
4562236b
HW		 384 *
385 * Returns 0 on success
386 */
7578ecda 387static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 388{
389 struct dc_init_data init_data;
390 adev->dm.ddev = adev->ddev;
391 adev->dm.adev = adev;
392
4562236b
HW		 393 /* Zero all the fields */
394 memset(&init_data, 0, sizeof(init_data));
395
4562236b
HW		 396 if(amdgpu_dm_irq_init(adev)) {
397 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
398 goto error;
399 }
400
401 init_data.asic_id.chip_family = adev->family;
402
403 init_data.asic_id.pci_revision_id = adev->rev_id;
404 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
405
770d13b1 406 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 407 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
408 init_data.asic_id.atombios_base_address =
409 adev->mode_info.atom_context->bios;
410
411 init_data.driver = adev;
412
413 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
414
415 if (!adev->dm.cgs_device) {
416 DRM_ERROR("amdgpu: failed to create cgs device.\n");
417 goto error;
418 }
419
420 init_data.cgs_device = adev->dm.cgs_device;
421
4562236b
HW		 422 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
423
6e227308
HW		 424 /*
425 * TODO debug why this doesn't work on Raven
426 */
427 if (adev->flags & AMD_IS_APU &&
428 adev->asic_type >= CHIP_CARRIZO &&
429 adev->asic_type < CHIP_RAVEN)
430 init_data.flags.gpu_vm_support = true;
431
4562236b
HW		 432 /* Display Core create. */
433 adev->dm.dc = dc_create(&init_data);
434
423788c7 435 if (adev->dm.dc) {
76121231 436 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 437 } else {
76121231 438 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 439 goto error;
440 }
4562236b 441
4562236b
HW		 442 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
443 if (!adev->dm.freesync_module) {
444 DRM_ERROR(
445 "amdgpu: failed to initialize freesync_module.\n");
446 } else
f1ad2f5e 447 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 448 adev->dm.freesync_module);
449
e277adc5
LSL		 450 amdgpu_dm_init_color_mod();
451
4562236b
HW		 452 if (amdgpu_dm_initialize_drm_device(adev)) {
453 DRM_ERROR(
454 "amdgpu: failed to initialize sw for display support.\n");
455 goto error;
456 }
457
458 /* Update the actual used number of crtc */
459 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
460
461 /* TODO: Add_display_info? */
462
463 /* TODO use dynamic cursor width */
ce75805e
AG		 464 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
465 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 466
467 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
468 DRM_ERROR(
469 "amdgpu: failed to initialize sw for display support.\n");
470 goto error;
471 }
472
e498eb71
NK		 473#if defined(CONFIG_DEBUG_FS)
474 if (dtn_debugfs_init(adev))
475 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
476#endif
477
f1ad2f5e 478 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 479
480 return 0;
481error:
482 amdgpu_dm_fini(adev);
483
59d0f396 484 return -EINVAL;
4562236b
HW		 485}
486
7578ecda 487static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 488{
489 amdgpu_dm_destroy_drm_device(&adev->dm);
490 /*
491 * TODO: pageflip, vlank interrupt
492 *
493 * amdgpu_dm_irq_fini(adev);
494 */
495
496 if (adev->dm.cgs_device) {
497 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
498 adev->dm.cgs_device = NULL;
499 }
500 if (adev->dm.freesync_module) {
501 mod_freesync_destroy(adev->dm.freesync_module);
502 adev->dm.freesync_module = NULL;
503 }
504 /* DC Destroy TODO: Replace destroy DAL */
21de3396 505 if (adev->dm.dc)
4562236b 506 dc_destroy(&adev->dm.dc);
4562236b
HW		 507 return;
508}
509
a94d5569 510static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 511{
a94d5569
DF		 512 const char *fw_name_dmcu;
513 int r;
514 const struct dmcu_firmware_header_v1_0 *hdr;
515
516 switch(adev->asic_type) {
517 case CHIP_BONAIRE:
518 case CHIP_HAWAII:
519 case CHIP_KAVERI:
520 case CHIP_KABINI:
521 case CHIP_MULLINS:
522 case CHIP_TONGA:
523 case CHIP_FIJI:
524 case CHIP_CARRIZO:
525 case CHIP_STONEY:
526 case CHIP_POLARIS11:
527 case CHIP_POLARIS10:
528 case CHIP_POLARIS12:
529 case CHIP_VEGAM:
530 case CHIP_VEGA10:
531 case CHIP_VEGA12:
532 case CHIP_VEGA20:
533 return 0;
534 case CHIP_RAVEN:
535 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
536 break;
537 default:
538 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 539 return -EINVAL;
a94d5569
DF		 540 }
541
542 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
543 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
544 return 0;
545 }
546
547 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
548 if (r == -ENOENT) {
549 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
550 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
551 adev->dm.fw_dmcu = NULL;
552 return 0;
553 }
554 if (r) {
555 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
556 fw_name_dmcu);
557 return r;
558 }
559
560 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
561 if (r) {
562 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
563 fw_name_dmcu);
564 release_firmware(adev->dm.fw_dmcu);
565 adev->dm.fw_dmcu = NULL;
566 return r;
567 }
568
569 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
570 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
571 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
572 adev->firmware.fw_size +=
573 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
574
575 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
576 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
577 adev->firmware.fw_size +=
578 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
579
ee6e89c0
DF		 580 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
581
a94d5569
DF		 582 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
583
4562236b
HW		 584 return 0;
585}
586
a94d5569
DF		 587static int dm_sw_init(void *handle)
588{
589 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
590
591 return load_dmcu_fw(adev);
592}
593
4562236b
HW		 594static int dm_sw_fini(void *handle)
595{
a94d5569
DF		 596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
598 if(adev->dm.fw_dmcu) {
599 release_firmware(adev->dm.fw_dmcu);
600 adev->dm.fw_dmcu = NULL;
601 }
602
4562236b
HW		 603 return 0;
604}
605
7abcf6b5 606static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 607{
c84dec2f 608 struct amdgpu_dm_connector *aconnector;
4562236b 609 struct drm_connector *connector;
7abcf6b5 610 int ret = 0;
4562236b
HW		 611
612 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
613
614 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 615 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 616 if (aconnector->dc_link->type == dc_connection_mst_branch &&
617 aconnector->mst_mgr.aux) {
f1ad2f5e 618 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 619 aconnector, aconnector->base.base.id);
620
621 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
622 if (ret < 0) {
623 DRM_ERROR("DM_MST: Failed to start MST\n");
624 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
625 return ret;
4562236b 626 }
7abcf6b5 627 }
4562236b
HW		 628 }
629
630 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 631 return ret;
632}
633
634static int dm_late_init(void *handle)
635{
42e67c3b 636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 637
42e67c3b 638 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 639}
640
641static void s3_handle_mst(struct drm_device *dev, bool suspend)
642{
c84dec2f 643 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 644 struct drm_connector *connector;
645
646 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
647
648 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
c84dec2f 649 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 650 if (aconnector->dc_link->type == dc_connection_mst_branch &&
651 !aconnector->mst_port) {
652
653 if (suspend)
654 drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
655 else
656 drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
657 }
658 }
659
660 drm_modeset_unlock(&dev->mode_config.connection_mutex);
661}
662
663static int dm_hw_init(void *handle)
664{
665 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
666 /* Create DAL display manager */
667 amdgpu_dm_init(adev);
4562236b
HW		 668 amdgpu_dm_hpd_init(adev);
669
4562236b
HW		 670 return 0;
671}
672
673static int dm_hw_fini(void *handle)
674{
675 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
676
677 amdgpu_dm_hpd_fini(adev);
678
679 amdgpu_dm_irq_fini(adev);
21de3396 680 amdgpu_dm_fini(adev);
4562236b
HW		 681 return 0;
682}
683
684static int dm_suspend(void *handle)
685{
686 struct amdgpu_device *adev = handle;
687 struct amdgpu_display_manager *dm = &adev->dm;
688 int ret = 0;
4562236b
HW		 689
690 s3_handle_mst(adev->ddev, true);
691
4562236b
HW		 692 amdgpu_dm_irq_suspend(adev);
693
0a214e2f 694 WARN_ON(adev->dm.cached_state);
a3621485
AG		 695 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
696
32f5062d 697 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 698
699 return ret;
700}
701
1daf8c63
AD		 702static struct amdgpu_dm_connector *
703amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
704 struct drm_crtc *crtc)
4562236b
HW		 705{
706 uint32_t i;
c2cea706 707 struct drm_connector_state *new_con_state;
4562236b
HW		 708 struct drm_connector *connector;
709 struct drm_crtc *crtc_from_state;
710
c2cea706
LSL		 711 for_each_new_connector_in_state(state, connector, new_con_state, i) {
712 crtc_from_state = new_con_state->crtc;
4562236b
HW		 713
714 if (crtc_from_state == crtc)
c84dec2f 715 return to_amdgpu_dm_connector(connector);
4562236b
HW		 716 }
717
718 return NULL;
719}
720
4562236b
HW		 721static int dm_resume(void *handle)
722{
723 struct amdgpu_device *adev = handle;
4562236b
HW		 724 struct drm_device *ddev = adev->ddev;
725 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 726 struct amdgpu_dm_connector *aconnector;
4562236b 727 struct drm_connector *connector;
4562236b 728 struct drm_crtc *crtc;
c2cea706 729 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 730 struct dm_crtc_state *dm_new_crtc_state;
731 struct drm_plane *plane;
732 struct drm_plane_state *new_plane_state;
733 struct dm_plane_state *dm_new_plane_state;
a80aa93d 734 int ret;
a3621485 735 int i;
4562236b 736
a80aa93d
ML		 737 /* power on hardware */
738 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
739
4562236b
HW		 740 /* program HPD filter */
741 dc_resume(dm->dc);
742
743 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
744 s3_handle_mst(ddev, false);
745
746 /*
747 * early enable HPD Rx IRQ, should be done before set mode as short
748 * pulse interrupts are used for MST
749 */
750 amdgpu_dm_irq_resume_early(adev);
751
4562236b 752 /* Do detection*/
a80aa93d 753 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 754 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 755
756 /*
757 * this is the case when traversing through already created
758 * MST connectors, should be skipped
759 */
760 if (aconnector->mst_port)
761 continue;
762
03ea364c 763 mutex_lock(&aconnector->hpd_lock);
8f38b66c 764 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 765
766 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
767 aconnector->fake_enable = false;
768
4562236b
HW		 769 aconnector->dc_sink = NULL;
770 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 771 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 772 }
773
1f6010a9 774 /* Force mode set in atomic commit */
a80aa93d 775 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 776 new_crtc_state->active_changed = true;
4f346e65 777
fcb4019e
LSL		 778 /*
779 * atomic_check is expected to create the dc states. We need to release
780 * them here, since they were duplicated as part of the suspend
781 * procedure.
782 */
a80aa93d 783 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 784 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
785 if (dm_new_crtc_state->stream) {
786 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
787 dc_stream_release(dm_new_crtc_state->stream);
788 dm_new_crtc_state->stream = NULL;
789 }
790 }
791
a80aa93d 792 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 793 dm_new_plane_state = to_dm_plane_state(new_plane_state);
794 if (dm_new_plane_state->dc_state) {
795 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
796 dc_plane_state_release(dm_new_plane_state->dc_state);
797 dm_new_plane_state->dc_state = NULL;
798 }
799 }
800
a80aa93d 801 ret = drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 802
a80aa93d 803 dm->cached_state = NULL;
0a214e2f 804
9faa4237 805 amdgpu_dm_irq_resume_late(adev);
4562236b
HW		 806
807 return ret;
808}
809
810static const struct amd_ip_funcs amdgpu_dm_funcs = {
811 .name = "dm",
812 .early_init = dm_early_init,
7abcf6b5 813 .late_init = dm_late_init,
4562236b
HW		 814 .sw_init = dm_sw_init,
815 .sw_fini = dm_sw_fini,
816 .hw_init = dm_hw_init,
817 .hw_fini = dm_hw_fini,
818 .suspend = dm_suspend,
819 .resume = dm_resume,
820 .is_idle = dm_is_idle,
821 .wait_for_idle = dm_wait_for_idle,
822 .check_soft_reset = dm_check_soft_reset,
823 .soft_reset = dm_soft_reset,
824 .set_clockgating_state = dm_set_clockgating_state,
825 .set_powergating_state = dm_set_powergating_state,
826};
827
828const struct amdgpu_ip_block_version dm_ip_block =
829{
830 .type = AMD_IP_BLOCK_TYPE_DCE,
831 .major = 1,
832 .minor = 0,
833 .rev = 0,
834 .funcs = &amdgpu_dm_funcs,
835};
836
ca3268c4 837
7578ecda 838static struct drm_atomic_state *
ca3268c4
HW		 839dm_atomic_state_alloc(struct drm_device *dev)
840{
841 struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
842
1dc90497 843 if (!state)
ca3268c4 844 return NULL;
1dc90497
AG		 845
846 if (drm_atomic_state_init(dev, &state->base) < 0)
847 goto fail;
848
ca3268c4 849 return &state->base;
1dc90497
AG		 850
851fail:
852 kfree(state);
853 return NULL;
ca3268c4
HW		 854}
855
0a323b84
AG		 856static void
857dm_atomic_state_clear(struct drm_atomic_state *state)
858{
859 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
860
861 if (dm_state->context) {
608ac7bb 862 dc_release_state(dm_state->context);
0a323b84
AG		 863 dm_state->context = NULL;
864 }
865
866 drm_atomic_state_default_clear(state);
867}
868
869static void
870dm_atomic_state_alloc_free(struct drm_atomic_state *state)
871{
872 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
873 drm_atomic_state_default_release(state);
874 kfree(dm_state);
875}
876
b3663f70 877static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 878 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 879 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 880 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 881 .atomic_commit = amdgpu_dm_atomic_commit,
ca3268c4 882 .atomic_state_alloc = dm_atomic_state_alloc,
0a323b84
AG		 883 .atomic_state_clear = dm_atomic_state_clear,
884 .atomic_state_free = dm_atomic_state_alloc_free
54f5499a
AG		 885};
886
887static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
888 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 889};
890
7578ecda 891static void
3ee6b26b 892amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 893{
894 struct drm_connector *connector = &aconnector->base;
895 struct drm_device *dev = connector->dev;
b73a22d3 896 struct dc_sink *sink;
4562236b
HW		 897
898 /* MST handled by drm_mst framework */
899 if (aconnector->mst_mgr.mst_state == true)
900 return;
901
902
903 sink = aconnector->dc_link->local_sink;
904
1f6010a9
DF		 905 /*
906 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 907 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 908 * Skip if already done during boot.
4562236b
HW		 909 */
910 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
911 && aconnector->dc_em_sink) {
912
1f6010a9
DF		 913 /*
914 * For S3 resume with headless use eml_sink to fake stream
915 * because on resume connector->sink is set to NULL
4562236b
HW		 916 */
917 mutex_lock(&dev->mode_config.mutex);
918
919 if (sink) {
922aa1e1 920 if (aconnector->dc_sink) {
98e6436d 921 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 922 /*
923 * retain and release below are used to
924 * bump up refcount for sink because the link doesn't point
925 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 926 * reshuffle by UMD we will get into unwanted dc_sink release
927 */
928 if (aconnector->dc_sink != aconnector->dc_em_sink)
929 dc_sink_release(aconnector->dc_sink);
930 }
4562236b 931 aconnector->dc_sink = sink;
98e6436d
AK		 932 amdgpu_dm_update_freesync_caps(connector,
933 aconnector->edid);
4562236b 934 } else {
98e6436d 935 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 936 if (!aconnector->dc_sink)
937 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1
AG		 938 else if (aconnector->dc_sink != aconnector->dc_em_sink)
939 dc_sink_retain(aconnector->dc_sink);
4562236b
HW		 940 }
941
942 mutex_unlock(&dev->mode_config.mutex);
943 return;
944 }
945
946 /*
947 * TODO: temporary guard to look for proper fix
948 * if this sink is MST sink, we should not do anything
949 */
950 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
951 return;
952
953 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 954 /*
955 * We got a DP short pulse (Link Loss, DP CTS, etc...).
956 * Do nothing!!
957 */
f1ad2f5e 958 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b
HW		 959 aconnector->connector_id);
960 return;
961 }
962
f1ad2f5e 963 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 964 aconnector->connector_id, aconnector->dc_sink, sink);
965
966 mutex_lock(&dev->mode_config.mutex);
967
1f6010a9
DF		 968 /*
969 * 1. Update status of the drm connector
970 * 2. Send an event and let userspace tell us what to do
971 */
4562236b 972 if (sink) {
1f6010a9
DF		 973 /*
974 * TODO: check if we still need the S3 mode update workaround.
975 * If yes, put it here.
976 */
4562236b 977 if (aconnector->dc_sink)
98e6436d 978 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 979
980 aconnector->dc_sink = sink;
900b3cb1 981 if (sink->dc_edid.length == 0) {
4562236b 982 aconnector->edid = NULL;
e86e8947 983 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 984 } else {
4562236b
HW		 985 aconnector->edid =
986 (struct edid *) sink->dc_edid.raw_edid;
987
988
c555f023 989 drm_connector_update_edid_property(connector,
4562236b 990 aconnector->edid);
e86e8947
HV		 991 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
992 aconnector->edid);
4562236b 993 }
98e6436d 994 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 995
996 } else {
e86e8947 997 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 998 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 999 drm_connector_update_edid_property(connector, NULL);
4562236b
HW		 1000 aconnector->num_modes = 0;
1001 aconnector->dc_sink = NULL;
5326c452 1002 aconnector->edid = NULL;
4562236b
HW		 1003 }
1004
1005 mutex_unlock(&dev->mode_config.mutex);
1006}
1007
1008static void handle_hpd_irq(void *param)
1009{
c84dec2f 1010 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1011 struct drm_connector *connector = &aconnector->base;
1012 struct drm_device *dev = connector->dev;
1013
1f6010a9
DF		 1014 /*
1015 * In case of failure or MST no need to update connector status or notify the OS
1016 * since (for MST case) MST does this in its own context.
4562236b
HW		 1017 */
1018 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1019
1020 if (aconnector->fake_enable)
1021 aconnector->fake_enable = false;
1022
8f38b66c 1023 if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1024 amdgpu_dm_update_connector_after_detect(aconnector);
1025
1026
1027 drm_modeset_lock_all(dev);
1028 dm_restore_drm_connector_state(dev, connector);
1029 drm_modeset_unlock_all(dev);
1030
1031 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1032 drm_kms_helper_hotplug_event(dev);
1033 }
1034 mutex_unlock(&aconnector->hpd_lock);
1035
1036}
1037
c84dec2f 1038static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1039{
1040 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1041 uint8_t dret;
1042 bool new_irq_handled = false;
1043 int dpcd_addr;
1044 int dpcd_bytes_to_read;
1045
1046 const int max_process_count = 30;
1047 int process_count = 0;
1048
1049 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1050
1051 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1052 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1053 /* DPCD 0x200 - 0x201 for downstream IRQ */
1054 dpcd_addr = DP_SINK_COUNT;
1055 } else {
1056 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1057 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1058 dpcd_addr = DP_SINK_COUNT_ESI;
1059 }
1060
1061 dret = drm_dp_dpcd_read(
1062 &aconnector->dm_dp_aux.aux,
1063 dpcd_addr,
1064 esi,
1065 dpcd_bytes_to_read);
1066
1067 while (dret == dpcd_bytes_to_read &&
1068 process_count < max_process_count) {
1069 uint8_t retry;
1070 dret = 0;
1071
1072 process_count++;
1073
f1ad2f5e 1074 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1075 /* handle HPD short pulse irq */
1076 if (aconnector->mst_mgr.mst_state)
1077 drm_dp_mst_hpd_irq(
1078 &aconnector->mst_mgr,
1079 esi,
1080 &new_irq_handled);
4562236b
HW		 1081
1082 if (new_irq_handled) {
1083 /* ACK at DPCD to notify down stream */
1084 const int ack_dpcd_bytes_to_write =
1085 dpcd_bytes_to_read - 1;
1086
1087 for (retry = 0; retry < 3; retry++) {
1088 uint8_t wret;
1089
1090 wret = drm_dp_dpcd_write(
1091 &aconnector->dm_dp_aux.aux,
1092 dpcd_addr + 1,
1093 &esi[1],
1094 ack_dpcd_bytes_to_write);
1095 if (wret == ack_dpcd_bytes_to_write)
1096 break;
1097 }
1098
1f6010a9 1099 /* check if there is new irq to be handled */
4562236b
HW		 1100 dret = drm_dp_dpcd_read(
1101 &aconnector->dm_dp_aux.aux,
1102 dpcd_addr,
1103 esi,
1104 dpcd_bytes_to_read);
1105
1106 new_irq_handled = false;
d4a6e8a9 1107 } else {
4562236b 1108 break;
d4a6e8a9 1109 }
4562236b
HW		 1110 }
1111
1112 if (process_count == max_process_count)
f1ad2f5e 1113 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1114}
1115
1116static void handle_hpd_rx_irq(void *param)
1117{
c84dec2f 1118 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1119 struct drm_connector *connector = &aconnector->base;
1120 struct drm_device *dev = connector->dev;
53cbf65c 1121 struct dc_link *dc_link = aconnector->dc_link;
4562236b
HW		 1122 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1123
1f6010a9
DF		 1124 /*
1125 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1126 * conflict, after implement i2c helper, this mutex should be
1127 * retired.
1128 */
53cbf65c 1129 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1130 mutex_lock(&aconnector->hpd_lock);
1131
4e18814e 1132 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1133 !is_mst_root_connector) {
1134 /* Downstream Port status changed. */
53cbf65c 1135 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1136
1137 if (aconnector->fake_enable)
1138 aconnector->fake_enable = false;
1139
4562236b
HW		 1140 amdgpu_dm_update_connector_after_detect(aconnector);
1141
1142
1143 drm_modeset_lock_all(dev);
1144 dm_restore_drm_connector_state(dev, connector);
1145 drm_modeset_unlock_all(dev);
1146
1147 drm_kms_helper_hotplug_event(dev);
1148 }
1149 }
1150 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1151 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1152 dm_handle_hpd_rx_irq(aconnector);
1153
e86e8947
HV		 1154 if (dc_link->type != dc_connection_mst_branch) {
1155 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1156 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1157 }
4562236b
HW		 1158}
1159
1160static void register_hpd_handlers(struct amdgpu_device *adev)
1161{
1162 struct drm_device *dev = adev->ddev;
1163 struct drm_connector *connector;
c84dec2f 1164 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1165 const struct dc_link *dc_link;
1166 struct dc_interrupt_params int_params = {0};
1167
1168 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1169 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1170
1171 list_for_each_entry(connector,
1172 &dev->mode_config.connector_list, head) {
1173
c84dec2f 1174 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1175 dc_link = aconnector->dc_link;
1176
1177 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1178 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1179 int_params.irq_source = dc_link->irq_source_hpd;
1180
1181 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1182 handle_hpd_irq,
1183 (void *) aconnector);
1184 }
1185
1186 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1187
1188 /* Also register for DP short pulse (hpd_rx). */
1189 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1190 int_params.irq_source = dc_link->irq_source_hpd_rx;
1191
1192 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1193 handle_hpd_rx_irq,
1194 (void *) aconnector);
1195 }
1196 }
1197}
1198
1199/* Register IRQ sources and initialize IRQ callbacks */
1200static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1201{
1202 struct dc *dc = adev->dm.dc;
1203 struct common_irq_params *c_irq_params;
1204 struct dc_interrupt_params int_params = {0};
1205 int r;
1206 int i;
2c8ad2d5
AD		 1207 unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1208
ff5ef992 1209 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1210 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1211 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1212 adev->asic_type == CHIP_RAVEN)
3760f76c 1213 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1214
1215 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1216 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1217
1f6010a9
DF		 1218 /*
1219 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1220 * 1. Register a set() function with base driver.
1221 * Base driver will call set() function to enable/disable an
1222 * interrupt in DC hardware.
1223 * 2. Register amdgpu_dm_irq_handler().
1224 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1225 * coming from DC hardware.
1226 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1227 * for acknowledging and handling. */
1228
b57de80a 1229 /* Use VBLANK interrupt */
e9029155 1230 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1231 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1232 if (r) {
1233 DRM_ERROR("Failed to add crtc irq id!\n");
1234 return r;
1235 }
1236
1237 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1238 int_params.irq_source =
3d761e79 1239 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1240
b57de80a 1241 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1242
1243 c_irq_params->adev = adev;
1244 c_irq_params->irq_src = int_params.irq_source;
1245
1246 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1247 dm_crtc_high_irq, c_irq_params);
1248 }
1249
3d761e79 1250 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1251 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1252 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1253 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1254 if (r) {
1255 DRM_ERROR("Failed to add page flip irq id!\n");
1256 return r;
1257 }
1258
1259 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1260 int_params.irq_source =
1261 dc_interrupt_to_irq_source(dc, i, 0);
1262
1263 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1264
1265 c_irq_params->adev = adev;
1266 c_irq_params->irq_src = int_params.irq_source;
1267
1268 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1269 dm_pflip_high_irq, c_irq_params);
1270
1271 }
1272
1273 /* HPD */
2c8ad2d5
AD		 1274 r = amdgpu_irq_add_id(adev, client_id,
1275 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1276 if (r) {
1277 DRM_ERROR("Failed to add hpd irq id!\n");
1278 return r;
1279 }
1280
1281 register_hpd_handlers(adev);
1282
1283 return 0;
1284}
1285
ff5ef992
AD		 1286#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1287/* Register IRQ sources and initialize IRQ callbacks */
1288static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1289{
1290 struct dc *dc = adev->dm.dc;
1291 struct common_irq_params *c_irq_params;
1292 struct dc_interrupt_params int_params = {0};
1293 int r;
1294 int i;
1295
1296 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1297 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1298
1f6010a9
DF		 1299 /*
1300 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1301 * 1. Register a set() function with base driver.
1302 * Base driver will call set() function to enable/disable an
1303 * interrupt in DC hardware.
1304 * 2. Register amdgpu_dm_irq_handler().
1305 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1306 * coming from DC hardware.
1307 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1308 * for acknowledging and handling.
1f6010a9 1309 */
ff5ef992
AD		 1310
1311 /* Use VSTARTUP interrupt */
1312 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1313 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1314 i++) {
3760f76c 1315 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1316
1317 if (r) {
1318 DRM_ERROR("Failed to add crtc irq id!\n");
1319 return r;
1320 }
1321
1322 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1323 int_params.irq_source =
1324 dc_interrupt_to_irq_source(dc, i, 0);
1325
1326 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1327
1328 c_irq_params->adev = adev;
1329 c_irq_params->irq_src = int_params.irq_source;
1330
1331 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1332 dm_crtc_high_irq, c_irq_params);
1333 }
1334
1335 /* Use GRPH_PFLIP interrupt */
1336 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1337 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1338 i++) {
3760f76c 1339 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1340 if (r) {
1341 DRM_ERROR("Failed to add page flip irq id!\n");
1342 return r;
1343 }
1344
1345 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1346 int_params.irq_source =
1347 dc_interrupt_to_irq_source(dc, i, 0);
1348
1349 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1350
1351 c_irq_params->adev = adev;
1352 c_irq_params->irq_src = int_params.irq_source;
1353
1354 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1355 dm_pflip_high_irq, c_irq_params);
1356
1357 }
1358
1359 /* HPD */
3760f76c 1360 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1361 &adev->hpd_irq);
1362 if (r) {
1363 DRM_ERROR("Failed to add hpd irq id!\n");
1364 return r;
1365 }
1366
1367 register_hpd_handlers(adev);
1368
1369 return 0;
1370}
1371#endif
1372
4562236b
HW		 1373static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1374{
1375 int r;
1376
1377 adev->mode_info.mode_config_initialized = true;
1378
4562236b 1379 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1380 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1381
1382 adev->ddev->mode_config.max_width = 16384;
1383 adev->ddev->mode_config.max_height = 16384;
1384
1385 adev->ddev->mode_config.preferred_depth = 24;
1386 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1387 /* indicates support for immediate flip */
4562236b
HW		 1388 adev->ddev->mode_config.async_page_flip = true;
1389
770d13b1 1390 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1391
3dc9b1ce 1392 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1393 if (r)
1394 return r;
1395
1396 return 0;
1397}
1398
1399#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1400 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1401
1402static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1403{
1404 struct amdgpu_display_manager *dm = bl_get_data(bd);
1405
1406 if (dc_link_set_backlight_level(dm->backlight_link,
1407 bd->props.brightness, 0, 0))
1408 return 0;
1409 else
1410 return 1;
1411}
1412
1413static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1414{
620a0d27
DF		 1415 struct amdgpu_display_manager *dm = bl_get_data(bd);
1416 int ret = dc_link_get_backlight_level(dm->backlight_link);
1417
1418 if (ret == DC_ERROR_UNEXPECTED)
1419 return bd->props.brightness;
1420 return ret;
4562236b
HW		 1421}
1422
1423static const struct backlight_ops amdgpu_dm_backlight_ops = {
1424 .get_brightness = amdgpu_dm_backlight_get_brightness,
1425 .update_status = amdgpu_dm_backlight_update_status,
1426};
1427
7578ecda
AD		 1428static void
1429amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1430{
1431 char bl_name[16];
1432 struct backlight_properties props = { 0 };
1433
1434 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1435 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1436 props.type = BACKLIGHT_RAW;
1437
1438 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1439 dm->adev->ddev->primary->index);
1440
1441 dm->backlight_dev = backlight_device_register(bl_name,
1442 dm->adev->ddev->dev,
1443 dm,
1444 &amdgpu_dm_backlight_ops,
1445 &props);
1446
74baea42 1447 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1448 DRM_ERROR("DM: Backlight registration failed!\n");
1449 else
f1ad2f5e 1450 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1451}
1452
1453#endif
1454
df534fff
S		 1455static int initialize_plane(struct amdgpu_display_manager *dm,
1456 struct amdgpu_mode_info *mode_info,
1457 int plane_id)
1458{
1459 struct amdgpu_plane *plane;
1460 unsigned long possible_crtcs;
1461 int ret = 0;
1462
1463 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1464 mode_info->planes[plane_id] = plane;
1465
1466 if (!plane) {
1467 DRM_ERROR("KMS: Failed to allocate plane\n");
1468 return -ENOMEM;
1469 }
1470 plane->base.type = mode_info->plane_type[plane_id];
1471
1472 /*
1f6010a9 1473 * HACK: IGT tests expect that each plane can only have
df534fff
S		 1474 * one possible CRTC. For now, set one CRTC for each
1475 * plane that is not an underlay, but still allow multiple
1476 * CRTCs for underlay planes.
1477 */
1478 possible_crtcs = 1 << plane_id;
1479 if (plane_id >= dm->dc->caps.max_streams)
1480 possible_crtcs = 0xff;
1481
1482 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1483
1484 if (ret) {
1485 DRM_ERROR("KMS: Failed to initialize plane\n");
1486 return ret;
1487 }
1488
1489 return ret;
1490}
1491
89fc8d4e
HW		 1492
1493static void register_backlight_device(struct amdgpu_display_manager *dm,
1494 struct dc_link *link)
1495{
1496#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1497 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1498
1499 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1500 link->type != dc_connection_none) {
1f6010a9
DF		 1501 /*
1502 * Event if registration failed, we should continue with
89fc8d4e
HW		 1503 * DM initialization because not having a backlight control
1504 * is better then a black screen.
1505 */
1506 amdgpu_dm_register_backlight_device(dm);
1507
1508 if (dm->backlight_dev)
1509 dm->backlight_link = link;
1510 }
1511#endif
1512}
1513
1514
1f6010a9
DF		 1515/*
1516 * In this architecture, the association
4562236b
HW		 1517 * connector -> encoder -> crtc
1518 * id not really requried. The crtc and connector will hold the
1519 * display_index as an abstraction to use with DAL component
1520 *
1521 * Returns 0 on success
1522 */
7578ecda 1523static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1524{
1525 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1526 int32_t i;
c84dec2f 1527 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1528 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1529 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1530 uint32_t link_cnt;
df534fff 1531 int32_t total_overlay_planes, total_primary_planes;
4562236b
HW		 1532
1533 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1534 if (amdgpu_dm_mode_config_init(dm->adev)) {
1535 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 1536 return -EINVAL;
4562236b
HW		 1537 }
1538
df534fff
S		 1539 /* Identify the number of planes to be initialized */
1540 total_overlay_planes = dm->dc->caps.max_slave_planes;
1541 total_primary_planes = dm->dc->caps.max_planes - dm->dc->caps.max_slave_planes;
efa6a8b7 1542
df534fff
S		 1543 /* First initialize overlay planes, index starting after primary planes */
1544 for (i = (total_overlay_planes - 1); i >= 0; i--) {
1545 if (initialize_plane(dm, mode_info, (total_primary_planes + i))) {
1546 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
cd8a2ae8 1547 goto fail;
d4e13b0d 1548 }
df534fff 1549 }
92f3ac40 1550
df534fff
S		 1551 /* Initialize primary planes */
1552 for (i = (total_primary_planes - 1); i >= 0; i--) {
1553 if (initialize_plane(dm, mode_info, i)) {
1554 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1555 goto fail;
d4e13b0d
AD		 1556 }
1557 }
4562236b 1558
d4e13b0d
AD		 1559 for (i = 0; i < dm->dc->caps.max_streams; i++)
1560 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
4562236b 1561 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1562 goto fail;
4562236b 1563 }
4562236b 1564
ab2541b6 1565 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1566
1567 /* loops over all connectors on the board */
1568 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1569 struct dc_link *link = NULL;
4562236b
HW		 1570
1571 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1572 DRM_ERROR(
1573 "KMS: Cannot support more than %d display indexes\n",
1574 AMDGPU_DM_MAX_DISPLAY_INDEX);
1575 continue;
1576 }
1577
1578 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1579 if (!aconnector)
cd8a2ae8 1580 goto fail;
4562236b
HW		 1581
1582 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1583 if (!aencoder)
cd8a2ae8 1584 goto fail;
4562236b
HW		 1585
1586 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1587 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1588 goto fail;
4562236b
HW		 1589 }
1590
1591 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1592 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1593 goto fail;
4562236b
HW		 1594 }
1595
89fc8d4e
HW		 1596 link = dc_get_link_at_index(dm->dc, i);
1597
1598 if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 1599 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 1600 register_backlight_device(dm, link);
1601 }
1602
1603
4562236b
HW		 1604 }
1605
1606 /* Software is initialized. Now we can register interrupt handlers. */
1607 switch (adev->asic_type) {
1608 case CHIP_BONAIRE:
1609 case CHIP_HAWAII:
cd4b356f
AD		 1610 case CHIP_KAVERI:
1611 case CHIP_KABINI:
1612 case CHIP_MULLINS:
4562236b
HW		 1613 case CHIP_TONGA:
1614 case CHIP_FIJI:
1615 case CHIP_CARRIZO:
1616 case CHIP_STONEY:
1617 case CHIP_POLARIS11:
1618 case CHIP_POLARIS10:
b264d345 1619 case CHIP_POLARIS12:
7737de91 1620 case CHIP_VEGAM:
2c8ad2d5 1621 case CHIP_VEGA10:
2325ff30 1622 case CHIP_VEGA12:
1fe6bf2f 1623 case CHIP_VEGA20:
4562236b
HW		 1624 if (dce110_register_irq_handlers(dm->adev)) {
1625 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1626 goto fail;
4562236b
HW		 1627 }
1628 break;
ff5ef992
AD		 1629#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1630 case CHIP_RAVEN:
1631 if (dcn10_register_irq_handlers(dm->adev)) {
1632 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 1633 goto fail;
ff5ef992
AD		 1634 }
1635 break;
1636#endif
4562236b 1637 default:
e63f8673 1638 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 1639 goto fail;
4562236b
HW		 1640 }
1641
1bc460a4
HW		 1642 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1643 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1644
4562236b 1645 return 0;
cd8a2ae8 1646fail:
4562236b 1647 kfree(aencoder);
4562236b 1648 kfree(aconnector);
3be5262e 1649 for (i = 0; i < dm->dc->caps.max_planes; i++)
d4e13b0d 1650 kfree(mode_info->planes[i]);
59d0f396 1651 return -EINVAL;
4562236b
HW		 1652}
1653
7578ecda 1654static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1655{
1656 drm_mode_config_cleanup(dm->ddev);
1657 return;
1658}
1659
1660/******************************************************************************
1661 * amdgpu_display_funcs functions
1662 *****************************************************************************/
1663
1f6010a9 1664/*
4562236b
HW		 1665 * dm_bandwidth_update - program display watermarks
1666 *
1667 * @adev: amdgpu_device pointer
1668 *
1669 * Calculate and program the display watermarks and line buffer allocation.
1670 */
1671static void dm_bandwidth_update(struct amdgpu_device *adev)
1672{
49c07a99 1673 /* TODO: implement later */
4562236b
HW		 1674}
1675
4562236b
HW		 1676static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1677 struct drm_file *filp)
1678{
98e6436d
AK		 1679 struct drm_atomic_state *state;
1680 struct drm_modeset_acquire_ctx ctx;
1681 struct drm_crtc *crtc;
1682 struct drm_connector *connector;
1683 struct drm_connector_state *old_con_state, *new_con_state;
1684 int ret = 0;
4562236b 1685 uint8_t i;
98e6436d 1686 bool enable = false;
4562236b 1687
98e6436d 1688 drm_modeset_acquire_init(&ctx, 0);
4562236b 1689
98e6436d
AK		 1690 state = drm_atomic_state_alloc(dev);
1691 if (!state) {
1692 ret = -ENOMEM;
1693 goto out;
1694 }
1695 state->acquire_ctx = &ctx;
1696
1697retry:
1698 drm_for_each_crtc(crtc, dev) {
1699 ret = drm_atomic_add_affected_connectors(state, crtc);
1700 if (ret)
1701 goto fail;
1702
1703 /* TODO rework amdgpu_dm_commit_planes so we don't need this */
1704 ret = drm_atomic_add_affected_planes(state, crtc);
1705 if (ret)
1706 goto fail;
1707 }
4562236b 1708
98e6436d
AK		 1709 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
1710 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
1711 struct drm_crtc_state *new_crtc_state;
1712 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
1713 struct dm_crtc_state *dm_new_crtc_state;
4562236b 1714
98e6436d
AK		 1715 if (!acrtc) {
1716 ASSERT(0);
1717 continue;
1718 }
4562236b 1719
98e6436d
AK		 1720 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
1721 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4562236b 1722
98e6436d 1723 dm_new_crtc_state->freesync_enabled = enable;
4562236b
HW		 1724 }
1725
98e6436d
AK		 1726 ret = drm_atomic_commit(state);
1727
1728fail:
1729 if (ret == -EDEADLK) {
1730 drm_atomic_state_clear(state);
1731 drm_modeset_backoff(&ctx);
1732 goto retry;
1733 }
1734
1735 drm_atomic_state_put(state);
1736
1737out:
1738 drm_modeset_drop_locks(&ctx);
1739 drm_modeset_acquire_fini(&ctx);
1740 return ret;
4562236b
HW		 1741}
1742
39cc5be2 1743static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 1744 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1745 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 1746 .backlight_set_level = NULL, /* never called for DC */
1747 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 1748 .hpd_sense = NULL,/* called unconditionally */
1749 .hpd_set_polarity = NULL, /* called unconditionally */
1750 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 1751 .page_flip_get_scanoutpos =
1752 dm_crtc_get_scanoutpos,/* called unconditionally */
1753 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1754 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1755 .notify_freesync = amdgpu_notify_freesync,
1756
1757};
1758
1759#if defined(CONFIG_DEBUG_KERNEL_DC)
1760
3ee6b26b
AD		 1761static ssize_t s3_debug_store(struct device *device,
1762 struct device_attribute *attr,
1763 const char *buf,
1764 size_t count)
4562236b
HW		 1765{
1766 int ret;
1767 int s3_state;
1768 struct pci_dev *pdev = to_pci_dev(device);
1769 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1770 struct amdgpu_device *adev = drm_dev->dev_private;
1771
1772 ret = kstrtoint(buf, 0, &s3_state);
1773
1774 if (ret == 0) {
1775 if (s3_state) {
1776 dm_resume(adev);
4562236b
HW		 1777 drm_kms_helper_hotplug_event(adev->ddev);
1778 } else
1779 dm_suspend(adev);
1780 }
1781
1782 return ret == 0 ? count : 0;
1783}
1784
1785DEVICE_ATTR_WO(s3_debug);
1786
1787#endif
1788
1789static int dm_early_init(void *handle)
1790{
1791 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1792
4562236b
HW		 1793 switch (adev->asic_type) {
1794 case CHIP_BONAIRE:
1795 case CHIP_HAWAII:
1796 adev->mode_info.num_crtc = 6;
1797 adev->mode_info.num_hpd = 6;
1798 adev->mode_info.num_dig = 6;
3be5262e 1799 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1800 break;
cd4b356f
AD		 1801 case CHIP_KAVERI:
1802 adev->mode_info.num_crtc = 4;
1803 adev->mode_info.num_hpd = 6;
1804 adev->mode_info.num_dig = 7;
1805 adev->mode_info.plane_type = dm_plane_type_default;
1806 break;
1807 case CHIP_KABINI:
1808 case CHIP_MULLINS:
1809 adev->mode_info.num_crtc = 2;
1810 adev->mode_info.num_hpd = 6;
1811 adev->mode_info.num_dig = 6;
1812 adev->mode_info.plane_type = dm_plane_type_default;
1813 break;
4562236b
HW		 1814 case CHIP_FIJI:
1815 case CHIP_TONGA:
1816 adev->mode_info.num_crtc = 6;
1817 adev->mode_info.num_hpd = 6;
1818 adev->mode_info.num_dig = 7;
3be5262e 1819 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1820 break;
1821 case CHIP_CARRIZO:
1822 adev->mode_info.num_crtc = 3;
1823 adev->mode_info.num_hpd = 6;
1824 adev->mode_info.num_dig = 9;
3be5262e 1825 adev->mode_info.plane_type = dm_plane_type_carizzo;
4562236b
HW		 1826 break;
1827 case CHIP_STONEY:
1828 adev->mode_info.num_crtc = 2;
1829 adev->mode_info.num_hpd = 6;
1830 adev->mode_info.num_dig = 9;
3be5262e 1831 adev->mode_info.plane_type = dm_plane_type_stoney;
4562236b
HW		 1832 break;
1833 case CHIP_POLARIS11:
b264d345 1834 case CHIP_POLARIS12:
4562236b
HW		 1835 adev->mode_info.num_crtc = 5;
1836 adev->mode_info.num_hpd = 5;
1837 adev->mode_info.num_dig = 5;
3be5262e 1838 adev->mode_info.plane_type = dm_plane_type_default;
4562236b
HW		 1839 break;
1840 case CHIP_POLARIS10:
7737de91 1841 case CHIP_VEGAM:
4562236b
HW		 1842 adev->mode_info.num_crtc = 6;
1843 adev->mode_info.num_hpd = 6;
1844 adev->mode_info.num_dig = 6;
3be5262e 1845 adev->mode_info.plane_type = dm_plane_type_default;
4562236b 1846 break;
2c8ad2d5 1847 case CHIP_VEGA10:
2325ff30 1848 case CHIP_VEGA12:
1fe6bf2f 1849 case CHIP_VEGA20:
2c8ad2d5
AD		 1850 adev->mode_info.num_crtc = 6;
1851 adev->mode_info.num_hpd = 6;
1852 adev->mode_info.num_dig = 6;
3be5262e 1853 adev->mode_info.plane_type = dm_plane_type_default;
2c8ad2d5 1854 break;
ff5ef992
AD		 1855#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1856 case CHIP_RAVEN:
1857 adev->mode_info.num_crtc = 4;
1858 adev->mode_info.num_hpd = 4;
1859 adev->mode_info.num_dig = 4;
3be5262e 1860 adev->mode_info.plane_type = dm_plane_type_default;
ff5ef992
AD		 1861 break;
1862#endif
4562236b 1863 default:
e63f8673 1864 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 1865 return -EINVAL;
1866 }
1867
c8dd5715
MD		 1868 amdgpu_dm_set_irq_funcs(adev);
1869
39cc5be2
AD		 1870 if (adev->mode_info.funcs == NULL)
1871 adev->mode_info.funcs = &dm_display_funcs;
1872
1f6010a9
DF		 1873 /*
1874 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 1875 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 1876 * amdgpu_device_init()
1877 */
4562236b
HW		 1878#if defined(CONFIG_DEBUG_KERNEL_DC)
1879 device_create_file(
1880 adev->ddev->dev,
1881 &dev_attr_s3_debug);
1882#endif
1883
1884 return 0;
1885}
1886
9b690ef3 1887static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 1888 struct dc_stream_state *new_stream,
1889 struct dc_stream_state *old_stream)
9b690ef3 1890{
e7b07cee
HW		 1891 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1892 return false;
1893
1894 if (!crtc_state->enable)
1895 return false;
1896
1897 return crtc_state->active;
1898}
1899
1900static bool modereset_required(struct drm_crtc_state *crtc_state)
1901{
1902 if (!drm_atomic_crtc_needs_modeset(crtc_state))
1903 return false;
1904
1905 return !crtc_state->enable || !crtc_state->active;
1906}
1907
7578ecda 1908static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 1909{
1910 drm_encoder_cleanup(encoder);
1911 kfree(encoder);
1912}
1913
1914static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1915 .destroy = amdgpu_dm_encoder_destroy,
1916};
1917
3ee6b26b
AD		 1918static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1919 struct dc_plane_state *plane_state)
e7b07cee 1920{
3be5262e
HW		 1921 plane_state->src_rect.x = state->src_x >> 16;
1922 plane_state->src_rect.y = state->src_y >> 16;
1f6010a9 1923 /* we ignore the mantissa for now and do not deal with floating pixels :( */
3be5262e 1924 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 1925
3be5262e 1926 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 1927 return false;
1928
3be5262e
HW		 1929 plane_state->src_rect.height = state->src_h >> 16;
1930 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 1931 return false;
1932
3be5262e
HW		 1933 plane_state->dst_rect.x = state->crtc_x;
1934 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 1935
1936 if (state->crtc_w == 0)
1937 return false;
1938
3be5262e 1939 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 1940
1941 if (state->crtc_h == 0)
1942 return false;
1943
3be5262e 1944 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 1945
3be5262e 1946 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 1947
1948 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1949 case DRM_MODE_ROTATE_0:
3be5262e 1950 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1951 break;
1952 case DRM_MODE_ROTATE_90:
3be5262e 1953 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 1954 break;
1955 case DRM_MODE_ROTATE_180:
3be5262e 1956 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 1957 break;
1958 case DRM_MODE_ROTATE_270:
3be5262e 1959 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 1960 break;
1961 default:
3be5262e 1962 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 1963 break;
1964 }
1965
4562236b
HW		 1966 return true;
1967}
3ee6b26b 1968static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 1969 uint64_t *tiling_flags)
e7b07cee 1970{
e68d14dd 1971 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 1972 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 1973
e7b07cee 1974 if (unlikely(r)) {
1f6010a9 1975 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 1976 if (r != -ERESTARTSYS)
1977 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 1978 return r;
1979 }
1980
e7b07cee
HW		 1981 if (tiling_flags)
1982 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1983
1984 amdgpu_bo_unreserve(rbo);
1985
1986 return r;
1987}
1988
3ee6b26b
AD		 1989static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1990 struct dc_plane_state *plane_state,
9817d5f5 1991 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 1992{
1993 uint64_t tiling_flags;
e7b07cee
HW		 1994 unsigned int awidth;
1995 const struct drm_framebuffer *fb = &amdgpu_fb->base;
1996 int ret = 0;
1997 struct drm_format_name_buf format_name;
1998
1999 ret = get_fb_info(
2000 amdgpu_fb,
9817d5f5 2001 &tiling_flags);
e7b07cee
HW		 2002
2003 if (ret)
2004 return ret;
2005
2006 switch (fb->format->format) {
2007 case DRM_FORMAT_C8:
3be5262e 2008 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 2009 break;
2010 case DRM_FORMAT_RGB565:
3be5262e 2011 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 2012 break;
2013 case DRM_FORMAT_XRGB8888:
2014 case DRM_FORMAT_ARGB8888:
3be5262e 2015 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 2016 break;
2017 case DRM_FORMAT_XRGB2101010:
2018 case DRM_FORMAT_ARGB2101010:
3be5262e 2019 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 2020 break;
2021 case DRM_FORMAT_XBGR2101010:
2022 case DRM_FORMAT_ABGR2101010:
3be5262e 2023 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 2024 break;
bcd47f60
MR		 2025 case DRM_FORMAT_XBGR8888:
2026 case DRM_FORMAT_ABGR8888:
2027 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2028 break;
e7b07cee 2029 case DRM_FORMAT_NV21:
3be5262e 2030 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 2031 break;
2032 case DRM_FORMAT_NV12:
3be5262e 2033 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 2034 break;
2035 default:
2036 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 2037 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 2038 return -EINVAL;
2039 }
2040
3be5262e
HW		 2041 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2042 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 2043 plane_state->plane_size.grph.surface_size.x = 0;
2044 plane_state->plane_size.grph.surface_size.y = 0;
2045 plane_state->plane_size.grph.surface_size.width = fb->width;
2046 plane_state->plane_size.grph.surface_size.height = fb->height;
2047 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 2048 fb->pitches[0] / fb->format->cpp[0];
2049 /* TODO: unhardcode */
3be5262e 2050 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 2051
2052 } else {
2053 awidth = ALIGN(fb->width, 64);
3be5262e 2054 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 2055 plane_state->plane_size.video.luma_size.x = 0;
2056 plane_state->plane_size.video.luma_size.y = 0;
2057 plane_state->plane_size.video.luma_size.width = awidth;
2058 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 2059 /* TODO: unhardcode */
3be5262e 2060 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 2061
3be5262e
HW		 2062 plane_state->plane_size.video.chroma_size.x = 0;
2063 plane_state->plane_size.video.chroma_size.y = 0;
2064 plane_state->plane_size.video.chroma_size.width = awidth;
2065 plane_state->plane_size.video.chroma_size.height = fb->height;
2066 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 2067
2068 /* TODO: unhardcode */
3be5262e 2069 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 2070 }
2071
3be5262e 2072 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
e7b07cee 2073
b830ebc9
HW		 2074 /* Fill GFX8 params */
2075 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2076 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 2077
2078 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2079 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2080 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2081 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2082 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2083
2084 /* XXX fix me for VI */
3be5262e
HW		 2085 plane_state->tiling_info.gfx8.num_banks = num_banks;
2086 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 2087 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 2088 plane_state->tiling_info.gfx8.tile_split = tile_split;
2089 plane_state->tiling_info.gfx8.bank_width = bankw;
2090 plane_state->tiling_info.gfx8.bank_height = bankh;
2091 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2092 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 2093 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2094 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2095 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 2096 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 2097 }
2098
3be5262e 2099 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2100 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2101
2102 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2103 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2104 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2105 adev->asic_type == CHIP_RAVEN) {
2106 /* Fill GFX9 params */
3be5262e 2107 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2108 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2109 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2110 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2111 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2112 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2113 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2114 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2115 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2116 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2117 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2118 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2119 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2120 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2121 plane_state->tiling_info.gfx9.shaderEnable = 1;
e7b07cee
HW		 2122 }
2123
3be5262e
HW		 2124 plane_state->visible = true;
2125 plane_state->scaling_quality.h_taps_c = 0;
2126 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2127
3be5262e
HW		 2128 /* is this needed? is plane_state zeroed at allocation? */
2129 plane_state->scaling_quality.h_taps = 0;
2130 plane_state->scaling_quality.v_taps = 0;
2131 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2132
2133 return ret;
2134
2135}
2136
3ee6b26b
AD		 2137static int fill_plane_attributes(struct amdgpu_device *adev,
2138 struct dc_plane_state *dc_plane_state,
2139 struct drm_plane_state *plane_state,
9817d5f5 2140 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2141{
2142 const struct amdgpu_framebuffer *amdgpu_fb =
2143 to_amdgpu_framebuffer(plane_state->fb);
2144 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2145 int ret = 0;
2146
3be5262e 2147 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2148 return -EINVAL;
2149
2150 ret = fill_plane_attributes_from_fb(
2151 crtc->dev->dev_private,
3be5262e 2152 dc_plane_state,
9817d5f5 2153 amdgpu_fb);
e7b07cee
HW		 2154
2155 if (ret)
2156 return ret;
2157
e277adc5
LSL		 2158 /*
2159 * Always set input transfer function, since plane state is refreshed
2160 * every time.
2161 */
2162 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2163 if (ret) {
2164 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2165 dc_plane_state->in_transfer_func = NULL;
2166 }
e7b07cee
HW		 2167
2168 return ret;
2169}
2170
3ee6b26b
AD		 2171static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2172 const struct dm_connector_state *dm_state,
2173 struct dc_stream_state *stream)
e7b07cee
HW		 2174{
2175 enum amdgpu_rmx_type rmx_type;
2176
2177 struct rect src = { 0 }; /* viewport in composition space*/
2178 struct rect dst = { 0 }; /* stream addressable area */
2179
2180 /* no mode. nothing to be done */
2181 if (!mode)
2182 return;
2183
2184 /* Full screen scaling by default */
2185 src.width = mode->hdisplay;
2186 src.height = mode->vdisplay;
2187 dst.width = stream->timing.h_addressable;
2188 dst.height = stream->timing.v_addressable;
2189
f4791779
HW		 2190 if (dm_state) {
2191 rmx_type = dm_state->scaling;
2192 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2193 if (src.width * dst.height <
2194 src.height * dst.width) {
2195 /* height needs less upscaling/more downscaling */
2196 dst.width = src.width *
2197 dst.height / src.height;
2198 } else {
2199 /* width needs less upscaling/more downscaling */
2200 dst.height = src.height *
2201 dst.width / src.width;
2202 }
2203 } else if (rmx_type == RMX_CENTER) {
2204 dst = src;
e7b07cee 2205 }
e7b07cee 2206
f4791779
HW		 2207 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2208 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2209
f4791779
HW		 2210 if (dm_state->underscan_enable) {
2211 dst.x += dm_state->underscan_hborder / 2;
2212 dst.y += dm_state->underscan_vborder / 2;
2213 dst.width -= dm_state->underscan_hborder;
2214 dst.height -= dm_state->underscan_vborder;
2215 }
e7b07cee
HW		 2216 }
2217
2218 stream->src = src;
2219 stream->dst = dst;
2220
f1ad2f5e 2221 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2222 dst.x, dst.y, dst.width, dst.height);
2223
2224}
2225
3ee6b26b
AD		 2226static enum dc_color_depth
2227convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee
HW		 2228{
2229 uint32_t bpc = connector->display_info.bpc;
2230
e7b07cee
HW		 2231 switch (bpc) {
2232 case 0:
1f6010a9
DF		 2233 /*
2234 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2235 * EDID revision before 1.4
2236 * TODO: Fix edid parsing
2237 */
2238 return COLOR_DEPTH_888;
2239 case 6:
2240 return COLOR_DEPTH_666;
2241 case 8:
2242 return COLOR_DEPTH_888;
2243 case 10:
2244 return COLOR_DEPTH_101010;
2245 case 12:
2246 return COLOR_DEPTH_121212;
2247 case 14:
2248 return COLOR_DEPTH_141414;
2249 case 16:
2250 return COLOR_DEPTH_161616;
2251 default:
2252 return COLOR_DEPTH_UNDEFINED;
2253 }
2254}
2255
3ee6b26b
AD		 2256static enum dc_aspect_ratio
2257get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2258{
e11d4147
LSL		 2259 /* 1-1 mapping, since both enums follow the HDMI spec. */
2260 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2261}
2262
3ee6b26b
AD		 2263static enum dc_color_space
2264get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2265{
2266 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2267
2268 switch (dc_crtc_timing->pixel_encoding) {
2269 case PIXEL_ENCODING_YCBCR422:
2270 case PIXEL_ENCODING_YCBCR444:
2271 case PIXEL_ENCODING_YCBCR420:
2272 {
2273 /*
2274 * 27030khz is the separation point between HDTV and SDTV
2275 * according to HDMI spec, we use YCbCr709 and YCbCr601
2276 * respectively
2277 */
2278 if (dc_crtc_timing->pix_clk_khz > 27030) {
2279 if (dc_crtc_timing->flags.Y_ONLY)
2280 color_space =
2281 COLOR_SPACE_YCBCR709_LIMITED;
2282 else
2283 color_space = COLOR_SPACE_YCBCR709;
2284 } else {
2285 if (dc_crtc_timing->flags.Y_ONLY)
2286 color_space =
2287 COLOR_SPACE_YCBCR601_LIMITED;
2288 else
2289 color_space = COLOR_SPACE_YCBCR601;
2290 }
2291
2292 }
2293 break;
2294 case PIXEL_ENCODING_RGB:
2295 color_space = COLOR_SPACE_SRGB;
2296 break;
2297
2298 default:
2299 WARN_ON(1);
2300 break;
2301 }
2302
2303 return color_space;
2304}
2305
400443e8
ML		 2306static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2307{
2308 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2309 return;
2310
2311 timing_out->display_color_depth--;
2312}
2313
2314static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2315 const struct drm_display_info *info)
2316{
2317 int normalized_clk;
2318 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2319 return;
2320 do {
2321 normalized_clk = timing_out->pix_clk_khz;
2322 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2323 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2324 normalized_clk /= 2;
2325 /* Adjusting pix clock following on HDMI spec based on colour depth */
2326 switch (timing_out->display_color_depth) {
2327 case COLOR_DEPTH_101010:
2328 normalized_clk = (normalized_clk * 30) / 24;
2329 break;
2330 case COLOR_DEPTH_121212:
2331 normalized_clk = (normalized_clk * 36) / 24;
2332 break;
2333 case COLOR_DEPTH_161616:
2334 normalized_clk = (normalized_clk * 48) / 24;
2335 break;
2336 default:
2337 return;
2338 }
2339 if (normalized_clk <= info->max_tmds_clock)
2340 return;
2341 reduce_mode_colour_depth(timing_out);
2342
2343 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2344
2345}
e7b07cee 2346
3ee6b26b
AD		 2347static void
2348fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2349 const struct drm_display_mode *mode_in,
2350 const struct drm_connector *connector)
e7b07cee
HW		 2351{
2352 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2353 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2354
e7b07cee
HW		 2355 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2356
2357 timing_out->h_border_left = 0;
2358 timing_out->h_border_right = 0;
2359 timing_out->v_border_top = 0;
2360 timing_out->v_border_bottom = 0;
2361 /* TODO: un-hardcode */
fe61a2f1
ML		 2362 if (drm_mode_is_420_only(info, mode_in)
2363 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2364 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2365 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
e7b07cee
HW		 2366 && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2367 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2368 else
2369 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2370
2371 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2372 timing_out->display_color_depth = convert_color_depth_from_display_info(
2373 connector);
2374 timing_out->scan_type = SCANNING_TYPE_NODATA;
2375 timing_out->hdmi_vic = 0;
2376 timing_out->vic = drm_match_cea_mode(mode_in);
2377
2378 timing_out->h_addressable = mode_in->crtc_hdisplay;
2379 timing_out->h_total = mode_in->crtc_htotal;
2380 timing_out->h_sync_width =
2381 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2382 timing_out->h_front_porch =
2383 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2384 timing_out->v_total = mode_in->crtc_vtotal;
2385 timing_out->v_addressable = mode_in->crtc_vdisplay;
2386 timing_out->v_front_porch =
2387 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2388 timing_out->v_sync_width =
2389 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2390 timing_out->pix_clk_khz = mode_in->crtc_clock;
2391 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2392 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2393 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2394 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2395 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2396
2397 stream->output_color_space = get_output_color_space(timing_out);
2398
e43a432c
AK		 2399 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2400 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
400443e8
ML		 2401 if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2402 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2403}
2404
3ee6b26b
AD		 2405static void fill_audio_info(struct audio_info *audio_info,
2406 const struct drm_connector *drm_connector,
2407 const struct dc_sink *dc_sink)
e7b07cee
HW		 2408{
2409 int i = 0;
2410 int cea_revision = 0;
2411 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2412
2413 audio_info->manufacture_id = edid_caps->manufacturer_id;
2414 audio_info->product_id = edid_caps->product_id;
2415
2416 cea_revision = drm_connector->display_info.cea_rev;
2417
d2b2562c
TSD		 2418 strncpy(audio_info->display_name,
2419 edid_caps->display_name,
2420 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
e7b07cee 2421
b830ebc9 2422 if (cea_revision >= 3) {
e7b07cee
HW		 2423 audio_info->mode_count = edid_caps->audio_mode_count;
2424
2425 for (i = 0; i < audio_info->mode_count; ++i) {
2426 audio_info->modes[i].format_code =
2427 (enum audio_format_code)
2428 (edid_caps->audio_modes[i].format_code);
2429 audio_info->modes[i].channel_count =
2430 edid_caps->audio_modes[i].channel_count;
2431 audio_info->modes[i].sample_rates.all =
2432 edid_caps->audio_modes[i].sample_rate;
2433 audio_info->modes[i].sample_size =
2434 edid_caps->audio_modes[i].sample_size;
2435 }
2436 }
2437
2438 audio_info->flags.all = edid_caps->speaker_flags;
2439
2440 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2441 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2442 audio_info->video_latency = drm_connector->video_latency[0];
2443 audio_info->audio_latency = drm_connector->audio_latency[0];
2444 }
2445
2446 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2447
2448}
2449
3ee6b26b
AD		 2450static void
2451copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2452 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2453{
2454 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2455 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2456 dst_mode->crtc_clock = src_mode->crtc_clock;
2457 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2458 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2459 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2460 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2461 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2462 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2463 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2464 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2465 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2466 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2467 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2468}
2469
3ee6b26b
AD		 2470static void
2471decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2472 const struct drm_display_mode *native_mode,
2473 bool scale_enabled)
e7b07cee
HW		 2474{
2475 if (scale_enabled) {
2476 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2477 } else if (native_mode->clock == drm_mode->clock &&
2478 native_mode->htotal == drm_mode->htotal &&
2479 native_mode->vtotal == drm_mode->vtotal) {
2480 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2481 } else {
2482 /* no scaling nor amdgpu inserted, no need to patch */
2483 }
2484}
2485
aed15309
ML		 2486static struct dc_sink *
2487create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2488{
2e0ac3d6 2489 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2490 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2491 sink_init_data.link = aconnector->dc_link;
2492 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2493
2494 sink = dc_sink_create(&sink_init_data);
423788c7 2495 if (!sink) {
2e0ac3d6 2496 DRM_ERROR("Failed to create sink!\n");
aed15309 2497 return NULL;
423788c7 2498 }
2e0ac3d6 2499 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2500
aed15309 2501 return sink;
2e0ac3d6
HW		 2502}
2503
fa2123db
ML		 2504static void set_multisync_trigger_params(
2505 struct dc_stream_state *stream)
2506{
2507 if (stream->triggered_crtc_reset.enabled) {
2508 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2509 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2510 }
2511}
2512
2513static void set_master_stream(struct dc_stream_state *stream_set[],
2514 int stream_count)
2515{
2516 int j, highest_rfr = 0, master_stream = 0;
2517
2518 for (j = 0; j < stream_count; j++) {
2519 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2520 int refresh_rate = 0;
2521
2522 refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2523 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2524 if (refresh_rate > highest_rfr) {
2525 highest_rfr = refresh_rate;
2526 master_stream = j;
2527 }
2528 }
2529 }
2530 for (j = 0; j < stream_count; j++) {
03736f4c 2531 if (stream_set[j])
fa2123db
ML		 2532 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2533 }
2534}
2535
2536static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2537{
2538 int i = 0;
2539
2540 if (context->stream_count < 2)
2541 return;
2542 for (i = 0; i < context->stream_count ; i++) {
2543 if (!context->streams[i])
2544 continue;
1f6010a9
DF		 2545 /*
2546 * TODO: add a function to read AMD VSDB bits and set
fa2123db 2547 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 2548 * For now it's set to false
fa2123db
ML		 2549 */
2550 set_multisync_trigger_params(context->streams[i]);
2551 }
2552 set_master_stream(context->streams, context->stream_count);
2553}
2554
3ee6b26b
AD		 2555static struct dc_stream_state *
2556create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2557 const struct drm_display_mode *drm_mode,
2558 const struct dm_connector_state *dm_state)
e7b07cee
HW		 2559{
2560 struct drm_display_mode *preferred_mode = NULL;
391ef035 2561 struct drm_connector *drm_connector;
0971c40e 2562 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2563 struct drm_display_mode mode = *drm_mode;
2564 bool native_mode_found = false;
aed15309 2565 struct dc_sink *sink = NULL;
b830ebc9 2566 if (aconnector == NULL) {
e7b07cee 2567 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2568 return stream;
e7b07cee
HW		 2569 }
2570
e7b07cee 2571 drm_connector = &aconnector->base;
2e0ac3d6 2572
f4ac176e
JZ		 2573 if (!aconnector->dc_sink) {
2574 /*
391ef035
JFZ		 2575 * Create dc_sink when necessary to MST
2576 * Don't apply fake_sink to MST
f4ac176e 2577 */
391ef035
JFZ		 2578 if (aconnector->mst_port) {
2579 dm_dp_mst_dc_sink_create(drm_connector);
64245fa7 2580 return stream;
391ef035 2581 }
f4ac176e 2582
aed15309
ML		 2583 sink = create_fake_sink(aconnector);
2584 if (!sink)
64245fa7 2585 return stream;
aed15309
ML		 2586 } else {
2587 sink = aconnector->dc_sink;
f4ac176e 2588 }
2e0ac3d6 2589
aed15309 2590 stream = dc_create_stream_for_sink(sink);
4562236b 2591
b830ebc9 2592 if (stream == NULL) {
e7b07cee 2593 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2594 goto finish;
e7b07cee
HW		 2595 }
2596
2597 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2598 /* Search for preferred mode */
2599 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2600 native_mode_found = true;
2601 break;
2602 }
2603 }
2604 if (!native_mode_found)
2605 preferred_mode = list_first_entry_or_null(
2606 &aconnector->base.modes,
2607 struct drm_display_mode,
2608 head);
2609
b830ebc9 2610 if (preferred_mode == NULL) {
1f6010a9
DF		 2611 /*
2612 * This may not be an error, the use case is when we have no
e7b07cee
HW		 2613 * usermode calls to reset and set mode upon hotplug. In this
2614 * case, we call set mode ourselves to restore the previous mode
2615 * and the modelist may not be filled in in time.
2616 */
f1ad2f5e 2617 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 2618 } else {
2619 decide_crtc_timing_for_drm_display_mode(
2620 &mode, preferred_mode,
f4791779 2621 dm_state ? (dm_state->scaling != RMX_OFF) : false);
e7b07cee
HW		 2622 }
2623
f783577c
JFZ		 2624 if (!dm_state)
2625 drm_mode_set_crtcinfo(&mode, 0);
2626
e7b07cee
HW		 2627 fill_stream_properties_from_drm_display_mode(stream,
2628 &mode, &aconnector->base);
2629 update_stream_scaling_settings(&mode, dm_state, stream);
2630
2631 fill_audio_info(
2632 &stream->audio_info,
2633 drm_connector,
aed15309 2634 sink);
e7b07cee 2635
9182b4cb
HW		 2636 update_stream_signal(stream);
2637
9e3efe3e
HW		 2638 if (dm_state && dm_state->freesync_capable)
2639 stream->ignore_msa_timing_param = true;
aed15309
ML		 2640finish:
2641 if (sink && sink->sink_signal == SIGNAL_TYPE_VIRTUAL)
2642 dc_sink_release(sink);
9e3efe3e 2643
e7b07cee
HW		 2644 return stream;
2645}
2646
7578ecda 2647static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 2648{
2649 drm_crtc_cleanup(crtc);
2650 kfree(crtc);
2651}
2652
2653static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 2654 struct drm_crtc_state *state)
e7b07cee
HW		 2655{
2656 struct dm_crtc_state *cur = to_dm_crtc_state(state);
2657
2658 /* TODO Destroy dc_stream objects are stream object is flattened */
2659 if (cur->stream)
2660 dc_stream_release(cur->stream);
2661
2662
2663 __drm_atomic_helper_crtc_destroy_state(state);
2664
2665
2666 kfree(state);
2667}
2668
2669static void dm_crtc_reset_state(struct drm_crtc *crtc)
2670{
2671 struct dm_crtc_state *state;
2672
2673 if (crtc->state)
2674 dm_crtc_destroy_state(crtc, crtc->state);
2675
2676 state = kzalloc(sizeof(*state), GFP_KERNEL);
2677 if (WARN_ON(!state))
2678 return;
2679
2680 crtc->state = &state->base;
2681 crtc->state->crtc = crtc;
2682
2683}
2684
2685static struct drm_crtc_state *
2686dm_crtc_duplicate_state(struct drm_crtc *crtc)
2687{
2688 struct dm_crtc_state *state, *cur;
2689
2690 cur = to_dm_crtc_state(crtc->state);
2691
2692 if (WARN_ON(!crtc->state))
2693 return NULL;
2694
2004f45e 2695 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 2696 if (!state)
2697 return NULL;
e7b07cee
HW		 2698
2699 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2700
2701 if (cur->stream) {
2702 state->stream = cur->stream;
2703 dc_stream_retain(state->stream);
2704 }
2705
98e6436d
AK		 2706 state->adjust = cur->adjust;
2707 state->vrr_infopacket = cur->vrr_infopacket;
2708 state->freesync_enabled = cur->freesync_enabled;
2709
e7b07cee
HW		 2710 /* TODO Duplicate dc_stream after objects are stream object is flattened */
2711
2712 return &state->base;
2713}
2714
589d2739
HW		 2715
2716static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
2717{
2718 enum dc_irq_source irq_source;
2719 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2720 struct amdgpu_device *adev = crtc->dev->dev_private;
2721
2722 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 2723 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 2724}
2725
2726static int dm_enable_vblank(struct drm_crtc *crtc)
2727{
2728 return dm_set_vblank(crtc, true);
2729}
2730
2731static void dm_disable_vblank(struct drm_crtc *crtc)
2732{
2733 dm_set_vblank(crtc, false);
2734}
2735
e7b07cee
HW		 2736/* Implemented only the options currently availible for the driver */
2737static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2738 .reset = dm_crtc_reset_state,
2739 .destroy = amdgpu_dm_crtc_destroy,
2740 .gamma_set = drm_atomic_helper_legacy_gamma_set,
2741 .set_config = drm_atomic_helper_set_config,
2742 .page_flip = drm_atomic_helper_page_flip,
2743 .atomic_duplicate_state = dm_crtc_duplicate_state,
2744 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 2745 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 2746 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 2747 .enable_vblank = dm_enable_vblank,
2748 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 2749};
2750
2751static enum drm_connector_status
2752amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2753{
2754 bool connected;
c84dec2f 2755 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 2756
1f6010a9
DF		 2757 /*
2758 * Notes:
e7b07cee
HW		 2759 * 1. This interface is NOT called in context of HPD irq.
2760 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 2761 * makes it a bad place for *any* MST-related activity.
2762 */
e7b07cee 2763
8580d60b
HW		 2764 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2765 !aconnector->fake_enable)
e7b07cee
HW		 2766 connected = (aconnector->dc_sink != NULL);
2767 else
2768 connected = (aconnector->base.force == DRM_FORCE_ON);
2769
2770 return (connected ? connector_status_connected :
2771 connector_status_disconnected);
2772}
2773
3ee6b26b
AD		 2774int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2775 struct drm_connector_state *connector_state,
2776 struct drm_property *property,
2777 uint64_t val)
e7b07cee
HW		 2778{
2779 struct drm_device *dev = connector->dev;
2780 struct amdgpu_device *adev = dev->dev_private;
2781 struct dm_connector_state *dm_old_state =
2782 to_dm_connector_state(connector->state);
2783 struct dm_connector_state *dm_new_state =
2784 to_dm_connector_state(connector_state);
2785
2786 int ret = -EINVAL;
2787
2788 if (property == dev->mode_config.scaling_mode_property) {
2789 enum amdgpu_rmx_type rmx_type;
2790
2791 switch (val) {
2792 case DRM_MODE_SCALE_CENTER:
2793 rmx_type = RMX_CENTER;
2794 break;
2795 case DRM_MODE_SCALE_ASPECT:
2796 rmx_type = RMX_ASPECT;
2797 break;
2798 case DRM_MODE_SCALE_FULLSCREEN:
2799 rmx_type = RMX_FULL;
2800 break;
2801 case DRM_MODE_SCALE_NONE:
2802 default:
2803 rmx_type = RMX_OFF;
2804 break;
2805 }
2806
2807 if (dm_old_state->scaling == rmx_type)
2808 return 0;
2809
2810 dm_new_state->scaling = rmx_type;
2811 ret = 0;
2812 } else if (property == adev->mode_info.underscan_hborder_property) {
2813 dm_new_state->underscan_hborder = val;
2814 ret = 0;
2815 } else if (property == adev->mode_info.underscan_vborder_property) {
2816 dm_new_state->underscan_vborder = val;
2817 ret = 0;
2818 } else if (property == adev->mode_info.underscan_property) {
2819 dm_new_state->underscan_enable = val;
2820 ret = 0;
2821 }
2822
2823 return ret;
2824}
2825
3ee6b26b
AD		 2826int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2827 const struct drm_connector_state *state,
2828 struct drm_property *property,
2829 uint64_t *val)
e7b07cee
HW		 2830{
2831 struct drm_device *dev = connector->dev;
2832 struct amdgpu_device *adev = dev->dev_private;
2833 struct dm_connector_state *dm_state =
2834 to_dm_connector_state(state);
2835 int ret = -EINVAL;
2836
2837 if (property == dev->mode_config.scaling_mode_property) {
2838 switch (dm_state->scaling) {
2839 case RMX_CENTER:
2840 *val = DRM_MODE_SCALE_CENTER;
2841 break;
2842 case RMX_ASPECT:
2843 *val = DRM_MODE_SCALE_ASPECT;
2844 break;
2845 case RMX_FULL:
2846 *val = DRM_MODE_SCALE_FULLSCREEN;
2847 break;
2848 case RMX_OFF:
2849 default:
2850 *val = DRM_MODE_SCALE_NONE;
2851 break;
2852 }
2853 ret = 0;
2854 } else if (property == adev->mode_info.underscan_hborder_property) {
2855 *val = dm_state->underscan_hborder;
2856 ret = 0;
2857 } else if (property == adev->mode_info.underscan_vborder_property) {
2858 *val = dm_state->underscan_vborder;
2859 ret = 0;
2860 } else if (property == adev->mode_info.underscan_property) {
2861 *val = dm_state->underscan_enable;
2862 ret = 0;
2863 }
2864 return ret;
2865}
2866
7578ecda 2867static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 2868{
c84dec2f 2869 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 2870 const struct dc_link *link = aconnector->dc_link;
2871 struct amdgpu_device *adev = connector->dev->dev_private;
2872 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 2873
e7b07cee
HW		 2874#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2875 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2876
89fc8d4e 2877 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 2878 link->type != dc_connection_none &&
2879 dm->backlight_dev) {
2880 backlight_device_unregister(dm->backlight_dev);
2881 dm->backlight_dev = NULL;
e7b07cee
HW		 2882 }
2883#endif
e86e8947 2884 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 2885 drm_connector_unregister(connector);
2886 drm_connector_cleanup(connector);
2887 kfree(connector);
2888}
2889
2890void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2891{
2892 struct dm_connector_state *state =
2893 to_dm_connector_state(connector->state);
2894
df099b9b
LSL		 2895 if (connector->state)
2896 __drm_atomic_helper_connector_destroy_state(connector->state);
2897
e7b07cee
HW		 2898 kfree(state);
2899
2900 state = kzalloc(sizeof(*state), GFP_KERNEL);
2901
2902 if (state) {
2903 state->scaling = RMX_OFF;
2904 state->underscan_enable = false;
2905 state->underscan_hborder = 0;
2906 state->underscan_vborder = 0;
2907
df099b9b 2908 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 2909 }
2910}
2911
3ee6b26b
AD		 2912struct drm_connector_state *
2913amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 2914{
2915 struct dm_connector_state *state =
2916 to_dm_connector_state(connector->state);
2917
2918 struct dm_connector_state *new_state =
2919 kmemdup(state, sizeof(*state), GFP_KERNEL);
2920
98e6436d
AK		 2921 if (!new_state)
2922 return NULL;
e7b07cee 2923
98e6436d
AK		 2924 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
2925
2926 new_state->freesync_capable = state->freesync_capable;
2927 new_state->freesync_enable = state->freesync_enable;
2928
2929 return &new_state->base;
e7b07cee
HW		 2930}
2931
2932static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2933 .reset = amdgpu_dm_connector_funcs_reset,
2934 .detect = amdgpu_dm_connector_detect,
2935 .fill_modes = drm_helper_probe_single_connector_modes,
2936 .destroy = amdgpu_dm_connector_destroy,
2937 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2938 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2939 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2940 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2941};
2942
e7b07cee
HW		 2943static int get_modes(struct drm_connector *connector)
2944{
2945 return amdgpu_dm_connector_get_modes(connector);
2946}
2947
c84dec2f 2948static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2949{
2950 struct dc_sink_init_data init_params = {
2951 .link = aconnector->dc_link,
2952 .sink_signal = SIGNAL_TYPE_VIRTUAL
2953 };
70e8ffc5 2954 struct edid *edid;
e7b07cee 2955
a89ff457 2956 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 2957 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2958 aconnector->base.name);
2959
2960 aconnector->base.force = DRM_FORCE_OFF;
2961 aconnector->base.override_edid = false;
2962 return;
2963 }
2964
70e8ffc5
HW		 2965 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2966
e7b07cee
HW		 2967 aconnector->edid = edid;
2968
2969 aconnector->dc_em_sink = dc_link_add_remote_sink(
2970 aconnector->dc_link,
2971 (uint8_t *)edid,
2972 (edid->extensions + 1) * EDID_LENGTH,
2973 &init_params);
2974
a68d90e7 2975 if (aconnector->base.force == DRM_FORCE_ON)
e7b07cee
HW		 2976 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2977 aconnector->dc_link->local_sink :
2978 aconnector->dc_em_sink;
2979}
2980
c84dec2f 2981static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 2982{
2983 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2984
1f6010a9
DF		 2985 /*
2986 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 2987 * Those settings have to be != 0 to get initial modeset
2988 */
2989 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2990 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2991 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2992 }
2993
2994
2995 aconnector->base.override_edid = true;
2996 create_eml_sink(aconnector);
2997}
2998
ba9ca088 2999enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3000 struct drm_display_mode *mode)
e7b07cee
HW		 3001{
3002 int result = MODE_ERROR;
3003 struct dc_sink *dc_sink;
3004 struct amdgpu_device *adev = connector->dev->dev_private;
3005 /* TODO: Unhardcode stream count */
0971c40e 3006 struct dc_stream_state *stream;
c84dec2f 3007 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3008 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3009
3010 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3011 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3012 return result;
3013
1f6010a9
DF		 3014 /*
3015 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3016 * EDID mgmt
3017 */
3018 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3019 !aconnector->dc_em_sink)
3020 handle_edid_mgmt(aconnector);
3021
c84dec2f 3022 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3023
b830ebc9 3024 if (dc_sink == NULL) {
e7b07cee
HW		 3025 DRM_ERROR("dc_sink is NULL!\n");
3026 goto fail;
3027 }
3028
f4791779 3029 stream = create_stream_for_sink(aconnector, mode, NULL);
b830ebc9 3030 if (stream == NULL) {
e7b07cee
HW		 3031 DRM_ERROR("Failed to create stream for sink!\n");
3032 goto fail;
3033 }
3034
a39438f0
HW		 3035 dc_result = dc_validate_stream(adev->dm.dc, stream);
3036
3037 if (dc_result == DC_OK)
e7b07cee 3038 result = MODE_OK;
a39438f0 3039 else
9f921b14 3040 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3041 mode->vdisplay,
3042 mode->hdisplay,
9f921b14
HW		 3043 mode->clock,
3044 dc_result);
e7b07cee
HW		 3045
3046 dc_stream_release(stream);
3047
3048fail:
3049 /* TODO: error handling*/
3050 return result;
3051}
3052
3053static const struct drm_connector_helper_funcs
3054amdgpu_dm_connector_helper_funcs = {
3055 /*
1f6010a9 3056 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 3057 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 3058 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 3059 * in get_modes call back, not just return the modes count
3060 */
e7b07cee
HW		 3061 .get_modes = get_modes,
3062 .mode_valid = amdgpu_dm_connector_mode_valid,
a487411a 3063 .best_encoder = drm_atomic_helper_best_encoder
e7b07cee
HW		 3064};
3065
3066static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3067{
3068}
3069
3ee6b26b
AD		 3070static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3071 struct drm_crtc_state *state)
e7b07cee
HW		 3072{
3073 struct amdgpu_device *adev = crtc->dev->dev_private;
3074 struct dc *dc = adev->dm.dc;
3075 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3076 int ret = -EINVAL;
3077
9b690ef3
BL		 3078 if (unlikely(!dm_crtc_state->stream &&
3079 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 3080 WARN_ON(1);
3081 return ret;
3082 }
3083
1f6010a9 3084 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 3085 if (!dm_crtc_state->stream)
3086 return 0;
3087
62c933f9 3088 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3089 return 0;
3090
3091 return ret;
3092}
3093
3ee6b26b
AD		 3094static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3095 const struct drm_display_mode *mode,
3096 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3097{
3098 return true;
3099}
3100
3101static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3102 .disable = dm_crtc_helper_disable,
3103 .atomic_check = dm_crtc_helper_atomic_check,
3104 .mode_fixup = dm_crtc_helper_mode_fixup
3105};
3106
3107static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3108{
3109
3110}
3111
3ee6b26b
AD		 3112static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3113 struct drm_crtc_state *crtc_state,
3114 struct drm_connector_state *conn_state)
e7b07cee
HW		 3115{
3116 return 0;
3117}
3118
3119const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3120 .disable = dm_encoder_helper_disable,
3121 .atomic_check = dm_encoder_helper_atomic_check
3122};
3123
3124static void dm_drm_plane_reset(struct drm_plane *plane)
3125{
3126 struct dm_plane_state *amdgpu_state = NULL;
3127
3128 if (plane->state)
3129 plane->funcs->atomic_destroy_state(plane, plane->state);
3130
3131 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 3132 WARN_ON(amdgpu_state == NULL);
1f6010a9 3133
e7b07cee
HW		 3134 if (amdgpu_state) {
3135 plane->state = &amdgpu_state->base;
3136 plane->state->plane = plane;
3137 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3138 }
e7b07cee
HW		 3139}
3140
3141static struct drm_plane_state *
3142dm_drm_plane_duplicate_state(struct drm_plane *plane)
3143{
3144 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3145
3146 old_dm_plane_state = to_dm_plane_state(plane->state);
3147 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3148 if (!dm_plane_state)
3149 return NULL;
3150
3151 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3152
3be5262e
HW		 3153 if (old_dm_plane_state->dc_state) {
3154 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3155 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3156 }
3157
3158 return &dm_plane_state->base;
3159}
3160
3161void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3162 struct drm_plane_state *state)
e7b07cee
HW		 3163{
3164 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3165
3be5262e
HW		 3166 if (dm_plane_state->dc_state)
3167 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3168
0627bbd3 3169 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3170}
3171
3172static const struct drm_plane_funcs dm_plane_funcs = {
3173 .update_plane = drm_atomic_helper_update_plane,
3174 .disable_plane = drm_atomic_helper_disable_plane,
3175 .destroy = drm_plane_cleanup,
3176 .reset = dm_drm_plane_reset,
3177 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3178 .atomic_destroy_state = dm_drm_plane_destroy_state,
3179};
3180
3ee6b26b
AD		 3181static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3182 struct drm_plane_state *new_state)
e7b07cee
HW		 3183{
3184 struct amdgpu_framebuffer *afb;
3185 struct drm_gem_object *obj;
5d43be0c 3186 struct amdgpu_device *adev;
e7b07cee 3187 struct amdgpu_bo *rbo;
56087b31 3188 uint64_t chroma_addr = 0;
e7b07cee
HW		 3189 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3190 unsigned int awidth;
5d43be0c
CK		 3191 uint32_t domain;
3192 int r;
e7b07cee
HW		 3193
3194 dm_plane_state_old = to_dm_plane_state(plane->state);
3195 dm_plane_state_new = to_dm_plane_state(new_state);
3196
3197 if (!new_state->fb) {
f1ad2f5e 3198 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3199 return 0;
3200 }
3201
3202 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3203 obj = new_state->fb->obj[0];
e7b07cee 3204 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3205 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3206 r = amdgpu_bo_reserve(rbo, false);
3207 if (unlikely(r != 0))
3208 return r;
3209
5d43be0c 3210 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3211 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3212 else
3213 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3214
7b7c6c81 3215 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3216 if (unlikely(r != 0)) {
30b7c614
HW		 3217 if (r != -ERESTARTSYS)
3218 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3219 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3220 return r;
3221 }
3222
bb812f1e
JZ		 3223 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3224 if (unlikely(r != 0)) {
3225 amdgpu_bo_unpin(rbo);
3226 amdgpu_bo_unreserve(rbo);
3227 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3228 return r;
3229 }
bb812f1e
JZ		 3230 amdgpu_bo_unreserve(rbo);
3231
7b7c6c81 3232 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3233
3234 amdgpu_bo_ref(rbo);
3235
3be5262e
HW		 3236 if (dm_plane_state_new->dc_state &&
3237 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3238 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3239
3be5262e
HW		 3240 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3241 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3242 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
e7b07cee
HW		 3243 } else {
3244 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3245 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3246 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3247 = lower_32_bits(afb->address);
56087b31
S		 3248 plane_state->address.video_progressive.luma_addr.high_part
3249 = upper_32_bits(afb->address);
35888630 3250 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3251 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3252 = lower_32_bits(chroma_addr);
3253 plane_state->address.video_progressive.chroma_addr.high_part
3254 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3255 }
3256 }
3257
e7b07cee
HW		 3258 return 0;
3259}
3260
3ee6b26b
AD		 3261static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3262 struct drm_plane_state *old_state)
e7b07cee
HW		 3263{
3264 struct amdgpu_bo *rbo;
e7b07cee
HW		 3265 int r;
3266
3267 if (!old_state->fb)
3268 return;
3269
e68d14dd 3270 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3271 r = amdgpu_bo_reserve(rbo, false);
3272 if (unlikely(r)) {
3273 DRM_ERROR("failed to reserve rbo before unpin\n");
3274 return;
b830ebc9
HW		 3275 }
3276
3277 amdgpu_bo_unpin(rbo);
3278 amdgpu_bo_unreserve(rbo);
3279 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3280}
3281
7578ecda
AD		 3282static int dm_plane_atomic_check(struct drm_plane *plane,
3283 struct drm_plane_state *state)
cbd19488
AG		 3284{
3285 struct amdgpu_device *adev = plane->dev->dev_private;
3286 struct dc *dc = adev->dm.dc;
3287 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3288
3be5262e 3289 if (!dm_plane_state->dc_state)
9a3329b1 3290 return 0;
cbd19488 3291
a05bcff1
S		 3292 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3293 return -EINVAL;
3294
62c933f9 3295 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3296 return 0;
3297
3298 return -EINVAL;
3299}
3300
e7b07cee
HW		 3301static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3302 .prepare_fb = dm_plane_helper_prepare_fb,
3303 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3304 .atomic_check = dm_plane_atomic_check,
e7b07cee
HW		 3305};
3306
3307/*
3308 * TODO: these are currently initialized to rgb formats only.
3309 * For future use cases we should either initialize them dynamically based on
3310 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 3311 * check will succeed, and let DC implement proper check
e7b07cee 3312 */
d90371b0 3313static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3314 DRM_FORMAT_RGB888,
3315 DRM_FORMAT_XRGB8888,
3316 DRM_FORMAT_ARGB8888,
3317 DRM_FORMAT_RGBA8888,
3318 DRM_FORMAT_XRGB2101010,
3319 DRM_FORMAT_XBGR2101010,
3320 DRM_FORMAT_ARGB2101010,
3321 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3322 DRM_FORMAT_XBGR8888,
3323 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3324};
3325
99d1abf8 3326static const uint32_t yuv_formats[] = {
e7b07cee
HW		 3327 DRM_FORMAT_NV12,
3328 DRM_FORMAT_NV21,
3329};
3330
3331static const u32 cursor_formats[] = {
3332 DRM_FORMAT_ARGB8888
3333};
3334
7578ecda
AD		 3335static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3336 struct amdgpu_plane *aplane,
3337 unsigned long possible_crtcs)
e7b07cee
HW		 3338{
3339 int res = -EPERM;
3340
3341 switch (aplane->base.type) {
3342 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3343 res = drm_universal_plane_init(
3344 dm->adev->ddev,
3345 &aplane->base,
3346 possible_crtcs,
3347 &dm_plane_funcs,
3348 rgb_formats,
3349 ARRAY_SIZE(rgb_formats),
3350 NULL, aplane->base.type, NULL);
3351 break;
3352 case DRM_PLANE_TYPE_OVERLAY:
3353 res = drm_universal_plane_init(
3354 dm->adev->ddev,
3355 &aplane->base,
3356 possible_crtcs,
3357 &dm_plane_funcs,
3358 yuv_formats,
3359 ARRAY_SIZE(yuv_formats),
3360 NULL, aplane->base.type, NULL);
3361 break;
3362 case DRM_PLANE_TYPE_CURSOR:
3363 res = drm_universal_plane_init(
3364 dm->adev->ddev,
3365 &aplane->base,
3366 possible_crtcs,
3367 &dm_plane_funcs,
3368 cursor_formats,
3369 ARRAY_SIZE(cursor_formats),
3370 NULL, aplane->base.type, NULL);
3371 break;
3372 }
3373
3374 drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3375
96719c54
HW		 3376 /* Create (reset) the plane state */
3377 if (aplane->base.funcs->reset)
3378 aplane->base.funcs->reset(&aplane->base);
3379
3380
e7b07cee
HW		 3381 return res;
3382}
3383
7578ecda
AD		 3384static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3385 struct drm_plane *plane,
3386 uint32_t crtc_index)
e7b07cee
HW		 3387{
3388 struct amdgpu_crtc *acrtc = NULL;
3389 struct amdgpu_plane *cursor_plane;
3390
3391 int res = -ENOMEM;
3392
3393 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3394 if (!cursor_plane)
3395 goto fail;
3396
3397 cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3398 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3399
3400 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3401 if (!acrtc)
3402 goto fail;
3403
3404 res = drm_crtc_init_with_planes(
3405 dm->ddev,
3406 &acrtc->base,
3407 plane,
3408 &cursor_plane->base,
3409 &amdgpu_dm_crtc_funcs, NULL);
3410
3411 if (res)
3412 goto fail;
3413
3414 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3415
96719c54
HW		 3416 /* Create (reset) the plane state */
3417 if (acrtc->base.funcs->reset)
3418 acrtc->base.funcs->reset(&acrtc->base);
3419
e7b07cee
HW		 3420 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3421 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3422
3423 acrtc->crtc_id = crtc_index;
3424 acrtc->base.enabled = false;
c37e2d29 3425 acrtc->otg_inst = -1;
e7b07cee
HW		 3426
3427 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3428 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3429 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3430 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3431
3432 return 0;
3433
3434fail:
b830ebc9
HW		 3435 kfree(acrtc);
3436 kfree(cursor_plane);
e7b07cee
HW		 3437 return res;
3438}
3439
3440
3441static int to_drm_connector_type(enum signal_type st)
3442{
3443 switch (st) {
3444 case SIGNAL_TYPE_HDMI_TYPE_A:
3445 return DRM_MODE_CONNECTOR_HDMIA;
3446 case SIGNAL_TYPE_EDP:
3447 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 3448 case SIGNAL_TYPE_LVDS:
3449 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 3450 case SIGNAL_TYPE_RGB:
3451 return DRM_MODE_CONNECTOR_VGA;
3452 case SIGNAL_TYPE_DISPLAY_PORT:
3453 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3454 return DRM_MODE_CONNECTOR_DisplayPort;
3455 case SIGNAL_TYPE_DVI_DUAL_LINK:
3456 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3457 return DRM_MODE_CONNECTOR_DVID;
3458 case SIGNAL_TYPE_VIRTUAL:
3459 return DRM_MODE_CONNECTOR_VIRTUAL;
3460
3461 default:
3462 return DRM_MODE_CONNECTOR_Unknown;
3463 }
3464}
3465
3466static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3467{
3468 const struct drm_connector_helper_funcs *helper =
3469 connector->helper_private;
3470 struct drm_encoder *encoder;
3471 struct amdgpu_encoder *amdgpu_encoder;
3472
3473 encoder = helper->best_encoder(connector);
3474
3475 if (encoder == NULL)
3476 return;
3477
3478 amdgpu_encoder = to_amdgpu_encoder(encoder);
3479
3480 amdgpu_encoder->native_mode.clock = 0;
3481
3482 if (!list_empty(&connector->probed_modes)) {
3483 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3484
e7b07cee 3485 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3486 &connector->probed_modes,
3487 head) {
3488 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3489 amdgpu_encoder->native_mode = *preferred_mode;
3490
e7b07cee
HW		 3491 break;
3492 }
3493
3494 }
3495}
3496
3ee6b26b
AD		 3497static struct drm_display_mode *
3498amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3499 char *name,
3500 int hdisplay, int vdisplay)
e7b07cee
HW		 3501{
3502 struct drm_device *dev = encoder->dev;
3503 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3504 struct drm_display_mode *mode = NULL;
3505 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3506
3507 mode = drm_mode_duplicate(dev, native_mode);
3508
b830ebc9 3509 if (mode == NULL)
e7b07cee
HW		 3510 return NULL;
3511
3512 mode->hdisplay = hdisplay;
3513 mode->vdisplay = vdisplay;
3514 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3515 strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3516
3517 return mode;
3518
3519}
3520
3521static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 3522 struct drm_connector *connector)
e7b07cee
HW		 3523{
3524 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3525 struct drm_display_mode *mode = NULL;
3526 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 3527 struct amdgpu_dm_connector *amdgpu_dm_connector =
3528 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3529 int i;
3530 int n;
3531 struct mode_size {
3532 char name[DRM_DISPLAY_MODE_LEN];
3533 int w;
3534 int h;
b830ebc9 3535 } common_modes[] = {
e7b07cee
HW		 3536 { "640x480", 640, 480},
3537 { "800x600", 800, 600},
3538 { "1024x768", 1024, 768},
3539 { "1280x720", 1280, 720},
3540 { "1280x800", 1280, 800},
3541 {"1280x1024", 1280, 1024},
3542 { "1440x900", 1440, 900},
3543 {"1680x1050", 1680, 1050},
3544 {"1600x1200", 1600, 1200},
3545 {"1920x1080", 1920, 1080},
3546 {"1920x1200", 1920, 1200}
3547 };
3548
b830ebc9 3549 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 3550
3551 for (i = 0; i < n; i++) {
3552 struct drm_display_mode *curmode = NULL;
3553 bool mode_existed = false;
3554
3555 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 3556 common_modes[i].h > native_mode->vdisplay ||
3557 (common_modes[i].w == native_mode->hdisplay &&
3558 common_modes[i].h == native_mode->vdisplay))
3559 continue;
e7b07cee
HW		 3560
3561 list_for_each_entry(curmode, &connector->probed_modes, head) {
3562 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 3563 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 3564 mode_existed = true;
3565 break;
3566 }
3567 }
3568
3569 if (mode_existed)
3570 continue;
3571
3572 mode = amdgpu_dm_create_common_mode(encoder,
3573 common_modes[i].name, common_modes[i].w,
3574 common_modes[i].h);
3575 drm_mode_probed_add(connector, mode);
c84dec2f 3576 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 3577 }
3578}
3579
3ee6b26b
AD		 3580static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3581 struct edid *edid)
e7b07cee 3582{
c84dec2f
HW		 3583 struct amdgpu_dm_connector *amdgpu_dm_connector =
3584 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3585
3586 if (edid) {
3587 /* empty probed_modes */
3588 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 3589 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 3590 drm_add_edid_modes(connector, edid);
3591
e7b07cee 3592 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 3593 } else {
c84dec2f 3594 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 3595 }
e7b07cee
HW		 3596}
3597
7578ecda 3598static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee
HW		 3599{
3600 const struct drm_connector_helper_funcs *helper =
3601 connector->helper_private;
c84dec2f
HW		 3602 struct amdgpu_dm_connector *amdgpu_dm_connector =
3603 to_amdgpu_dm_connector(connector);
e7b07cee 3604 struct drm_encoder *encoder;
c84dec2f 3605 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee
HW		 3606
3607 encoder = helper->best_encoder(connector);
3e332d3a 3608
85ee15d6 3609 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 3610 amdgpu_dm_connector->num_modes =
3611 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 3612 } else {
3613 amdgpu_dm_connector_ddc_get_modes(connector, edid);
3614 amdgpu_dm_connector_add_common_modes(encoder, connector);
3615 }
3e332d3a 3616 amdgpu_dm_fbc_init(connector);
5099114b 3617
c84dec2f 3618 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 3619}
3620
3ee6b26b
AD		 3621void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3622 struct amdgpu_dm_connector *aconnector,
3623 int connector_type,
3624 struct dc_link *link,
3625 int link_index)
e7b07cee
HW		 3626{
3627 struct amdgpu_device *adev = dm->ddev->dev_private;
3628
3629 aconnector->connector_id = link_index;
3630 aconnector->dc_link = link;
3631 aconnector->base.interlace_allowed = false;
3632 aconnector->base.doublescan_allowed = false;
3633 aconnector->base.stereo_allowed = false;
3634 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3635 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 3636 mutex_init(&aconnector->hpd_lock);
3637
1f6010a9
DF		 3638 /*
3639 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 3640 * which means HPD hot plug not supported
3641 */
e7b07cee
HW		 3642 switch (connector_type) {
3643 case DRM_MODE_CONNECTOR_HDMIA:
3644 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c
JFZ		 3645 aconnector->base.ycbcr_420_allowed =
3646 link->link_enc->features.ycbcr420_supported ? true : false;
e7b07cee
HW		 3647 break;
3648 case DRM_MODE_CONNECTOR_DisplayPort:
3649 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c
JFZ		 3650 aconnector->base.ycbcr_420_allowed =
3651 link->link_enc->features.ycbcr420_supported ? true : false;
e7b07cee
HW		 3652 break;
3653 case DRM_MODE_CONNECTOR_DVID:
3654 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3655 break;
3656 default:
3657 break;
3658 }
3659
3660 drm_object_attach_property(&aconnector->base.base,
3661 dm->ddev->mode_config.scaling_mode_property,
3662 DRM_MODE_SCALE_NONE);
3663
3664 drm_object_attach_property(&aconnector->base.base,
3665 adev->mode_info.underscan_property,
3666 UNDERSCAN_OFF);
3667 drm_object_attach_property(&aconnector->base.base,
3668 adev->mode_info.underscan_hborder_property,
3669 0);
3670 drm_object_attach_property(&aconnector->base.base,
3671 adev->mode_info.underscan_vborder_property,
3672 0);
3673
3674}
3675
7578ecda
AD		 3676static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3677 struct i2c_msg *msgs, int num)
e7b07cee
HW		 3678{
3679 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3680 struct ddc_service *ddc_service = i2c->ddc_service;
3681 struct i2c_command cmd;
3682 int i;
3683 int result = -EIO;
3684
b830ebc9 3685 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 3686
3687 if (!cmd.payloads)
3688 return result;
3689
3690 cmd.number_of_payloads = num;
3691 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3692 cmd.speed = 100;
3693
3694 for (i = 0; i < num; i++) {
3695 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3696 cmd.payloads[i].address = msgs[i].addr;
3697 cmd.payloads[i].length = msgs[i].len;
3698 cmd.payloads[i].data = msgs[i].buf;
3699 }
3700
c85e6e54
DF		 3701 if (dc_submit_i2c(
3702 ddc_service->ctx->dc,
3703 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 3704 &cmd))
3705 result = num;
3706
3707 kfree(cmd.payloads);
3708 return result;
3709}
3710
7578ecda 3711static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 3712{
3713 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3714}
3715
3716static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3717 .master_xfer = amdgpu_dm_i2c_xfer,
3718 .functionality = amdgpu_dm_i2c_func,
3719};
3720
3ee6b26b
AD		 3721static struct amdgpu_i2c_adapter *
3722create_i2c(struct ddc_service *ddc_service,
3723 int link_index,
3724 int *res)
e7b07cee
HW		 3725{
3726 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3727 struct amdgpu_i2c_adapter *i2c;
3728
b830ebc9 3729 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 3730 if (!i2c)
3731 return NULL;
e7b07cee
HW		 3732 i2c->base.owner = THIS_MODULE;
3733 i2c->base.class = I2C_CLASS_DDC;
3734 i2c->base.dev.parent = &adev->pdev->dev;
3735 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 3736 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 3737 i2c_set_adapdata(&i2c->base, i2c);
3738 i2c->ddc_service = ddc_service;
c85e6e54 3739 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 3740
3741 return i2c;
3742}
3743
89fc8d4e 3744
1f6010a9
DF		 3745/*
3746 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 3747 * dc_link which will be represented by this aconnector.
3748 */
7578ecda
AD		 3749static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3750 struct amdgpu_dm_connector *aconnector,
3751 uint32_t link_index,
3752 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 3753{
3754 int res = 0;
3755 int connector_type;
3756 struct dc *dc = dm->dc;
3757 struct dc_link *link = dc_get_link_at_index(dc, link_index);
3758 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 3759
3760 link->priv = aconnector;
e7b07cee 3761
f1ad2f5e 3762 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 3763
3764 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 3765 if (!i2c) {
3766 DRM_ERROR("Failed to create i2c adapter data\n");
3767 return -ENOMEM;
3768 }
3769
e7b07cee
HW		 3770 aconnector->i2c = i2c;
3771 res = i2c_add_adapter(&i2c->base);
3772
3773 if (res) {
3774 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3775 goto out_free;
3776 }
3777
3778 connector_type = to_drm_connector_type(link->connector_signal);
3779
3780 res = drm_connector_init(
3781 dm->ddev,
3782 &aconnector->base,
3783 &amdgpu_dm_connector_funcs,
3784 connector_type);
3785
3786 if (res) {
3787 DRM_ERROR("connector_init failed\n");
3788 aconnector->connector_id = -1;
3789 goto out_free;
3790 }
3791
3792 drm_connector_helper_add(
3793 &aconnector->base,
3794 &amdgpu_dm_connector_helper_funcs);
3795
96719c54
HW		 3796 if (aconnector->base.funcs->reset)
3797 aconnector->base.funcs->reset(&aconnector->base);
3798
e7b07cee
HW		 3799 amdgpu_dm_connector_init_helper(
3800 dm,
3801 aconnector,
3802 connector_type,
3803 link,
3804 link_index);
3805
cde4c44d 3806 drm_connector_attach_encoder(
e7b07cee
HW		 3807 &aconnector->base, &aencoder->base);
3808
3809 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 3810#if defined(CONFIG_DEBUG_FS)
3811 res = connector_debugfs_init(aconnector);
3812 if (res) {
3813 DRM_ERROR("Failed to create debugfs for connector");
3814 goto out_free;
3815 }
3816#endif
e7b07cee
HW		 3817
3818 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3819 || connector_type == DRM_MODE_CONNECTOR_eDP)
3820 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3821
e7b07cee
HW		 3822out_free:
3823 if (res) {
3824 kfree(i2c);
3825 aconnector->i2c = NULL;
3826 }
3827 return res;
3828}
3829
3830int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3831{
3832 switch (adev->mode_info.num_crtc) {
3833 case 1:
3834 return 0x1;
3835 case 2:
3836 return 0x3;
3837 case 3:
3838 return 0x7;
3839 case 4:
3840 return 0xf;
3841 case 5:
3842 return 0x1f;
3843 case 6:
3844 default:
3845 return 0x3f;
3846 }
3847}
3848
7578ecda
AD		 3849static int amdgpu_dm_encoder_init(struct drm_device *dev,
3850 struct amdgpu_encoder *aencoder,
3851 uint32_t link_index)
e7b07cee
HW		 3852{
3853 struct amdgpu_device *adev = dev->dev_private;
3854
3855 int res = drm_encoder_init(dev,
3856 &aencoder->base,
3857 &amdgpu_dm_encoder_funcs,
3858 DRM_MODE_ENCODER_TMDS,
3859 NULL);
3860
3861 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3862
3863 if (!res)
3864 aencoder->encoder_id = link_index;
3865 else
3866 aencoder->encoder_id = -1;
3867
3868 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3869
3870 return res;
3871}
3872
3ee6b26b
AD		 3873static void manage_dm_interrupts(struct amdgpu_device *adev,
3874 struct amdgpu_crtc *acrtc,
3875 bool enable)
e7b07cee
HW		 3876{
3877 /*
3878 * this is not correct translation but will work as soon as VBLANK
3879 * constant is the same as PFLIP
3880 */
3881 int irq_type =
734dd01d 3882 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 3883 adev,
3884 acrtc->crtc_id);
3885
3886 if (enable) {
3887 drm_crtc_vblank_on(&acrtc->base);
3888 amdgpu_irq_get(
3889 adev,
3890 &adev->pageflip_irq,
3891 irq_type);
3892 } else {
3893
3894 amdgpu_irq_put(
3895 adev,
3896 &adev->pageflip_irq,
3897 irq_type);
3898 drm_crtc_vblank_off(&acrtc->base);
3899 }
3900}
3901
3ee6b26b
AD		 3902static bool
3903is_scaling_state_different(const struct dm_connector_state *dm_state,
3904 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 3905{
3906 if (dm_state->scaling != old_dm_state->scaling)
3907 return true;
3908 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3909 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3910 return true;
3911 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3912 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3913 return true;
b830ebc9
HW		 3914 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3915 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3916 return true;
e7b07cee
HW		 3917 return false;
3918}
3919
3ee6b26b
AD		 3920static void remove_stream(struct amdgpu_device *adev,
3921 struct amdgpu_crtc *acrtc,
3922 struct dc_stream_state *stream)
e7b07cee
HW		 3923{
3924 /* this is the update mode case */
e7b07cee
HW		 3925
3926 acrtc->otg_inst = -1;
3927 acrtc->enabled = false;
3928}
3929
7578ecda
AD		 3930static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3931 struct dc_cursor_position *position)
2a8f6ccb 3932{
f4c2cc43 3933 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 3934 int x, y;
3935 int xorigin = 0, yorigin = 0;
3936
3937 if (!crtc || !plane->state->fb) {
3938 position->enable = false;
3939 position->x = 0;
3940 position->y = 0;
3941 return 0;
3942 }
3943
3944 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3945 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3946 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3947 __func__,
3948 plane->state->crtc_w,
3949 plane->state->crtc_h);
3950 return -EINVAL;
3951 }
3952
3953 x = plane->state->crtc_x;
3954 y = plane->state->crtc_y;
3955 /* avivo cursor are offset into the total surface */
3956 x += crtc->primary->state->src_x >> 16;
3957 y += crtc->primary->state->src_y >> 16;
3958 if (x < 0) {
3959 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3960 x = 0;
3961 }
3962 if (y < 0) {
3963 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3964 y = 0;
3965 }
3966 position->enable = true;
3967 position->x = x;
3968 position->y = y;
3969 position->x_hotspot = xorigin;
3970 position->y_hotspot = yorigin;
3971
3972 return 0;
3973}
3974
3ee6b26b
AD		 3975static void handle_cursor_update(struct drm_plane *plane,
3976 struct drm_plane_state *old_plane_state)
e7b07cee 3977{
2a8f6ccb
HW		 3978 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3979 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3980 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3981 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3982 uint64_t address = afb ? afb->address : 0;
3983 struct dc_cursor_position position;
3984 struct dc_cursor_attributes attributes;
3985 int ret;
3986
e7b07cee
HW		 3987 if (!plane->state->fb && !old_plane_state->fb)
3988 return;
3989
f1ad2f5e 3990 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 3991 __func__,
3992 amdgpu_crtc->crtc_id,
3993 plane->state->crtc_w,
3994 plane->state->crtc_h);
2a8f6ccb
HW		 3995
3996 ret = get_cursor_position(plane, crtc, &position);
3997 if (ret)
3998 return;
3999
4000 if (!position.enable) {
4001 /* turn off cursor */
4002 if (crtc_state && crtc_state->stream)
4003 dc_stream_set_cursor_position(crtc_state->stream,
4004 &position);
4005 return;
e7b07cee 4006 }
e7b07cee 4007
2a8f6ccb
HW		 4008 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4009 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4010
4011 attributes.address.high_part = upper_32_bits(address);
4012 attributes.address.low_part = lower_32_bits(address);
4013 attributes.width = plane->state->crtc_w;
4014 attributes.height = plane->state->crtc_h;
4015 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4016 attributes.rotation_angle = 0;
4017 attributes.attribute_flags.value = 0;
4018
4019 attributes.pitch = attributes.width;
4020
886daac9
JZ		 4021 if (crtc_state->stream) {
4022 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4023 &attributes))
4024 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 4025
2a8f6ccb
HW		 4026 if (!dc_stream_set_cursor_position(crtc_state->stream,
4027 &position))
4028 DRM_ERROR("DC failed to set cursor position\n");
886daac9 4029 }
2a8f6ccb 4030}
e7b07cee
HW		 4031
4032static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4033{
4034
4035 assert_spin_locked(&acrtc->base.dev->event_lock);
4036 WARN_ON(acrtc->event);
4037
4038 acrtc->event = acrtc->base.state->event;
4039
4040 /* Set the flip status */
4041 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4042
4043 /* Mark this event as consumed */
4044 acrtc->base.state->event = NULL;
4045
4046 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4047 acrtc->crtc_id);
4048}
4049
4050/*
4051 * Executes flip
4052 *
4053 * Waits on all BO's fences and for proper vblank count
4054 */
3ee6b26b
AD		 4055static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
4056 struct drm_framebuffer *fb,
bc6828e0
BL		 4057 uint32_t target,
4058 struct dc_state *state)
e7b07cee
HW		 4059{
4060 unsigned long flags;
4061 uint32_t target_vblank;
4062 int r, vpos, hpos;
4063 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4064 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
e68d14dd 4065 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
e7b07cee 4066 struct amdgpu_device *adev = crtc->dev->dev_private;
aac6a07e 4067 bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
e7b07cee 4068 struct dc_flip_addrs addr = { {0} };
3be5262e 4069 /* TODO eliminate or rename surface_update */
e7b07cee
HW		 4070 struct dc_surface_update surface_updates[1] = { {0} };
4071 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
d999853e 4072 struct dc_stream_status *stream_status;
e7b07cee
HW		 4073
4074
4075 /* Prepare wait for target vblank early - before the fence-waits */
23effc11 4076 target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
e7b07cee
HW		 4077 amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
4078
1f6010a9
DF		 4079 /*
4080 * TODO This might fail and hence better not used, wait
e7b07cee
HW		 4081 * explicitly on fences instead
4082 * and in general should be called for
4083 * blocking commit to as per framework helpers
b830ebc9 4084 */
e7b07cee
HW		 4085 r = amdgpu_bo_reserve(abo, true);
4086 if (unlikely(r != 0)) {
4087 DRM_ERROR("failed to reserve buffer before flip\n");
4088 WARN_ON(1);
4089 }
4090
4091 /* Wait for all fences on this FB */
4092 WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
4093 MAX_SCHEDULE_TIMEOUT) < 0);
4094
4095 amdgpu_bo_unreserve(abo);
4096
1f6010a9
DF		 4097 /*
4098 * Wait until we're out of the vertical blank period before the one
e7b07cee
HW		 4099 * targeted by the flip
4100 */
4101 while ((acrtc->enabled &&
aa8e286a
SL		 4102 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
4103 0, &vpos, &hpos, NULL,
4104 NULL, &crtc->hwmode)
e7b07cee
HW		 4105 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4106 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4107 (int)(target_vblank -
4108 amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
4109 usleep_range(1000, 1100);
4110 }
4111
4112 /* Flip */
4113 spin_lock_irqsave(&crtc->dev->event_lock, flags);
e7b07cee
HW		 4114
4115 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
4116 WARN_ON(!acrtc_state->stream);
4117
4118 addr.address.grph.addr.low_part = lower_32_bits(afb->address);
4119 addr.address.grph.addr.high_part = upper_32_bits(afb->address);
4120 addr.flip_immediate = async_flip;
4121
4122
4123 if (acrtc->base.state->event)
4124 prepare_flip_isr(acrtc);
4125
4de9f38b
S		 4126 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4127
d999853e
NK		 4128 stream_status = dc_stream_get_status(acrtc_state->stream);
4129 if (!stream_status) {
4130 DRM_ERROR("No stream status for CRTC: id=%d\n",
4131 acrtc->crtc_id);
4132 return;
4133 }
4134
4135 surface_updates->surface = stream_status->plane_states[0];
4136 if (!surface_updates->surface) {
4137 DRM_ERROR("No surface for CRTC: id=%d\n",
4138 acrtc->crtc_id);
4139 return;
4140 }
e7b07cee
HW		 4141 surface_updates->flip_addr = &addr;
4142
bc6828e0
BL		 4143 dc_commit_updates_for_stream(adev->dm.dc,
4144 surface_updates,
4145 1,
4146 acrtc_state->stream,
4147 NULL,
4148 &surface_updates->surface,
4149 state);
e7b07cee
HW		 4150
4151 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
4152 __func__,
4153 addr.address.grph.addr.high_part,
4154 addr.address.grph.addr.low_part);
e7b07cee
HW		 4155}
4156
44d09c6a
HW		 4157/*
4158 * TODO this whole function needs to go
4159 *
4160 * dc_surface_update is needlessly complex. See if we can just replace this
4161 * with a dc_plane_state and follow the atomic model a bit more closely here.
4162 */
4163static bool commit_planes_to_stream(
4164 struct dc *dc,
4165 struct dc_plane_state **plane_states,
4166 uint8_t new_plane_count,
4167 struct dm_crtc_state *dm_new_crtc_state,
4168 struct dm_crtc_state *dm_old_crtc_state,
4169 struct dc_state *state)
4170{
4171 /* no need to dynamically allocate this. it's pretty small */
4172 struct dc_surface_update updates[MAX_SURFACES];
4173 struct dc_flip_addrs *flip_addr;
4174 struct dc_plane_info *plane_info;
4175 struct dc_scaling_info *scaling_info;
4176 int i;
4177 struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
4178 struct dc_stream_update *stream_update =
4179 kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
4180
4181 if (!stream_update) {
4182 BREAK_TO_DEBUGGER();
4183 return false;
4184 }
4185
4186 flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
4187 GFP_KERNEL);
4188 plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
4189 GFP_KERNEL);
4190 scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
4191 GFP_KERNEL);
4192
4193 if (!flip_addr || !plane_info || !scaling_info) {
4194 kfree(flip_addr);
4195 kfree(plane_info);
4196 kfree(scaling_info);
4197 kfree(stream_update);
4198 return false;
4199 }
4200
4201 memset(updates, 0, sizeof(updates));
4202
4203 stream_update->src = dc_stream->src;
4204 stream_update->dst = dc_stream->dst;
4205 stream_update->out_transfer_func = dc_stream->out_transfer_func;
4206
98e6436d
AK		 4207 if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
4208 stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
4209 stream_update->adjust = &dc_stream->adjust;
4210 }
4211
44d09c6a
HW		 4212 for (i = 0; i < new_plane_count; i++) {
4213 updates[i].surface = plane_states[i];
4214 updates[i].gamma =
4215 (struct dc_gamma *)plane_states[i]->gamma_correction;
4216 updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
4217 flip_addr[i].address = plane_states[i]->address;
4218 flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
4219 plane_info[i].color_space = plane_states[i]->color_space;
44d09c6a
HW		 4220 plane_info[i].format = plane_states[i]->format;
4221 plane_info[i].plane_size = plane_states[i]->plane_size;
4222 plane_info[i].rotation = plane_states[i]->rotation;
4223 plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
4224 plane_info[i].stereo_format = plane_states[i]->stereo_format;
4225 plane_info[i].tiling_info = plane_states[i]->tiling_info;
4226 plane_info[i].visible = plane_states[i]->visible;
4227 plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
4228 plane_info[i].dcc = plane_states[i]->dcc;
4229 scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
4230 scaling_info[i].src_rect = plane_states[i]->src_rect;
4231 scaling_info[i].dst_rect = plane_states[i]->dst_rect;
4232 scaling_info[i].clip_rect = plane_states[i]->clip_rect;
4233
4234 updates[i].flip_addr = &flip_addr[i];
4235 updates[i].plane_info = &plane_info[i];
4236 updates[i].scaling_info = &scaling_info[i];
4237 }
4238
4239 dc_commit_updates_for_stream(
4240 dc,
4241 updates,
4242 new_plane_count,
4243 dc_stream, stream_update, plane_states, state);
4244
4245 kfree(flip_addr);
4246 kfree(plane_info);
4247 kfree(scaling_info);
4248 kfree(stream_update);
4249 return true;
4250}
4251
3be5262e 4252static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3ee6b26b
AD		 4253 struct drm_device *dev,
4254 struct amdgpu_display_manager *dm,
4255 struct drm_crtc *pcrtc,
4256 bool *wait_for_vblank)
e7b07cee
HW		 4257{
4258 uint32_t i;
4259 struct drm_plane *plane;
0bc9706d 4260 struct drm_plane_state *old_plane_state, *new_plane_state;
0971c40e 4261 struct dc_stream_state *dc_stream_attach;
3be5262e 4262 struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
e7b07cee 4263 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4264 struct drm_crtc_state *new_pcrtc_state =
4265 drm_atomic_get_new_crtc_state(state, pcrtc);
4266 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4267 struct dm_crtc_state *dm_old_crtc_state =
4268 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
bc6828e0 4269 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
e7b07cee
HW		 4270 int planes_count = 0;
4271 unsigned long flags;
4272
4273 /* update planes when needed */
0bc9706d
LSL		 4274 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4275 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4276 struct drm_crtc_state *new_crtc_state;
0bc9706d 4277 struct drm_framebuffer *fb = new_plane_state->fb;
e7b07cee 4278 bool pflip_needed;
54d76575 4279 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee
HW		 4280
4281 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
4282 handle_cursor_update(plane, old_plane_state);
4283 continue;
4284 }
4285
f5ba60fe
DD		 4286 if (!fb || !crtc || pcrtc != crtc)
4287 continue;
4288
4289 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4290 if (!new_crtc_state->active)
e7b07cee
HW		 4291 continue;
4292
4293 pflip_needed = !state->allow_modeset;
4294
4295 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4296 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3be5262e
HW		 4297 DRM_ERROR("%s: acrtc %d, already busy\n",
4298 __func__,
4299 acrtc_attach->crtc_id);
b830ebc9 4300 /* In commit tail framework this cannot happen */
e7b07cee
HW		 4301 WARN_ON(1);
4302 }
4303 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4304
a2a330ad 4305 if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
54d76575 4306 WARN_ON(!dm_new_plane_state->dc_state);
e7b07cee 4307
54d76575 4308 plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
e7b07cee
HW		 4309
4310 dc_stream_attach = acrtc_state->stream;
4311 planes_count++;
4312
0bc9706d 4313 } else if (new_crtc_state->planes_changed) {
e7b07cee
HW		 4314 /* Assume even ONE crtc with immediate flip means
4315 * entire can't wait for VBLANK
4316 * TODO Check if it's correct
4317 */
4318 *wait_for_vblank =
0bc9706d 4319 new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
e7b07cee
HW		 4320 false : true;
4321
4322 /* TODO: Needs rework for multiplane flip */
4323 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
4324 drm_crtc_vblank_get(crtc);
4325
4326 amdgpu_dm_do_flip(
4327 crtc,
4328 fb,
23effc11 4329 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
bc6828e0 4330 dm_state->context);
e7b07cee
HW		 4331 }
4332
4333 }
4334
4335 if (planes_count) {
4336 unsigned long flags;
4337
0bc9706d 4338 if (new_pcrtc_state->event) {
e7b07cee
HW		 4339
4340 drm_crtc_vblank_get(pcrtc);
4341
4342 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4343 prepare_flip_isr(acrtc_attach);
4344 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4345 }
4346
98e6436d
AK		 4347 dc_stream_attach->adjust = acrtc_state->adjust;
4348 dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
44d09c6a
HW		 4349
4350 if (false == commit_planes_to_stream(dm->dc,
3be5262e
HW		 4351 plane_states_constructed,
4352 planes_count,
44d09c6a
HW		 4353 acrtc_state,
4354 dm_old_crtc_state,
bc6828e0 4355 dm_state->context))
3be5262e 4356 dm_error("%s: Failed to attach plane!\n", __func__);
e7b07cee
HW		 4357 } else {
4358 /*TODO BUG Here should go disable planes on CRTC. */
4359 }
4360}
4361
1f6010a9 4362/*
27b3f4fc
LSL		 4363 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4364 * @crtc_state: the DRM CRTC state
4365 * @stream_state: the DC stream state.
4366 *
4367 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4368 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4369 */
4370static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4371 struct dc_stream_state *stream_state)
4372{
4373 stream_state->mode_changed = crtc_state->mode_changed;
4374}
e7b07cee 4375
7578ecda
AD		 4376static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4377 struct drm_atomic_state *state,
4378 bool nonblock)
e7b07cee
HW		 4379{
4380 struct drm_crtc *crtc;
c2cea706 4381 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4382 struct amdgpu_device *adev = dev->dev_private;
4383 int i;
4384
4385 /*
4386 * We evade vblanks and pflips on crtc that
4387 * should be changed. We do it here to flush & disable
4388 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4389 * it will update crtc->dm_crtc_state->stream pointer which is used in
4390 * the ISRs.
4391 */
c2cea706 4392 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4393 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee
HW		 4394 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4395
54d76575 4396 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
e7b07cee
HW		 4397 manage_dm_interrupts(adev, acrtc, false);
4398 }
1f6010a9
DF		 4399 /*
4400 * Add check here for SoC's that support hardware cursor plane, to
4401 * unset legacy_cursor_update
4402 */
e7b07cee
HW		 4403
4404 return drm_atomic_helper_commit(dev, state, nonblock);
4405
4406 /*TODO Handle EINTR, reenable IRQ*/
4407}
4408
7578ecda 4409static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4410{
4411 struct drm_device *dev = state->dev;
4412 struct amdgpu_device *adev = dev->dev_private;
4413 struct amdgpu_display_manager *dm = &adev->dm;
4414 struct dm_atomic_state *dm_state;
4415 uint32_t i, j;
5cc6dcbd 4416 struct drm_crtc *crtc;
0bc9706d 4417 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4418 unsigned long flags;
4419 bool wait_for_vblank = true;
4420 struct drm_connector *connector;
c2cea706 4421 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4422 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4423 int crtc_disable_count = 0;
e7b07cee
HW		 4424
4425 drm_atomic_helper_update_legacy_modeset_state(dev, state);
4426
4427 dm_state = to_dm_atomic_state(state);
4428
4429 /* update changed items */
0bc9706d 4430 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 4431 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4432
54d76575
LSL		 4433 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4434 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 4435
f1ad2f5e 4436 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4437 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4438 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4439 "connectors_changed:%d\n",
4440 acrtc->crtc_id,
0bc9706d
LSL		 4441 new_crtc_state->enable,
4442 new_crtc_state->active,
4443 new_crtc_state->planes_changed,
4444 new_crtc_state->mode_changed,
4445 new_crtc_state->active_changed,
4446 new_crtc_state->connectors_changed);
e7b07cee 4447
27b3f4fc
LSL		 4448 /* Copy all transient state flags into dc state */
4449 if (dm_new_crtc_state->stream) {
4450 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4451 dm_new_crtc_state->stream);
4452 }
4453
e7b07cee
HW		 4454 /* handles headless hotplug case, updating new_state and
4455 * aconnector as needed
4456 */
4457
54d76575 4458 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 4459
f1ad2f5e 4460 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 4461
54d76575 4462 if (!dm_new_crtc_state->stream) {
e7b07cee 4463 /*
b830ebc9
HW		 4464 * this could happen because of issues with
4465 * userspace notifications delivery.
4466 * In this case userspace tries to set mode on
1f6010a9
DF		 4467 * display which is disconnected in fact.
4468 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 4469 * We expect reset mode will come soon.
4470 *
4471 * This can also happen when unplug is done
4472 * during resume sequence ended
4473 *
4474 * In this case, we want to pretend we still
4475 * have a sink to keep the pipe running so that
4476 * hw state is consistent with the sw state
4477 */
f1ad2f5e 4478 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 4479 __func__, acrtc->base.base.id);
4480 continue;
4481 }
4482
54d76575
LSL		 4483 if (dm_old_crtc_state->stream)
4484 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 4485
97028037
LP		 4486 pm_runtime_get_noresume(dev->dev);
4487
e7b07cee 4488 acrtc->enabled = true;
0bc9706d
LSL		 4489 acrtc->hw_mode = new_crtc_state->mode;
4490 crtc->hwmode = new_crtc_state->mode;
4491 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 4492 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 4493
4494 /* i.e. reset mode */
54d76575
LSL		 4495 if (dm_old_crtc_state->stream)
4496 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 4497 }
4498 } /* for_each_crtc_in_state() */
4499
fa2123db
ML		 4500 if (dm_state->context) {
4501 dm_enable_per_frame_crtc_master_sync(dm_state->context);
608ac7bb 4502 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
fa2123db 4503 }
e7b07cee 4504
0bc9706d 4505 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4506 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 4507
54d76575 4508 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4509
54d76575 4510 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 4511 const struct dc_stream_status *status =
54d76575 4512 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee
HW		 4513
4514 if (!status)
54d76575 4515 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 4516 else
4517 acrtc->otg_inst = status->primary_otg_inst;
4518 }
4519 }
4520
ebdd27e1 4521 /* Handle scaling and underscan changes*/
c2cea706 4522 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 4523 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4524 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4525 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 4526 struct dc_stream_status *status = NULL;
4527
44d09c6a 4528 if (acrtc) {
0bc9706d 4529 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 4530 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
4531 }
0bc9706d 4532
e7b07cee 4533 /* Skip any modesets/resets */
0bc9706d 4534 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 4535 continue;
4536
1f6010a9 4537 /* Skip anything that is not scaling or underscan changes */
54d76575 4538 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 4539 continue;
4540
54d76575 4541 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4542
54d76575
LSL		 4543 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4544 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 4545
70e8ffc5
HW		 4546 if (!dm_new_crtc_state->stream)
4547 continue;
4548
54d76575 4549 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 4550 WARN_ON(!status);
3be5262e 4551 WARN_ON(!status->plane_count);
e7b07cee 4552
98e6436d
AK		 4553 dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
4554 dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
4555
e7b07cee 4556 /*TODO How it works with MPO ?*/
44d09c6a 4557 if (!commit_planes_to_stream(
e7b07cee 4558 dm->dc,
3be5262e
HW		 4559 status->plane_states,
4560 status->plane_count,
44d09c6a
HW		 4561 dm_new_crtc_state,
4562 to_dm_crtc_state(old_crtc_state),
bc6828e0 4563 dm_state->context))
e7b07cee
HW		 4564 dm_error("%s: Failed to update stream scaling!\n", __func__);
4565 }
4566
e1fc2dca
LSL		 4567 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4568 new_crtc_state, i) {
e7b07cee
HW		 4569 /*
4570 * loop to enable interrupts on newly arrived crtc
4571 */
e1fc2dca
LSL		 4572 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4573 bool modeset_needed;
b830ebc9 4574
fe2a1965
LP		 4575 if (old_crtc_state->active && !new_crtc_state->active)
4576 crtc_disable_count++;
4577
54d76575 4578 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 4579 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4580 modeset_needed = modeset_required(
4581 new_crtc_state,
4582 dm_new_crtc_state->stream,
4583 dm_old_crtc_state->stream);
4584
4585 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4586 continue;
e7b07cee 4587
e7b07cee
HW		 4588 manage_dm_interrupts(adev, acrtc, true);
4589 }
4590
4591 /* update planes when needed per crtc*/
5cc6dcbd 4592 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 4593 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 4594
54d76575 4595 if (dm_new_crtc_state->stream)
5cc6dcbd 4596 amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
e7b07cee
HW		 4597 }
4598
4599
4600 /*
4601 * send vblank event on all events not handled in flip and
4602 * mark consumed event for drm_atomic_helper_commit_hw_done
4603 */
4604 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 4605 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 4606
0bc9706d
LSL		 4607 if (new_crtc_state->event)
4608 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 4609
0bc9706d 4610 new_crtc_state->event = NULL;
e7b07cee
HW		 4611 }
4612 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4613
4614 /* Signal HW programming completion */
4615 drm_atomic_helper_commit_hw_done(state);
4616
4617 if (wait_for_vblank)
320a1274 4618 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 4619
4620 drm_atomic_helper_cleanup_planes(dev, state);
97028037 4621
1f6010a9
DF		 4622 /*
4623 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 4624 * so we can put the GPU into runtime suspend if we're not driving any
4625 * displays anymore
4626 */
fe2a1965
LP		 4627 for (i = 0; i < crtc_disable_count; i++)
4628 pm_runtime_put_autosuspend(dev->dev);
97028037 4629 pm_runtime_mark_last_busy(dev->dev);
e7b07cee
HW		 4630}
4631
4632
4633static int dm_force_atomic_commit(struct drm_connector *connector)
4634{
4635 int ret = 0;
4636 struct drm_device *ddev = connector->dev;
4637 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4638 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4639 struct drm_plane *plane = disconnected_acrtc->base.primary;
4640 struct drm_connector_state *conn_state;
4641 struct drm_crtc_state *crtc_state;
4642 struct drm_plane_state *plane_state;
4643
4644 if (!state)
4645 return -ENOMEM;
4646
4647 state->acquire_ctx = ddev->mode_config.acquire_ctx;
4648
4649 /* Construct an atomic state to restore previous display setting */
4650
4651 /*
4652 * Attach connectors to drm_atomic_state
4653 */
4654 conn_state = drm_atomic_get_connector_state(state, connector);
4655
4656 ret = PTR_ERR_OR_ZERO(conn_state);
4657 if (ret)
4658 goto err;
4659
4660 /* Attach crtc to drm_atomic_state*/
4661 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4662
4663 ret = PTR_ERR_OR_ZERO(crtc_state);
4664 if (ret)
4665 goto err;
4666
4667 /* force a restore */
4668 crtc_state->mode_changed = true;
4669
4670 /* Attach plane to drm_atomic_state */
4671 plane_state = drm_atomic_get_plane_state(state, plane);
4672
4673 ret = PTR_ERR_OR_ZERO(plane_state);
4674 if (ret)
4675 goto err;
4676
4677
4678 /* Call commit internally with the state we just constructed */
4679 ret = drm_atomic_commit(state);
4680 if (!ret)
4681 return 0;
4682
4683err:
4684 DRM_ERROR("Restoring old state failed with %i\n", ret);
4685 drm_atomic_state_put(state);
4686
4687 return ret;
4688}
4689
4690/*
1f6010a9
DF		 4691 * This function handles all cases when set mode does not come upon hotplug.
4692 * This includes when a display is unplugged then plugged back into the
4693 * same port and when running without usermode desktop manager supprot
e7b07cee 4694 */
3ee6b26b
AD		 4695void dm_restore_drm_connector_state(struct drm_device *dev,
4696 struct drm_connector *connector)
e7b07cee 4697{
c84dec2f 4698 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4699 struct amdgpu_crtc *disconnected_acrtc;
4700 struct dm_crtc_state *acrtc_state;
4701
4702 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4703 return;
4704
4705 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 4706 if (!disconnected_acrtc)
4707 return;
e7b07cee 4708
70e8ffc5
HW		 4709 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4710 if (!acrtc_state->stream)
e7b07cee
HW		 4711 return;
4712
4713 /*
4714 * If the previous sink is not released and different from the current,
4715 * we deduce we are in a state where we can not rely on usermode call
4716 * to turn on the display, so we do it here
4717 */
4718 if (acrtc_state->stream->sink != aconnector->dc_sink)
4719 dm_force_atomic_commit(&aconnector->base);
4720}
4721
1f6010a9 4722/*
e7b07cee
HW		 4723 * Grabs all modesetting locks to serialize against any blocking commits,
4724 * Waits for completion of all non blocking commits.
4725 */
3ee6b26b
AD		 4726static int do_aquire_global_lock(struct drm_device *dev,
4727 struct drm_atomic_state *state)
e7b07cee
HW		 4728{
4729 struct drm_crtc *crtc;
4730 struct drm_crtc_commit *commit;
4731 long ret;
4732
1f6010a9
DF		 4733 /*
4734 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 4735 * ensure that when the framework release it the
4736 * extra locks we are locking here will get released to
4737 */
4738 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4739 if (ret)
4740 return ret;
4741
4742 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4743 spin_lock(&crtc->commit_lock);
4744 commit = list_first_entry_or_null(&crtc->commit_list,
4745 struct drm_crtc_commit, commit_entry);
4746 if (commit)
4747 drm_crtc_commit_get(commit);
4748 spin_unlock(&crtc->commit_lock);
4749
4750 if (!commit)
4751 continue;
4752
1f6010a9
DF		 4753 /*
4754 * Make sure all pending HW programming completed and
e7b07cee
HW		 4755 * page flips done
4756 */
4757 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4758
4759 if (ret > 0)
4760 ret = wait_for_completion_interruptible_timeout(
4761 &commit->flip_done, 10*HZ);
4762
4763 if (ret == 0)
4764 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 4765 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 4766
4767 drm_crtc_commit_put(commit);
4768 }
4769
4770 return ret < 0 ? ret : 0;
4771}
4772
98e6436d
AK		 4773void set_freesync_on_stream(struct amdgpu_display_manager *dm,
4774 struct dm_crtc_state *new_crtc_state,
4775 struct dm_connector_state *new_con_state,
4776 struct dc_stream_state *new_stream)
4777{
4778 struct mod_freesync_config config = {0};
4779 struct mod_vrr_params vrr = {0};
4780 struct dc_info_packet vrr_infopacket = {0};
4781 struct amdgpu_dm_connector *aconnector =
4782 to_amdgpu_dm_connector(new_con_state->base.connector);
4783
4784 if (new_con_state->freesync_capable &&
4785 new_con_state->freesync_enable) {
4786 config.state = new_crtc_state->freesync_enabled ?
4787 VRR_STATE_ACTIVE_VARIABLE :
4788 VRR_STATE_INACTIVE;
4789 config.min_refresh_in_uhz =
4790 aconnector->min_vfreq * 1000000;
4791 config.max_refresh_in_uhz =
4792 aconnector->max_vfreq * 1000000;
69ff8845 4793 config.vsif_supported = true;
98e6436d
AK		 4794 }
4795
4796 mod_freesync_build_vrr_params(dm->freesync_module,
4797 new_stream,
4798 &config, &vrr);
4799
4800 mod_freesync_build_vrr_infopacket(dm->freesync_module,
4801 new_stream,
4802 &vrr,
c2791297
S		 4803 packet_type_fs1,
4804 NULL,
98e6436d
AK		 4805 &vrr_infopacket);
4806
4807 new_crtc_state->adjust = vrr.adjust;
4808 new_crtc_state->vrr_infopacket = vrr_infopacket;
4809}
4810
4811static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
3ee6b26b
AD		 4812 struct drm_atomic_state *state,
4813 bool enable,
4814 bool *lock_and_validation_needed)
e7b07cee 4815{
e7b07cee 4816 struct drm_crtc *crtc;
c2cea706 4817 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537 4818 int i;
54d76575 4819 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
1dc90497 4820 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
9635b754 4821 struct dc_stream_state *new_stream;
62f55537 4822 int ret = 0;
d4d4a645 4823
1f6010a9
DF		 4824 /*
4825 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
4826 * update changed items
4827 */
c2cea706 4828 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
62f55537 4829 struct amdgpu_crtc *acrtc = NULL;
c84dec2f 4830 struct amdgpu_dm_connector *aconnector = NULL;
a9e8d275
DF		 4831 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
4832 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
f2877656 4833 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 4834
9635b754
DS		 4835 new_stream = NULL;
4836
54d76575
LSL		 4837 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4838 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
62f55537 4839 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 4840
f2877656
HW		 4841 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4842
4843 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4844 ret = -EINVAL;
4845 goto fail;
4846 }
4847
1daf8c63 4848 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 4849
62f55537 4850 /* TODO This hack should go away */
f4ac176e 4851 if (aconnector && enable) {
1f6010a9 4852 /* Make sure fake sink is created in plug-in scenario */
a9e8d275 4853 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
c2cea706 4854 &aconnector->base);
a9e8d275
DF		 4855 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
4856 &aconnector->base);
19f89e23 4857
a9e8d275
DF		 4858 if (IS_ERR(drm_new_conn_state)) {
4859 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
62f55537
AG		 4860 break;
4861 }
19f89e23 4862
a9e8d275
DF		 4863 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
4864 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 4865
62f55537 4866 new_stream = create_stream_for_sink(aconnector,
c2cea706 4867 &new_crtc_state->mode,
a9e8d275 4868 dm_new_conn_state);
19f89e23 4869
62f55537
AG		 4870 /*
4871 * we can have no stream on ACTION_SET if a display
1f6010a9 4872 * was disconnected during S3, in this case it is not an
62f55537 4873 * error, the OS will be updated after detection, and
1f6010a9 4874 * will do the right thing on next atomic commit
62f55537 4875 */
19f89e23 4876
62f55537 4877 if (!new_stream) {
f1ad2f5e 4878 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
62f55537
AG		 4879 __func__, acrtc->base.base.id);
4880 break;
19f89e23 4881 }
e7b07cee 4882
98e6436d
AK		 4883 set_freesync_on_stream(dm, dm_new_crtc_state,
4884 dm_new_conn_state, new_stream);
4885
a97599a4
LSL		 4886 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4887 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4888 new_crtc_state->mode_changed = false;
4889 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4890 new_crtc_state->mode_changed);
4891 }
62f55537 4892 }
b830ebc9 4893
98e6436d
AK		 4894 if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
4895 new_crtc_state->mode_changed = true;
4896
c2cea706 4897 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9635b754 4898 goto next_crtc;
e7b07cee 4899
f1ad2f5e 4900 DRM_DEBUG_DRIVER(
e7b07cee
HW		 4901 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4902 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4903 "connectors_changed:%d\n",
4904 acrtc->crtc_id,
c2cea706
LSL		 4905 new_crtc_state->enable,
4906 new_crtc_state->active,
4907 new_crtc_state->planes_changed,
4908 new_crtc_state->mode_changed,
4909 new_crtc_state->active_changed,
4910 new_crtc_state->connectors_changed);
e7b07cee 4911
62f55537
AG		 4912 /* Remove stream for any changed/disabled CRTC */
4913 if (!enable) {
4914
54d76575 4915 if (!dm_old_crtc_state->stream)
9635b754 4916 goto next_crtc;
62f55537 4917
f1ad2f5e 4918 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
62f55537 4919 crtc->base.id);
e7b07cee 4920
1dc90497 4921 /* i.e. reset mode */
62c933f9 4922 if (dc_remove_stream_from_ctx(
98e6436d 4923 dm->dc,
62f55537 4924 dm_state->context,
62c933f9 4925 dm_old_crtc_state->stream) != DC_OK) {
62f55537 4926 ret = -EINVAL;
9635b754 4927 goto fail;
62f55537
AG		 4928 }
4929
54d76575
LSL		 4930 dc_stream_release(dm_old_crtc_state->stream);
4931 dm_new_crtc_state->stream = NULL;
62f55537
AG		 4932
4933 *lock_and_validation_needed = true;
4934
4935 } else {/* Add stream for any updated/enabled CRTC */
fc17235f
JZ		 4936 /*
4937 * Quick fix to prevent NULL pointer on new_stream when
4938 * added MST connectors not found in existing crtc_state in the chained mode
4939 * TODO: need to dig out the root cause of that
4940 */
4941 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
1bed4d09 4942 goto next_crtc;
62f55537 4943
c2cea706 4944 if (modereset_required(new_crtc_state))
9635b754 4945 goto next_crtc;
62f55537 4946
c2cea706 4947 if (modeset_required(new_crtc_state, new_stream,
54d76575 4948 dm_old_crtc_state->stream)) {
62f55537 4949
54d76575 4950 WARN_ON(dm_new_crtc_state->stream);
62f55537 4951
54d76575 4952 dm_new_crtc_state->stream = new_stream;
27b3f4fc 4953
62f55537
AG		 4954 dc_stream_retain(new_stream);
4955
f1ad2f5e 4956 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
62f55537 4957 crtc->base.id);
1dc90497 4958
13ab1b44 4959 if (dc_add_stream_to_ctx(
98e6436d 4960 dm->dc,
1dc90497 4961 dm_state->context,
13ab1b44 4962 dm_new_crtc_state->stream) != DC_OK) {
1dc90497 4963 ret = -EINVAL;
9635b754 4964 goto fail;
1dc90497
AG		 4965 }
4966
62f55537 4967 *lock_and_validation_needed = true;
9b690ef3 4968 }
62f55537 4969 }
9b690ef3 4970
9635b754 4971next_crtc:
62f55537
AG		 4972 /* Release extra reference */
4973 if (new_stream)
4974 dc_stream_release(new_stream);
e277adc5
LSL		 4975
4976 /*
4977 * We want to do dc stream updates that do not require a
4978 * full modeset below.
4979 */
20fa2ff0
LSL		 4980 if (!(enable && aconnector && new_crtc_state->enable &&
4981 new_crtc_state->active))
e277adc5
LSL		 4982 continue;
4983 /*
4984 * Given above conditions, the dc state cannot be NULL because:
20fa2ff0
LSL		 4985 * 1. We're in the process of enabling CRTCs (just been added
4986 * to the dc context, or already is on the context)
4987 * 2. Has a valid connector attached, and
4988 * 3. Is currently active and enabled.
4989 * => The dc stream state currently exists.
e277adc5
LSL		 4990 */
4991 BUG_ON(dm_new_crtc_state->stream == NULL);
4992
a9e8d275
DF		 4993 /* Scaling or underscan settings */
4994 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
4995 update_stream_scaling_settings(
4996 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
4997
bc13f2f8
LSL		 4998 /*
4999 * Color management settings. We also update color properties
5000 * when a modeset is needed, to ensure it gets reprogrammed.
5001 */
5002 if (dm_new_crtc_state->base.color_mgmt_changed ||
5003 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
e277adc5
LSL		 5004 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5005 if (ret)
5006 goto fail;
5007 amdgpu_dm_set_ctm(dm_new_crtc_state);
5008 }
98e6436d
AK		 5009
5010
62f55537 5011 }
e7b07cee 5012
62f55537 5013 return ret;
9635b754
DS		 5014
5015fail:
5016 if (new_stream)
5017 dc_stream_release(new_stream);
5018 return ret;
62f55537 5019}
9b690ef3 5020
3ee6b26b
AD		 5021static int dm_update_planes_state(struct dc *dc,
5022 struct drm_atomic_state *state,
5023 bool enable,
5024 bool *lock_and_validation_needed)
62f55537
AG		 5025{
5026 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 5027 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
62f55537
AG		 5028 struct drm_plane *plane;
5029 struct drm_plane_state *old_plane_state, *new_plane_state;
54d76575 5030 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
62f55537 5031 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
54d76575 5032 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 5033 int i ;
5034 /* TODO return page_flip_needed() function */
5035 bool pflip_needed = !state->allow_modeset;
5036 int ret = 0;
e7b07cee 5037
9b690ef3 5038
df534fff
S		 5039 /* Add new planes, in reverse order as DC expectation */
5040 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
62f55537
AG		 5041 new_plane_crtc = new_plane_state->crtc;
5042 old_plane_crtc = old_plane_state->crtc;
54d76575
LSL		 5043 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5044 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537
AG		 5045
5046 /*TODO Implement atomic check for cursor plane */
5047 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5048 continue;
9b690ef3 5049
62f55537
AG		 5050 /* Remove any changed/removed planes */
5051 if (!enable) {
a2a330ad
S		 5052 if (pflip_needed &&
5053 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 5054 continue;
a7b06724 5055
62f55537
AG		 5056 if (!old_plane_crtc)
5057 continue;
5058
0bc9706d
LSL		 5059 old_crtc_state = drm_atomic_get_old_crtc_state(
5060 state, old_plane_crtc);
54d76575 5061 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 5062
54d76575 5063 if (!dm_old_crtc_state->stream)
62f55537
AG		 5064 continue;
5065
f2877656 5066 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
62f55537 5067 plane->base.id, old_plane_crtc->base.id);
9b690ef3 5068
62f55537
AG		 5069 if (!dc_remove_plane_from_context(
5070 dc,
54d76575
LSL		 5071 dm_old_crtc_state->stream,
5072 dm_old_plane_state->dc_state,
62f55537
AG		 5073 dm_state->context)) {
5074
5075 ret = EINVAL;
5076 return ret;
e7b07cee
HW		 5077 }
5078
9b690ef3 5079
54d76575
LSL		 5080 dc_plane_state_release(dm_old_plane_state->dc_state);
5081 dm_new_plane_state->dc_state = NULL;
1dc90497 5082
62f55537 5083 *lock_and_validation_needed = true;
1dc90497 5084
62f55537 5085 } else { /* Add new planes */
8c45c5db 5086 struct dc_plane_state *dc_new_plane_state;
1dc90497 5087
62f55537
AG		 5088 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5089 continue;
e7b07cee 5090
62f55537
AG		 5091 if (!new_plane_crtc)
5092 continue;
e7b07cee 5093
62f55537 5094 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
54d76575 5095 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 5096
54d76575 5097 if (!dm_new_crtc_state->stream)
62f55537
AG		 5098 continue;
5099
a2a330ad
S		 5100 if (pflip_needed &&
5101 plane->type != DRM_PLANE_TYPE_OVERLAY)
c21b68c5 5102 continue;
62f55537 5103
54d76575 5104 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 5105
8c45c5db 5106 dc_new_plane_state = dc_create_plane_state(dc);
d5400aab
LSL		 5107 if (!dc_new_plane_state)
5108 return -ENOMEM;
62f55537 5109
8c45c5db
LSL		 5110 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5111 plane->base.id, new_plane_crtc->base.id);
5112
62f55537
AG		 5113 ret = fill_plane_attributes(
5114 new_plane_crtc->dev->dev_private,
8c45c5db 5115 dc_new_plane_state,
62f55537 5116 new_plane_state,
9817d5f5 5117 new_crtc_state);
8c45c5db
LSL		 5118 if (ret) {
5119 dc_plane_state_release(dc_new_plane_state);
62f55537 5120 return ret;
8c45c5db 5121 }
62f55537 5122
8c45c5db
LSL		 5123 /*
5124 * Any atomic check errors that occur after this will
5125 * not need a release. The plane state will be attached
5126 * to the stream, and therefore part of the atomic
5127 * state. It'll be released when the atomic state is
5128 * cleaned.
5129 */
62f55537
AG		 5130 if (!dc_add_plane_to_context(
5131 dc,
54d76575 5132 dm_new_crtc_state->stream,
8c45c5db 5133 dc_new_plane_state,
62f55537
AG		 5134 dm_state->context)) {
5135
8c45c5db 5136 dc_plane_state_release(dc_new_plane_state);
d5400aab 5137 return -EINVAL;
e7b07cee 5138 }
62f55537 5139
8c45c5db
LSL		 5140 dm_new_plane_state->dc_state = dc_new_plane_state;
5141
000b59ea
LSL		 5142 /* Tell DC to do a full surface update every time there
5143 * is a plane change. Inefficient, but works for now.
5144 */
5145 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5146
62f55537 5147 *lock_and_validation_needed = true;
e7b07cee 5148 }
62f55537 5149 }
e7b07cee
HW		 5150
5151
62f55537
AG		 5152 return ret;
5153}
a87fa993
BL		 5154enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, struct drm_atomic_state *state)
5155{
5156
5157
5158 int i, j, num_plane;
5159 struct drm_plane_state *old_plane_state, *new_plane_state;
5160 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5161 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5162 struct drm_plane *plane;
5163
5164 struct drm_crtc *crtc;
5165 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5166 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5167 struct dc_stream_status *status = NULL;
5168
5169 struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL);
5170 struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL);
5171 struct dc_stream_update stream_update;
5172 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5173
5174
5175 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5176 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5177 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5178 num_plane = 0;
5179
5180 if (new_dm_crtc_state->stream) {
5181
5182 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5183 new_plane_crtc = new_plane_state->crtc;
5184 old_plane_crtc = old_plane_state->crtc;
5185 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5186 old_dm_plane_state = to_dm_plane_state(old_plane_state);
5187
5188 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5189 continue;
5190
5191 if (!state->allow_modeset)
5192 continue;
5193
5194 if (crtc == new_plane_crtc) {
5195 updates[num_plane].surface = &surface[num_plane];
5196
5197 if (new_crtc_state->mode_changed) {
5198 updates[num_plane].surface->src_rect =
5199 new_dm_plane_state->dc_state->src_rect;
5200 updates[num_plane].surface->dst_rect =
5201 new_dm_plane_state->dc_state->dst_rect;
5202 updates[num_plane].surface->rotation =
5203 new_dm_plane_state->dc_state->rotation;
5204 updates[num_plane].surface->in_transfer_func =
5205 new_dm_plane_state->dc_state->in_transfer_func;
5206 stream_update.dst = new_dm_crtc_state->stream->dst;
5207 stream_update.src = new_dm_crtc_state->stream->src;
5208 }
5209
5210 if (new_crtc_state->color_mgmt_changed) {
5211 updates[num_plane].gamma =
5212 new_dm_plane_state->dc_state->gamma_correction;
5213 updates[num_plane].in_transfer_func =
5214 new_dm_plane_state->dc_state->in_transfer_func;
5215 stream_update.gamut_remap =
5216 &new_dm_crtc_state->stream->gamut_remap_matrix;
5217 stream_update.out_transfer_func =
5218 new_dm_crtc_state->stream->out_transfer_func;
5219 }
5220
5221 num_plane++;
5222 }
5223 }
5224
5225 if (num_plane > 0) {
5226 status = dc_stream_get_status(new_dm_crtc_state->stream);
5227 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5228 &stream_update, status);
5229
5230 if (update_type > UPDATE_TYPE_MED) {
5231 update_type = UPDATE_TYPE_FULL;
5232 goto ret;
5233 }
5234 }
5235
5236 } else if (!new_dm_crtc_state->stream && old_dm_crtc_state->stream) {
5237 update_type = UPDATE_TYPE_FULL;
5238 goto ret;
5239 }
5240 }
5241
5242ret:
5243 kfree(updates);
5244 kfree(surface);
5245
5246 return update_type;
5247}
62f55537 5248
7578ecda
AD		 5249static int amdgpu_dm_atomic_check(struct drm_device *dev,
5250 struct drm_atomic_state *state)
62f55537 5251{
62f55537
AG		 5252 struct amdgpu_device *adev = dev->dev_private;
5253 struct dc *dc = adev->dm.dc;
5254 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
5255 struct drm_connector *connector;
c2cea706 5256 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5257 struct drm_crtc *crtc;
fc9e9920 5258 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
a87fa993
BL		 5259 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5260 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5261
1e88ad0a 5262 int ret, i;
e7b07cee 5263
62f55537
AG		 5264 /*
5265 * This bool will be set for true for any modeset/reset
5266 * or plane update which implies non fast surface update.
5267 */
5268 bool lock_and_validation_needed = false;
5269
5270 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5271 if (ret)
5272 goto fail;
62f55537 5273
1e88ad0a 5274 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
98e6436d
AK		 5275 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5276 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5277
1e88ad0a 5278 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d
AK		 5279 !new_crtc_state->color_mgmt_changed &&
5280 (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
1e88ad0a 5281 continue;
7bef1af3 5282
1e88ad0a
S		 5283 if (!new_crtc_state->enable)
5284 continue;
fc9e9920 5285
1e88ad0a
S		 5286 ret = drm_atomic_add_affected_connectors(state, crtc);
5287 if (ret)
5288 return ret;
fc9e9920 5289
1e88ad0a
S		 5290 ret = drm_atomic_add_affected_planes(state, crtc);
5291 if (ret)
5292 goto fail;
e7b07cee
HW		 5293 }
5294
62f55537
AG		 5295 dm_state->context = dc_create_state();
5296 ASSERT(dm_state->context);
f36cc577 5297 dc_resource_state_copy_construct_current(dc, dm_state->context);
62f55537
AG		 5298
5299 /* Remove exiting planes if they are modified */
5300 ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
5301 if (ret) {
5302 goto fail;
5303 }
5304
5305 /* Disable all crtcs which require disable */
98e6436d 5306 ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
62f55537
AG		 5307 if (ret) {
5308 goto fail;
5309 }
5310
5311 /* Enable all crtcs which require enable */
98e6436d 5312 ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
62f55537
AG		 5313 if (ret) {
5314 goto fail;
5315 }
5316
5317 /* Add new/modified planes */
5318 ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
5319 if (ret) {
5320 goto fail;
5321 }
5322
b349f76e
ES		 5323 /* Run this here since we want to validate the streams we created */
5324 ret = drm_atomic_helper_check_planes(dev, state);
5325 if (ret)
5326 goto fail;
62f55537 5327
ebdd27e1 5328 /* Check scaling and underscan changes*/
1f6010a9 5329 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 5330 * new stream into context w\o causing full reset. Need to
5331 * decide how to handle.
5332 */
c2cea706 5333 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5334 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5335 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5336 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 5337
5338 /* Skip any modesets/resets */
0bc9706d
LSL		 5339 if (!acrtc || drm_atomic_crtc_needs_modeset(
5340 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 5341 continue;
5342
b830ebc9 5343 /* Skip any thing not scale or underscan changes */
54d76575 5344 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 5345 continue;
5346
a87fa993 5347 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 5348 lock_and_validation_needed = true;
5349 }
5350
e7b07cee
HW		 5351 /*
5352 * For full updates case when
1f6010a9 5353 * removing/adding/updating streams on one CRTC while flipping
e7b07cee
HW		 5354 * on another CRTC,
5355 * acquiring global lock will guarantee that any such full
5356 * update commit
5357 * will wait for completion of any outstanding flip using DRMs
5358 * synchronization events.
5359 */
a87fa993
BL		 5360 update_type = dm_determine_update_type_for_commit(dc, state);
5361
5362 if (overall_update_type < update_type)
5363 overall_update_type = update_type;
5364
5365 /*
5366 * lock_and_validation_needed was an old way to determine if we need to set
5367 * the global lock. Leaving it in to check if we broke any corner cases
5368 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
5369 * lock_and_validation_needed false = UPDATE_TYPE_FAST
5370 */
5371 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
5372 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
5373 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
5374 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
e7b07cee 5375
e7b07cee 5376
a87fa993 5377 if (overall_update_type > UPDATE_TYPE_FAST) {
e7b07cee
HW		 5378
5379 ret = do_aquire_global_lock(dev, state);
5380 if (ret)
5381 goto fail;
1dc90497 5382
e750d56d 5383 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 5384 ret = -EINVAL;
5385 goto fail;
5386 }
5387 }
5388
5389 /* Must be success */
5390 WARN_ON(ret);
5391 return ret;
5392
5393fail:
5394 if (ret == -EDEADLK)
01e28f9c 5395 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 5396 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 5397 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 5398 else
01e28f9c 5399 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 5400
5401 return ret;
5402}
5403
3ee6b26b
AD		 5404static bool is_dp_capable_without_timing_msa(struct dc *dc,
5405 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 5406{
5407 uint8_t dpcd_data;
5408 bool capable = false;
5409
c84dec2f 5410 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 5411 dm_helpers_dp_read_dpcd(
5412 NULL,
c84dec2f 5413 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 5414 DP_DOWN_STREAM_PORT_COUNT,
5415 &dpcd_data,
5416 sizeof(dpcd_data))) {
5417 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
5418 }
5419
5420 return capable;
5421}
98e6436d
AK		 5422void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
5423 struct edid *edid)
e7b07cee
HW		 5424{
5425 int i;
e7b07cee
HW		 5426 bool edid_check_required;
5427 struct detailed_timing *timing;
5428 struct detailed_non_pixel *data;
5429 struct detailed_data_monitor_range *range;
c84dec2f
HW		 5430 struct amdgpu_dm_connector *amdgpu_dm_connector =
5431 to_amdgpu_dm_connector(connector);
8218d7f1 5432 struct dm_connector_state *dm_con_state;
e7b07cee
HW		 5433
5434 struct drm_device *dev = connector->dev;
5435 struct amdgpu_device *adev = dev->dev_private;
b830ebc9 5436
8218d7f1
HW		 5437 if (!connector->state) {
5438 DRM_ERROR("%s - Connector has no state", __func__);
5439 return;
5440 }
5441
98e6436d
AK		 5442 if (!edid) {
5443 dm_con_state = to_dm_connector_state(connector->state);
5444
5445 amdgpu_dm_connector->min_vfreq = 0;
5446 amdgpu_dm_connector->max_vfreq = 0;
5447 amdgpu_dm_connector->pixel_clock_mhz = 0;
5448
5449 dm_con_state->freesync_capable = false;
5450 dm_con_state->freesync_enable = false;
5451 return;
5452 }
5453
8218d7f1
HW		 5454 dm_con_state = to_dm_connector_state(connector->state);
5455
e7b07cee 5456 edid_check_required = false;
c84dec2f 5457 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee
HW		 5458 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
5459 return;
5460 }
5461 if (!adev->dm.freesync_module)
5462 return;
5463 /*
5464 * if edid non zero restrict freesync only for dp and edp
5465 */
5466 if (edid) {
c84dec2f
HW		 5467 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
5468 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 5469 edid_check_required = is_dp_capable_without_timing_msa(
5470 adev->dm.dc,
c84dec2f 5471 amdgpu_dm_connector);
e7b07cee
HW		 5472 }
5473 }
8218d7f1 5474 dm_con_state->freesync_capable = false;
e7b07cee
HW		 5475 if (edid_check_required == true && (edid->version > 1 ||
5476 (edid->version == 1 && edid->revision > 1))) {
5477 for (i = 0; i < 4; i++) {
5478
5479 timing = &edid->detailed_timings[i];
5480 data = &timing->data.other_data;
5481 range = &data->data.range;
5482 /*
5483 * Check if monitor has continuous frequency mode
5484 */
5485 if (data->type != EDID_DETAIL_MONITOR_RANGE)
5486 continue;
5487 /*
5488 * Check for flag range limits only. If flag == 1 then
5489 * no additional timing information provided.
5490 * Default GTF, GTF Secondary curve and CVT are not
5491 * supported
5492 */
5493 if (range->flags != 1)
5494 continue;
5495
c84dec2f
HW		 5496 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
5497 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
5498 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 5499 range->pixel_clock_mhz * 10;
5500 break;
5501 }
5502
c84dec2f 5503 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 5504 amdgpu_dm_connector->min_vfreq > 10) {
5505
8218d7f1 5506 dm_con_state->freesync_capable = true;
e7b07cee
HW		 5507 }
5508 }
e7b07cee
HW		 5509}
5510
Linux 6.x block layer and io_uring tree(s)