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drm/amd/display: Create overlay planes
[linux-2.6-block.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm.c
CommitLineData
4562236b
HW		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
0cf5eb76
DF		 26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS
28
4562236b
HW		 29#include "dm_services_types.h"
30#include "dc.h"
1dc90497 31#include "dc/inc/core_types.h"
4562236b
HW		 32
33#include "vid.h"
34#include "amdgpu.h"
a49dcb88 35#include "amdgpu_display.h"
a94d5569 36#include "amdgpu_ucode.h"
4562236b
HW		 37#include "atom.h"
38#include "amdgpu_dm.h"
e7b07cee 39#include "amdgpu_pm.h"
4562236b
HW		 40
41#include "amd_shared.h"
42#include "amdgpu_dm_irq.h"
43#include "dm_helpers.h"
e7b07cee 44#include "amdgpu_dm_mst_types.h"
dc38fd9d
DF		 45#if defined(CONFIG_DEBUG_FS)
46#include "amdgpu_dm_debugfs.h"
47#endif
4562236b
HW		 48
49#include "ivsrcid/ivsrcid_vislands30.h"
50
51#include <linux/module.h>
52#include <linux/moduleparam.h>
53#include <linux/version.h>
e7b07cee 54#include <linux/types.h>
97028037 55#include <linux/pm_runtime.h>
a94d5569 56#include <linux/firmware.h>
4562236b 57
e7b07cee 58#include <drm/drmP.h>
4562236b 59#include <drm/drm_atomic.h>
674e78ac 60#include <drm/drm_atomic_uapi.h>
4562236b
HW		 61#include <drm/drm_atomic_helper.h>
62#include <drm/drm_dp_mst_helper.h>
e7b07cee
HW		 63#include <drm/drm_fb_helper.h>
64#include <drm/drm_edid.h>
4562236b 65
ff5ef992
AD		 66#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
67#include "ivsrcid/irqsrcs_dcn_1_0.h"
68
ad941f7a
FX		 69#include "dcn/dcn_1_0_offset.h"
70#include "dcn/dcn_1_0_sh_mask.h"
407e7517
HZ		 71#include "soc15_hw_ip.h"
72#include "vega10_ip_offset.h"
ff5ef992
AD		 73
74#include "soc15_common.h"
75#endif
76
e7b07cee 77#include "modules/inc/mod_freesync.h"
bbf854dc 78#include "modules/power/power_helpers.h"
ecd0136b 79#include "modules/inc/mod_info_packet.h"
e7b07cee 80
a94d5569
DF		 81#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
82MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
e7b07cee 83
b8592b48
LL		 84/**
85 * DOC: overview
86 *
87 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
88 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
89 * requests into DC requests, and DC responses into DRM responses.
90 *
91 * The root control structure is &struct amdgpu_display_manager.
92 */
93
7578ecda
AD		 94/* basic init/fini API */
95static int amdgpu_dm_init(struct amdgpu_device *adev);
96static void amdgpu_dm_fini(struct amdgpu_device *adev);
97
1f6010a9
DF		 98/*
99 * initializes drm_device display related structures, based on the information
7578ecda
AD		 100 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
101 * drm_encoder, drm_mode_config
102 *
103 * Returns 0 on success
104 */
105static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
106/* removes and deallocates the drm structures, created by the above function */
107static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
108
109static void
110amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
111
112static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 113 struct drm_plane *plane,
7578ecda
AD		 114 unsigned long possible_crtcs);
115static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
116 struct drm_plane *plane,
117 uint32_t link_index);
118static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
119 struct amdgpu_dm_connector *amdgpu_dm_connector,
120 uint32_t link_index,
121 struct amdgpu_encoder *amdgpu_encoder);
122static int amdgpu_dm_encoder_init(struct drm_device *dev,
123 struct amdgpu_encoder *aencoder,
124 uint32_t link_index);
125
126static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
127
128static int amdgpu_dm_atomic_commit(struct drm_device *dev,
129 struct drm_atomic_state *state,
130 bool nonblock);
131
132static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
133
134static int amdgpu_dm_atomic_check(struct drm_device *dev,
135 struct drm_atomic_state *state);
136
674e78ac
NK		 137static void handle_cursor_update(struct drm_plane *plane,
138 struct drm_plane_state *old_plane_state);
7578ecda 139
4562236b
HW		 140/*
141 * dm_vblank_get_counter
142 *
143 * @brief
144 * Get counter for number of vertical blanks
145 *
146 * @param
147 * struct amdgpu_device *adev - [in] desired amdgpu device
148 * int disp_idx - [in] which CRTC to get the counter from
149 *
150 * @return
151 * Counter for vertical blanks
152 */
153static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
154{
155 if (crtc >= adev->mode_info.num_crtc)
156 return 0;
157 else {
158 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 159 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
160 acrtc->base.state);
4562236b 161
da5c47f6
AG		 162
163 if (acrtc_state->stream == NULL) {
0971c40e
HW		 164 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
165 crtc);
4562236b
HW		 166 return 0;
167 }
168
da5c47f6 169 return dc_stream_get_vblank_counter(acrtc_state->stream);
4562236b
HW		 170 }
171}
172
173static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
3ee6b26b 174 u32 *vbl, u32 *position)
4562236b 175{
81c50963
ST		 176 uint32_t v_blank_start, v_blank_end, h_position, v_position;
177
4562236b
HW		 178 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
179 return -EINVAL;
180 else {
181 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
da5c47f6
AG		 182 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
183 acrtc->base.state);
4562236b 184
da5c47f6 185 if (acrtc_state->stream == NULL) {
0971c40e
HW		 186 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
187 crtc);
4562236b
HW		 188 return 0;
189 }
190
81c50963
ST		 191 /*
192 * TODO rework base driver to use values directly.
193 * for now parse it back into reg-format
194 */
da5c47f6 195 dc_stream_get_scanoutpos(acrtc_state->stream,
81c50963
ST		 196 &v_blank_start,
197 &v_blank_end,
198 &h_position,
199 &v_position);
200
e806208d
AG		 201 *position = v_position | (h_position << 16);
202 *vbl = v_blank_start | (v_blank_end << 16);
4562236b
HW		 203 }
204
205 return 0;
206}
207
208static bool dm_is_idle(void *handle)
209{
210 /* XXX todo */
211 return true;
212}
213
214static int dm_wait_for_idle(void *handle)
215{
216 /* XXX todo */
217 return 0;
218}
219
220static bool dm_check_soft_reset(void *handle)
221{
222 return false;
223}
224
225static int dm_soft_reset(void *handle)
226{
227 /* XXX todo */
228 return 0;
229}
230
3ee6b26b
AD		 231static struct amdgpu_crtc *
232get_crtc_by_otg_inst(struct amdgpu_device *adev,
233 int otg_inst)
4562236b
HW		 234{
235 struct drm_device *dev = adev->ddev;
236 struct drm_crtc *crtc;
237 struct amdgpu_crtc *amdgpu_crtc;
238
4562236b
HW		 239 if (otg_inst == -1) {
240 WARN_ON(1);
241 return adev->mode_info.crtcs[0];
242 }
243
244 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
245 amdgpu_crtc = to_amdgpu_crtc(crtc);
246
247 if (amdgpu_crtc->otg_inst == otg_inst)
248 return amdgpu_crtc;
249 }
250
251 return NULL;
252}
253
254static void dm_pflip_high_irq(void *interrupt_params)
255{
4562236b
HW		 256 struct amdgpu_crtc *amdgpu_crtc;
257 struct common_irq_params *irq_params = interrupt_params;
258 struct amdgpu_device *adev = irq_params->adev;
259 unsigned long flags;
260
261 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
262
263 /* IRQ could occur when in initial stage */
1f6010a9 264 /* TODO work and BO cleanup */
4562236b
HW		 265 if (amdgpu_crtc == NULL) {
266 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
267 return;
268 }
269
270 spin_lock_irqsave(&adev->ddev->event_lock, flags);
4562236b
HW		 271
272 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
273 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
274 amdgpu_crtc->pflip_status,
275 AMDGPU_FLIP_SUBMITTED,
276 amdgpu_crtc->crtc_id,
277 amdgpu_crtc);
278 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
279 return;
280 }
281
7b19bba5
MK		 282 /* Update to correct count(s) if racing with vblank irq */
283 amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
4562236b 284
1f6010a9 285 /* wake up userspace */
1159898a 286 if (amdgpu_crtc->event) {
54f5499a 287 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
1159898a 288
54f5499a
AG		 289 /* page flip completed. clean up */
290 amdgpu_crtc->event = NULL;
1159898a 291
54f5499a
AG		 292 } else
293 WARN_ON(1);
4562236b 294
54f5499a 295 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
4562236b
HW		 296 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
297
54f5499a
AG		 298 DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
299 __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
4562236b
HW		 300
301 drm_crtc_vblank_put(&amdgpu_crtc->base);
4562236b
HW		 302}
303
304static void dm_crtc_high_irq(void *interrupt_params)
305{
306 struct common_irq_params *irq_params = interrupt_params;
307 struct amdgpu_device *adev = irq_params->adev;
4562236b 308 struct amdgpu_crtc *acrtc;
180db303 309 struct dm_crtc_state *acrtc_state;
4562236b 310
b57de80a 311 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
4562236b 312
e5d0170e
LSL		 313 if (acrtc) {
314 drm_crtc_handle_vblank(&acrtc->base);
315 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
180db303
NK		 316
317 acrtc_state = to_dm_crtc_state(acrtc->base.state);
318
319 if (acrtc_state->stream &&
320 acrtc_state->vrr_params.supported &&
321 acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
322 mod_freesync_handle_v_update(
323 adev->dm.freesync_module,
324 acrtc_state->stream,
325 &acrtc_state->vrr_params);
326
327 dc_stream_adjust_vmin_vmax(
328 adev->dm.dc,
329 acrtc_state->stream,
330 &acrtc_state->vrr_params.adjust);
331 }
e5d0170e 332 }
4562236b
HW		 333}
334
335static int dm_set_clockgating_state(void *handle,
336 enum amd_clockgating_state state)
337{
338 return 0;
339}
340
341static int dm_set_powergating_state(void *handle,
342 enum amd_powergating_state state)
343{
344 return 0;
345}
346
347/* Prototypes of private functions */
348static int dm_early_init(void* handle);
349
a32e24b4 350/* Allocate memory for FBC compressed data */
3e332d3a 351static void amdgpu_dm_fbc_init(struct drm_connector *connector)
a32e24b4 352{
3e332d3a
RL		 353 struct drm_device *dev = connector->dev;
354 struct amdgpu_device *adev = dev->dev_private;
a32e24b4 355 struct dm_comressor_info *compressor = &adev->dm.compressor;
3e332d3a
RL		 356 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
357 struct drm_display_mode *mode;
42e67c3b
RL		 358 unsigned long max_size = 0;
359
360 if (adev->dm.dc->fbc_compressor == NULL)
361 return;
a32e24b4 362
3e332d3a 363 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
42e67c3b
RL		 364 return;
365
3e332d3a
RL		 366 if (compressor->bo_ptr)
367 return;
42e67c3b 368
42e67c3b 369
3e332d3a
RL		 370 list_for_each_entry(mode, &connector->modes, head) {
371 if (max_size < mode->htotal * mode->vtotal)
372 max_size = mode->htotal * mode->vtotal;
42e67c3b
RL		 373 }
374
375 if (max_size) {
376 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
0e5916ff 377 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
42e67c3b 378 &compressor->gpu_addr, &compressor->cpu_addr);
a32e24b4
RL		 379
380 if (r)
42e67c3b
RL		 381 DRM_ERROR("DM: Failed to initialize FBC\n");
382 else {
383 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
384 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
385 }
386
a32e24b4
RL		 387 }
388
389}
a32e24b4 390
7578ecda 391static int amdgpu_dm_init(struct amdgpu_device *adev)
4562236b
HW		 392{
393 struct dc_init_data init_data;
394 adev->dm.ddev = adev->ddev;
395 adev->dm.adev = adev;
396
4562236b
HW		 397 /* Zero all the fields */
398 memset(&init_data, 0, sizeof(init_data));
399
674e78ac
NK		 400 mutex_init(&adev->dm.dc_lock);
401
4562236b
HW		 402 if(amdgpu_dm_irq_init(adev)) {
403 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
404 goto error;
405 }
406
407 init_data.asic_id.chip_family = adev->family;
408
409 init_data.asic_id.pci_revision_id = adev->rev_id;
410 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
411
770d13b1 412 init_data.asic_id.vram_width = adev->gmc.vram_width;
4562236b
HW		 413 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
414 init_data.asic_id.atombios_base_address =
415 adev->mode_info.atom_context->bios;
416
417 init_data.driver = adev;
418
419 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
420
421 if (!adev->dm.cgs_device) {
422 DRM_ERROR("amdgpu: failed to create cgs device.\n");
423 goto error;
424 }
425
426 init_data.cgs_device = adev->dm.cgs_device;
427
4562236b
HW		 428 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
429
6e227308
HW		 430 /*
431 * TODO debug why this doesn't work on Raven
432 */
433 if (adev->flags & AMD_IS_APU &&
434 adev->asic_type >= CHIP_CARRIZO &&
435 adev->asic_type < CHIP_RAVEN)
436 init_data.flags.gpu_vm_support = true;
437
04b94af4
AD		 438 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
439 init_data.flags.fbc_support = true;
440
4562236b
HW		 441 /* Display Core create. */
442 adev->dm.dc = dc_create(&init_data);
443
423788c7 444 if (adev->dm.dc) {
76121231 445 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
423788c7 446 } else {
76121231 447 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
423788c7
ES		 448 goto error;
449 }
4562236b 450
4562236b
HW		 451 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
452 if (!adev->dm.freesync_module) {
453 DRM_ERROR(
454 "amdgpu: failed to initialize freesync_module.\n");
455 } else
f1ad2f5e 456 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
4562236b
HW		 457 adev->dm.freesync_module);
458
e277adc5
LSL		 459 amdgpu_dm_init_color_mod();
460
4562236b
HW		 461 if (amdgpu_dm_initialize_drm_device(adev)) {
462 DRM_ERROR(
463 "amdgpu: failed to initialize sw for display support.\n");
464 goto error;
465 }
466
467 /* Update the actual used number of crtc */
468 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
469
470 /* TODO: Add_display_info? */
471
472 /* TODO use dynamic cursor width */
ce75805e
AG		 473 adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
474 adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
4562236b
HW		 475
476 if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
477 DRM_ERROR(
478 "amdgpu: failed to initialize sw for display support.\n");
479 goto error;
480 }
481
e498eb71
NK		 482#if defined(CONFIG_DEBUG_FS)
483 if (dtn_debugfs_init(adev))
484 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
485#endif
486
f1ad2f5e 487 DRM_DEBUG_DRIVER("KMS initialized.\n");
4562236b
HW		 488
489 return 0;
490error:
491 amdgpu_dm_fini(adev);
492
59d0f396 493 return -EINVAL;
4562236b
HW		 494}
495
7578ecda 496static void amdgpu_dm_fini(struct amdgpu_device *adev)
4562236b
HW		 497{
498 amdgpu_dm_destroy_drm_device(&adev->dm);
499 /*
500 * TODO: pageflip, vlank interrupt
501 *
502 * amdgpu_dm_irq_fini(adev);
503 */
504
505 if (adev->dm.cgs_device) {
506 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
507 adev->dm.cgs_device = NULL;
508 }
509 if (adev->dm.freesync_module) {
510 mod_freesync_destroy(adev->dm.freesync_module);
511 adev->dm.freesync_module = NULL;
512 }
513 /* DC Destroy TODO: Replace destroy DAL */
21de3396 514 if (adev->dm.dc)
4562236b 515 dc_destroy(&adev->dm.dc);
674e78ac
NK		 516
517 mutex_destroy(&adev->dm.dc_lock);
518
4562236b
HW		 519 return;
520}
521
a94d5569 522static int load_dmcu_fw(struct amdgpu_device *adev)
4562236b 523{
a94d5569
DF		 524 const char *fw_name_dmcu;
525 int r;
526 const struct dmcu_firmware_header_v1_0 *hdr;
527
528 switch(adev->asic_type) {
529 case CHIP_BONAIRE:
530 case CHIP_HAWAII:
531 case CHIP_KAVERI:
532 case CHIP_KABINI:
533 case CHIP_MULLINS:
534 case CHIP_TONGA:
535 case CHIP_FIJI:
536 case CHIP_CARRIZO:
537 case CHIP_STONEY:
538 case CHIP_POLARIS11:
539 case CHIP_POLARIS10:
540 case CHIP_POLARIS12:
541 case CHIP_VEGAM:
542 case CHIP_VEGA10:
543 case CHIP_VEGA12:
544 case CHIP_VEGA20:
545 return 0;
546 case CHIP_RAVEN:
547 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
548 break;
549 default:
550 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
59d0f396 551 return -EINVAL;
a94d5569
DF		 552 }
553
554 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
555 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
556 return 0;
557 }
558
559 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
560 if (r == -ENOENT) {
561 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
562 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
563 adev->dm.fw_dmcu = NULL;
564 return 0;
565 }
566 if (r) {
567 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
568 fw_name_dmcu);
569 return r;
570 }
571
572 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
573 if (r) {
574 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
575 fw_name_dmcu);
576 release_firmware(adev->dm.fw_dmcu);
577 adev->dm.fw_dmcu = NULL;
578 return r;
579 }
580
581 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
582 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
583 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
584 adev->firmware.fw_size +=
585 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
586
587 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
588 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
589 adev->firmware.fw_size +=
590 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
591
ee6e89c0
DF		 592 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
593
a94d5569
DF		 594 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
595
4562236b
HW		 596 return 0;
597}
598
a94d5569
DF		 599static int dm_sw_init(void *handle)
600{
601 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
602
603 return load_dmcu_fw(adev);
604}
605
4562236b
HW		 606static int dm_sw_fini(void *handle)
607{
a94d5569
DF		 608 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
609
610 if(adev->dm.fw_dmcu) {
611 release_firmware(adev->dm.fw_dmcu);
612 adev->dm.fw_dmcu = NULL;
613 }
614
4562236b
HW		 615 return 0;
616}
617
7abcf6b5 618static int detect_mst_link_for_all_connectors(struct drm_device *dev)
4562236b 619{
c84dec2f 620 struct amdgpu_dm_connector *aconnector;
4562236b 621 struct drm_connector *connector;
7abcf6b5 622 int ret = 0;
4562236b
HW		 623
624 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
625
626 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
b349f76e 627 aconnector = to_amdgpu_dm_connector(connector);
30ec2b97
JFZ		 628 if (aconnector->dc_link->type == dc_connection_mst_branch &&
629 aconnector->mst_mgr.aux) {
f1ad2f5e 630 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
7abcf6b5
AG		 631 aconnector, aconnector->base.base.id);
632
633 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
634 if (ret < 0) {
635 DRM_ERROR("DM_MST: Failed to start MST\n");
636 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
637 return ret;
4562236b 638 }
7abcf6b5 639 }
4562236b
HW		 640 }
641
642 drm_modeset_unlock(&dev->mode_config.connection_mutex);
7abcf6b5
AG		 643 return ret;
644}
645
646static int dm_late_init(void *handle)
647{
42e67c3b 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7abcf6b5 649
bbf854dc
DF		 650 struct dmcu_iram_parameters params;
651 unsigned int linear_lut[16];
652 int i;
653 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
654 bool ret;
655
656 for (i = 0; i < 16; i++)
657 linear_lut[i] = 0xFFFF * i / 15;
658
659 params.set = 0;
660 params.backlight_ramping_start = 0xCCCC;
661 params.backlight_ramping_reduction = 0xCCCCCCCC;
662 params.backlight_lut_array_size = 16;
663 params.backlight_lut_array = linear_lut;
664
665 ret = dmcu_load_iram(dmcu, params);
666
667 if (!ret)
668 return -EINVAL;
669
42e67c3b 670 return detect_mst_link_for_all_connectors(adev->ddev);
4562236b
HW		 671}
672
673static void s3_handle_mst(struct drm_device *dev, bool suspend)
674{
c84dec2f 675 struct amdgpu_dm_connector *aconnector;
4562236b 676 struct drm_connector *connector;
fe7553be
LP		 677 struct drm_dp_mst_topology_mgr *mgr;
678 int ret;
679 bool need_hotplug = false;
4562236b
HW		 680
681 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
682
fe7553be
LP		 683 list_for_each_entry(connector, &dev->mode_config.connector_list,
684 head) {
685 aconnector = to_amdgpu_dm_connector(connector);
686 if (aconnector->dc_link->type != dc_connection_mst_branch ||
687 aconnector->mst_port)
688 continue;
689
690 mgr = &aconnector->mst_mgr;
691
692 if (suspend) {
693 drm_dp_mst_topology_mgr_suspend(mgr);
694 } else {
695 ret = drm_dp_mst_topology_mgr_resume(mgr);
696 if (ret < 0) {
697 drm_dp_mst_topology_mgr_set_mst(mgr, false);
698 need_hotplug = true;
699 }
700 }
4562236b
HW		 701 }
702
703 drm_modeset_unlock(&dev->mode_config.connection_mutex);
fe7553be
LP		 704
705 if (need_hotplug)
706 drm_kms_helper_hotplug_event(dev);
4562236b
HW		 707}
708
b8592b48
LL		 709/**
710 * dm_hw_init() - Initialize DC device
711 * @handle: The base driver device containing the amdpgu_dm device.
712 *
713 * Initialize the &struct amdgpu_display_manager device. This involves calling
714 * the initializers of each DM component, then populating the struct with them.
715 *
716 * Although the function implies hardware initialization, both hardware and
717 * software are initialized here. Splitting them out to their relevant init
718 * hooks is a future TODO item.
719 *
720 * Some notable things that are initialized here:
721 *
722 * - Display Core, both software and hardware
723 * - DC modules that we need (freesync and color management)
724 * - DRM software states
725 * - Interrupt sources and handlers
726 * - Vblank support
727 * - Debug FS entries, if enabled
728 */
4562236b
HW		 729static int dm_hw_init(void *handle)
730{
731 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
732 /* Create DAL display manager */
733 amdgpu_dm_init(adev);
4562236b
HW		 734 amdgpu_dm_hpd_init(adev);
735
4562236b
HW		 736 return 0;
737}
738
b8592b48
LL		 739/**
740 * dm_hw_fini() - Teardown DC device
741 * @handle: The base driver device containing the amdpgu_dm device.
742 *
743 * Teardown components within &struct amdgpu_display_manager that require
744 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
745 * were loaded. Also flush IRQ workqueues and disable them.
746 */
4562236b
HW		 747static int dm_hw_fini(void *handle)
748{
749 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
750
751 amdgpu_dm_hpd_fini(adev);
752
753 amdgpu_dm_irq_fini(adev);
21de3396 754 amdgpu_dm_fini(adev);
4562236b
HW		 755 return 0;
756}
757
758static int dm_suspend(void *handle)
759{
760 struct amdgpu_device *adev = handle;
761 struct amdgpu_display_manager *dm = &adev->dm;
762 int ret = 0;
4562236b
HW		 763
764 s3_handle_mst(adev->ddev, true);
765
4562236b
HW		 766 amdgpu_dm_irq_suspend(adev);
767
0a214e2f 768 WARN_ON(adev->dm.cached_state);
a3621485
AG		 769 adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
770
32f5062d 771 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
4562236b
HW		 772
773 return ret;
774}
775
1daf8c63
AD		 776static struct amdgpu_dm_connector *
777amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
778 struct drm_crtc *crtc)
4562236b
HW		 779{
780 uint32_t i;
c2cea706 781 struct drm_connector_state *new_con_state;
4562236b
HW		 782 struct drm_connector *connector;
783 struct drm_crtc *crtc_from_state;
784
c2cea706
LSL		 785 for_each_new_connector_in_state(state, connector, new_con_state, i) {
786 crtc_from_state = new_con_state->crtc;
4562236b
HW		 787
788 if (crtc_from_state == crtc)
c84dec2f 789 return to_amdgpu_dm_connector(connector);
4562236b
HW		 790 }
791
792 return NULL;
793}
794
fbbdadf2
BL		 795static void emulated_link_detect(struct dc_link *link)
796{
797 struct dc_sink_init_data sink_init_data = { 0 };
798 struct display_sink_capability sink_caps = { 0 };
799 enum dc_edid_status edid_status;
800 struct dc_context *dc_ctx = link->ctx;
801 struct dc_sink *sink = NULL;
802 struct dc_sink *prev_sink = NULL;
803
804 link->type = dc_connection_none;
805 prev_sink = link->local_sink;
806
807 if (prev_sink != NULL)
808 dc_sink_retain(prev_sink);
809
810 switch (link->connector_signal) {
811 case SIGNAL_TYPE_HDMI_TYPE_A: {
812 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
813 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
814 break;
815 }
816
817 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
818 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
819 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
820 break;
821 }
822
823 case SIGNAL_TYPE_DVI_DUAL_LINK: {
824 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
825 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
826 break;
827 }
828
829 case SIGNAL_TYPE_LVDS: {
830 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
831 sink_caps.signal = SIGNAL_TYPE_LVDS;
832 break;
833 }
834
835 case SIGNAL_TYPE_EDP: {
836 sink_caps.transaction_type =
837 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
838 sink_caps.signal = SIGNAL_TYPE_EDP;
839 break;
840 }
841
842 case SIGNAL_TYPE_DISPLAY_PORT: {
843 sink_caps.transaction_type =
844 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
845 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
846 break;
847 }
848
849 default:
850 DC_ERROR("Invalid connector type! signal:%d\n",
851 link->connector_signal);
852 return;
853 }
854
855 sink_init_data.link = link;
856 sink_init_data.sink_signal = sink_caps.signal;
857
858 sink = dc_sink_create(&sink_init_data);
859 if (!sink) {
860 DC_ERROR("Failed to create sink!\n");
861 return;
862 }
863
dcd5fb82 864 /* dc_sink_create returns a new reference */
fbbdadf2
BL		 865 link->local_sink = sink;
866
867 edid_status = dm_helpers_read_local_edid(
868 link->ctx,
869 link,
870 sink);
871
872 if (edid_status != EDID_OK)
873 DC_ERROR("Failed to read EDID");
874
875}
876
4562236b
HW		 877static int dm_resume(void *handle)
878{
879 struct amdgpu_device *adev = handle;
4562236b
HW		 880 struct drm_device *ddev = adev->ddev;
881 struct amdgpu_display_manager *dm = &adev->dm;
c84dec2f 882 struct amdgpu_dm_connector *aconnector;
4562236b 883 struct drm_connector *connector;
4562236b 884 struct drm_crtc *crtc;
c2cea706 885 struct drm_crtc_state *new_crtc_state;
fcb4019e
LSL		 886 struct dm_crtc_state *dm_new_crtc_state;
887 struct drm_plane *plane;
888 struct drm_plane_state *new_plane_state;
889 struct dm_plane_state *dm_new_plane_state;
fbbdadf2 890 enum dc_connection_type new_connection_type = dc_connection_none;
a3621485 891 int i;
4562236b 892
a80aa93d
ML		 893 /* power on hardware */
894 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
895
4562236b
HW		 896 /* program HPD filter */
897 dc_resume(dm->dc);
898
899 /* On resume we need to rewrite the MSTM control bits to enamble MST*/
900 s3_handle_mst(ddev, false);
901
902 /*
903 * early enable HPD Rx IRQ, should be done before set mode as short
904 * pulse interrupts are used for MST
905 */
906 amdgpu_dm_irq_resume_early(adev);
907
4562236b 908 /* Do detection*/
a80aa93d 909 list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
c84dec2f 910 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 911
912 /*
913 * this is the case when traversing through already created
914 * MST connectors, should be skipped
915 */
916 if (aconnector->mst_port)
917 continue;
918
03ea364c 919 mutex_lock(&aconnector->hpd_lock);
fbbdadf2
BL		 920 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
921 DRM_ERROR("KMS: Failed to detect connector\n");
922
923 if (aconnector->base.force && new_connection_type == dc_connection_none)
924 emulated_link_detect(aconnector->dc_link);
925 else
926 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3eb4eba4
RL		 927
928 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
929 aconnector->fake_enable = false;
930
dcd5fb82
MF		 931 if (aconnector->dc_sink)
932 dc_sink_release(aconnector->dc_sink);
4562236b
HW		 933 aconnector->dc_sink = NULL;
934 amdgpu_dm_update_connector_after_detect(aconnector);
03ea364c 935 mutex_unlock(&aconnector->hpd_lock);
4562236b
HW		 936 }
937
1f6010a9 938 /* Force mode set in atomic commit */
a80aa93d 939 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
c2cea706 940 new_crtc_state->active_changed = true;
4f346e65 941
fcb4019e
LSL		 942 /*
943 * atomic_check is expected to create the dc states. We need to release
944 * them here, since they were duplicated as part of the suspend
945 * procedure.
946 */
a80aa93d 947 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
fcb4019e
LSL		 948 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
949 if (dm_new_crtc_state->stream) {
950 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
951 dc_stream_release(dm_new_crtc_state->stream);
952 dm_new_crtc_state->stream = NULL;
953 }
954 }
955
a80aa93d 956 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
fcb4019e
LSL		 957 dm_new_plane_state = to_dm_plane_state(new_plane_state);
958 if (dm_new_plane_state->dc_state) {
959 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
960 dc_plane_state_release(dm_new_plane_state->dc_state);
961 dm_new_plane_state->dc_state = NULL;
962 }
963 }
964
2d1af6a1 965 drm_atomic_helper_resume(ddev, dm->cached_state);
4562236b 966
a80aa93d 967 dm->cached_state = NULL;
0a214e2f 968
9faa4237 969 amdgpu_dm_irq_resume_late(adev);
4562236b 970
2d1af6a1 971 return 0;
4562236b
HW		 972}
973
b8592b48
LL		 974/**
975 * DOC: DM Lifecycle
976 *
977 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
978 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
979 * the base driver's device list to be initialized and torn down accordingly.
980 *
981 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
982 */
983
4562236b
HW		 984static const struct amd_ip_funcs amdgpu_dm_funcs = {
985 .name = "dm",
986 .early_init = dm_early_init,
7abcf6b5 987 .late_init = dm_late_init,
4562236b
HW		 988 .sw_init = dm_sw_init,
989 .sw_fini = dm_sw_fini,
990 .hw_init = dm_hw_init,
991 .hw_fini = dm_hw_fini,
992 .suspend = dm_suspend,
993 .resume = dm_resume,
994 .is_idle = dm_is_idle,
995 .wait_for_idle = dm_wait_for_idle,
996 .check_soft_reset = dm_check_soft_reset,
997 .soft_reset = dm_soft_reset,
998 .set_clockgating_state = dm_set_clockgating_state,
999 .set_powergating_state = dm_set_powergating_state,
1000};
1001
1002const struct amdgpu_ip_block_version dm_ip_block =
1003{
1004 .type = AMD_IP_BLOCK_TYPE_DCE,
1005 .major = 1,
1006 .minor = 0,
1007 .rev = 0,
1008 .funcs = &amdgpu_dm_funcs,
1009};
1010
ca3268c4 1011
b8592b48
LL		 1012/**
1013 * DOC: atomic
1014 *
1015 * *WIP*
1016 */
0a323b84 1017
b3663f70 1018static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
4d4772f6 1019 .fb_create = amdgpu_display_user_framebuffer_create,
366c1baa 1020 .output_poll_changed = drm_fb_helper_output_poll_changed,
4562236b 1021 .atomic_check = amdgpu_dm_atomic_check,
da5c47f6 1022 .atomic_commit = amdgpu_dm_atomic_commit,
54f5499a
AG		 1023};
1024
1025static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1026 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
4562236b
HW		 1027};
1028
7578ecda 1029static void
3ee6b26b 1030amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1031{
1032 struct drm_connector *connector = &aconnector->base;
1033 struct drm_device *dev = connector->dev;
b73a22d3 1034 struct dc_sink *sink;
4562236b
HW		 1035
1036 /* MST handled by drm_mst framework */
1037 if (aconnector->mst_mgr.mst_state == true)
1038 return;
1039
1040
1041 sink = aconnector->dc_link->local_sink;
dcd5fb82
MF		 1042 if (sink)
1043 dc_sink_retain(sink);
4562236b 1044
1f6010a9
DF		 1045 /*
1046 * Edid mgmt connector gets first update only in mode_valid hook and then
4562236b 1047 * the connector sink is set to either fake or physical sink depends on link status.
1f6010a9 1048 * Skip if already done during boot.
4562236b
HW		 1049 */
1050 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1051 && aconnector->dc_em_sink) {
1052
1f6010a9
DF		 1053 /*
1054 * For S3 resume with headless use eml_sink to fake stream
1055 * because on resume connector->sink is set to NULL
4562236b
HW		 1056 */
1057 mutex_lock(&dev->mode_config.mutex);
1058
1059 if (sink) {
922aa1e1 1060 if (aconnector->dc_sink) {
98e6436d 1061 amdgpu_dm_update_freesync_caps(connector, NULL);
1f6010a9
DF		 1062 /*
1063 * retain and release below are used to
1064 * bump up refcount for sink because the link doesn't point
1065 * to it anymore after disconnect, so on next crtc to connector
922aa1e1
AG		 1066 * reshuffle by UMD we will get into unwanted dc_sink release
1067 */
dcd5fb82 1068 dc_sink_release(aconnector->dc_sink);
922aa1e1 1069 }
4562236b 1070 aconnector->dc_sink = sink;
dcd5fb82 1071 dc_sink_retain(aconnector->dc_sink);
98e6436d
AK		 1072 amdgpu_dm_update_freesync_caps(connector,
1073 aconnector->edid);
4562236b 1074 } else {
98e6436d 1075 amdgpu_dm_update_freesync_caps(connector, NULL);
dcd5fb82 1076 if (!aconnector->dc_sink) {
4562236b 1077 aconnector->dc_sink = aconnector->dc_em_sink;
922aa1e1 1078 dc_sink_retain(aconnector->dc_sink);
dcd5fb82 1079 }
4562236b
HW		 1080 }
1081
1082 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1083
1084 if (sink)
1085 dc_sink_release(sink);
4562236b
HW		 1086 return;
1087 }
1088
1089 /*
1090 * TODO: temporary guard to look for proper fix
1091 * if this sink is MST sink, we should not do anything
1092 */
dcd5fb82
MF		 1093 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1094 dc_sink_release(sink);
4562236b 1095 return;
dcd5fb82 1096 }
4562236b
HW		 1097
1098 if (aconnector->dc_sink == sink) {
1f6010a9
DF		 1099 /*
1100 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1101 * Do nothing!!
1102 */
f1ad2f5e 1103 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
4562236b 1104 aconnector->connector_id);
dcd5fb82
MF		 1105 if (sink)
1106 dc_sink_release(sink);
4562236b
HW		 1107 return;
1108 }
1109
f1ad2f5e 1110 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
4562236b
HW		 1111 aconnector->connector_id, aconnector->dc_sink, sink);
1112
1113 mutex_lock(&dev->mode_config.mutex);
1114
1f6010a9
DF		 1115 /*
1116 * 1. Update status of the drm connector
1117 * 2. Send an event and let userspace tell us what to do
1118 */
4562236b 1119 if (sink) {
1f6010a9
DF		 1120 /*
1121 * TODO: check if we still need the S3 mode update workaround.
1122 * If yes, put it here.
1123 */
4562236b 1124 if (aconnector->dc_sink)
98e6436d 1125 amdgpu_dm_update_freesync_caps(connector, NULL);
4562236b
HW		 1126
1127 aconnector->dc_sink = sink;
dcd5fb82 1128 dc_sink_retain(aconnector->dc_sink);
900b3cb1 1129 if (sink->dc_edid.length == 0) {
4562236b 1130 aconnector->edid = NULL;
e86e8947 1131 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
900b3cb1 1132 } else {
4562236b
HW		 1133 aconnector->edid =
1134 (struct edid *) sink->dc_edid.raw_edid;
1135
1136
c555f023 1137 drm_connector_update_edid_property(connector,
4562236b 1138 aconnector->edid);
e86e8947
HV		 1139 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1140 aconnector->edid);
4562236b 1141 }
98e6436d 1142 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
4562236b
HW		 1143
1144 } else {
e86e8947 1145 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
98e6436d 1146 amdgpu_dm_update_freesync_caps(connector, NULL);
c555f023 1147 drm_connector_update_edid_property(connector, NULL);
4562236b 1148 aconnector->num_modes = 0;
dcd5fb82 1149 dc_sink_release(aconnector->dc_sink);
4562236b 1150 aconnector->dc_sink = NULL;
5326c452 1151 aconnector->edid = NULL;
4562236b
HW		 1152 }
1153
1154 mutex_unlock(&dev->mode_config.mutex);
dcd5fb82
MF		 1155
1156 if (sink)
1157 dc_sink_release(sink);
4562236b
HW		 1158}
1159
1160static void handle_hpd_irq(void *param)
1161{
c84dec2f 1162 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1163 struct drm_connector *connector = &aconnector->base;
1164 struct drm_device *dev = connector->dev;
fbbdadf2 1165 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1166
1f6010a9
DF		 1167 /*
1168 * In case of failure or MST no need to update connector status or notify the OS
1169 * since (for MST case) MST does this in its own context.
4562236b
HW		 1170 */
1171 mutex_lock(&aconnector->hpd_lock);
2e0ac3d6
HW		 1172
1173 if (aconnector->fake_enable)
1174 aconnector->fake_enable = false;
1175
fbbdadf2
BL		 1176 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1177 DRM_ERROR("KMS: Failed to detect connector\n");
1178
1179 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1180 emulated_link_detect(aconnector->dc_link);
1181
1182
1183 drm_modeset_lock_all(dev);
1184 dm_restore_drm_connector_state(dev, connector);
1185 drm_modeset_unlock_all(dev);
1186
1187 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1188 drm_kms_helper_hotplug_event(dev);
1189
1190 } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
4562236b
HW		 1191 amdgpu_dm_update_connector_after_detect(aconnector);
1192
1193
1194 drm_modeset_lock_all(dev);
1195 dm_restore_drm_connector_state(dev, connector);
1196 drm_modeset_unlock_all(dev);
1197
1198 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1199 drm_kms_helper_hotplug_event(dev);
1200 }
1201 mutex_unlock(&aconnector->hpd_lock);
1202
1203}
1204
c84dec2f 1205static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
4562236b
HW		 1206{
1207 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1208 uint8_t dret;
1209 bool new_irq_handled = false;
1210 int dpcd_addr;
1211 int dpcd_bytes_to_read;
1212
1213 const int max_process_count = 30;
1214 int process_count = 0;
1215
1216 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1217
1218 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1219 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1220 /* DPCD 0x200 - 0x201 for downstream IRQ */
1221 dpcd_addr = DP_SINK_COUNT;
1222 } else {
1223 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1224 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1225 dpcd_addr = DP_SINK_COUNT_ESI;
1226 }
1227
1228 dret = drm_dp_dpcd_read(
1229 &aconnector->dm_dp_aux.aux,
1230 dpcd_addr,
1231 esi,
1232 dpcd_bytes_to_read);
1233
1234 while (dret == dpcd_bytes_to_read &&
1235 process_count < max_process_count) {
1236 uint8_t retry;
1237 dret = 0;
1238
1239 process_count++;
1240
f1ad2f5e 1241 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4562236b
HW		 1242 /* handle HPD short pulse irq */
1243 if (aconnector->mst_mgr.mst_state)
1244 drm_dp_mst_hpd_irq(
1245 &aconnector->mst_mgr,
1246 esi,
1247 &new_irq_handled);
4562236b
HW		 1248
1249 if (new_irq_handled) {
1250 /* ACK at DPCD to notify down stream */
1251 const int ack_dpcd_bytes_to_write =
1252 dpcd_bytes_to_read - 1;
1253
1254 for (retry = 0; retry < 3; retry++) {
1255 uint8_t wret;
1256
1257 wret = drm_dp_dpcd_write(
1258 &aconnector->dm_dp_aux.aux,
1259 dpcd_addr + 1,
1260 &esi[1],
1261 ack_dpcd_bytes_to_write);
1262 if (wret == ack_dpcd_bytes_to_write)
1263 break;
1264 }
1265
1f6010a9 1266 /* check if there is new irq to be handled */
4562236b
HW		 1267 dret = drm_dp_dpcd_read(
1268 &aconnector->dm_dp_aux.aux,
1269 dpcd_addr,
1270 esi,
1271 dpcd_bytes_to_read);
1272
1273 new_irq_handled = false;
d4a6e8a9 1274 } else {
4562236b 1275 break;
d4a6e8a9 1276 }
4562236b
HW		 1277 }
1278
1279 if (process_count == max_process_count)
f1ad2f5e 1280 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
4562236b
HW		 1281}
1282
1283static void handle_hpd_rx_irq(void *param)
1284{
c84dec2f 1285 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
4562236b
HW		 1286 struct drm_connector *connector = &aconnector->base;
1287 struct drm_device *dev = connector->dev;
53cbf65c 1288 struct dc_link *dc_link = aconnector->dc_link;
4562236b 1289 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
fbbdadf2 1290 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b 1291
1f6010a9
DF		 1292 /*
1293 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
4562236b
HW		 1294 * conflict, after implement i2c helper, this mutex should be
1295 * retired.
1296 */
53cbf65c 1297 if (dc_link->type != dc_connection_mst_branch)
4562236b
HW		 1298 mutex_lock(&aconnector->hpd_lock);
1299
4e18814e 1300 if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
4562236b
HW		 1301 !is_mst_root_connector) {
1302 /* Downstream Port status changed. */
fbbdadf2
BL		 1303 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1304 DRM_ERROR("KMS: Failed to detect connector\n");
1305
1306 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1307 emulated_link_detect(dc_link);
1308
1309 if (aconnector->fake_enable)
1310 aconnector->fake_enable = false;
1311
1312 amdgpu_dm_update_connector_after_detect(aconnector);
1313
1314
1315 drm_modeset_lock_all(dev);
1316 dm_restore_drm_connector_state(dev, connector);
1317 drm_modeset_unlock_all(dev);
1318
1319 drm_kms_helper_hotplug_event(dev);
1320 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
88ac3dda
RL		 1321
1322 if (aconnector->fake_enable)
1323 aconnector->fake_enable = false;
1324
4562236b
HW		 1325 amdgpu_dm_update_connector_after_detect(aconnector);
1326
1327
1328 drm_modeset_lock_all(dev);
1329 dm_restore_drm_connector_state(dev, connector);
1330 drm_modeset_unlock_all(dev);
1331
1332 drm_kms_helper_hotplug_event(dev);
1333 }
1334 }
1335 if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
53cbf65c 1336 (dc_link->type == dc_connection_mst_branch))
4562236b
HW		 1337 dm_handle_hpd_rx_irq(aconnector);
1338
e86e8947
HV		 1339 if (dc_link->type != dc_connection_mst_branch) {
1340 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
4562236b 1341 mutex_unlock(&aconnector->hpd_lock);
e86e8947 1342 }
4562236b
HW		 1343}
1344
1345static void register_hpd_handlers(struct amdgpu_device *adev)
1346{
1347 struct drm_device *dev = adev->ddev;
1348 struct drm_connector *connector;
c84dec2f 1349 struct amdgpu_dm_connector *aconnector;
4562236b
HW		 1350 const struct dc_link *dc_link;
1351 struct dc_interrupt_params int_params = {0};
1352
1353 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1354 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1355
1356 list_for_each_entry(connector,
1357 &dev->mode_config.connector_list, head) {
1358
c84dec2f 1359 aconnector = to_amdgpu_dm_connector(connector);
4562236b
HW		 1360 dc_link = aconnector->dc_link;
1361
1362 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1363 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1364 int_params.irq_source = dc_link->irq_source_hpd;
1365
1366 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1367 handle_hpd_irq,
1368 (void *) aconnector);
1369 }
1370
1371 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1372
1373 /* Also register for DP short pulse (hpd_rx). */
1374 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1375 int_params.irq_source = dc_link->irq_source_hpd_rx;
1376
1377 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1378 handle_hpd_rx_irq,
1379 (void *) aconnector);
1380 }
1381 }
1382}
1383
1384/* Register IRQ sources and initialize IRQ callbacks */
1385static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1386{
1387 struct dc *dc = adev->dm.dc;
1388 struct common_irq_params *c_irq_params;
1389 struct dc_interrupt_params int_params = {0};
1390 int r;
1391 int i;
1ffdeca6 1392 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2c8ad2d5 1393
ff5ef992 1394 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 1395 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 1396 adev->asic_type == CHIP_VEGA20 ||
ff5ef992 1397 adev->asic_type == CHIP_RAVEN)
3760f76c 1398 client_id = SOC15_IH_CLIENTID_DCE;
4562236b
HW		 1399
1400 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1401 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1402
1f6010a9
DF		 1403 /*
1404 * Actions of amdgpu_irq_add_id():
4562236b
HW		 1405 * 1. Register a set() function with base driver.
1406 * Base driver will call set() function to enable/disable an
1407 * interrupt in DC hardware.
1408 * 2. Register amdgpu_dm_irq_handler().
1409 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1410 * coming from DC hardware.
1411 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1412 * for acknowledging and handling. */
1413
b57de80a 1414 /* Use VBLANK interrupt */
e9029155 1415 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2c8ad2d5 1416 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
4562236b
HW		 1417 if (r) {
1418 DRM_ERROR("Failed to add crtc irq id!\n");
1419 return r;
1420 }
1421
1422 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1423 int_params.irq_source =
3d761e79 1424 dc_interrupt_to_irq_source(dc, i, 0);
4562236b 1425
b57de80a 1426 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
4562236b
HW		 1427
1428 c_irq_params->adev = adev;
1429 c_irq_params->irq_src = int_params.irq_source;
1430
1431 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1432 dm_crtc_high_irq, c_irq_params);
1433 }
1434
3d761e79 1435 /* Use GRPH_PFLIP interrupt */
4562236b
HW		 1436 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1437 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2c8ad2d5 1438 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
4562236b
HW		 1439 if (r) {
1440 DRM_ERROR("Failed to add page flip irq id!\n");
1441 return r;
1442 }
1443
1444 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1445 int_params.irq_source =
1446 dc_interrupt_to_irq_source(dc, i, 0);
1447
1448 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1449
1450 c_irq_params->adev = adev;
1451 c_irq_params->irq_src = int_params.irq_source;
1452
1453 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1454 dm_pflip_high_irq, c_irq_params);
1455
1456 }
1457
1458 /* HPD */
2c8ad2d5
AD		 1459 r = amdgpu_irq_add_id(adev, client_id,
1460 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
4562236b
HW		 1461 if (r) {
1462 DRM_ERROR("Failed to add hpd irq id!\n");
1463 return r;
1464 }
1465
1466 register_hpd_handlers(adev);
1467
1468 return 0;
1469}
1470
ff5ef992
AD		 1471#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1472/* Register IRQ sources and initialize IRQ callbacks */
1473static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1474{
1475 struct dc *dc = adev->dm.dc;
1476 struct common_irq_params *c_irq_params;
1477 struct dc_interrupt_params int_params = {0};
1478 int r;
1479 int i;
1480
1481 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1482 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1483
1f6010a9
DF		 1484 /*
1485 * Actions of amdgpu_irq_add_id():
ff5ef992
AD		 1486 * 1. Register a set() function with base driver.
1487 * Base driver will call set() function to enable/disable an
1488 * interrupt in DC hardware.
1489 * 2. Register amdgpu_dm_irq_handler().
1490 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1491 * coming from DC hardware.
1492 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1493 * for acknowledging and handling.
1f6010a9 1494 */
ff5ef992
AD		 1495
1496 /* Use VSTARTUP interrupt */
1497 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1498 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1499 i++) {
3760f76c 1500 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
ff5ef992
AD		 1501
1502 if (r) {
1503 DRM_ERROR("Failed to add crtc irq id!\n");
1504 return r;
1505 }
1506
1507 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1508 int_params.irq_source =
1509 dc_interrupt_to_irq_source(dc, i, 0);
1510
1511 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1512
1513 c_irq_params->adev = adev;
1514 c_irq_params->irq_src = int_params.irq_source;
1515
1516 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1517 dm_crtc_high_irq, c_irq_params);
1518 }
1519
1520 /* Use GRPH_PFLIP interrupt */
1521 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1522 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1523 i++) {
3760f76c 1524 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
ff5ef992
AD		 1525 if (r) {
1526 DRM_ERROR("Failed to add page flip irq id!\n");
1527 return r;
1528 }
1529
1530 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1531 int_params.irq_source =
1532 dc_interrupt_to_irq_source(dc, i, 0);
1533
1534 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1535
1536 c_irq_params->adev = adev;
1537 c_irq_params->irq_src = int_params.irq_source;
1538
1539 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1540 dm_pflip_high_irq, c_irq_params);
1541
1542 }
1543
1544 /* HPD */
3760f76c 1545 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
ff5ef992
AD		 1546 &adev->hpd_irq);
1547 if (r) {
1548 DRM_ERROR("Failed to add hpd irq id!\n");
1549 return r;
1550 }
1551
1552 register_hpd_handlers(adev);
1553
1554 return 0;
1555}
1556#endif
1557
eb3dc897
NK		 1558/*
1559 * Acquires the lock for the atomic state object and returns
1560 * the new atomic state.
1561 *
1562 * This should only be called during atomic check.
1563 */
1564static int dm_atomic_get_state(struct drm_atomic_state *state,
1565 struct dm_atomic_state **dm_state)
1566{
1567 struct drm_device *dev = state->dev;
1568 struct amdgpu_device *adev = dev->dev_private;
1569 struct amdgpu_display_manager *dm = &adev->dm;
1570 struct drm_private_state *priv_state;
1571 int ret;
1572
1573 if (*dm_state)
1574 return 0;
1575
1576 ret = drm_modeset_lock(&dm->atomic_obj_lock, state->acquire_ctx);
1577 if (ret)
1578 return ret;
1579
1580 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1581 if (IS_ERR(priv_state))
1582 return PTR_ERR(priv_state);
1583
1584 *dm_state = to_dm_atomic_state(priv_state);
1585
1586 return 0;
1587}
1588
1589struct dm_atomic_state *
1590dm_atomic_get_new_state(struct drm_atomic_state *state)
1591{
1592 struct drm_device *dev = state->dev;
1593 struct amdgpu_device *adev = dev->dev_private;
1594 struct amdgpu_display_manager *dm = &adev->dm;
1595 struct drm_private_obj *obj;
1596 struct drm_private_state *new_obj_state;
1597 int i;
1598
1599 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1600 if (obj->funcs == dm->atomic_obj.funcs)
1601 return to_dm_atomic_state(new_obj_state);
1602 }
1603
1604 return NULL;
1605}
1606
1607struct dm_atomic_state *
1608dm_atomic_get_old_state(struct drm_atomic_state *state)
1609{
1610 struct drm_device *dev = state->dev;
1611 struct amdgpu_device *adev = dev->dev_private;
1612 struct amdgpu_display_manager *dm = &adev->dm;
1613 struct drm_private_obj *obj;
1614 struct drm_private_state *old_obj_state;
1615 int i;
1616
1617 for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1618 if (obj->funcs == dm->atomic_obj.funcs)
1619 return to_dm_atomic_state(old_obj_state);
1620 }
1621
1622 return NULL;
1623}
1624
1625static struct drm_private_state *
1626dm_atomic_duplicate_state(struct drm_private_obj *obj)
1627{
1628 struct dm_atomic_state *old_state, *new_state;
1629
1630 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1631 if (!new_state)
1632 return NULL;
1633
1634 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1635
1636 new_state->context = dc_create_state();
1637 if (!new_state->context) {
1638 kfree(new_state);
1639 return NULL;
1640 }
1641
1642 old_state = to_dm_atomic_state(obj->state);
1643 if (old_state && old_state->context)
1644 dc_resource_state_copy_construct(old_state->context,
1645 new_state->context);
1646
1647 return &new_state->base;
1648}
1649
1650static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1651 struct drm_private_state *state)
1652{
1653 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1654
1655 if (dm_state && dm_state->context)
1656 dc_release_state(dm_state->context);
1657
1658 kfree(dm_state);
1659}
1660
1661static struct drm_private_state_funcs dm_atomic_state_funcs = {
1662 .atomic_duplicate_state = dm_atomic_duplicate_state,
1663 .atomic_destroy_state = dm_atomic_destroy_state,
1664};
1665
4562236b
HW		 1666static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1667{
eb3dc897 1668 struct dm_atomic_state *state;
4562236b
HW		 1669 int r;
1670
1671 adev->mode_info.mode_config_initialized = true;
1672
4562236b 1673 adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
54f5499a 1674 adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
4562236b
HW		 1675
1676 adev->ddev->mode_config.max_width = 16384;
1677 adev->ddev->mode_config.max_height = 16384;
1678
1679 adev->ddev->mode_config.preferred_depth = 24;
1680 adev->ddev->mode_config.prefer_shadow = 1;
1f6010a9 1681 /* indicates support for immediate flip */
4562236b
HW		 1682 adev->ddev->mode_config.async_page_flip = true;
1683
770d13b1 1684 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
4562236b 1685
eb3dc897
NK		 1686 drm_modeset_lock_init(&adev->dm.atomic_obj_lock);
1687
1688 state = kzalloc(sizeof(*state), GFP_KERNEL);
1689 if (!state)
1690 return -ENOMEM;
1691
1692 state->context = dc_create_state();
1693 if (!state->context) {
1694 kfree(state);
1695 return -ENOMEM;
1696 }
1697
1698 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1699
8c1a765b
DA		 1700 drm_atomic_private_obj_init(adev->ddev,
1701 &adev->dm.atomic_obj,
eb3dc897
NK		 1702 &state->base,
1703 &dm_atomic_state_funcs);
1704
3dc9b1ce 1705 r = amdgpu_display_modeset_create_props(adev);
4562236b
HW		 1706 if (r)
1707 return r;
1708
1709 return 0;
1710}
1711
206bbafe
DF		 1712#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1713#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1714
4562236b
HW		 1715#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1716 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1717
206bbafe
DF		 1718static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1719{
1720#if defined(CONFIG_ACPI)
1721 struct amdgpu_dm_backlight_caps caps;
1722
1723 if (dm->backlight_caps.caps_valid)
1724 return;
1725
1726 amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1727 if (caps.caps_valid) {
1728 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1729 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1730 dm->backlight_caps.caps_valid = true;
1731 } else {
1732 dm->backlight_caps.min_input_signal =
1733 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1734 dm->backlight_caps.max_input_signal =
1735 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1736 }
1737#else
8bcbc9ef
DF		 1738 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1739 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
206bbafe
DF		 1740#endif
1741}
1742
4562236b
HW		 1743static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1744{
1745 struct amdgpu_display_manager *dm = bl_get_data(bd);
206bbafe
DF		 1746 struct amdgpu_dm_backlight_caps caps;
1747 uint32_t brightness = bd->props.brightness;
4562236b 1748
206bbafe
DF		 1749 amdgpu_dm_update_backlight_caps(dm);
1750 caps = dm->backlight_caps;
0cafc82f 1751 /*
206bbafe
DF		 1752 * The brightness input is in the range 0-255
1753 * It needs to be rescaled to be between the
1754 * requested min and max input signal
1755 *
1756 * It also needs to be scaled up by 0x101 to
1757 * match the DC interface which has a range of
1758 * 0 to 0xffff
0cafc82f 1759 */
206bbafe
DF		 1760 brightness =
1761 brightness
1762 * 0x101
1763 * (caps.max_input_signal - caps.min_input_signal)
1764 / AMDGPU_MAX_BL_LEVEL
1765 + caps.min_input_signal * 0x101;
4562236b
HW		 1766
1767 if (dc_link_set_backlight_level(dm->backlight_link,
923fe495 1768 brightness, 0))
4562236b
HW		 1769 return 0;
1770 else
1771 return 1;
1772}
1773
1774static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1775{
620a0d27
DF		 1776 struct amdgpu_display_manager *dm = bl_get_data(bd);
1777 int ret = dc_link_get_backlight_level(dm->backlight_link);
1778
1779 if (ret == DC_ERROR_UNEXPECTED)
1780 return bd->props.brightness;
1781 return ret;
4562236b
HW		 1782}
1783
1784static const struct backlight_ops amdgpu_dm_backlight_ops = {
1785 .get_brightness = amdgpu_dm_backlight_get_brightness,
1786 .update_status = amdgpu_dm_backlight_update_status,
1787};
1788
7578ecda
AD		 1789static void
1790amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4562236b
HW		 1791{
1792 char bl_name[16];
1793 struct backlight_properties props = { 0 };
1794
206bbafe
DF		 1795 amdgpu_dm_update_backlight_caps(dm);
1796
4562236b 1797 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
53a53f86 1798 props.brightness = AMDGPU_MAX_BL_LEVEL;
4562236b
HW		 1799 props.type = BACKLIGHT_RAW;
1800
1801 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1802 dm->adev->ddev->primary->index);
1803
1804 dm->backlight_dev = backlight_device_register(bl_name,
1805 dm->adev->ddev->dev,
1806 dm,
1807 &amdgpu_dm_backlight_ops,
1808 &props);
1809
74baea42 1810 if (IS_ERR(dm->backlight_dev))
4562236b
HW		 1811 DRM_ERROR("DM: Backlight registration failed!\n");
1812 else
f1ad2f5e 1813 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4562236b
HW		 1814}
1815
1816#endif
1817
df534fff 1818static int initialize_plane(struct amdgpu_display_manager *dm,
b2fddb13
NK		 1819 struct amdgpu_mode_info *mode_info, int plane_id,
1820 enum drm_plane_type plane_type)
df534fff 1821{
f180b4bc 1822 struct drm_plane *plane;
df534fff
S		 1823 unsigned long possible_crtcs;
1824 int ret = 0;
1825
f180b4bc 1826 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
df534fff
S		 1827 mode_info->planes[plane_id] = plane;
1828
1829 if (!plane) {
1830 DRM_ERROR("KMS: Failed to allocate plane\n");
1831 return -ENOMEM;
1832 }
b2fddb13 1833 plane->type = plane_type;
df534fff
S		 1834
1835 /*
b2fddb13
NK		 1836 * HACK: IGT tests expect that the primary plane for a CRTC
1837 * can only have one possible CRTC. Only expose support for
1838 * any CRTC if they're not going to be used as a primary plane
1839 * for a CRTC - like overlay or underlay planes.
df534fff
S		 1840 */
1841 possible_crtcs = 1 << plane_id;
1842 if (plane_id >= dm->dc->caps.max_streams)
1843 possible_crtcs = 0xff;
1844
1845 ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);
1846
1847 if (ret) {
1848 DRM_ERROR("KMS: Failed to initialize plane\n");
1849 return ret;
1850 }
1851
1852 return ret;
1853}
1854
89fc8d4e
HW		 1855
1856static void register_backlight_device(struct amdgpu_display_manager *dm,
1857 struct dc_link *link)
1858{
1859#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1860 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1861
1862 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
1863 link->type != dc_connection_none) {
1f6010a9
DF		 1864 /*
1865 * Event if registration failed, we should continue with
89fc8d4e
HW		 1866 * DM initialization because not having a backlight control
1867 * is better then a black screen.
1868 */
1869 amdgpu_dm_register_backlight_device(dm);
1870
1871 if (dm->backlight_dev)
1872 dm->backlight_link = link;
1873 }
1874#endif
1875}
1876
1877
1f6010a9
DF		 1878/*
1879 * In this architecture, the association
4562236b
HW		 1880 * connector -> encoder -> crtc
1881 * id not really requried. The crtc and connector will hold the
1882 * display_index as an abstraction to use with DAL component
1883 *
1884 * Returns 0 on success
1885 */
7578ecda 1886static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4562236b
HW		 1887{
1888 struct amdgpu_display_manager *dm = &adev->dm;
df534fff 1889 int32_t i;
c84dec2f 1890 struct amdgpu_dm_connector *aconnector = NULL;
f2a0f5e6 1891 struct amdgpu_encoder *aencoder = NULL;
d4e13b0d 1892 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4562236b 1893 uint32_t link_cnt;
0d579c7e 1894 int32_t overlay_planes, primary_planes, total_planes;
fbbdadf2 1895 enum dc_connection_type new_connection_type = dc_connection_none;
4562236b
HW		 1896
1897 link_cnt = dm->dc->caps.max_links;
4562236b
HW		 1898 if (amdgpu_dm_mode_config_init(dm->adev)) {
1899 DRM_ERROR("DM: Failed to initialize mode config\n");
59d0f396 1900 return -EINVAL;
4562236b
HW		 1901 }
1902
0d579c7e
NK		 1903 /*
1904 * Determine the number of overlay planes supported.
1905 * Only support DCN for now, and cap so we don't encourage
1906 * userspace to use up all the planes.
1907 */
1908 overlay_planes = 0;
1909
1910 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
1911 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
1912
1913 if (plane->type == DC_PLANE_TYPE_DCN_UNIVERSAL &&
1914 plane->blends_with_above && plane->blends_with_below &&
1915 plane->supports_argb8888)
1916 overlay_planes += 1;
1917 }
1918
1919 overlay_planes = min(overlay_planes, 1);
1920
b2fddb13
NK		 1921 /* There is one primary plane per CRTC */
1922 primary_planes = dm->dc->caps.max_streams;
0d579c7e
NK		 1923
1924 total_planes = primary_planes + overlay_planes;
1925 ASSERT(total_planes < AMDGPU_MAX_PLANES);
efa6a8b7 1926
b2fddb13
NK		 1927 /*
1928 * Initialize primary planes, implicit planes for legacy IOCTLS.
1929 * Order is reversed to match iteration order in atomic check.
1930 */
1931 for (i = (primary_planes - 1); i >= 0; i--) {
1932 if (initialize_plane(dm, mode_info, i,
1933 DRM_PLANE_TYPE_PRIMARY)) {
df534fff 1934 DRM_ERROR("KMS: Failed to initialize primary plane\n");
cd8a2ae8 1935 goto fail;
d4e13b0d
AD		 1936 }
1937 }
4562236b 1938
0d579c7e
NK		 1939 /*
1940 * Initialize overlay planes, index starting after primary planes.
1941 * These planes have a higher DRM index than the primary planes since
1942 * they should be considered as having a higher z-order.
1943 * Order is reversed to match iteration order in atomic check.
1944 */
1945 for (i = (overlay_planes - 1); i >= 0; i--) {
1946 if (initialize_plane(dm, mode_info, primary_planes + i,
1947 DRM_PLANE_TYPE_OVERLAY)) {
1948 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
1949 goto fail;
1950 }
1951 }
1952
d4e13b0d 1953 for (i = 0; i < dm->dc->caps.max_streams; i++)
f180b4bc 1954 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4562236b 1955 DRM_ERROR("KMS: Failed to initialize crtc\n");
cd8a2ae8 1956 goto fail;
4562236b 1957 }
4562236b 1958
ab2541b6 1959 dm->display_indexes_num = dm->dc->caps.max_streams;
4562236b
HW		 1960
1961 /* loops over all connectors on the board */
1962 for (i = 0; i < link_cnt; i++) {
89fc8d4e 1963 struct dc_link *link = NULL;
4562236b
HW		 1964
1965 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1966 DRM_ERROR(
1967 "KMS: Cannot support more than %d display indexes\n",
1968 AMDGPU_DM_MAX_DISPLAY_INDEX);
1969 continue;
1970 }
1971
1972 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1973 if (!aconnector)
cd8a2ae8 1974 goto fail;
4562236b
HW		 1975
1976 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
8440c304 1977 if (!aencoder)
cd8a2ae8 1978 goto fail;
4562236b
HW		 1979
1980 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1981 DRM_ERROR("KMS: Failed to initialize encoder\n");
cd8a2ae8 1982 goto fail;
4562236b
HW		 1983 }
1984
1985 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1986 DRM_ERROR("KMS: Failed to initialize connector\n");
cd8a2ae8 1987 goto fail;
4562236b
HW		 1988 }
1989
89fc8d4e
HW		 1990 link = dc_get_link_at_index(dm->dc, i);
1991
fbbdadf2
BL		 1992 if (!dc_link_detect_sink(link, &new_connection_type))
1993 DRM_ERROR("KMS: Failed to detect connector\n");
1994
1995 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1996 emulated_link_detect(link);
1997 amdgpu_dm_update_connector_after_detect(aconnector);
1998
1999 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
4562236b 2000 amdgpu_dm_update_connector_after_detect(aconnector);
89fc8d4e
HW		 2001 register_backlight_device(dm, link);
2002 }
2003
2004
4562236b
HW		 2005 }
2006
2007 /* Software is initialized. Now we can register interrupt handlers. */
2008 switch (adev->asic_type) {
2009 case CHIP_BONAIRE:
2010 case CHIP_HAWAII:
cd4b356f
AD		 2011 case CHIP_KAVERI:
2012 case CHIP_KABINI:
2013 case CHIP_MULLINS:
4562236b
HW		 2014 case CHIP_TONGA:
2015 case CHIP_FIJI:
2016 case CHIP_CARRIZO:
2017 case CHIP_STONEY:
2018 case CHIP_POLARIS11:
2019 case CHIP_POLARIS10:
b264d345 2020 case CHIP_POLARIS12:
7737de91 2021 case CHIP_VEGAM:
2c8ad2d5 2022 case CHIP_VEGA10:
2325ff30 2023 case CHIP_VEGA12:
1fe6bf2f 2024 case CHIP_VEGA20:
4562236b
HW		 2025 if (dce110_register_irq_handlers(dm->adev)) {
2026 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2027 goto fail;
4562236b
HW		 2028 }
2029 break;
ff5ef992
AD		 2030#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2031 case CHIP_RAVEN:
2032 if (dcn10_register_irq_handlers(dm->adev)) {
2033 DRM_ERROR("DM: Failed to initialize IRQ\n");
cd8a2ae8 2034 goto fail;
ff5ef992
AD		 2035 }
2036 break;
2037#endif
4562236b 2038 default:
e63f8673 2039 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
cd8a2ae8 2040 goto fail;
4562236b
HW		 2041 }
2042
1bc460a4
HW		 2043 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2044 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2045
4562236b 2046 return 0;
cd8a2ae8 2047fail:
4562236b 2048 kfree(aencoder);
4562236b 2049 kfree(aconnector);
b2fddb13 2050 for (i = 0; i < primary_planes; i++)
d4e13b0d 2051 kfree(mode_info->planes[i]);
59d0f396 2052 return -EINVAL;
4562236b
HW		 2053}
2054
7578ecda 2055static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4562236b
HW		 2056{
2057 drm_mode_config_cleanup(dm->ddev);
eb3dc897 2058 drm_atomic_private_obj_fini(&dm->atomic_obj);
4562236b
HW		 2059 return;
2060}
2061
2062/******************************************************************************
2063 * amdgpu_display_funcs functions
2064 *****************************************************************************/
2065
1f6010a9 2066/*
4562236b
HW		 2067 * dm_bandwidth_update - program display watermarks
2068 *
2069 * @adev: amdgpu_device pointer
2070 *
2071 * Calculate and program the display watermarks and line buffer allocation.
2072 */
2073static void dm_bandwidth_update(struct amdgpu_device *adev)
2074{
49c07a99 2075 /* TODO: implement later */
4562236b
HW		 2076}
2077
39cc5be2 2078static const struct amdgpu_display_funcs dm_display_funcs = {
4562236b
HW		 2079 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2080 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
7b42573b
HW		 2081 .backlight_set_level = NULL, /* never called for DC */
2082 .backlight_get_level = NULL, /* never called for DC */
4562236b
HW		 2083 .hpd_sense = NULL,/* called unconditionally */
2084 .hpd_set_polarity = NULL, /* called unconditionally */
2085 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2086 .page_flip_get_scanoutpos =
2087 dm_crtc_get_scanoutpos,/* called unconditionally */
2088 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2089 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4562236b
HW		 2090};
2091
2092#if defined(CONFIG_DEBUG_KERNEL_DC)
2093
3ee6b26b
AD		 2094static ssize_t s3_debug_store(struct device *device,
2095 struct device_attribute *attr,
2096 const char *buf,
2097 size_t count)
4562236b
HW		 2098{
2099 int ret;
2100 int s3_state;
2101 struct pci_dev *pdev = to_pci_dev(device);
2102 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2103 struct amdgpu_device *adev = drm_dev->dev_private;
2104
2105 ret = kstrtoint(buf, 0, &s3_state);
2106
2107 if (ret == 0) {
2108 if (s3_state) {
2109 dm_resume(adev);
4562236b
HW		 2110 drm_kms_helper_hotplug_event(adev->ddev);
2111 } else
2112 dm_suspend(adev);
2113 }
2114
2115 return ret == 0 ? count : 0;
2116}
2117
2118DEVICE_ATTR_WO(s3_debug);
2119
2120#endif
2121
2122static int dm_early_init(void *handle)
2123{
2124 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2125
4562236b
HW		 2126 switch (adev->asic_type) {
2127 case CHIP_BONAIRE:
2128 case CHIP_HAWAII:
2129 adev->mode_info.num_crtc = 6;
2130 adev->mode_info.num_hpd = 6;
2131 adev->mode_info.num_dig = 6;
4562236b 2132 break;
cd4b356f
AD		 2133 case CHIP_KAVERI:
2134 adev->mode_info.num_crtc = 4;
2135 adev->mode_info.num_hpd = 6;
2136 adev->mode_info.num_dig = 7;
cd4b356f
AD		 2137 break;
2138 case CHIP_KABINI:
2139 case CHIP_MULLINS:
2140 adev->mode_info.num_crtc = 2;
2141 adev->mode_info.num_hpd = 6;
2142 adev->mode_info.num_dig = 6;
cd4b356f 2143 break;
4562236b
HW		 2144 case CHIP_FIJI:
2145 case CHIP_TONGA:
2146 adev->mode_info.num_crtc = 6;
2147 adev->mode_info.num_hpd = 6;
2148 adev->mode_info.num_dig = 7;
4562236b
HW		 2149 break;
2150 case CHIP_CARRIZO:
2151 adev->mode_info.num_crtc = 3;
2152 adev->mode_info.num_hpd = 6;
2153 adev->mode_info.num_dig = 9;
4562236b
HW		 2154 break;
2155 case CHIP_STONEY:
2156 adev->mode_info.num_crtc = 2;
2157 adev->mode_info.num_hpd = 6;
2158 adev->mode_info.num_dig = 9;
4562236b
HW		 2159 break;
2160 case CHIP_POLARIS11:
b264d345 2161 case CHIP_POLARIS12:
4562236b
HW		 2162 adev->mode_info.num_crtc = 5;
2163 adev->mode_info.num_hpd = 5;
2164 adev->mode_info.num_dig = 5;
4562236b
HW		 2165 break;
2166 case CHIP_POLARIS10:
7737de91 2167 case CHIP_VEGAM:
4562236b
HW		 2168 adev->mode_info.num_crtc = 6;
2169 adev->mode_info.num_hpd = 6;
2170 adev->mode_info.num_dig = 6;
4562236b 2171 break;
2c8ad2d5 2172 case CHIP_VEGA10:
2325ff30 2173 case CHIP_VEGA12:
1fe6bf2f 2174 case CHIP_VEGA20:
2c8ad2d5
AD		 2175 adev->mode_info.num_crtc = 6;
2176 adev->mode_info.num_hpd = 6;
2177 adev->mode_info.num_dig = 6;
2178 break;
ff5ef992
AD		 2179#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2180 case CHIP_RAVEN:
2181 adev->mode_info.num_crtc = 4;
2182 adev->mode_info.num_hpd = 4;
2183 adev->mode_info.num_dig = 4;
ff5ef992
AD		 2184 break;
2185#endif
4562236b 2186 default:
e63f8673 2187 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
4562236b
HW		 2188 return -EINVAL;
2189 }
2190
c8dd5715
MD		 2191 amdgpu_dm_set_irq_funcs(adev);
2192
39cc5be2
AD		 2193 if (adev->mode_info.funcs == NULL)
2194 adev->mode_info.funcs = &dm_display_funcs;
2195
1f6010a9
DF		 2196 /*
2197 * Note: Do NOT change adev->audio_endpt_rreg and
4562236b 2198 * adev->audio_endpt_wreg because they are initialised in
1f6010a9
DF		 2199 * amdgpu_device_init()
2200 */
4562236b
HW		 2201#if defined(CONFIG_DEBUG_KERNEL_DC)
2202 device_create_file(
2203 adev->ddev->dev,
2204 &dev_attr_s3_debug);
2205#endif
2206
2207 return 0;
2208}
2209
9b690ef3 2210static bool modeset_required(struct drm_crtc_state *crtc_state,
0971c40e
HW		 2211 struct dc_stream_state *new_stream,
2212 struct dc_stream_state *old_stream)
9b690ef3 2213{
e7b07cee
HW		 2214 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2215 return false;
2216
2217 if (!crtc_state->enable)
2218 return false;
2219
2220 return crtc_state->active;
2221}
2222
2223static bool modereset_required(struct drm_crtc_state *crtc_state)
2224{
2225 if (!drm_atomic_crtc_needs_modeset(crtc_state))
2226 return false;
2227
2228 return !crtc_state->enable || !crtc_state->active;
2229}
2230
7578ecda 2231static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
e7b07cee
HW		 2232{
2233 drm_encoder_cleanup(encoder);
2234 kfree(encoder);
2235}
2236
2237static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2238 .destroy = amdgpu_dm_encoder_destroy,
2239};
2240
3ee6b26b
AD		 2241static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
2242 struct dc_plane_state *plane_state)
e7b07cee 2243{
3be5262e
HW		 2244 plane_state->src_rect.x = state->src_x >> 16;
2245 plane_state->src_rect.y = state->src_y >> 16;
1f6010a9 2246 /* we ignore the mantissa for now and do not deal with floating pixels :( */
3be5262e 2247 plane_state->src_rect.width = state->src_w >> 16;
e7b07cee 2248
3be5262e 2249 if (plane_state->src_rect.width == 0)
e7b07cee
HW		 2250 return false;
2251
3be5262e
HW		 2252 plane_state->src_rect.height = state->src_h >> 16;
2253 if (plane_state->src_rect.height == 0)
e7b07cee
HW		 2254 return false;
2255
3be5262e
HW		 2256 plane_state->dst_rect.x = state->crtc_x;
2257 plane_state->dst_rect.y = state->crtc_y;
e7b07cee
HW		 2258
2259 if (state->crtc_w == 0)
2260 return false;
2261
3be5262e 2262 plane_state->dst_rect.width = state->crtc_w;
e7b07cee
HW		 2263
2264 if (state->crtc_h == 0)
2265 return false;
2266
3be5262e 2267 plane_state->dst_rect.height = state->crtc_h;
e7b07cee 2268
3be5262e 2269 plane_state->clip_rect = plane_state->dst_rect;
e7b07cee
HW		 2270
2271 switch (state->rotation & DRM_MODE_ROTATE_MASK) {
2272 case DRM_MODE_ROTATE_0:
3be5262e 2273 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2274 break;
2275 case DRM_MODE_ROTATE_90:
3be5262e 2276 plane_state->rotation = ROTATION_ANGLE_90;
e7b07cee
HW		 2277 break;
2278 case DRM_MODE_ROTATE_180:
3be5262e 2279 plane_state->rotation = ROTATION_ANGLE_180;
e7b07cee
HW		 2280 break;
2281 case DRM_MODE_ROTATE_270:
3be5262e 2282 plane_state->rotation = ROTATION_ANGLE_270;
e7b07cee
HW		 2283 break;
2284 default:
3be5262e 2285 plane_state->rotation = ROTATION_ANGLE_0;
e7b07cee
HW		 2286 break;
2287 }
2288
4562236b
HW		 2289 return true;
2290}
3ee6b26b 2291static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
9817d5f5 2292 uint64_t *tiling_flags)
e7b07cee 2293{
e68d14dd 2294 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
e7b07cee 2295 int r = amdgpu_bo_reserve(rbo, false);
b830ebc9 2296
e7b07cee 2297 if (unlikely(r)) {
1f6010a9 2298 /* Don't show error message when returning -ERESTARTSYS */
9bbc3031
JZ		 2299 if (r != -ERESTARTSYS)
2300 DRM_ERROR("Unable to reserve buffer: %d\n", r);
e7b07cee
HW		 2301 return r;
2302 }
2303
e7b07cee
HW		 2304 if (tiling_flags)
2305 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2306
2307 amdgpu_bo_unreserve(rbo);
2308
2309 return r;
2310}
2311
7df7e505
NK		 2312static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2313{
2314 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2315
2316 return offset ? (address + offset * 256) : 0;
2317}
2318
2319static bool fill_plane_dcc_attributes(struct amdgpu_device *adev,
2320 const struct amdgpu_framebuffer *afb,
2321 struct dc_plane_state *plane_state,
2322 uint64_t info)
2323{
2324 struct dc *dc = adev->dm.dc;
8daa1218
NC		 2325 struct dc_dcc_surface_param input;
2326 struct dc_surface_dcc_cap output;
7df7e505
NK		 2327 uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2328 uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2329 uint64_t dcc_address;
2330
8daa1218
NC		 2331 memset(&input, 0, sizeof(input));
2332 memset(&output, 0, sizeof(output));
2333
7df7e505
NK		 2334 if (!offset)
2335 return false;
2336
2337 if (!dc->cap_funcs.get_dcc_compression_cap)
2338 return false;
2339
2340 input.format = plane_state->format;
2341 input.surface_size.width =
2342 plane_state->plane_size.grph.surface_size.width;
2343 input.surface_size.height =
2344 plane_state->plane_size.grph.surface_size.height;
2345 input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle;
2346
2347 if (plane_state->rotation == ROTATION_ANGLE_0 ||
2348 plane_state->rotation == ROTATION_ANGLE_180)
2349 input.scan = SCAN_DIRECTION_HORIZONTAL;
2350 else if (plane_state->rotation == ROTATION_ANGLE_90 ||
2351 plane_state->rotation == ROTATION_ANGLE_270)
2352 input.scan = SCAN_DIRECTION_VERTICAL;
2353
2354 if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2355 return false;
2356
2357 if (!output.capable)
2358 return false;
2359
2360 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2361 return false;
2362
2363 plane_state->dcc.enable = 1;
2364 plane_state->dcc.grph.meta_pitch =
2365 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2366 plane_state->dcc.grph.independent_64b_blks = i64b;
2367
2368 dcc_address = get_dcc_address(afb->address, info);
2369 plane_state->address.grph.meta_addr.low_part =
2370 lower_32_bits(dcc_address);
2371 plane_state->address.grph.meta_addr.high_part =
2372 upper_32_bits(dcc_address);
2373
2374 return true;
2375}
2376
3ee6b26b
AD		 2377static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
2378 struct dc_plane_state *plane_state,
9817d5f5 2379 const struct amdgpu_framebuffer *amdgpu_fb)
e7b07cee
HW		 2380{
2381 uint64_t tiling_flags;
e7b07cee
HW		 2382 unsigned int awidth;
2383 const struct drm_framebuffer *fb = &amdgpu_fb->base;
2384 int ret = 0;
2385 struct drm_format_name_buf format_name;
2386
2387 ret = get_fb_info(
2388 amdgpu_fb,
9817d5f5 2389 &tiling_flags);
e7b07cee
HW		 2390
2391 if (ret)
2392 return ret;
2393
2394 switch (fb->format->format) {
2395 case DRM_FORMAT_C8:
3be5262e 2396 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
e7b07cee
HW		 2397 break;
2398 case DRM_FORMAT_RGB565:
3be5262e 2399 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
e7b07cee
HW		 2400 break;
2401 case DRM_FORMAT_XRGB8888:
2402 case DRM_FORMAT_ARGB8888:
3be5262e 2403 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
e7b07cee
HW		 2404 break;
2405 case DRM_FORMAT_XRGB2101010:
2406 case DRM_FORMAT_ARGB2101010:
3be5262e 2407 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
e7b07cee
HW		 2408 break;
2409 case DRM_FORMAT_XBGR2101010:
2410 case DRM_FORMAT_ABGR2101010:
3be5262e 2411 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
e7b07cee 2412 break;
bcd47f60
MR		 2413 case DRM_FORMAT_XBGR8888:
2414 case DRM_FORMAT_ABGR8888:
2415 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2416 break;
e7b07cee 2417 case DRM_FORMAT_NV21:
3be5262e 2418 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
e7b07cee
HW		 2419 break;
2420 case DRM_FORMAT_NV12:
3be5262e 2421 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
e7b07cee
HW		 2422 break;
2423 default:
2424 DRM_ERROR("Unsupported screen format %s\n",
1ecfc3da 2425 drm_get_format_name(fb->format->format, &format_name));
e7b07cee
HW		 2426 return -EINVAL;
2427 }
2428
7df7e505
NK		 2429 memset(&plane_state->address, 0, sizeof(plane_state->address));
2430 memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
2431 memset(&plane_state->dcc, 0, sizeof(plane_state->dcc));
2432
3be5262e
HW		 2433 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2434 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
3be5262e
HW		 2435 plane_state->plane_size.grph.surface_size.x = 0;
2436 plane_state->plane_size.grph.surface_size.y = 0;
2437 plane_state->plane_size.grph.surface_size.width = fb->width;
2438 plane_state->plane_size.grph.surface_size.height = fb->height;
2439 plane_state->plane_size.grph.surface_pitch =
e7b07cee
HW		 2440 fb->pitches[0] / fb->format->cpp[0];
2441 /* TODO: unhardcode */
3be5262e 2442 plane_state->color_space = COLOR_SPACE_SRGB;
e7b07cee
HW		 2443
2444 } else {
2445 awidth = ALIGN(fb->width, 64);
3be5262e 2446 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e
HW		 2447 plane_state->plane_size.video.luma_size.x = 0;
2448 plane_state->plane_size.video.luma_size.y = 0;
2449 plane_state->plane_size.video.luma_size.width = awidth;
2450 plane_state->plane_size.video.luma_size.height = fb->height;
e7b07cee 2451 /* TODO: unhardcode */
3be5262e 2452 plane_state->plane_size.video.luma_pitch = awidth;
e7b07cee 2453
3be5262e
HW		 2454 plane_state->plane_size.video.chroma_size.x = 0;
2455 plane_state->plane_size.video.chroma_size.y = 0;
2456 plane_state->plane_size.video.chroma_size.width = awidth;
2457 plane_state->plane_size.video.chroma_size.height = fb->height;
2458 plane_state->plane_size.video.chroma_pitch = awidth / 2;
e7b07cee
HW		 2459
2460 /* TODO: unhardcode */
3be5262e 2461 plane_state->color_space = COLOR_SPACE_YCBCR709;
e7b07cee
HW		 2462 }
2463
b830ebc9
HW		 2464 /* Fill GFX8 params */
2465 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2466 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
e7b07cee
HW		 2467
2468 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2469 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2470 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2471 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2472 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2473
2474 /* XXX fix me for VI */
3be5262e
HW		 2475 plane_state->tiling_info.gfx8.num_banks = num_banks;
2476 plane_state->tiling_info.gfx8.array_mode =
e7b07cee 2477 DC_ARRAY_2D_TILED_THIN1;
3be5262e
HW		 2478 plane_state->tiling_info.gfx8.tile_split = tile_split;
2479 plane_state->tiling_info.gfx8.bank_width = bankw;
2480 plane_state->tiling_info.gfx8.bank_height = bankh;
2481 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2482 plane_state->tiling_info.gfx8.tile_mode =
e7b07cee
HW		 2483 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2484 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2485 == DC_ARRAY_1D_TILED_THIN1) {
3be5262e 2486 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
e7b07cee
HW		 2487 }
2488
3be5262e 2489 plane_state->tiling_info.gfx8.pipe_config =
e7b07cee
HW		 2490 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2491
2492 if (adev->asic_type == CHIP_VEGA10 ||
2325ff30 2493 adev->asic_type == CHIP_VEGA12 ||
1fe6bf2f 2494 adev->asic_type == CHIP_VEGA20 ||
e7b07cee
HW		 2495 adev->asic_type == CHIP_RAVEN) {
2496 /* Fill GFX9 params */
3be5262e 2497 plane_state->tiling_info.gfx9.num_pipes =
e7b07cee 2498 adev->gfx.config.gb_addr_config_fields.num_pipes;
3be5262e 2499 plane_state->tiling_info.gfx9.num_banks =
e7b07cee 2500 adev->gfx.config.gb_addr_config_fields.num_banks;
3be5262e 2501 plane_state->tiling_info.gfx9.pipe_interleave =
e7b07cee 2502 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
3be5262e 2503 plane_state->tiling_info.gfx9.num_shader_engines =
e7b07cee 2504 adev->gfx.config.gb_addr_config_fields.num_se;
3be5262e 2505 plane_state->tiling_info.gfx9.max_compressed_frags =
e7b07cee 2506 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
3be5262e 2507 plane_state->tiling_info.gfx9.num_rb_per_se =
e7b07cee 2508 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
3be5262e 2509 plane_state->tiling_info.gfx9.swizzle =
e7b07cee 2510 AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
3be5262e 2511 plane_state->tiling_info.gfx9.shaderEnable = 1;
7df7e505
NK		 2512
2513 fill_plane_dcc_attributes(adev, amdgpu_fb, plane_state,
2514 tiling_flags);
e7b07cee
HW		 2515 }
2516
3be5262e
HW		 2517 plane_state->visible = true;
2518 plane_state->scaling_quality.h_taps_c = 0;
2519 plane_state->scaling_quality.v_taps_c = 0;
e7b07cee 2520
3be5262e
HW		 2521 /* is this needed? is plane_state zeroed at allocation? */
2522 plane_state->scaling_quality.h_taps = 0;
2523 plane_state->scaling_quality.v_taps = 0;
2524 plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
e7b07cee
HW		 2525
2526 return ret;
2527
2528}
2529
3ee6b26b
AD		 2530static int fill_plane_attributes(struct amdgpu_device *adev,
2531 struct dc_plane_state *dc_plane_state,
2532 struct drm_plane_state *plane_state,
9817d5f5 2533 struct drm_crtc_state *crtc_state)
e7b07cee
HW		 2534{
2535 const struct amdgpu_framebuffer *amdgpu_fb =
2536 to_amdgpu_framebuffer(plane_state->fb);
2537 const struct drm_crtc *crtc = plane_state->crtc;
e7b07cee
HW		 2538 int ret = 0;
2539
3be5262e 2540 if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
e7b07cee
HW		 2541 return -EINVAL;
2542
2543 ret = fill_plane_attributes_from_fb(
2544 crtc->dev->dev_private,
3be5262e 2545 dc_plane_state,
9817d5f5 2546 amdgpu_fb);
e7b07cee
HW		 2547
2548 if (ret)
2549 return ret;
2550
e277adc5
LSL		 2551 /*
2552 * Always set input transfer function, since plane state is refreshed
2553 * every time.
2554 */
2555 ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
8c45c5db
LSL		 2556 if (ret) {
2557 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2558 dc_plane_state->in_transfer_func = NULL;
2559 }
e7b07cee
HW		 2560
2561 return ret;
2562}
2563
3ee6b26b
AD		 2564static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2565 const struct dm_connector_state *dm_state,
2566 struct dc_stream_state *stream)
e7b07cee
HW		 2567{
2568 enum amdgpu_rmx_type rmx_type;
2569
2570 struct rect src = { 0 }; /* viewport in composition space*/
2571 struct rect dst = { 0 }; /* stream addressable area */
2572
2573 /* no mode. nothing to be done */
2574 if (!mode)
2575 return;
2576
2577 /* Full screen scaling by default */
2578 src.width = mode->hdisplay;
2579 src.height = mode->vdisplay;
2580 dst.width = stream->timing.h_addressable;
2581 dst.height = stream->timing.v_addressable;
2582
f4791779
HW		 2583 if (dm_state) {
2584 rmx_type = dm_state->scaling;
2585 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2586 if (src.width * dst.height <
2587 src.height * dst.width) {
2588 /* height needs less upscaling/more downscaling */
2589 dst.width = src.width *
2590 dst.height / src.height;
2591 } else {
2592 /* width needs less upscaling/more downscaling */
2593 dst.height = src.height *
2594 dst.width / src.width;
2595 }
2596 } else if (rmx_type == RMX_CENTER) {
2597 dst = src;
e7b07cee 2598 }
e7b07cee 2599
f4791779
HW		 2600 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2601 dst.y = (stream->timing.v_addressable - dst.height) / 2;
e7b07cee 2602
f4791779
HW		 2603 if (dm_state->underscan_enable) {
2604 dst.x += dm_state->underscan_hborder / 2;
2605 dst.y += dm_state->underscan_vborder / 2;
2606 dst.width -= dm_state->underscan_hborder;
2607 dst.height -= dm_state->underscan_vborder;
2608 }
e7b07cee
HW		 2609 }
2610
2611 stream->src = src;
2612 stream->dst = dst;
2613
f1ad2f5e 2614 DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n",
e7b07cee
HW		 2615 dst.x, dst.y, dst.width, dst.height);
2616
2617}
2618
3ee6b26b
AD		 2619static enum dc_color_depth
2620convert_color_depth_from_display_info(const struct drm_connector *connector)
e7b07cee 2621{
07e3a1cf
NK		 2622 struct dm_connector_state *dm_conn_state =
2623 to_dm_connector_state(connector->state);
e7b07cee
HW		 2624 uint32_t bpc = connector->display_info.bpc;
2625
07e3a1cf
NK		 2626 /* TODO: Remove this when there's support for max_bpc in drm */
2627 if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2628 /* Round down to nearest even number. */
2629 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2630
e7b07cee
HW		 2631 switch (bpc) {
2632 case 0:
1f6010a9
DF		 2633 /*
2634 * Temporary Work around, DRM doesn't parse color depth for
e7b07cee
HW		 2635 * EDID revision before 1.4
2636 * TODO: Fix edid parsing
2637 */
2638 return COLOR_DEPTH_888;
2639 case 6:
2640 return COLOR_DEPTH_666;
2641 case 8:
2642 return COLOR_DEPTH_888;
2643 case 10:
2644 return COLOR_DEPTH_101010;
2645 case 12:
2646 return COLOR_DEPTH_121212;
2647 case 14:
2648 return COLOR_DEPTH_141414;
2649 case 16:
2650 return COLOR_DEPTH_161616;
2651 default:
2652 return COLOR_DEPTH_UNDEFINED;
2653 }
2654}
2655
3ee6b26b
AD		 2656static enum dc_aspect_ratio
2657get_aspect_ratio(const struct drm_display_mode *mode_in)
e7b07cee 2658{
e11d4147
LSL		 2659 /* 1-1 mapping, since both enums follow the HDMI spec. */
2660 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
e7b07cee
HW		 2661}
2662
3ee6b26b
AD		 2663static enum dc_color_space
2664get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
e7b07cee
HW		 2665{
2666 enum dc_color_space color_space = COLOR_SPACE_SRGB;
2667
2668 switch (dc_crtc_timing->pixel_encoding) {
2669 case PIXEL_ENCODING_YCBCR422:
2670 case PIXEL_ENCODING_YCBCR444:
2671 case PIXEL_ENCODING_YCBCR420:
2672 {
2673 /*
2674 * 27030khz is the separation point between HDTV and SDTV
2675 * according to HDMI spec, we use YCbCr709 and YCbCr601
2676 * respectively
2677 */
380604e2 2678 if (dc_crtc_timing->pix_clk_100hz > 270300) {
e7b07cee
HW		 2679 if (dc_crtc_timing->flags.Y_ONLY)
2680 color_space =
2681 COLOR_SPACE_YCBCR709_LIMITED;
2682 else
2683 color_space = COLOR_SPACE_YCBCR709;
2684 } else {
2685 if (dc_crtc_timing->flags.Y_ONLY)
2686 color_space =
2687 COLOR_SPACE_YCBCR601_LIMITED;
2688 else
2689 color_space = COLOR_SPACE_YCBCR601;
2690 }
2691
2692 }
2693 break;
2694 case PIXEL_ENCODING_RGB:
2695 color_space = COLOR_SPACE_SRGB;
2696 break;
2697
2698 default:
2699 WARN_ON(1);
2700 break;
2701 }
2702
2703 return color_space;
2704}
2705
400443e8
ML		 2706static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
2707{
2708 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2709 return;
2710
2711 timing_out->display_color_depth--;
2712}
2713
2714static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
2715 const struct drm_display_info *info)
2716{
2717 int normalized_clk;
2718 if (timing_out->display_color_depth <= COLOR_DEPTH_888)
2719 return;
2720 do {
380604e2 2721 normalized_clk = timing_out->pix_clk_100hz / 10;
400443e8
ML		 2722 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
2723 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2724 normalized_clk /= 2;
2725 /* Adjusting pix clock following on HDMI spec based on colour depth */
2726 switch (timing_out->display_color_depth) {
2727 case COLOR_DEPTH_101010:
2728 normalized_clk = (normalized_clk * 30) / 24;
2729 break;
2730 case COLOR_DEPTH_121212:
2731 normalized_clk = (normalized_clk * 36) / 24;
2732 break;
2733 case COLOR_DEPTH_161616:
2734 normalized_clk = (normalized_clk * 48) / 24;
2735 break;
2736 default:
2737 return;
2738 }
2739 if (normalized_clk <= info->max_tmds_clock)
2740 return;
2741 reduce_mode_colour_depth(timing_out);
2742
2743 } while (timing_out->display_color_depth > COLOR_DEPTH_888);
2744
2745}
e7b07cee 2746
3ee6b26b
AD		 2747static void
2748fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2749 const struct drm_display_mode *mode_in,
b333730d
BL		 2750 const struct drm_connector *connector,
2751 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2752{
2753 struct dc_crtc_timing *timing_out = &stream->timing;
fe61a2f1 2754 const struct drm_display_info *info = &connector->display_info;
b830ebc9 2755
e7b07cee
HW		 2756 memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2757
2758 timing_out->h_border_left = 0;
2759 timing_out->h_border_right = 0;
2760 timing_out->v_border_top = 0;
2761 timing_out->v_border_bottom = 0;
2762 /* TODO: un-hardcode */
fe61a2f1 2763 if (drm_mode_is_420_only(info, mode_in)
ceb3dbb4 2764 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
fe61a2f1
ML		 2765 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
2766 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
ceb3dbb4 2767 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
e7b07cee
HW		 2768 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2769 else
2770 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2771
2772 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2773 timing_out->display_color_depth = convert_color_depth_from_display_info(
2774 connector);
2775 timing_out->scan_type = SCANNING_TYPE_NODATA;
2776 timing_out->hdmi_vic = 0;
b333730d
BL		 2777
2778 if(old_stream) {
2779 timing_out->vic = old_stream->timing.vic;
2780 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
2781 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
2782 } else {
2783 timing_out->vic = drm_match_cea_mode(mode_in);
2784 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2785 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2786 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2787 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2788 }
e7b07cee
HW		 2789
2790 timing_out->h_addressable = mode_in->crtc_hdisplay;
2791 timing_out->h_total = mode_in->crtc_htotal;
2792 timing_out->h_sync_width =
2793 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2794 timing_out->h_front_porch =
2795 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2796 timing_out->v_total = mode_in->crtc_vtotal;
2797 timing_out->v_addressable = mode_in->crtc_vdisplay;
2798 timing_out->v_front_porch =
2799 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2800 timing_out->v_sync_width =
2801 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
380604e2 2802 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
e7b07cee 2803 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
e7b07cee
HW		 2804
2805 stream->output_color_space = get_output_color_space(timing_out);
2806
e43a432c
AK		 2807 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
2808 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
ceb3dbb4 2809 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
400443e8 2810 adjust_colour_depth_from_display_info(timing_out, info);
e7b07cee
HW		 2811}
2812
3ee6b26b
AD		 2813static void fill_audio_info(struct audio_info *audio_info,
2814 const struct drm_connector *drm_connector,
2815 const struct dc_sink *dc_sink)
e7b07cee
HW		 2816{
2817 int i = 0;
2818 int cea_revision = 0;
2819 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2820
2821 audio_info->manufacture_id = edid_caps->manufacturer_id;
2822 audio_info->product_id = edid_caps->product_id;
2823
2824 cea_revision = drm_connector->display_info.cea_rev;
2825
090afc1e 2826 strscpy(audio_info->display_name,
d2b2562c 2827 edid_caps->display_name,
090afc1e 2828 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
e7b07cee 2829
b830ebc9 2830 if (cea_revision >= 3) {
e7b07cee
HW		 2831 audio_info->mode_count = edid_caps->audio_mode_count;
2832
2833 for (i = 0; i < audio_info->mode_count; ++i) {
2834 audio_info->modes[i].format_code =
2835 (enum audio_format_code)
2836 (edid_caps->audio_modes[i].format_code);
2837 audio_info->modes[i].channel_count =
2838 edid_caps->audio_modes[i].channel_count;
2839 audio_info->modes[i].sample_rates.all =
2840 edid_caps->audio_modes[i].sample_rate;
2841 audio_info->modes[i].sample_size =
2842 edid_caps->audio_modes[i].sample_size;
2843 }
2844 }
2845
2846 audio_info->flags.all = edid_caps->speaker_flags;
2847
2848 /* TODO: We only check for the progressive mode, check for interlace mode too */
b830ebc9 2849 if (drm_connector->latency_present[0]) {
e7b07cee
HW		 2850 audio_info->video_latency = drm_connector->video_latency[0];
2851 audio_info->audio_latency = drm_connector->audio_latency[0];
2852 }
2853
2854 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2855
2856}
2857
3ee6b26b
AD		 2858static void
2859copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2860 struct drm_display_mode *dst_mode)
e7b07cee
HW		 2861{
2862 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2863 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2864 dst_mode->crtc_clock = src_mode->crtc_clock;
2865 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2866 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
b830ebc9 2867 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
e7b07cee
HW		 2868 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2869 dst_mode->crtc_htotal = src_mode->crtc_htotal;
2870 dst_mode->crtc_hskew = src_mode->crtc_hskew;
2871 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2872 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2873 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2874 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2875 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2876}
2877
3ee6b26b
AD		 2878static void
2879decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2880 const struct drm_display_mode *native_mode,
2881 bool scale_enabled)
e7b07cee
HW		 2882{
2883 if (scale_enabled) {
2884 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2885 } else if (native_mode->clock == drm_mode->clock &&
2886 native_mode->htotal == drm_mode->htotal &&
2887 native_mode->vtotal == drm_mode->vtotal) {
2888 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2889 } else {
2890 /* no scaling nor amdgpu inserted, no need to patch */
2891 }
2892}
2893
aed15309
ML		 2894static struct dc_sink *
2895create_fake_sink(struct amdgpu_dm_connector *aconnector)
2e0ac3d6 2896{
2e0ac3d6 2897 struct dc_sink_init_data sink_init_data = { 0 };
aed15309 2898 struct dc_sink *sink = NULL;
2e0ac3d6
HW		 2899 sink_init_data.link = aconnector->dc_link;
2900 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2901
2902 sink = dc_sink_create(&sink_init_data);
423788c7 2903 if (!sink) {
2e0ac3d6 2904 DRM_ERROR("Failed to create sink!\n");
aed15309 2905 return NULL;
423788c7 2906 }
2e0ac3d6 2907 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
423788c7 2908
aed15309 2909 return sink;
2e0ac3d6
HW		 2910}
2911
fa2123db
ML		 2912static void set_multisync_trigger_params(
2913 struct dc_stream_state *stream)
2914{
2915 if (stream->triggered_crtc_reset.enabled) {
2916 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2917 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2918 }
2919}
2920
2921static void set_master_stream(struct dc_stream_state *stream_set[],
2922 int stream_count)
2923{
2924 int j, highest_rfr = 0, master_stream = 0;
2925
2926 for (j = 0; j < stream_count; j++) {
2927 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2928 int refresh_rate = 0;
2929
380604e2 2930 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
fa2123db
ML		 2931 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2932 if (refresh_rate > highest_rfr) {
2933 highest_rfr = refresh_rate;
2934 master_stream = j;
2935 }
2936 }
2937 }
2938 for (j = 0; j < stream_count; j++) {
03736f4c 2939 if (stream_set[j])
fa2123db
ML		 2940 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2941 }
2942}
2943
2944static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2945{
2946 int i = 0;
2947
2948 if (context->stream_count < 2)
2949 return;
2950 for (i = 0; i < context->stream_count ; i++) {
2951 if (!context->streams[i])
2952 continue;
1f6010a9
DF		 2953 /*
2954 * TODO: add a function to read AMD VSDB bits and set
fa2123db 2955 * crtc_sync_master.multi_sync_enabled flag
1f6010a9 2956 * For now it's set to false
fa2123db
ML		 2957 */
2958 set_multisync_trigger_params(context->streams[i]);
2959 }
2960 set_master_stream(context->streams, context->stream_count);
2961}
2962
3ee6b26b
AD		 2963static struct dc_stream_state *
2964create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2965 const struct drm_display_mode *drm_mode,
b333730d
BL		 2966 const struct dm_connector_state *dm_state,
2967 const struct dc_stream_state *old_stream)
e7b07cee
HW		 2968{
2969 struct drm_display_mode *preferred_mode = NULL;
391ef035 2970 struct drm_connector *drm_connector;
0971c40e 2971 struct dc_stream_state *stream = NULL;
e7b07cee
HW		 2972 struct drm_display_mode mode = *drm_mode;
2973 bool native_mode_found = false;
b333730d
BL		 2974 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
2975 int mode_refresh;
58124bf8 2976 int preferred_refresh = 0;
b333730d 2977
aed15309 2978 struct dc_sink *sink = NULL;
b830ebc9 2979 if (aconnector == NULL) {
e7b07cee 2980 DRM_ERROR("aconnector is NULL!\n");
64245fa7 2981 return stream;
e7b07cee
HW		 2982 }
2983
e7b07cee 2984 drm_connector = &aconnector->base;
2e0ac3d6 2985
f4ac176e 2986 if (!aconnector->dc_sink) {
e3fa5c4c
JFZ		 2987 sink = create_fake_sink(aconnector);
2988 if (!sink)
2989 return stream;
aed15309
ML		 2990 } else {
2991 sink = aconnector->dc_sink;
dcd5fb82 2992 dc_sink_retain(sink);
f4ac176e 2993 }
2e0ac3d6 2994
aed15309 2995 stream = dc_create_stream_for_sink(sink);
4562236b 2996
b830ebc9 2997 if (stream == NULL) {
e7b07cee 2998 DRM_ERROR("Failed to create stream for sink!\n");
aed15309 2999 goto finish;
e7b07cee
HW		 3000 }
3001
ceb3dbb4
JL		 3002 stream->dm_stream_context = aconnector;
3003
e7b07cee
HW		 3004 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3005 /* Search for preferred mode */
3006 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3007 native_mode_found = true;
3008 break;
3009 }
3010 }
3011 if (!native_mode_found)
3012 preferred_mode = list_first_entry_or_null(
3013 &aconnector->base.modes,
3014 struct drm_display_mode,
3015 head);
3016
b333730d
BL		 3017 mode_refresh = drm_mode_vrefresh(&mode);
3018
b830ebc9 3019 if (preferred_mode == NULL) {
1f6010a9
DF		 3020 /*
3021 * This may not be an error, the use case is when we have no
e7b07cee
HW		 3022 * usermode calls to reset and set mode upon hotplug. In this
3023 * case, we call set mode ourselves to restore the previous mode
3024 * and the modelist may not be filled in in time.
3025 */
f1ad2f5e 3026 DRM_DEBUG_DRIVER("No preferred mode found\n");
e7b07cee
HW		 3027 } else {
3028 decide_crtc_timing_for_drm_display_mode(
3029 &mode, preferred_mode,
f4791779 3030 dm_state ? (dm_state->scaling != RMX_OFF) : false);
58124bf8 3031 preferred_refresh = drm_mode_vrefresh(preferred_mode);
e7b07cee
HW		 3032 }
3033
f783577c
JFZ		 3034 if (!dm_state)
3035 drm_mode_set_crtcinfo(&mode, 0);
3036
b333730d
BL		 3037 /*
3038 * If scaling is enabled and refresh rate didn't change
3039 * we copy the vic and polarities of the old timings
3040 */
3041 if (!scale || mode_refresh != preferred_refresh)
3042 fill_stream_properties_from_drm_display_mode(stream,
3043 &mode, &aconnector->base, NULL);
3044 else
3045 fill_stream_properties_from_drm_display_mode(stream,
3046 &mode, &aconnector->base, old_stream);
3047
e7b07cee
HW		 3048 update_stream_scaling_settings(&mode, dm_state, stream);
3049
3050 fill_audio_info(
3051 &stream->audio_info,
3052 drm_connector,
aed15309 3053 sink);
e7b07cee 3054
ceb3dbb4 3055 update_stream_signal(stream, sink);
9182b4cb 3056
aed15309 3057finish:
dcd5fb82 3058 dc_sink_release(sink);
9e3efe3e 3059
e7b07cee
HW		 3060 return stream;
3061}
3062
7578ecda 3063static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
e7b07cee
HW		 3064{
3065 drm_crtc_cleanup(crtc);
3066 kfree(crtc);
3067}
3068
3069static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3ee6b26b 3070 struct drm_crtc_state *state)
e7b07cee
HW		 3071{
3072 struct dm_crtc_state *cur = to_dm_crtc_state(state);
3073
3074 /* TODO Destroy dc_stream objects are stream object is flattened */
3075 if (cur->stream)
3076 dc_stream_release(cur->stream);
3077
3078
3079 __drm_atomic_helper_crtc_destroy_state(state);
3080
3081
3082 kfree(state);
3083}
3084
3085static void dm_crtc_reset_state(struct drm_crtc *crtc)
3086{
3087 struct dm_crtc_state *state;
3088
3089 if (crtc->state)
3090 dm_crtc_destroy_state(crtc, crtc->state);
3091
3092 state = kzalloc(sizeof(*state), GFP_KERNEL);
3093 if (WARN_ON(!state))
3094 return;
3095
3096 crtc->state = &state->base;
3097 crtc->state->crtc = crtc;
3098
3099}
3100
3101static struct drm_crtc_state *
3102dm_crtc_duplicate_state(struct drm_crtc *crtc)
3103{
3104 struct dm_crtc_state *state, *cur;
3105
3106 cur = to_dm_crtc_state(crtc->state);
3107
3108 if (WARN_ON(!crtc->state))
3109 return NULL;
3110
2004f45e 3111 state = kzalloc(sizeof(*state), GFP_KERNEL);
2a55f096
ES		 3112 if (!state)
3113 return NULL;
e7b07cee
HW		 3114
3115 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3116
3117 if (cur->stream) {
3118 state->stream = cur->stream;
3119 dc_stream_retain(state->stream);
3120 }
3121
180db303 3122 state->vrr_params = cur->vrr_params;
98e6436d 3123 state->vrr_infopacket = cur->vrr_infopacket;
c1ee92f9 3124 state->abm_level = cur->abm_level;
bb47de73
NK		 3125 state->vrr_supported = cur->vrr_supported;
3126 state->freesync_config = cur->freesync_config;
ed20dc0d 3127 state->crc_enabled = cur->crc_enabled;
98e6436d 3128
e7b07cee
HW		 3129 /* TODO Duplicate dc_stream after objects are stream object is flattened */
3130
3131 return &state->base;
3132}
3133
589d2739
HW		 3134
3135static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3136{
3137 enum dc_irq_source irq_source;
3138 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3139 struct amdgpu_device *adev = crtc->dev->dev_private;
3140
3141 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
a0e30392 3142 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
589d2739
HW		 3143}
3144
3145static int dm_enable_vblank(struct drm_crtc *crtc)
3146{
3147 return dm_set_vblank(crtc, true);
3148}
3149
3150static void dm_disable_vblank(struct drm_crtc *crtc)
3151{
3152 dm_set_vblank(crtc, false);
3153}
3154
e7b07cee
HW		 3155/* Implemented only the options currently availible for the driver */
3156static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3157 .reset = dm_crtc_reset_state,
3158 .destroy = amdgpu_dm_crtc_destroy,
3159 .gamma_set = drm_atomic_helper_legacy_gamma_set,
3160 .set_config = drm_atomic_helper_set_config,
3161 .page_flip = drm_atomic_helper_page_flip,
3162 .atomic_duplicate_state = dm_crtc_duplicate_state,
3163 .atomic_destroy_state = dm_crtc_destroy_state,
31aec354 3164 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3b3b8448 3165 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
589d2739
HW		 3166 .enable_vblank = dm_enable_vblank,
3167 .disable_vblank = dm_disable_vblank,
e7b07cee
HW		 3168};
3169
3170static enum drm_connector_status
3171amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3172{
3173 bool connected;
c84dec2f 3174 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee 3175
1f6010a9
DF		 3176 /*
3177 * Notes:
e7b07cee
HW		 3178 * 1. This interface is NOT called in context of HPD irq.
3179 * 2. This interface *is called* in context of user-mode ioctl. Which
1f6010a9
DF		 3180 * makes it a bad place for *any* MST-related activity.
3181 */
e7b07cee 3182
8580d60b
HW		 3183 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3184 !aconnector->fake_enable)
e7b07cee
HW		 3185 connected = (aconnector->dc_sink != NULL);
3186 else
3187 connected = (aconnector->base.force == DRM_FORCE_ON);
3188
3189 return (connected ? connector_status_connected :
3190 connector_status_disconnected);
3191}
3192
3ee6b26b
AD		 3193int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3194 struct drm_connector_state *connector_state,
3195 struct drm_property *property,
3196 uint64_t val)
e7b07cee
HW		 3197{
3198 struct drm_device *dev = connector->dev;
3199 struct amdgpu_device *adev = dev->dev_private;
3200 struct dm_connector_state *dm_old_state =
3201 to_dm_connector_state(connector->state);
3202 struct dm_connector_state *dm_new_state =
3203 to_dm_connector_state(connector_state);
3204
3205 int ret = -EINVAL;
3206
3207 if (property == dev->mode_config.scaling_mode_property) {
3208 enum amdgpu_rmx_type rmx_type;
3209
3210 switch (val) {
3211 case DRM_MODE_SCALE_CENTER:
3212 rmx_type = RMX_CENTER;
3213 break;
3214 case DRM_MODE_SCALE_ASPECT:
3215 rmx_type = RMX_ASPECT;
3216 break;
3217 case DRM_MODE_SCALE_FULLSCREEN:
3218 rmx_type = RMX_FULL;
3219 break;
3220 case DRM_MODE_SCALE_NONE:
3221 default:
3222 rmx_type = RMX_OFF;
3223 break;
3224 }
3225
3226 if (dm_old_state->scaling == rmx_type)
3227 return 0;
3228
3229 dm_new_state->scaling = rmx_type;
3230 ret = 0;
3231 } else if (property == adev->mode_info.underscan_hborder_property) {
3232 dm_new_state->underscan_hborder = val;
3233 ret = 0;
3234 } else if (property == adev->mode_info.underscan_vborder_property) {
3235 dm_new_state->underscan_vborder = val;
3236 ret = 0;
3237 } else if (property == adev->mode_info.underscan_property) {
3238 dm_new_state->underscan_enable = val;
3239 ret = 0;
07e3a1cf
NK		 3240 } else if (property == adev->mode_info.max_bpc_property) {
3241 dm_new_state->max_bpc = val;
3242 ret = 0;
c1ee92f9
DF		 3243 } else if (property == adev->mode_info.abm_level_property) {
3244 dm_new_state->abm_level = val;
3245 ret = 0;
e7b07cee
HW		 3246 }
3247
3248 return ret;
3249}
3250
3ee6b26b
AD		 3251int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3252 const struct drm_connector_state *state,
3253 struct drm_property *property,
3254 uint64_t *val)
e7b07cee
HW		 3255{
3256 struct drm_device *dev = connector->dev;
3257 struct amdgpu_device *adev = dev->dev_private;
3258 struct dm_connector_state *dm_state =
3259 to_dm_connector_state(state);
3260 int ret = -EINVAL;
3261
3262 if (property == dev->mode_config.scaling_mode_property) {
3263 switch (dm_state->scaling) {
3264 case RMX_CENTER:
3265 *val = DRM_MODE_SCALE_CENTER;
3266 break;
3267 case RMX_ASPECT:
3268 *val = DRM_MODE_SCALE_ASPECT;
3269 break;
3270 case RMX_FULL:
3271 *val = DRM_MODE_SCALE_FULLSCREEN;
3272 break;
3273 case RMX_OFF:
3274 default:
3275 *val = DRM_MODE_SCALE_NONE;
3276 break;
3277 }
3278 ret = 0;
3279 } else if (property == adev->mode_info.underscan_hborder_property) {
3280 *val = dm_state->underscan_hborder;
3281 ret = 0;
3282 } else if (property == adev->mode_info.underscan_vborder_property) {
3283 *val = dm_state->underscan_vborder;
3284 ret = 0;
3285 } else if (property == adev->mode_info.underscan_property) {
3286 *val = dm_state->underscan_enable;
3287 ret = 0;
07e3a1cf
NK		 3288 } else if (property == adev->mode_info.max_bpc_property) {
3289 *val = dm_state->max_bpc;
3290 ret = 0;
c1ee92f9
DF		 3291 } else if (property == adev->mode_info.abm_level_property) {
3292 *val = dm_state->abm_level;
3293 ret = 0;
e7b07cee 3294 }
c1ee92f9 3295
e7b07cee
HW		 3296 return ret;
3297}
3298
7578ecda 3299static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
e7b07cee 3300{
c84dec2f 3301 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 3302 const struct dc_link *link = aconnector->dc_link;
3303 struct amdgpu_device *adev = connector->dev->dev_private;
3304 struct amdgpu_display_manager *dm = &adev->dm;
ada8ce15 3305
e7b07cee
HW		 3306#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3307 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3308
89fc8d4e 3309 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5cd29ed0
HW		 3310 link->type != dc_connection_none &&
3311 dm->backlight_dev) {
3312 backlight_device_unregister(dm->backlight_dev);
3313 dm->backlight_dev = NULL;
e7b07cee
HW		 3314 }
3315#endif
dcd5fb82
MF		 3316
3317 if (aconnector->dc_em_sink)
3318 dc_sink_release(aconnector->dc_em_sink);
3319 aconnector->dc_em_sink = NULL;
3320 if (aconnector->dc_sink)
3321 dc_sink_release(aconnector->dc_sink);
3322 aconnector->dc_sink = NULL;
3323
e86e8947 3324 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
e7b07cee
HW		 3325 drm_connector_unregister(connector);
3326 drm_connector_cleanup(connector);
3327 kfree(connector);
3328}
3329
3330void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3331{
3332 struct dm_connector_state *state =
3333 to_dm_connector_state(connector->state);
3334
df099b9b
LSL		 3335 if (connector->state)
3336 __drm_atomic_helper_connector_destroy_state(connector->state);
3337
e7b07cee
HW		 3338 kfree(state);
3339
3340 state = kzalloc(sizeof(*state), GFP_KERNEL);
3341
3342 if (state) {
3343 state->scaling = RMX_OFF;
3344 state->underscan_enable = false;
3345 state->underscan_hborder = 0;
3346 state->underscan_vborder = 0;
49f1c44b 3347 state->max_bpc = 8;
e7b07cee 3348
df099b9b 3349 __drm_atomic_helper_connector_reset(connector, &state->base);
e7b07cee
HW		 3350 }
3351}
3352
3ee6b26b
AD		 3353struct drm_connector_state *
3354amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
e7b07cee
HW		 3355{
3356 struct dm_connector_state *state =
3357 to_dm_connector_state(connector->state);
3358
3359 struct dm_connector_state *new_state =
3360 kmemdup(state, sizeof(*state), GFP_KERNEL);
3361
98e6436d
AK		 3362 if (!new_state)
3363 return NULL;
e7b07cee 3364
98e6436d
AK		 3365 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3366
3367 new_state->freesync_capable = state->freesync_capable;
c1ee92f9 3368 new_state->abm_level = state->abm_level;
922454c2
NK		 3369 new_state->scaling = state->scaling;
3370 new_state->underscan_enable = state->underscan_enable;
3371 new_state->underscan_hborder = state->underscan_hborder;
3372 new_state->underscan_vborder = state->underscan_vborder;
49f1c44b 3373 new_state->max_bpc = state->max_bpc;
98e6436d
AK		 3374
3375 return &new_state->base;
e7b07cee
HW		 3376}
3377
3378static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3379 .reset = amdgpu_dm_connector_funcs_reset,
3380 .detect = amdgpu_dm_connector_detect,
3381 .fill_modes = drm_helper_probe_single_connector_modes,
3382 .destroy = amdgpu_dm_connector_destroy,
3383 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3384 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3385 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3386 .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3387};
3388
e7b07cee
HW		 3389static int get_modes(struct drm_connector *connector)
3390{
3391 return amdgpu_dm_connector_get_modes(connector);
3392}
3393
c84dec2f 3394static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3395{
3396 struct dc_sink_init_data init_params = {
3397 .link = aconnector->dc_link,
3398 .sink_signal = SIGNAL_TYPE_VIRTUAL
3399 };
70e8ffc5 3400 struct edid *edid;
e7b07cee 3401
a89ff457 3402 if (!aconnector->base.edid_blob_ptr) {
e7b07cee
HW		 3403 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3404 aconnector->base.name);
3405
3406 aconnector->base.force = DRM_FORCE_OFF;
3407 aconnector->base.override_edid = false;
3408 return;
3409 }
3410
70e8ffc5
HW		 3411 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3412
e7b07cee
HW		 3413 aconnector->edid = edid;
3414
3415 aconnector->dc_em_sink = dc_link_add_remote_sink(
3416 aconnector->dc_link,
3417 (uint8_t *)edid,
3418 (edid->extensions + 1) * EDID_LENGTH,
3419 &init_params);
3420
dcd5fb82 3421 if (aconnector->base.force == DRM_FORCE_ON) {
e7b07cee
HW		 3422 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3423 aconnector->dc_link->local_sink :
3424 aconnector->dc_em_sink;
dcd5fb82
MF		 3425 dc_sink_retain(aconnector->dc_sink);
3426 }
e7b07cee
HW		 3427}
3428
c84dec2f 3429static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
e7b07cee
HW		 3430{
3431 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3432
1f6010a9
DF		 3433 /*
3434 * In case of headless boot with force on for DP managed connector
e7b07cee
HW		 3435 * Those settings have to be != 0 to get initial modeset
3436 */
3437 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3438 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3439 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3440 }
3441
3442
3443 aconnector->base.override_edid = true;
3444 create_eml_sink(aconnector);
3445}
3446
ba9ca088 3447enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3ee6b26b 3448 struct drm_display_mode *mode)
e7b07cee
HW		 3449{
3450 int result = MODE_ERROR;
3451 struct dc_sink *dc_sink;
3452 struct amdgpu_device *adev = connector->dev->dev_private;
3453 /* TODO: Unhardcode stream count */
0971c40e 3454 struct dc_stream_state *stream;
c84dec2f 3455 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
a39438f0 3456 enum dc_status dc_result = DC_OK;
e7b07cee
HW		 3457
3458 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3459 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3460 return result;
3461
1f6010a9
DF		 3462 /*
3463 * Only run this the first time mode_valid is called to initilialize
e7b07cee
HW		 3464 * EDID mgmt
3465 */
3466 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3467 !aconnector->dc_em_sink)
3468 handle_edid_mgmt(aconnector);
3469
c84dec2f 3470 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
e7b07cee 3471
b830ebc9 3472 if (dc_sink == NULL) {
e7b07cee
HW		 3473 DRM_ERROR("dc_sink is NULL!\n");
3474 goto fail;
3475 }
3476
b333730d 3477 stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
b830ebc9 3478 if (stream == NULL) {
e7b07cee
HW		 3479 DRM_ERROR("Failed to create stream for sink!\n");
3480 goto fail;
3481 }
3482
a39438f0
HW		 3483 dc_result = dc_validate_stream(adev->dm.dc, stream);
3484
3485 if (dc_result == DC_OK)
e7b07cee 3486 result = MODE_OK;
a39438f0 3487 else
9f921b14 3488 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
a39438f0
HW		 3489 mode->vdisplay,
3490 mode->hdisplay,
9f921b14
HW		 3491 mode->clock,
3492 dc_result);
e7b07cee
HW		 3493
3494 dc_stream_release(stream);
3495
3496fail:
3497 /* TODO: error handling*/
3498 return result;
3499}
3500
3501static const struct drm_connector_helper_funcs
3502amdgpu_dm_connector_helper_funcs = {
3503 /*
1f6010a9 3504 * If hotplugging a second bigger display in FB Con mode, bigger resolution
b830ebc9 3505 * modes will be filtered by drm_mode_validate_size(), and those modes
1f6010a9 3506 * are missing after user start lightdm. So we need to renew modes list.
b830ebc9
HW		 3507 * in get_modes call back, not just return the modes count
3508 */
e7b07cee
HW		 3509 .get_modes = get_modes,
3510 .mode_valid = amdgpu_dm_connector_mode_valid,
e7b07cee
HW		 3511};
3512
3513static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3514{
3515}
3516
3ee6b26b
AD		 3517static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3518 struct drm_crtc_state *state)
e7b07cee
HW		 3519{
3520 struct amdgpu_device *adev = crtc->dev->dev_private;
3521 struct dc *dc = adev->dm.dc;
3522 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3523 int ret = -EINVAL;
3524
9b690ef3
BL		 3525 if (unlikely(!dm_crtc_state->stream &&
3526 modeset_required(state, NULL, dm_crtc_state->stream))) {
e7b07cee
HW		 3527 WARN_ON(1);
3528 return ret;
3529 }
3530
1f6010a9 3531 /* In some use cases, like reset, no stream is attached */
e7b07cee
HW		 3532 if (!dm_crtc_state->stream)
3533 return 0;
3534
62c933f9 3535 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
e7b07cee
HW		 3536 return 0;
3537
3538 return ret;
3539}
3540
3ee6b26b
AD		 3541static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
3542 const struct drm_display_mode *mode,
3543 struct drm_display_mode *adjusted_mode)
e7b07cee
HW		 3544{
3545 return true;
3546}
3547
3548static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
3549 .disable = dm_crtc_helper_disable,
3550 .atomic_check = dm_crtc_helper_atomic_check,
3551 .mode_fixup = dm_crtc_helper_mode_fixup
3552};
3553
3554static void dm_encoder_helper_disable(struct drm_encoder *encoder)
3555{
3556
3557}
3558
3ee6b26b
AD		 3559static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
3560 struct drm_crtc_state *crtc_state,
3561 struct drm_connector_state *conn_state)
e7b07cee
HW		 3562{
3563 return 0;
3564}
3565
3566const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
3567 .disable = dm_encoder_helper_disable,
3568 .atomic_check = dm_encoder_helper_atomic_check
3569};
3570
3571static void dm_drm_plane_reset(struct drm_plane *plane)
3572{
3573 struct dm_plane_state *amdgpu_state = NULL;
3574
3575 if (plane->state)
3576 plane->funcs->atomic_destroy_state(plane, plane->state);
3577
3578 amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
f922237d 3579 WARN_ON(amdgpu_state == NULL);
1f6010a9 3580
e7b07cee
HW		 3581 if (amdgpu_state) {
3582 plane->state = &amdgpu_state->base;
3583 plane->state->plane = plane;
3584 plane->state->rotation = DRM_MODE_ROTATE_0;
f922237d 3585 }
e7b07cee
HW		 3586}
3587
3588static struct drm_plane_state *
3589dm_drm_plane_duplicate_state(struct drm_plane *plane)
3590{
3591 struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
3592
3593 old_dm_plane_state = to_dm_plane_state(plane->state);
3594 dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
3595 if (!dm_plane_state)
3596 return NULL;
3597
3598 __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
3599
3be5262e
HW		 3600 if (old_dm_plane_state->dc_state) {
3601 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
3602 dc_plane_state_retain(dm_plane_state->dc_state);
e7b07cee
HW		 3603 }
3604
3605 return &dm_plane_state->base;
3606}
3607
3608void dm_drm_plane_destroy_state(struct drm_plane *plane,
3ee6b26b 3609 struct drm_plane_state *state)
e7b07cee
HW		 3610{
3611 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3612
3be5262e
HW		 3613 if (dm_plane_state->dc_state)
3614 dc_plane_state_release(dm_plane_state->dc_state);
e7b07cee 3615
0627bbd3 3616 drm_atomic_helper_plane_destroy_state(plane, state);
e7b07cee
HW		 3617}
3618
3619static const struct drm_plane_funcs dm_plane_funcs = {
3620 .update_plane = drm_atomic_helper_update_plane,
3621 .disable_plane = drm_atomic_helper_disable_plane,
02680efb 3622 .destroy = drm_primary_helper_destroy,
e7b07cee
HW		 3623 .reset = dm_drm_plane_reset,
3624 .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3625 .atomic_destroy_state = dm_drm_plane_destroy_state,
3626};
3627
3ee6b26b
AD		 3628static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3629 struct drm_plane_state *new_state)
e7b07cee
HW		 3630{
3631 struct amdgpu_framebuffer *afb;
3632 struct drm_gem_object *obj;
5d43be0c 3633 struct amdgpu_device *adev;
e7b07cee 3634 struct amdgpu_bo *rbo;
56087b31 3635 uint64_t chroma_addr = 0;
e7b07cee 3636 struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
7df7e505 3637 uint64_t tiling_flags, dcc_address;
e7b07cee 3638 unsigned int awidth;
5d43be0c
CK		 3639 uint32_t domain;
3640 int r;
e7b07cee
HW		 3641
3642 dm_plane_state_old = to_dm_plane_state(plane->state);
3643 dm_plane_state_new = to_dm_plane_state(new_state);
3644
3645 if (!new_state->fb) {
f1ad2f5e 3646 DRM_DEBUG_DRIVER("No FB bound\n");
e7b07cee
HW		 3647 return 0;
3648 }
3649
3650 afb = to_amdgpu_framebuffer(new_state->fb);
e68d14dd 3651 obj = new_state->fb->obj[0];
e7b07cee 3652 rbo = gem_to_amdgpu_bo(obj);
5d43be0c 3653 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
e7b07cee
HW		 3654 r = amdgpu_bo_reserve(rbo, false);
3655 if (unlikely(r != 0))
3656 return r;
3657
5d43be0c 3658 if (plane->type != DRM_PLANE_TYPE_CURSOR)
1d2361e5 3659 domain = amdgpu_display_supported_domains(adev);
5d43be0c
CK		 3660 else
3661 domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07cee 3662
7b7c6c81 3663 r = amdgpu_bo_pin(rbo, domain);
e7b07cee 3664 if (unlikely(r != 0)) {
30b7c614
HW		 3665 if (r != -ERESTARTSYS)
3666 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
bb812f1e 3667 amdgpu_bo_unreserve(rbo);
e7b07cee
HW		 3668 return r;
3669 }
3670
bb812f1e
JZ		 3671 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
3672 if (unlikely(r != 0)) {
3673 amdgpu_bo_unpin(rbo);
3674 amdgpu_bo_unreserve(rbo);
3675 DRM_ERROR("%p bind failed\n", rbo);
e7b07cee
HW		 3676 return r;
3677 }
7df7e505
NK		 3678
3679 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
3680
bb812f1e
JZ		 3681 amdgpu_bo_unreserve(rbo);
3682
7b7c6c81 3683 afb->address = amdgpu_bo_gpu_offset(rbo);
e7b07cee
HW		 3684
3685 amdgpu_bo_ref(rbo);
3686
3be5262e
HW		 3687 if (dm_plane_state_new->dc_state &&
3688 dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3689 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
e7b07cee 3690
3be5262e
HW		 3691 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3692 plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3693 plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
7df7e505
NK		 3694
3695 dcc_address =
3696 get_dcc_address(afb->address, tiling_flags);
3697 plane_state->address.grph.meta_addr.low_part =
3698 lower_32_bits(dcc_address);
3699 plane_state->address.grph.meta_addr.high_part =
3700 upper_32_bits(dcc_address);
e7b07cee
HW		 3701 } else {
3702 awidth = ALIGN(new_state->fb->width, 64);
56087b31 3703 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3be5262e 3704 plane_state->address.video_progressive.luma_addr.low_part
e7b07cee 3705 = lower_32_bits(afb->address);
56087b31
S		 3706 plane_state->address.video_progressive.luma_addr.high_part
3707 = upper_32_bits(afb->address);
35888630 3708 chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3be5262e 3709 plane_state->address.video_progressive.chroma_addr.low_part
56087b31
S		 3710 = lower_32_bits(chroma_addr);
3711 plane_state->address.video_progressive.chroma_addr.high_part
3712 = upper_32_bits(chroma_addr);
e7b07cee
HW		 3713 }
3714 }
3715
e7b07cee
HW		 3716 return 0;
3717}
3718
3ee6b26b
AD		 3719static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3720 struct drm_plane_state *old_state)
e7b07cee
HW		 3721{
3722 struct amdgpu_bo *rbo;
e7b07cee
HW		 3723 int r;
3724
3725 if (!old_state->fb)
3726 return;
3727
e68d14dd 3728 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
e7b07cee
HW		 3729 r = amdgpu_bo_reserve(rbo, false);
3730 if (unlikely(r)) {
3731 DRM_ERROR("failed to reserve rbo before unpin\n");
3732 return;
b830ebc9
HW		 3733 }
3734
3735 amdgpu_bo_unpin(rbo);
3736 amdgpu_bo_unreserve(rbo);
3737 amdgpu_bo_unref(&rbo);
e7b07cee
HW		 3738}
3739
7578ecda
AD		 3740static int dm_plane_atomic_check(struct drm_plane *plane,
3741 struct drm_plane_state *state)
cbd19488
AG		 3742{
3743 struct amdgpu_device *adev = plane->dev->dev_private;
3744 struct dc *dc = adev->dm.dc;
3745 struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3746
3be5262e 3747 if (!dm_plane_state->dc_state)
9a3329b1 3748 return 0;
cbd19488 3749
a05bcff1
S		 3750 if (!fill_rects_from_plane_state(state, dm_plane_state->dc_state))
3751 return -EINVAL;
3752
62c933f9 3753 if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
cbd19488
AG		 3754 return 0;
3755
3756 return -EINVAL;
3757}
3758
674e78ac
NK		 3759static int dm_plane_atomic_async_check(struct drm_plane *plane,
3760 struct drm_plane_state *new_plane_state)
3761{
77acd1cd
NK		 3762 struct drm_plane_state *old_plane_state =
3763 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
3764
674e78ac
NK		 3765 /* Only support async updates on cursor planes. */
3766 if (plane->type != DRM_PLANE_TYPE_CURSOR)
3767 return -EINVAL;
3768
77acd1cd
NK		 3769 /*
3770 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
3771 * async commits so don't allow fb changes.
3772 */
3773 if (old_plane_state->fb != new_plane_state->fb)
3774 return -EINVAL;
3775
674e78ac
NK		 3776 return 0;
3777}
3778
3779static void dm_plane_atomic_async_update(struct drm_plane *plane,
3780 struct drm_plane_state *new_state)
3781{
3782 struct drm_plane_state *old_state =
3783 drm_atomic_get_old_plane_state(new_state->state, plane);
3784
3785 if (plane->state->fb != new_state->fb)
3786 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
3787
3788 plane->state->src_x = new_state->src_x;
3789 plane->state->src_y = new_state->src_y;
3790 plane->state->src_w = new_state->src_w;
3791 plane->state->src_h = new_state->src_h;
3792 plane->state->crtc_x = new_state->crtc_x;
3793 plane->state->crtc_y = new_state->crtc_y;
3794 plane->state->crtc_w = new_state->crtc_w;
3795 plane->state->crtc_h = new_state->crtc_h;
3796
3797 handle_cursor_update(plane, old_state);
3798}
3799
e7b07cee
HW		 3800static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3801 .prepare_fb = dm_plane_helper_prepare_fb,
3802 .cleanup_fb = dm_plane_helper_cleanup_fb,
cbd19488 3803 .atomic_check = dm_plane_atomic_check,
674e78ac
NK		 3804 .atomic_async_check = dm_plane_atomic_async_check,
3805 .atomic_async_update = dm_plane_atomic_async_update
e7b07cee
HW		 3806};
3807
3808/*
3809 * TODO: these are currently initialized to rgb formats only.
3810 * For future use cases we should either initialize them dynamically based on
3811 * plane capabilities, or initialize this array to all formats, so internal drm
1f6010a9 3812 * check will succeed, and let DC implement proper check
e7b07cee 3813 */
d90371b0 3814static const uint32_t rgb_formats[] = {
e7b07cee
HW		 3815 DRM_FORMAT_XRGB8888,
3816 DRM_FORMAT_ARGB8888,
3817 DRM_FORMAT_RGBA8888,
3818 DRM_FORMAT_XRGB2101010,
3819 DRM_FORMAT_XBGR2101010,
3820 DRM_FORMAT_ARGB2101010,
3821 DRM_FORMAT_ABGR2101010,
bcd47f60
MR		 3822 DRM_FORMAT_XBGR8888,
3823 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3824};
3825
0d579c7e
NK		 3826static const uint32_t overlay_formats[] = {
3827 DRM_FORMAT_XRGB8888,
3828 DRM_FORMAT_ARGB8888,
3829 DRM_FORMAT_RGBA8888,
3830 DRM_FORMAT_XBGR8888,
3831 DRM_FORMAT_ABGR8888,
e7b07cee
HW		 3832};
3833
3834static const u32 cursor_formats[] = {
3835 DRM_FORMAT_ARGB8888
3836};
3837
7578ecda 3838static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
f180b4bc 3839 struct drm_plane *plane,
7578ecda 3840 unsigned long possible_crtcs)
e7b07cee
HW		 3841{
3842 int res = -EPERM;
3843
f180b4bc 3844 switch (plane->type) {
e7b07cee 3845 case DRM_PLANE_TYPE_PRIMARY:
e7b07cee
HW		 3846 res = drm_universal_plane_init(
3847 dm->adev->ddev,
f180b4bc 3848 plane,
e7b07cee
HW		 3849 possible_crtcs,
3850 &dm_plane_funcs,
3851 rgb_formats,
3852 ARRAY_SIZE(rgb_formats),
f180b4bc 3853 NULL, plane->type, NULL);
e7b07cee
HW		 3854 break;
3855 case DRM_PLANE_TYPE_OVERLAY:
3856 res = drm_universal_plane_init(
3857 dm->adev->ddev,
f180b4bc 3858 plane,
e7b07cee
HW		 3859 possible_crtcs,
3860 &dm_plane_funcs,
0d579c7e
NK		 3861 overlay_formats,
3862 ARRAY_SIZE(overlay_formats),
f180b4bc 3863 NULL, plane->type, NULL);
e7b07cee
HW		 3864 break;
3865 case DRM_PLANE_TYPE_CURSOR:
3866 res = drm_universal_plane_init(
3867 dm->adev->ddev,
f180b4bc 3868 plane,
e7b07cee
HW		 3869 possible_crtcs,
3870 &dm_plane_funcs,
3871 cursor_formats,
3872 ARRAY_SIZE(cursor_formats),
f180b4bc 3873 NULL, plane->type, NULL);
e7b07cee
HW		 3874 break;
3875 }
3876
f180b4bc 3877 drm_plane_helper_add(plane, &dm_plane_helper_funcs);
e7b07cee 3878
96719c54 3879 /* Create (reset) the plane state */
f180b4bc
HW		 3880 if (plane->funcs->reset)
3881 plane->funcs->reset(plane);
96719c54
HW		 3882
3883
e7b07cee
HW		 3884 return res;
3885}
3886
7578ecda
AD		 3887static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3888 struct drm_plane *plane,
3889 uint32_t crtc_index)
e7b07cee
HW		 3890{
3891 struct amdgpu_crtc *acrtc = NULL;
f180b4bc 3892 struct drm_plane *cursor_plane;
e7b07cee
HW		 3893
3894 int res = -ENOMEM;
3895
3896 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3897 if (!cursor_plane)
3898 goto fail;
3899
f180b4bc 3900 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
e7b07cee
HW		 3901 res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3902
3903 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3904 if (!acrtc)
3905 goto fail;
3906
3907 res = drm_crtc_init_with_planes(
3908 dm->ddev,
3909 &acrtc->base,
3910 plane,
f180b4bc 3911 cursor_plane,
e7b07cee
HW		 3912 &amdgpu_dm_crtc_funcs, NULL);
3913
3914 if (res)
3915 goto fail;
3916
3917 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3918
96719c54
HW		 3919 /* Create (reset) the plane state */
3920 if (acrtc->base.funcs->reset)
3921 acrtc->base.funcs->reset(&acrtc->base);
3922
e7b07cee
HW		 3923 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3924 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3925
3926 acrtc->crtc_id = crtc_index;
3927 acrtc->base.enabled = false;
c37e2d29 3928 acrtc->otg_inst = -1;
e7b07cee
HW		 3929
3930 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
236d0e4f
LSL		 3931 drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3932 true, MAX_COLOR_LUT_ENTRIES);
086247a4 3933 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
e7b07cee
HW		 3934
3935 return 0;
3936
3937fail:
b830ebc9
HW		 3938 kfree(acrtc);
3939 kfree(cursor_plane);
e7b07cee
HW		 3940 return res;
3941}
3942
3943
3944static int to_drm_connector_type(enum signal_type st)
3945{
3946 switch (st) {
3947 case SIGNAL_TYPE_HDMI_TYPE_A:
3948 return DRM_MODE_CONNECTOR_HDMIA;
3949 case SIGNAL_TYPE_EDP:
3950 return DRM_MODE_CONNECTOR_eDP;
11c3ee48
AD		 3951 case SIGNAL_TYPE_LVDS:
3952 return DRM_MODE_CONNECTOR_LVDS;
e7b07cee
HW		 3953 case SIGNAL_TYPE_RGB:
3954 return DRM_MODE_CONNECTOR_VGA;
3955 case SIGNAL_TYPE_DISPLAY_PORT:
3956 case SIGNAL_TYPE_DISPLAY_PORT_MST:
3957 return DRM_MODE_CONNECTOR_DisplayPort;
3958 case SIGNAL_TYPE_DVI_DUAL_LINK:
3959 case SIGNAL_TYPE_DVI_SINGLE_LINK:
3960 return DRM_MODE_CONNECTOR_DVID;
3961 case SIGNAL_TYPE_VIRTUAL:
3962 return DRM_MODE_CONNECTOR_VIRTUAL;
3963
3964 default:
3965 return DRM_MODE_CONNECTOR_Unknown;
3966 }
3967}
3968
2b4c1c05
DV		 3969static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
3970{
3971 return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
3972}
3973
e7b07cee
HW		 3974static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3975{
e7b07cee
HW		 3976 struct drm_encoder *encoder;
3977 struct amdgpu_encoder *amdgpu_encoder;
3978
2b4c1c05 3979 encoder = amdgpu_dm_connector_to_encoder(connector);
e7b07cee
HW		 3980
3981 if (encoder == NULL)
3982 return;
3983
3984 amdgpu_encoder = to_amdgpu_encoder(encoder);
3985
3986 amdgpu_encoder->native_mode.clock = 0;
3987
3988 if (!list_empty(&connector->probed_modes)) {
3989 struct drm_display_mode *preferred_mode = NULL;
b830ebc9 3990
e7b07cee 3991 list_for_each_entry(preferred_mode,
b830ebc9
HW		 3992 &connector->probed_modes,
3993 head) {
3994 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3995 amdgpu_encoder->native_mode = *preferred_mode;
3996
e7b07cee
HW		 3997 break;
3998 }
3999
4000 }
4001}
4002
3ee6b26b
AD		 4003static struct drm_display_mode *
4004amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4005 char *name,
4006 int hdisplay, int vdisplay)
e7b07cee
HW		 4007{
4008 struct drm_device *dev = encoder->dev;
4009 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4010 struct drm_display_mode *mode = NULL;
4011 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4012
4013 mode = drm_mode_duplicate(dev, native_mode);
4014
b830ebc9 4015 if (mode == NULL)
e7b07cee
HW		 4016 return NULL;
4017
4018 mode->hdisplay = hdisplay;
4019 mode->vdisplay = vdisplay;
4020 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
090afc1e 4021 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
e7b07cee
HW		 4022
4023 return mode;
4024
4025}
4026
4027static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3ee6b26b 4028 struct drm_connector *connector)
e7b07cee
HW		 4029{
4030 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4031 struct drm_display_mode *mode = NULL;
4032 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
c84dec2f
HW		 4033 struct amdgpu_dm_connector *amdgpu_dm_connector =
4034 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4035 int i;
4036 int n;
4037 struct mode_size {
4038 char name[DRM_DISPLAY_MODE_LEN];
4039 int w;
4040 int h;
b830ebc9 4041 } common_modes[] = {
e7b07cee
HW		 4042 { "640x480", 640, 480},
4043 { "800x600", 800, 600},
4044 { "1024x768", 1024, 768},
4045 { "1280x720", 1280, 720},
4046 { "1280x800", 1280, 800},
4047 {"1280x1024", 1280, 1024},
4048 { "1440x900", 1440, 900},
4049 {"1680x1050", 1680, 1050},
4050 {"1600x1200", 1600, 1200},
4051 {"1920x1080", 1920, 1080},
4052 {"1920x1200", 1920, 1200}
4053 };
4054
b830ebc9 4055 n = ARRAY_SIZE(common_modes);
e7b07cee
HW		 4056
4057 for (i = 0; i < n; i++) {
4058 struct drm_display_mode *curmode = NULL;
4059 bool mode_existed = false;
4060
4061 if (common_modes[i].w > native_mode->hdisplay ||
b830ebc9
HW		 4062 common_modes[i].h > native_mode->vdisplay ||
4063 (common_modes[i].w == native_mode->hdisplay &&
4064 common_modes[i].h == native_mode->vdisplay))
4065 continue;
e7b07cee
HW		 4066
4067 list_for_each_entry(curmode, &connector->probed_modes, head) {
4068 if (common_modes[i].w == curmode->hdisplay &&
b830ebc9 4069 common_modes[i].h == curmode->vdisplay) {
e7b07cee
HW		 4070 mode_existed = true;
4071 break;
4072 }
4073 }
4074
4075 if (mode_existed)
4076 continue;
4077
4078 mode = amdgpu_dm_create_common_mode(encoder,
4079 common_modes[i].name, common_modes[i].w,
4080 common_modes[i].h);
4081 drm_mode_probed_add(connector, mode);
c84dec2f 4082 amdgpu_dm_connector->num_modes++;
e7b07cee
HW		 4083 }
4084}
4085
3ee6b26b
AD		 4086static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4087 struct edid *edid)
e7b07cee 4088{
c84dec2f
HW		 4089 struct amdgpu_dm_connector *amdgpu_dm_connector =
4090 to_amdgpu_dm_connector(connector);
e7b07cee
HW		 4091
4092 if (edid) {
4093 /* empty probed_modes */
4094 INIT_LIST_HEAD(&connector->probed_modes);
c84dec2f 4095 amdgpu_dm_connector->num_modes =
e7b07cee
HW		 4096 drm_add_edid_modes(connector, edid);
4097
e7b07cee 4098 amdgpu_dm_get_native_mode(connector);
a8d8d3dc 4099 } else {
c84dec2f 4100 amdgpu_dm_connector->num_modes = 0;
a8d8d3dc 4101 }
e7b07cee
HW		 4102}
4103
7578ecda 4104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
e7b07cee 4105{
c84dec2f
HW		 4106 struct amdgpu_dm_connector *amdgpu_dm_connector =
4107 to_amdgpu_dm_connector(connector);
e7b07cee 4108 struct drm_encoder *encoder;
c84dec2f 4109 struct edid *edid = amdgpu_dm_connector->edid;
e7b07cee 4110
2b4c1c05 4111 encoder = amdgpu_dm_connector_to_encoder(connector);
3e332d3a 4112
85ee15d6 4113 if (!edid || !drm_edid_is_valid(edid)) {
1b369d3c
ML		 4114 amdgpu_dm_connector->num_modes =
4115 drm_add_modes_noedid(connector, 640, 480);
85ee15d6
ML		 4116 } else {
4117 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4118 amdgpu_dm_connector_add_common_modes(encoder, connector);
4119 }
3e332d3a 4120 amdgpu_dm_fbc_init(connector);
5099114b 4121
c84dec2f 4122 return amdgpu_dm_connector->num_modes;
e7b07cee
HW		 4123}
4124
3ee6b26b
AD		 4125void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4126 struct amdgpu_dm_connector *aconnector,
4127 int connector_type,
4128 struct dc_link *link,
4129 int link_index)
e7b07cee
HW		 4130{
4131 struct amdgpu_device *adev = dm->ddev->dev_private;
4132
4133 aconnector->connector_id = link_index;
4134 aconnector->dc_link = link;
4135 aconnector->base.interlace_allowed = false;
4136 aconnector->base.doublescan_allowed = false;
4137 aconnector->base.stereo_allowed = false;
4138 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4139 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
e7b07cee
HW		 4140 mutex_init(&aconnector->hpd_lock);
4141
1f6010a9
DF		 4142 /*
4143 * configure support HPD hot plug connector_>polled default value is 0
b830ebc9
HW		 4144 * which means HPD hot plug not supported
4145 */
e7b07cee
HW		 4146 switch (connector_type) {
4147 case DRM_MODE_CONNECTOR_HDMIA:
4148 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4149 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4150 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
e7b07cee
HW		 4151 break;
4152 case DRM_MODE_CONNECTOR_DisplayPort:
4153 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
e7baae1c 4154 aconnector->base.ycbcr_420_allowed =
9ea59d5a 4155 link->link_enc->features.dp_ycbcr420_supported ? true : false;
e7b07cee
HW		 4156 break;
4157 case DRM_MODE_CONNECTOR_DVID:
4158 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4159 break;
4160 default:
4161 break;
4162 }
4163
4164 drm_object_attach_property(&aconnector->base.base,
4165 dm->ddev->mode_config.scaling_mode_property,
4166 DRM_MODE_SCALE_NONE);
4167
4168 drm_object_attach_property(&aconnector->base.base,
4169 adev->mode_info.underscan_property,
4170 UNDERSCAN_OFF);
4171 drm_object_attach_property(&aconnector->base.base,
4172 adev->mode_info.underscan_hborder_property,
4173 0);
4174 drm_object_attach_property(&aconnector->base.base,
4175 adev->mode_info.underscan_vborder_property,
4176 0);
07e3a1cf
NK		 4177 drm_object_attach_property(&aconnector->base.base,
4178 adev->mode_info.max_bpc_property,
4179 0);
e7b07cee 4180
c1ee92f9
DF		 4181 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4182 dc_is_dmcu_initialized(adev->dm.dc)) {
4183 drm_object_attach_property(&aconnector->base.base,
4184 adev->mode_info.abm_level_property, 0);
4185 }
bb47de73
NK		 4186
4187 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7fad8da1
NK		 4188 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4189 connector_type == DRM_MODE_CONNECTOR_eDP) {
bb47de73
NK		 4190 drm_connector_attach_vrr_capable_property(
4191 &aconnector->base);
4192 }
e7b07cee
HW		 4193}
4194
7578ecda
AD		 4195static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4196 struct i2c_msg *msgs, int num)
e7b07cee
HW		 4197{
4198 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4199 struct ddc_service *ddc_service = i2c->ddc_service;
4200 struct i2c_command cmd;
4201 int i;
4202 int result = -EIO;
4203
b830ebc9 4204 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
e7b07cee
HW		 4205
4206 if (!cmd.payloads)
4207 return result;
4208
4209 cmd.number_of_payloads = num;
4210 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4211 cmd.speed = 100;
4212
4213 for (i = 0; i < num; i++) {
4214 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4215 cmd.payloads[i].address = msgs[i].addr;
4216 cmd.payloads[i].length = msgs[i].len;
4217 cmd.payloads[i].data = msgs[i].buf;
4218 }
4219
c85e6e54
DF		 4220 if (dc_submit_i2c(
4221 ddc_service->ctx->dc,
4222 ddc_service->ddc_pin->hw_info.ddc_channel,
e7b07cee
HW		 4223 &cmd))
4224 result = num;
4225
4226 kfree(cmd.payloads);
4227 return result;
4228}
4229
7578ecda 4230static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
e7b07cee
HW		 4231{
4232 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4233}
4234
4235static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4236 .master_xfer = amdgpu_dm_i2c_xfer,
4237 .functionality = amdgpu_dm_i2c_func,
4238};
4239
3ee6b26b
AD		 4240static struct amdgpu_i2c_adapter *
4241create_i2c(struct ddc_service *ddc_service,
4242 int link_index,
4243 int *res)
e7b07cee
HW		 4244{
4245 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4246 struct amdgpu_i2c_adapter *i2c;
4247
b830ebc9 4248 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
2a55f096
ES		 4249 if (!i2c)
4250 return NULL;
e7b07cee
HW		 4251 i2c->base.owner = THIS_MODULE;
4252 i2c->base.class = I2C_CLASS_DDC;
4253 i2c->base.dev.parent = &adev->pdev->dev;
4254 i2c->base.algo = &amdgpu_dm_i2c_algo;
b830ebc9 4255 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
e7b07cee
HW		 4256 i2c_set_adapdata(&i2c->base, i2c);
4257 i2c->ddc_service = ddc_service;
c85e6e54 4258 i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
e7b07cee
HW		 4259
4260 return i2c;
4261}
4262
89fc8d4e 4263
1f6010a9
DF		 4264/*
4265 * Note: this function assumes that dc_link_detect() was called for the
b830ebc9
HW		 4266 * dc_link which will be represented by this aconnector.
4267 */
7578ecda
AD		 4268static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4269 struct amdgpu_dm_connector *aconnector,
4270 uint32_t link_index,
4271 struct amdgpu_encoder *aencoder)
e7b07cee
HW		 4272{
4273 int res = 0;
4274 int connector_type;
4275 struct dc *dc = dm->dc;
4276 struct dc_link *link = dc_get_link_at_index(dc, link_index);
4277 struct amdgpu_i2c_adapter *i2c;
9a227d26
TSD		 4278
4279 link->priv = aconnector;
e7b07cee 4280
f1ad2f5e 4281 DRM_DEBUG_DRIVER("%s()\n", __func__);
e7b07cee
HW		 4282
4283 i2c = create_i2c(link->ddc, link->link_index, &res);
2a55f096
ES		 4284 if (!i2c) {
4285 DRM_ERROR("Failed to create i2c adapter data\n");
4286 return -ENOMEM;
4287 }
4288
e7b07cee
HW		 4289 aconnector->i2c = i2c;
4290 res = i2c_add_adapter(&i2c->base);
4291
4292 if (res) {
4293 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4294 goto out_free;
4295 }
4296
4297 connector_type = to_drm_connector_type(link->connector_signal);
4298
4299 res = drm_connector_init(
4300 dm->ddev,
4301 &aconnector->base,
4302 &amdgpu_dm_connector_funcs,
4303 connector_type);
4304
4305 if (res) {
4306 DRM_ERROR("connector_init failed\n");
4307 aconnector->connector_id = -1;
4308 goto out_free;
4309 }
4310
4311 drm_connector_helper_add(
4312 &aconnector->base,
4313 &amdgpu_dm_connector_helper_funcs);
4314
96719c54
HW		 4315 if (aconnector->base.funcs->reset)
4316 aconnector->base.funcs->reset(&aconnector->base);
4317
e7b07cee
HW		 4318 amdgpu_dm_connector_init_helper(
4319 dm,
4320 aconnector,
4321 connector_type,
4322 link,
4323 link_index);
4324
cde4c44d 4325 drm_connector_attach_encoder(
e7b07cee
HW		 4326 &aconnector->base, &aencoder->base);
4327
4328 drm_connector_register(&aconnector->base);
dc38fd9d
DF		 4329#if defined(CONFIG_DEBUG_FS)
4330 res = connector_debugfs_init(aconnector);
4331 if (res) {
4332 DRM_ERROR("Failed to create debugfs for connector");
4333 goto out_free;
4334 }
4335#endif
e7b07cee
HW		 4336
4337 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4338 || connector_type == DRM_MODE_CONNECTOR_eDP)
4339 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4340
e7b07cee
HW		 4341out_free:
4342 if (res) {
4343 kfree(i2c);
4344 aconnector->i2c = NULL;
4345 }
4346 return res;
4347}
4348
4349int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4350{
4351 switch (adev->mode_info.num_crtc) {
4352 case 1:
4353 return 0x1;
4354 case 2:
4355 return 0x3;
4356 case 3:
4357 return 0x7;
4358 case 4:
4359 return 0xf;
4360 case 5:
4361 return 0x1f;
4362 case 6:
4363 default:
4364 return 0x3f;
4365 }
4366}
4367
7578ecda
AD		 4368static int amdgpu_dm_encoder_init(struct drm_device *dev,
4369 struct amdgpu_encoder *aencoder,
4370 uint32_t link_index)
e7b07cee
HW		 4371{
4372 struct amdgpu_device *adev = dev->dev_private;
4373
4374 int res = drm_encoder_init(dev,
4375 &aencoder->base,
4376 &amdgpu_dm_encoder_funcs,
4377 DRM_MODE_ENCODER_TMDS,
4378 NULL);
4379
4380 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4381
4382 if (!res)
4383 aencoder->encoder_id = link_index;
4384 else
4385 aencoder->encoder_id = -1;
4386
4387 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4388
4389 return res;
4390}
4391
3ee6b26b
AD		 4392static void manage_dm_interrupts(struct amdgpu_device *adev,
4393 struct amdgpu_crtc *acrtc,
4394 bool enable)
e7b07cee
HW		 4395{
4396 /*
4397 * this is not correct translation but will work as soon as VBLANK
4398 * constant is the same as PFLIP
4399 */
4400 int irq_type =
734dd01d 4401 amdgpu_display_crtc_idx_to_irq_type(
e7b07cee
HW		 4402 adev,
4403 acrtc->crtc_id);
4404
4405 if (enable) {
4406 drm_crtc_vblank_on(&acrtc->base);
4407 amdgpu_irq_get(
4408 adev,
4409 &adev->pageflip_irq,
4410 irq_type);
4411 } else {
4412
4413 amdgpu_irq_put(
4414 adev,
4415 &adev->pageflip_irq,
4416 irq_type);
4417 drm_crtc_vblank_off(&acrtc->base);
4418 }
4419}
4420
3ee6b26b
AD		 4421static bool
4422is_scaling_state_different(const struct dm_connector_state *dm_state,
4423 const struct dm_connector_state *old_dm_state)
e7b07cee
HW		 4424{
4425 if (dm_state->scaling != old_dm_state->scaling)
4426 return true;
4427 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4428 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4429 return true;
4430 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4431 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4432 return true;
b830ebc9
HW		 4433 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4434 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4435 return true;
e7b07cee
HW		 4436 return false;
4437}
4438
3ee6b26b
AD		 4439static void remove_stream(struct amdgpu_device *adev,
4440 struct amdgpu_crtc *acrtc,
4441 struct dc_stream_state *stream)
e7b07cee
HW		 4442{
4443 /* this is the update mode case */
e7b07cee
HW		 4444
4445 acrtc->otg_inst = -1;
4446 acrtc->enabled = false;
4447}
4448
7578ecda
AD		 4449static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4450 struct dc_cursor_position *position)
2a8f6ccb 4451{
f4c2cc43 4452 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2a8f6ccb
HW		 4453 int x, y;
4454 int xorigin = 0, yorigin = 0;
4455
4456 if (!crtc || !plane->state->fb) {
4457 position->enable = false;
4458 position->x = 0;
4459 position->y = 0;
4460 return 0;
4461 }
4462
4463 if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4464 (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4465 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4466 __func__,
4467 plane->state->crtc_w,
4468 plane->state->crtc_h);
4469 return -EINVAL;
4470 }
4471
4472 x = plane->state->crtc_x;
4473 y = plane->state->crtc_y;
4474 /* avivo cursor are offset into the total surface */
4475 x += crtc->primary->state->src_x >> 16;
4476 y += crtc->primary->state->src_y >> 16;
4477 if (x < 0) {
4478 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4479 x = 0;
4480 }
4481 if (y < 0) {
4482 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4483 y = 0;
4484 }
4485 position->enable = true;
4486 position->x = x;
4487 position->y = y;
4488 position->x_hotspot = xorigin;
4489 position->y_hotspot = yorigin;
4490
4491 return 0;
4492}
4493
3ee6b26b
AD		 4494static void handle_cursor_update(struct drm_plane *plane,
4495 struct drm_plane_state *old_plane_state)
e7b07cee 4496{
674e78ac 4497 struct amdgpu_device *adev = plane->dev->dev_private;
2a8f6ccb
HW		 4498 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4499 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4500 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4501 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4502 uint64_t address = afb ? afb->address : 0;
4503 struct dc_cursor_position position;
4504 struct dc_cursor_attributes attributes;
4505 int ret;
4506
e7b07cee
HW		 4507 if (!plane->state->fb && !old_plane_state->fb)
4508 return;
4509
f1ad2f5e 4510 DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
c12a7ba5
HW		 4511 __func__,
4512 amdgpu_crtc->crtc_id,
4513 plane->state->crtc_w,
4514 plane->state->crtc_h);
2a8f6ccb
HW		 4515
4516 ret = get_cursor_position(plane, crtc, &position);
4517 if (ret)
4518 return;
4519
4520 if (!position.enable) {
4521 /* turn off cursor */
674e78ac
NK		 4522 if (crtc_state && crtc_state->stream) {
4523 mutex_lock(&adev->dm.dc_lock);
2a8f6ccb
HW		 4524 dc_stream_set_cursor_position(crtc_state->stream,
4525 &position);
674e78ac
NK		 4526 mutex_unlock(&adev->dm.dc_lock);
4527 }
2a8f6ccb 4528 return;
e7b07cee 4529 }
e7b07cee 4530
2a8f6ccb
HW		 4531 amdgpu_crtc->cursor_width = plane->state->crtc_w;
4532 amdgpu_crtc->cursor_height = plane->state->crtc_h;
4533
4534 attributes.address.high_part = upper_32_bits(address);
4535 attributes.address.low_part = lower_32_bits(address);
4536 attributes.width = plane->state->crtc_w;
4537 attributes.height = plane->state->crtc_h;
4538 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
4539 attributes.rotation_angle = 0;
4540 attributes.attribute_flags.value = 0;
4541
4542 attributes.pitch = attributes.width;
4543
886daac9 4544 if (crtc_state->stream) {
674e78ac 4545 mutex_lock(&adev->dm.dc_lock);
886daac9
JZ		 4546 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
4547 &attributes))
4548 DRM_ERROR("DC failed to set cursor attributes\n");
2a8f6ccb 4549
2a8f6ccb
HW		 4550 if (!dc_stream_set_cursor_position(crtc_state->stream,
4551 &position))
4552 DRM_ERROR("DC failed to set cursor position\n");
674e78ac 4553 mutex_unlock(&adev->dm.dc_lock);
886daac9 4554 }
2a8f6ccb 4555}
e7b07cee
HW		 4556
4557static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
4558{
4559
4560 assert_spin_locked(&acrtc->base.dev->event_lock);
4561 WARN_ON(acrtc->event);
4562
4563 acrtc->event = acrtc->base.state->event;
4564
4565 /* Set the flip status */
4566 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
4567
4568 /* Mark this event as consumed */
4569 acrtc->base.state->event = NULL;
4570
4571 DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
4572 acrtc->crtc_id);
4573}
4574
bb47de73
NK		 4575static void update_freesync_state_on_stream(
4576 struct amdgpu_display_manager *dm,
4577 struct dm_crtc_state *new_crtc_state,
180db303
NK		 4578 struct dc_stream_state *new_stream,
4579 struct dc_plane_state *surface,
4580 u32 flip_timestamp_in_us)
bb47de73 4581{
180db303 4582 struct mod_vrr_params vrr_params = new_crtc_state->vrr_params;
bb47de73
NK		 4583 struct dc_info_packet vrr_infopacket = {0};
4584 struct mod_freesync_config config = new_crtc_state->freesync_config;
4585
4586 if (!new_stream)
4587 return;
4588
4589 /*
4590 * TODO: Determine why min/max totals and vrefresh can be 0 here.
4591 * For now it's sufficient to just guard against these conditions.
4592 */
4593
4594 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
4595 return;
4596
4597 if (new_crtc_state->vrr_supported &&
4598 config.min_refresh_in_uhz &&
4599 config.max_refresh_in_uhz) {
4600 config.state = new_crtc_state->base.vrr_enabled ?
4601 VRR_STATE_ACTIVE_VARIABLE :
4602 VRR_STATE_INACTIVE;
4603 } else {
4604 config.state = VRR_STATE_UNSUPPORTED;
4605 }
4606
4607 mod_freesync_build_vrr_params(dm->freesync_module,
4608 new_stream,
180db303
NK		 4609 &config, &vrr_params);
4610
4611 if (surface) {
4612 mod_freesync_handle_preflip(
4613 dm->freesync_module,
4614 surface,
4615 new_stream,
4616 flip_timestamp_in_us,
4617 &vrr_params);
4618 }
bb47de73
NK		 4619
4620 mod_freesync_build_vrr_infopacket(
4621 dm->freesync_module,
4622 new_stream,
180db303 4623 &vrr_params,
ecd0136b
HT		 4624 PACKET_TYPE_VRR,
4625 TRANSFER_FUNC_UNKNOWN,
bb47de73
NK		 4626 &vrr_infopacket);
4627
8a48b44c 4628 new_crtc_state->freesync_timing_changed |=
180db303
NK		 4629 (memcmp(&new_crtc_state->vrr_params.adjust,
4630 &vrr_params.adjust,
4631 sizeof(vrr_params.adjust)) != 0);
bb47de73 4632
8a48b44c 4633 new_crtc_state->freesync_vrr_info_changed |=
bb47de73
NK		 4634 (memcmp(&new_crtc_state->vrr_infopacket,
4635 &vrr_infopacket,
4636 sizeof(vrr_infopacket)) != 0);
4637
180db303 4638 new_crtc_state->vrr_params = vrr_params;
bb47de73
NK		 4639 new_crtc_state->vrr_infopacket = vrr_infopacket;
4640
180db303 4641 new_stream->adjust = new_crtc_state->vrr_params.adjust;
bb47de73
NK		 4642 new_stream->vrr_infopacket = vrr_infopacket;
4643
4644 if (new_crtc_state->freesync_vrr_info_changed)
4645 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
4646 new_crtc_state->base.crtc->base.id,
4647 (int)new_crtc_state->base.vrr_enabled,
180db303 4648 (int)vrr_params.state);
bb47de73
NK		 4649}
4650
3be5262e 4651static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
eb3dc897 4652 struct dc_state *dc_state,
3ee6b26b
AD		 4653 struct drm_device *dev,
4654 struct amdgpu_display_manager *dm,
4655 struct drm_crtc *pcrtc,
420cd472 4656 bool wait_for_vblank)
e7b07cee 4657{
8a48b44c
DF		 4658 uint32_t i, r;
4659 uint64_t timestamp_ns;
e7b07cee 4660 struct drm_plane *plane;
0bc9706d 4661 struct drm_plane_state *old_plane_state, *new_plane_state;
e7b07cee 4662 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
0bc9706d
LSL		 4663 struct drm_crtc_state *new_pcrtc_state =
4664 drm_atomic_get_new_crtc_state(state, pcrtc);
4665 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
44d09c6a
HW		 4666 struct dm_crtc_state *dm_old_crtc_state =
4667 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
74aa7bd4 4668 int planes_count = 0, vpos, hpos;
e7b07cee 4669 unsigned long flags;
8a48b44c
DF		 4670 struct amdgpu_bo *abo;
4671 uint64_t tiling_flags, dcc_address;
8a48b44c 4672 uint32_t target, target_vblank;
7b19bba5
MK		 4673 uint64_t last_flip_vblank;
4674 bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
74aa7bd4 4675 bool pflip_present = false;
8a48b44c 4676
bc7f670e
DF		 4677 struct {
4678 struct dc_surface_update surface_updates[MAX_SURFACES];
4679 struct dc_plane_info plane_infos[MAX_SURFACES];
4680 struct dc_scaling_info scaling_infos[MAX_SURFACES];
74aa7bd4 4681 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
bc7f670e 4682 struct dc_stream_update stream_update;
74aa7bd4 4683 } *bundle;
bc7f670e 4684
74aa7bd4 4685 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8a48b44c 4686
74aa7bd4
DF		 4687 if (!bundle) {
4688 dm_error("Failed to allocate update bundle\n");
4b510503
NK		 4689 goto cleanup;
4690 }
e7b07cee
HW		 4691
4692 /* update planes when needed */
0bc9706d
LSL		 4693 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4694 struct drm_crtc *crtc = new_plane_state->crtc;
f5ba60fe 4695 struct drm_crtc_state *new_crtc_state;
0bc9706d 4696 struct drm_framebuffer *fb = new_plane_state->fb;
8a48b44c 4697 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
74aa7bd4 4698 bool framebuffer_changed;
c7af5f77 4699 struct dc_plane_state *dc_plane;
54d76575 4700 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
e7b07cee 4701
80c218d5
NK		 4702 /* Cursor plane is handled after stream updates */
4703 if (plane->type == DRM_PLANE_TYPE_CURSOR)
e7b07cee 4704 continue;
e7b07cee 4705
f5ba60fe
DD		 4706 if (!fb || !crtc || pcrtc != crtc)
4707 continue;
4708
4709 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
4710 if (!new_crtc_state->active)
e7b07cee
HW		 4711 continue;
4712
74aa7bd4
DF		 4713 dc_plane = dm_new_plane_state->dc_state;
4714
4715 framebuffer_changed = old_plane_state->fb &&
b2e85302 4716 old_plane_state->fb != new_plane_state->fb;
e7b07cee 4717
74aa7bd4 4718 pflip_present = pflip_present || framebuffer_changed;
e7b07cee 4719
74aa7bd4 4720 if (framebuffer_changed) {
8a48b44c
DF		 4721 /*
4722 * TODO This might fail and hence better not used, wait
4723 * explicitly on fences instead
4724 * and in general should be called for
4725 * blocking commit to as per framework helpers
4726 */
4727 abo = gem_to_amdgpu_bo(fb->obj[0]);
4728 r = amdgpu_bo_reserve(abo, true);
f7c8930d 4729 if (unlikely(r != 0))
8a48b44c 4730 DRM_ERROR("failed to reserve buffer before flip\n");
8a48b44c 4731
f7c8930d
AG		 4732 /*
4733 * Wait for all fences on this FB. Do limited wait to avoid
4734 * deadlock during GPU reset when this fence will not signal
4735 * but we hold reservation lock for the BO.
4736 */
4737 r = reservation_object_wait_timeout_rcu(abo->tbo.resv,
4738 true, false,
4739 msecs_to_jiffies(5000));
4740 if (unlikely(r == 0))
4741 DRM_ERROR("Waiting for fences timed out.");
4742
4743
8a48b44c
DF		 4744
4745 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
4746
4747 amdgpu_bo_unreserve(abo);
4748
74aa7bd4
DF		 4749 bundle->flip_addrs[planes_count].address.grph.addr.low_part = lower_32_bits(afb->address);
4750 bundle->flip_addrs[planes_count].address.grph.addr.high_part = upper_32_bits(afb->address);
8a48b44c
DF		 4751
4752 dcc_address = get_dcc_address(afb->address, tiling_flags);
74aa7bd4
DF		 4753 bundle->flip_addrs[planes_count].address.grph.meta_addr.low_part = lower_32_bits(dcc_address);
4754 bundle->flip_addrs[planes_count].address.grph.meta_addr.high_part = upper_32_bits(dcc_address);
8a48b44c 4755
74aa7bd4 4756 bundle->flip_addrs[planes_count].flip_immediate =
8a48b44c
DF		 4757 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
4758
4759 timestamp_ns = ktime_get_ns();
74aa7bd4
DF		 4760 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
4761 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
4762 bundle->surface_updates[planes_count].surface = dc_plane;
8a48b44c 4763
74aa7bd4 4764 if (!bundle->surface_updates[planes_count].surface) {
8a48b44c
DF		 4765 DRM_ERROR("No surface for CRTC: id=%d\n",
4766 acrtc_attach->crtc_id);
4767 continue;
4768 }
4769
c7af5f77 4770 if (plane == pcrtc->primary)
8a48b44c
DF		 4771 update_freesync_state_on_stream(
4772 dm,
4773 acrtc_state,
4774 acrtc_state->stream,
c7af5f77 4775 dc_plane,
74aa7bd4 4776 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8a48b44c 4777
8a48b44c
DF		 4778 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
4779 __func__,
74aa7bd4
DF		 4780 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
4781 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8a48b44c
DF		 4782 }
4783
74aa7bd4 4784 bundle->surface_updates[planes_count].surface = dc_plane;
bc7f670e 4785 if (new_pcrtc_state->color_mgmt_changed) {
74aa7bd4
DF		 4786 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
4787 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
bc7f670e
DF		 4788 }
4789
4790
74aa7bd4
DF		 4791 bundle->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality;
4792 bundle->scaling_infos[planes_count].src_rect = dc_plane->src_rect;
4793 bundle->scaling_infos[planes_count].dst_rect = dc_plane->dst_rect;
4794 bundle->scaling_infos[planes_count].clip_rect = dc_plane->clip_rect;
4795 bundle->surface_updates[planes_count].scaling_info = &bundle->scaling_infos[planes_count];
bc7f670e
DF		 4796
4797
74aa7bd4
DF		 4798 bundle->plane_infos[planes_count].color_space = dc_plane->color_space;
4799 bundle->plane_infos[planes_count].format = dc_plane->format;
4800 bundle->plane_infos[planes_count].plane_size = dc_plane->plane_size;
4801 bundle->plane_infos[planes_count].rotation = dc_plane->rotation;
4802 bundle->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror;
4803 bundle->plane_infos[planes_count].stereo_format = dc_plane->stereo_format;
4804 bundle->plane_infos[planes_count].tiling_info = dc_plane->tiling_info;
4805 bundle->plane_infos[planes_count].visible = dc_plane->visible;
4806 bundle->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha;
4807 bundle->plane_infos[planes_count].dcc = dc_plane->dcc;
4808 bundle->surface_updates[planes_count].plane_info = &bundle->plane_infos[planes_count];
bc7f670e
DF		 4809
4810 planes_count += 1;
4811
8a48b44c
DF		 4812 }
4813
74aa7bd4 4814 if (pflip_present) {
7b19bba5
MK		 4815 if (!vrr_active) {
4816 /* Use old throttling in non-vrr fixed refresh rate mode
4817 * to keep flip scheduling based on target vblank counts
4818 * working in a backwards compatible way, e.g., for
4819 * clients using the GLX_OML_sync_control extension or
4820 * DRI3/Present extension with defined target_msc.
4821 */
4822 last_flip_vblank = drm_crtc_vblank_count(pcrtc);
4823 }
4824 else {
4825 /* For variable refresh rate mode only:
4826 * Get vblank of last completed flip to avoid > 1 vrr
4827 * flips per video frame by use of throttling, but allow
4828 * flip programming anywhere in the possibly large
4829 * variable vrr vblank interval for fine-grained flip
4830 * timing control and more opportunity to avoid stutter
4831 * on late submission of flips.
4832 */
4833 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4834 last_flip_vblank = acrtc_attach->last_flip_vblank;
4835 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4836 }
4837
420cd472 4838 target = (uint32_t)last_flip_vblank + wait_for_vblank;
7b19bba5 4839
8a48b44c
DF		 4840 /* Prepare wait for target vblank early - before the fence-waits */
4841 target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) +
4842 amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id);
4843
4844 /*
4845 * Wait until we're out of the vertical blank period before the one
4846 * targeted by the flip
4847 */
4848 while ((acrtc_attach->enabled &&
4849 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
4850 0, &vpos, &hpos, NULL,
4851 NULL, &pcrtc->hwmode)
4852 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
4853 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
4854 (int)(target_vblank -
4855 amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
4856 usleep_range(1000, 1100);
4857 }
4858
4859 if (acrtc_attach->base.state->event) {
4860 drm_crtc_vblank_get(pcrtc);
4861
4862 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4863
4864 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
4865 prepare_flip_isr(acrtc_attach);
4866
4867 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4868 }
4869
4870 if (acrtc_state->stream) {
4871
4872 if (acrtc_state->freesync_timing_changed)
74aa7bd4 4873 bundle->stream_update.adjust =
8a48b44c
DF		 4874 &acrtc_state->stream->adjust;
4875
4876 if (acrtc_state->freesync_vrr_info_changed)
74aa7bd4 4877 bundle->stream_update.vrr_infopacket =
8a48b44c 4878 &acrtc_state->stream->vrr_infopacket;
e7b07cee 4879 }
e7b07cee
HW		 4880 }
4881
4882 if (planes_count) {
bc7f670e 4883 if (new_pcrtc_state->mode_changed) {
74aa7bd4
DF		 4884 bundle->stream_update.src = acrtc_state->stream->src;
4885 bundle->stream_update.dst = acrtc_state->stream->dst;
e7b07cee
HW		 4886 }
4887
bc7f670e 4888 if (new_pcrtc_state->color_mgmt_changed)
74aa7bd4 4889 bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
bc7f670e 4890
8a48b44c 4891 acrtc_state->stream->abm_level = acrtc_state->abm_level;
bc7f670e 4892 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
74aa7bd4 4893 bundle->stream_update.abm_level = &acrtc_state->abm_level;
44d09c6a 4894
bc7f670e
DF		 4895 mutex_lock(&dm->dc_lock);
4896 dc_commit_updates_for_stream(dm->dc,
74aa7bd4 4897 bundle->surface_updates,
bc7f670e
DF		 4898 planes_count,
4899 acrtc_state->stream,
74aa7bd4 4900 &bundle->stream_update,
bc7f670e
DF		 4901 dc_state);
4902 mutex_unlock(&dm->dc_lock);
e7b07cee 4903 }
4b510503 4904
80c218d5
NK		 4905 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
4906 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4907 handle_cursor_update(plane, old_plane_state);
4908
4b510503 4909cleanup:
74aa7bd4 4910 kfree(bundle);
e7b07cee
HW		 4911}
4912
1f6010a9 4913/*
27b3f4fc
LSL		 4914 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4915 * @crtc_state: the DRM CRTC state
4916 * @stream_state: the DC stream state.
4917 *
4918 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4919 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4920 */
4921static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4922 struct dc_stream_state *stream_state)
4923{
b9952f93 4924 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
27b3f4fc 4925}
e7b07cee 4926
7578ecda
AD		 4927static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4928 struct drm_atomic_state *state,
4929 bool nonblock)
e7b07cee
HW		 4930{
4931 struct drm_crtc *crtc;
c2cea706 4932 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4933 struct amdgpu_device *adev = dev->dev_private;
4934 int i;
4935
4936 /*
4937 * We evade vblanks and pflips on crtc that
4938 * should be changed. We do it here to flush & disable
4939 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4940 * it will update crtc->dm_crtc_state->stream pointer which is used in
4941 * the ISRs.
4942 */
c2cea706 4943 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
54d76575 4944 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
428da2bd 4945 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee
HW		 4946 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4947
428da2bd
NK		 4948 if (drm_atomic_crtc_needs_modeset(new_crtc_state)
4949 && dm_old_crtc_state->stream) {
4950 /*
43a6a02e
NK		 4951 * If the stream is removed and CRC capture was
4952 * enabled on the CRTC the extra vblank reference
4953 * needs to be dropped since CRC capture will be
4954 * disabled.
428da2bd 4955 */
43a6a02e
NK		 4956 if (!dm_new_crtc_state->stream
4957 && dm_new_crtc_state->crc_enabled) {
428da2bd
NK		 4958 drm_crtc_vblank_put(crtc);
4959 dm_new_crtc_state->crc_enabled = false;
4960 }
4961
e7b07cee 4962 manage_dm_interrupts(adev, acrtc, false);
428da2bd 4963 }
e7b07cee 4964 }
1f6010a9
DF		 4965 /*
4966 * Add check here for SoC's that support hardware cursor plane, to
4967 * unset legacy_cursor_update
4968 */
e7b07cee
HW		 4969
4970 return drm_atomic_helper_commit(dev, state, nonblock);
4971
4972 /*TODO Handle EINTR, reenable IRQ*/
4973}
4974
b8592b48
LL		 4975/**
4976 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
4977 * @state: The atomic state to commit
4978 *
4979 * This will tell DC to commit the constructed DC state from atomic_check,
4980 * programming the hardware. Any failures here implies a hardware failure, since
4981 * atomic check should have filtered anything non-kosher.
4982 */
7578ecda 4983static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
e7b07cee
HW		 4984{
4985 struct drm_device *dev = state->dev;
4986 struct amdgpu_device *adev = dev->dev_private;
4987 struct amdgpu_display_manager *dm = &adev->dm;
4988 struct dm_atomic_state *dm_state;
eb3dc897 4989 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
e7b07cee 4990 uint32_t i, j;
5cc6dcbd 4991 struct drm_crtc *crtc;
0bc9706d 4992 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
e7b07cee
HW		 4993 unsigned long flags;
4994 bool wait_for_vblank = true;
4995 struct drm_connector *connector;
c2cea706 4996 struct drm_connector_state *old_con_state, *new_con_state;
54d76575 4997 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
fe2a1965 4998 int crtc_disable_count = 0;
e7b07cee
HW		 4999
5000 drm_atomic_helper_update_legacy_modeset_state(dev, state);
5001
eb3dc897
NK		 5002 dm_state = dm_atomic_get_new_state(state);
5003 if (dm_state && dm_state->context) {
5004 dc_state = dm_state->context;
5005 } else {
5006 /* No state changes, retain current state. */
5007 dc_state_temp = dc_create_state();
5008 ASSERT(dc_state_temp);
5009 dc_state = dc_state_temp;
5010 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5011 }
e7b07cee
HW		 5012
5013 /* update changed items */
0bc9706d 5014 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
e7b07cee 5015 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5016
54d76575
LSL		 5017 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5018 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
e7b07cee 5019
f1ad2f5e 5020 DRM_DEBUG_DRIVER(
e7b07cee
HW		 5021 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5022 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5023 "connectors_changed:%d\n",
5024 acrtc->crtc_id,
0bc9706d
LSL		 5025 new_crtc_state->enable,
5026 new_crtc_state->active,
5027 new_crtc_state->planes_changed,
5028 new_crtc_state->mode_changed,
5029 new_crtc_state->active_changed,
5030 new_crtc_state->connectors_changed);
e7b07cee 5031
27b3f4fc
LSL		 5032 /* Copy all transient state flags into dc state */
5033 if (dm_new_crtc_state->stream) {
5034 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5035 dm_new_crtc_state->stream);
5036 }
5037
e7b07cee
HW		 5038 /* handles headless hotplug case, updating new_state and
5039 * aconnector as needed
5040 */
5041
54d76575 5042 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
e7b07cee 5043
f1ad2f5e 5044 DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
e7b07cee 5045
54d76575 5046 if (!dm_new_crtc_state->stream) {
e7b07cee 5047 /*
b830ebc9
HW		 5048 * this could happen because of issues with
5049 * userspace notifications delivery.
5050 * In this case userspace tries to set mode on
1f6010a9
DF		 5051 * display which is disconnected in fact.
5052 * dc_sink is NULL in this case on aconnector.
b830ebc9
HW		 5053 * We expect reset mode will come soon.
5054 *
5055 * This can also happen when unplug is done
5056 * during resume sequence ended
5057 *
5058 * In this case, we want to pretend we still
5059 * have a sink to keep the pipe running so that
5060 * hw state is consistent with the sw state
5061 */
f1ad2f5e 5062 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
e7b07cee
HW		 5063 __func__, acrtc->base.base.id);
5064 continue;
5065 }
5066
54d76575
LSL		 5067 if (dm_old_crtc_state->stream)
5068 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee 5069
97028037
LP		 5070 pm_runtime_get_noresume(dev->dev);
5071
e7b07cee 5072 acrtc->enabled = true;
0bc9706d
LSL		 5073 acrtc->hw_mode = new_crtc_state->mode;
5074 crtc->hwmode = new_crtc_state->mode;
5075 } else if (modereset_required(new_crtc_state)) {
f1ad2f5e 5076 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
e7b07cee
HW		 5077
5078 /* i.e. reset mode */
54d76575
LSL		 5079 if (dm_old_crtc_state->stream)
5080 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
e7b07cee
HW		 5081 }
5082 } /* for_each_crtc_in_state() */
5083
eb3dc897
NK		 5084 if (dc_state) {
5085 dm_enable_per_frame_crtc_master_sync(dc_state);
674e78ac 5086 mutex_lock(&dm->dc_lock);
eb3dc897 5087 WARN_ON(!dc_commit_state(dm->dc, dc_state));
674e78ac 5088 mutex_unlock(&dm->dc_lock);
fa2123db 5089 }
e7b07cee 5090
0bc9706d 5091 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5092 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
b830ebc9 5093
54d76575 5094 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5095
54d76575 5096 if (dm_new_crtc_state->stream != NULL) {
e7b07cee 5097 const struct dc_stream_status *status =
54d76575 5098 dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5099
eb3dc897 5100 if (!status)
09f609c3
LL		 5101 status = dc_stream_get_status_from_state(dc_state,
5102 dm_new_crtc_state->stream);
eb3dc897 5103
e7b07cee 5104 if (!status)
54d76575 5105 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
e7b07cee
HW		 5106 else
5107 acrtc->otg_inst = status->primary_otg_inst;
5108 }
5109 }
5110
02d6a6fc 5111 /* Handle connector state changes */
c2cea706 5112 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 5113 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5114 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5115 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
19afd799
NC		 5116 struct dc_surface_update dummy_updates[MAX_SURFACES];
5117 struct dc_stream_update stream_update;
e7b07cee
HW		 5118 struct dc_stream_status *status = NULL;
5119
19afd799
NC		 5120 memset(&dummy_updates, 0, sizeof(dummy_updates));
5121 memset(&stream_update, 0, sizeof(stream_update));
5122
44d09c6a 5123 if (acrtc) {
0bc9706d 5124 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
44d09c6a
HW		 5125 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5126 }
0bc9706d 5127
e7b07cee 5128 /* Skip any modesets/resets */
0bc9706d 5129 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
e7b07cee
HW		 5130 continue;
5131
54d76575 5132 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
c1ee92f9
DF		 5133 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5134
c1ee92f9
DF		 5135 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5136 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5137 continue;
e7b07cee 5138
02d6a6fc
DF		 5139 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5140 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5141 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
e7b07cee 5142
02d6a6fc
DF		 5143 stream_update.src = dm_new_crtc_state->stream->src;
5144 stream_update.dst = dm_new_crtc_state->stream->dst;
5145 }
5146
5147 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5148 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5149
5150 stream_update.abm_level = &dm_new_crtc_state->abm_level;
5151 }
70e8ffc5 5152
54d76575 5153 status = dc_stream_get_status(dm_new_crtc_state->stream);
e7b07cee 5154 WARN_ON(!status);
3be5262e 5155 WARN_ON(!status->plane_count);
e7b07cee 5156
02d6a6fc
DF		 5157 /*
5158 * TODO: DC refuses to perform stream updates without a dc_surface_update.
5159 * Here we create an empty update on each plane.
5160 * To fix this, DC should permit updating only stream properties.
5161 */
5162 for (j = 0; j < status->plane_count; j++)
5163 dummy_updates[j].surface = status->plane_states[0];
5164
5165
5166 mutex_lock(&dm->dc_lock);
5167 dc_commit_updates_for_stream(dm->dc,
5168 dummy_updates,
5169 status->plane_count,
5170 dm_new_crtc_state->stream,
5171 &stream_update,
5172 dc_state);
5173 mutex_unlock(&dm->dc_lock);
e7b07cee
HW		 5174 }
5175
e1fc2dca
LSL		 5176 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5177 new_crtc_state, i) {
e7b07cee
HW		 5178 /*
5179 * loop to enable interrupts on newly arrived crtc
5180 */
e1fc2dca
LSL		 5181 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5182 bool modeset_needed;
b830ebc9 5183
fe2a1965
LP		 5184 if (old_crtc_state->active && !new_crtc_state->active)
5185 crtc_disable_count++;
5186
54d76575 5187 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e1fc2dca
LSL		 5188 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5189 modeset_needed = modeset_required(
5190 new_crtc_state,
5191 dm_new_crtc_state->stream,
5192 dm_old_crtc_state->stream);
5193
5194 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
5195 continue;
e7b07cee 5196
e7b07cee 5197 manage_dm_interrupts(adev, acrtc, true);
43a6a02e 5198
cc7e422d 5199#ifdef CONFIG_DEBUG_FS
43a6a02e
NK		 5200 /* The stream has changed so CRC capture needs to re-enabled. */
5201 if (dm_new_crtc_state->crc_enabled)
5202 amdgpu_dm_crtc_set_crc_source(crtc, "auto");
cc7e422d 5203#endif
e7b07cee
HW		 5204 }
5205
420cd472
DF		 5206 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
5207 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
5208 wait_for_vblank = false;
5209
e7b07cee 5210 /* update planes when needed per crtc*/
5cc6dcbd 5211 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
54d76575 5212 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
e7b07cee 5213
54d76575 5214 if (dm_new_crtc_state->stream)
eb3dc897 5215 amdgpu_dm_commit_planes(state, dc_state, dev,
420cd472 5216 dm, crtc, wait_for_vblank);
e7b07cee
HW		 5217 }
5218
5219
5220 /*
5221 * send vblank event on all events not handled in flip and
5222 * mark consumed event for drm_atomic_helper_commit_hw_done
5223 */
5224 spin_lock_irqsave(&adev->ddev->event_lock, flags);
0bc9706d 5225 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
e7b07cee 5226
0bc9706d
LSL		 5227 if (new_crtc_state->event)
5228 drm_send_event_locked(dev, &new_crtc_state->event->base);
e7b07cee 5229
0bc9706d 5230 new_crtc_state->event = NULL;
e7b07cee
HW		 5231 }
5232 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5233
29c8f234
LL		 5234 /* Signal HW programming completion */
5235 drm_atomic_helper_commit_hw_done(state);
e7b07cee
HW		 5236
5237 if (wait_for_vblank)
320a1274 5238 drm_atomic_helper_wait_for_flip_done(dev, state);
e7b07cee
HW		 5239
5240 drm_atomic_helper_cleanup_planes(dev, state);
97028037 5241
1f6010a9
DF		 5242 /*
5243 * Finally, drop a runtime PM reference for each newly disabled CRTC,
97028037
LP		 5244 * so we can put the GPU into runtime suspend if we're not driving any
5245 * displays anymore
5246 */
fe2a1965
LP		 5247 for (i = 0; i < crtc_disable_count; i++)
5248 pm_runtime_put_autosuspend(dev->dev);
97028037 5249 pm_runtime_mark_last_busy(dev->dev);
eb3dc897
NK		 5250
5251 if (dc_state_temp)
5252 dc_release_state(dc_state_temp);
e7b07cee
HW		 5253}
5254
5255
5256static int dm_force_atomic_commit(struct drm_connector *connector)
5257{
5258 int ret = 0;
5259 struct drm_device *ddev = connector->dev;
5260 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5261 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5262 struct drm_plane *plane = disconnected_acrtc->base.primary;
5263 struct drm_connector_state *conn_state;
5264 struct drm_crtc_state *crtc_state;
5265 struct drm_plane_state *plane_state;
5266
5267 if (!state)
5268 return -ENOMEM;
5269
5270 state->acquire_ctx = ddev->mode_config.acquire_ctx;
5271
5272 /* Construct an atomic state to restore previous display setting */
5273
5274 /*
5275 * Attach connectors to drm_atomic_state
5276 */
5277 conn_state = drm_atomic_get_connector_state(state, connector);
5278
5279 ret = PTR_ERR_OR_ZERO(conn_state);
5280 if (ret)
5281 goto err;
5282
5283 /* Attach crtc to drm_atomic_state*/
5284 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5285
5286 ret = PTR_ERR_OR_ZERO(crtc_state);
5287 if (ret)
5288 goto err;
5289
5290 /* force a restore */
5291 crtc_state->mode_changed = true;
5292
5293 /* Attach plane to drm_atomic_state */
5294 plane_state = drm_atomic_get_plane_state(state, plane);
5295
5296 ret = PTR_ERR_OR_ZERO(plane_state);
5297 if (ret)
5298 goto err;
5299
5300
5301 /* Call commit internally with the state we just constructed */
5302 ret = drm_atomic_commit(state);
5303 if (!ret)
5304 return 0;
5305
5306err:
5307 DRM_ERROR("Restoring old state failed with %i\n", ret);
5308 drm_atomic_state_put(state);
5309
5310 return ret;
5311}
5312
5313/*
1f6010a9
DF		 5314 * This function handles all cases when set mode does not come upon hotplug.
5315 * This includes when a display is unplugged then plugged back into the
5316 * same port and when running without usermode desktop manager supprot
e7b07cee 5317 */
3ee6b26b
AD		 5318void dm_restore_drm_connector_state(struct drm_device *dev,
5319 struct drm_connector *connector)
e7b07cee 5320{
c84dec2f 5321 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
e7b07cee
HW		 5322 struct amdgpu_crtc *disconnected_acrtc;
5323 struct dm_crtc_state *acrtc_state;
5324
5325 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5326 return;
5327
5328 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
70e8ffc5
HW		 5329 if (!disconnected_acrtc)
5330 return;
e7b07cee 5331
70e8ffc5
HW		 5332 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5333 if (!acrtc_state->stream)
e7b07cee
HW		 5334 return;
5335
5336 /*
5337 * If the previous sink is not released and different from the current,
5338 * we deduce we are in a state where we can not rely on usermode call
5339 * to turn on the display, so we do it here
5340 */
5341 if (acrtc_state->stream->sink != aconnector->dc_sink)
5342 dm_force_atomic_commit(&aconnector->base);
5343}
5344
1f6010a9 5345/*
e7b07cee
HW		 5346 * Grabs all modesetting locks to serialize against any blocking commits,
5347 * Waits for completion of all non blocking commits.
5348 */
3ee6b26b
AD		 5349static int do_aquire_global_lock(struct drm_device *dev,
5350 struct drm_atomic_state *state)
e7b07cee
HW		 5351{
5352 struct drm_crtc *crtc;
5353 struct drm_crtc_commit *commit;
5354 long ret;
5355
1f6010a9
DF		 5356 /*
5357 * Adding all modeset locks to aquire_ctx will
e7b07cee
HW		 5358 * ensure that when the framework release it the
5359 * extra locks we are locking here will get released to
5360 */
5361 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
5362 if (ret)
5363 return ret;
5364
5365 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5366 spin_lock(&crtc->commit_lock);
5367 commit = list_first_entry_or_null(&crtc->commit_list,
5368 struct drm_crtc_commit, commit_entry);
5369 if (commit)
5370 drm_crtc_commit_get(commit);
5371 spin_unlock(&crtc->commit_lock);
5372
5373 if (!commit)
5374 continue;
5375
1f6010a9
DF		 5376 /*
5377 * Make sure all pending HW programming completed and
e7b07cee
HW		 5378 * page flips done
5379 */
5380 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
5381
5382 if (ret > 0)
5383 ret = wait_for_completion_interruptible_timeout(
5384 &commit->flip_done, 10*HZ);
5385
5386 if (ret == 0)
5387 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
b830ebc9 5388 "timed out\n", crtc->base.id, crtc->name);
e7b07cee
HW		 5389
5390 drm_crtc_commit_put(commit);
5391 }
5392
5393 return ret < 0 ? ret : 0;
5394}
5395
bb47de73
NK		 5396static void get_freesync_config_for_crtc(
5397 struct dm_crtc_state *new_crtc_state,
5398 struct dm_connector_state *new_con_state)
98e6436d
AK		 5399{
5400 struct mod_freesync_config config = {0};
98e6436d
AK		 5401 struct amdgpu_dm_connector *aconnector =
5402 to_amdgpu_dm_connector(new_con_state->base.connector);
a057ec46 5403 struct drm_display_mode *mode = &new_crtc_state->base.mode;
98e6436d 5404
a057ec46
IB		 5405 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
5406 aconnector->min_vfreq <= drm_mode_vrefresh(mode);
bb47de73 5407
a057ec46
IB		 5408 if (new_crtc_state->vrr_supported) {
5409 new_crtc_state->stream->ignore_msa_timing_param = true;
bb47de73 5410 config.state = new_crtc_state->base.vrr_enabled ?
98e6436d
AK		 5411 VRR_STATE_ACTIVE_VARIABLE :
5412 VRR_STATE_INACTIVE;
5413 config.min_refresh_in_uhz =
5414 aconnector->min_vfreq * 1000000;
5415 config.max_refresh_in_uhz =
5416 aconnector->max_vfreq * 1000000;
69ff8845 5417 config.vsif_supported = true;
180db303 5418 config.btr = true;
98e6436d
AK		 5419 }
5420
bb47de73
NK		 5421 new_crtc_state->freesync_config = config;
5422}
98e6436d 5423
bb47de73
NK		 5424static void reset_freesync_config_for_crtc(
5425 struct dm_crtc_state *new_crtc_state)
5426{
5427 new_crtc_state->vrr_supported = false;
98e6436d 5428
180db303
NK		 5429 memset(&new_crtc_state->vrr_params, 0,
5430 sizeof(new_crtc_state->vrr_params));
bb47de73
NK		 5431 memset(&new_crtc_state->vrr_infopacket, 0,
5432 sizeof(new_crtc_state->vrr_infopacket));
98e6436d
AK		 5433}
5434
4b9674e5
LL		 5435static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
5436 struct drm_atomic_state *state,
5437 struct drm_crtc *crtc,
5438 struct drm_crtc_state *old_crtc_state,
5439 struct drm_crtc_state *new_crtc_state,
5440 bool enable,
5441 bool *lock_and_validation_needed)
e7b07cee 5442{
eb3dc897 5443 struct dm_atomic_state *dm_state = NULL;
54d76575 5444 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9635b754 5445 struct dc_stream_state *new_stream;
62f55537 5446 int ret = 0;
d4d4a645 5447
1f6010a9
DF		 5448 /*
5449 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
5450 * update changed items
5451 */
4b9674e5
LL		 5452 struct amdgpu_crtc *acrtc = NULL;
5453 struct amdgpu_dm_connector *aconnector = NULL;
5454 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
5455 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
5456 struct drm_plane_state *new_plane_state = NULL;
e7b07cee 5457
4b9674e5 5458 new_stream = NULL;
9635b754 5459
4b9674e5
LL		 5460 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5461 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5462 acrtc = to_amdgpu_crtc(crtc);
e7b07cee 5463
4b9674e5 5464 new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
f2877656 5465
4b9674e5
LL		 5466 if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
5467 ret = -EINVAL;
5468 goto fail;
5469 }
f2877656 5470
4b9674e5 5471 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
19f89e23 5472
4b9674e5
LL		 5473 /* TODO This hack should go away */
5474 if (aconnector && enable) {
5475 /* Make sure fake sink is created in plug-in scenario */
5476 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
5477 &aconnector->base);
5478 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
5479 &aconnector->base);
19f89e23 5480
4b9674e5
LL		 5481 if (IS_ERR(drm_new_conn_state)) {
5482 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
5483 goto fail;
5484 }
19f89e23 5485
4b9674e5
LL		 5486 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
5487 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
19f89e23 5488
02d35a67
JFZ		 5489 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5490 goto skip_modeset;
5491
4b9674e5
LL		 5492 new_stream = create_stream_for_sink(aconnector,
5493 &new_crtc_state->mode,
5494 dm_new_conn_state,
5495 dm_old_crtc_state->stream);
19f89e23 5496
4b9674e5
LL		 5497 /*
5498 * we can have no stream on ACTION_SET if a display
5499 * was disconnected during S3, in this case it is not an
5500 * error, the OS will be updated after detection, and
5501 * will do the right thing on next atomic commit
5502 */
19f89e23 5503
4b9674e5
LL		 5504 if (!new_stream) {
5505 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5506 __func__, acrtc->base.base.id);
5507 ret = -ENOMEM;
5508 goto fail;
5509 }
e7b07cee 5510
4b9674e5 5511 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
98e6436d 5512
4b9674e5
LL		 5513 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
5514 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
5515 new_crtc_state->mode_changed = false;
5516 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
5517 new_crtc_state->mode_changed);
62f55537 5518 }
4b9674e5 5519 }
b830ebc9 5520
02d35a67 5521 /* mode_changed flag may get updated above, need to check again */
4b9674e5
LL		 5522 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
5523 goto skip_modeset;
e7b07cee 5524
4b9674e5
LL		 5525 DRM_DEBUG_DRIVER(
5526 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5527 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5528 "connectors_changed:%d\n",
5529 acrtc->crtc_id,
5530 new_crtc_state->enable,
5531 new_crtc_state->active,
5532 new_crtc_state->planes_changed,
5533 new_crtc_state->mode_changed,
5534 new_crtc_state->active_changed,
5535 new_crtc_state->connectors_changed);
62f55537 5536
4b9674e5
LL		 5537 /* Remove stream for any changed/disabled CRTC */
5538 if (!enable) {
62f55537 5539
4b9674e5
LL		 5540 if (!dm_old_crtc_state->stream)
5541 goto skip_modeset;
eb3dc897 5542
4b9674e5
LL		 5543 ret = dm_atomic_get_state(state, &dm_state);
5544 if (ret)
5545 goto fail;
e7b07cee 5546
4b9674e5
LL		 5547 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
5548 crtc->base.id);
62f55537 5549
4b9674e5
LL		 5550 /* i.e. reset mode */
5551 if (dc_remove_stream_from_ctx(
5552 dm->dc,
5553 dm_state->context,
5554 dm_old_crtc_state->stream) != DC_OK) {
5555 ret = -EINVAL;
5556 goto fail;
5557 }
62f55537 5558
4b9674e5
LL		 5559 dc_stream_release(dm_old_crtc_state->stream);
5560 dm_new_crtc_state->stream = NULL;
bb47de73 5561
4b9674e5 5562 reset_freesync_config_for_crtc(dm_new_crtc_state);
62f55537 5563
4b9674e5 5564 *lock_and_validation_needed = true;
62f55537 5565
4b9674e5
LL		 5566 } else {/* Add stream for any updated/enabled CRTC */
5567 /*
5568 * Quick fix to prevent NULL pointer on new_stream when
5569 * added MST connectors not found in existing crtc_state in the chained mode
5570 * TODO: need to dig out the root cause of that
5571 */
5572 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
5573 goto skip_modeset;
62f55537 5574
4b9674e5
LL		 5575 if (modereset_required(new_crtc_state))
5576 goto skip_modeset;
62f55537 5577
4b9674e5
LL		 5578 if (modeset_required(new_crtc_state, new_stream,
5579 dm_old_crtc_state->stream)) {
62f55537 5580
4b9674e5 5581 WARN_ON(dm_new_crtc_state->stream);
eb3dc897 5582
4b9674e5
LL		 5583 ret = dm_atomic_get_state(state, &dm_state);
5584 if (ret)
5585 goto fail;
27b3f4fc 5586
4b9674e5 5587 dm_new_crtc_state->stream = new_stream;
62f55537 5588
4b9674e5 5589 dc_stream_retain(new_stream);
1dc90497 5590
4b9674e5
LL		 5591 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
5592 crtc->base.id);
1dc90497 5593
4b9674e5
LL		 5594 if (dc_add_stream_to_ctx(
5595 dm->dc,
5596 dm_state->context,
5597 dm_new_crtc_state->stream) != DC_OK) {
5598 ret = -EINVAL;
5599 goto fail;
9b690ef3
BL		 5600 }
5601
4b9674e5
LL		 5602 *lock_and_validation_needed = true;
5603 }
5604 }
e277adc5 5605
4b9674e5
LL		 5606skip_modeset:
5607 /* Release extra reference */
5608 if (new_stream)
5609 dc_stream_release(new_stream);
e277adc5 5610
4b9674e5
LL		 5611 /*
5612 * We want to do dc stream updates that do not require a
5613 * full modeset below.
5614 */
5615 if (!(enable && aconnector && new_crtc_state->enable &&
5616 new_crtc_state->active))
5617 return 0;
5618 /*
5619 * Given above conditions, the dc state cannot be NULL because:
5620 * 1. We're in the process of enabling CRTCs (just been added
5621 * to the dc context, or already is on the context)
5622 * 2. Has a valid connector attached, and
5623 * 3. Is currently active and enabled.
5624 * => The dc stream state currently exists.
5625 */
5626 BUG_ON(dm_new_crtc_state->stream == NULL);
a9e8d275 5627
4b9674e5
LL		 5628 /* Scaling or underscan settings */
5629 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
5630 update_stream_scaling_settings(
5631 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
98e6436d 5632
4b9674e5
LL		 5633 /*
5634 * Color management settings. We also update color properties
5635 * when a modeset is needed, to ensure it gets reprogrammed.
5636 */
5637 if (dm_new_crtc_state->base.color_mgmt_changed ||
5638 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
5639 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
5640 if (ret)
5641 goto fail;
5642 amdgpu_dm_set_ctm(dm_new_crtc_state);
62f55537 5643 }
e7b07cee 5644
4b9674e5
LL		 5645 /* Update Freesync settings. */
5646 get_freesync_config_for_crtc(dm_new_crtc_state,
5647 dm_new_conn_state);
5648
62f55537 5649 return ret;
9635b754
DS		 5650
5651fail:
5652 if (new_stream)
5653 dc_stream_release(new_stream);
5654 return ret;
62f55537 5655}
9b690ef3 5656
9e869063
LL		 5657static int dm_update_plane_state(struct dc *dc,
5658 struct drm_atomic_state *state,
5659 struct drm_plane *plane,
5660 struct drm_plane_state *old_plane_state,
5661 struct drm_plane_state *new_plane_state,
5662 bool enable,
5663 bool *lock_and_validation_needed)
62f55537 5664{
eb3dc897
NK		 5665
5666 struct dm_atomic_state *dm_state = NULL;
62f55537 5667 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
0bc9706d 5668 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
54d76575 5669 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
54d76575 5670 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
62f55537
AG		 5671 /* TODO return page_flip_needed() function */
5672 bool pflip_needed = !state->allow_modeset;
5673 int ret = 0;
e7b07cee 5674
9b690ef3 5675
9e869063
LL		 5676 new_plane_crtc = new_plane_state->crtc;
5677 old_plane_crtc = old_plane_state->crtc;
5678 dm_new_plane_state = to_dm_plane_state(new_plane_state);
5679 dm_old_plane_state = to_dm_plane_state(old_plane_state);
62f55537 5680
9e869063
LL		 5681 /*TODO Implement atomic check for cursor plane */
5682 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5683 return 0;
9b690ef3 5684
9e869063
LL		 5685 /* Remove any changed/removed planes */
5686 if (!enable) {
5687 if (pflip_needed &&
5688 plane->type != DRM_PLANE_TYPE_OVERLAY)
5689 return 0;
a7b06724 5690
9e869063
LL		 5691 if (!old_plane_crtc)
5692 return 0;
62f55537 5693
9e869063
LL		 5694 old_crtc_state = drm_atomic_get_old_crtc_state(
5695 state, old_plane_crtc);
5696 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9b690ef3 5697
9e869063
LL		 5698 if (!dm_old_crtc_state->stream)
5699 return 0;
62f55537 5700
9e869063
LL		 5701 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
5702 plane->base.id, old_plane_crtc->base.id);
9b690ef3 5703
9e869063
LL		 5704 ret = dm_atomic_get_state(state, &dm_state);
5705 if (ret)
5706 return ret;
eb3dc897 5707
9e869063
LL		 5708 if (!dc_remove_plane_from_context(
5709 dc,
5710 dm_old_crtc_state->stream,
5711 dm_old_plane_state->dc_state,
5712 dm_state->context)) {
62f55537 5713
9e869063
LL		 5714 ret = EINVAL;
5715 return ret;
5716 }
e7b07cee 5717
9b690ef3 5718
9e869063
LL		 5719 dc_plane_state_release(dm_old_plane_state->dc_state);
5720 dm_new_plane_state->dc_state = NULL;
1dc90497 5721
9e869063 5722 *lock_and_validation_needed = true;
1dc90497 5723
9e869063
LL		 5724 } else { /* Add new planes */
5725 struct dc_plane_state *dc_new_plane_state;
1dc90497 5726
9e869063
LL		 5727 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
5728 return 0;
e7b07cee 5729
9e869063
LL		 5730 if (!new_plane_crtc)
5731 return 0;
e7b07cee 5732
9e869063
LL		 5733 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
5734 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1dc90497 5735
9e869063
LL		 5736 if (!dm_new_crtc_state->stream)
5737 return 0;
62f55537 5738
9e869063
LL		 5739 if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY)
5740 return 0;
62f55537 5741
9e869063 5742 WARN_ON(dm_new_plane_state->dc_state);
9b690ef3 5743
9e869063
LL		 5744 dc_new_plane_state = dc_create_plane_state(dc);
5745 if (!dc_new_plane_state)
5746 return -ENOMEM;
62f55537 5747
9e869063
LL		 5748 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
5749 plane->base.id, new_plane_crtc->base.id);
8c45c5db 5750
9e869063
LL		 5751 ret = fill_plane_attributes(
5752 new_plane_crtc->dev->dev_private,
5753 dc_new_plane_state,
5754 new_plane_state,
5755 new_crtc_state);
5756 if (ret) {
5757 dc_plane_state_release(dc_new_plane_state);
5758 return ret;
5759 }
62f55537 5760
9e869063
LL		 5761 ret = dm_atomic_get_state(state, &dm_state);
5762 if (ret) {
5763 dc_plane_state_release(dc_new_plane_state);
5764 return ret;
5765 }
eb3dc897 5766
9e869063
LL		 5767 /*
5768 * Any atomic check errors that occur after this will
5769 * not need a release. The plane state will be attached
5770 * to the stream, and therefore part of the atomic
5771 * state. It'll be released when the atomic state is
5772 * cleaned.
5773 */
5774 if (!dc_add_plane_to_context(
5775 dc,
5776 dm_new_crtc_state->stream,
5777 dc_new_plane_state,
5778 dm_state->context)) {
62f55537 5779
9e869063
LL		 5780 dc_plane_state_release(dc_new_plane_state);
5781 return -EINVAL;
5782 }
8c45c5db 5783
9e869063 5784 dm_new_plane_state->dc_state = dc_new_plane_state;
000b59ea 5785
9e869063
LL		 5786 /* Tell DC to do a full surface update every time there
5787 * is a plane change. Inefficient, but works for now.
5788 */
5789 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
5790
5791 *lock_and_validation_needed = true;
62f55537 5792 }
e7b07cee
HW		 5793
5794
62f55537
AG		 5795 return ret;
5796}
a87fa993 5797
eb3dc897
NK		 5798static int
5799dm_determine_update_type_for_commit(struct dc *dc,
5800 struct drm_atomic_state *state,
5801 enum surface_update_type *out_type)
5802{
5803 struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
5804 int i, j, num_plane, ret = 0;
a87fa993
BL		 5805 struct drm_plane_state *old_plane_state, *new_plane_state;
5806 struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
5807 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
5808 struct drm_plane *plane;
5809
5810 struct drm_crtc *crtc;
5811 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
5812 struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
5813 struct dc_stream_status *status = NULL;
5814
fe96b99d
GS		 5815 struct dc_surface_update *updates;
5816 struct dc_plane_state *surface;
a87fa993
BL		 5817 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5818
fe96b99d
GS		 5819 updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
5820 surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL);
5821
4f712911
BL		 5822 if (!updates || !surface) {
5823 DRM_ERROR("Plane or surface update failed to allocate");
5824 /* Set type to FULL to avoid crashing in DC*/
5825 update_type = UPDATE_TYPE_FULL;
eb3dc897 5826 goto cleanup;
4f712911 5827 }
a87fa993
BL		 5828
5829 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
c448a53a
NK		 5830 struct dc_stream_update stream_update = { 0 };
5831
a87fa993
BL		 5832 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
5833 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
5834 num_plane = 0;
5835
6836d239
NK		 5836 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
5837 update_type = UPDATE_TYPE_FULL;
5838 goto cleanup;
5839 }
a87fa993 5840
6836d239 5841 if (!new_dm_crtc_state->stream)
c744e974 5842 continue;
eb3dc897 5843
c744e974
NK		 5844 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
5845 new_plane_crtc = new_plane_state->crtc;
5846 old_plane_crtc = old_plane_state->crtc;
5847 new_dm_plane_state = to_dm_plane_state(new_plane_state);
5848 old_dm_plane_state = to_dm_plane_state(old_plane_state);
eb3dc897 5849
c744e974
NK		 5850 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5851 continue;
eb3dc897 5852
6836d239
NK		 5853 if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
5854 update_type = UPDATE_TYPE_FULL;
5855 goto cleanup;
5856 }
5857
c744e974
NK		 5858 if (!state->allow_modeset)
5859 continue;
a87fa993 5860
c744e974
NK		 5861 if (crtc != new_plane_crtc)
5862 continue;
5863
5864 updates[num_plane].surface = &surface[num_plane];
5865
5866 if (new_crtc_state->mode_changed) {
5867 updates[num_plane].surface->src_rect =
5868 new_dm_plane_state->dc_state->src_rect;
5869 updates[num_plane].surface->dst_rect =
5870 new_dm_plane_state->dc_state->dst_rect;
5871 updates[num_plane].surface->rotation =
5872 new_dm_plane_state->dc_state->rotation;
5873 updates[num_plane].surface->in_transfer_func =
5874 new_dm_plane_state->dc_state->in_transfer_func;
5875 stream_update.dst = new_dm_crtc_state->stream->dst;
5876 stream_update.src = new_dm_crtc_state->stream->src;
5877 }
5878
5879 if (new_crtc_state->color_mgmt_changed) {
5880 updates[num_plane].gamma =
5881 new_dm_plane_state->dc_state->gamma_correction;
5882 updates[num_plane].in_transfer_func =
5883 new_dm_plane_state->dc_state->in_transfer_func;
5884 stream_update.gamut_remap =
5885 &new_dm_crtc_state->stream->gamut_remap_matrix;
5886 stream_update.out_transfer_func =
5887 new_dm_crtc_state->stream->out_transfer_func;
a87fa993
BL		 5888 }
5889
c744e974
NK		 5890 num_plane++;
5891 }
5892
5893 if (num_plane == 0)
5894 continue;
5895
5896 ret = dm_atomic_get_state(state, &dm_state);
5897 if (ret)
5898 goto cleanup;
5899
5900 old_dm_state = dm_atomic_get_old_state(state);
5901 if (!old_dm_state) {
5902 ret = -EINVAL;
5903 goto cleanup;
5904 }
5905
5906 status = dc_stream_get_status_from_state(old_dm_state->context,
5907 new_dm_crtc_state->stream);
5908
5909 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
5910 &stream_update, status);
5911
5912 if (update_type > UPDATE_TYPE_MED) {
a87fa993 5913 update_type = UPDATE_TYPE_FULL;
eb3dc897 5914 goto cleanup;
a87fa993
BL		 5915 }
5916 }
5917
eb3dc897 5918cleanup:
a87fa993
BL		 5919 kfree(updates);
5920 kfree(surface);
5921
eb3dc897
NK		 5922 *out_type = update_type;
5923 return ret;
a87fa993 5924}
62f55537 5925
b8592b48
LL		 5926/**
5927 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
5928 * @dev: The DRM device
5929 * @state: The atomic state to commit
5930 *
5931 * Validate that the given atomic state is programmable by DC into hardware.
5932 * This involves constructing a &struct dc_state reflecting the new hardware
5933 * state we wish to commit, then querying DC to see if it is programmable. It's
5934 * important not to modify the existing DC state. Otherwise, atomic_check
5935 * may unexpectedly commit hardware changes.
5936 *
5937 * When validating the DC state, it's important that the right locks are
5938 * acquired. For full updates case which removes/adds/updates streams on one
5939 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
5940 * that any such full update commit will wait for completion of any outstanding
5941 * flip using DRMs synchronization events. See
5942 * dm_determine_update_type_for_commit()
5943 *
5944 * Note that DM adds the affected connectors for all CRTCs in state, when that
5945 * might not seem necessary. This is because DC stream creation requires the
5946 * DC sink, which is tied to the DRM connector state. Cleaning this up should
5947 * be possible but non-trivial - a possible TODO item.
5948 *
5949 * Return: -Error code if validation failed.
5950 */
7578ecda
AD		 5951static int amdgpu_dm_atomic_check(struct drm_device *dev,
5952 struct drm_atomic_state *state)
62f55537 5953{
62f55537 5954 struct amdgpu_device *adev = dev->dev_private;
eb3dc897 5955 struct dm_atomic_state *dm_state = NULL;
62f55537 5956 struct dc *dc = adev->dm.dc;
62f55537 5957 struct drm_connector *connector;
c2cea706 5958 struct drm_connector_state *old_con_state, *new_con_state;
62f55537 5959 struct drm_crtc *crtc;
fc9e9920 5960 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9e869063
LL		 5961 struct drm_plane *plane;
5962 struct drm_plane_state *old_plane_state, *new_plane_state;
a87fa993
BL		 5963 enum surface_update_type update_type = UPDATE_TYPE_FAST;
5964 enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
5965
1e88ad0a 5966 int ret, i;
e7b07cee 5967
62f55537
AG		 5968 /*
5969 * This bool will be set for true for any modeset/reset
5970 * or plane update which implies non fast surface update.
5971 */
5972 bool lock_and_validation_needed = false;
5973
5974 ret = drm_atomic_helper_check_modeset(dev, state);
01e28f9c
MD		 5975 if (ret)
5976 goto fail;
62f55537 5977
1e88ad0a
S		 5978 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5979 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
98e6436d 5980 !new_crtc_state->color_mgmt_changed &&
a93587b3 5981 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
1e88ad0a 5982 continue;
7bef1af3 5983
1e88ad0a
S		 5984 if (!new_crtc_state->enable)
5985 continue;
fc9e9920 5986
1e88ad0a
S		 5987 ret = drm_atomic_add_affected_connectors(state, crtc);
5988 if (ret)
5989 return ret;
fc9e9920 5990
1e88ad0a
S		 5991 ret = drm_atomic_add_affected_planes(state, crtc);
5992 if (ret)
5993 goto fail;
e7b07cee
HW		 5994 }
5995
2d9e6431
NK		 5996 /*
5997 * Add all primary and overlay planes on the CRTC to the state
5998 * whenever a plane is enabled to maintain correct z-ordering
5999 * and to enable fast surface updates.
6000 */
6001 drm_for_each_crtc(crtc, dev) {
6002 bool modified = false;
6003
6004 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6005 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6006 continue;
6007
6008 if (new_plane_state->crtc == crtc ||
6009 old_plane_state->crtc == crtc) {
6010 modified = true;
6011 break;
6012 }
6013 }
6014
6015 if (!modified)
6016 continue;
6017
6018 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
6019 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6020 continue;
6021
6022 new_plane_state =
6023 drm_atomic_get_plane_state(state, plane);
6024
6025 if (IS_ERR(new_plane_state)) {
6026 ret = PTR_ERR(new_plane_state);
6027 goto fail;
6028 }
6029 }
6030 }
6031
62f55537 6032 /* Remove exiting planes if they are modified */
9e869063
LL		 6033 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6034 ret = dm_update_plane_state(dc, state, plane,
6035 old_plane_state,
6036 new_plane_state,
6037 false,
6038 &lock_and_validation_needed);
6039 if (ret)
6040 goto fail;
62f55537
AG		 6041 }
6042
6043 /* Disable all crtcs which require disable */
4b9674e5
LL		 6044 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6045 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6046 old_crtc_state,
6047 new_crtc_state,
6048 false,
6049 &lock_and_validation_needed);
6050 if (ret)
6051 goto fail;
62f55537
AG		 6052 }
6053
6054 /* Enable all crtcs which require enable */
4b9674e5
LL		 6055 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6056 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6057 old_crtc_state,
6058 new_crtc_state,
6059 true,
6060 &lock_and_validation_needed);
6061 if (ret)
6062 goto fail;
62f55537
AG		 6063 }
6064
6065 /* Add new/modified planes */
9e869063
LL		 6066 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6067 ret = dm_update_plane_state(dc, state, plane,
6068 old_plane_state,
6069 new_plane_state,
6070 true,
6071 &lock_and_validation_needed);
6072 if (ret)
6073 goto fail;
62f55537
AG		 6074 }
6075
b349f76e
ES		 6076 /* Run this here since we want to validate the streams we created */
6077 ret = drm_atomic_helper_check_planes(dev, state);
6078 if (ret)
6079 goto fail;
62f55537 6080
ebdd27e1 6081 /* Check scaling and underscan changes*/
1f6010a9 6082 /* TODO Removed scaling changes validation due to inability to commit
e7b07cee
HW		 6083 * new stream into context w\o causing full reset. Need to
6084 * decide how to handle.
6085 */
c2cea706 6086 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
54d76575
LSL		 6087 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6088 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6089 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
e7b07cee
HW		 6090
6091 /* Skip any modesets/resets */
0bc9706d
LSL		 6092 if (!acrtc || drm_atomic_crtc_needs_modeset(
6093 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
e7b07cee
HW		 6094 continue;
6095
b830ebc9 6096 /* Skip any thing not scale or underscan changes */
54d76575 6097 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
e7b07cee
HW		 6098 continue;
6099
a87fa993 6100 overall_update_type = UPDATE_TYPE_FULL;
e7b07cee
HW		 6101 lock_and_validation_needed = true;
6102 }
6103
eb3dc897
NK		 6104 ret = dm_determine_update_type_for_commit(dc, state, &update_type);
6105 if (ret)
6106 goto fail;
a87fa993
BL		 6107
6108 if (overall_update_type < update_type)
6109 overall_update_type = update_type;
6110
6111 /*
6112 * lock_and_validation_needed was an old way to determine if we need to set
6113 * the global lock. Leaving it in to check if we broke any corner cases
6114 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6115 * lock_and_validation_needed false = UPDATE_TYPE_FAST
6116 */
6117 if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6118 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6119 else if (!lock_and_validation_needed && overall_update_type > UPDATE_TYPE_FAST)
6120 WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
e7b07cee 6121
e7b07cee 6122
a87fa993 6123 if (overall_update_type > UPDATE_TYPE_FAST) {
eb3dc897
NK		 6124 ret = dm_atomic_get_state(state, &dm_state);
6125 if (ret)
6126 goto fail;
e7b07cee
HW		 6127
6128 ret = do_aquire_global_lock(dev, state);
6129 if (ret)
6130 goto fail;
1dc90497 6131
e750d56d 6132 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
e7b07cee
HW		 6133 ret = -EINVAL;
6134 goto fail;
6135 }
674e78ac
NK		 6136 } else if (state->legacy_cursor_update) {
6137 /*
6138 * This is a fast cursor update coming from the plane update
6139 * helper, check if it can be done asynchronously for better
6140 * performance.
6141 */
6142 state->async_update = !drm_atomic_helper_async_check(dev, state);
e7b07cee
HW		 6143 }
6144
6145 /* Must be success */
6146 WARN_ON(ret);
6147 return ret;
6148
6149fail:
6150 if (ret == -EDEADLK)
01e28f9c 6151 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
e7b07cee 6152 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
01e28f9c 6153 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
e7b07cee 6154 else
01e28f9c 6155 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
e7b07cee
HW		 6156
6157 return ret;
6158}
6159
3ee6b26b
AD		 6160static bool is_dp_capable_without_timing_msa(struct dc *dc,
6161 struct amdgpu_dm_connector *amdgpu_dm_connector)
e7b07cee
HW		 6162{
6163 uint8_t dpcd_data;
6164 bool capable = false;
6165
c84dec2f 6166 if (amdgpu_dm_connector->dc_link &&
e7b07cee
HW		 6167 dm_helpers_dp_read_dpcd(
6168 NULL,
c84dec2f 6169 amdgpu_dm_connector->dc_link,
e7b07cee
HW		 6170 DP_DOWN_STREAM_PORT_COUNT,
6171 &dpcd_data,
6172 sizeof(dpcd_data))) {
6173 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6174 }
6175
6176 return capable;
6177}
98e6436d
AK		 6178void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6179 struct edid *edid)
e7b07cee
HW		 6180{
6181 int i;
e7b07cee
HW		 6182 bool edid_check_required;
6183 struct detailed_timing *timing;
6184 struct detailed_non_pixel *data;
6185 struct detailed_data_monitor_range *range;
c84dec2f
HW		 6186 struct amdgpu_dm_connector *amdgpu_dm_connector =
6187 to_amdgpu_dm_connector(connector);
bb47de73 6188 struct dm_connector_state *dm_con_state = NULL;
e7b07cee
HW		 6189
6190 struct drm_device *dev = connector->dev;
6191 struct amdgpu_device *adev = dev->dev_private;
bb47de73 6192 bool freesync_capable = false;
b830ebc9 6193
8218d7f1
HW		 6194 if (!connector->state) {
6195 DRM_ERROR("%s - Connector has no state", __func__);
bb47de73 6196 goto update;
8218d7f1
HW		 6197 }
6198
98e6436d
AK		 6199 if (!edid) {
6200 dm_con_state = to_dm_connector_state(connector->state);
6201
6202 amdgpu_dm_connector->min_vfreq = 0;
6203 amdgpu_dm_connector->max_vfreq = 0;
6204 amdgpu_dm_connector->pixel_clock_mhz = 0;
6205
bb47de73 6206 goto update;
98e6436d
AK		 6207 }
6208
8218d7f1
HW		 6209 dm_con_state = to_dm_connector_state(connector->state);
6210
e7b07cee 6211 edid_check_required = false;
c84dec2f 6212 if (!amdgpu_dm_connector->dc_sink) {
e7b07cee 6213 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
bb47de73 6214 goto update;
e7b07cee
HW		 6215 }
6216 if (!adev->dm.freesync_module)
bb47de73 6217 goto update;
e7b07cee
HW		 6218 /*
6219 * if edid non zero restrict freesync only for dp and edp
6220 */
6221 if (edid) {
c84dec2f
HW		 6222 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6223 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
e7b07cee
HW		 6224 edid_check_required = is_dp_capable_without_timing_msa(
6225 adev->dm.dc,
c84dec2f 6226 amdgpu_dm_connector);
e7b07cee
HW		 6227 }
6228 }
e7b07cee
HW		 6229 if (edid_check_required == true && (edid->version > 1 ||
6230 (edid->version == 1 && edid->revision > 1))) {
6231 for (i = 0; i < 4; i++) {
6232
6233 timing = &edid->detailed_timings[i];
6234 data = &timing->data.other_data;
6235 range = &data->data.range;
6236 /*
6237 * Check if monitor has continuous frequency mode
6238 */
6239 if (data->type != EDID_DETAIL_MONITOR_RANGE)
6240 continue;
6241 /*
6242 * Check for flag range limits only. If flag == 1 then
6243 * no additional timing information provided.
6244 * Default GTF, GTF Secondary curve and CVT are not
6245 * supported
6246 */
6247 if (range->flags != 1)
6248 continue;
6249
c84dec2f
HW		 6250 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6251 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6252 amdgpu_dm_connector->pixel_clock_mhz =
e7b07cee
HW		 6253 range->pixel_clock_mhz * 10;
6254 break;
6255 }
6256
c84dec2f 6257 if (amdgpu_dm_connector->max_vfreq -
98e6436d
AK		 6258 amdgpu_dm_connector->min_vfreq > 10) {
6259
bb47de73 6260 freesync_capable = true;
e7b07cee
HW		 6261 }
6262 }
bb47de73
NK		 6263
6264update:
6265 if (dm_con_state)
6266 dm_con_state->freesync_capable = freesync_capable;
6267
6268 if (connector->vrr_capable_property)
6269 drm_connector_set_vrr_capable_property(connector,
6270 freesync_capable);
e7b07cee
HW		 6271}
6272
Linux 6.x block layer and io_uring tree(s)