drm/amdkfd: Introduce kfd_node struct (v5)
[linux-block.git] / drivers / gpu / drm / amd / amdkfd / kfd_topology.c
CommitLineData
d87f36a0 1// SPDX-License-Identifier: GPL-2.0 OR MIT
5b5c4e40 2/*
d87f36a0 3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5b5c4e40
EP
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/pci.h>
27#include <linux/errno.h>
28#include <linux/acpi.h>
29#include <linux/hash.h>
30#include <linux/cpufreq.h>
f7c826ad 31#include <linux/log2.h>
520b8fb7
FK
32#include <linux/dmi.h>
33#include <linux/atomic.h>
5b5c4e40
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34
35#include "kfd_priv.h"
36#include "kfd_crat.h"
37#include "kfd_topology.h"
851a645e 38#include "kfd_device_queue_manager.h"
64d1c3a4 39#include "kfd_iommu.h"
5a75ea56 40#include "kfd_svm.h"
5b87245f 41#include "amdgpu_amdkfd.h"
0dee45a2 42#include "amdgpu_ras.h"
0f28cca8 43#include "amdgpu.h"
5b5c4e40 44
4f449311
HK
45/* topology_device_list - Master list of all topology devices */
46static struct list_head topology_device_list;
520b8fb7 47static struct kfd_system_properties sys_props;
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EP
48
49static DECLARE_RWSEM(topology_lock);
46d18d51 50static uint32_t topology_crat_proximity_domain;
5b5c4e40 51
46d18d51 52struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(
3a87177e
HK
53 uint32_t proximity_domain)
54{
55 struct kfd_topology_device *top_dev;
56 struct kfd_topology_device *device = NULL;
57
3a87177e
HK
58 list_for_each_entry(top_dev, &topology_device_list, list)
59 if (top_dev->proximity_domain == proximity_domain) {
60 device = top_dev;
61 break;
62 }
63
46d18d51
MJ
64 return device;
65}
66
67struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
68 uint32_t proximity_domain)
69{
70 struct kfd_topology_device *device = NULL;
71
72 down_read(&topology_lock);
73
74 device = kfd_topology_device_by_proximity_domain_no_lock(
75 proximity_domain);
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HK
76 up_read(&topology_lock);
77
78 return device;
79}
80
44d8cc6f 81struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id)
5b5c4e40 82{
44d8cc6f
YZ
83 struct kfd_topology_device *top_dev = NULL;
84 struct kfd_topology_device *ret = NULL;
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EP
85
86 down_read(&topology_lock);
87
88 list_for_each_entry(top_dev, &topology_device_list, list)
89 if (top_dev->gpu_id == gpu_id) {
44d8cc6f 90 ret = top_dev;
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91 break;
92 }
93
94 up_read(&topology_lock);
95
44d8cc6f
YZ
96 return ret;
97}
98
8dc1db31 99struct kfd_node *kfd_device_by_id(uint32_t gpu_id)
44d8cc6f
YZ
100{
101 struct kfd_topology_device *top_dev;
102
103 top_dev = kfd_topology_device_by_id(gpu_id);
104 if (!top_dev)
105 return NULL;
106
107 return top_dev->gpu;
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EP
108}
109
8dc1db31 110struct kfd_node *kfd_device_by_pci_dev(const struct pci_dev *pdev)
5b5c4e40
EP
111{
112 struct kfd_topology_device *top_dev;
8dc1db31 113 struct kfd_node *device = NULL;
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114
115 down_read(&topology_lock);
116
117 list_for_each_entry(top_dev, &topology_device_list, list)
d69a3b76 118 if (top_dev->gpu && top_dev->gpu->adev->pdev == pdev) {
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119 device = top_dev->gpu;
120 break;
121 }
122
123 up_read(&topology_lock);
124
125 return device;
126}
127
8dc1db31 128struct kfd_node *kfd_device_by_adev(const struct amdgpu_device *adev)
1dde0ea9
FK
129{
130 struct kfd_topology_device *top_dev;
8dc1db31 131 struct kfd_node *device = NULL;
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132
133 down_read(&topology_lock);
134
135 list_for_each_entry(top_dev, &topology_device_list, list)
574c4183 136 if (top_dev->gpu && top_dev->gpu->adev == adev) {
1dde0ea9
FK
137 device = top_dev->gpu;
138 break;
139 }
140
141 up_read(&topology_lock);
142
143 return device;
144}
145
3a87177e 146/* Called with write topology_lock acquired */
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147static void kfd_release_topology_device(struct kfd_topology_device *dev)
148{
149 struct kfd_mem_properties *mem;
150 struct kfd_cache_properties *cache;
151 struct kfd_iolink_properties *iolink;
0f28cca8 152 struct kfd_iolink_properties *p2plink;
f4757347 153 struct kfd_perf_properties *perf;
5b5c4e40 154
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EP
155 list_del(&dev->list);
156
157 while (dev->mem_props.next != &dev->mem_props) {
158 mem = container_of(dev->mem_props.next,
159 struct kfd_mem_properties, list);
160 list_del(&mem->list);
161 kfree(mem);
162 }
163
164 while (dev->cache_props.next != &dev->cache_props) {
165 cache = container_of(dev->cache_props.next,
166 struct kfd_cache_properties, list);
167 list_del(&cache->list);
168 kfree(cache);
169 }
170
171 while (dev->io_link_props.next != &dev->io_link_props) {
172 iolink = container_of(dev->io_link_props.next,
173 struct kfd_iolink_properties, list);
174 list_del(&iolink->list);
175 kfree(iolink);
176 }
177
0f28cca8
RE
178 while (dev->p2p_link_props.next != &dev->p2p_link_props) {
179 p2plink = container_of(dev->p2p_link_props.next,
180 struct kfd_iolink_properties, list);
181 list_del(&p2plink->list);
182 kfree(p2plink);
183 }
184
f4757347
AL
185 while (dev->perf_props.next != &dev->perf_props) {
186 perf = container_of(dev->perf_props.next,
187 struct kfd_perf_properties, list);
188 list_del(&perf->list);
189 kfree(perf);
190 }
191
5b5c4e40 192 kfree(dev);
5b5c4e40
EP
193}
194
4f449311 195void kfd_release_topology_device_list(struct list_head *device_list)
5b5c4e40
EP
196{
197 struct kfd_topology_device *dev;
198
4f449311
HK
199 while (!list_empty(device_list)) {
200 dev = list_first_entry(device_list,
201 struct kfd_topology_device, list);
5b5c4e40 202 kfd_release_topology_device(dev);
4f449311 203 }
5b5c4e40
EP
204}
205
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HK
206static void kfd_release_live_view(void)
207{
208 kfd_release_topology_device_list(&topology_device_list);
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209 memset(&sys_props, 0, sizeof(sys_props));
210}
211
4f449311
HK
212struct kfd_topology_device *kfd_create_topology_device(
213 struct list_head *device_list)
5b5c4e40
EP
214{
215 struct kfd_topology_device *dev;
216
217 dev = kfd_alloc_struct(dev);
4eacc26b 218 if (!dev) {
5b5c4e40 219 pr_err("No memory to allocate a topology device");
16b9201c 220 return NULL;
5b5c4e40
EP
221 }
222
223 INIT_LIST_HEAD(&dev->mem_props);
224 INIT_LIST_HEAD(&dev->cache_props);
225 INIT_LIST_HEAD(&dev->io_link_props);
0f28cca8 226 INIT_LIST_HEAD(&dev->p2p_link_props);
f4757347 227 INIT_LIST_HEAD(&dev->perf_props);
5b5c4e40 228
4f449311 229 list_add_tail(&dev->list, device_list);
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230
231 return dev;
16b9201c 232}
5b5c4e40 233
5b5c4e40 234
83a13ef5
FK
235#define sysfs_show_gen_prop(buffer, offs, fmt, ...) \
236 (offs += snprintf(buffer+offs, PAGE_SIZE-offs, \
237 fmt, __VA_ARGS__))
238#define sysfs_show_32bit_prop(buffer, offs, name, value) \
239 sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
240#define sysfs_show_64bit_prop(buffer, offs, name, value) \
241 sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
242#define sysfs_show_32bit_val(buffer, offs, value) \
243 sysfs_show_gen_prop(buffer, offs, "%u\n", value)
244#define sysfs_show_str_val(buffer, offs, value) \
245 sysfs_show_gen_prop(buffer, offs, "%s\n", value)
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246
247static ssize_t sysprops_show(struct kobject *kobj, struct attribute *attr,
248 char *buffer)
249{
83a13ef5 250 int offs = 0;
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EP
251
252 /* Making sure that the buffer is an empty string */
253 buffer[0] = 0;
254
255 if (attr == &sys_props.attr_genid) {
83a13ef5
FK
256 sysfs_show_32bit_val(buffer, offs,
257 sys_props.generation_count);
5b5c4e40 258 } else if (attr == &sys_props.attr_props) {
83a13ef5
FK
259 sysfs_show_64bit_prop(buffer, offs, "platform_oem",
260 sys_props.platform_oem);
261 sysfs_show_64bit_prop(buffer, offs, "platform_id",
262 sys_props.platform_id);
263 sysfs_show_64bit_prop(buffer, offs, "platform_rev",
264 sys_props.platform_rev);
5b5c4e40 265 } else {
83a13ef5 266 offs = -EINVAL;
5b5c4e40
EP
267 }
268
83a13ef5 269 return offs;
5b5c4e40
EP
270}
271
5108d768
YZ
272static void kfd_topology_kobj_release(struct kobject *kobj)
273{
274 kfree(kobj);
275}
276
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EP
277static const struct sysfs_ops sysprops_ops = {
278 .show = sysprops_show,
279};
280
4fa01c63 281static const struct kobj_type sysprops_type = {
5108d768 282 .release = kfd_topology_kobj_release,
5b5c4e40
EP
283 .sysfs_ops = &sysprops_ops,
284};
285
286static ssize_t iolink_show(struct kobject *kobj, struct attribute *attr,
287 char *buffer)
288{
83a13ef5 289 int offs = 0;
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EP
290 struct kfd_iolink_properties *iolink;
291
292 /* Making sure that the buffer is an empty string */
293 buffer[0] = 0;
294
295 iolink = container_of(attr, struct kfd_iolink_properties, attr);
6b855f7b
HK
296 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu))
297 return -EPERM;
83a13ef5
FK
298 sysfs_show_32bit_prop(buffer, offs, "type", iolink->iolink_type);
299 sysfs_show_32bit_prop(buffer, offs, "version_major", iolink->ver_maj);
300 sysfs_show_32bit_prop(buffer, offs, "version_minor", iolink->ver_min);
301 sysfs_show_32bit_prop(buffer, offs, "node_from", iolink->node_from);
302 sysfs_show_32bit_prop(buffer, offs, "node_to", iolink->node_to);
303 sysfs_show_32bit_prop(buffer, offs, "weight", iolink->weight);
304 sysfs_show_32bit_prop(buffer, offs, "min_latency", iolink->min_latency);
305 sysfs_show_32bit_prop(buffer, offs, "max_latency", iolink->max_latency);
306 sysfs_show_32bit_prop(buffer, offs, "min_bandwidth",
307 iolink->min_bandwidth);
308 sysfs_show_32bit_prop(buffer, offs, "max_bandwidth",
309 iolink->max_bandwidth);
310 sysfs_show_32bit_prop(buffer, offs, "recommended_transfer_size",
311 iolink->rec_transfer_size);
312 sysfs_show_32bit_prop(buffer, offs, "flags", iolink->flags);
313
314 return offs;
5b5c4e40
EP
315}
316
317static const struct sysfs_ops iolink_ops = {
318 .show = iolink_show,
319};
320
4fa01c63 321static const struct kobj_type iolink_type = {
5108d768 322 .release = kfd_topology_kobj_release,
5b5c4e40
EP
323 .sysfs_ops = &iolink_ops,
324};
325
326static ssize_t mem_show(struct kobject *kobj, struct attribute *attr,
327 char *buffer)
328{
83a13ef5 329 int offs = 0;
5b5c4e40
EP
330 struct kfd_mem_properties *mem;
331
332 /* Making sure that the buffer is an empty string */
333 buffer[0] = 0;
334
335 mem = container_of(attr, struct kfd_mem_properties, attr);
6b855f7b
HK
336 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu))
337 return -EPERM;
83a13ef5
FK
338 sysfs_show_32bit_prop(buffer, offs, "heap_type", mem->heap_type);
339 sysfs_show_64bit_prop(buffer, offs, "size_in_bytes",
340 mem->size_in_bytes);
341 sysfs_show_32bit_prop(buffer, offs, "flags", mem->flags);
342 sysfs_show_32bit_prop(buffer, offs, "width", mem->width);
343 sysfs_show_32bit_prop(buffer, offs, "mem_clk_max",
344 mem->mem_clk_max);
345
346 return offs;
5b5c4e40
EP
347}
348
349static const struct sysfs_ops mem_ops = {
350 .show = mem_show,
351};
352
4fa01c63 353static const struct kobj_type mem_type = {
5108d768 354 .release = kfd_topology_kobj_release,
5b5c4e40
EP
355 .sysfs_ops = &mem_ops,
356};
357
358static ssize_t kfd_cache_show(struct kobject *kobj, struct attribute *attr,
359 char *buffer)
360{
83a13ef5 361 int offs = 0;
bc0c75a3 362 uint32_t i, j;
5b5c4e40
EP
363 struct kfd_cache_properties *cache;
364
365 /* Making sure that the buffer is an empty string */
366 buffer[0] = 0;
5b5c4e40 367 cache = container_of(attr, struct kfd_cache_properties, attr);
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HK
368 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu))
369 return -EPERM;
83a13ef5 370 sysfs_show_32bit_prop(buffer, offs, "processor_id_low",
5b5c4e40 371 cache->processor_id_low);
83a13ef5
FK
372 sysfs_show_32bit_prop(buffer, offs, "level", cache->cache_level);
373 sysfs_show_32bit_prop(buffer, offs, "size", cache->cache_size);
374 sysfs_show_32bit_prop(buffer, offs, "cache_line_size",
375 cache->cacheline_size);
376 sysfs_show_32bit_prop(buffer, offs, "cache_lines_per_tag",
377 cache->cachelines_per_tag);
378 sysfs_show_32bit_prop(buffer, offs, "association", cache->cache_assoc);
379 sysfs_show_32bit_prop(buffer, offs, "latency", cache->cache_latency);
380 sysfs_show_32bit_prop(buffer, offs, "type", cache->cache_type);
c0cc999f 381
83a13ef5 382 offs += snprintf(buffer+offs, PAGE_SIZE-offs, "sibling_map ");
c0cc999f 383 for (i = 0; i < cache->sibling_map_size; i++)
83a13ef5 384 for (j = 0; j < sizeof(cache->sibling_map[0])*8; j++)
bc0c75a3 385 /* Check each bit */
83a13ef5 386 offs += snprintf(buffer+offs, PAGE_SIZE-offs, "%d,",
c0cc999f 387 (cache->sibling_map[i] >> j) & 1);
83a13ef5 388
bc0c75a3 389 /* Replace the last "," with end of line */
83a13ef5
FK
390 buffer[offs-1] = '\n';
391 return offs;
5b5c4e40
EP
392}
393
394static const struct sysfs_ops cache_ops = {
395 .show = kfd_cache_show,
396};
397
4fa01c63 398static const struct kobj_type cache_type = {
5108d768 399 .release = kfd_topology_kobj_release,
5b5c4e40
EP
400 .sysfs_ops = &cache_ops,
401};
402
f4757347
AL
403/****** Sysfs of Performance Counters ******/
404
405struct kfd_perf_attr {
406 struct kobj_attribute attr;
407 uint32_t data;
408};
409
410static ssize_t perf_show(struct kobject *kobj, struct kobj_attribute *attrs,
411 char *buf)
412{
83a13ef5 413 int offs = 0;
f4757347
AL
414 struct kfd_perf_attr *attr;
415
416 buf[0] = 0;
417 attr = container_of(attrs, struct kfd_perf_attr, attr);
418 if (!attr->data) /* invalid data for PMC */
419 return 0;
420 else
83a13ef5 421 return sysfs_show_32bit_val(buf, offs, attr->data);
f4757347
AL
422}
423
424#define KFD_PERF_DESC(_name, _data) \
425{ \
426 .attr = __ATTR(_name, 0444, perf_show, NULL), \
427 .data = _data, \
428}
429
430static struct kfd_perf_attr perf_attr_iommu[] = {
431 KFD_PERF_DESC(max_concurrent, 0),
432 KFD_PERF_DESC(num_counters, 0),
433 KFD_PERF_DESC(counter_ids, 0),
434};
435/****************************************/
436
5b5c4e40
EP
437static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
438 char *buffer)
439{
83a13ef5 440 int offs = 0;
5b5c4e40 441 struct kfd_topology_device *dev;
f7c826ad 442 uint32_t log_max_watch_addr;
5b5c4e40
EP
443
444 /* Making sure that the buffer is an empty string */
445 buffer[0] = 0;
446
447 if (strcmp(attr->name, "gpu_id") == 0) {
448 dev = container_of(attr, struct kfd_topology_device,
449 attr_gpuid);
6b855f7b
HK
450 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
451 return -EPERM;
83a13ef5 452 return sysfs_show_32bit_val(buffer, offs, dev->gpu_id);
f7c826ad
AS
453 }
454
455 if (strcmp(attr->name, "name") == 0) {
5b5c4e40
EP
456 dev = container_of(attr, struct kfd_topology_device,
457 attr_name);
c181159a 458
6b855f7b
HK
459 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
460 return -EPERM;
83a13ef5 461 return sysfs_show_str_val(buffer, offs, dev->node_props.name);
f7c826ad 462 }
5b5c4e40 463
f7c826ad
AS
464 dev = container_of(attr, struct kfd_topology_device,
465 attr_props);
6b855f7b
HK
466 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
467 return -EPERM;
83a13ef5
FK
468 sysfs_show_32bit_prop(buffer, offs, "cpu_cores_count",
469 dev->node_props.cpu_cores_count);
470 sysfs_show_32bit_prop(buffer, offs, "simd_count",
6127896f 471 dev->gpu ? dev->node_props.simd_count : 0);
83a13ef5
FK
472 sysfs_show_32bit_prop(buffer, offs, "mem_banks_count",
473 dev->node_props.mem_banks_count);
474 sysfs_show_32bit_prop(buffer, offs, "caches_count",
475 dev->node_props.caches_count);
476 sysfs_show_32bit_prop(buffer, offs, "io_links_count",
477 dev->node_props.io_links_count);
0f28cca8
RE
478 sysfs_show_32bit_prop(buffer, offs, "p2p_links_count",
479 dev->node_props.p2p_links_count);
83a13ef5
FK
480 sysfs_show_32bit_prop(buffer, offs, "cpu_core_id_base",
481 dev->node_props.cpu_core_id_base);
482 sysfs_show_32bit_prop(buffer, offs, "simd_id_base",
483 dev->node_props.simd_id_base);
484 sysfs_show_32bit_prop(buffer, offs, "max_waves_per_simd",
485 dev->node_props.max_waves_per_simd);
486 sysfs_show_32bit_prop(buffer, offs, "lds_size_in_kb",
487 dev->node_props.lds_size_in_kb);
488 sysfs_show_32bit_prop(buffer, offs, "gds_size_in_kb",
489 dev->node_props.gds_size_in_kb);
490 sysfs_show_32bit_prop(buffer, offs, "num_gws",
491 dev->node_props.num_gws);
492 sysfs_show_32bit_prop(buffer, offs, "wave_front_size",
493 dev->node_props.wave_front_size);
494 sysfs_show_32bit_prop(buffer, offs, "array_count",
495 dev->node_props.array_count);
496 sysfs_show_32bit_prop(buffer, offs, "simd_arrays_per_engine",
497 dev->node_props.simd_arrays_per_engine);
498 sysfs_show_32bit_prop(buffer, offs, "cu_per_simd_array",
499 dev->node_props.cu_per_simd_array);
500 sysfs_show_32bit_prop(buffer, offs, "simd_per_cu",
501 dev->node_props.simd_per_cu);
502 sysfs_show_32bit_prop(buffer, offs, "max_slots_scratch_cu",
503 dev->node_props.max_slots_scratch_cu);
9d6fa9c7
GS
504 sysfs_show_32bit_prop(buffer, offs, "gfx_target_version",
505 dev->node_props.gfx_target_version);
83a13ef5
FK
506 sysfs_show_32bit_prop(buffer, offs, "vendor_id",
507 dev->node_props.vendor_id);
508 sysfs_show_32bit_prop(buffer, offs, "device_id",
509 dev->node_props.device_id);
510 sysfs_show_32bit_prop(buffer, offs, "location_id",
511 dev->node_props.location_id);
512 sysfs_show_32bit_prop(buffer, offs, "domain",
513 dev->node_props.domain);
514 sysfs_show_32bit_prop(buffer, offs, "drm_render_minor",
515 dev->node_props.drm_render_minor);
516 sysfs_show_64bit_prop(buffer, offs, "hive_id",
517 dev->node_props.hive_id);
518 sysfs_show_32bit_prop(buffer, offs, "num_sdma_engines",
519 dev->node_props.num_sdma_engines);
520 sysfs_show_32bit_prop(buffer, offs, "num_sdma_xgmi_engines",
521 dev->node_props.num_sdma_xgmi_engines);
522 sysfs_show_32bit_prop(buffer, offs, "num_sdma_queues_per_engine",
523 dev->node_props.num_sdma_queues_per_engine);
524 sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
525 dev->node_props.num_cp_queues);
f7c826ad
AS
526
527 if (dev->gpu) {
528 log_max_watch_addr =
8dc1db31 529 __ilog2_u32(dev->gpu->kfd->device_info.num_of_watch_points);
f7c826ad
AS
530
531 if (log_max_watch_addr) {
532 dev->node_props.capability |=
533 HSA_CAP_WATCH_POINTS_SUPPORTED;
534
535 dev->node_props.capability |=
536 ((log_max_watch_addr <<
537 HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT) &
538 HSA_CAP_WATCH_POINTS_TOTALBITS_MASK);
5b5c4e40
EP
539 }
540
7eb0502a 541 if (dev->gpu->adev->asic_type == CHIP_TONGA)
413e85d5
BG
542 dev->node_props.capability |=
543 HSA_CAP_AQL_QUEUE_DOUBLE_MAP;
544
83a13ef5 545 sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_fcompute",
3a87177e 546 dev->node_props.max_engine_clk_fcompute);
42e08c78 547
83a13ef5 548 sysfs_show_64bit_prop(buffer, offs, "local_mem_size", 0ULL);
f7c826ad 549
83a13ef5 550 sysfs_show_32bit_prop(buffer, offs, "fw_version",
8dc1db31 551 dev->gpu->kfd->mec_fw_version);
83a13ef5
FK
552 sysfs_show_32bit_prop(buffer, offs, "capability",
553 dev->node_props.capability);
554 sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version",
8dc1db31 555 dev->gpu->kfd->sdma_fw_version);
11964258 556 sysfs_show_64bit_prop(buffer, offs, "unique_id",
02274fc0 557 dev->gpu->adev->unique_id);
11964258 558
5b5c4e40
EP
559 }
560
83a13ef5
FK
561 return sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_ccompute",
562 cpufreq_quick_get_max(0)/1000);
5b5c4e40
EP
563}
564
565static const struct sysfs_ops node_ops = {
566 .show = node_show,
567};
568
4fa01c63 569static const struct kobj_type node_type = {
5108d768 570 .release = kfd_topology_kobj_release,
5b5c4e40
EP
571 .sysfs_ops = &node_ops,
572};
573
574static void kfd_remove_sysfs_file(struct kobject *kobj, struct attribute *attr)
575{
576 sysfs_remove_file(kobj, attr);
577 kobject_del(kobj);
578 kobject_put(kobj);
579}
580
581static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
582{
0f28cca8 583 struct kfd_iolink_properties *p2plink;
5b5c4e40
EP
584 struct kfd_iolink_properties *iolink;
585 struct kfd_cache_properties *cache;
586 struct kfd_mem_properties *mem;
f4757347 587 struct kfd_perf_properties *perf;
5b5c4e40 588
5b5c4e40
EP
589 if (dev->kobj_iolink) {
590 list_for_each_entry(iolink, &dev->io_link_props, list)
591 if (iolink->kobj) {
592 kfd_remove_sysfs_file(iolink->kobj,
593 &iolink->attr);
16b9201c 594 iolink->kobj = NULL;
5b5c4e40
EP
595 }
596 kobject_del(dev->kobj_iolink);
597 kobject_put(dev->kobj_iolink);
16b9201c 598 dev->kobj_iolink = NULL;
5b5c4e40
EP
599 }
600
0f28cca8
RE
601 if (dev->kobj_p2plink) {
602 list_for_each_entry(p2plink, &dev->p2p_link_props, list)
603 if (p2plink->kobj) {
604 kfd_remove_sysfs_file(p2plink->kobj,
605 &p2plink->attr);
606 p2plink->kobj = NULL;
607 }
608 kobject_del(dev->kobj_p2plink);
609 kobject_put(dev->kobj_p2plink);
610 dev->kobj_p2plink = NULL;
611 }
612
5b5c4e40
EP
613 if (dev->kobj_cache) {
614 list_for_each_entry(cache, &dev->cache_props, list)
615 if (cache->kobj) {
616 kfd_remove_sysfs_file(cache->kobj,
617 &cache->attr);
16b9201c 618 cache->kobj = NULL;
5b5c4e40
EP
619 }
620 kobject_del(dev->kobj_cache);
621 kobject_put(dev->kobj_cache);
16b9201c 622 dev->kobj_cache = NULL;
5b5c4e40
EP
623 }
624
625 if (dev->kobj_mem) {
626 list_for_each_entry(mem, &dev->mem_props, list)
627 if (mem->kobj) {
628 kfd_remove_sysfs_file(mem->kobj, &mem->attr);
16b9201c 629 mem->kobj = NULL;
5b5c4e40
EP
630 }
631 kobject_del(dev->kobj_mem);
632 kobject_put(dev->kobj_mem);
16b9201c 633 dev->kobj_mem = NULL;
5b5c4e40
EP
634 }
635
f4757347
AL
636 if (dev->kobj_perf) {
637 list_for_each_entry(perf, &dev->perf_props, list) {
638 kfree(perf->attr_group);
639 perf->attr_group = NULL;
640 }
641 kobject_del(dev->kobj_perf);
642 kobject_put(dev->kobj_perf);
643 dev->kobj_perf = NULL;
644 }
645
5b5c4e40
EP
646 if (dev->kobj_node) {
647 sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid);
648 sysfs_remove_file(dev->kobj_node, &dev->attr_name);
649 sysfs_remove_file(dev->kobj_node, &dev->attr_props);
650 kobject_del(dev->kobj_node);
651 kobject_put(dev->kobj_node);
16b9201c 652 dev->kobj_node = NULL;
5b5c4e40
EP
653 }
654}
655
656static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
657 uint32_t id)
658{
0f28cca8 659 struct kfd_iolink_properties *p2plink;
5b5c4e40
EP
660 struct kfd_iolink_properties *iolink;
661 struct kfd_cache_properties *cache;
662 struct kfd_mem_properties *mem;
f4757347 663 struct kfd_perf_properties *perf;
5b5c4e40 664 int ret;
f4757347
AL
665 uint32_t i, num_attrs;
666 struct attribute **attrs;
5b5c4e40 667
32fa8219
FK
668 if (WARN_ON(dev->kobj_node))
669 return -EEXIST;
670
5b5c4e40
EP
671 /*
672 * Creating the sysfs folders
673 */
5b5c4e40
EP
674 dev->kobj_node = kfd_alloc_struct(dev->kobj_node);
675 if (!dev->kobj_node)
676 return -ENOMEM;
677
678 ret = kobject_init_and_add(dev->kobj_node, &node_type,
679 sys_props.kobj_nodes, "%d", id);
20eca012
QW
680 if (ret < 0) {
681 kobject_put(dev->kobj_node);
5b5c4e40 682 return ret;
20eca012 683 }
5b5c4e40
EP
684
685 dev->kobj_mem = kobject_create_and_add("mem_banks", dev->kobj_node);
686 if (!dev->kobj_mem)
687 return -ENOMEM;
688
689 dev->kobj_cache = kobject_create_and_add("caches", dev->kobj_node);
690 if (!dev->kobj_cache)
691 return -ENOMEM;
692
693 dev->kobj_iolink = kobject_create_and_add("io_links", dev->kobj_node);
694 if (!dev->kobj_iolink)
695 return -ENOMEM;
696
0f28cca8
RE
697 dev->kobj_p2plink = kobject_create_and_add("p2p_links", dev->kobj_node);
698 if (!dev->kobj_p2plink)
699 return -ENOMEM;
700
f4757347
AL
701 dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node);
702 if (!dev->kobj_perf)
703 return -ENOMEM;
704
5b5c4e40
EP
705 /*
706 * Creating sysfs files for node properties
707 */
708 dev->attr_gpuid.name = "gpu_id";
709 dev->attr_gpuid.mode = KFD_SYSFS_FILE_MODE;
710 sysfs_attr_init(&dev->attr_gpuid);
711 dev->attr_name.name = "name";
712 dev->attr_name.mode = KFD_SYSFS_FILE_MODE;
713 sysfs_attr_init(&dev->attr_name);
714 dev->attr_props.name = "properties";
715 dev->attr_props.mode = KFD_SYSFS_FILE_MODE;
716 sysfs_attr_init(&dev->attr_props);
717 ret = sysfs_create_file(dev->kobj_node, &dev->attr_gpuid);
718 if (ret < 0)
719 return ret;
720 ret = sysfs_create_file(dev->kobj_node, &dev->attr_name);
721 if (ret < 0)
722 return ret;
723 ret = sysfs_create_file(dev->kobj_node, &dev->attr_props);
724 if (ret < 0)
725 return ret;
726
727 i = 0;
728 list_for_each_entry(mem, &dev->mem_props, list) {
729 mem->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
730 if (!mem->kobj)
731 return -ENOMEM;
732 ret = kobject_init_and_add(mem->kobj, &mem_type,
733 dev->kobj_mem, "%d", i);
20eca012
QW
734 if (ret < 0) {
735 kobject_put(mem->kobj);
5b5c4e40 736 return ret;
20eca012 737 }
5b5c4e40
EP
738
739 mem->attr.name = "properties";
740 mem->attr.mode = KFD_SYSFS_FILE_MODE;
741 sysfs_attr_init(&mem->attr);
742 ret = sysfs_create_file(mem->kobj, &mem->attr);
743 if (ret < 0)
744 return ret;
745 i++;
746 }
747
748 i = 0;
749 list_for_each_entry(cache, &dev->cache_props, list) {
750 cache->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
751 if (!cache->kobj)
752 return -ENOMEM;
753 ret = kobject_init_and_add(cache->kobj, &cache_type,
754 dev->kobj_cache, "%d", i);
20eca012
QW
755 if (ret < 0) {
756 kobject_put(cache->kobj);
5b5c4e40 757 return ret;
20eca012 758 }
5b5c4e40
EP
759
760 cache->attr.name = "properties";
761 cache->attr.mode = KFD_SYSFS_FILE_MODE;
762 sysfs_attr_init(&cache->attr);
763 ret = sysfs_create_file(cache->kobj, &cache->attr);
764 if (ret < 0)
765 return ret;
766 i++;
767 }
768
769 i = 0;
770 list_for_each_entry(iolink, &dev->io_link_props, list) {
771 iolink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
772 if (!iolink->kobj)
773 return -ENOMEM;
774 ret = kobject_init_and_add(iolink->kobj, &iolink_type,
775 dev->kobj_iolink, "%d", i);
20eca012
QW
776 if (ret < 0) {
777 kobject_put(iolink->kobj);
5b5c4e40 778 return ret;
20eca012 779 }
5b5c4e40
EP
780
781 iolink->attr.name = "properties";
782 iolink->attr.mode = KFD_SYSFS_FILE_MODE;
783 sysfs_attr_init(&iolink->attr);
784 ret = sysfs_create_file(iolink->kobj, &iolink->attr);
785 if (ret < 0)
786 return ret;
787 i++;
f4757347
AL
788 }
789
0f28cca8
RE
790 i = 0;
791 list_for_each_entry(p2plink, &dev->p2p_link_props, list) {
792 p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
793 if (!p2plink->kobj)
794 return -ENOMEM;
795 ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
796 dev->kobj_p2plink, "%d", i);
797 if (ret < 0) {
798 kobject_put(p2plink->kobj);
799 return ret;
800 }
801
802 p2plink->attr.name = "properties";
803 p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
1f9d1ff1 804 sysfs_attr_init(&p2plink->attr);
0f28cca8
RE
805 ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
806 if (ret < 0)
807 return ret;
808 i++;
809 }
810
f4757347 811 /* All hardware blocks have the same number of attributes. */
3f866f5f 812 num_attrs = ARRAY_SIZE(perf_attr_iommu);
f4757347
AL
813 list_for_each_entry(perf, &dev->perf_props, list) {
814 perf->attr_group = kzalloc(sizeof(struct kfd_perf_attr)
815 * num_attrs + sizeof(struct attribute_group),
816 GFP_KERNEL);
817 if (!perf->attr_group)
818 return -ENOMEM;
819
820 attrs = (struct attribute **)(perf->attr_group + 1);
821 if (!strcmp(perf->block_name, "iommu")) {
822 /* Information of IOMMU's num_counters and counter_ids is shown
823 * under /sys/bus/event_source/devices/amd_iommu. We don't
824 * duplicate here.
825 */
826 perf_attr_iommu[0].data = perf->max_concurrent;
827 for (i = 0; i < num_attrs; i++)
828 attrs[i] = &perf_attr_iommu[i].attr.attr;
829 }
830 perf->attr_group->name = perf->block_name;
831 perf->attr_group->attrs = attrs;
832 ret = sysfs_create_group(dev->kobj_perf, perf->attr_group);
833 if (ret < 0)
834 return ret;
835 }
5b5c4e40
EP
836
837 return 0;
838}
839
3a87177e 840/* Called with write topology lock acquired */
5b5c4e40
EP
841static int kfd_build_sysfs_node_tree(void)
842{
843 struct kfd_topology_device *dev;
844 int ret;
845 uint32_t i = 0;
846
847 list_for_each_entry(dev, &topology_device_list, list) {
8dfead6c 848 ret = kfd_build_sysfs_node_entry(dev, i);
5b5c4e40
EP
849 if (ret < 0)
850 return ret;
851 i++;
852 }
853
854 return 0;
855}
856
3a87177e 857/* Called with write topology lock acquired */
5b5c4e40
EP
858static void kfd_remove_sysfs_node_tree(void)
859{
860 struct kfd_topology_device *dev;
861
862 list_for_each_entry(dev, &topology_device_list, list)
863 kfd_remove_sysfs_node_entry(dev);
864}
865
866static int kfd_topology_update_sysfs(void)
867{
868 int ret;
869
4eacc26b 870 if (!sys_props.kobj_topology) {
5b5c4e40
EP
871 sys_props.kobj_topology =
872 kfd_alloc_struct(sys_props.kobj_topology);
873 if (!sys_props.kobj_topology)
874 return -ENOMEM;
875
876 ret = kobject_init_and_add(sys_props.kobj_topology,
877 &sysprops_type, &kfd_device->kobj,
878 "topology");
20eca012
QW
879 if (ret < 0) {
880 kobject_put(sys_props.kobj_topology);
5b5c4e40 881 return ret;
20eca012 882 }
5b5c4e40
EP
883
884 sys_props.kobj_nodes = kobject_create_and_add("nodes",
885 sys_props.kobj_topology);
886 if (!sys_props.kobj_nodes)
887 return -ENOMEM;
888
889 sys_props.attr_genid.name = "generation_id";
890 sys_props.attr_genid.mode = KFD_SYSFS_FILE_MODE;
891 sysfs_attr_init(&sys_props.attr_genid);
892 ret = sysfs_create_file(sys_props.kobj_topology,
893 &sys_props.attr_genid);
894 if (ret < 0)
895 return ret;
896
897 sys_props.attr_props.name = "system_properties";
898 sys_props.attr_props.mode = KFD_SYSFS_FILE_MODE;
899 sysfs_attr_init(&sys_props.attr_props);
900 ret = sysfs_create_file(sys_props.kobj_topology,
901 &sys_props.attr_props);
902 if (ret < 0)
903 return ret;
904 }
905
906 kfd_remove_sysfs_node_tree();
907
908 return kfd_build_sysfs_node_tree();
909}
910
911static void kfd_topology_release_sysfs(void)
912{
913 kfd_remove_sysfs_node_tree();
914 if (sys_props.kobj_topology) {
915 sysfs_remove_file(sys_props.kobj_topology,
916 &sys_props.attr_genid);
917 sysfs_remove_file(sys_props.kobj_topology,
918 &sys_props.attr_props);
919 if (sys_props.kobj_nodes) {
920 kobject_del(sys_props.kobj_nodes);
921 kobject_put(sys_props.kobj_nodes);
16b9201c 922 sys_props.kobj_nodes = NULL;
5b5c4e40
EP
923 }
924 kobject_del(sys_props.kobj_topology);
925 kobject_put(sys_props.kobj_topology);
16b9201c 926 sys_props.kobj_topology = NULL;
5b5c4e40
EP
927 }
928}
929
4f449311
HK
930/* Called with write topology_lock acquired */
931static void kfd_topology_update_device_list(struct list_head *temp_list,
932 struct list_head *master_list)
933{
934 while (!list_empty(temp_list)) {
935 list_move_tail(temp_list->next, master_list);
936 sys_props.num_devices++;
937 }
938}
939
520b8fb7
FK
940static void kfd_debug_print_topology(void)
941{
942 struct kfd_topology_device *dev;
943
944 down_read(&topology_lock);
945
946 dev = list_last_entry(&topology_device_list,
947 struct kfd_topology_device, list);
948 if (dev) {
949 if (dev->node_props.cpu_cores_count &&
950 dev->node_props.simd_count) {
951 pr_info("Topology: Add APU node [0x%0x:0x%0x]\n",
952 dev->node_props.device_id,
953 dev->node_props.vendor_id);
954 } else if (dev->node_props.cpu_cores_count)
955 pr_info("Topology: Add CPU node\n");
956 else if (dev->node_props.simd_count)
957 pr_info("Topology: Add dGPU node [0x%0x:0x%0x]\n",
958 dev->node_props.device_id,
959 dev->node_props.vendor_id);
960 }
961 up_read(&topology_lock);
962}
963
964/* Helper function for intializing platform_xx members of
965 * kfd_system_properties. Uses OEM info from the last CPU/APU node.
966 */
967static void kfd_update_system_properties(void)
968{
969 struct kfd_topology_device *dev;
970
971 down_read(&topology_lock);
972 dev = list_last_entry(&topology_device_list,
973 struct kfd_topology_device, list);
974 if (dev) {
975 sys_props.platform_id =
976 (*((uint64_t *)dev->oem_id)) & CRAT_OEMID_64BIT_MASK;
977 sys_props.platform_oem = *((uint64_t *)dev->oem_table_id);
978 sys_props.platform_rev = dev->oem_revision;
979 }
980 up_read(&topology_lock);
981}
982
983static void find_system_memory(const struct dmi_header *dm,
984 void *private)
985{
986 struct kfd_mem_properties *mem;
987 u16 mem_width, mem_clock;
988 struct kfd_topology_device *kdev =
989 (struct kfd_topology_device *)private;
990 const u8 *dmi_data = (const u8 *)(dm + 1);
991
992 if (dm->type == DMI_ENTRY_MEM_DEVICE && dm->length >= 0x15) {
993 mem_width = (u16)(*(const u16 *)(dmi_data + 0x6));
994 mem_clock = (u16)(*(const u16 *)(dmi_data + 0x11));
995 list_for_each_entry(mem, &kdev->mem_props, list) {
996 if (mem_width != 0xFFFF && mem_width != 0)
997 mem->width = mem_width;
998 if (mem_clock != 0)
999 mem->mem_clk_max = mem_clock;
1000 }
1001 }
1002}
f4757347
AL
1003
1004/*
1005 * Performance counters information is not part of CRAT but we would like to
1006 * put them in the sysfs under topology directory for Thunk to get the data.
1007 * This function is called before updating the sysfs.
1008 */
1009static int kfd_add_perf_to_topology(struct kfd_topology_device *kdev)
1010{
64d1c3a4
FK
1011 /* These are the only counters supported so far */
1012 return kfd_iommu_add_perf_counters(kdev);
f4757347
AL
1013}
1014
520b8fb7
FK
1015/* kfd_add_non_crat_information - Add information that is not currently
1016 * defined in CRAT but is necessary for KFD topology
1017 * @dev - topology device to which addition info is added
1018 */
1019static void kfd_add_non_crat_information(struct kfd_topology_device *kdev)
1020{
1021 /* Check if CPU only node. */
1022 if (!kdev->gpu) {
1023 /* Add system memory information */
1024 dmi_walk(find_system_memory, kdev);
1025 }
1026 /* TODO: For GPU node, rearrange code from kfd_topology_add_device */
1027}
1028
b441093e
HK
1029/* kfd_is_acpi_crat_invalid - CRAT from ACPI is valid only for AMD APU devices.
1030 * Ignore CRAT for all other devices. AMD APU is identified if both CPU
1031 * and GPU cores are present.
1032 * @device_list - topology device list created by parsing ACPI CRAT table.
1033 * @return - TRUE if invalid, FALSE is valid.
1034 */
1035static bool kfd_is_acpi_crat_invalid(struct list_head *device_list)
1036{
1037 struct kfd_topology_device *dev;
1038
1039 list_for_each_entry(dev, device_list, list) {
1040 if (dev->node_props.cpu_cores_count &&
1041 dev->node_props.simd_count)
1042 return false;
1043 }
1044 pr_info("Ignoring ACPI CRAT on non-APU system\n");
1045 return true;
1046}
1047
5b5c4e40
EP
1048int kfd_topology_init(void)
1049{
16b9201c 1050 void *crat_image = NULL;
5b5c4e40
EP
1051 size_t image_size = 0;
1052 int ret;
4f449311 1053 struct list_head temp_topology_device_list;
520b8fb7
FK
1054 int cpu_only_node = 0;
1055 struct kfd_topology_device *kdev;
1056 int proximity_domain;
5b5c4e40 1057
4f449311
HK
1058 /* topology_device_list - Master list of all topology devices
1059 * temp_topology_device_list - temporary list created while parsing CRAT
1060 * or VCRAT. Once parsing is complete the contents of list is moved to
1061 * topology_device_list
5b5c4e40 1062 */
4f449311
HK
1063
1064 /* Initialize the head for the both the lists */
5b5c4e40 1065 INIT_LIST_HEAD(&topology_device_list);
4f449311 1066 INIT_LIST_HEAD(&temp_topology_device_list);
5b5c4e40 1067 init_rwsem(&topology_lock);
5b5c4e40
EP
1068
1069 memset(&sys_props, 0, sizeof(sys_props));
1070
520b8fb7
FK
1071 /* Proximity domains in ACPI CRAT tables start counting at
1072 * 0. The same should be true for virtual CRAT tables created
1073 * at this stage. GPUs added later in kfd_topology_add_device
1074 * use a counter.
1075 */
1076 proximity_domain = 0;
1077
5b5c4e40 1078 /*
520b8fb7 1079 * Get the CRAT image from the ACPI. If ACPI doesn't have one
b441093e 1080 * or if ACPI CRAT is invalid create a virtual CRAT.
520b8fb7
FK
1081 * NOTE: The current implementation expects all AMD APUs to have
1082 * CRAT. If no CRAT is available, it is assumed to be a CPU
5b5c4e40 1083 */
8e05247d
HK
1084 ret = kfd_create_crat_image_acpi(&crat_image, &image_size);
1085 if (!ret) {
4f449311 1086 ret = kfd_parse_crat_table(crat_image,
520b8fb7
FK
1087 &temp_topology_device_list,
1088 proximity_domain);
b441093e
HK
1089 if (ret ||
1090 kfd_is_acpi_crat_invalid(&temp_topology_device_list)) {
520b8fb7
FK
1091 kfd_release_topology_device_list(
1092 &temp_topology_device_list);
1093 kfd_destroy_crat_image(crat_image);
1094 crat_image = NULL;
1095 }
1096 }
1097
1098 if (!crat_image) {
1099 ret = kfd_create_crat_image_virtual(&crat_image, &image_size,
1100 COMPUTE_UNIT_CPU, NULL,
1101 proximity_domain);
1102 cpu_only_node = 1;
1103 if (ret) {
1104 pr_err("Error creating VCRAT table for CPU\n");
1105 return ret;
1106 }
1107
1108 ret = kfd_parse_crat_table(crat_image,
1109 &temp_topology_device_list,
1110 proximity_domain);
1111 if (ret) {
1112 pr_err("Error parsing VCRAT table for CPU\n");
5b5c4e40 1113 goto err;
520b8fb7 1114 }
5b5c4e40
EP
1115 }
1116
f4757347
AL
1117 kdev = list_first_entry(&temp_topology_device_list,
1118 struct kfd_topology_device, list);
1119 kfd_add_perf_to_topology(kdev);
1120
8e05247d 1121 down_write(&topology_lock);
4f449311
HK
1122 kfd_topology_update_device_list(&temp_topology_device_list,
1123 &topology_device_list);
46d18d51 1124 topology_crat_proximity_domain = sys_props.num_devices-1;
8e05247d
HK
1125 ret = kfd_topology_update_sysfs();
1126 up_write(&topology_lock);
1127
4f449311
HK
1128 if (!ret) {
1129 sys_props.generation_count++;
520b8fb7
FK
1130 kfd_update_system_properties();
1131 kfd_debug_print_topology();
4f449311 1132 } else
8e05247d
HK
1133 pr_err("Failed to update topology in sysfs ret=%d\n", ret);
1134
520b8fb7
FK
1135 /* For nodes with GPU, this information gets added
1136 * when GPU is detected (kfd_topology_add_device).
1137 */
1138 if (cpu_only_node) {
1139 /* Add additional information to CPU only node created above */
1140 down_write(&topology_lock);
1141 kdev = list_first_entry(&topology_device_list,
1142 struct kfd_topology_device, list);
1143 up_write(&topology_lock);
1144 kfd_add_non_crat_information(kdev);
1145 }
1146
5b5c4e40 1147err:
8e05247d 1148 kfd_destroy_crat_image(crat_image);
5b5c4e40
EP
1149 return ret;
1150}
1151
1152void kfd_topology_shutdown(void)
1153{
4f449311 1154 down_write(&topology_lock);
5b5c4e40
EP
1155 kfd_topology_release_sysfs();
1156 kfd_release_live_view();
4f449311 1157 up_write(&topology_lock);
5b5c4e40
EP
1158}
1159
8dc1db31 1160static uint32_t kfd_generate_gpu_id(struct kfd_node *gpu)
5b5c4e40
EP
1161{
1162 uint32_t hashout;
1163 uint32_t buf[7];
585f0e6c 1164 uint64_t local_mem_size;
5b5c4e40
EP
1165 int i;
1166
1167 if (!gpu)
1168 return 0;
1169
8dc1db31
MJ
1170 local_mem_size = gpu->kfd->local_mem_info.local_mem_size_private +
1171 gpu->kfd->local_mem_info.local_mem_size_public;
d69a3b76
MJ
1172 buf[0] = gpu->adev->pdev->devfn;
1173 buf[1] = gpu->adev->pdev->subsystem_vendor |
1174 (gpu->adev->pdev->subsystem_device << 16);
1175 buf[2] = pci_domain_nr(gpu->adev->pdev->bus);
1176 buf[3] = gpu->adev->pdev->device;
1177 buf[4] = gpu->adev->pdev->bus->number;
585f0e6c
EC
1178 buf[5] = lower_32_bits(local_mem_size);
1179 buf[6] = upper_32_bits(local_mem_size);
5b5c4e40
EP
1180
1181 for (i = 0, hashout = 0; i < 7; i++)
1182 hashout ^= hash_32(buf[i], KFD_GPU_ID_HASH_WIDTH);
1183
1184 return hashout;
1185}
3a87177e
HK
1186/* kfd_assign_gpu - Attach @gpu to the correct kfd topology device. If
1187 * the GPU device is not already present in the topology device
1188 * list then return NULL. This means a new topology device has to
1189 * be created for this GPU.
3a87177e 1190 */
8dc1db31 1191static struct kfd_topology_device *kfd_assign_gpu(struct kfd_node *gpu)
5b5c4e40
EP
1192{
1193 struct kfd_topology_device *dev;
16b9201c 1194 struct kfd_topology_device *out_dev = NULL;
171bc67e
HK
1195 struct kfd_mem_properties *mem;
1196 struct kfd_cache_properties *cache;
1197 struct kfd_iolink_properties *iolink;
0f28cca8 1198 struct kfd_iolink_properties *p2plink;
5b5c4e40 1199
b8fe0524
FK
1200 list_for_each_entry(dev, &topology_device_list, list) {
1201 /* Discrete GPUs need their own topology device list
1202 * entries. Don't assign them to CPU/APU nodes.
1203 */
8dc1db31 1204 if (!gpu->kfd->use_iommu_v2 &&
b8fe0524
FK
1205 dev->node_props.cpu_cores_count)
1206 continue;
1207
4eacc26b 1208 if (!dev->gpu && (dev->node_props.simd_count > 0)) {
5b5c4e40
EP
1209 dev->gpu = gpu;
1210 out_dev = dev;
171bc67e
HK
1211
1212 list_for_each_entry(mem, &dev->mem_props, list)
1213 mem->gpu = dev->gpu;
1214 list_for_each_entry(cache, &dev->cache_props, list)
1215 cache->gpu = dev->gpu;
1216 list_for_each_entry(iolink, &dev->io_link_props, list)
1217 iolink->gpu = dev->gpu;
0f28cca8
RE
1218 list_for_each_entry(p2plink, &dev->p2p_link_props, list)
1219 p2plink->gpu = dev->gpu;
5b5c4e40
EP
1220 break;
1221 }
b8fe0524 1222 }
5b5c4e40
EP
1223 return out_dev;
1224}
1225
1226static void kfd_notify_gpu_change(uint32_t gpu_id, int arrival)
1227{
1228 /*
1229 * TODO: Generate an event for thunk about the arrival/removal
1230 * of the GPU
1231 */
1232}
1233
3a87177e
HK
1234/* kfd_fill_mem_clk_max_info - Since CRAT doesn't have memory clock info,
1235 * patch this after CRAT parsing.
1236 */
1237static void kfd_fill_mem_clk_max_info(struct kfd_topology_device *dev)
1238{
1239 struct kfd_mem_properties *mem;
1240 struct kfd_local_mem_info local_mem_info;
1241
1242 if (!dev)
1243 return;
1244
1245 /* Currently, amdgpu driver (amdgpu_mc) deals only with GPUs with
1246 * single bank of VRAM local memory.
1247 * for dGPUs - VCRAT reports only one bank of Local Memory
1248 * for APUs - If CRAT from ACPI reports more than one bank, then
1249 * all the banks will report the same mem_clk_max information
1250 */
574c4183 1251 amdgpu_amdkfd_get_local_mem_info(dev->gpu->adev, &local_mem_info);
3a87177e
HK
1252
1253 list_for_each_entry(mem, &dev->mem_props, list)
1254 mem->mem_clk_max = local_mem_info.mem_clk_max;
1255}
1256
bdd24657
JK
1257static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev,
1258 struct kfd_topology_device *target_gpu_dev,
1259 struct kfd_iolink_properties *link)
3a87177e 1260{
bdd24657
JK
1261 /* xgmi always supports atomics between links. */
1262 if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI)
3a87177e
HK
1263 return;
1264
bdd24657
JK
1265 /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */
1266 if (target_gpu_dev) {
1267 uint32_t cap;
1268
d69a3b76 1269 pcie_capability_read_dword(target_gpu_dev->gpu->adev->pdev,
deb68983 1270 PCI_EXP_DEVCAP2, &cap);
d35f00d8 1271
deb68983
JK
1272 if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
1273 PCI_EXP_DEVCAP2_ATOMIC_COMP64)))
bdd24657 1274 link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
deb68983 1275 CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
bdd24657
JK
1276 /* set gpu (dev) flags. */
1277 } else {
8dc1db31 1278 if (!dev->gpu->kfd->pci_atomic_requested ||
7eb0502a 1279 dev->gpu->adev->asic_type == CHIP_HAWAII)
bdd24657 1280 link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
deb68983
JK
1281 CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
1282 }
bdd24657
JK
1283}
1284
c9cfbf7f
EH
1285static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,
1286 struct kfd_iolink_properties *outbound_link,
1287 struct kfd_iolink_properties *inbound_link)
1288{
1289 /* CPU -> GPU with PCIe */
1290 if (!to_dev->gpu &&
1291 inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
1292 inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1293
1294 if (to_dev->gpu) {
1295 /* GPU <-> GPU with PCIe and
1296 * Vega20 with XGMI
1297 */
1298 if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS ||
1299 (inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
046e674b 1300 KFD_GC_VERSION(to_dev->gpu) == IP_VERSION(9, 4, 0))) {
c9cfbf7f
EH
1301 outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1302 inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1303 }
1304 }
1305}
1306
bdd24657
JK
1307static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
1308{
1309 struct kfd_iolink_properties *link, *inbound_link;
1310 struct kfd_topology_device *peer_dev;
1311
1312 if (!dev || !dev->gpu)
1313 return;
d35f00d8
EH
1314
1315 /* GPU only creates direct links so apply flags setting to all */
1316 list_for_each_entry(link, &dev->io_link_props, list) {
bdd24657
JK
1317 link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1318 kfd_set_iolink_no_atomics(dev, NULL, link);
1319 peer_dev = kfd_topology_device_by_proximity_domain(
d35f00d8 1320 link->node_to);
bdd24657
JK
1321
1322 if (!peer_dev)
1323 continue;
1324
a0af5dbd
JK
1325 /* Include the CPU peer in GPU hive if connected over xGMI. */
1326 if (!peer_dev->gpu && !peer_dev->node_props.hive_id &&
1327 dev->node_props.hive_id &&
1328 dev->gpu->adev->gmc.xgmi.connected_to_cpu)
1329 peer_dev->node_props.hive_id = dev->node_props.hive_id;
1330
bdd24657
JK
1331 list_for_each_entry(inbound_link, &peer_dev->io_link_props,
1332 list) {
1333 if (inbound_link->node_to != link->node_from)
1334 continue;
1335
1336 inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1337 kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
c9cfbf7f 1338 kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
d35f00d8
EH
1339 }
1340 }
0f28cca8
RE
1341
1342 /* Create indirect links so apply flags setting to all */
1343 list_for_each_entry(link, &dev->p2p_link_props, list) {
1344 link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1345 kfd_set_iolink_no_atomics(dev, NULL, link);
1346 peer_dev = kfd_topology_device_by_proximity_domain(
1347 link->node_to);
1348
1349 if (!peer_dev)
1350 continue;
1351
1352 list_for_each_entry(inbound_link, &peer_dev->p2p_link_props,
1353 list) {
1354 if (inbound_link->node_to != link->node_from)
1355 continue;
1356
1357 inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1358 kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
1359 kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
1360 }
1361 }
1362}
1363
1364static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev,
1365 struct kfd_iolink_properties *p2plink)
1366{
1367 int ret;
1368
1369 p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
1370 if (!p2plink->kobj)
1371 return -ENOMEM;
1372
1373 ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
1374 dev->kobj_p2plink, "%d", dev->node_props.p2p_links_count - 1);
1375 if (ret < 0) {
1376 kobject_put(p2plink->kobj);
1377 return ret;
1378 }
1379
1380 p2plink->attr.name = "properties";
1381 p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
1382 sysfs_attr_init(&p2plink->attr);
1383 ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
1384 if (ret < 0)
1385 return ret;
1386
1387 return 0;
1388}
1389
1390static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int gpu_node)
1391{
7d50b92d 1392 struct kfd_iolink_properties *gpu_link, *tmp_link, *cpu_link;
0f28cca8 1393 struct kfd_iolink_properties *props = NULL, *props2 = NULL;
0f28cca8
RE
1394 struct kfd_topology_device *cpu_dev;
1395 int ret = 0;
1396 int i, num_cpu;
1397
1398 num_cpu = 0;
1399 list_for_each_entry(cpu_dev, &topology_device_list, list) {
1400 if (cpu_dev->gpu)
1401 break;
1402 num_cpu++;
1403 }
1404
1405 gpu_link = list_first_entry(&kdev->io_link_props,
1406 struct kfd_iolink_properties, list);
1407 if (!gpu_link)
1408 return -ENOMEM;
1409
1410 for (i = 0; i < num_cpu; i++) {
1411 /* CPU <--> GPU */
1412 if (gpu_link->node_to == i)
1413 continue;
1414
1415 /* find CPU <--> CPU links */
7d50b92d 1416 cpu_link = NULL;
0f28cca8
RE
1417 cpu_dev = kfd_topology_device_by_proximity_domain(i);
1418 if (cpu_dev) {
7d50b92d 1419 list_for_each_entry(tmp_link,
0f28cca8 1420 &cpu_dev->io_link_props, list) {
7d50b92d
DC
1421 if (tmp_link->node_to == gpu_link->node_to) {
1422 cpu_link = tmp_link;
0f28cca8 1423 break;
7d50b92d 1424 }
0f28cca8
RE
1425 }
1426 }
1427
7d50b92d 1428 if (!cpu_link)
0f28cca8
RE
1429 return -ENOMEM;
1430
1431 /* CPU <--> CPU <--> GPU, GPU node*/
1432 props = kfd_alloc_struct(props);
1433 if (!props)
1434 return -ENOMEM;
1435
1436 memcpy(props, gpu_link, sizeof(struct kfd_iolink_properties));
1437 props->weight = gpu_link->weight + cpu_link->weight;
1438 props->min_latency = gpu_link->min_latency + cpu_link->min_latency;
1439 props->max_latency = gpu_link->max_latency + cpu_link->max_latency;
1440 props->min_bandwidth = min(gpu_link->min_bandwidth, cpu_link->min_bandwidth);
1441 props->max_bandwidth = min(gpu_link->max_bandwidth, cpu_link->max_bandwidth);
1442
1443 props->node_from = gpu_node;
1444 props->node_to = i;
1445 kdev->node_props.p2p_links_count++;
1446 list_add_tail(&props->list, &kdev->p2p_link_props);
1447 ret = kfd_build_p2p_node_entry(kdev, props);
1448 if (ret < 0)
1449 return ret;
1450
1451 /* for small Bar, no CPU --> GPU in-direct links */
1452 if (kfd_dev_is_large_bar(kdev->gpu)) {
1453 /* CPU <--> CPU <--> GPU, CPU node*/
1454 props2 = kfd_alloc_struct(props2);
1455 if (!props2)
1456 return -ENOMEM;
1457
1458 memcpy(props2, props, sizeof(struct kfd_iolink_properties));
1459 props2->node_from = i;
1460 props2->node_to = gpu_node;
1461 props2->kobj = NULL;
1462 cpu_dev->node_props.p2p_links_count++;
1463 list_add_tail(&props2->list, &cpu_dev->p2p_link_props);
1464 ret = kfd_build_p2p_node_entry(cpu_dev, props2);
1465 if (ret < 0)
1466 return ret;
1467 }
1468 }
1469 return ret;
1470}
1471
1472#if defined(CONFIG_HSA_AMD_P2P)
1473static int kfd_add_peer_prop(struct kfd_topology_device *kdev,
1474 struct kfd_topology_device *peer, int from, int to)
1475{
1476 struct kfd_iolink_properties *props = NULL;
1477 struct kfd_iolink_properties *iolink1, *iolink2, *iolink3;
1478 struct kfd_topology_device *cpu_dev;
1479 int ret = 0;
1480
1481 if (!amdgpu_device_is_peer_accessible(
1482 kdev->gpu->adev,
1483 peer->gpu->adev))
1484 return ret;
1485
1486 iolink1 = list_first_entry(&kdev->io_link_props,
1487 struct kfd_iolink_properties, list);
1488 if (!iolink1)
1489 return -ENOMEM;
1490
1491 iolink2 = list_first_entry(&peer->io_link_props,
1492 struct kfd_iolink_properties, list);
1493 if (!iolink2)
1494 return -ENOMEM;
1495
1496 props = kfd_alloc_struct(props);
1497 if (!props)
1498 return -ENOMEM;
1499
1500 memcpy(props, iolink1, sizeof(struct kfd_iolink_properties));
1501
1502 props->weight = iolink1->weight + iolink2->weight;
1503 props->min_latency = iolink1->min_latency + iolink2->min_latency;
1504 props->max_latency = iolink1->max_latency + iolink2->max_latency;
1505 props->min_bandwidth = min(iolink1->min_bandwidth, iolink2->min_bandwidth);
1506 props->max_bandwidth = min(iolink2->max_bandwidth, iolink2->max_bandwidth);
1507
1508 if (iolink1->node_to != iolink2->node_to) {
1509 /* CPU->CPU link*/
1510 cpu_dev = kfd_topology_device_by_proximity_domain(iolink1->node_to);
1511 if (cpu_dev) {
1512 list_for_each_entry(iolink3, &cpu_dev->io_link_props, list)
1513 if (iolink3->node_to == iolink2->node_to)
1514 break;
1515
1516 props->weight += iolink3->weight;
1517 props->min_latency += iolink3->min_latency;
1518 props->max_latency += iolink3->max_latency;
1519 props->min_bandwidth = min(props->min_bandwidth,
1520 iolink3->min_bandwidth);
1521 props->max_bandwidth = min(props->max_bandwidth,
1522 iolink3->max_bandwidth);
1523 } else {
1524 WARN(1, "CPU node not found");
1525 }
1526 }
1527
1528 props->node_from = from;
1529 props->node_to = to;
1530 peer->node_props.p2p_links_count++;
1531 list_add_tail(&props->list, &peer->p2p_link_props);
1532 ret = kfd_build_p2p_node_entry(peer, props);
1533
1534 return ret;
1535}
1536#endif
1537
1538static int kfd_dev_create_p2p_links(void)
1539{
1540 struct kfd_topology_device *dev;
1541 struct kfd_topology_device *new_dev;
914da384
AD
1542#if defined(CONFIG_HSA_AMD_P2P)
1543 uint32_t i;
1544#endif
1545 uint32_t k;
0f28cca8
RE
1546 int ret = 0;
1547
1548 k = 0;
1549 list_for_each_entry(dev, &topology_device_list, list)
1550 k++;
1551 if (k < 2)
1552 return 0;
1553
1554 new_dev = list_last_entry(&topology_device_list, struct kfd_topology_device, list);
1555 if (WARN_ON(!new_dev->gpu))
1556 return 0;
1557
1558 k--;
0f28cca8
RE
1559
1560 /* create in-direct links */
1561 ret = kfd_create_indirect_link_prop(new_dev, k);
1562 if (ret < 0)
1563 goto out;
1564
1565 /* create p2p links */
1566#if defined(CONFIG_HSA_AMD_P2P)
914da384 1567 i = 0;
0f28cca8
RE
1568 list_for_each_entry(dev, &topology_device_list, list) {
1569 if (dev == new_dev)
1570 break;
1571 if (!dev->gpu || !dev->gpu->adev ||
8dc1db31
MJ
1572 (dev->gpu->kfd->hive_id &&
1573 dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id))
0f28cca8
RE
1574 goto next;
1575
1576 /* check if node(s) is/are peer accessible in one direction or bi-direction */
1577 ret = kfd_add_peer_prop(new_dev, dev, i, k);
1578 if (ret < 0)
1579 goto out;
1580
1581 ret = kfd_add_peer_prop(dev, new_dev, k, i);
1582 if (ret < 0)
1583 goto out;
1584next:
1585 i++;
1586 }
1587#endif
1588
1589out:
1590 return ret;
3a87177e
HK
1591}
1592
c0cc999f
MJ
1593/* Helper function. See kfd_fill_gpu_cache_info for parameter description */
1594static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext,
1595 struct kfd_gpu_cache_info *pcache_info,
1596 struct kfd_cu_info *cu_info,
1597 int cu_bitmask,
1598 int cache_type, unsigned int cu_processor_id,
1599 int cu_block)
1600{
1601 unsigned int cu_sibling_map_mask;
1602 int first_active_cu;
1603 struct kfd_cache_properties *pcache = NULL;
1604
1605 cu_sibling_map_mask = cu_bitmask;
1606 cu_sibling_map_mask >>= cu_block;
1607 cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1608 first_active_cu = ffs(cu_sibling_map_mask);
1609
1610 /* CU could be inactive. In case of shared cache find the first active
1611 * CU. and incase of non-shared cache check if the CU is inactive. If
1612 * inactive active skip it
1613 */
1614 if (first_active_cu) {
1615 pcache = kfd_alloc_struct(pcache);
1616 if (!pcache)
1617 return -ENOMEM;
1618
1619 memset(pcache, 0, sizeof(struct kfd_cache_properties));
1620 pcache->processor_id_low = cu_processor_id + (first_active_cu - 1);
1621 pcache->cache_level = pcache_info[cache_type].cache_level;
1622 pcache->cache_size = pcache_info[cache_type].cache_size;
1623
1624 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1625 pcache->cache_type |= HSA_CACHE_TYPE_DATA;
1626 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_INST_CACHE)
1627 pcache->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1628 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1629 pcache->cache_type |= HSA_CACHE_TYPE_CPU;
1630 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1631 pcache->cache_type |= HSA_CACHE_TYPE_HSACU;
1632
1633 /* Sibling map is w.r.t processor_id_low, so shift out
1634 * inactive CU
1635 */
1636 cu_sibling_map_mask =
1637 cu_sibling_map_mask >> (first_active_cu - 1);
1638
1639 pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1640 pcache->sibling_map[1] =
1641 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1642 pcache->sibling_map[2] =
1643 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1644 pcache->sibling_map[3] =
1645 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1646
1647 pcache->sibling_map_size = 4;
1648 *props_ext = pcache;
1649
1650 return 0;
1651 }
1652 return 1;
1653}
1654
1655/* Helper function. See kfd_fill_gpu_cache_info for parameter description */
1656static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext,
1657 struct kfd_gpu_cache_info *pcache_info,
1658 struct kfd_cu_info *cu_info,
1659 int cache_type, unsigned int cu_processor_id)
1660{
1661 unsigned int cu_sibling_map_mask;
1662 int first_active_cu;
1663 int i, j, k;
1664 struct kfd_cache_properties *pcache = NULL;
1665
1666 cu_sibling_map_mask = cu_info->cu_bitmap[0][0];
1667 cu_sibling_map_mask &=
1668 ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1669 first_active_cu = ffs(cu_sibling_map_mask);
1670
1671 /* CU could be inactive. In case of shared cache find the first active
1672 * CU. and incase of non-shared cache check if the CU is inactive. If
1673 * inactive active skip it
1674 */
1675 if (first_active_cu) {
1676 pcache = kfd_alloc_struct(pcache);
1677 if (!pcache)
1678 return -ENOMEM;
1679
1680 memset(pcache, 0, sizeof(struct kfd_cache_properties));
1681 pcache->processor_id_low = cu_processor_id
1682 + (first_active_cu - 1);
1683 pcache->cache_level = pcache_info[cache_type].cache_level;
1684 pcache->cache_size = pcache_info[cache_type].cache_size;
1685
1686 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1687 pcache->cache_type |= HSA_CACHE_TYPE_DATA;
1688 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_INST_CACHE)
1689 pcache->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1690 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1691 pcache->cache_type |= HSA_CACHE_TYPE_CPU;
1692 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1693 pcache->cache_type |= HSA_CACHE_TYPE_HSACU;
1694
1695 /* Sibling map is w.r.t processor_id_low, so shift out
1696 * inactive CU
1697 */
1698 cu_sibling_map_mask = cu_sibling_map_mask >> (first_active_cu - 1);
1699 k = 0;
1700
1701 for (i = 0; i < cu_info->num_shader_engines; i++) {
1702 for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) {
1703 pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1704 pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1705 pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1706 pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1707 k += 4;
1708
1709 cu_sibling_map_mask = cu_info->cu_bitmap[i % 4][j + i / 4];
1710 cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1711 }
1712 }
1713 pcache->sibling_map_size = k;
1714 *props_ext = pcache;
1715 return 0;
1716 }
1717 return 1;
1718}
1719
1720#define KFD_MAX_CACHE_TYPES 6
1721
1722/* kfd_fill_cache_non_crat_info - Fill GPU cache info using kfd_gpu_cache_info
1723 * tables
1724 */
8dc1db31 1725static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct kfd_node *kdev)
c0cc999f
MJ
1726{
1727 struct kfd_gpu_cache_info *pcache_info = NULL;
1728 int i, j, k;
1729 int ct = 0;
1730 unsigned int cu_processor_id;
1731 int ret;
1732 unsigned int num_cu_shared;
1733 struct kfd_cu_info cu_info;
1734 struct kfd_cu_info *pcu_info;
1735 int gpu_processor_id;
1736 struct kfd_cache_properties *props_ext;
1737 int num_of_entries = 0;
1738 int num_of_cache_types = 0;
1739 struct kfd_gpu_cache_info cache_info[KFD_MAX_CACHE_TYPES];
1740
1741 amdgpu_amdkfd_get_cu_info(kdev->adev, &cu_info);
1742 pcu_info = &cu_info;
1743
1744 gpu_processor_id = dev->node_props.simd_id_base;
1745
1746 pcache_info = cache_info;
1747 num_of_cache_types = kfd_get_gpu_cache_info(kdev, &pcache_info);
1748 if (!num_of_cache_types) {
1749 pr_warn("no cache info found\n");
1750 return;
1751 }
1752
1753 /* For each type of cache listed in the kfd_gpu_cache_info table,
1754 * go through all available Compute Units.
1755 * The [i,j,k] loop will
1756 * if kfd_gpu_cache_info.num_cu_shared = 1
1757 * will parse through all available CU
1758 * If (kfd_gpu_cache_info.num_cu_shared != 1)
1759 * then it will consider only one CU from
1760 * the shared unit
1761 */
1762 for (ct = 0; ct < num_of_cache_types; ct++) {
1763 cu_processor_id = gpu_processor_id;
1764 if (pcache_info[ct].cache_level == 1) {
1765 for (i = 0; i < pcu_info->num_shader_engines; i++) {
1766 for (j = 0; j < pcu_info->num_shader_arrays_per_engine; j++) {
1767 for (k = 0; k < pcu_info->num_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
1768
1769 ret = fill_in_l1_pcache(&props_ext, pcache_info, pcu_info,
1770 pcu_info->cu_bitmap[i % 4][j + i / 4], ct,
1771 cu_processor_id, k);
1772
1773 if (ret < 0)
1774 break;
1775
1776 if (!ret) {
1777 num_of_entries++;
1778 list_add_tail(&props_ext->list, &dev->cache_props);
1779 }
1780
1781 /* Move to next CU block */
1782 num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
1783 pcu_info->num_cu_per_sh) ?
1784 pcache_info[ct].num_cu_shared :
1785 (pcu_info->num_cu_per_sh - k);
1786 cu_processor_id += num_cu_shared;
1787 }
1788 }
1789 }
1790 } else {
1791 ret = fill_in_l2_l3_pcache(&props_ext, pcache_info,
1792 pcu_info, ct, cu_processor_id);
1793
1794 if (ret < 0)
1795 break;
1796
1797 if (!ret) {
1798 num_of_entries++;
1799 list_add_tail(&props_ext->list, &dev->cache_props);
1800 }
1801 }
1802 }
1803 dev->node_props.caches_count += num_of_entries;
1804 pr_debug("Added [%d] GPU cache entries\n", num_of_entries);
1805}
1806
8dc1db31 1807static int kfd_topology_add_device_locked(struct kfd_node *gpu, uint32_t gpu_id,
f701acb6
FK
1808 struct kfd_topology_device **dev)
1809{
1810 int proximity_domain = ++topology_crat_proximity_domain;
1811 struct list_head temp_topology_device_list;
1812 void *crat_image = NULL;
1813 size_t image_size = 0;
1814 int res;
1815
1816 res = kfd_create_crat_image_virtual(&crat_image, &image_size,
1817 COMPUTE_UNIT_GPU, gpu,
1818 proximity_domain);
1819 if (res) {
1820 pr_err("Error creating VCRAT for GPU (ID: 0x%x)\n",
1821 gpu_id);
1822 topology_crat_proximity_domain--;
1823 goto err;
1824 }
1825
1826 INIT_LIST_HEAD(&temp_topology_device_list);
1827
1828 res = kfd_parse_crat_table(crat_image,
1829 &temp_topology_device_list,
1830 proximity_domain);
1831 if (res) {
1832 pr_err("Error parsing VCRAT for GPU (ID: 0x%x)\n",
1833 gpu_id);
1834 topology_crat_proximity_domain--;
1835 goto err;
1836 }
1837
1838 kfd_topology_update_device_list(&temp_topology_device_list,
1839 &topology_device_list);
1840
1841 *dev = kfd_assign_gpu(gpu);
1842 if (WARN_ON(!*dev)) {
1843 res = -ENODEV;
1844 goto err;
1845 }
1846
1847 /* Fill the cache affinity information here for the GPUs
1848 * using VCRAT
1849 */
1850 kfd_fill_cache_non_crat_info(*dev, gpu);
1851
1852 /* Update the SYSFS tree, since we added another topology
1853 * device
1854 */
1855 res = kfd_topology_update_sysfs();
1856 if (!res)
1857 sys_props.generation_count++;
1858 else
1859 pr_err("Failed to update GPU (ID: 0x%x) to sysfs topology. res=%d\n",
1860 gpu_id, res);
1861
1862err:
1863 kfd_destroy_crat_image(crat_image);
1864 return res;
1865}
1866
8dc1db31 1867int kfd_topology_add_device(struct kfd_node *gpu)
5b5c4e40
EP
1868{
1869 uint32_t gpu_id;
1870 struct kfd_topology_device *dev;
f7ce2fad 1871 struct kfd_cu_info cu_info;
4f449311 1872 int res = 0;
b7675b7b
GS
1873 int i;
1874 const char *asic_name = amdgpu_asic_name[gpu->adev->asic_type];
4f449311 1875
5b5c4e40 1876 gpu_id = kfd_generate_gpu_id(gpu);
79775b62 1877 pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id);
5b5c4e40 1878
3a87177e
HK
1879 /* Check to see if this gpu device exists in the topology_device_list.
1880 * If so, assign the gpu to that device,
1881 * else create a Virtual CRAT for this gpu device and then parse that
1882 * CRAT to create a new topology device. Once created assign the gpu to
1883 * that topology device
5b5c4e40 1884 */
c0cc999f 1885 down_write(&topology_lock);
5b5c4e40 1886 dev = kfd_assign_gpu(gpu);
f701acb6
FK
1887 if (!dev)
1888 res = kfd_topology_add_device_locked(gpu, gpu_id, &dev);
c0cc999f 1889 up_write(&topology_lock);
f701acb6
FK
1890 if (res)
1891 return res;
5b5c4e40
EP
1892
1893 dev->gpu_id = gpu_id;
1894 gpu->id = gpu_id;
3a87177e 1895
0f28cca8
RE
1896 kfd_dev_create_p2p_links();
1897
3a87177e
HK
1898 /* TODO: Move the following lines to function
1899 * kfd_add_non_crat_information
1900 */
1901
1902 /* Fill-in additional information that is not available in CRAT but
1903 * needed for the topology
1904 */
1905
574c4183 1906 amdgpu_amdkfd_get_cu_info(dev->gpu->adev, &cu_info);
c181159a 1907
b7675b7b
GS
1908 for (i = 0; i < KFD_TOPOLOGY_PUBLIC_NAME_SIZE-1; i++) {
1909 dev->node_props.name[i] = __tolower(asic_name[i]);
1910 if (asic_name[i] == '\0')
1911 break;
1912 }
1913 dev->node_props.name[i] = '\0';
c181159a 1914
3a87177e
HK
1915 dev->node_props.simd_arrays_per_engine =
1916 cu_info.num_shader_arrays_per_engine;
1917
8dc1db31
MJ
1918 dev->node_props.gfx_target_version =
1919 gpu->kfd->device_info.gfx_target_version;
d69a3b76
MJ
1920 dev->node_props.vendor_id = gpu->adev->pdev->vendor;
1921 dev->node_props.device_id = gpu->adev->pdev->device;
c6d1ec41 1922 dev->node_props.capability |=
02274fc0 1923 ((dev->gpu->adev->rev_id << HSA_CAP_ASIC_REVISION_SHIFT) &
c6d1ec41 1924 HSA_CAP_ASIC_REVISION_MASK);
d69a3b76
MJ
1925 dev->node_props.location_id = pci_dev_id(gpu->adev->pdev);
1926 dev->node_props.domain = pci_domain_nr(gpu->adev->pdev->bus);
3a87177e 1927 dev->node_props.max_engine_clk_fcompute =
574c4183 1928 amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->adev);
3a87177e
HK
1929 dev->node_props.max_engine_clk_ccompute =
1930 cpufreq_quick_get_max(0) / 1000;
7c9b7171 1931 dev->node_props.drm_render_minor =
8dc1db31 1932 gpu->kfd->shared_resources.drm_render_minor;
3a87177e 1933
8dc1db31 1934 dev->node_props.hive_id = gpu->kfd->hive_id;
ee2f17f4 1935 dev->node_props.num_sdma_engines = kfd_get_num_sdma_engines(gpu);
14568cf6 1936 dev->node_props.num_sdma_xgmi_engines =
ee2f17f4 1937 kfd_get_num_xgmi_sdma_engines(gpu);
bb71c74d 1938 dev->node_props.num_sdma_queues_per_engine =
8dc1db31
MJ
1939 gpu->kfd->device_info.num_sdma_queues_per_engine -
1940 gpu->kfd->device_info.num_reserved_sdma_queues_per_engine;
29633d0e 1941 dev->node_props.num_gws = (dev->gpu->gws &&
29e76462 1942 dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
02274fc0 1943 dev->gpu->adev->gds.gws_size : 0;
e6945304 1944 dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);
0c1690e3 1945
3a87177e
HK
1946 kfd_fill_mem_clk_max_info(dev);
1947 kfd_fill_iolink_non_crat_info(dev);
1948
7eb0502a 1949 switch (dev->gpu->adev->asic_type) {
3a87177e
HK
1950 case CHIP_KAVERI:
1951 case CHIP_HAWAII:
1952 case CHIP_TONGA:
1953 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 <<
1954 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
1955 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
1956 break;
1957 case CHIP_CARRIZO:
1958 case CHIP_FIJI:
1959 case CHIP_POLARIS10:
1960 case CHIP_POLARIS11:
846a44d7 1961 case CHIP_POLARIS12:
ed81cd6e 1962 case CHIP_VEGAM:
42aa8793 1963 pr_debug("Adding doorbell packet type capability\n");
3a87177e
HK
1964 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 <<
1965 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
1966 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
1967 break;
1968 default:
e4804a39
GS
1969 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(9, 0, 1))
1970 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
1971 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
1972 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
1973 else
1974 WARN(1, "Unexpected ASIC family %u",
7eb0502a 1975 dev->gpu->adev->asic_type);
7639a8c4
BG
1976 }
1977
1ae99eab 1978 /*
2243f493
RB
1979 * Overwrite ATS capability according to needs_iommu_device to fix
1980 * potential missing corresponding bit in CRAT of BIOS.
1981 */
8dc1db31 1982 if (dev->gpu->kfd->use_iommu_v2)
1ae99eab
OZ
1983 dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
1984 else
1985 dev->node_props.capability &= ~HSA_CAP_ATS_PRESENT;
1986
3a87177e
HK
1987 /* Fix errors in CZ CRAT.
1988 * simd_count: Carrizo CRAT reports wrong simd_count, probably
1989 * because it doesn't consider masked out CUs
70f372bf 1990 * max_waves_per_simd: Carrizo reports wrong max_waves_per_simd
3a87177e 1991 */
7eb0502a 1992 if (dev->gpu->adev->asic_type == CHIP_CARRIZO) {
3a87177e
HK
1993 dev->node_props.simd_count =
1994 cu_info.simd_per_cu * cu_info.cu_active_number;
70f372bf 1995 dev->node_props.max_waves_per_simd = 10;
70f372bf 1996 }
3a87177e 1997
5436ab94
SY
1998 /* kfd only concerns sram ecc on GFX and HBM ecc on UMC */
1999 dev->node_props.capability |=
56c5977e 2000 ((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
5436ab94 2001 HSA_CAP_SRAM_EDCSUPPORTED : 0;
56c5977e
GS
2002 dev->node_props.capability |=
2003 ((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
5436ab94
SY
2004 HSA_CAP_MEM_EDCSUPPORTED : 0;
2005
046e674b 2006 if (KFD_GC_VERSION(dev->gpu) != IP_VERSION(9, 0, 1))
56c5977e 2007 dev->node_props.capability |= (dev->gpu->adev->ras_enabled != 0) ?
0dee45a2 2008 HSA_CAP_RASEVENTNOTIFY : 0;
0dee45a2 2009
56c5977e 2010 if (KFD_IS_SVM_API_SUPPORTED(dev->gpu->adev->kfd.dev))
4c166eb9
PY
2011 dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED;
2012
3a87177e
HK
2013 kfd_debug_print_topology();
2014
7d4f8db4 2015 kfd_notify_gpu_change(gpu_id, 1);
f701acb6 2016
7d4f8db4 2017 return 0;
5b5c4e40
EP
2018}
2019
46d18d51
MJ
2020/**
2021 * kfd_topology_update_io_links() - Update IO links after device removal.
2022 * @proximity_domain: Proximity domain value of the dev being removed.
2023 *
2024 * The topology list currently is arranged in increasing order of
2025 * proximity domain.
2026 *
2027 * Two things need to be done when a device is removed:
2028 * 1. All the IO links to this device need to be removed.
2029 * 2. All nodes after the current device node need to move
2030 * up once this device node is removed from the topology
2031 * list. As a result, the proximity domain values for
2032 * all nodes after the node being deleted reduce by 1.
2033 * This would also cause the proximity domain values for
2034 * io links to be updated based on new proximity domain
2035 * values.
2036 *
2037 * Context: The caller must hold write topology_lock.
2038 */
2039static void kfd_topology_update_io_links(int proximity_domain)
2040{
2041 struct kfd_topology_device *dev;
0f28cca8 2042 struct kfd_iolink_properties *iolink, *p2plink, *tmp;
46d18d51
MJ
2043
2044 list_for_each_entry(dev, &topology_device_list, list) {
2045 if (dev->proximity_domain > proximity_domain)
2046 dev->proximity_domain--;
2047
2048 list_for_each_entry_safe(iolink, tmp, &dev->io_link_props, list) {
2049 /*
2050 * If there is an io link to the dev being deleted
2051 * then remove that IO link also.
2052 */
2053 if (iolink->node_to == proximity_domain) {
2054 list_del(&iolink->list);
46d18d51 2055 dev->node_props.io_links_count--;
98447635
MJ
2056 } else {
2057 if (iolink->node_from > proximity_domain)
2058 iolink->node_from--;
2059 if (iolink->node_to > proximity_domain)
2060 iolink->node_to--;
46d18d51
MJ
2061 }
2062 }
0f28cca8
RE
2063
2064 list_for_each_entry_safe(p2plink, tmp, &dev->p2p_link_props, list) {
2065 /*
2066 * If there is a p2p link to the dev being deleted
2067 * then remove that p2p link also.
2068 */
2069 if (p2plink->node_to == proximity_domain) {
2070 list_del(&p2plink->list);
2071 dev->node_props.p2p_links_count--;
2072 } else {
2073 if (p2plink->node_from > proximity_domain)
2074 p2plink->node_from--;
2075 if (p2plink->node_to > proximity_domain)
2076 p2plink->node_to--;
2077 }
2078 }
46d18d51
MJ
2079 }
2080}
2081
8dc1db31 2082int kfd_topology_remove_device(struct kfd_node *gpu)
5b5c4e40 2083{
4f449311 2084 struct kfd_topology_device *dev, *tmp;
5b5c4e40
EP
2085 uint32_t gpu_id;
2086 int res = -ENODEV;
46d18d51 2087 int i = 0;
5b5c4e40 2088
5b5c4e40
EP
2089 down_write(&topology_lock);
2090
46d18d51 2091 list_for_each_entry_safe(dev, tmp, &topology_device_list, list) {
5b5c4e40
EP
2092 if (dev->gpu == gpu) {
2093 gpu_id = dev->gpu_id;
2094 kfd_remove_sysfs_node_entry(dev);
2095 kfd_release_topology_device(dev);
4f449311 2096 sys_props.num_devices--;
46d18d51
MJ
2097 kfd_topology_update_io_links(i);
2098 topology_crat_proximity_domain = sys_props.num_devices-1;
2099 sys_props.generation_count++;
5b5c4e40
EP
2100 res = 0;
2101 if (kfd_topology_update_sysfs() < 0)
2102 kfd_topology_release_sysfs();
2103 break;
2104 }
46d18d51
MJ
2105 i++;
2106 }
5b5c4e40
EP
2107
2108 up_write(&topology_lock);
2109
174de876 2110 if (!res)
5b5c4e40
EP
2111 kfd_notify_gpu_change(gpu_id, 0);
2112
2113 return res;
2114}
2115
6d82eb0e
HK
2116/* kfd_topology_enum_kfd_devices - Enumerate through all devices in KFD
2117 * topology. If GPU device is found @idx, then valid kfd_dev pointer is
2118 * returned through @kdev
2119 * Return - 0: On success (@kdev will be NULL for non GPU nodes)
2120 * -1: If end of list
5b5c4e40 2121 */
8dc1db31 2122int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev)
5b5c4e40
EP
2123{
2124
2125 struct kfd_topology_device *top_dev;
5b5c4e40
EP
2126 uint8_t device_idx = 0;
2127
6d82eb0e 2128 *kdev = NULL;
5b5c4e40
EP
2129 down_read(&topology_lock);
2130
2131 list_for_each_entry(top_dev, &topology_device_list, list) {
2132 if (device_idx == idx) {
6d82eb0e
HK
2133 *kdev = top_dev->gpu;
2134 up_read(&topology_lock);
2135 return 0;
5b5c4e40
EP
2136 }
2137
2138 device_idx++;
2139 }
2140
2141 up_read(&topology_lock);
2142
6d82eb0e 2143 return -1;
5b5c4e40
EP
2144
2145}
851a645e 2146
520b8fb7
FK
2147static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask)
2148{
520b8fb7
FK
2149 int first_cpu_of_numa_node;
2150
2151 if (!cpumask || cpumask == cpu_none_mask)
2152 return -1;
2153 first_cpu_of_numa_node = cpumask_first(cpumask);
2154 if (first_cpu_of_numa_node >= nr_cpu_ids)
2155 return -1;
df1dd4f4
FK
2156#ifdef CONFIG_X86_64
2157 return cpu_data(first_cpu_of_numa_node).apicid;
2158#else
2159 return first_cpu_of_numa_node;
2160#endif
520b8fb7
FK
2161}
2162
2163/* kfd_numa_node_to_apic_id - Returns the APIC ID of the first logical processor
2164 * of the given NUMA node (numa_node_id)
2165 * Return -1 on failure
2166 */
2167int kfd_numa_node_to_apic_id(int numa_node_id)
2168{
2169 if (numa_node_id == -1) {
2170 pr_warn("Invalid NUMA Node. Use online CPU mask\n");
2171 return kfd_cpumask_to_apic_id(cpu_online_mask);
2172 }
2173 return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id));
2174}
2175
6127896f
HR
2176void kfd_double_confirm_iommu_support(struct kfd_dev *gpu)
2177{
2178 struct kfd_topology_device *dev;
2179
2180 gpu->use_iommu_v2 = false;
2181
f0dc99a6 2182 if (!gpu->device_info.needs_iommu_device)
6127896f
HR
2183 return;
2184
2185 down_read(&topology_lock);
2186
2187 /* Only use IOMMUv2 if there is an APU topology node with no GPU
2188 * assigned yet. This GPU will be assigned to it.
2189 */
2190 list_for_each_entry(dev, &topology_device_list, list)
2191 if (dev->node_props.cpu_cores_count &&
2192 dev->node_props.simd_count &&
2193 !dev->gpu)
2194 gpu->use_iommu_v2 = true;
2195
2196 up_read(&topology_lock);
2197}
2198
851a645e
FK
2199#if defined(CONFIG_DEBUG_FS)
2200
2201int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data)
2202{
2203 struct kfd_topology_device *dev;
2204 unsigned int i = 0;
2205 int r = 0;
2206
2207 down_read(&topology_lock);
2208
2209 list_for_each_entry(dev, &topology_device_list, list) {
2210 if (!dev->gpu) {
2211 i++;
2212 continue;
2213 }
2214
2215 seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
2216 r = dqm_debugfs_hqds(m, dev->gpu->dqm);
2217 if (r)
2218 break;
2219 }
2220
2221 up_read(&topology_lock);
2222
2223 return r;
2224}
2225
2226int kfd_debugfs_rls_by_device(struct seq_file *m, void *data)
2227{
2228 struct kfd_topology_device *dev;
2229 unsigned int i = 0;
2230 int r = 0;
2231
2232 down_read(&topology_lock);
2233
2234 list_for_each_entry(dev, &topology_device_list, list) {
2235 if (!dev->gpu) {
2236 i++;
2237 continue;
2238 }
2239
2240 seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
9af5379c 2241 r = pm_debugfs_runlist(m, &dev->gpu->dqm->packet_mgr);
851a645e
FK
2242 if (r)
2243 break;
2244 }
2245
2246 up_read(&topology_lock);
2247
2248 return r;
2249}
2250
2251#endif