Commit | Line | Data |
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4a488a7a OG |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #ifndef KFD_PRIV_H_INCLUDED | |
24 | #define KFD_PRIV_H_INCLUDED | |
25 | ||
26 | #include <linux/hashtable.h> | |
27 | #include <linux/mmu_notifier.h> | |
28 | #include <linux/mutex.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/atomic.h> | |
31 | #include <linux/workqueue.h> | |
32 | #include <linux/spinlock.h> | |
19f6d2a6 | 33 | #include <linux/kfd_ioctl.h> |
482f0777 | 34 | #include <linux/idr.h> |
04ad47bd | 35 | #include <linux/kfifo.h> |
851a645e | 36 | #include <linux/seq_file.h> |
5ce10687 | 37 | #include <linux/kref.h> |
de9f26bb | 38 | #include <linux/sysfs.h> |
6b855f7b | 39 | #include <linux/device_cgroup.h> |
1cd4d9ee SR |
40 | #include <drm/drm_file.h> |
41 | #include <drm/drm_drv.h> | |
42 | #include <drm/drm_device.h> | |
99c7b309 | 43 | #include <drm/drm_ioctl.h> |
4a488a7a | 44 | #include <kgd_kfd_interface.h> |
6d220a7e | 45 | #include <linux/swap.h> |
4a488a7a | 46 | |
e596b903 | 47 | #include "amd_shared.h" |
6ae27841 | 48 | #include "amdgpu.h" |
e596b903 | 49 | |
af47b390 LA |
50 | #define KFD_MAX_RING_ENTRY_SIZE 8 |
51 | ||
5b5c4e40 EP |
52 | #define KFD_SYSFS_FILE_MODE 0444 |
53 | ||
df03ef93 HK |
54 | /* GPU ID hash width in bits */ |
55 | #define KFD_GPU_ID_HASH_WIDTH 16 | |
56 | ||
57 | /* Use upper bits of mmap offset to store KFD driver specific information. | |
58 | * BITS[63:62] - Encode MMAP type | |
59 | * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to | |
60 | * BITS[45:0] - MMAP offset value | |
61 | * | |
62 | * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these | |
63 | * defines are w.r.t to PAGE_SIZE | |
64 | */ | |
29453755 | 65 | #define KFD_MMAP_TYPE_SHIFT 62 |
df03ef93 HK |
66 | #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) |
67 | #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) | |
68 | #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) | |
69 | #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) | |
d33ea570 | 70 | #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) |
df03ef93 | 71 | |
29453755 | 72 | #define KFD_MMAP_GPU_ID_SHIFT 46 |
df03ef93 HK |
73 | #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ |
74 | << KFD_MMAP_GPU_ID_SHIFT) | |
75 | #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ | |
76 | & KFD_MMAP_GPU_ID_MASK) | |
29453755 | 77 | #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ |
df03ef93 HK |
78 | >> KFD_MMAP_GPU_ID_SHIFT) |
79 | ||
ed6e6a34 BG |
80 | /* |
81 | * When working with cp scheduler we should assign the HIQ manually or via | |
e7016d8e | 82 | * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot |
ed6e6a34 BG |
83 | * definitions for Kaveri. In Kaveri only the first ME queues participates |
84 | * in the cp scheduling taking that in mind we set the HIQ slot in the | |
85 | * second ME. | |
86 | */ | |
87 | #define KFD_CIK_HIQ_PIPE 4 | |
88 | #define KFD_CIK_HIQ_QUEUE 0 | |
89 | ||
5b5c4e40 EP |
90 | /* Macro for allocating structures */ |
91 | #define kfd_alloc_struct(ptr_to_struct) \ | |
92 | ((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL)) | |
93 | ||
19f6d2a6 | 94 | #define KFD_MAX_NUM_OF_PROCESSES 512 |
b8cbab04 | 95 | #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 |
19f6d2a6 | 96 | |
373d7080 FK |
97 | /* |
98 | * Size of the per-process TBA+TMA buffer: 2 pages | |
99 | * | |
100 | * The first page is the TBA used for the CWSR ISA code. The second | |
a4497974 | 101 | * page is used as TMA for user-mode trap handler setup in daisy-chain mode. |
373d7080 FK |
102 | */ |
103 | #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) | |
104 | #define KFD_CWSR_TMA_OFFSET PAGE_SIZE | |
105 | ||
74523943 YZ |
106 | #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ |
107 | (KFD_MAX_NUM_OF_PROCESSES * \ | |
108 | KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) | |
109 | ||
110 | #define KFD_KERNEL_QUEUE_SIZE 2048 | |
111 | ||
14328aa5 PC |
112 | #define KFD_UNMAP_LATENCY_MS (4000) |
113 | ||
1f86805a YZ |
114 | /* |
115 | * 512 = 0x200 | |
116 | * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the | |
117 | * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. | |
118 | * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC | |
119 | * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in | |
120 | * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. | |
121 | */ | |
122 | #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 | |
123 | ||
124 | ||
19f6d2a6 | 125 | /* |
b8cbab04 OG |
126 | * Kernel module parameter to specify maximum number of supported queues per |
127 | * device | |
19f6d2a6 | 128 | */ |
b8cbab04 | 129 | extern int max_num_of_queues_per_device; |
19f6d2a6 | 130 | |
ed6e6a34 | 131 | |
31c21fec BG |
132 | /* Kernel module parameter to specify the scheduling policy */ |
133 | extern int sched_policy; | |
134 | ||
a99c6d4f FK |
135 | /* |
136 | * Kernel module parameter to specify the maximum process | |
137 | * number per HW scheduler | |
138 | */ | |
139 | extern int hws_max_conc_proc; | |
140 | ||
373d7080 FK |
141 | extern int cwsr_enable; |
142 | ||
81663016 OG |
143 | /* |
144 | * Kernel module parameter to specify whether to send sigterm to HSA process on | |
145 | * unhandled exception | |
146 | */ | |
147 | extern int send_sigterm; | |
148 | ||
374200b1 FK |
149 | /* |
150 | * This kernel module is used to simulate large bar machine on non-large bar | |
151 | * enabled machines. | |
152 | */ | |
153 | extern int debug_largebar; | |
154 | ||
ebcfd1e2 FK |
155 | /* |
156 | * Ignore CRAT table during KFD initialization, can be used to work around | |
157 | * broken CRAT tables on some AMD systems | |
158 | */ | |
159 | extern int ignore_crat; | |
160 | ||
a4497974 | 161 | /* Set sh_mem_config.retry_disable on GFX v9 */ |
75ee6487 | 162 | extern int amdgpu_noretry; |
bed4f110 | 163 | |
a4497974 | 164 | /* Halt if HWS hang is detected */ |
0e9a860c YZ |
165 | extern int halt_if_hws_hang; |
166 | ||
a4497974 | 167 | /* Whether MEC FW support GWS barriers */ |
29e76462 OZ |
168 | extern bool hws_gws_support; |
169 | ||
a4497974 | 170 | /* Queue preemption timeout in ms */ |
14328aa5 PC |
171 | extern int queue_preemption_timeout_ms; |
172 | ||
6d909c5d OZ |
173 | /* |
174 | * Don't evict process queues on vm fault | |
175 | */ | |
176 | extern int amdgpu_no_queue_eviction_on_vm_fault; | |
177 | ||
a4497974 | 178 | /* Enable eviction debug messages */ |
b2057956 FK |
179 | extern bool debug_evictions; |
180 | ||
ed6e6a34 BG |
181 | enum cache_policy { |
182 | cache_policy_coherent, | |
183 | cache_policy_noncoherent | |
184 | }; | |
185 | ||
ef568db7 FK |
186 | #define KFD_IS_SOC15(chip) ((chip) >= CHIP_VEGA10) |
187 | ||
f3a39818 AL |
188 | struct kfd_event_interrupt_class { |
189 | bool (*interrupt_isr)(struct kfd_dev *dev, | |
58e69886 LX |
190 | const uint32_t *ih_ring_entry, uint32_t *patched_ihre, |
191 | bool *patched_flag); | |
f3a39818 | 192 | void (*interrupt_wq)(struct kfd_dev *dev, |
58e69886 | 193 | const uint32_t *ih_ring_entry); |
f3a39818 AL |
194 | }; |
195 | ||
4a488a7a | 196 | struct kfd_device_info { |
e596b903 | 197 | enum amd_asic_type asic_family; |
c181159a | 198 | const char *asic_name; |
f3a39818 | 199 | const struct kfd_event_interrupt_class *event_interrupt_class; |
4a488a7a | 200 | unsigned int max_pasid_bits; |
992839ad | 201 | unsigned int max_no_of_hqd; |
ada2b29c | 202 | unsigned int doorbell_size; |
4a488a7a | 203 | size_t ih_ring_entry_size; |
f7c826ad | 204 | uint8_t num_of_watch_points; |
19f6d2a6 | 205 | uint16_t mqd_size_aligned; |
373d7080 | 206 | bool supports_cwsr; |
64d1c3a4 | 207 | bool needs_iommu_device; |
3ee2d00c | 208 | bool needs_pci_atomics; |
98bb9222 | 209 | unsigned int num_sdma_engines; |
1b4670f6 | 210 | unsigned int num_xgmi_sdma_engines; |
d5094189 | 211 | unsigned int num_sdma_queues_per_engine; |
4a488a7a OG |
212 | }; |
213 | ||
36b5c08f OG |
214 | struct kfd_mem_obj { |
215 | uint32_t range_start; | |
216 | uint32_t range_end; | |
217 | uint64_t gpu_addr; | |
218 | uint32_t *cpu_ptr; | |
b91d43dd | 219 | void *gtt_mem; |
36b5c08f OG |
220 | }; |
221 | ||
44008d7a YZ |
222 | struct kfd_vmid_info { |
223 | uint32_t first_vmid_kfd; | |
224 | uint32_t last_vmid_kfd; | |
225 | uint32_t vmid_num_kfd; | |
226 | }; | |
227 | ||
4a488a7a OG |
228 | struct kfd_dev { |
229 | struct kgd_dev *kgd; | |
230 | ||
231 | const struct kfd_device_info *device_info; | |
232 | struct pci_dev *pdev; | |
3a0c3423 | 233 | struct drm_device *ddev; |
4a488a7a OG |
234 | |
235 | unsigned int id; /* topology stub index */ | |
236 | ||
19f6d2a6 OG |
237 | phys_addr_t doorbell_base; /* Start of actual doorbells used by |
238 | * KFD. It is aligned for mapping | |
239 | * into user mode | |
240 | */ | |
339903fa YZ |
241 | size_t doorbell_base_dw_offset; /* Offset from the start of the PCI |
242 | * doorbell BAR to the first KFD | |
243 | * doorbell in dwords. GFX reserves | |
244 | * the segment before this offset. | |
19f6d2a6 | 245 | */ |
19f6d2a6 OG |
246 | u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells |
247 | * page used by kernel queue | |
248 | */ | |
249 | ||
4a488a7a | 250 | struct kgd2kfd_shared_resources shared_resources; |
44008d7a | 251 | struct kfd_vmid_info vm_info; |
4a488a7a | 252 | |
cea405b1 XZ |
253 | const struct kfd2kgd_calls *kfd2kgd; |
254 | struct mutex doorbell_mutex; | |
f761d8bd JP |
255 | DECLARE_BITMAP(doorbell_available_index, |
256 | KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); | |
cea405b1 | 257 | |
36b5c08f OG |
258 | void *gtt_mem; |
259 | uint64_t gtt_start_gpu_addr; | |
260 | void *gtt_start_cpu_ptr; | |
261 | void *gtt_sa_bitmap; | |
262 | struct mutex gtt_sa_lock; | |
263 | unsigned int gtt_sa_chunk_size; | |
264 | unsigned int gtt_sa_num_of_chunks; | |
265 | ||
2249d558 | 266 | /* Interrupts */ |
04ad47bd | 267 | struct kfifo ih_fifo; |
48e876a2 | 268 | struct workqueue_struct *ih_wq; |
2249d558 AL |
269 | struct work_struct interrupt_work; |
270 | spinlock_t interrupt_lock; | |
271 | ||
ed6e6a34 BG |
272 | /* QCM Device instance */ |
273 | struct device_queue_manager *dqm; | |
4a488a7a | 274 | |
ed6e6a34 | 275 | bool init_complete; |
2249d558 AL |
276 | /* |
277 | * Interrupts of interest to KFD are copied | |
278 | * from the HW ring into a SW ring. | |
279 | */ | |
280 | bool interrupts_active; | |
fbeb661b YS |
281 | |
282 | /* Debug manager */ | |
0d87c9cf | 283 | struct kfd_dbgmgr *dbgmgr; |
373d7080 | 284 | |
5ade6c9c FK |
285 | /* Firmware versions */ |
286 | uint16_t mec_fw_version; | |
29633d0e | 287 | uint16_t mec2_fw_version; |
5ade6c9c FK |
288 | uint16_t sdma_fw_version; |
289 | ||
a99c6d4f FK |
290 | /* Maximum process number mapped to HW scheduler */ |
291 | unsigned int max_proc_per_quantum; | |
292 | ||
373d7080 FK |
293 | /* CWSR */ |
294 | bool cwsr_enabled; | |
295 | const void *cwsr_isa; | |
296 | unsigned int cwsr_isa_size; | |
0c1690e3 SL |
297 | |
298 | /* xGMI */ | |
299 | uint64_t hive_id; | |
a4497974 | 300 | |
d35f00d8 | 301 | bool pci_atomic_requested; |
9b54d201 | 302 | |
6127896f HR |
303 | /* Use IOMMU v2 flag */ |
304 | bool use_iommu_v2; | |
305 | ||
9b54d201 EH |
306 | /* SRAM ECC flag */ |
307 | atomic_t sram_ecc_flag; | |
f756e631 HK |
308 | |
309 | /* Compute Profile ref. count */ | |
310 | atomic_t compute_profile; | |
e09d4fc8 | 311 | |
a4497974 | 312 | /* Global GWS resource shared between processes */ |
e09d4fc8 | 313 | void *gws; |
938a0650 AL |
314 | |
315 | /* Clients watching SMI events */ | |
316 | struct list_head smi_clients; | |
317 | spinlock_t smi_lock; | |
55977744 MJ |
318 | |
319 | uint32_t reset_seq_num; | |
59d7115d MJ |
320 | |
321 | struct ida doorbell_ida; | |
322 | unsigned int max_doorbell_slices; | |
9b498efa AD |
323 | |
324 | int noretry; | |
4a488a7a OG |
325 | }; |
326 | ||
19f6d2a6 OG |
327 | enum kfd_mempool { |
328 | KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, | |
329 | KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, | |
330 | KFD_MEMPOOL_FRAMEBUFFER = 3, | |
331 | }; | |
332 | ||
4a488a7a OG |
333 | /* Character device interface */ |
334 | int kfd_chardev_init(void); | |
335 | void kfd_chardev_exit(void); | |
336 | struct device *kfd_chardev(void); | |
337 | ||
241f24f8 | 338 | /** |
a4497974 | 339 | * enum kfd_unmap_queues_filter - Enum for queue filters. |
241f24f8 | 340 | * |
7da2bcf8 | 341 | * @KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE: Preempts single queue. |
241f24f8 | 342 | * |
7da2bcf8 | 343 | * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the |
241f24f8 BG |
344 | * running queues list. |
345 | * | |
7da2bcf8 | 346 | * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to |
241f24f8 BG |
347 | * specific process. |
348 | * | |
349 | */ | |
7da2bcf8 YZ |
350 | enum kfd_unmap_queues_filter { |
351 | KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE, | |
352 | KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, | |
353 | KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, | |
354 | KFD_UNMAP_QUEUES_FILTER_BY_PASID | |
241f24f8 | 355 | }; |
19f6d2a6 | 356 | |
ed8aab45 | 357 | /** |
a4497974 | 358 | * enum kfd_queue_type - Enum for various queue types. |
ed8aab45 BG |
359 | * |
360 | * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. | |
361 | * | |
a4497974 | 362 | * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. |
ed8aab45 BG |
363 | * |
364 | * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. | |
365 | * | |
366 | * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. | |
a4497974 RB |
367 | * |
368 | * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. | |
ed8aab45 BG |
369 | */ |
370 | enum kfd_queue_type { | |
371 | KFD_QUEUE_TYPE_COMPUTE, | |
372 | KFD_QUEUE_TYPE_SDMA, | |
373 | KFD_QUEUE_TYPE_HIQ, | |
1b4670f6 OZ |
374 | KFD_QUEUE_TYPE_DIQ, |
375 | KFD_QUEUE_TYPE_SDMA_XGMI | |
ed8aab45 BG |
376 | }; |
377 | ||
6e99df57 BG |
378 | enum kfd_queue_format { |
379 | KFD_QUEUE_FORMAT_PM4, | |
380 | KFD_QUEUE_FORMAT_AQL | |
381 | }; | |
382 | ||
0ccbc7cd OZ |
383 | enum KFD_QUEUE_PRIORITY { |
384 | KFD_QUEUE_PRIORITY_MINIMUM = 0, | |
385 | KFD_QUEUE_PRIORITY_MAXIMUM = 15 | |
386 | }; | |
387 | ||
ed8aab45 BG |
388 | /** |
389 | * struct queue_properties | |
390 | * | |
391 | * @type: The queue type. | |
392 | * | |
393 | * @queue_id: Queue identifier. | |
394 | * | |
395 | * @queue_address: Queue ring buffer address. | |
396 | * | |
397 | * @queue_size: Queue ring buffer size. | |
398 | * | |
399 | * @priority: Defines the queue priority relative to other queues in the | |
400 | * process. | |
401 | * This is just an indication and HW scheduling may override the priority as | |
402 | * necessary while keeping the relative prioritization. | |
403 | * the priority granularity is from 0 to f which f is the highest priority. | |
404 | * currently all queues are initialized with the highest priority. | |
405 | * | |
406 | * @queue_percent: This field is partially implemented and currently a zero in | |
407 | * this field defines that the queue is non active. | |
408 | * | |
409 | * @read_ptr: User space address which points to the number of dwords the | |
410 | * cp read from the ring buffer. This field updates automatically by the H/W. | |
411 | * | |
412 | * @write_ptr: Defines the number of dwords written to the ring buffer. | |
413 | * | |
a4497974 RB |
414 | * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring |
415 | * buffer. This field should be similar to write_ptr and the user should | |
416 | * update this field after updating the write_ptr. | |
ed8aab45 BG |
417 | * |
418 | * @doorbell_off: The doorbell offset in the doorbell pci-bar. | |
419 | * | |
8eabaf54 KR |
420 | * @is_interop: Defines if this is a interop queue. Interop queue means that |
421 | * the queue can access both graphics and compute resources. | |
ed8aab45 | 422 | * |
26103436 FK |
423 | * @is_evicted: Defines if the queue is evicted. Only active queues |
424 | * are evicted, rendering them inactive. | |
425 | * | |
426 | * @is_active: Defines if the queue is active or not. @is_active and | |
427 | * @is_evicted are protected by the DQM lock. | |
ed8aab45 | 428 | * |
b8020b03 JG |
429 | * @is_gws: Defines if the queue has been updated to be GWS-capable or not. |
430 | * @is_gws should be protected by the DQM lock, since changing it can yield the | |
431 | * possibility of updating DQM state on number of GWS queues. | |
432 | * | |
ed8aab45 BG |
433 | * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid |
434 | * of the queue. | |
435 | * | |
436 | * This structure represents the queue properties for each queue no matter if | |
437 | * it's user mode or kernel mode queue. | |
438 | * | |
439 | */ | |
440 | struct queue_properties { | |
441 | enum kfd_queue_type type; | |
6e99df57 | 442 | enum kfd_queue_format format; |
ed8aab45 BG |
443 | unsigned int queue_id; |
444 | uint64_t queue_address; | |
445 | uint64_t queue_size; | |
446 | uint32_t priority; | |
447 | uint32_t queue_percent; | |
448 | uint32_t *read_ptr; | |
449 | uint32_t *write_ptr; | |
ada2b29c | 450 | void __iomem *doorbell_ptr; |
ed8aab45 BG |
451 | uint32_t doorbell_off; |
452 | bool is_interop; | |
26103436 | 453 | bool is_evicted; |
ed8aab45 | 454 | bool is_active; |
b8020b03 | 455 | bool is_gws; |
ed8aab45 BG |
456 | /* Not relevant for user mode queues in cp scheduling */ |
457 | unsigned int vmid; | |
77669eb8 BG |
458 | /* Relevant only for sdma queues*/ |
459 | uint32_t sdma_engine_id; | |
460 | uint32_t sdma_queue_id; | |
461 | uint32_t sdma_vm_addr; | |
ff3d04a1 BG |
462 | /* Relevant only for VI */ |
463 | uint64_t eop_ring_buffer_address; | |
464 | uint32_t eop_ring_buffer_size; | |
465 | uint64_t ctx_save_restore_area_address; | |
466 | uint32_t ctx_save_restore_area_size; | |
373d7080 FK |
467 | uint32_t ctl_stack_size; |
468 | uint64_t tba_addr; | |
469 | uint64_t tma_addr; | |
39e7f331 FK |
470 | /* Relevant for CU */ |
471 | uint32_t cu_mask_count; /* Must be a multiple of 32 */ | |
472 | uint32_t *cu_mask; | |
ed8aab45 BG |
473 | }; |
474 | ||
bb2d2128 FK |
475 | #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ |
476 | (q).queue_address != 0 && \ | |
477 | (q).queue_percent > 0 && \ | |
478 | !(q).is_evicted) | |
479 | ||
ed8aab45 BG |
480 | /** |
481 | * struct queue | |
482 | * | |
483 | * @list: Queue linked list. | |
484 | * | |
a4497974 | 485 | * @mqd: The queue MQD (memory queue descriptor). |
ed8aab45 BG |
486 | * |
487 | * @mqd_mem_obj: The MQD local gpu memory object. | |
488 | * | |
489 | * @gart_mqd_addr: The MQD gart mc address. | |
490 | * | |
491 | * @properties: The queue properties. | |
492 | * | |
493 | * @mec: Used only in no cp scheduling mode and identifies to micro engine id | |
a4497974 | 494 | * that the queue should be executed on. |
ed8aab45 | 495 | * |
8eabaf54 KR |
496 | * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe |
497 | * id. | |
ed8aab45 BG |
498 | * |
499 | * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. | |
500 | * | |
501 | * @process: The kfd process that created this queue. | |
502 | * | |
503 | * @device: The kfd device that created this queue. | |
504 | * | |
eb82da1d OZ |
505 | * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL |
506 | * otherwise. | |
507 | * | |
ed8aab45 BG |
508 | * This structure represents user mode compute queues. |
509 | * It contains all the necessary data to handle such queues. | |
510 | * | |
511 | */ | |
512 | ||
513 | struct queue { | |
514 | struct list_head list; | |
515 | void *mqd; | |
516 | struct kfd_mem_obj *mqd_mem_obj; | |
517 | uint64_t gart_mqd_addr; | |
518 | struct queue_properties properties; | |
519 | ||
520 | uint32_t mec; | |
521 | uint32_t pipe; | |
522 | uint32_t queue; | |
523 | ||
77669eb8 | 524 | unsigned int sdma_id; |
ef568db7 | 525 | unsigned int doorbell_id; |
77669eb8 | 526 | |
ed8aab45 BG |
527 | struct kfd_process *process; |
528 | struct kfd_dev *device; | |
eb82da1d | 529 | void *gws; |
6d220a7e AL |
530 | |
531 | /* procfs */ | |
532 | struct kobject kobj; | |
ed8aab45 BG |
533 | }; |
534 | ||
6e99df57 | 535 | enum KFD_MQD_TYPE { |
d7c0b047 | 536 | KFD_MQD_TYPE_HIQ = 0, /* for hiq */ |
85d258f9 BG |
537 | KFD_MQD_TYPE_CP, /* for cp queues and diq */ |
538 | KFD_MQD_TYPE_SDMA, /* for sdma queues */ | |
59f650a0 | 539 | KFD_MQD_TYPE_DIQ, /* for diq */ |
6e99df57 BG |
540 | KFD_MQD_TYPE_MAX |
541 | }; | |
542 | ||
0ccbc7cd OZ |
543 | enum KFD_PIPE_PRIORITY { |
544 | KFD_PIPE_PRIORITY_CS_LOW = 0, | |
545 | KFD_PIPE_PRIORITY_CS_MEDIUM, | |
546 | KFD_PIPE_PRIORITY_CS_HIGH | |
547 | }; | |
548 | ||
241f24f8 BG |
549 | struct scheduling_resources { |
550 | unsigned int vmid_mask; | |
551 | enum kfd_queue_type type; | |
552 | uint64_t queue_mask; | |
553 | uint64_t gws_mask; | |
554 | uint32_t oac_mask; | |
555 | uint32_t gds_heap_base; | |
556 | uint32_t gds_heap_size; | |
557 | }; | |
558 | ||
559 | struct process_queue_manager { | |
560 | /* data */ | |
561 | struct kfd_process *process; | |
241f24f8 BG |
562 | struct list_head queues; |
563 | unsigned long *queue_slot_bitmap; | |
564 | }; | |
565 | ||
566 | struct qcm_process_device { | |
567 | /* The Device Queue Manager that owns this data */ | |
568 | struct device_queue_manager *dqm; | |
569 | struct process_queue_manager *pqm; | |
241f24f8 BG |
570 | /* Queues list */ |
571 | struct list_head queues_list; | |
572 | struct list_head priv_queue_list; | |
573 | ||
574 | unsigned int queue_count; | |
575 | unsigned int vmid; | |
576 | bool is_debug; | |
26103436 | 577 | unsigned int evicted; /* eviction counter, 0=active */ |
9fd3f1bf FK |
578 | |
579 | /* This flag tells if we should reset all wavefronts on | |
580 | * process termination | |
581 | */ | |
582 | bool reset_wavefronts; | |
583 | ||
b8020b03 JG |
584 | /* This flag tells us if this process has a GWS-capable |
585 | * queue that will be mapped into the runlist. It's | |
586 | * possible to request a GWS BO, but not have the queue | |
587 | * currently mapped, and this changes how the MAP_PROCESS | |
588 | * PM4 packet is configured. | |
589 | */ | |
590 | bool mapped_gws_queue; | |
591 | ||
a4497974 | 592 | /* All the memory management data should be here too */ |
241f24f8 | 593 | uint64_t gds_context_area; |
435e2f97 | 594 | /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ |
e715c6d0 | 595 | uint64_t page_table_base; |
241f24f8 BG |
596 | uint32_t sh_mem_config; |
597 | uint32_t sh_mem_bases; | |
598 | uint32_t sh_mem_ape1_base; | |
599 | uint32_t sh_mem_ape1_limit; | |
241f24f8 BG |
600 | uint32_t gds_size; |
601 | uint32_t num_gws; | |
602 | uint32_t num_oac; | |
6a1c9510 | 603 | uint32_t sh_hidden_private_base; |
373d7080 FK |
604 | |
605 | /* CWSR memory */ | |
606 | void *cwsr_kaddr; | |
d01994c2 | 607 | uint64_t cwsr_base; |
373d7080 FK |
608 | uint64_t tba_addr; |
609 | uint64_t tma_addr; | |
d01994c2 FK |
610 | |
611 | /* IB memory */ | |
612 | uint64_t ib_base; | |
552764b6 | 613 | void *ib_kaddr; |
ef568db7 FK |
614 | |
615 | /* doorbell resources per process per device */ | |
616 | unsigned long *doorbell_bitmap; | |
241f24f8 BG |
617 | }; |
618 | ||
26103436 FK |
619 | /* KFD Memory Eviction */ |
620 | ||
621 | /* Approx. wait time before attempting to restore evicted BOs */ | |
622 | #define PROCESS_RESTORE_TIME_MS 100 | |
623 | /* Approx. back off time if restore fails due to lack of memory */ | |
624 | #define PROCESS_BACK_OFF_TIME_MS 100 | |
625 | /* Approx. time before evicting the process again */ | |
626 | #define PROCESS_ACTIVE_TIME_MS 10 | |
627 | ||
5ec7e028 FK |
628 | /* 8 byte handle containing GPU ID in the most significant 4 bytes and |
629 | * idr_handle in the least significant 4 bytes | |
630 | */ | |
631 | #define MAKE_HANDLE(gpu_id, idr_handle) \ | |
632 | (((uint64_t)(gpu_id) << 32) + idr_handle) | |
633 | #define GET_GPU_ID(handle) (handle >> 32) | |
634 | #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) | |
635 | ||
733fa1f7 YZ |
636 | enum kfd_pdd_bound { |
637 | PDD_UNBOUND = 0, | |
638 | PDD_BOUND, | |
639 | PDD_BOUND_SUSPENDED, | |
640 | }; | |
641 | ||
4327bed2 | 642 | #define MAX_SYSFS_FILENAME_LEN 15 |
32cb59f3 MJ |
643 | |
644 | /* | |
645 | * SDMA counter runs at 100MHz frequency. | |
646 | * We display SDMA activity in microsecond granularity in sysfs. | |
647 | * As a result, the divisor is 100. | |
648 | */ | |
649 | #define SDMA_ACTIVITY_DIVISOR 100 | |
d4566dee | 650 | |
19f6d2a6 OG |
651 | /* Data that is per-process-per device. */ |
652 | struct kfd_process_device { | |
19f6d2a6 OG |
653 | /* The device that owns this data. */ |
654 | struct kfd_dev *dev; | |
655 | ||
9fd3f1bf FK |
656 | /* The process that owns this kfd_process_device. */ |
657 | struct kfd_process *process; | |
19f6d2a6 | 658 | |
45102048 BG |
659 | /* per-process-per device QCM data structure */ |
660 | struct qcm_process_device qpd; | |
661 | ||
19f6d2a6 OG |
662 | /*Apertures*/ |
663 | uint64_t lds_base; | |
664 | uint64_t lds_limit; | |
665 | uint64_t gpuvm_base; | |
666 | uint64_t gpuvm_limit; | |
667 | uint64_t scratch_base; | |
668 | uint64_t scratch_limit; | |
669 | ||
403575c4 | 670 | /* VM context for GPUVM allocations */ |
b84394e2 | 671 | struct file *drm_file; |
b40a6ab2 | 672 | void *drm_priv; |
403575c4 | 673 | |
52b29d73 FK |
674 | /* GPUVM allocations storage */ |
675 | struct idr alloc_idr; | |
676 | ||
9fd3f1bf FK |
677 | /* Flag used to tell the pdd has dequeued from the dqm. |
678 | * This is used to prevent dev->dqm->ops.process_termination() from | |
679 | * being called twice when it is already called in IOMMU callback | |
680 | * function. | |
a82918f1 | 681 | */ |
9fd3f1bf | 682 | bool already_dequeued; |
9593f4d6 | 683 | bool runtime_inuse; |
64d1c3a4 FK |
684 | |
685 | /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ | |
686 | enum kfd_pdd_bound bound; | |
d4566dee MJ |
687 | |
688 | /* VRAM usage */ | |
689 | uint64_t vram_usage; | |
690 | struct attribute attr_vram; | |
32cb59f3 MJ |
691 | char vram_filename[MAX_SYSFS_FILENAME_LEN]; |
692 | ||
693 | /* SDMA activity tracking */ | |
694 | uint64_t sdma_past_activity_counter; | |
695 | struct attribute attr_sdma; | |
696 | char sdma_filename[MAX_SYSFS_FILENAME_LEN]; | |
4327bed2 PC |
697 | |
698 | /* Eviction activity tracking */ | |
699 | uint64_t last_evict_timestamp; | |
700 | atomic64_t evict_duration_counter; | |
701 | struct attribute attr_evict; | |
702 | ||
703 | struct kobject *kobj_stats; | |
59d7115d | 704 | unsigned int doorbell_index; |
f2fa07b3 RE |
705 | |
706 | /* | |
707 | * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process | |
708 | * that is associated with device encoded by "this" struct instance. The | |
709 | * value reflects CU usage by all of the waves launched by this process | |
710 | * on this device. A very important property of occupancy parameter is | |
711 | * that its value is a snapshot of current use. | |
712 | * | |
713 | * Following is to be noted regarding how this parameter is reported: | |
714 | * | |
715 | * The number of waves that a CU can launch is limited by couple of | |
716 | * parameters. These are encoded by struct amdgpu_cu_info instance | |
717 | * that is part of every device definition. For GFX9 devices this | |
718 | * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves | |
719 | * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) | |
720 | * when they do use scratch memory. This could change for future | |
721 | * devices and therefore this example should be considered as a guide. | |
722 | * | |
723 | * All CU's of a device are available for the process. This may not be true | |
724 | * under certain conditions - e.g. CU masking. | |
725 | * | |
726 | * Finally number of CU's that are occupied by a process is affected by both | |
727 | * number of CU's a device has along with number of other competing processes | |
728 | */ | |
729 | struct attribute attr_cu_occupancy; | |
19f6d2a6 OG |
730 | }; |
731 | ||
52a5fdce AS |
732 | #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) |
733 | ||
4a488a7a OG |
734 | /* Process data */ |
735 | struct kfd_process { | |
19f6d2a6 OG |
736 | /* |
737 | * kfd_process are stored in an mm_struct*->kfd_process* | |
738 | * hash table (kfd_processes in kfd_process.c) | |
739 | */ | |
740 | struct hlist_node kfd_processes; | |
741 | ||
9b56bb11 FK |
742 | /* |
743 | * Opaque pointer to mm_struct. We don't hold a reference to | |
744 | * it so it should never be dereferenced from here. This is | |
745 | * only used for looking up processes by their mm. | |
746 | */ | |
747 | void *mm; | |
19f6d2a6 | 748 | |
5ce10687 FK |
749 | struct kref ref; |
750 | struct work_struct release_work; | |
751 | ||
19f6d2a6 OG |
752 | struct mutex mutex; |
753 | ||
754 | /* | |
755 | * In any process, the thread that started main() is the lead | |
756 | * thread and outlives the rest. | |
757 | * It is here because amd_iommu_bind_pasid wants a task_struct. | |
894a8293 FK |
758 | * It can also be used for safely getting a reference to the |
759 | * mm_struct of the process. | |
19f6d2a6 OG |
760 | */ |
761 | struct task_struct *lead_thread; | |
762 | ||
763 | /* We want to receive a notification when the mm_struct is destroyed */ | |
764 | struct mmu_notifier mmu_notifier; | |
765 | ||
c7b6bac9 | 766 | u32 pasid; |
19f6d2a6 OG |
767 | |
768 | /* | |
6ae27841 | 769 | * Array of kfd_process_device pointers, |
19f6d2a6 OG |
770 | * one for each device the process is using. |
771 | */ | |
6ae27841 AS |
772 | struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; |
773 | uint32_t n_pdds; | |
19f6d2a6 | 774 | |
45102048 BG |
775 | struct process_queue_manager pqm; |
776 | ||
19f6d2a6 OG |
777 | /*Is the user space process 32 bit?*/ |
778 | bool is_32bit_user_mode; | |
f3a39818 AL |
779 | |
780 | /* Event-related data */ | |
781 | struct mutex event_mutex; | |
482f0777 FK |
782 | /* Event ID allocator and lookup */ |
783 | struct idr event_idr; | |
50cb7dd9 FK |
784 | /* Event page */ |
785 | struct kfd_signal_page *signal_page; | |
b9a5d0a5 | 786 | size_t signal_mapped_size; |
f3a39818 | 787 | size_t signal_event_count; |
c986169f | 788 | bool signal_event_limit_reached; |
403575c4 FK |
789 | |
790 | /* Information used for memory eviction */ | |
791 | void *kgd_process_info; | |
792 | /* Eviction fence that is attached to all the BOs of this process. The | |
793 | * fence will be triggered during eviction and new one will be created | |
794 | * during restore | |
795 | */ | |
796 | struct dma_fence *ef; | |
26103436 FK |
797 | |
798 | /* Work items for evicting and restoring BOs */ | |
799 | struct delayed_work eviction_work; | |
800 | struct delayed_work restore_work; | |
801 | /* seqno of the last scheduled eviction */ | |
802 | unsigned int last_eviction_seqno; | |
803 | /* Approx. the last timestamp (in jiffies) when the process was | |
804 | * restored after an eviction | |
805 | */ | |
806 | unsigned long last_restore_timestamp; | |
de9f26bb KR |
807 | |
808 | /* Kobj for our procfs */ | |
809 | struct kobject *kobj; | |
6d220a7e | 810 | struct kobject *kobj_queues; |
de9f26bb | 811 | struct attribute attr_pasid; |
40ce74d1 PY |
812 | |
813 | bool svm_disabled; | |
4a488a7a OG |
814 | }; |
815 | ||
64d1c3a4 FK |
816 | #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ |
817 | extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); | |
818 | extern struct srcu_struct kfd_processes_srcu; | |
819 | ||
76baee6c | 820 | /** |
a4497974 RB |
821 | * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. |
822 | * | |
823 | * @filep: pointer to file structure. | |
824 | * @p: amdkfd process pointer. | |
825 | * @data: pointer to arg that was copied from user. | |
76baee6c | 826 | * |
a4497974 | 827 | * Return: returns ioctl completion code. |
76baee6c OG |
828 | */ |
829 | typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, | |
830 | void *data); | |
831 | ||
832 | struct amdkfd_ioctl_desc { | |
833 | unsigned int cmd; | |
834 | int flags; | |
835 | amdkfd_ioctl_t *func; | |
836 | unsigned int cmd_drv; | |
837 | const char *name; | |
838 | }; | |
67f7cf9f | 839 | bool kfd_dev_is_large_bar(struct kfd_dev *dev); |
76baee6c | 840 | |
1679ae8f | 841 | int kfd_process_create_wq(void); |
19f6d2a6 | 842 | void kfd_process_destroy_wq(void); |
373d7080 | 843 | struct kfd_process *kfd_create_process(struct file *filep); |
19f6d2a6 | 844 | struct kfd_process *kfd_get_process(const struct task_struct *); |
c7b6bac9 | 845 | struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid); |
26103436 | 846 | struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); |
2aeb742b AS |
847 | |
848 | int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); | |
849 | static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, | |
850 | uint32_t gpuidx, uint32_t *gpuid) { | |
851 | return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; | |
852 | } | |
853 | static inline struct kfd_process_device *kfd_process_device_from_gpuidx( | |
854 | struct kfd_process *p, uint32_t gpuidx) { | |
855 | return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; | |
856 | } | |
857 | ||
abb208a8 | 858 | void kfd_unref_process(struct kfd_process *p); |
6b95e797 FK |
859 | int kfd_process_evict_queues(struct kfd_process *p); |
860 | int kfd_process_restore_queues(struct kfd_process *p); | |
26103436 FK |
861 | void kfd_suspend_all_processes(void); |
862 | int kfd_resume_all_processes(void); | |
19f6d2a6 | 863 | |
b84394e2 FK |
864 | int kfd_process_device_init_vm(struct kfd_process_device *pdd, |
865 | struct file *drm_file); | |
64c7f8cf | 866 | struct kfd_process_device *kfd_bind_process_to_device(struct kfd_dev *dev, |
733fa1f7 | 867 | struct kfd_process *p); |
19f6d2a6 | 868 | struct kfd_process_device *kfd_get_process_device_data(struct kfd_dev *dev, |
093c7d8c AS |
869 | struct kfd_process *p); |
870 | struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, | |
871 | struct kfd_process *p); | |
19f6d2a6 | 872 | |
df03ef93 | 873 | int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process, |
373d7080 FK |
874 | struct vm_area_struct *vma); |
875 | ||
52b29d73 FK |
876 | /* KFD process API for creating and translating handles */ |
877 | int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, | |
878 | void *mem); | |
879 | void *kfd_process_device_translate_handle(struct kfd_process_device *p, | |
880 | int handle); | |
881 | void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, | |
882 | int handle); | |
883 | ||
19f6d2a6 OG |
884 | /* PASIDs */ |
885 | int kfd_pasid_init(void); | |
886 | void kfd_pasid_exit(void); | |
887 | bool kfd_set_pasid_limit(unsigned int new_limit); | |
888 | unsigned int kfd_get_pasid_limit(void); | |
c7b6bac9 FY |
889 | u32 kfd_pasid_alloc(void); |
890 | void kfd_pasid_free(u32 pasid); | |
19f6d2a6 OG |
891 | |
892 | /* Doorbells */ | |
ef568db7 | 893 | size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); |
735df2ba FK |
894 | int kfd_doorbell_init(struct kfd_dev *kfd); |
895 | void kfd_doorbell_fini(struct kfd_dev *kfd); | |
df03ef93 HK |
896 | int kfd_doorbell_mmap(struct kfd_dev *dev, struct kfd_process *process, |
897 | struct vm_area_struct *vma); | |
ada2b29c | 898 | void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, |
19f6d2a6 OG |
899 | unsigned int *doorbell_off); |
900 | void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); | |
901 | u32 read_kernel_doorbell(u32 __iomem *db); | |
ada2b29c | 902 | void write_kernel_doorbell(void __iomem *db, u32 value); |
9d7d0248 | 903 | void write_kernel_doorbell64(void __iomem *db, u64 value); |
339903fa | 904 | unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, |
59d7115d | 905 | struct kfd_process_device *pdd, |
ef568db7 | 906 | unsigned int doorbell_id); |
59d7115d MJ |
907 | phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); |
908 | int kfd_alloc_process_doorbells(struct kfd_dev *kfd, | |
909 | unsigned int *doorbell_index); | |
910 | void kfd_free_process_doorbells(struct kfd_dev *kfd, | |
911 | unsigned int doorbell_index); | |
6e81090b OG |
912 | /* GTT Sub-Allocator */ |
913 | ||
914 | int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, | |
915 | struct kfd_mem_obj **mem_obj); | |
916 | ||
917 | int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj); | |
918 | ||
4a488a7a OG |
919 | extern struct device *kfd_device; |
920 | ||
de9f26bb KR |
921 | /* KFD's procfs */ |
922 | void kfd_procfs_init(void); | |
923 | void kfd_procfs_shutdown(void); | |
6d220a7e AL |
924 | int kfd_procfs_add_queue(struct queue *q); |
925 | void kfd_procfs_del_queue(struct queue *q); | |
de9f26bb | 926 | |
5b5c4e40 EP |
927 | /* Topology */ |
928 | int kfd_topology_init(void); | |
929 | void kfd_topology_shutdown(void); | |
930 | int kfd_topology_add_device(struct kfd_dev *gpu); | |
931 | int kfd_topology_remove_device(struct kfd_dev *gpu); | |
3a87177e HK |
932 | struct kfd_topology_device *kfd_topology_device_by_proximity_domain( |
933 | uint32_t proximity_domain); | |
44d8cc6f | 934 | struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); |
5b5c4e40 EP |
935 | struct kfd_dev *kfd_device_by_id(uint32_t gpu_id); |
936 | struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev); | |
1dde0ea9 | 937 | struct kfd_dev *kfd_device_by_kgd(const struct kgd_dev *kgd); |
6d82eb0e | 938 | int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev); |
520b8fb7 | 939 | int kfd_numa_node_to_apic_id(int numa_node_id); |
6127896f | 940 | void kfd_double_confirm_iommu_support(struct kfd_dev *gpu); |
5b5c4e40 | 941 | |
4a488a7a | 942 | /* Interrupts */ |
2249d558 AL |
943 | int kfd_interrupt_init(struct kfd_dev *dev); |
944 | void kfd_interrupt_exit(struct kfd_dev *dev); | |
2249d558 | 945 | bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry); |
58e69886 LX |
946 | bool interrupt_is_wanted(struct kfd_dev *dev, |
947 | const uint32_t *ih_ring_entry, | |
948 | uint32_t *patched_ihre, bool *flag); | |
4a488a7a | 949 | |
19f6d2a6 OG |
950 | /* amdkfd Apertures */ |
951 | int kfd_init_apertures(struct kfd_process *process); | |
952 | ||
7c9631af JC |
953 | void kfd_process_set_trap_handler(struct qcm_process_device *qpd, |
954 | uint64_t tba_addr, | |
955 | uint64_t tma_addr); | |
956 | ||
ed6e6a34 | 957 | /* Queue Context Management */ |
e88a614c | 958 | int init_queue(struct queue **q, const struct queue_properties *properties); |
ed6e6a34 | 959 | void uninit_queue(struct queue *q); |
45102048 | 960 | void print_queue_properties(struct queue_properties *q); |
ed6e6a34 BG |
961 | void print_queue(struct queue *q); |
962 | ||
4b8f589b BG |
963 | struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, |
964 | struct kfd_dev *dev); | |
ee04955a FK |
965 | struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type, |
966 | struct kfd_dev *dev); | |
4b8f589b BG |
967 | struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, |
968 | struct kfd_dev *dev); | |
ee04955a FK |
969 | struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type, |
970 | struct kfd_dev *dev); | |
b91d43dd FK |
971 | struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, |
972 | struct kfd_dev *dev); | |
14328aa5 PC |
973 | struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, |
974 | struct kfd_dev *dev); | |
64c7f8cf BG |
975 | struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev); |
976 | void device_queue_manager_uninit(struct device_queue_manager *dqm); | |
241f24f8 BG |
977 | struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, |
978 | enum kfd_queue_type type); | |
c2a77fde | 979 | void kernel_queue_uninit(struct kernel_queue *kq, bool hanging); |
c7b6bac9 | 980 | int kfd_process_vm_fault(struct device_queue_manager *dqm, u32 pasid); |
241f24f8 | 981 | |
45102048 BG |
982 | /* Process Queue Manager */ |
983 | struct process_queue_node { | |
984 | struct queue *q; | |
985 | struct kernel_queue *kq; | |
986 | struct list_head process_queue_list; | |
987 | }; | |
988 | ||
9fd3f1bf FK |
989 | void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); |
990 | void kfd_process_dequeue_from_all_devices(struct kfd_process *p); | |
45102048 BG |
991 | int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); |
992 | void pqm_uninit(struct process_queue_manager *pqm); | |
993 | int pqm_create_queue(struct process_queue_manager *pqm, | |
994 | struct kfd_dev *dev, | |
995 | struct file *f, | |
996 | struct queue_properties *properties, | |
e47a8b52 YZ |
997 | unsigned int *qid, |
998 | uint32_t *p_doorbell_offset_in_process); | |
45102048 BG |
999 | int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); |
1000 | int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid, | |
1001 | struct queue_properties *p); | |
39e7f331 FK |
1002 | int pqm_set_cu_mask(struct process_queue_manager *pqm, unsigned int qid, |
1003 | struct queue_properties *p); | |
eb82da1d OZ |
1004 | int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, |
1005 | void *gws); | |
fbeb661b YS |
1006 | struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm, |
1007 | unsigned int qid); | |
5bb4b78b OZ |
1008 | struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, |
1009 | unsigned int qid); | |
5df099e8 JC |
1010 | int pqm_get_wave_state(struct process_queue_manager *pqm, |
1011 | unsigned int qid, | |
1012 | void __user *ctl_stack, | |
1013 | u32 *ctl_stack_used_size, | |
1014 | u32 *save_area_used_size); | |
45102048 | 1015 | |
b010affe QH |
1016 | int amdkfd_fence_wait_timeout(uint64_t *fence_addr, |
1017 | uint64_t fence_value, | |
14328aa5 | 1018 | unsigned int timeout_ms); |
788bf83d | 1019 | |
ed6e6a34 BG |
1020 | /* Packet Manager */ |
1021 | ||
64c7f8cf BG |
1022 | #define KFD_FENCE_COMPLETED (100) |
1023 | #define KFD_FENCE_INIT (10) | |
241f24f8 | 1024 | |
ed6e6a34 BG |
1025 | struct packet_manager { |
1026 | struct device_queue_manager *dqm; | |
1027 | struct kernel_queue *priv_queue; | |
1028 | struct mutex lock; | |
1029 | bool allocated; | |
1030 | struct kfd_mem_obj *ib_buffer_obj; | |
851a645e | 1031 | unsigned int ib_size_bytes; |
819ec5ac | 1032 | bool is_over_subscription; |
f6e27ff1 FK |
1033 | |
1034 | const struct packet_manager_funcs *pmf; | |
1035 | }; | |
1036 | ||
1037 | struct packet_manager_funcs { | |
1038 | /* Support ASIC-specific packet formats for PM4 packets */ | |
1039 | int (*map_process)(struct packet_manager *pm, uint32_t *buffer, | |
1040 | struct qcm_process_device *qpd); | |
1041 | int (*runlist)(struct packet_manager *pm, uint32_t *buffer, | |
1042 | uint64_t ib, size_t ib_size_in_dwords, bool chain); | |
1043 | int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, | |
1044 | struct scheduling_resources *res); | |
1045 | int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, | |
1046 | struct queue *q, bool is_static); | |
1047 | int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, | |
1048 | enum kfd_queue_type type, | |
1049 | enum kfd_unmap_queues_filter mode, | |
1050 | uint32_t filter_param, bool reset, | |
1051 | unsigned int sdma_engine); | |
1052 | int (*query_status)(struct packet_manager *pm, uint32_t *buffer, | |
b010affe | 1053 | uint64_t fence_address, uint64_t fence_value); |
f6e27ff1 FK |
1054 | int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); |
1055 | ||
1056 | /* Packet sizes */ | |
1057 | int map_process_size; | |
1058 | int runlist_size; | |
1059 | int set_resources_size; | |
1060 | int map_queues_size; | |
1061 | int unmap_queues_size; | |
1062 | int query_status_size; | |
1063 | int release_mem_size; | |
ed6e6a34 BG |
1064 | }; |
1065 | ||
f6e27ff1 | 1066 | extern const struct packet_manager_funcs kfd_vi_pm_funcs; |
454150b1 | 1067 | extern const struct packet_manager_funcs kfd_v9_pm_funcs; |
f6e27ff1 | 1068 | |
64c7f8cf | 1069 | int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); |
c2a77fde | 1070 | void pm_uninit(struct packet_manager *pm, bool hanging); |
64c7f8cf BG |
1071 | int pm_send_set_resources(struct packet_manager *pm, |
1072 | struct scheduling_resources *res); | |
1073 | int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); | |
1074 | int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, | |
b010affe | 1075 | uint64_t fence_value); |
64c7f8cf BG |
1076 | |
1077 | int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, | |
7da2bcf8 | 1078 | enum kfd_unmap_queues_filter mode, |
64c7f8cf BG |
1079 | uint32_t filter_param, bool reset, |
1080 | unsigned int sdma_engine); | |
1081 | ||
241f24f8 BG |
1082 | void pm_release_ib(struct packet_manager *pm); |
1083 | ||
454150b1 FK |
1084 | /* Following PM funcs can be shared among VI and AI */ |
1085 | unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); | |
454150b1 | 1086 | |
19f6d2a6 | 1087 | uint64_t kfd_get_number_elems(struct kfd_dev *kfd); |
19f6d2a6 | 1088 | |
f3a39818 AL |
1089 | /* Events */ |
1090 | extern const struct kfd_event_interrupt_class event_interrupt_class_cik; | |
ca750681 FK |
1091 | extern const struct kfd_event_interrupt_class event_interrupt_class_v9; |
1092 | ||
930c5ff4 | 1093 | extern const struct kfd_device_global_init_class device_global_init_class_cik; |
f3a39818 | 1094 | |
f3a39818 AL |
1095 | void kfd_event_init_process(struct kfd_process *p); |
1096 | void kfd_event_free_process(struct kfd_process *p); | |
1097 | int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); | |
1098 | int kfd_wait_on_events(struct kfd_process *p, | |
59d3e8be | 1099 | uint32_t num_events, void __user *data, |
f3a39818 | 1100 | bool all, uint32_t user_timeout_ms, |
fdf0c833 | 1101 | uint32_t *wait_result); |
c7b6bac9 | 1102 | void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, |
f3a39818 | 1103 | uint32_t valid_id_bits); |
59d3e8be | 1104 | void kfd_signal_iommu_event(struct kfd_dev *dev, |
c7b6bac9 FY |
1105 | u32 pasid, unsigned long address, |
1106 | bool is_write_requested, bool is_execute_requested); | |
1107 | void kfd_signal_hw_exception_event(u32 pasid); | |
f3a39818 AL |
1108 | int kfd_set_event(struct kfd_process *p, uint32_t event_id); |
1109 | int kfd_reset_event(struct kfd_process *p, uint32_t event_id); | |
0fc8011f FK |
1110 | int kfd_event_page_set(struct kfd_process *p, void *kernel_address, |
1111 | uint64_t size); | |
f3a39818 AL |
1112 | int kfd_event_create(struct file *devkfd, struct kfd_process *p, |
1113 | uint32_t event_type, bool auto_reset, uint32_t node_id, | |
1114 | uint32_t *event_id, uint32_t *event_trigger_data, | |
1115 | uint64_t *event_page_offset, uint32_t *event_slot_index); | |
1116 | int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); | |
1117 | ||
c7b6bac9 | 1118 | void kfd_signal_vm_fault_event(struct kfd_dev *dev, u32 pasid, |
2640c3fa | 1119 | struct kfd_vm_fault_info *info); |
1120 | ||
e42051d2 SL |
1121 | void kfd_signal_reset_event(struct kfd_dev *dev); |
1122 | ||
403575c4 FK |
1123 | void kfd_flush_tlb(struct kfd_process_device *pdd); |
1124 | ||
c3447e81 BG |
1125 | int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p); |
1126 | ||
e42051d2 SL |
1127 | bool kfd_is_locked(void); |
1128 | ||
f756e631 HK |
1129 | /* Compute profile */ |
1130 | void kfd_inc_compute_active(struct kfd_dev *dev); | |
1131 | void kfd_dec_compute_active(struct kfd_dev *dev); | |
1132 | ||
6b855f7b HK |
1133 | /* Cgroup Support */ |
1134 | /* Check with device cgroup if @kfd device is accessible */ | |
1135 | static inline int kfd_devcgroup_check_permission(struct kfd_dev *kfd) | |
1136 | { | |
eec8fd02 | 1137 | #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) |
6b855f7b HK |
1138 | struct drm_device *ddev = kfd->ddev; |
1139 | ||
99c7b309 | 1140 | return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, |
6b855f7b HK |
1141 | ddev->render->index, |
1142 | DEVCG_ACC_WRITE | DEVCG_ACC_READ); | |
1143 | #else | |
1144 | return 0; | |
1145 | #endif | |
1146 | } | |
1147 | ||
851a645e FK |
1148 | /* Debugfs */ |
1149 | #if defined(CONFIG_DEBUG_FS) | |
1150 | ||
1151 | void kfd_debugfs_init(void); | |
1152 | void kfd_debugfs_fini(void); | |
1153 | int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); | |
1154 | int pqm_debugfs_mqds(struct seq_file *m, void *data); | |
1155 | int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); | |
1156 | int dqm_debugfs_hqds(struct seq_file *m, void *data); | |
1157 | int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); | |
1158 | int pm_debugfs_runlist(struct seq_file *m, void *data); | |
1159 | ||
a29ec470 SL |
1160 | int kfd_debugfs_hang_hws(struct kfd_dev *dev); |
1161 | int pm_debugfs_hang_hws(struct packet_manager *pm); | |
1162 | int dqm_debugfs_execute_queues(struct device_queue_manager *dqm); | |
1163 | ||
851a645e FK |
1164 | #else |
1165 | ||
1166 | static inline void kfd_debugfs_init(void) {} | |
1167 | static inline void kfd_debugfs_fini(void) {} | |
1168 | ||
1169 | #endif | |
1170 | ||
4a488a7a | 1171 | #endif |