[linux-2.6-block.git] / drivers / gpu / drm / amd / amdkfd / kfd_mqd_manager_cik.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/printk.h>
#include <linux/slab.h>
#include <linux/mm_types.h>

#include "kfd_priv.h"
#include "kfd_mqd_manager.h"
#include "cik_regs.h"
#include "cik_structs.h"
#include "oss/oss_2_4_sh_mask.h"

static inline struct cik_mqd *get_mqd(void *mqd)
{
	return (struct cik_mqd *)mqd;
}

static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
{
	return (struct cik_sdma_rlc_registers *)mqd;
}

static void update_cu_mask(struct mqd_manager *mm, void *mqd,
			struct queue_properties *q)
{
	struct cik_mqd *m;
	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */

	if (q->cu_mask_count == 0)
		return;

	mqd_symmetrically_map_cu_mask(mm,
		q->cu_mask, q->cu_mask_count, se_mask);

	m = get_mqd(mqd);
	m->compute_static_thread_mgmt_se0 = se_mask[0];
	m->compute_static_thread_mgmt_se1 = se_mask[1];
	m->compute_static_thread_mgmt_se2 = se_mask[2];
	m->compute_static_thread_mgmt_se3 = se_mask[3];

	pr_debug("Update cu mask to %#x %#x %#x %#x\n",
		m->compute_static_thread_mgmt_se0,
		m->compute_static_thread_mgmt_se1,
		m->compute_static_thread_mgmt_se2,
		m->compute_static_thread_mgmt_se3);
}

static void set_priority(struct cik_mqd *m, struct queue_properties *q)
{
	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
	m->cp_hqd_queue_priority = q->priority;
}

static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
					struct queue_properties *q)
{
	struct kfd_mem_obj *mqd_mem_obj;

	if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd),
			&mqd_mem_obj))
		return NULL;

	return mqd_mem_obj;
}

static void init_mqd(struct mqd_manager *mm, void **mqd,
		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
		struct queue_properties *q)
{
	uint64_t addr;
	struct cik_mqd *m;

	m = (struct cik_mqd *) mqd_mem_obj->cpu_ptr;
	addr = mqd_mem_obj->gpu_addr;

	memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));

	m->header = 0xC0310800;
	m->compute_pipelinestat_enable = 1;
	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;

	/*
	 * Make sure to use the last queue state saved on mqd when the cp
	 * reassigns the queue, so when queue is switched on/off (e.g over
	 * subscription or quantum timeout) the context will be consistent
	 */
	m->cp_hqd_persistent_state =
				DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ;

	m->cp_mqd_control             = MQD_CONTROL_PRIV_STATE_EN;
	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);

	m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS |
				QUANTUM_DURATION(10);

	/*
	 * Pipe Priority
	 * Identifies the pipe relative priority when this queue is connected
	 * to the pipeline. The pipe priority is against the GFX pipe and HP3D.
	 * In KFD we are using a fixed pipe priority set to CS_MEDIUM.
	 * 0 = CS_LOW (typically below GFX)
	 * 1 = CS_MEDIUM (typically between HP3D and GFX
	 * 2 = CS_HIGH (typically above HP3D)
	 */
	set_priority(m, q);

	if (q->format == KFD_QUEUE_FORMAT_AQL)
		m->cp_hqd_iq_rptr = AQL_ENABLE;

	*mqd = m;
	if (gart_addr)
		*gart_addr = addr;
	mm->update_mqd(mm, m, q);
}

static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
			struct queue_properties *q)
{
	struct cik_sdma_rlc_registers *m;

	m = (struct cik_sdma_rlc_registers *) mqd_mem_obj->cpu_ptr;

	memset(m, 0, sizeof(struct cik_sdma_rlc_registers));

	*mqd = m;
	if (gart_addr)
		*gart_addr = mqd_mem_obj->gpu_addr;

	mm->update_mqd(mm, m, q);
}

static void free_mqd(struct mqd_manager *mm, void *mqd,
			struct kfd_mem_obj *mqd_mem_obj)
{
	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
}


static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id,
		    uint32_t queue_id, struct queue_properties *p,
		    struct mm_struct *mms)
{
	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
	uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);

	return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
					  (uint32_t __user *)p->write_ptr,
					  wptr_shift, wptr_mask, mms);
}

static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
			 uint32_t pipe_id, uint32_t queue_id,
			 struct queue_properties *p, struct mm_struct *mms)
{
	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
					       (uint32_t __user *)p->write_ptr,
					       mms);
}

static void __update_mqd(struct mqd_manager *mm, void *mqd,
			struct queue_properties *q, unsigned int atc_bit)
{
	struct cik_mqd *m;

	m = get_mqd(mqd);
	m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
				DEFAULT_MIN_AVAIL_SIZE;
	m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE;
	if (atc_bit) {
		m->cp_hqd_pq_control |= PQ_ATC_EN;
		m->cp_hqd_ib_control |= IB_ATC_EN;
	}

	/*
	 * Calculating queue size which is log base 2 of actual queue size -1
	 * dwords and another -1 for ffs
	 */
	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
	m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);

	m->cp_hqd_vmid = q->vmid;

	if (q->format == KFD_QUEUE_FORMAT_AQL)
		m->cp_hqd_pq_control |= NO_UPDATE_RPTR;

	update_cu_mask(mm, mqd, q);
	set_priority(m, q);

	q->is_active = QUEUE_IS_ACTIVE(*q);
}

static void update_mqd(struct mqd_manager *mm, void *mqd,
			struct queue_properties *q)
{
	__update_mqd(mm, mqd, q, 1);
}

static uint32_t read_doorbell_id(void *mqd)
{
	struct cik_mqd *m = (struct cik_mqd *)mqd;

	return m->queue_doorbell_id0;
}

static void update_mqd_hawaii(struct mqd_manager *mm, void *mqd,
			struct queue_properties *q)
{
	__update_mqd(mm, mqd, q, 0);
}

static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
				struct queue_properties *q)
{
	struct cik_sdma_rlc_registers *m;

	m = get_sdma_mqd(mqd);
	m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
			<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
			q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
			1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
			6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;

	m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8);
	m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);
	m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
	m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
	m->sdma_rlc_doorbell =
		q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;

	m->sdma_rlc_virtual_addr = q->sdma_vm_addr;

	m->sdma_engine_id = q->sdma_engine_id;
	m->sdma_queue_id = q->sdma_queue_id;

	q->is_active = QUEUE_IS_ACTIVE(*q);
}

static int destroy_mqd(struct mqd_manager *mm, void *mqd,
			enum kfd_preempt_type type,
			unsigned int timeout, uint32_t pipe_id,
			uint32_t queue_id)
{
	return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout,
					pipe_id, queue_id);
}

/*
 * preempt type here is ignored because there is only one way
 * to preempt sdma queue
 */
static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
				enum kfd_preempt_type type,
				unsigned int timeout, uint32_t pipe_id,
				uint32_t queue_id)
{
	return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
}

static bool is_occupied(struct mqd_manager *mm, void *mqd,
			uint64_t queue_address,	uint32_t pipe_id,
			uint32_t queue_id)
{

	return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address,
					pipe_id, queue_id);

}

static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
			uint64_t queue_address,	uint32_t pipe_id,
			uint32_t queue_id)
{
	return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
}

/*
 * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation.
 * The HIQ queue in Kaveri is using the same MQD structure as all the user mode
 * queues but with different initial values.
 */

static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
		struct queue_properties *q)
{
	init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
}

static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
				struct queue_properties *q)
{
	struct cik_mqd *m;

	m = get_mqd(mqd);
	m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE |
				DEFAULT_MIN_AVAIL_SIZE |
				PRIV_STATE |
				KMD_QUEUE;

	/*
	 * Calculating queue size which is log base 2 of actual queue
	 * size -1 dwords
	 */
	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
	m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);

	m->cp_hqd_vmid = q->vmid;

	q->is_active = QUEUE_IS_ACTIVE(*q);

	set_priority(m, q);
}

#if defined(CONFIG_DEBUG_FS)

static int debugfs_show_mqd(struct seq_file *m, void *data)
{
	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
		     data, sizeof(struct cik_mqd), false);
	return 0;
}

static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
{
	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
		     data, sizeof(struct cik_sdma_rlc_registers), false);
	return 0;
}

#endif


struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
		struct kfd_dev *dev)
{
	struct mqd_manager *mqd;

	if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
		return NULL;

	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
	if (!mqd)
		return NULL;

	mqd->dev = dev;

	switch (type) {
	case KFD_MQD_TYPE_CP:
		mqd->allocate_mqd = allocate_mqd;
		mqd->init_mqd = init_mqd;
		mqd->free_mqd = free_mqd;
		mqd->load_mqd = load_mqd;
		mqd->update_mqd = update_mqd;
		mqd->destroy_mqd = destroy_mqd;
		mqd->is_occupied = is_occupied;
		mqd->mqd_size = sizeof(struct cik_mqd);
#if defined(CONFIG_DEBUG_FS)
		mqd->debugfs_show_mqd = debugfs_show_mqd;
#endif
		break;
	case KFD_MQD_TYPE_HIQ:
		mqd->allocate_mqd = allocate_hiq_mqd;
		mqd->init_mqd = init_mqd_hiq;
		mqd->free_mqd = free_mqd_hiq_sdma;
		mqd->load_mqd = load_mqd;
		mqd->update_mqd = update_mqd_hiq;
		mqd->destroy_mqd = destroy_mqd;
		mqd->is_occupied = is_occupied;
		mqd->mqd_size = sizeof(struct cik_mqd);
#if defined(CONFIG_DEBUG_FS)
		mqd->debugfs_show_mqd = debugfs_show_mqd;
#endif
		mqd->read_doorbell_id = read_doorbell_id;
		break;
	case KFD_MQD_TYPE_DIQ:
		mqd->allocate_mqd = allocate_mqd;
		mqd->init_mqd = init_mqd_hiq;
		mqd->free_mqd = free_mqd;
		mqd->load_mqd = load_mqd;
		mqd->update_mqd = update_mqd_hiq;
		mqd->destroy_mqd = destroy_mqd;
		mqd->is_occupied = is_occupied;
		mqd->mqd_size = sizeof(struct cik_mqd);
#if defined(CONFIG_DEBUG_FS)
		mqd->debugfs_show_mqd = debugfs_show_mqd;
#endif
		break;
	case KFD_MQD_TYPE_SDMA:
		mqd->allocate_mqd = allocate_sdma_mqd;
		mqd->init_mqd = init_mqd_sdma;
		mqd->free_mqd = free_mqd_hiq_sdma;
		mqd->load_mqd = load_mqd_sdma;
		mqd->update_mqd = update_mqd_sdma;
		mqd->destroy_mqd = destroy_mqd_sdma;
		mqd->is_occupied = is_occupied_sdma;
		mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers);
#if defined(CONFIG_DEBUG_FS)
		mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
#endif
		break;
	default:
		kfree(mqd);
		return NULL;
	}

	return mqd;
}

struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
			struct kfd_dev *dev)
{
	struct mqd_manager *mqd;

	mqd = mqd_manager_init_cik(type, dev);
	if (!mqd)
		return NULL;
	if (type == KFD_MQD_TYPE_CP)
		mqd->update_mqd = update_mqd_hawaii;
	return mqd;
}
Commit	Line	Data
4b8f589b BG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include <linux/printk.h>
	25	#include <linux/slab.h>
589ee628 IM	26	#include <linux/mm_types.h>
589ee628 IM	27
4b8f589b BG	28	#include "kfd_priv.h"
	29	#include "kfd_mqd_manager.h"
	30	#include "cik_regs.h"
	31	#include "cik_structs.h"
3d30b28b	32	#include "oss/oss_2_4_sh_mask.h"
4b8f589b	33
4b8f589b BG	34	static inline struct cik_mqd get_mqd(void mqd)
	35	{
	36	return (struct cik_mqd *)mqd;
	37	}
	38
97b9ad12 FK	39	static inline struct cik_sdma_rlc_registers get_sdma_mqd(void mqd)
	40	{
	41	return (struct cik_sdma_rlc_registers *)mqd;
	42	}
	43
39e7f331 FK	44	static void update_cu_mask(struct mqd_manager mm, void mqd,
	45	struct queue_properties *q)
	46	{
	47	struct cik_mqd *m;
	48	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
	49
	50	if (q->cu_mask_count == 0)
	51	return;
	52
	53	mqd_symmetrically_map_cu_mask(mm,
	54	q->cu_mask, q->cu_mask_count, se_mask);
	55
	56	m = get_mqd(mqd);
	57	m->compute_static_thread_mgmt_se0 = se_mask[0];
	58	m->compute_static_thread_mgmt_se1 = se_mask[1];
	59	m->compute_static_thread_mgmt_se2 = se_mask[2];
	60	m->compute_static_thread_mgmt_se3 = se_mask[3];
	61
	62	pr_debug("Update cu mask to %#x %#x %#x %#x\n",
	63	m->compute_static_thread_mgmt_se0,
	64	m->compute_static_thread_mgmt_se1,
	65	m->compute_static_thread_mgmt_se2,
	66	m->compute_static_thread_mgmt_se3);
	67	}
	68
0ccbc7cd OZ	69	static void set_priority(struct cik_mqd m, struct queue_properties q)
	70	{
	71	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
	72	m->cp_hqd_queue_priority = q->priority;
	73	}
	74
d1f8f0d1 OZ	75	static struct kfd_mem_obj allocate_mqd(struct kfd_dev kfd,
	76	struct queue_properties *q)
	77	{
	78	struct kfd_mem_obj *mqd_mem_obj;
	79
	80	if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd),
	81	&mqd_mem_obj))
	82	return NULL;
	83
	84	return mqd_mem_obj;
	85	}
	86
8636e53c OZ	87	static void init_mqd(struct mqd_manager mm, void *mqd,
8636e53c OZ	88	struct kfd_mem_obj mqd_mem_obj, uint64_t gart_addr,
4b8f589b BG	89	struct queue_properties *q)
	90	{
	91	uint64_t addr;
	92	struct cik_mqd *m;
4b8f589b	93
8636e53c OZ	94	m = (struct cik_mqd *) mqd_mem_obj->cpu_ptr;
8636e53c OZ	95	addr = mqd_mem_obj->gpu_addr;
4b8f589b BG	96
	97	memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256));
	98
	99	m->header = 0xC0310800;
	100	m->compute_pipelinestat_enable = 1;
	101	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
	102	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
	103	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
	104	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
	105
	106	/*
	107	* Make sure to use the last queue state saved on mqd when the cp
	108	* reassigns the queue, so when queue is switched on/off (e.g over
	109	* subscription or quantum timeout) the context will be consistent
	110	*/
	111	m->cp_hqd_persistent_state =
	112	DEFAULT_CP_HQD_PERSISTENT_STATE \| PRELOAD_REQ;
	113
	114	m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN;
	115	m->cp_mqd_base_addr_lo = lower_32_bits(addr);
	116	m->cp_mqd_base_addr_hi = upper_32_bits(addr);
	117
4b8f589b BG	118	m->cp_hqd_quantum = QUANTUM_EN \| QUANTUM_SCALE_1MS \|
	119	QUANTUM_DURATION(10);
	120
	121	/*
	122	* Pipe Priority
	123	* Identifies the pipe relative priority when this queue is connected
	124	* to the pipeline. The pipe priority is against the GFX pipe and HP3D.
	125	* In KFD we are using a fixed pipe priority set to CS_MEDIUM.
	126	* 0 = CS_LOW (typically below GFX)
	127	* 1 = CS_MEDIUM (typically between HP3D and GFX
	128	* 2 = CS_HIGH (typically above HP3D)
	129	*/
0ccbc7cd	130	set_priority(m, q);
4b8f589b	131
d752f95e JC	132	if (q->format == KFD_QUEUE_FORMAT_AQL)
	133	m->cp_hqd_iq_rptr = AQL_ENABLE;
	134
4b8f589b	135	*mqd = m;
4eacc26b	136	if (gart_addr)
4b8f589b	137	*gart_addr = addr;
8636e53c	138	mm->update_mqd(mm, m, q);
4b8f589b BG	139	}
4b8f589b BG	140
8636e53c OZ	141	static void init_mqd_sdma(struct mqd_manager mm, void *mqd,
8636e53c OZ	142	struct kfd_mem_obj mqd_mem_obj, uint64_t gart_addr,
4b8f589b BG	143	struct queue_properties *q)
4b8f589b BG	144	{
4b8f589b BG	145	struct cik_sdma_rlc_registers *m;
4b8f589b BG	146
8636e53c	147	m = (struct cik_sdma_rlc_registers *) mqd_mem_obj->cpu_ptr;
4b8f589b BG	148
	149	memset(m, 0, sizeof(struct cik_sdma_rlc_registers));
	150
	151	*mqd = m;
4eacc26b	152	if (gart_addr)
8636e53c	153	*gart_addr = mqd_mem_obj->gpu_addr;
4b8f589b	154
8636e53c	155	mm->update_mqd(mm, m, q);
4b8f589b BG	156	}
4b8f589b BG	157
8636e53c	158	static void free_mqd(struct mqd_manager mm, void mqd,
4b8f589b BG	159	struct kfd_mem_obj *mqd_mem_obj)
4b8f589b BG	160	{
4b8f589b BG	161	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
	162	}
	163
4b8f589b BG	164
4b8f589b BG	165	static int load_mqd(struct mqd_manager mm, void mqd, uint32_t pipe_id,
70539bd7 FK	166	uint32_t queue_id, struct queue_properties *p,
70539bd7 FK	167	struct mm_struct *mms)
4b8f589b	168	{
70539bd7 FK	169	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
70539bd7 FK	170	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
6d566930	171	uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
70539bd7 FK	172
	173	return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
	174	(uint32_t __user *)p->write_ptr,
	175	wptr_shift, wptr_mask, mms);
4b8f589b BG	176	}
	177
	178	static int load_mqd_sdma(struct mqd_manager mm, void mqd,
70539bd7 FK	179	uint32_t pipe_id, uint32_t queue_id,
70539bd7 FK	180	struct queue_properties p, struct mm_struct mms)
4b8f589b	181	{
7ce66118 FK	182	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
	183	(uint32_t __user *)p->write_ptr,
	184	mms);
4b8f589b BG	185	}
4b8f589b BG	186
8636e53c	187	static void __update_mqd(struct mqd_manager mm, void mqd,
ee04955a	188	struct queue_properties *q, unsigned int atc_bit)
4b8f589b BG	189	{
	190	struct cik_mqd *m;
	191
4b8f589b BG	192	m = get_mqd(mqd);
4b8f589b BG	193	m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE \|
ee04955a FK	194	DEFAULT_MIN_AVAIL_SIZE;
	195	m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE;
	196	if (atc_bit) {
	197	m->cp_hqd_pq_control \|= PQ_ATC_EN;
	198	m->cp_hqd_ib_control \|= IB_ATC_EN;
	199	}
4b8f589b BG	200
	201	/*
	202	* Calculating queue size which is log base 2 of actual queue size -1
	203	* dwords and another -1 for ffs
	204	*/
115c8c41	205	m->cp_hqd_pq_control \|= order_base_2(q->queue_size / 4) - 1;
4b8f589b BG	206	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
	207	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
	208	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
	209	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
70539bd7	210	m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);
4b8f589b BG	211
	212	m->cp_hqd_vmid = q->vmid;
	213
8eabaf54	214	if (q->format == KFD_QUEUE_FORMAT_AQL)
4b8f589b	215	m->cp_hqd_pq_control \|= NO_UPDATE_RPTR;
4b8f589b	216
39e7f331	217	update_cu_mask(mm, mqd, q);
0ccbc7cd	218	set_priority(m, q);
39e7f331	219
bb2d2128	220	q->is_active = QUEUE_IS_ACTIVE(*q);
4b8f589b BG	221	}
4b8f589b BG	222
8636e53c	223	static void update_mqd(struct mqd_manager mm, void mqd,
ee04955a FK	224	struct queue_properties *q)
ee04955a FK	225	{
8636e53c	226	__update_mqd(mm, mqd, q, 1);
ee04955a FK	227	}
ee04955a FK	228
51a0f459 OZ	229	static uint32_t read_doorbell_id(void *mqd)
	230	{
	231	struct cik_mqd m = (struct cik_mqd )mqd;
	232
	233	return m->queue_doorbell_id0;
	234	}
	235
8636e53c	236	static void update_mqd_hawaii(struct mqd_manager mm, void mqd,
ee04955a FK	237	struct queue_properties *q)
ee04955a FK	238	{
8636e53c	239	__update_mqd(mm, mqd, q, 0);
ee04955a FK	240	}
ee04955a FK	241
8636e53c	242	static void update_mqd_sdma(struct mqd_manager mm, void mqd,
4b8f589b BG	243	struct queue_properties *q)
	244	{
	245	struct cik_sdma_rlc_registers *m;
	246
4b8f589b	247	m = get_sdma_mqd(mqd);
115c8c41	248	m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
d12fb13f	249	<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT \|
3d30b28b OG	250	q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT \|
	251	1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT \|
	252	6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
4b8f589b BG	253
	254	m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8);
	255	m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8);
	256	m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
	257	m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
bba9662d JC	258	m->sdma_rlc_doorbell =
bba9662d JC	259	q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
3d30b28b	260
4b8f589b BG	261	m->sdma_rlc_virtual_addr = q->sdma_vm_addr;
	262
	263	m->sdma_engine_id = q->sdma_engine_id;
	264	m->sdma_queue_id = q->sdma_queue_id;
	265
bb2d2128	266	q->is_active = QUEUE_IS_ACTIVE(*q);
4b8f589b BG	267	}
	268
	269	static int destroy_mqd(struct mqd_manager mm, void mqd,
	270	enum kfd_preempt_type type,
	271	unsigned int timeout, uint32_t pipe_id,
	272	uint32_t queue_id)
	273	{
70539bd7	274	return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout,
4b8f589b BG	275	pipe_id, queue_id);
	276	}
	277
	278	/*
	279	* preempt type here is ignored because there is only one way
	280	* to preempt sdma queue
	281	*/
	282	static int destroy_mqd_sdma(struct mqd_manager mm, void mqd,
	283	enum kfd_preempt_type type,
	284	unsigned int timeout, uint32_t pipe_id,
	285	uint32_t queue_id)
	286	{
cea405b1	287	return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
4b8f589b BG	288	}
	289
	290	static bool is_occupied(struct mqd_manager mm, void mqd,
	291	uint64_t queue_address, uint32_t pipe_id,
	292	uint32_t queue_id)
	293	{
	294
cea405b1	295	return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address,
4b8f589b BG	296	pipe_id, queue_id);
	297
	298	}
	299
	300	static bool is_occupied_sdma(struct mqd_manager mm, void mqd,
	301	uint64_t queue_address, uint32_t pipe_id,
	302	uint32_t queue_id)
	303	{
cea405b1	304	return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
4b8f589b BG	305	}
	306
	307	/*
	308	* HIQ MQD Implementation, concrete implementation for HIQ MQD implementation.
	309	* The HIQ queue in Kaveri is using the same MQD structure as all the user mode
	310	* queues but with different initial values.
	311	*/
	312
8636e53c OZ	313	static void init_mqd_hiq(struct mqd_manager mm, void *mqd,
8636e53c OZ	314	struct kfd_mem_obj mqd_mem_obj, uint64_t gart_addr,
4b8f589b BG	315	struct queue_properties *q)
4b8f589b BG	316	{
8636e53c	317	init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
4b8f589b BG	318	}
4b8f589b BG	319
8636e53c	320	static void update_mqd_hiq(struct mqd_manager mm, void mqd,
4b8f589b BG	321	struct queue_properties *q)
	322	{
	323	struct cik_mqd *m;
	324
4b8f589b BG	325	m = get_mqd(mqd);
	326	m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE \|
	327	DEFAULT_MIN_AVAIL_SIZE \|
	328	PRIV_STATE \|
	329	KMD_QUEUE;
	330
	331	/*
	332	* Calculating queue size which is log base 2 of actual queue
	333	* size -1 dwords
	334	*/
115c8c41	335	m->cp_hqd_pq_control \|= order_base_2(q->queue_size / 4) - 1;
4b8f589b BG	336	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
	337	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
	338	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
	339	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
bba9662d	340	m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off);
4b8f589b BG	341
	342	m->cp_hqd_vmid = q->vmid;
	343
bb2d2128	344	q->is_active = QUEUE_IS_ACTIVE(*q);
4b8f589b	345
0ccbc7cd	346	set_priority(m, q);
4b8f589b BG	347	}
4b8f589b BG	348
851a645e FK	349	#if defined(CONFIG_DEBUG_FS)
	350
	351	static int debugfs_show_mqd(struct seq_file m, void data)
	352	{
	353	seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
	354	data, sizeof(struct cik_mqd), false);
	355	return 0;
	356	}
	357
	358	static int debugfs_show_mqd_sdma(struct seq_file m, void data)
	359	{
	360	seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
	361	data, sizeof(struct cik_sdma_rlc_registers), false);
	362	return 0;
	363	}
	364
	365	#endif
	366
4b8f589b BG	367
	368	struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
	369	struct kfd_dev *dev)
	370	{
	371	struct mqd_manager *mqd;
	372
32fa8219 FK	373	if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
32fa8219 FK	374	return NULL;
4b8f589b	375
1cd106ec	376	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
4b8f589b BG	377	if (!mqd)
	378	return NULL;
	379
	380	mqd->dev = dev;
	381
	382	switch (type) {
	383	case KFD_MQD_TYPE_CP:
8636e53c	384	mqd->allocate_mqd = allocate_mqd;
4b8f589b	385	mqd->init_mqd = init_mqd;
8636e53c	386	mqd->free_mqd = free_mqd;
4b8f589b BG	387	mqd->load_mqd = load_mqd;
	388	mqd->update_mqd = update_mqd;
	389	mqd->destroy_mqd = destroy_mqd;
	390	mqd->is_occupied = is_occupied;
6c6cde55	391	mqd->mqd_size = sizeof(struct cik_mqd);
851a645e FK	392	#if defined(CONFIG_DEBUG_FS)
	393	mqd->debugfs_show_mqd = debugfs_show_mqd;
	394	#endif
4b8f589b BG	395	break;
4b8f589b BG	396	case KFD_MQD_TYPE_HIQ:
8636e53c	397	mqd->allocate_mqd = allocate_hiq_mqd;
4b8f589b	398	mqd->init_mqd = init_mqd_hiq;
8636e53c	399	mqd->free_mqd = free_mqd_hiq_sdma;
4b8f589b BG	400	mqd->load_mqd = load_mqd;
	401	mqd->update_mqd = update_mqd_hiq;
	402	mqd->destroy_mqd = destroy_mqd;
	403	mqd->is_occupied = is_occupied;
6c6cde55	404	mqd->mqd_size = sizeof(struct cik_mqd);
851a645e FK	405	#if defined(CONFIG_DEBUG_FS)
851a645e FK	406	mqd->debugfs_show_mqd = debugfs_show_mqd;
59f650a0	407	#endif
51a0f459	408	mqd->read_doorbell_id = read_doorbell_id;
59f650a0 OZ	409	break;
59f650a0 OZ	410	case KFD_MQD_TYPE_DIQ:
7633c5e0	411	mqd->allocate_mqd = allocate_mqd;
59f650a0	412	mqd->init_mqd = init_mqd_hiq;
8636e53c	413	mqd->free_mqd = free_mqd;
59f650a0 OZ	414	mqd->load_mqd = load_mqd;
	415	mqd->update_mqd = update_mqd_hiq;
	416	mqd->destroy_mqd = destroy_mqd;
	417	mqd->is_occupied = is_occupied;
6c6cde55	418	mqd->mqd_size = sizeof(struct cik_mqd);
59f650a0 OZ	419	#if defined(CONFIG_DEBUG_FS)
59f650a0 OZ	420	mqd->debugfs_show_mqd = debugfs_show_mqd;
851a645e	421	#endif
4b8f589b BG	422	break;
4b8f589b BG	423	case KFD_MQD_TYPE_SDMA:
8636e53c	424	mqd->allocate_mqd = allocate_sdma_mqd;
4b8f589b	425	mqd->init_mqd = init_mqd_sdma;
8636e53c	426	mqd->free_mqd = free_mqd_hiq_sdma;
4b8f589b BG	427	mqd->load_mqd = load_mqd_sdma;
	428	mqd->update_mqd = update_mqd_sdma;
	429	mqd->destroy_mqd = destroy_mqd_sdma;
	430	mqd->is_occupied = is_occupied_sdma;
6c6cde55	431	mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers);
851a645e FK	432	#if defined(CONFIG_DEBUG_FS)
	433	mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
	434	#endif
4b8f589b BG	435	break;
	436	default:
	437	kfree(mqd);
	438	return NULL;
	439	}
	440
	441	return mqd;
	442	}
	443
ee04955a FK	444	struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type,
	445	struct kfd_dev *dev)
	446	{
	447	struct mqd_manager *mqd;
	448
	449	mqd = mqd_manager_init_cik(type, dev);
	450	if (!mqd)
	451	return NULL;
d7c0b047	452	if (type == KFD_MQD_TYPE_CP)
ee04955a FK	453	mqd->update_mqd = update_mqd_hawaii;
	454	return mqd;
	455	}