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aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/module.h> | |
26 | #include "drmP.h" | |
27 | #include "amdgpu.h" | |
28 | #include "amdgpu_atombios.h" | |
29 | #include "amdgpu_ih.h" | |
30 | #include "amdgpu_uvd.h" | |
31 | #include "amdgpu_vce.h" | |
32 | #include "amdgpu_ucode.h" | |
33 | #include "atom.h" | |
d0dd7f0c | 34 | #include "amd_pcie.h" |
aaa36a97 AD |
35 | |
36 | #include "gmc/gmc_8_1_d.h" | |
37 | #include "gmc/gmc_8_1_sh_mask.h" | |
38 | ||
39 | #include "oss/oss_3_0_d.h" | |
40 | #include "oss/oss_3_0_sh_mask.h" | |
41 | ||
42 | #include "bif/bif_5_0_d.h" | |
43 | #include "bif/bif_5_0_sh_mask.h" | |
44 | ||
45 | #include "gca/gfx_8_0_d.h" | |
46 | #include "gca/gfx_8_0_sh_mask.h" | |
47 | ||
48 | #include "smu/smu_7_1_1_d.h" | |
49 | #include "smu/smu_7_1_1_sh_mask.h" | |
50 | ||
51 | #include "uvd/uvd_5_0_d.h" | |
52 | #include "uvd/uvd_5_0_sh_mask.h" | |
53 | ||
54 | #include "vce/vce_3_0_d.h" | |
55 | #include "vce/vce_3_0_sh_mask.h" | |
56 | ||
57 | #include "dce/dce_10_0_d.h" | |
58 | #include "dce/dce_10_0_sh_mask.h" | |
59 | ||
60 | #include "vid.h" | |
61 | #include "vi.h" | |
62 | #include "vi_dpm.h" | |
63 | #include "gmc_v8_0.h" | |
429c45de | 64 | #include "gmc_v7_0.h" |
aaa36a97 AD |
65 | #include "gfx_v8_0.h" |
66 | #include "sdma_v2_4.h" | |
67 | #include "sdma_v3_0.h" | |
68 | #include "dce_v10_0.h" | |
69 | #include "dce_v11_0.h" | |
70 | #include "iceland_ih.h" | |
71 | #include "tonga_ih.h" | |
72 | #include "cz_ih.h" | |
73 | #include "uvd_v5_0.h" | |
74 | #include "uvd_v6_0.h" | |
75 | #include "vce_v3_0.h" | |
1f7371b2 | 76 | #include "amdgpu_powerplay.h" |
a8fe58ce MB |
77 | #if defined(CONFIG_DRM_AMD_ACP) |
78 | #include "amdgpu_acp.h" | |
79 | #endif | |
e9ed3a67 | 80 | #include "dce_virtual.h" |
aaa36a97 | 81 | |
f8951068 FC |
82 | MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); |
83 | MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); | |
84 | MODULE_FIRMWARE("amdgpu/polaris11_smc.bin"); | |
85 | MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin"); | |
86 | ||
aaa36a97 AD |
87 | /* |
88 | * Indirect registers accessor | |
89 | */ | |
90 | static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) | |
91 | { | |
92 | unsigned long flags; | |
93 | u32 r; | |
94 | ||
95 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
96 | WREG32(mmPCIE_INDEX, reg); | |
97 | (void)RREG32(mmPCIE_INDEX); | |
98 | r = RREG32(mmPCIE_DATA); | |
99 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
100 | return r; | |
101 | } | |
102 | ||
103 | static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
104 | { | |
105 | unsigned long flags; | |
106 | ||
107 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
108 | WREG32(mmPCIE_INDEX, reg); | |
109 | (void)RREG32(mmPCIE_INDEX); | |
110 | WREG32(mmPCIE_DATA, v); | |
111 | (void)RREG32(mmPCIE_DATA); | |
112 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
113 | } | |
114 | ||
115 | static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) | |
116 | { | |
117 | unsigned long flags; | |
118 | u32 r; | |
119 | ||
120 | spin_lock_irqsave(&adev->smc_idx_lock, flags); | |
121 | WREG32(mmSMC_IND_INDEX_0, (reg)); | |
122 | r = RREG32(mmSMC_IND_DATA_0); | |
123 | spin_unlock_irqrestore(&adev->smc_idx_lock, flags); | |
124 | return r; | |
125 | } | |
126 | ||
127 | static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
128 | { | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&adev->smc_idx_lock, flags); | |
132 | WREG32(mmSMC_IND_INDEX_0, (reg)); | |
133 | WREG32(mmSMC_IND_DATA_0, (v)); | |
134 | spin_unlock_irqrestore(&adev->smc_idx_lock, flags); | |
135 | } | |
136 | ||
7b92cdbf AD |
137 | /* smu_8_0_d.h */ |
138 | #define mmMP0PUB_IND_INDEX 0x180 | |
139 | #define mmMP0PUB_IND_DATA 0x181 | |
140 | ||
141 | static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) | |
142 | { | |
143 | unsigned long flags; | |
144 | u32 r; | |
145 | ||
146 | spin_lock_irqsave(&adev->smc_idx_lock, flags); | |
147 | WREG32(mmMP0PUB_IND_INDEX, (reg)); | |
148 | r = RREG32(mmMP0PUB_IND_DATA); | |
149 | spin_unlock_irqrestore(&adev->smc_idx_lock, flags); | |
150 | return r; | |
151 | } | |
152 | ||
153 | static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
154 | { | |
155 | unsigned long flags; | |
156 | ||
157 | spin_lock_irqsave(&adev->smc_idx_lock, flags); | |
158 | WREG32(mmMP0PUB_IND_INDEX, (reg)); | |
159 | WREG32(mmMP0PUB_IND_DATA, (v)); | |
160 | spin_unlock_irqrestore(&adev->smc_idx_lock, flags); | |
161 | } | |
162 | ||
aaa36a97 AD |
163 | static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) |
164 | { | |
165 | unsigned long flags; | |
166 | u32 r; | |
167 | ||
168 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); | |
169 | WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); | |
170 | r = RREG32(mmUVD_CTX_DATA); | |
171 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); | |
172 | return r; | |
173 | } | |
174 | ||
175 | static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
176 | { | |
177 | unsigned long flags; | |
178 | ||
179 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); | |
180 | WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); | |
181 | WREG32(mmUVD_CTX_DATA, (v)); | |
182 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); | |
183 | } | |
184 | ||
185 | static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) | |
186 | { | |
187 | unsigned long flags; | |
188 | u32 r; | |
189 | ||
190 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
191 | WREG32(mmDIDT_IND_INDEX, (reg)); | |
192 | r = RREG32(mmDIDT_IND_DATA); | |
193 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
194 | return r; | |
195 | } | |
196 | ||
197 | static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
198 | { | |
199 | unsigned long flags; | |
200 | ||
201 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
202 | WREG32(mmDIDT_IND_INDEX, (reg)); | |
203 | WREG32(mmDIDT_IND_DATA, (v)); | |
204 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
205 | } | |
206 | ||
ccdbb20a RZ |
207 | static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) |
208 | { | |
209 | unsigned long flags; | |
210 | u32 r; | |
211 | ||
212 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); | |
213 | WREG32(mmGC_CAC_IND_INDEX, (reg)); | |
214 | r = RREG32(mmGC_CAC_IND_DATA); | |
215 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); | |
216 | return r; | |
217 | } | |
218 | ||
219 | static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
220 | { | |
221 | unsigned long flags; | |
222 | ||
223 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); | |
224 | WREG32(mmGC_CAC_IND_INDEX, (reg)); | |
225 | WREG32(mmGC_CAC_IND_DATA, (v)); | |
226 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); | |
227 | } | |
228 | ||
229 | ||
aaa36a97 AD |
230 | static const u32 tonga_mgcg_cgcg_init[] = |
231 | { | |
232 | mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, | |
233 | mmPCIE_INDEX, 0xffffffff, 0x0140001c, | |
234 | mmPCIE_DATA, 0x000f0000, 0x00000000, | |
235 | mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, | |
236 | mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, | |
aaa36a97 AD |
237 | mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, |
238 | mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, | |
239 | }; | |
240 | ||
48299f95 DZ |
241 | static const u32 fiji_mgcg_cgcg_init[] = |
242 | { | |
243 | mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, | |
244 | mmPCIE_INDEX, 0xffffffff, 0x0140001c, | |
245 | mmPCIE_DATA, 0x000f0000, 0x00000000, | |
246 | mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, | |
247 | mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, | |
248 | mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, | |
249 | mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, | |
250 | }; | |
251 | ||
aaa36a97 AD |
252 | static const u32 iceland_mgcg_cgcg_init[] = |
253 | { | |
254 | mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2, | |
255 | mmPCIE_DATA, 0x000f0000, 0x00000000, | |
256 | mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0, | |
257 | mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, | |
258 | mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, | |
259 | }; | |
260 | ||
261 | static const u32 cz_mgcg_cgcg_init[] = | |
262 | { | |
263 | mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, | |
264 | mmPCIE_INDEX, 0xffffffff, 0x0140001c, | |
265 | mmPCIE_DATA, 0x000f0000, 0x00000000, | |
aaa36a97 AD |
266 | mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, |
267 | mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, | |
268 | }; | |
269 | ||
39bb0c92 SL |
270 | static const u32 stoney_mgcg_cgcg_init[] = |
271 | { | |
272 | mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, | |
273 | mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, | |
274 | mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, | |
275 | }; | |
276 | ||
aaa36a97 AD |
277 | static void vi_init_golden_registers(struct amdgpu_device *adev) |
278 | { | |
279 | /* Some of the registers might be dependent on GRBM_GFX_INDEX */ | |
280 | mutex_lock(&adev->grbm_idx_mutex); | |
281 | ||
282 | switch (adev->asic_type) { | |
283 | case CHIP_TOPAZ: | |
284 | amdgpu_program_register_sequence(adev, | |
285 | iceland_mgcg_cgcg_init, | |
286 | (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); | |
287 | break; | |
48299f95 DZ |
288 | case CHIP_FIJI: |
289 | amdgpu_program_register_sequence(adev, | |
290 | fiji_mgcg_cgcg_init, | |
291 | (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); | |
292 | break; | |
aaa36a97 AD |
293 | case CHIP_TONGA: |
294 | amdgpu_program_register_sequence(adev, | |
295 | tonga_mgcg_cgcg_init, | |
296 | (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); | |
297 | break; | |
298 | case CHIP_CARRIZO: | |
299 | amdgpu_program_register_sequence(adev, | |
300 | cz_mgcg_cgcg_init, | |
301 | (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); | |
302 | break; | |
39bb0c92 SL |
303 | case CHIP_STONEY: |
304 | amdgpu_program_register_sequence(adev, | |
305 | stoney_mgcg_cgcg_init, | |
306 | (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); | |
307 | break; | |
2cc0c0b5 FC |
308 | case CHIP_POLARIS11: |
309 | case CHIP_POLARIS10: | |
aaa36a97 AD |
310 | default: |
311 | break; | |
312 | } | |
313 | mutex_unlock(&adev->grbm_idx_mutex); | |
314 | } | |
315 | ||
316 | /** | |
317 | * vi_get_xclk - get the xclk | |
318 | * | |
319 | * @adev: amdgpu_device pointer | |
320 | * | |
321 | * Returns the reference clock used by the gfx engine | |
322 | * (VI). | |
323 | */ | |
324 | static u32 vi_get_xclk(struct amdgpu_device *adev) | |
325 | { | |
326 | u32 reference_clock = adev->clock.spll.reference_freq; | |
327 | u32 tmp; | |
328 | ||
2f7d10b3 | 329 | if (adev->flags & AMD_IS_APU) |
aaa36a97 AD |
330 | return reference_clock; |
331 | ||
332 | tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); | |
333 | if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) | |
334 | return 1000; | |
335 | ||
336 | tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); | |
337 | if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) | |
338 | return reference_clock / 4; | |
339 | ||
340 | return reference_clock; | |
341 | } | |
342 | ||
343 | /** | |
344 | * vi_srbm_select - select specific register instances | |
345 | * | |
346 | * @adev: amdgpu_device pointer | |
347 | * @me: selected ME (micro engine) | |
348 | * @pipe: pipe | |
349 | * @queue: queue | |
350 | * @vmid: VMID | |
351 | * | |
352 | * Switches the currently active registers instances. Some | |
353 | * registers are instanced per VMID, others are instanced per | |
354 | * me/pipe/queue combination. | |
355 | */ | |
356 | void vi_srbm_select(struct amdgpu_device *adev, | |
357 | u32 me, u32 pipe, u32 queue, u32 vmid) | |
358 | { | |
359 | u32 srbm_gfx_cntl = 0; | |
360 | srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe); | |
361 | srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); | |
362 | srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid); | |
363 | srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue); | |
364 | WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); | |
365 | } | |
366 | ||
367 | static void vi_vga_set_state(struct amdgpu_device *adev, bool state) | |
368 | { | |
369 | /* todo */ | |
370 | } | |
371 | ||
372 | static bool vi_read_disabled_bios(struct amdgpu_device *adev) | |
373 | { | |
374 | u32 bus_cntl; | |
375 | u32 d1vga_control = 0; | |
376 | u32 d2vga_control = 0; | |
377 | u32 vga_render_control = 0; | |
378 | u32 rom_cntl; | |
379 | bool r; | |
380 | ||
381 | bus_cntl = RREG32(mmBUS_CNTL); | |
382 | if (adev->mode_info.num_crtc) { | |
383 | d1vga_control = RREG32(mmD1VGA_CONTROL); | |
384 | d2vga_control = RREG32(mmD2VGA_CONTROL); | |
385 | vga_render_control = RREG32(mmVGA_RENDER_CONTROL); | |
386 | } | |
387 | rom_cntl = RREG32_SMC(ixROM_CNTL); | |
388 | ||
389 | /* enable the rom */ | |
390 | WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); | |
391 | if (adev->mode_info.num_crtc) { | |
392 | /* Disable VGA mode */ | |
393 | WREG32(mmD1VGA_CONTROL, | |
394 | (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | | |
395 | D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); | |
396 | WREG32(mmD2VGA_CONTROL, | |
397 | (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK | | |
398 | D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK))); | |
399 | WREG32(mmVGA_RENDER_CONTROL, | |
400 | (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); | |
401 | } | |
402 | WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); | |
403 | ||
404 | r = amdgpu_read_bios(adev); | |
405 | ||
406 | /* restore regs */ | |
407 | WREG32(mmBUS_CNTL, bus_cntl); | |
408 | if (adev->mode_info.num_crtc) { | |
409 | WREG32(mmD1VGA_CONTROL, d1vga_control); | |
410 | WREG32(mmD2VGA_CONTROL, d2vga_control); | |
411 | WREG32(mmVGA_RENDER_CONTROL, vga_render_control); | |
412 | } | |
413 | WREG32_SMC(ixROM_CNTL, rom_cntl); | |
414 | return r; | |
415 | } | |
95addb2a AD |
416 | |
417 | static bool vi_read_bios_from_rom(struct amdgpu_device *adev, | |
418 | u8 *bios, u32 length_bytes) | |
419 | { | |
420 | u32 *dw_ptr; | |
421 | unsigned long flags; | |
422 | u32 i, length_dw; | |
423 | ||
424 | if (bios == NULL) | |
425 | return false; | |
426 | if (length_bytes == 0) | |
427 | return false; | |
428 | /* APU vbios image is part of sbios image */ | |
429 | if (adev->flags & AMD_IS_APU) | |
430 | return false; | |
431 | ||
432 | dw_ptr = (u32 *)bios; | |
433 | length_dw = ALIGN(length_bytes, 4) / 4; | |
434 | /* take the smc lock since we are using the smc index */ | |
435 | spin_lock_irqsave(&adev->smc_idx_lock, flags); | |
436 | /* set rom index to 0 */ | |
437 | WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); | |
438 | WREG32(mmSMC_IND_DATA_0, 0); | |
439 | /* set index to data for continous read */ | |
440 | WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); | |
441 | for (i = 0; i < length_dw; i++) | |
442 | dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); | |
443 | spin_unlock_irqrestore(&adev->smc_idx_lock, flags); | |
444 | ||
445 | return true; | |
446 | } | |
447 | ||
048765ad AR |
448 | static u32 vi_get_virtual_caps(struct amdgpu_device *adev) |
449 | { | |
450 | u32 caps = 0; | |
451 | u32 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); | |
452 | ||
453 | if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE)) | |
454 | caps |= AMDGPU_VIRT_CAPS_SRIOV_EN; | |
455 | ||
456 | if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER)) | |
457 | caps |= AMDGPU_VIRT_CAPS_IS_VF; | |
458 | ||
459 | return caps; | |
460 | } | |
461 | ||
eca2240f | 462 | static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { |
aaa36a97 AD |
463 | {mmGB_MACROTILE_MODE7, true}, |
464 | }; | |
465 | ||
eca2240f | 466 | static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { |
aaa36a97 AD |
467 | {mmGB_TILE_MODE7, true}, |
468 | {mmGB_TILE_MODE12, true}, | |
469 | {mmGB_TILE_MODE17, true}, | |
470 | {mmGB_TILE_MODE23, true}, | |
471 | {mmGB_MACROTILE_MODE7, true}, | |
472 | }; | |
473 | ||
eca2240f | 474 | static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { |
aaa36a97 | 475 | {mmGRBM_STATUS, false}, |
c7890fea MO |
476 | {mmGRBM_STATUS2, false}, |
477 | {mmGRBM_STATUS_SE0, false}, | |
478 | {mmGRBM_STATUS_SE1, false}, | |
479 | {mmGRBM_STATUS_SE2, false}, | |
480 | {mmGRBM_STATUS_SE3, false}, | |
481 | {mmSRBM_STATUS, false}, | |
482 | {mmSRBM_STATUS2, false}, | |
483 | {mmSRBM_STATUS3, false}, | |
484 | {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false}, | |
485 | {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false}, | |
486 | {mmCP_STAT, false}, | |
487 | {mmCP_STALLED_STAT1, false}, | |
488 | {mmCP_STALLED_STAT2, false}, | |
489 | {mmCP_STALLED_STAT3, false}, | |
490 | {mmCP_CPF_BUSY_STAT, false}, | |
491 | {mmCP_CPF_STALLED_STAT1, false}, | |
492 | {mmCP_CPF_STATUS, false}, | |
493 | {mmCP_CPC_BUSY_STAT, false}, | |
494 | {mmCP_CPC_STALLED_STAT1, false}, | |
495 | {mmCP_CPC_STATUS, false}, | |
aaa36a97 AD |
496 | {mmGB_ADDR_CONFIG, false}, |
497 | {mmMC_ARB_RAMCFG, false}, | |
498 | {mmGB_TILE_MODE0, false}, | |
499 | {mmGB_TILE_MODE1, false}, | |
500 | {mmGB_TILE_MODE2, false}, | |
501 | {mmGB_TILE_MODE3, false}, | |
502 | {mmGB_TILE_MODE4, false}, | |
503 | {mmGB_TILE_MODE5, false}, | |
504 | {mmGB_TILE_MODE6, false}, | |
505 | {mmGB_TILE_MODE7, false}, | |
506 | {mmGB_TILE_MODE8, false}, | |
507 | {mmGB_TILE_MODE9, false}, | |
508 | {mmGB_TILE_MODE10, false}, | |
509 | {mmGB_TILE_MODE11, false}, | |
510 | {mmGB_TILE_MODE12, false}, | |
511 | {mmGB_TILE_MODE13, false}, | |
512 | {mmGB_TILE_MODE14, false}, | |
513 | {mmGB_TILE_MODE15, false}, | |
514 | {mmGB_TILE_MODE16, false}, | |
515 | {mmGB_TILE_MODE17, false}, | |
516 | {mmGB_TILE_MODE18, false}, | |
517 | {mmGB_TILE_MODE19, false}, | |
518 | {mmGB_TILE_MODE20, false}, | |
519 | {mmGB_TILE_MODE21, false}, | |
520 | {mmGB_TILE_MODE22, false}, | |
521 | {mmGB_TILE_MODE23, false}, | |
522 | {mmGB_TILE_MODE24, false}, | |
523 | {mmGB_TILE_MODE25, false}, | |
524 | {mmGB_TILE_MODE26, false}, | |
525 | {mmGB_TILE_MODE27, false}, | |
526 | {mmGB_TILE_MODE28, false}, | |
527 | {mmGB_TILE_MODE29, false}, | |
528 | {mmGB_TILE_MODE30, false}, | |
529 | {mmGB_TILE_MODE31, false}, | |
530 | {mmGB_MACROTILE_MODE0, false}, | |
531 | {mmGB_MACROTILE_MODE1, false}, | |
532 | {mmGB_MACROTILE_MODE2, false}, | |
533 | {mmGB_MACROTILE_MODE3, false}, | |
534 | {mmGB_MACROTILE_MODE4, false}, | |
535 | {mmGB_MACROTILE_MODE5, false}, | |
536 | {mmGB_MACROTILE_MODE6, false}, | |
537 | {mmGB_MACROTILE_MODE7, false}, | |
538 | {mmGB_MACROTILE_MODE8, false}, | |
539 | {mmGB_MACROTILE_MODE9, false}, | |
540 | {mmGB_MACROTILE_MODE10, false}, | |
541 | {mmGB_MACROTILE_MODE11, false}, | |
542 | {mmGB_MACROTILE_MODE12, false}, | |
543 | {mmGB_MACROTILE_MODE13, false}, | |
544 | {mmGB_MACROTILE_MODE14, false}, | |
545 | {mmGB_MACROTILE_MODE15, false}, | |
546 | {mmCC_RB_BACKEND_DISABLE, false, true}, | |
547 | {mmGC_USER_RB_BACKEND_DISABLE, false, true}, | |
548 | {mmGB_BACKEND_MAP, false, false}, | |
549 | {mmPA_SC_RASTER_CONFIG, false, true}, | |
550 | {mmPA_SC_RASTER_CONFIG_1, false, true}, | |
551 | }; | |
552 | ||
553 | static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, | |
554 | u32 sh_num, u32 reg_offset) | |
555 | { | |
556 | uint32_t val; | |
557 | ||
558 | mutex_lock(&adev->grbm_idx_mutex); | |
559 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
9559ef5b | 560 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); |
aaa36a97 AD |
561 | |
562 | val = RREG32(reg_offset); | |
563 | ||
564 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
9559ef5b | 565 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
aaa36a97 AD |
566 | mutex_unlock(&adev->grbm_idx_mutex); |
567 | return val; | |
568 | } | |
569 | ||
570 | static int vi_read_register(struct amdgpu_device *adev, u32 se_num, | |
571 | u32 sh_num, u32 reg_offset, u32 *value) | |
572 | { | |
eca2240f NW |
573 | const struct amdgpu_allowed_register_entry *asic_register_table = NULL; |
574 | const struct amdgpu_allowed_register_entry *asic_register_entry; | |
aaa36a97 AD |
575 | uint32_t size, i; |
576 | ||
577 | *value = 0; | |
578 | switch (adev->asic_type) { | |
579 | case CHIP_TOPAZ: | |
580 | asic_register_table = tonga_allowed_read_registers; | |
581 | size = ARRAY_SIZE(tonga_allowed_read_registers); | |
582 | break; | |
48299f95 | 583 | case CHIP_FIJI: |
aaa36a97 | 584 | case CHIP_TONGA: |
2cc0c0b5 FC |
585 | case CHIP_POLARIS11: |
586 | case CHIP_POLARIS10: | |
aaa36a97 | 587 | case CHIP_CARRIZO: |
39bb0c92 | 588 | case CHIP_STONEY: |
aaa36a97 AD |
589 | asic_register_table = cz_allowed_read_registers; |
590 | size = ARRAY_SIZE(cz_allowed_read_registers); | |
591 | break; | |
592 | default: | |
593 | return -EINVAL; | |
594 | } | |
595 | ||
596 | if (asic_register_table) { | |
597 | for (i = 0; i < size; i++) { | |
598 | asic_register_entry = asic_register_table + i; | |
599 | if (reg_offset != asic_register_entry->reg_offset) | |
600 | continue; | |
601 | if (!asic_register_entry->untouched) | |
602 | *value = asic_register_entry->grbm_indexed ? | |
603 | vi_read_indexed_register(adev, se_num, | |
604 | sh_num, reg_offset) : | |
605 | RREG32(reg_offset); | |
606 | return 0; | |
607 | } | |
608 | } | |
609 | ||
610 | for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { | |
611 | if (reg_offset != vi_allowed_read_registers[i].reg_offset) | |
612 | continue; | |
613 | ||
614 | if (!vi_allowed_read_registers[i].untouched) | |
615 | *value = vi_allowed_read_registers[i].grbm_indexed ? | |
616 | vi_read_indexed_register(adev, se_num, | |
617 | sh_num, reg_offset) : | |
618 | RREG32(reg_offset); | |
619 | return 0; | |
620 | } | |
621 | return -EINVAL; | |
622 | } | |
623 | ||
89a31827 | 624 | static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) |
aaa36a97 | 625 | { |
a2c5c698 | 626 | u32 i; |
aaa36a97 AD |
627 | |
628 | dev_info(adev->dev, "GPU pci config reset\n"); | |
629 | ||
aaa36a97 AD |
630 | /* disable BM */ |
631 | pci_clear_master(adev->pdev); | |
632 | /* reset */ | |
633 | amdgpu_pci_config_reset(adev); | |
634 | ||
635 | udelay(100); | |
636 | ||
637 | /* wait for asic to come out of reset */ | |
638 | for (i = 0; i < adev->usec_timeout; i++) { | |
b314f9a9 CZ |
639 | if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { |
640 | /* enable BM */ | |
641 | pci_set_master(adev->pdev); | |
89a31827 | 642 | return 0; |
b314f9a9 | 643 | } |
aaa36a97 AD |
644 | udelay(1); |
645 | } | |
89a31827 | 646 | return -EINVAL; |
aaa36a97 AD |
647 | } |
648 | ||
649 | static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) | |
650 | { | |
651 | u32 tmp = RREG32(mmBIOS_SCRATCH_3); | |
652 | ||
653 | if (hung) | |
654 | tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
655 | else | |
656 | tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
657 | ||
658 | WREG32(mmBIOS_SCRATCH_3, tmp); | |
659 | } | |
660 | ||
661 | /** | |
662 | * vi_asic_reset - soft reset GPU | |
663 | * | |
664 | * @adev: amdgpu_device pointer | |
665 | * | |
666 | * Look up which blocks are hung and attempt | |
667 | * to reset them. | |
668 | * Returns 0 for success. | |
669 | */ | |
670 | static int vi_asic_reset(struct amdgpu_device *adev) | |
671 | { | |
89a31827 CZ |
672 | int r; |
673 | ||
a2c5c698 | 674 | vi_set_bios_scratch_engine_hung(adev, true); |
aaa36a97 | 675 | |
89a31827 | 676 | r = vi_gpu_pci_config_reset(adev); |
aaa36a97 | 677 | |
a2c5c698 | 678 | vi_set_bios_scratch_engine_hung(adev, false); |
aaa36a97 | 679 | |
89a31827 | 680 | return r; |
aaa36a97 AD |
681 | } |
682 | ||
683 | static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, | |
684 | u32 cntl_reg, u32 status_reg) | |
685 | { | |
686 | int r, i; | |
687 | struct atom_clock_dividers dividers; | |
688 | uint32_t tmp; | |
689 | ||
690 | r = amdgpu_atombios_get_clock_dividers(adev, | |
691 | COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, | |
692 | clock, false, ÷rs); | |
693 | if (r) | |
694 | return r; | |
695 | ||
696 | tmp = RREG32_SMC(cntl_reg); | |
697 | tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | | |
698 | CG_DCLK_CNTL__DCLK_DIVIDER_MASK); | |
699 | tmp |= dividers.post_divider; | |
700 | WREG32_SMC(cntl_reg, tmp); | |
701 | ||
702 | for (i = 0; i < 100; i++) { | |
703 | if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) | |
704 | break; | |
705 | mdelay(10); | |
706 | } | |
707 | if (i == 100) | |
708 | return -ETIMEDOUT; | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) | |
714 | { | |
715 | int r; | |
716 | ||
717 | r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); | |
718 | if (r) | |
719 | return r; | |
720 | ||
721 | r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
726 | static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) | |
727 | { | |
728 | /* todo */ | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | static void vi_pcie_gen3_enable(struct amdgpu_device *adev) | |
734 | { | |
e79d5c08 AD |
735 | if (pci_is_root_bus(adev->pdev->bus)) |
736 | return; | |
737 | ||
aaa36a97 AD |
738 | if (amdgpu_pcie_gen2 == 0) |
739 | return; | |
740 | ||
2f7d10b3 | 741 | if (adev->flags & AMD_IS_APU) |
aaa36a97 AD |
742 | return; |
743 | ||
d0dd7f0c AD |
744 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
745 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) | |
aaa36a97 AD |
746 | return; |
747 | ||
748 | /* todo */ | |
749 | } | |
750 | ||
751 | static void vi_program_aspm(struct amdgpu_device *adev) | |
752 | { | |
753 | ||
754 | if (amdgpu_aspm == 0) | |
755 | return; | |
756 | ||
757 | /* todo */ | |
758 | } | |
759 | ||
760 | static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, | |
761 | bool enable) | |
762 | { | |
763 | u32 tmp; | |
764 | ||
765 | /* not necessary on CZ */ | |
2f7d10b3 | 766 | if (adev->flags & AMD_IS_APU) |
aaa36a97 AD |
767 | return; |
768 | ||
769 | tmp = RREG32(mmBIF_DOORBELL_APER_EN); | |
770 | if (enable) | |
771 | tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); | |
772 | else | |
773 | tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); | |
774 | ||
775 | WREG32(mmBIF_DOORBELL_APER_EN, tmp); | |
776 | } | |
777 | ||
778 | /* topaz has no DCE, UVD, VCE */ | |
779 | static const struct amdgpu_ip_block_version topaz_ip_blocks[] = | |
780 | { | |
781 | /* ORDER MATTERS! */ | |
782 | { | |
5fc3aeeb | 783 | .type = AMD_IP_BLOCK_TYPE_COMMON, |
aaa36a97 AD |
784 | .major = 2, |
785 | .minor = 0, | |
786 | .rev = 0, | |
787 | .funcs = &vi_common_ip_funcs, | |
788 | }, | |
789 | { | |
5fc3aeeb | 790 | .type = AMD_IP_BLOCK_TYPE_GMC, |
429c45de KW |
791 | .major = 7, |
792 | .minor = 4, | |
aaa36a97 | 793 | .rev = 0, |
429c45de | 794 | .funcs = &gmc_v7_0_ip_funcs, |
aaa36a97 AD |
795 | }, |
796 | { | |
5fc3aeeb | 797 | .type = AMD_IP_BLOCK_TYPE_IH, |
aaa36a97 AD |
798 | .major = 2, |
799 | .minor = 4, | |
800 | .rev = 0, | |
801 | .funcs = &iceland_ih_ip_funcs, | |
802 | }, | |
803 | { | |
5fc3aeeb | 804 | .type = AMD_IP_BLOCK_TYPE_SMC, |
aaa36a97 AD |
805 | .major = 7, |
806 | .minor = 1, | |
807 | .rev = 0, | |
1f7371b2 | 808 | .funcs = &amdgpu_pp_ip_funcs, |
aaa36a97 AD |
809 | }, |
810 | { | |
5fc3aeeb | 811 | .type = AMD_IP_BLOCK_TYPE_GFX, |
aaa36a97 AD |
812 | .major = 8, |
813 | .minor = 0, | |
814 | .rev = 0, | |
815 | .funcs = &gfx_v8_0_ip_funcs, | |
816 | }, | |
817 | { | |
5fc3aeeb | 818 | .type = AMD_IP_BLOCK_TYPE_SDMA, |
aaa36a97 AD |
819 | .major = 2, |
820 | .minor = 4, | |
821 | .rev = 0, | |
822 | .funcs = &sdma_v2_4_ip_funcs, | |
823 | }, | |
824 | }; | |
825 | ||
4f4b7834 AD |
826 | static const struct amdgpu_ip_block_version topaz_ip_blocks_vd[] = |
827 | { | |
828 | /* ORDER MATTERS! */ | |
829 | { | |
830 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
831 | .major = 2, | |
832 | .minor = 0, | |
833 | .rev = 0, | |
834 | .funcs = &vi_common_ip_funcs, | |
835 | }, | |
836 | { | |
837 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
838 | .major = 7, | |
839 | .minor = 4, | |
840 | .rev = 0, | |
841 | .funcs = &gmc_v7_0_ip_funcs, | |
842 | }, | |
843 | { | |
844 | .type = AMD_IP_BLOCK_TYPE_IH, | |
845 | .major = 2, | |
846 | .minor = 4, | |
847 | .rev = 0, | |
848 | .funcs = &iceland_ih_ip_funcs, | |
849 | }, | |
850 | { | |
851 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
852 | .major = 7, | |
853 | .minor = 1, | |
854 | .rev = 0, | |
855 | .funcs = &amdgpu_pp_ip_funcs, | |
856 | }, | |
857 | { | |
858 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
859 | .major = 1, | |
860 | .minor = 0, | |
861 | .rev = 0, | |
862 | .funcs = &dce_virtual_ip_funcs, | |
863 | }, | |
864 | { | |
865 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
866 | .major = 8, | |
867 | .minor = 0, | |
868 | .rev = 0, | |
869 | .funcs = &gfx_v8_0_ip_funcs, | |
870 | }, | |
871 | { | |
872 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
873 | .major = 2, | |
874 | .minor = 4, | |
875 | .rev = 0, | |
876 | .funcs = &sdma_v2_4_ip_funcs, | |
877 | }, | |
878 | }; | |
879 | ||
aaa36a97 AD |
880 | static const struct amdgpu_ip_block_version tonga_ip_blocks[] = |
881 | { | |
882 | /* ORDER MATTERS! */ | |
883 | { | |
5fc3aeeb | 884 | .type = AMD_IP_BLOCK_TYPE_COMMON, |
aaa36a97 AD |
885 | .major = 2, |
886 | .minor = 0, | |
887 | .rev = 0, | |
888 | .funcs = &vi_common_ip_funcs, | |
889 | }, | |
890 | { | |
5fc3aeeb | 891 | .type = AMD_IP_BLOCK_TYPE_GMC, |
aaa36a97 AD |
892 | .major = 8, |
893 | .minor = 0, | |
894 | .rev = 0, | |
895 | .funcs = &gmc_v8_0_ip_funcs, | |
896 | }, | |
897 | { | |
5fc3aeeb | 898 | .type = AMD_IP_BLOCK_TYPE_IH, |
aaa36a97 AD |
899 | .major = 3, |
900 | .minor = 0, | |
901 | .rev = 0, | |
902 | .funcs = &tonga_ih_ip_funcs, | |
903 | }, | |
904 | { | |
5fc3aeeb | 905 | .type = AMD_IP_BLOCK_TYPE_SMC, |
aaa36a97 AD |
906 | .major = 7, |
907 | .minor = 1, | |
908 | .rev = 0, | |
1f7371b2 | 909 | .funcs = &amdgpu_pp_ip_funcs, |
aaa36a97 AD |
910 | }, |
911 | { | |
5fc3aeeb | 912 | .type = AMD_IP_BLOCK_TYPE_DCE, |
aaa36a97 AD |
913 | .major = 10, |
914 | .minor = 0, | |
915 | .rev = 0, | |
916 | .funcs = &dce_v10_0_ip_funcs, | |
917 | }, | |
918 | { | |
5fc3aeeb | 919 | .type = AMD_IP_BLOCK_TYPE_GFX, |
aaa36a97 AD |
920 | .major = 8, |
921 | .minor = 0, | |
922 | .rev = 0, | |
923 | .funcs = &gfx_v8_0_ip_funcs, | |
924 | }, | |
925 | { | |
5fc3aeeb | 926 | .type = AMD_IP_BLOCK_TYPE_SDMA, |
aaa36a97 AD |
927 | .major = 3, |
928 | .minor = 0, | |
929 | .rev = 0, | |
930 | .funcs = &sdma_v3_0_ip_funcs, | |
931 | }, | |
932 | { | |
5fc3aeeb | 933 | .type = AMD_IP_BLOCK_TYPE_UVD, |
aaa36a97 AD |
934 | .major = 5, |
935 | .minor = 0, | |
936 | .rev = 0, | |
937 | .funcs = &uvd_v5_0_ip_funcs, | |
938 | }, | |
939 | { | |
5fc3aeeb | 940 | .type = AMD_IP_BLOCK_TYPE_VCE, |
aaa36a97 AD |
941 | .major = 3, |
942 | .minor = 0, | |
943 | .rev = 0, | |
944 | .funcs = &vce_v3_0_ip_funcs, | |
945 | }, | |
946 | }; | |
947 | ||
e9ed3a67 ED |
948 | static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] = |
949 | { | |
950 | /* ORDER MATTERS! */ | |
951 | { | |
952 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
953 | .major = 2, | |
954 | .minor = 0, | |
955 | .rev = 0, | |
956 | .funcs = &vi_common_ip_funcs, | |
957 | }, | |
958 | { | |
959 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
960 | .major = 8, | |
961 | .minor = 0, | |
962 | .rev = 0, | |
963 | .funcs = &gmc_v8_0_ip_funcs, | |
964 | }, | |
965 | { | |
966 | .type = AMD_IP_BLOCK_TYPE_IH, | |
967 | .major = 3, | |
968 | .minor = 0, | |
969 | .rev = 0, | |
970 | .funcs = &tonga_ih_ip_funcs, | |
971 | }, | |
972 | { | |
973 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
974 | .major = 7, | |
975 | .minor = 1, | |
976 | .rev = 0, | |
977 | .funcs = &amdgpu_pp_ip_funcs, | |
978 | }, | |
979 | { | |
980 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
981 | .major = 10, | |
982 | .minor = 0, | |
983 | .rev = 0, | |
984 | .funcs = &dce_virtual_ip_funcs, | |
985 | }, | |
986 | { | |
987 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
988 | .major = 8, | |
989 | .minor = 0, | |
990 | .rev = 0, | |
991 | .funcs = &gfx_v8_0_ip_funcs, | |
992 | }, | |
993 | { | |
994 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
995 | .major = 3, | |
996 | .minor = 0, | |
997 | .rev = 0, | |
998 | .funcs = &sdma_v3_0_ip_funcs, | |
999 | }, | |
1000 | { | |
1001 | .type = AMD_IP_BLOCK_TYPE_UVD, | |
1002 | .major = 5, | |
1003 | .minor = 0, | |
1004 | .rev = 0, | |
1005 | .funcs = &uvd_v5_0_ip_funcs, | |
1006 | }, | |
1007 | { | |
1008 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1009 | .major = 3, | |
1010 | .minor = 0, | |
1011 | .rev = 0, | |
1012 | .funcs = &vce_v3_0_ip_funcs, | |
1013 | }, | |
1014 | }; | |
1015 | ||
48299f95 DZ |
1016 | static const struct amdgpu_ip_block_version fiji_ip_blocks[] = |
1017 | { | |
1018 | /* ORDER MATTERS! */ | |
1019 | { | |
1020 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
1021 | .major = 2, | |
1022 | .minor = 0, | |
1023 | .rev = 0, | |
1024 | .funcs = &vi_common_ip_funcs, | |
127a2628 DZ |
1025 | }, |
1026 | { | |
1027 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1028 | .major = 8, | |
1029 | .minor = 5, | |
1030 | .rev = 0, | |
1031 | .funcs = &gmc_v8_0_ip_funcs, | |
1032 | }, | |
aa8a3b53 DZ |
1033 | { |
1034 | .type = AMD_IP_BLOCK_TYPE_IH, | |
1035 | .major = 3, | |
1036 | .minor = 0, | |
1037 | .rev = 0, | |
1038 | .funcs = &tonga_ih_ip_funcs, | |
1039 | }, | |
8e711e1a DZ |
1040 | { |
1041 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
1042 | .major = 7, | |
1043 | .minor = 1, | |
1044 | .rev = 0, | |
899fa4c0 | 1045 | .funcs = &amdgpu_pp_ip_funcs, |
8e711e1a | 1046 | }, |
84390860 DZ |
1047 | { |
1048 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
1049 | .major = 10, | |
1050 | .minor = 1, | |
1051 | .rev = 0, | |
1052 | .funcs = &dce_v10_0_ip_funcs, | |
1053 | }, | |
af15a2d5 DZ |
1054 | { |
1055 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
1056 | .major = 8, | |
1057 | .minor = 0, | |
1058 | .rev = 0, | |
1059 | .funcs = &gfx_v8_0_ip_funcs, | |
1060 | }, | |
1a5bbb66 DZ |
1061 | { |
1062 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1063 | .major = 3, | |
1064 | .minor = 0, | |
1065 | .rev = 0, | |
1066 | .funcs = &sdma_v3_0_ip_funcs, | |
1067 | }, | |
974ee3db DZ |
1068 | { |
1069 | .type = AMD_IP_BLOCK_TYPE_UVD, | |
1070 | .major = 6, | |
1071 | .minor = 0, | |
1072 | .rev = 0, | |
1073 | .funcs = &uvd_v6_0_ip_funcs, | |
1074 | }, | |
188a9bcd AD |
1075 | { |
1076 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1077 | .major = 3, | |
1078 | .minor = 0, | |
1079 | .rev = 0, | |
1080 | .funcs = &vce_v3_0_ip_funcs, | |
1081 | }, | |
48299f95 DZ |
1082 | }; |
1083 | ||
e9ed3a67 ED |
1084 | static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] = |
1085 | { | |
1086 | /* ORDER MATTERS! */ | |
1087 | { | |
1088 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
1089 | .major = 2, | |
1090 | .minor = 0, | |
1091 | .rev = 0, | |
1092 | .funcs = &vi_common_ip_funcs, | |
1093 | }, | |
1094 | { | |
1095 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1096 | .major = 8, | |
1097 | .minor = 5, | |
1098 | .rev = 0, | |
1099 | .funcs = &gmc_v8_0_ip_funcs, | |
1100 | }, | |
1101 | { | |
1102 | .type = AMD_IP_BLOCK_TYPE_IH, | |
1103 | .major = 3, | |
1104 | .minor = 0, | |
1105 | .rev = 0, | |
1106 | .funcs = &tonga_ih_ip_funcs, | |
1107 | }, | |
1108 | { | |
1109 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
1110 | .major = 7, | |
1111 | .minor = 1, | |
1112 | .rev = 0, | |
1113 | .funcs = &amdgpu_pp_ip_funcs, | |
1114 | }, | |
1115 | { | |
1116 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
1117 | .major = 10, | |
1118 | .minor = 1, | |
1119 | .rev = 0, | |
1120 | .funcs = &dce_virtual_ip_funcs, | |
1121 | }, | |
1122 | { | |
1123 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
1124 | .major = 8, | |
1125 | .minor = 0, | |
1126 | .rev = 0, | |
1127 | .funcs = &gfx_v8_0_ip_funcs, | |
1128 | }, | |
1129 | { | |
1130 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1131 | .major = 3, | |
1132 | .minor = 0, | |
1133 | .rev = 0, | |
1134 | .funcs = &sdma_v3_0_ip_funcs, | |
1135 | }, | |
1136 | { | |
1137 | .type = AMD_IP_BLOCK_TYPE_UVD, | |
1138 | .major = 6, | |
1139 | .minor = 0, | |
1140 | .rev = 0, | |
1141 | .funcs = &uvd_v6_0_ip_funcs, | |
1142 | }, | |
1143 | { | |
1144 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1145 | .major = 3, | |
1146 | .minor = 0, | |
1147 | .rev = 0, | |
1148 | .funcs = &vce_v3_0_ip_funcs, | |
1149 | }, | |
1150 | }; | |
1151 | ||
2cc0c0b5 | 1152 | static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = |
c0c1f579 FC |
1153 | { |
1154 | /* ORDER MATTERS! */ | |
1155 | { | |
1156 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
1157 | .major = 2, | |
1158 | .minor = 0, | |
1159 | .rev = 0, | |
1160 | .funcs = &vi_common_ip_funcs, | |
1161 | }, | |
1162 | { | |
1163 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1164 | .major = 8, | |
1165 | .minor = 1, | |
1166 | .rev = 0, | |
1167 | .funcs = &gmc_v8_0_ip_funcs, | |
1168 | }, | |
1169 | { | |
1170 | .type = AMD_IP_BLOCK_TYPE_IH, | |
1171 | .major = 3, | |
1172 | .minor = 1, | |
1173 | .rev = 0, | |
1174 | .funcs = &tonga_ih_ip_funcs, | |
1175 | }, | |
1176 | { | |
1177 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
1178 | .major = 7, | |
1179 | .minor = 2, | |
1180 | .rev = 0, | |
1181 | .funcs = &amdgpu_pp_ip_funcs, | |
1182 | }, | |
1183 | { | |
1184 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
1185 | .major = 11, | |
1186 | .minor = 2, | |
1187 | .rev = 0, | |
1188 | .funcs = &dce_v11_0_ip_funcs, | |
1189 | }, | |
1190 | { | |
1191 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
1192 | .major = 8, | |
1193 | .minor = 0, | |
1194 | .rev = 0, | |
1195 | .funcs = &gfx_v8_0_ip_funcs, | |
1196 | }, | |
1197 | { | |
1198 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1199 | .major = 3, | |
1200 | .minor = 1, | |
1201 | .rev = 0, | |
1202 | .funcs = &sdma_v3_0_ip_funcs, | |
1203 | }, | |
1204 | { | |
1205 | .type = AMD_IP_BLOCK_TYPE_UVD, | |
1206 | .major = 6, | |
1207 | .minor = 3, | |
1208 | .rev = 0, | |
1209 | .funcs = &uvd_v6_0_ip_funcs, | |
1210 | }, | |
1211 | { | |
1212 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1213 | .major = 3, | |
1214 | .minor = 4, | |
1215 | .rev = 0, | |
1216 | .funcs = &vce_v3_0_ip_funcs, | |
1217 | }, | |
1218 | }; | |
1219 | ||
e9ed3a67 ED |
1220 | static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] = |
1221 | { | |
1222 | /* ORDER MATTERS! */ | |
1223 | { | |
1224 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
1225 | .major = 2, | |
1226 | .minor = 0, | |
1227 | .rev = 0, | |
1228 | .funcs = &vi_common_ip_funcs, | |
1229 | }, | |
1230 | { | |
1231 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1232 | .major = 8, | |
1233 | .minor = 1, | |
1234 | .rev = 0, | |
1235 | .funcs = &gmc_v8_0_ip_funcs, | |
1236 | }, | |
1237 | { | |
1238 | .type = AMD_IP_BLOCK_TYPE_IH, | |
1239 | .major = 3, | |
1240 | .minor = 1, | |
1241 | .rev = 0, | |
1242 | .funcs = &tonga_ih_ip_funcs, | |
1243 | }, | |
1244 | { | |
1245 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
1246 | .major = 7, | |
1247 | .minor = 2, | |
1248 | .rev = 0, | |
1249 | .funcs = &amdgpu_pp_ip_funcs, | |
1250 | }, | |
1251 | { | |
1252 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
1253 | .major = 11, | |
1254 | .minor = 2, | |
1255 | .rev = 0, | |
1256 | .funcs = &dce_virtual_ip_funcs, | |
1257 | }, | |
1258 | { | |
1259 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
1260 | .major = 8, | |
1261 | .minor = 0, | |
1262 | .rev = 0, | |
1263 | .funcs = &gfx_v8_0_ip_funcs, | |
1264 | }, | |
1265 | { | |
1266 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1267 | .major = 3, | |
1268 | .minor = 1, | |
1269 | .rev = 0, | |
1270 | .funcs = &sdma_v3_0_ip_funcs, | |
1271 | }, | |
1272 | { | |
1273 | .type = AMD_IP_BLOCK_TYPE_UVD, | |
1274 | .major = 6, | |
1275 | .minor = 3, | |
1276 | .rev = 0, | |
1277 | .funcs = &uvd_v6_0_ip_funcs, | |
1278 | }, | |
1279 | { | |
1280 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1281 | .major = 3, | |
1282 | .minor = 4, | |
1283 | .rev = 0, | |
1284 | .funcs = &vce_v3_0_ip_funcs, | |
1285 | }, | |
1286 | }; | |
1287 | ||
aaa36a97 AD |
1288 | static const struct amdgpu_ip_block_version cz_ip_blocks[] = |
1289 | { | |
1290 | /* ORDER MATTERS! */ | |
1291 | { | |
5fc3aeeb | 1292 | .type = AMD_IP_BLOCK_TYPE_COMMON, |
aaa36a97 AD |
1293 | .major = 2, |
1294 | .minor = 0, | |
1295 | .rev = 0, | |
1296 | .funcs = &vi_common_ip_funcs, | |
1297 | }, | |
1298 | { | |
5fc3aeeb | 1299 | .type = AMD_IP_BLOCK_TYPE_GMC, |
aaa36a97 AD |
1300 | .major = 8, |
1301 | .minor = 0, | |
1302 | .rev = 0, | |
1303 | .funcs = &gmc_v8_0_ip_funcs, | |
1304 | }, | |
1305 | { | |
5fc3aeeb | 1306 | .type = AMD_IP_BLOCK_TYPE_IH, |
aaa36a97 AD |
1307 | .major = 3, |
1308 | .minor = 0, | |
1309 | .rev = 0, | |
1310 | .funcs = &cz_ih_ip_funcs, | |
1311 | }, | |
1312 | { | |
5fc3aeeb | 1313 | .type = AMD_IP_BLOCK_TYPE_SMC, |
aaa36a97 AD |
1314 | .major = 8, |
1315 | .minor = 0, | |
1316 | .rev = 0, | |
1f7371b2 | 1317 | .funcs = &amdgpu_pp_ip_funcs |
aaa36a97 AD |
1318 | }, |
1319 | { | |
5fc3aeeb | 1320 | .type = AMD_IP_BLOCK_TYPE_DCE, |
aaa36a97 AD |
1321 | .major = 11, |
1322 | .minor = 0, | |
1323 | .rev = 0, | |
1324 | .funcs = &dce_v11_0_ip_funcs, | |
1325 | }, | |
1326 | { | |
5fc3aeeb | 1327 | .type = AMD_IP_BLOCK_TYPE_GFX, |
aaa36a97 AD |
1328 | .major = 8, |
1329 | .minor = 0, | |
1330 | .rev = 0, | |
1331 | .funcs = &gfx_v8_0_ip_funcs, | |
1332 | }, | |
1333 | { | |
5fc3aeeb | 1334 | .type = AMD_IP_BLOCK_TYPE_SDMA, |
aaa36a97 AD |
1335 | .major = 3, |
1336 | .minor = 0, | |
1337 | .rev = 0, | |
1338 | .funcs = &sdma_v3_0_ip_funcs, | |
1339 | }, | |
1340 | { | |
5fc3aeeb | 1341 | .type = AMD_IP_BLOCK_TYPE_UVD, |
aaa36a97 AD |
1342 | .major = 6, |
1343 | .minor = 0, | |
1344 | .rev = 0, | |
e9ed3a67 ED |
1345 | .funcs = &uvd_v6_0_ip_funcs, |
1346 | }, | |
1347 | { | |
1348 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1349 | .major = 3, | |
1350 | .minor = 0, | |
1351 | .rev = 0, | |
1352 | .funcs = &vce_v3_0_ip_funcs, | |
1353 | }, | |
1354 | #if defined(CONFIG_DRM_AMD_ACP) | |
1355 | { | |
1356 | .type = AMD_IP_BLOCK_TYPE_ACP, | |
1357 | .major = 2, | |
1358 | .minor = 2, | |
1359 | .rev = 0, | |
1360 | .funcs = &acp_ip_funcs, | |
1361 | }, | |
1362 | #endif | |
1363 | }; | |
1364 | ||
1365 | static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] = | |
1366 | { | |
1367 | /* ORDER MATTERS! */ | |
1368 | { | |
1369 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
1370 | .major = 2, | |
1371 | .minor = 0, | |
1372 | .rev = 0, | |
1373 | .funcs = &vi_common_ip_funcs, | |
1374 | }, | |
1375 | { | |
1376 | .type = AMD_IP_BLOCK_TYPE_GMC, | |
1377 | .major = 8, | |
1378 | .minor = 0, | |
1379 | .rev = 0, | |
1380 | .funcs = &gmc_v8_0_ip_funcs, | |
1381 | }, | |
1382 | { | |
1383 | .type = AMD_IP_BLOCK_TYPE_IH, | |
1384 | .major = 3, | |
1385 | .minor = 0, | |
1386 | .rev = 0, | |
1387 | .funcs = &cz_ih_ip_funcs, | |
1388 | }, | |
1389 | { | |
1390 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
1391 | .major = 8, | |
1392 | .minor = 0, | |
1393 | .rev = 0, | |
1394 | .funcs = &amdgpu_pp_ip_funcs | |
1395 | }, | |
1396 | { | |
1397 | .type = AMD_IP_BLOCK_TYPE_DCE, | |
1398 | .major = 11, | |
1399 | .minor = 0, | |
1400 | .rev = 0, | |
1401 | .funcs = &dce_virtual_ip_funcs, | |
1402 | }, | |
1403 | { | |
1404 | .type = AMD_IP_BLOCK_TYPE_GFX, | |
1405 | .major = 8, | |
1406 | .minor = 0, | |
1407 | .rev = 0, | |
1408 | .funcs = &gfx_v8_0_ip_funcs, | |
1409 | }, | |
1410 | { | |
1411 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1412 | .major = 3, | |
1413 | .minor = 0, | |
1414 | .rev = 0, | |
1415 | .funcs = &sdma_v3_0_ip_funcs, | |
1416 | }, | |
1417 | { | |
1418 | .type = AMD_IP_BLOCK_TYPE_UVD, | |
1419 | .major = 6, | |
1420 | .minor = 0, | |
1421 | .rev = 0, | |
aaa36a97 AD |
1422 | .funcs = &uvd_v6_0_ip_funcs, |
1423 | }, | |
1424 | { | |
5fc3aeeb | 1425 | .type = AMD_IP_BLOCK_TYPE_VCE, |
aaa36a97 AD |
1426 | .major = 3, |
1427 | .minor = 0, | |
1428 | .rev = 0, | |
1429 | .funcs = &vce_v3_0_ip_funcs, | |
1430 | }, | |
a8fe58ce MB |
1431 | #if defined(CONFIG_DRM_AMD_ACP) |
1432 | { | |
1433 | .type = AMD_IP_BLOCK_TYPE_ACP, | |
1434 | .major = 2, | |
1435 | .minor = 2, | |
1436 | .rev = 0, | |
1437 | .funcs = &acp_ip_funcs, | |
1438 | }, | |
1439 | #endif | |
aaa36a97 AD |
1440 | }; |
1441 | ||
1442 | int vi_set_ip_blocks(struct amdgpu_device *adev) | |
1443 | { | |
9accf2fd | 1444 | if (adev->enable_virtual_display) { |
a6be7570 ED |
1445 | switch (adev->asic_type) { |
1446 | case CHIP_TOPAZ: | |
4f4b7834 AD |
1447 | adev->ip_blocks = topaz_ip_blocks_vd; |
1448 | adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks_vd); | |
a6be7570 ED |
1449 | break; |
1450 | case CHIP_FIJI: | |
1451 | adev->ip_blocks = fiji_ip_blocks_vd; | |
1452 | adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd); | |
1453 | break; | |
1454 | case CHIP_TONGA: | |
1455 | adev->ip_blocks = tonga_ip_blocks_vd; | |
1456 | adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd); | |
1457 | break; | |
1458 | case CHIP_POLARIS11: | |
1459 | case CHIP_POLARIS10: | |
1460 | adev->ip_blocks = polaris11_ip_blocks_vd; | |
1461 | adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd); | |
1462 | break; | |
1463 | ||
1464 | case CHIP_CARRIZO: | |
1465 | case CHIP_STONEY: | |
1466 | adev->ip_blocks = cz_ip_blocks_vd; | |
1467 | adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd); | |
1468 | break; | |
1469 | default: | |
1470 | /* FIXME: not supported yet */ | |
1471 | return -EINVAL; | |
1472 | } | |
1473 | } else { | |
1474 | switch (adev->asic_type) { | |
1475 | case CHIP_TOPAZ: | |
1476 | adev->ip_blocks = topaz_ip_blocks; | |
1477 | adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks); | |
1478 | break; | |
1479 | case CHIP_FIJI: | |
1480 | adev->ip_blocks = fiji_ip_blocks; | |
1481 | adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks); | |
1482 | break; | |
1483 | case CHIP_TONGA: | |
1484 | adev->ip_blocks = tonga_ip_blocks; | |
1485 | adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); | |
1486 | break; | |
1487 | case CHIP_POLARIS11: | |
1488 | case CHIP_POLARIS10: | |
1489 | adev->ip_blocks = polaris11_ip_blocks; | |
1490 | adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); | |
1491 | break; | |
1492 | case CHIP_CARRIZO: | |
1493 | case CHIP_STONEY: | |
1494 | adev->ip_blocks = cz_ip_blocks; | |
1495 | adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); | |
1496 | break; | |
1497 | default: | |
1498 | /* FIXME: not supported yet */ | |
1499 | return -EINVAL; | |
1500 | } | |
aaa36a97 AD |
1501 | } |
1502 | ||
aaa36a97 AD |
1503 | return 0; |
1504 | } | |
1505 | ||
39bb0c92 SL |
1506 | #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 |
1507 | #define ATI_REV_ID_FUSE_MACRO__SHIFT 9 | |
1508 | #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 | |
1509 | ||
aaa36a97 AD |
1510 | static uint32_t vi_get_rev_id(struct amdgpu_device *adev) |
1511 | { | |
abdfb850 | 1512 | if (adev->flags & AMD_IS_APU) |
39bb0c92 SL |
1513 | return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) |
1514 | >> ATI_REV_ID_FUSE_MACRO__SHIFT; | |
aaa36a97 | 1515 | else |
abdfb850 FC |
1516 | return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) |
1517 | >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; | |
aaa36a97 AD |
1518 | } |
1519 | ||
1520 | static const struct amdgpu_asic_funcs vi_asic_funcs = | |
1521 | { | |
1522 | .read_disabled_bios = &vi_read_disabled_bios, | |
95addb2a | 1523 | .read_bios_from_rom = &vi_read_bios_from_rom, |
aaa36a97 AD |
1524 | .read_register = &vi_read_register, |
1525 | .reset = &vi_asic_reset, | |
1526 | .set_vga_state = &vi_vga_set_state, | |
1527 | .get_xclk = &vi_get_xclk, | |
1528 | .set_uvd_clocks = &vi_set_uvd_clocks, | |
1529 | .set_vce_clocks = &vi_set_vce_clocks, | |
048765ad | 1530 | .get_virtual_caps = &vi_get_virtual_caps, |
aaa36a97 AD |
1531 | }; |
1532 | ||
5fc3aeeb | 1533 | static int vi_common_early_init(void *handle) |
aaa36a97 AD |
1534 | { |
1535 | bool smc_enabled = false; | |
5fc3aeeb | 1536 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 | 1537 | |
2f7d10b3 | 1538 | if (adev->flags & AMD_IS_APU) { |
7b92cdbf AD |
1539 | adev->smc_rreg = &cz_smc_rreg; |
1540 | adev->smc_wreg = &cz_smc_wreg; | |
1541 | } else { | |
1542 | adev->smc_rreg = &vi_smc_rreg; | |
1543 | adev->smc_wreg = &vi_smc_wreg; | |
1544 | } | |
aaa36a97 AD |
1545 | adev->pcie_rreg = &vi_pcie_rreg; |
1546 | adev->pcie_wreg = &vi_pcie_wreg; | |
1547 | adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; | |
1548 | adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; | |
1549 | adev->didt_rreg = &vi_didt_rreg; | |
1550 | adev->didt_wreg = &vi_didt_wreg; | |
ccdbb20a RZ |
1551 | adev->gc_cac_rreg = &vi_gc_cac_rreg; |
1552 | adev->gc_cac_wreg = &vi_gc_cac_wreg; | |
aaa36a97 AD |
1553 | |
1554 | adev->asic_funcs = &vi_asic_funcs; | |
1555 | ||
5fc3aeeb | 1556 | if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && |
1557 | (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) | |
aaa36a97 AD |
1558 | smc_enabled = true; |
1559 | ||
1560 | adev->rev_id = vi_get_rev_id(adev); | |
1561 | adev->external_rev_id = 0xFF; | |
1562 | switch (adev->asic_type) { | |
1563 | case CHIP_TOPAZ: | |
aaa36a97 AD |
1564 | adev->cg_flags = 0; |
1565 | adev->pg_flags = 0; | |
1566 | adev->external_rev_id = 0x1; | |
aaa36a97 | 1567 | break; |
48299f95 | 1568 | case CHIP_FIJI: |
14698b6c AD |
1569 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1570 | AMD_CG_SUPPORT_GFX_MGLS | | |
1571 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1572 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1573 | AMD_CG_SUPPORT_GFX_CGTS | | |
1574 | AMD_CG_SUPPORT_GFX_CGTS_LS | | |
1575 | AMD_CG_SUPPORT_GFX_CGCG | | |
e08d53cb AD |
1576 | AMD_CG_SUPPORT_GFX_CGLS | |
1577 | AMD_CG_SUPPORT_SDMA_MGCG | | |
c90766cf AD |
1578 | AMD_CG_SUPPORT_SDMA_LS | |
1579 | AMD_CG_SUPPORT_BIF_LS | | |
1580 | AMD_CG_SUPPORT_HDP_MGCG | | |
1581 | AMD_CG_SUPPORT_HDP_LS | | |
3fde56b8 AD |
1582 | AMD_CG_SUPPORT_ROM_MGCG | |
1583 | AMD_CG_SUPPORT_MC_MGCG | | |
1584 | AMD_CG_SUPPORT_MC_LS; | |
b6bc28ff FC |
1585 | adev->pg_flags = 0; |
1586 | adev->external_rev_id = adev->rev_id + 0x3c; | |
1587 | break; | |
aaa36a97 | 1588 | case CHIP_TONGA: |
5f64e77e | 1589 | adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; |
aaa36a97 AD |
1590 | adev->pg_flags = 0; |
1591 | adev->external_rev_id = adev->rev_id + 0x14; | |
aaa36a97 | 1592 | break; |
2cc0c0b5 | 1593 | case CHIP_POLARIS11: |
c0c1f579 FC |
1594 | adev->cg_flags = 0; |
1595 | adev->pg_flags = 0; | |
1596 | adev->external_rev_id = adev->rev_id + 0x5A; | |
1597 | break; | |
2cc0c0b5 | 1598 | case CHIP_POLARIS10: |
c0c1f579 FC |
1599 | adev->cg_flags = 0; |
1600 | adev->pg_flags = 0; | |
1601 | adev->external_rev_id = adev->rev_id + 0x50; | |
1602 | break; | |
aaa36a97 | 1603 | case CHIP_CARRIZO: |
f0f3a8fb TSD |
1604 | adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | |
1605 | AMD_CG_SUPPORT_GFX_MGCG | | |
70eced9b AD |
1606 | AMD_CG_SUPPORT_GFX_MGLS | |
1607 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1608 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1609 | AMD_CG_SUPPORT_GFX_CGTS | | |
1610 | AMD_CG_SUPPORT_GFX_MGLS | | |
1611 | AMD_CG_SUPPORT_GFX_CGTS_LS | | |
1612 | AMD_CG_SUPPORT_GFX_CGCG | | |
03c335d3 AD |
1613 | AMD_CG_SUPPORT_GFX_CGLS | |
1614 | AMD_CG_SUPPORT_BIF_LS | | |
1615 | AMD_CG_SUPPORT_HDP_MGCG | | |
6f17a257 AD |
1616 | AMD_CG_SUPPORT_HDP_LS | |
1617 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1af69a2c TSD |
1618 | AMD_CG_SUPPORT_SDMA_LS | |
1619 | AMD_CG_SUPPORT_VCE_MGCG; | |
f6ade304 | 1620 | /* rev0 hardware requires workarounds to support PG */ |
0fd4af9e | 1621 | adev->pg_flags = 0; |
f6ade304 TSD |
1622 | if (adev->rev_id != 0x00) { |
1623 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | | |
1624 | AMD_PG_SUPPORT_GFX_SMG | | |
65b42622 | 1625 | AMD_PG_SUPPORT_GFX_PIPELINE | |
2ed0936d TSD |
1626 | AMD_PG_SUPPORT_UVD | |
1627 | AMD_PG_SUPPORT_VCE; | |
f6ade304 | 1628 | } |
aaa36a97 | 1629 | adev->external_rev_id = adev->rev_id + 0x1; |
aaa36a97 | 1630 | break; |
cde64939 | 1631 | case CHIP_STONEY: |
64694905 AD |
1632 | adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | |
1633 | AMD_CG_SUPPORT_GFX_MGCG | | |
b6711d1b | 1634 | AMD_CG_SUPPORT_GFX_MGLS | |
413cf600 TSD |
1635 | AMD_CG_SUPPORT_GFX_RLC_LS | |
1636 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1637 | AMD_CG_SUPPORT_GFX_CGTS | | |
1638 | AMD_CG_SUPPORT_GFX_MGLS | | |
1639 | AMD_CG_SUPPORT_GFX_CGTS_LS | | |
1640 | AMD_CG_SUPPORT_GFX_CGCG | | |
1641 | AMD_CG_SUPPORT_GFX_CGLS | | |
b6711d1b AD |
1642 | AMD_CG_SUPPORT_BIF_LS | |
1643 | AMD_CG_SUPPORT_HDP_MGCG | | |
1bf912ff AD |
1644 | AMD_CG_SUPPORT_HDP_LS | |
1645 | AMD_CG_SUPPORT_SDMA_MGCG | | |
8ef583e9 TSD |
1646 | AMD_CG_SUPPORT_SDMA_LS | |
1647 | AMD_CG_SUPPORT_VCE_MGCG; | |
4e86be75 TSD |
1648 | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | |
1649 | AMD_PG_SUPPORT_GFX_SMG | | |
c2cdb042 | 1650 | AMD_PG_SUPPORT_GFX_PIPELINE | |
75419c43 TSD |
1651 | AMD_PG_SUPPORT_UVD | |
1652 | AMD_PG_SUPPORT_VCE; | |
a47c78d9 | 1653 | adev->external_rev_id = adev->rev_id + 0x61; |
cde64939 | 1654 | break; |
aaa36a97 AD |
1655 | default: |
1656 | /* FIXME: not supported yet */ | |
1657 | return -EINVAL; | |
1658 | } | |
1659 | ||
a3d08fa5 FC |
1660 | if (amdgpu_smc_load_fw && smc_enabled) |
1661 | adev->firmware.smu_load = true; | |
1662 | ||
d0dd7f0c AD |
1663 | amdgpu_get_pcie_info(adev); |
1664 | ||
aaa36a97 AD |
1665 | return 0; |
1666 | } | |
1667 | ||
5fc3aeeb | 1668 | static int vi_common_sw_init(void *handle) |
aaa36a97 AD |
1669 | { |
1670 | return 0; | |
1671 | } | |
1672 | ||
5fc3aeeb | 1673 | static int vi_common_sw_fini(void *handle) |
aaa36a97 AD |
1674 | { |
1675 | return 0; | |
1676 | } | |
1677 | ||
5fc3aeeb | 1678 | static int vi_common_hw_init(void *handle) |
aaa36a97 | 1679 | { |
5fc3aeeb | 1680 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1681 | ||
aaa36a97 AD |
1682 | /* move the golden regs per IP block */ |
1683 | vi_init_golden_registers(adev); | |
1684 | /* enable pcie gen2/3 link */ | |
1685 | vi_pcie_gen3_enable(adev); | |
1686 | /* enable aspm */ | |
1687 | vi_program_aspm(adev); | |
1688 | /* enable the doorbell aperture */ | |
1689 | vi_enable_doorbell_aperture(adev, true); | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
5fc3aeeb | 1694 | static int vi_common_hw_fini(void *handle) |
aaa36a97 | 1695 | { |
5fc3aeeb | 1696 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1697 | ||
aaa36a97 AD |
1698 | /* enable the doorbell aperture */ |
1699 | vi_enable_doorbell_aperture(adev, false); | |
1700 | ||
1701 | return 0; | |
1702 | } | |
1703 | ||
5fc3aeeb | 1704 | static int vi_common_suspend(void *handle) |
aaa36a97 | 1705 | { |
5fc3aeeb | 1706 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1707 | ||
aaa36a97 AD |
1708 | return vi_common_hw_fini(adev); |
1709 | } | |
1710 | ||
5fc3aeeb | 1711 | static int vi_common_resume(void *handle) |
aaa36a97 | 1712 | { |
5fc3aeeb | 1713 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1714 | ||
aaa36a97 AD |
1715 | return vi_common_hw_init(adev); |
1716 | } | |
1717 | ||
5fc3aeeb | 1718 | static bool vi_common_is_idle(void *handle) |
aaa36a97 AD |
1719 | { |
1720 | return true; | |
1721 | } | |
1722 | ||
5fc3aeeb | 1723 | static int vi_common_wait_for_idle(void *handle) |
aaa36a97 AD |
1724 | { |
1725 | return 0; | |
1726 | } | |
1727 | ||
5fc3aeeb | 1728 | static int vi_common_soft_reset(void *handle) |
aaa36a97 | 1729 | { |
aaa36a97 AD |
1730 | return 0; |
1731 | } | |
1732 | ||
76f10b9a AD |
1733 | static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, |
1734 | bool enable) | |
6cec2655 EH |
1735 | { |
1736 | uint32_t temp, data; | |
1737 | ||
1738 | temp = data = RREG32_PCIE(ixPCIE_CNTL2); | |
1739 | ||
c90766cf | 1740 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) |
6cec2655 EH |
1741 | data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | |
1742 | PCIE_CNTL2__MST_MEM_LS_EN_MASK | | |
1743 | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; | |
1744 | else | |
1745 | data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | | |
1746 | PCIE_CNTL2__MST_MEM_LS_EN_MASK | | |
1747 | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); | |
1748 | ||
1749 | if (temp != data) | |
1750 | WREG32_PCIE(ixPCIE_CNTL2, data); | |
1751 | } | |
1752 | ||
76f10b9a AD |
1753 | static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, |
1754 | bool enable) | |
6cec2655 EH |
1755 | { |
1756 | uint32_t temp, data; | |
1757 | ||
1758 | temp = data = RREG32(mmHDP_HOST_PATH_CNTL); | |
1759 | ||
c90766cf | 1760 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) |
6cec2655 EH |
1761 | data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; |
1762 | else | |
1763 | data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; | |
1764 | ||
1765 | if (temp != data) | |
1766 | WREG32(mmHDP_HOST_PATH_CNTL, data); | |
1767 | } | |
1768 | ||
76f10b9a AD |
1769 | static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, |
1770 | bool enable) | |
6cec2655 EH |
1771 | { |
1772 | uint32_t temp, data; | |
1773 | ||
1774 | temp = data = RREG32(mmHDP_MEM_POWER_LS); | |
1775 | ||
c90766cf | 1776 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) |
6cec2655 EH |
1777 | data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; |
1778 | else | |
1779 | data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; | |
1780 | ||
1781 | if (temp != data) | |
1782 | WREG32(mmHDP_MEM_POWER_LS, data); | |
1783 | } | |
1784 | ||
76f10b9a AD |
1785 | static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, |
1786 | bool enable) | |
6cec2655 EH |
1787 | { |
1788 | uint32_t temp, data; | |
1789 | ||
1790 | temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); | |
1791 | ||
c90766cf | 1792 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) |
6cec2655 EH |
1793 | data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | |
1794 | CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); | |
1795 | else | |
1796 | data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | | |
1797 | CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; | |
1798 | ||
1799 | if (temp != data) | |
1800 | WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); | |
1801 | } | |
1802 | ||
5fc3aeeb | 1803 | static int vi_common_set_clockgating_state(void *handle, |
c90766cf | 1804 | enum amd_clockgating_state state) |
aaa36a97 | 1805 | { |
6cec2655 EH |
1806 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1807 | ||
1808 | switch (adev->asic_type) { | |
1809 | case CHIP_FIJI: | |
76f10b9a | 1810 | vi_update_bif_medium_grain_light_sleep(adev, |
6cec2655 | 1811 | state == AMD_CG_STATE_GATE ? true : false); |
76f10b9a | 1812 | vi_update_hdp_medium_grain_clock_gating(adev, |
6cec2655 | 1813 | state == AMD_CG_STATE_GATE ? true : false); |
76f10b9a | 1814 | vi_update_hdp_light_sleep(adev, |
6cec2655 | 1815 | state == AMD_CG_STATE_GATE ? true : false); |
76f10b9a AD |
1816 | vi_update_rom_medium_grain_clock_gating(adev, |
1817 | state == AMD_CG_STATE_GATE ? true : false); | |
1818 | break; | |
1819 | case CHIP_CARRIZO: | |
1820 | case CHIP_STONEY: | |
1821 | vi_update_bif_medium_grain_light_sleep(adev, | |
1822 | state == AMD_CG_STATE_GATE ? true : false); | |
1823 | vi_update_hdp_medium_grain_clock_gating(adev, | |
1824 | state == AMD_CG_STATE_GATE ? true : false); | |
1825 | vi_update_hdp_light_sleep(adev, | |
6cec2655 EH |
1826 | state == AMD_CG_STATE_GATE ? true : false); |
1827 | break; | |
1828 | default: | |
1829 | break; | |
1830 | } | |
aaa36a97 AD |
1831 | return 0; |
1832 | } | |
1833 | ||
5fc3aeeb | 1834 | static int vi_common_set_powergating_state(void *handle, |
1835 | enum amd_powergating_state state) | |
aaa36a97 AD |
1836 | { |
1837 | return 0; | |
1838 | } | |
1839 | ||
5fc3aeeb | 1840 | const struct amd_ip_funcs vi_common_ip_funcs = { |
88a907d6 | 1841 | .name = "vi_common", |
aaa36a97 AD |
1842 | .early_init = vi_common_early_init, |
1843 | .late_init = NULL, | |
1844 | .sw_init = vi_common_sw_init, | |
1845 | .sw_fini = vi_common_sw_fini, | |
1846 | .hw_init = vi_common_hw_init, | |
1847 | .hw_fini = vi_common_hw_fini, | |
1848 | .suspend = vi_common_suspend, | |
1849 | .resume = vi_common_resume, | |
1850 | .is_idle = vi_common_is_idle, | |
1851 | .wait_for_idle = vi_common_wait_for_idle, | |
1852 | .soft_reset = vi_common_soft_reset, | |
aaa36a97 AD |
1853 | .set_clockgating_state = vi_common_set_clockgating_state, |
1854 | .set_powergating_state = vi_common_set_powergating_state, | |
1855 | }; | |
1856 |