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drm/amdgpu/cik: add need_reset_on_init asic callback for CIK (v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / vi.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
aaa36a97 23#include <linux/slab.h>
248a1d6f 24#include <drm/drmP.h>
aaa36a97
AD		 25#include "amdgpu.h"
26#include "amdgpu_atombios.h"
27#include "amdgpu_ih.h"
28#include "amdgpu_uvd.h"
29#include "amdgpu_vce.h"
30#include "amdgpu_ucode.h"
31#include "atom.h"
d0dd7f0c 32#include "amd_pcie.h"
aaa36a97
AD		 33
34#include "gmc/gmc_8_1_d.h"
35#include "gmc/gmc_8_1_sh_mask.h"
36
37#include "oss/oss_3_0_d.h"
38#include "oss/oss_3_0_sh_mask.h"
39
40#include "bif/bif_5_0_d.h"
41#include "bif/bif_5_0_sh_mask.h"
42
43#include "gca/gfx_8_0_d.h"
44#include "gca/gfx_8_0_sh_mask.h"
45
46#include "smu/smu_7_1_1_d.h"
47#include "smu/smu_7_1_1_sh_mask.h"
48
49#include "uvd/uvd_5_0_d.h"
50#include "uvd/uvd_5_0_sh_mask.h"
51
52#include "vce/vce_3_0_d.h"
53#include "vce/vce_3_0_sh_mask.h"
54
55#include "dce/dce_10_0_d.h"
56#include "dce/dce_10_0_sh_mask.h"
57
58#include "vid.h"
59#include "vi.h"
60#include "vi_dpm.h"
61#include "gmc_v8_0.h"
429c45de 62#include "gmc_v7_0.h"
aaa36a97
AD		 63#include "gfx_v8_0.h"
64#include "sdma_v2_4.h"
65#include "sdma_v3_0.h"
66#include "dce_v10_0.h"
67#include "dce_v11_0.h"
68#include "iceland_ih.h"
69#include "tonga_ih.h"
70#include "cz_ih.h"
71#include "uvd_v5_0.h"
72#include "uvd_v6_0.h"
73#include "vce_v3_0.h"
a8fe58ce
MB		 74#if defined(CONFIG_DRM_AMD_ACP)
75#include "amdgpu_acp.h"
76#endif
e9ed3a67 77#include "dce_virtual.h"
99581cc5 78#include "mxgpu_vi.h"
4562236b 79#include "amdgpu_dm.h"
aaa36a97
AD		 80
81/*
82 * Indirect registers accessor
83 */
84static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
85{
86 unsigned long flags;
87 u32 r;
88
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
07944623
ED		 90 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
91 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
92 r = RREG32_NO_KIQ(mmPCIE_DATA);
aaa36a97
AD		 93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
94 return r;
95}
96
97static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
98{
99 unsigned long flags;
100
101 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
07944623
ED		 102 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
103 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
104 WREG32_NO_KIQ(mmPCIE_DATA, v);
105 (void)RREG32_NO_KIQ(mmPCIE_DATA);
aaa36a97
AD		 106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
107}
108
109static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
110{
111 unsigned long flags;
112 u32 r;
113
114 spin_lock_irqsave(&adev->smc_idx_lock, flags);
fa1d04e9
YT		 115 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
116 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
aaa36a97
AD		 117 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
118 return r;
119}
120
121static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
122{
123 unsigned long flags;
124
125 spin_lock_irqsave(&adev->smc_idx_lock, flags);
07944623
ED		 126 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
127 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
aaa36a97
AD		 128 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
129}
130
7b92cdbf
AD		 131/* smu_8_0_d.h */
132#define mmMP0PUB_IND_INDEX 0x180
133#define mmMP0PUB_IND_DATA 0x181
134
135static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
136{
137 unsigned long flags;
138 u32 r;
139
140 spin_lock_irqsave(&adev->smc_idx_lock, flags);
141 WREG32(mmMP0PUB_IND_INDEX, (reg));
142 r = RREG32(mmMP0PUB_IND_DATA);
143 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
144 return r;
145}
146
147static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
148{
149 unsigned long flags;
150
151 spin_lock_irqsave(&adev->smc_idx_lock, flags);
152 WREG32(mmMP0PUB_IND_INDEX, (reg));
153 WREG32(mmMP0PUB_IND_DATA, (v));
154 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
155}
156
aaa36a97
AD		 157static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
158{
159 unsigned long flags;
160 u32 r;
161
162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
163 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
164 r = RREG32(mmUVD_CTX_DATA);
165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
166 return r;
167}
168
169static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
170{
171 unsigned long flags;
172
173 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
174 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
175 WREG32(mmUVD_CTX_DATA, (v));
176 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
177}
178
179static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
180{
181 unsigned long flags;
182 u32 r;
183
184 spin_lock_irqsave(&adev->didt_idx_lock, flags);
185 WREG32(mmDIDT_IND_INDEX, (reg));
186 r = RREG32(mmDIDT_IND_DATA);
187 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
188 return r;
189}
190
191static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
192{
193 unsigned long flags;
194
195 spin_lock_irqsave(&adev->didt_idx_lock, flags);
196 WREG32(mmDIDT_IND_INDEX, (reg));
197 WREG32(mmDIDT_IND_DATA, (v));
198 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
199}
200
ccdbb20a
RZ		 201static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
202{
203 unsigned long flags;
204 u32 r;
205
206 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
207 WREG32(mmGC_CAC_IND_INDEX, (reg));
208 r = RREG32(mmGC_CAC_IND_DATA);
209 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
210 return r;
211}
212
213static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
214{
215 unsigned long flags;
216
217 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
218 WREG32(mmGC_CAC_IND_INDEX, (reg));
219 WREG32(mmGC_CAC_IND_DATA, (v));
220 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
221}
222
223
aaa36a97
AD		 224static const u32 tonga_mgcg_cgcg_init[] =
225{
226 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
227 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
228 mmPCIE_DATA, 0x000f0000, 0x00000000,
229 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
230 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
aaa36a97
AD		 231 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
232 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
233};
234
48299f95
DZ		 235static const u32 fiji_mgcg_cgcg_init[] =
236{
237 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
238 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
239 mmPCIE_DATA, 0x000f0000, 0x00000000,
240 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
241 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
242 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
243 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
244};
245
aaa36a97
AD		 246static const u32 iceland_mgcg_cgcg_init[] =
247{
248 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
249 mmPCIE_DATA, 0x000f0000, 0x00000000,
250 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
251 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
252 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
253};
254
255static const u32 cz_mgcg_cgcg_init[] =
256{
257 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
258 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
259 mmPCIE_DATA, 0x000f0000, 0x00000000,
aaa36a97
AD		 260 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
261 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
262};
263
39bb0c92
SL		 264static const u32 stoney_mgcg_cgcg_init[] =
265{
266 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
267 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
268 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
269};
270
aaa36a97
AD		 271static void vi_init_golden_registers(struct amdgpu_device *adev)
272{
273 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
274 mutex_lock(&adev->grbm_idx_mutex);
275
99581cc5
XY		 276 if (amdgpu_sriov_vf(adev)) {
277 xgpu_vi_init_golden_registers(adev);
278 mutex_unlock(&adev->grbm_idx_mutex);
279 return;
280 }
281
aaa36a97
AD		 282 switch (adev->asic_type) {
283 case CHIP_TOPAZ:
9c3f2b54
AD		 284 amdgpu_device_program_register_sequence(adev,
285 iceland_mgcg_cgcg_init,
286 ARRAY_SIZE(iceland_mgcg_cgcg_init));
aaa36a97 287 break;
48299f95 288 case CHIP_FIJI:
9c3f2b54
AD		 289 amdgpu_device_program_register_sequence(adev,
290 fiji_mgcg_cgcg_init,
291 ARRAY_SIZE(fiji_mgcg_cgcg_init));
48299f95 292 break;
aaa36a97 293 case CHIP_TONGA:
9c3f2b54
AD		 294 amdgpu_device_program_register_sequence(adev,
295 tonga_mgcg_cgcg_init,
296 ARRAY_SIZE(tonga_mgcg_cgcg_init));
aaa36a97
AD		 297 break;
298 case CHIP_CARRIZO:
9c3f2b54
AD		 299 amdgpu_device_program_register_sequence(adev,
300 cz_mgcg_cgcg_init,
301 ARRAY_SIZE(cz_mgcg_cgcg_init));
aaa36a97 302 break;
39bb0c92 303 case CHIP_STONEY:
9c3f2b54
AD		 304 amdgpu_device_program_register_sequence(adev,
305 stoney_mgcg_cgcg_init,
306 ARRAY_SIZE(stoney_mgcg_cgcg_init));
39bb0c92 307 break;
2cc0c0b5 308 case CHIP_POLARIS10:
b51c5194 309 case CHIP_POLARIS11:
c4642a47 310 case CHIP_POLARIS12:
b51c5194 311 case CHIP_VEGAM:
aaa36a97
AD		 312 default:
313 break;
314 }
315 mutex_unlock(&adev->grbm_idx_mutex);
316}
317
318/**
319 * vi_get_xclk - get the xclk
320 *
321 * @adev: amdgpu_device pointer
322 *
323 * Returns the reference clock used by the gfx engine
324 * (VI).
325 */
326static u32 vi_get_xclk(struct amdgpu_device *adev)
327{
328 u32 reference_clock = adev->clock.spll.reference_freq;
329 u32 tmp;
330
2f7d10b3 331 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 332 return reference_clock;
333
334 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
335 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
336 return 1000;
337
338 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
339 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
340 return reference_clock / 4;
341
342 return reference_clock;
343}
344
345/**
346 * vi_srbm_select - select specific register instances
347 *
348 * @adev: amdgpu_device pointer
349 * @me: selected ME (micro engine)
350 * @pipe: pipe
351 * @queue: queue
352 * @vmid: VMID
353 *
354 * Switches the currently active registers instances. Some
355 * registers are instanced per VMID, others are instanced per
356 * me/pipe/queue combination.
357 */
358void vi_srbm_select(struct amdgpu_device *adev,
359 u32 me, u32 pipe, u32 queue, u32 vmid)
360{
361 u32 srbm_gfx_cntl = 0;
362 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
365 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
366 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
367}
368
369static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
370{
371 /* todo */
372}
373
374static bool vi_read_disabled_bios(struct amdgpu_device *adev)
375{
376 u32 bus_cntl;
377 u32 d1vga_control = 0;
378 u32 d2vga_control = 0;
379 u32 vga_render_control = 0;
380 u32 rom_cntl;
381 bool r;
382
383 bus_cntl = RREG32(mmBUS_CNTL);
384 if (adev->mode_info.num_crtc) {
385 d1vga_control = RREG32(mmD1VGA_CONTROL);
386 d2vga_control = RREG32(mmD2VGA_CONTROL);
387 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
388 }
389 rom_cntl = RREG32_SMC(ixROM_CNTL);
390
391 /* enable the rom */
392 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
393 if (adev->mode_info.num_crtc) {
394 /* Disable VGA mode */
395 WREG32(mmD1VGA_CONTROL,
396 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
397 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
398 WREG32(mmD2VGA_CONTROL,
399 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
400 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
401 WREG32(mmVGA_RENDER_CONTROL,
402 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
403 }
404 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
405
406 r = amdgpu_read_bios(adev);
407
408 /* restore regs */
409 WREG32(mmBUS_CNTL, bus_cntl);
410 if (adev->mode_info.num_crtc) {
411 WREG32(mmD1VGA_CONTROL, d1vga_control);
412 WREG32(mmD2VGA_CONTROL, d2vga_control);
413 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
414 }
415 WREG32_SMC(ixROM_CNTL, rom_cntl);
416 return r;
417}
95addb2a
AD		 418
419static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
420 u8 *bios, u32 length_bytes)
421{
422 u32 *dw_ptr;
423 unsigned long flags;
424 u32 i, length_dw;
425
426 if (bios == NULL)
427 return false;
428 if (length_bytes == 0)
429 return false;
430 /* APU vbios image is part of sbios image */
431 if (adev->flags & AMD_IS_APU)
432 return false;
433
434 dw_ptr = (u32 *)bios;
435 length_dw = ALIGN(length_bytes, 4) / 4;
436 /* take the smc lock since we are using the smc index */
437 spin_lock_irqsave(&adev->smc_idx_lock, flags);
438 /* set rom index to 0 */
4bc10d16
ML		 439 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
440 WREG32(mmSMC_IND_DATA_11, 0);
95addb2a 441 /* set index to data for continous read */
4bc10d16 442 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
95addb2a 443 for (i = 0; i < length_dw; i++)
4bc10d16 444 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
95addb2a
AD		 445 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
446
447 return true;
448}
449
4e99a44e 450static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
048765ad 451{
57ad33a3
AD		 452 uint32_t reg = 0;
453
454 if (adev->asic_type == CHIP_TONGA ||
455 adev->asic_type == CHIP_FIJI) {
456 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
457 /* bit0: 0 means pf and 1 means vf */
04a0d2d9 458 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
57ad33a3 459 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
04a0d2d9
AD		 460 /* bit31: 0 means disable IOV and 1 means enable */
461 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
57ad33a3
AD		 462 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
463 }
4e99a44e
ML		 464
465 if (reg == 0) {
466 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
5a5099cb 467 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
4e99a44e 468 }
048765ad
AR		 469}
470
eca2240f 471static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
97fcc76b
CK		 472 {mmGRBM_STATUS},
473 {mmGRBM_STATUS2},
474 {mmGRBM_STATUS_SE0},
475 {mmGRBM_STATUS_SE1},
476 {mmGRBM_STATUS_SE2},
477 {mmGRBM_STATUS_SE3},
478 {mmSRBM_STATUS},
479 {mmSRBM_STATUS2},
480 {mmSRBM_STATUS3},
481 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
482 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
483 {mmCP_STAT},
484 {mmCP_STALLED_STAT1},
485 {mmCP_STALLED_STAT2},
486 {mmCP_STALLED_STAT3},
487 {mmCP_CPF_BUSY_STAT},
488 {mmCP_CPF_STALLED_STAT1},
489 {mmCP_CPF_STATUS},
490 {mmCP_CPC_BUSY_STAT},
491 {mmCP_CPC_STALLED_STAT1},
492 {mmCP_CPC_STATUS},
493 {mmGB_ADDR_CONFIG},
494 {mmMC_ARB_RAMCFG},
495 {mmGB_TILE_MODE0},
496 {mmGB_TILE_MODE1},
497 {mmGB_TILE_MODE2},
498 {mmGB_TILE_MODE3},
499 {mmGB_TILE_MODE4},
500 {mmGB_TILE_MODE5},
501 {mmGB_TILE_MODE6},
502 {mmGB_TILE_MODE7},
503 {mmGB_TILE_MODE8},
504 {mmGB_TILE_MODE9},
505 {mmGB_TILE_MODE10},
506 {mmGB_TILE_MODE11},
507 {mmGB_TILE_MODE12},
508 {mmGB_TILE_MODE13},
509 {mmGB_TILE_MODE14},
510 {mmGB_TILE_MODE15},
511 {mmGB_TILE_MODE16},
512 {mmGB_TILE_MODE17},
513 {mmGB_TILE_MODE18},
514 {mmGB_TILE_MODE19},
515 {mmGB_TILE_MODE20},
516 {mmGB_TILE_MODE21},
517 {mmGB_TILE_MODE22},
518 {mmGB_TILE_MODE23},
519 {mmGB_TILE_MODE24},
520 {mmGB_TILE_MODE25},
521 {mmGB_TILE_MODE26},
522 {mmGB_TILE_MODE27},
523 {mmGB_TILE_MODE28},
524 {mmGB_TILE_MODE29},
525 {mmGB_TILE_MODE30},
526 {mmGB_TILE_MODE31},
527 {mmGB_MACROTILE_MODE0},
528 {mmGB_MACROTILE_MODE1},
529 {mmGB_MACROTILE_MODE2},
530 {mmGB_MACROTILE_MODE3},
531 {mmGB_MACROTILE_MODE4},
532 {mmGB_MACROTILE_MODE5},
533 {mmGB_MACROTILE_MODE6},
534 {mmGB_MACROTILE_MODE7},
535 {mmGB_MACROTILE_MODE8},
536 {mmGB_MACROTILE_MODE9},
537 {mmGB_MACROTILE_MODE10},
538 {mmGB_MACROTILE_MODE11},
539 {mmGB_MACROTILE_MODE12},
540 {mmGB_MACROTILE_MODE13},
541 {mmGB_MACROTILE_MODE14},
542 {mmGB_MACROTILE_MODE15},
543 {mmCC_RB_BACKEND_DISABLE, true},
544 {mmGC_USER_RB_BACKEND_DISABLE, true},
545 {mmGB_BACKEND_MAP, false},
546 {mmPA_SC_RASTER_CONFIG, true},
547 {mmPA_SC_RASTER_CONFIG_1, true},
aaa36a97
AD		 548};
549
db9635cc
AD		 550static uint32_t vi_get_register_value(struct amdgpu_device *adev,
551 bool indexed, u32 se_num,
552 u32 sh_num, u32 reg_offset)
aaa36a97 553{
db9635cc
AD		 554 if (indexed) {
555 uint32_t val;
556 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
557 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
558
559 switch (reg_offset) {
560 case mmCC_RB_BACKEND_DISABLE:
561 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
562 case mmGC_USER_RB_BACKEND_DISABLE:
563 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
564 case mmPA_SC_RASTER_CONFIG:
565 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
566 case mmPA_SC_RASTER_CONFIG_1:
567 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
568 }
aaa36a97 569
db9635cc
AD		 570 mutex_lock(&adev->grbm_idx_mutex);
571 if (se_num != 0xffffffff || sh_num != 0xffffffff)
572 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
573
574 val = RREG32(reg_offset);
575
576 if (se_num != 0xffffffff || sh_num != 0xffffffff)
577 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
578 mutex_unlock(&adev->grbm_idx_mutex);
579 return val;
580 } else {
581 unsigned idx;
582
583 switch (reg_offset) {
584 case mmGB_ADDR_CONFIG:
585 return adev->gfx.config.gb_addr_config;
586 case mmMC_ARB_RAMCFG:
587 return adev->gfx.config.mc_arb_ramcfg;
588 case mmGB_TILE_MODE0:
589 case mmGB_TILE_MODE1:
590 case mmGB_TILE_MODE2:
591 case mmGB_TILE_MODE3:
592 case mmGB_TILE_MODE4:
593 case mmGB_TILE_MODE5:
594 case mmGB_TILE_MODE6:
595 case mmGB_TILE_MODE7:
596 case mmGB_TILE_MODE8:
597 case mmGB_TILE_MODE9:
598 case mmGB_TILE_MODE10:
599 case mmGB_TILE_MODE11:
600 case mmGB_TILE_MODE12:
601 case mmGB_TILE_MODE13:
602 case mmGB_TILE_MODE14:
603 case mmGB_TILE_MODE15:
604 case mmGB_TILE_MODE16:
605 case mmGB_TILE_MODE17:
606 case mmGB_TILE_MODE18:
607 case mmGB_TILE_MODE19:
608 case mmGB_TILE_MODE20:
609 case mmGB_TILE_MODE21:
610 case mmGB_TILE_MODE22:
611 case mmGB_TILE_MODE23:
612 case mmGB_TILE_MODE24:
613 case mmGB_TILE_MODE25:
614 case mmGB_TILE_MODE26:
615 case mmGB_TILE_MODE27:
616 case mmGB_TILE_MODE28:
617 case mmGB_TILE_MODE29:
618 case mmGB_TILE_MODE30:
619 case mmGB_TILE_MODE31:
620 idx = (reg_offset - mmGB_TILE_MODE0);
621 return adev->gfx.config.tile_mode_array[idx];
622 case mmGB_MACROTILE_MODE0:
623 case mmGB_MACROTILE_MODE1:
624 case mmGB_MACROTILE_MODE2:
625 case mmGB_MACROTILE_MODE3:
626 case mmGB_MACROTILE_MODE4:
627 case mmGB_MACROTILE_MODE5:
628 case mmGB_MACROTILE_MODE6:
629 case mmGB_MACROTILE_MODE7:
630 case mmGB_MACROTILE_MODE8:
631 case mmGB_MACROTILE_MODE9:
632 case mmGB_MACROTILE_MODE10:
633 case mmGB_MACROTILE_MODE11:
634 case mmGB_MACROTILE_MODE12:
635 case mmGB_MACROTILE_MODE13:
636 case mmGB_MACROTILE_MODE14:
637 case mmGB_MACROTILE_MODE15:
638 idx = (reg_offset - mmGB_MACROTILE_MODE0);
639 return adev->gfx.config.macrotile_mode_array[idx];
640 default:
641 return RREG32(reg_offset);
642 }
643 }
aaa36a97
AD		 644}
645
646static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
647 u32 sh_num, u32 reg_offset, u32 *value)
648{
3032f350 649 uint32_t i;
aaa36a97
AD		 650
651 *value = 0;
aaa36a97 652 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
97fcc76b
CK		 653 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
654
aaa36a97
AD		 655 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
656 continue;
657
97fcc76b
CK		 658 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
659 reg_offset);
aaa36a97
AD		 660 return 0;
661 }
662 return -EINVAL;
663}
664
89a31827 665static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
aaa36a97 666{
a2c5c698 667 u32 i;
aaa36a97
AD		 668
669 dev_info(adev->dev, "GPU pci config reset\n");
670
aaa36a97
AD		 671 /* disable BM */
672 pci_clear_master(adev->pdev);
673 /* reset */
8111c387 674 amdgpu_device_pci_config_reset(adev);
aaa36a97
AD		 675
676 udelay(100);
677
678 /* wait for asic to come out of reset */
679 for (i = 0; i < adev->usec_timeout; i++) {
b314f9a9
CZ		 680 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
681 /* enable BM */
682 pci_set_master(adev->pdev);
c836fec5 683 adev->has_hw_reset = true;
89a31827 684 return 0;
b314f9a9 685 }
aaa36a97
AD		 686 udelay(1);
687 }
89a31827 688 return -EINVAL;
aaa36a97
AD		 689}
690
aaa36a97
AD		 691/**
692 * vi_asic_reset - soft reset GPU
693 *
694 * @adev: amdgpu_device pointer
695 *
696 * Look up which blocks are hung and attempt
697 * to reset them.
698 * Returns 0 for success.
699 */
700static int vi_asic_reset(struct amdgpu_device *adev)
701{
89a31827
CZ		 702 int r;
703
72a57438 704 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
aaa36a97 705
89a31827 706 r = vi_gpu_pci_config_reset(adev);
aaa36a97 707
72a57438 708 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
aaa36a97 709
89a31827 710 return r;
aaa36a97
AD		 711}
712
bbf282d8
AD		 713static u32 vi_get_config_memsize(struct amdgpu_device *adev)
714{
715 return RREG32(mmCONFIG_MEMSIZE);
716}
717
aaa36a97
AD		 718static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
719 u32 cntl_reg, u32 status_reg)
720{
721 int r, i;
722 struct atom_clock_dividers dividers;
723 uint32_t tmp;
724
725 r = amdgpu_atombios_get_clock_dividers(adev,
726 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
727 clock, false, &dividers);
728 if (r)
729 return r;
730
731 tmp = RREG32_SMC(cntl_reg);
819a23f8
RZ		 732
733 if (adev->flags & AMD_IS_APU)
734 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
735 else
736 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
737 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
aaa36a97
AD		 738 tmp |= dividers.post_divider;
739 WREG32_SMC(cntl_reg, tmp);
740
741 for (i = 0; i < 100; i++) {
819a23f8
RZ		 742 tmp = RREG32_SMC(status_reg);
743 if (adev->flags & AMD_IS_APU) {
744 if (tmp & 0x10000)
745 break;
746 } else {
747 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
748 break;
749 }
aaa36a97
AD		 750 mdelay(10);
751 }
752 if (i == 100)
753 return -ETIMEDOUT;
aaa36a97
AD		 754 return 0;
755}
756
819a23f8
RZ		 757#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
758#define ixGNB_CLK1_STATUS 0xD822010C
759#define ixGNB_CLK2_DFS_CNTL 0xD8220110
760#define ixGNB_CLK2_STATUS 0xD822012C
08ebb6e9
RZ		 761#define ixGNB_CLK3_DFS_CNTL 0xD8220130
762#define ixGNB_CLK3_STATUS 0xD822014C
819a23f8 763
aaa36a97
AD		 764static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
765{
766 int r;
767
819a23f8
RZ		 768 if (adev->flags & AMD_IS_APU) {
769 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
770 if (r)
771 return r;
aaa36a97 772
819a23f8
RZ		 773 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
774 if (r)
775 return r;
776 } else {
777 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
778 if (r)
779 return r;
780
781 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
782 if (r)
783 return r;
784 }
aaa36a97
AD		 785
786 return 0;
787}
788
789static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
790{
714b1f53
RZ		 791 int r, i;
792 struct atom_clock_dividers dividers;
793 u32 tmp;
08ebb6e9
RZ		 794 u32 reg_ctrl;
795 u32 reg_status;
796 u32 status_mask;
797 u32 reg_mask;
798
799 if (adev->flags & AMD_IS_APU) {
800 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
801 reg_status = ixGNB_CLK3_STATUS;
802 status_mask = 0x00010000;
803 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
804 } else {
805 reg_ctrl = ixCG_ECLK_CNTL;
806 reg_status = ixCG_ECLK_STATUS;
807 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
808 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
809 }
714b1f53
RZ		 810
811 r = amdgpu_atombios_get_clock_dividers(adev,
812 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
813 ecclk, false, &dividers);
814 if (r)
815 return r;
816
817 for (i = 0; i < 100; i++) {
08ebb6e9 818 if (RREG32_SMC(reg_status) & status_mask)
714b1f53
RZ		 819 break;
820 mdelay(10);
821 }
08ebb6e9 822
714b1f53
RZ		 823 if (i == 100)
824 return -ETIMEDOUT;
825
08ebb6e9
RZ		 826 tmp = RREG32_SMC(reg_ctrl);
827 tmp &= ~reg_mask;
714b1f53 828 tmp |= dividers.post_divider;
08ebb6e9 829 WREG32_SMC(reg_ctrl, tmp);
714b1f53
RZ		 830
831 for (i = 0; i < 100; i++) {
08ebb6e9 832 if (RREG32_SMC(reg_status) & status_mask)
714b1f53
RZ		 833 break;
834 mdelay(10);
835 }
08ebb6e9 836
714b1f53
RZ		 837 if (i == 100)
838 return -ETIMEDOUT;
aaa36a97
AD		 839
840 return 0;
841}
842
843static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
844{
e79d5c08
AD		 845 if (pci_is_root_bus(adev->pdev->bus))
846 return;
847
aaa36a97
AD		 848 if (amdgpu_pcie_gen2 == 0)
849 return;
850
2f7d10b3 851 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 852 return;
853
d0dd7f0c
AD		 854 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
855 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
aaa36a97
AD		 856 return;
857
858 /* todo */
859}
860
861static void vi_program_aspm(struct amdgpu_device *adev)
862{
863
864 if (amdgpu_aspm == 0)
865 return;
866
867 /* todo */
868}
869
870static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
871 bool enable)
872{
873 u32 tmp;
874
875 /* not necessary on CZ */
2f7d10b3 876 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 877 return;
878
879 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
880 if (enable)
881 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
882 else
883 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
884
885 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
886}
887
39bb0c92
SL		 888#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
889#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
890#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
891
aaa36a97
AD		 892static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
893{
abdfb850 894 if (adev->flags & AMD_IS_APU)
39bb0c92
SL		 895 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
896 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
aaa36a97 897 else
abdfb850
FC		 898 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
899 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
aaa36a97
AD		 900}
901
69882565 902static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
dd8d07f2 903{
69882565
CK		 904 if (!ring || !ring->funcs->emit_wreg) {
905 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
906 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
907 } else {
908 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
909 }
dd8d07f2
AD		 910}
911
69882565
CK		 912static void vi_invalidate_hdp(struct amdgpu_device *adev,
913 struct amdgpu_ring *ring)
dd8d07f2 914{
69882565
CK		 915 if (!ring || !ring->funcs->emit_wreg) {
916 WREG32(mmHDP_DEBUG0, 1);
917 RREG32(mmHDP_DEBUG0);
918 } else {
919 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
920 }
dd8d07f2
AD		 921}
922
06082d9b
AD		 923static bool vi_need_full_reset(struct amdgpu_device *adev)
924{
925 switch (adev->asic_type) {
926 case CHIP_CARRIZO:
927 case CHIP_STONEY:
928 /* CZ has hang issues with full reset at the moment */
929 return false;
930 case CHIP_FIJI:
931 case CHIP_TONGA:
932 /* XXX: soft reset should work on fiji and tonga */
933 return true;
934 case CHIP_POLARIS10:
935 case CHIP_POLARIS11:
936 case CHIP_POLARIS12:
937 case CHIP_TOPAZ:
938 default:
939 /* change this when we support soft reset */
940 return true;
941 }
942}
943
b45e18ac
KR		 944static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
945 uint64_t *count1)
946{
947 uint32_t perfctr = 0;
948 uint64_t cnt0_of, cnt1_of;
949 int tmp;
950
951 /* This reports 0 on APUs, so return to avoid writing/reading registers
952 * that may or may not be different from their GPU counterparts
953 */
954 if (adev->flags & AMD_IS_APU)
955 return;
956
957 /* Set the 2 events that we wish to watch, defined above */
958 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
959 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
960 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
961
962 /* Write to enable desired perf counters */
963 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
964 /* Zero out and enable the perf counters
965 * Write 0x5:
966 * Bit 0 = Start all counters(1)
967 * Bit 2 = Global counter reset enable(1)
968 */
969 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
970
971 msleep(1000);
972
973 /* Load the shadow and disable the perf counters
974 * Write 0x2:
975 * Bit 0 = Stop counters(0)
976 * Bit 1 = Load the shadow counters(1)
977 */
978 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
979
980 /* Read register values to get any >32bit overflow */
981 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
982 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
983 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
984
985 /* Get the values and add the overflow */
986 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
987 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
988}
989
aaa36a97
AD		 990static const struct amdgpu_asic_funcs vi_asic_funcs =
991{
992 .read_disabled_bios = &vi_read_disabled_bios,
95addb2a 993 .read_bios_from_rom = &vi_read_bios_from_rom,
aaa36a97
AD		 994 .read_register = &vi_read_register,
995 .reset = &vi_asic_reset,
996 .set_vga_state = &vi_vga_set_state,
997 .get_xclk = &vi_get_xclk,
998 .set_uvd_clocks = &vi_set_uvd_clocks,
999 .set_vce_clocks = &vi_set_vce_clocks,
bbf282d8 1000 .get_config_memsize = &vi_get_config_memsize,
dd8d07f2
AD		 1001 .flush_hdp = &vi_flush_hdp,
1002 .invalidate_hdp = &vi_invalidate_hdp,
06082d9b 1003 .need_full_reset = &vi_need_full_reset,
4e2c1ac2 1004 .init_doorbell_index = &legacy_doorbell_index_init,
b45e18ac 1005 .get_pcie_usage = &vi_get_pcie_usage,
aaa36a97
AD		 1006};
1007
170d6e94
EH		 1008#define CZ_REV_BRISTOL(rev) \
1009 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1010
5fc3aeeb 1011static int vi_common_early_init(void *handle)
aaa36a97 1012{
5fc3aeeb 1013 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 1014
2f7d10b3 1015 if (adev->flags & AMD_IS_APU) {
7b92cdbf
AD		 1016 adev->smc_rreg = &cz_smc_rreg;
1017 adev->smc_wreg = &cz_smc_wreg;
1018 } else {
1019 adev->smc_rreg = &vi_smc_rreg;
1020 adev->smc_wreg = &vi_smc_wreg;
1021 }
aaa36a97
AD		 1022 adev->pcie_rreg = &vi_pcie_rreg;
1023 adev->pcie_wreg = &vi_pcie_wreg;
1024 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1025 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1026 adev->didt_rreg = &vi_didt_rreg;
1027 adev->didt_wreg = &vi_didt_wreg;
ccdbb20a
RZ		 1028 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1029 adev->gc_cac_wreg = &vi_gc_cac_wreg;
aaa36a97
AD		 1030
1031 adev->asic_funcs = &vi_asic_funcs;
1032
aaa36a97
AD		 1033 adev->rev_id = vi_get_rev_id(adev);
1034 adev->external_rev_id = 0xFF;
1035 switch (adev->asic_type) {
1036 case CHIP_TOPAZ:
aaa36a97
AD		 1037 adev->cg_flags = 0;
1038 adev->pg_flags = 0;
1039 adev->external_rev_id = 0x1;
aaa36a97 1040 break;
48299f95 1041 case CHIP_FIJI:
14698b6c
AD		 1042 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1043 AMD_CG_SUPPORT_GFX_MGLS |
1044 AMD_CG_SUPPORT_GFX_RLC_LS |
1045 AMD_CG_SUPPORT_GFX_CP_LS |
1046 AMD_CG_SUPPORT_GFX_CGTS |
1047 AMD_CG_SUPPORT_GFX_CGTS_LS |
1048 AMD_CG_SUPPORT_GFX_CGCG |
e08d53cb
AD		 1049 AMD_CG_SUPPORT_GFX_CGLS |
1050 AMD_CG_SUPPORT_SDMA_MGCG |
c90766cf
AD		 1051 AMD_CG_SUPPORT_SDMA_LS |
1052 AMD_CG_SUPPORT_BIF_LS |
1053 AMD_CG_SUPPORT_HDP_MGCG |
1054 AMD_CG_SUPPORT_HDP_LS |
3fde56b8
AD		 1055 AMD_CG_SUPPORT_ROM_MGCG |
1056 AMD_CG_SUPPORT_MC_MGCG |
79abf1ad
RZ		 1057 AMD_CG_SUPPORT_MC_LS |
1058 AMD_CG_SUPPORT_UVD_MGCG;
b6bc28ff
FC		 1059 adev->pg_flags = 0;
1060 adev->external_rev_id = adev->rev_id + 0x3c;
1061 break;
aaa36a97 1062 case CHIP_TONGA:
ca18b849
RZ		 1063 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1064 AMD_CG_SUPPORT_GFX_CGCG |
1065 AMD_CG_SUPPORT_GFX_CGLS |
1066 AMD_CG_SUPPORT_SDMA_MGCG |
1067 AMD_CG_SUPPORT_SDMA_LS |
1068 AMD_CG_SUPPORT_BIF_LS |
1069 AMD_CG_SUPPORT_HDP_MGCG |
1070 AMD_CG_SUPPORT_HDP_LS |
1071 AMD_CG_SUPPORT_ROM_MGCG |
1072 AMD_CG_SUPPORT_MC_MGCG |
1073 AMD_CG_SUPPORT_MC_LS |
1074 AMD_CG_SUPPORT_DRM_LS |
1075 AMD_CG_SUPPORT_UVD_MGCG;
54971406 1076 adev->pg_flags = 0;
aaa36a97 1077 adev->external_rev_id = adev->rev_id + 0x14;
aaa36a97 1078 break;
2cc0c0b5 1079 case CHIP_POLARIS11:
ca18b849
RZ		 1080 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1081 AMD_CG_SUPPORT_GFX_RLC_LS |
1082 AMD_CG_SUPPORT_GFX_CP_LS |
1083 AMD_CG_SUPPORT_GFX_CGCG |
1084 AMD_CG_SUPPORT_GFX_CGLS |
1085 AMD_CG_SUPPORT_GFX_3D_CGCG |
1086 AMD_CG_SUPPORT_GFX_3D_CGLS |
1087 AMD_CG_SUPPORT_SDMA_MGCG |
1088 AMD_CG_SUPPORT_SDMA_LS |
1089 AMD_CG_SUPPORT_BIF_MGCG |
1090 AMD_CG_SUPPORT_BIF_LS |
1091 AMD_CG_SUPPORT_HDP_MGCG |
1092 AMD_CG_SUPPORT_HDP_LS |
1093 AMD_CG_SUPPORT_ROM_MGCG |
1094 AMD_CG_SUPPORT_MC_MGCG |
1095 AMD_CG_SUPPORT_MC_LS |
1096 AMD_CG_SUPPORT_DRM_LS |
1097 AMD_CG_SUPPORT_UVD_MGCG |
ecc2cf7c 1098 AMD_CG_SUPPORT_VCE_MGCG;
c0c1f579
FC		 1099 adev->pg_flags = 0;
1100 adev->external_rev_id = adev->rev_id + 0x5A;
1101 break;
2cc0c0b5 1102 case CHIP_POLARIS10:
ca18b849
RZ		 1103 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1104 AMD_CG_SUPPORT_GFX_RLC_LS |
1105 AMD_CG_SUPPORT_GFX_CP_LS |
1106 AMD_CG_SUPPORT_GFX_CGCG |
1107 AMD_CG_SUPPORT_GFX_CGLS |
1108 AMD_CG_SUPPORT_GFX_3D_CGCG |
1109 AMD_CG_SUPPORT_GFX_3D_CGLS |
1110 AMD_CG_SUPPORT_SDMA_MGCG |
1111 AMD_CG_SUPPORT_SDMA_LS |
1112 AMD_CG_SUPPORT_BIF_MGCG |
1113 AMD_CG_SUPPORT_BIF_LS |
1114 AMD_CG_SUPPORT_HDP_MGCG |
1115 AMD_CG_SUPPORT_HDP_LS |
1116 AMD_CG_SUPPORT_ROM_MGCG |
1117 AMD_CG_SUPPORT_MC_MGCG |
1118 AMD_CG_SUPPORT_MC_LS |
1119 AMD_CG_SUPPORT_DRM_LS |
1120 AMD_CG_SUPPORT_UVD_MGCG |
ecc2cf7c 1121 AMD_CG_SUPPORT_VCE_MGCG;
c0c1f579
FC		 1122 adev->pg_flags = 0;
1123 adev->external_rev_id = adev->rev_id + 0x50;
1124 break;
c4642a47 1125 case CHIP_POLARIS12:
739e9fff
RZ		 1126 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1127 AMD_CG_SUPPORT_GFX_RLC_LS |
1128 AMD_CG_SUPPORT_GFX_CP_LS |
1129 AMD_CG_SUPPORT_GFX_CGCG |
1130 AMD_CG_SUPPORT_GFX_CGLS |
1131 AMD_CG_SUPPORT_GFX_3D_CGCG |
1132 AMD_CG_SUPPORT_GFX_3D_CGLS |
1133 AMD_CG_SUPPORT_SDMA_MGCG |
1134 AMD_CG_SUPPORT_SDMA_LS |
1135 AMD_CG_SUPPORT_BIF_MGCG |
1136 AMD_CG_SUPPORT_BIF_LS |
1137 AMD_CG_SUPPORT_HDP_MGCG |
1138 AMD_CG_SUPPORT_HDP_LS |
1139 AMD_CG_SUPPORT_ROM_MGCG |
1140 AMD_CG_SUPPORT_MC_MGCG |
1141 AMD_CG_SUPPORT_MC_LS |
1142 AMD_CG_SUPPORT_DRM_LS |
1143 AMD_CG_SUPPORT_UVD_MGCG |
1144 AMD_CG_SUPPORT_VCE_MGCG;
c4642a47
JZ		 1145 adev->pg_flags = 0;
1146 adev->external_rev_id = adev->rev_id + 0x64;
1147 break;
b51c5194
LL		 1148 case CHIP_VEGAM:
1149 adev->cg_flags = 0;
1150 /*AMD_CG_SUPPORT_GFX_MGCG |
1151 AMD_CG_SUPPORT_GFX_RLC_LS |
1152 AMD_CG_SUPPORT_GFX_CP_LS |
1153 AMD_CG_SUPPORT_GFX_CGCG |
1154 AMD_CG_SUPPORT_GFX_CGLS |
1155 AMD_CG_SUPPORT_GFX_3D_CGCG |
1156 AMD_CG_SUPPORT_GFX_3D_CGLS |
1157 AMD_CG_SUPPORT_SDMA_MGCG |
1158 AMD_CG_SUPPORT_SDMA_LS |
1159 AMD_CG_SUPPORT_BIF_MGCG |
1160 AMD_CG_SUPPORT_BIF_LS |
1161 AMD_CG_SUPPORT_HDP_MGCG |
1162 AMD_CG_SUPPORT_HDP_LS |
1163 AMD_CG_SUPPORT_ROM_MGCG |
1164 AMD_CG_SUPPORT_MC_MGCG |
1165 AMD_CG_SUPPORT_MC_LS |
1166 AMD_CG_SUPPORT_DRM_LS |
1167 AMD_CG_SUPPORT_UVD_MGCG |
1168 AMD_CG_SUPPORT_VCE_MGCG;*/
1169 adev->pg_flags = 0;
1170 adev->external_rev_id = adev->rev_id + 0x6E;
1171 break;
aaa36a97 1172 case CHIP_CARRIZO:
f0f3a8fb
TSD		 1173 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1174 AMD_CG_SUPPORT_GFX_MGCG |
70eced9b
AD		 1175 AMD_CG_SUPPORT_GFX_MGLS |
1176 AMD_CG_SUPPORT_GFX_RLC_LS |
1177 AMD_CG_SUPPORT_GFX_CP_LS |
1178 AMD_CG_SUPPORT_GFX_CGTS |
70eced9b 1179 AMD_CG_SUPPORT_GFX_CGTS_LS |
fb4bbba2 1180 AMD_CG_SUPPORT_GFX_CGCG |
03c335d3
AD		 1181 AMD_CG_SUPPORT_GFX_CGLS |
1182 AMD_CG_SUPPORT_BIF_LS |
1183 AMD_CG_SUPPORT_HDP_MGCG |
6f17a257
AD		 1184 AMD_CG_SUPPORT_HDP_LS |
1185 AMD_CG_SUPPORT_SDMA_MGCG |
1af69a2c
TSD		 1186 AMD_CG_SUPPORT_SDMA_LS |
1187 AMD_CG_SUPPORT_VCE_MGCG;
f6ade304 1188 /* rev0 hardware requires workarounds to support PG */
0fd4af9e 1189 adev->pg_flags = 0;
170d6e94 1190 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
c2cade3d 1191 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
65b42622 1192 AMD_PG_SUPPORT_GFX_PIPELINE |
98fccc78 1193 AMD_PG_SUPPORT_CP |
2ed0936d
TSD		 1194 AMD_PG_SUPPORT_UVD |
1195 AMD_PG_SUPPORT_VCE;
f6ade304 1196 }
aaa36a97 1197 adev->external_rev_id = adev->rev_id + 0x1;
aaa36a97 1198 break;
cde64939 1199 case CHIP_STONEY:
64694905
AD		 1200 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1201 AMD_CG_SUPPORT_GFX_MGCG |
b6711d1b 1202 AMD_CG_SUPPORT_GFX_MGLS |
413cf600
TSD		 1203 AMD_CG_SUPPORT_GFX_RLC_LS |
1204 AMD_CG_SUPPORT_GFX_CP_LS |
1205 AMD_CG_SUPPORT_GFX_CGTS |
413cf600 1206 AMD_CG_SUPPORT_GFX_CGTS_LS |
413cf600 1207 AMD_CG_SUPPORT_GFX_CGLS |
b6711d1b
AD		 1208 AMD_CG_SUPPORT_BIF_LS |
1209 AMD_CG_SUPPORT_HDP_MGCG |
1bf912ff
AD		 1210 AMD_CG_SUPPORT_HDP_LS |
1211 AMD_CG_SUPPORT_SDMA_MGCG |
8ef583e9
TSD		 1212 AMD_CG_SUPPORT_SDMA_LS |
1213 AMD_CG_SUPPORT_VCE_MGCG;
e6b2a7d2 1214 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
4e86be75 1215 AMD_PG_SUPPORT_GFX_SMG |
c2cdb042 1216 AMD_PG_SUPPORT_GFX_PIPELINE |
98fccc78 1217 AMD_PG_SUPPORT_CP |
75419c43
TSD		 1218 AMD_PG_SUPPORT_UVD |
1219 AMD_PG_SUPPORT_VCE;
a47c78d9 1220 adev->external_rev_id = adev->rev_id + 0x61;
cde64939 1221 break;
aaa36a97
AD		 1222 default:
1223 /* FIXME: not supported yet */
1224 return -EINVAL;
1225 }
1226
ab276632
XY		 1227 if (amdgpu_sriov_vf(adev)) {
1228 amdgpu_virt_init_setting(adev);
1229 xgpu_vi_mailbox_set_irq_funcs(adev);
1230 }
1231
aaa36a97
AD		 1232 return 0;
1233}
1234
99581cc5
XY		 1235static int vi_common_late_init(void *handle)
1236{
1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1238
1239 if (amdgpu_sriov_vf(adev))
1240 xgpu_vi_mailbox_get_irq(adev);
1241
1242 return 0;
1243}
1244
5fc3aeeb 1245static int vi_common_sw_init(void *handle)
aaa36a97 1246{
99581cc5
XY		 1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1248
1249 if (amdgpu_sriov_vf(adev))
1250 xgpu_vi_mailbox_add_irq_id(adev);
1251
aaa36a97
AD		 1252 return 0;
1253}
1254
5fc3aeeb 1255static int vi_common_sw_fini(void *handle)
aaa36a97
AD		 1256{
1257 return 0;
1258}
1259
5fc3aeeb 1260static int vi_common_hw_init(void *handle)
aaa36a97 1261{
5fc3aeeb 1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263
aaa36a97
AD		 1264 /* move the golden regs per IP block */
1265 vi_init_golden_registers(adev);
1266 /* enable pcie gen2/3 link */
1267 vi_pcie_gen3_enable(adev);
1268 /* enable aspm */
1269 vi_program_aspm(adev);
1270 /* enable the doorbell aperture */
1271 vi_enable_doorbell_aperture(adev, true);
1272
1273 return 0;
1274}
1275
5fc3aeeb 1276static int vi_common_hw_fini(void *handle)
aaa36a97 1277{
5fc3aeeb 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
aaa36a97
AD		 1280 /* enable the doorbell aperture */
1281 vi_enable_doorbell_aperture(adev, false);
1282
63d24f88
XY		 1283 if (amdgpu_sriov_vf(adev))
1284 xgpu_vi_mailbox_put_irq(adev);
1285
aaa36a97
AD		 1286 return 0;
1287}
1288
5fc3aeeb 1289static int vi_common_suspend(void *handle)
aaa36a97 1290{
5fc3aeeb 1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292
aaa36a97
AD		 1293 return vi_common_hw_fini(adev);
1294}
1295
5fc3aeeb 1296static int vi_common_resume(void *handle)
aaa36a97 1297{
5fc3aeeb 1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299
aaa36a97
AD		 1300 return vi_common_hw_init(adev);
1301}
1302
5fc3aeeb 1303static bool vi_common_is_idle(void *handle)
aaa36a97
AD		 1304{
1305 return true;
1306}
1307
5fc3aeeb 1308static int vi_common_wait_for_idle(void *handle)
aaa36a97
AD		 1309{
1310 return 0;
1311}
1312
5fc3aeeb 1313static int vi_common_soft_reset(void *handle)
aaa36a97 1314{
aaa36a97
AD		 1315 return 0;
1316}
1317
76f10b9a
AD		 1318static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1319 bool enable)
6cec2655
EH		 1320{
1321 uint32_t temp, data;
1322
1323 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1324
c90766cf 1325 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
6cec2655
EH		 1326 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1327 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1328 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1329 else
1330 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1331 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1332 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1333
1334 if (temp != data)
1335 WREG32_PCIE(ixPCIE_CNTL2, data);
1336}
1337
76f10b9a
AD		 1338static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1339 bool enable)
6cec2655
EH		 1340{
1341 uint32_t temp, data;
1342
1343 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1344
c90766cf 1345 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
6cec2655
EH		 1346 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1347 else
1348 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1349
1350 if (temp != data)
1351 WREG32(mmHDP_HOST_PATH_CNTL, data);
1352}
1353
76f10b9a
AD		 1354static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1355 bool enable)
6cec2655
EH		 1356{
1357 uint32_t temp, data;
1358
1359 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1360
c90766cf 1361 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
6cec2655
EH		 1362 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1363 else
1364 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1365
1366 if (temp != data)
1367 WREG32(mmHDP_MEM_POWER_LS, data);
1368}
1369
f6f534e2
RZ		 1370static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1371 bool enable)
1372{
1373 uint32_t temp, data;
1374
1375 temp = data = RREG32(0x157a);
1376
1377 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1378 data |= 1;
1379 else
1380 data &= ~1;
1381
1382 if (temp != data)
1383 WREG32(0x157a, data);
1384}
1385
1386
76f10b9a
AD		 1387static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1388 bool enable)
6cec2655
EH		 1389{
1390 uint32_t temp, data;
1391
1392 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1393
c90766cf 1394 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
6cec2655
EH		 1395 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1396 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1397 else
1398 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1399 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1400
1401 if (temp != data)
1402 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1403}
1404
1bb08f91
RZ		 1405static int vi_common_set_clockgating_state_by_smu(void *handle,
1406 enum amd_clockgating_state state)
1407{
8a19e7fa
RZ		 1408 uint32_t msg_id, pp_state = 0;
1409 uint32_t pp_support_state = 0;
1bb08f91 1410 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1bb08f91 1411
8a19e7fa
RZ		 1412 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1413 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
3f2ddfa8 1414 pp_support_state = PP_STATE_SUPPORT_LS;
8a19e7fa
RZ		 1415 pp_state = PP_STATE_LS;
1416 }
1417 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
3f2ddfa8 1418 pp_support_state |= PP_STATE_SUPPORT_CG;
8a19e7fa
RZ		 1419 pp_state |= PP_STATE_CG;
1420 }
1421 if (state == AMD_CG_STATE_UNGATE)
1422 pp_state = 0;
1423 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1424 PP_BLOCK_SYS_MC,
1425 pp_support_state,
1426 pp_state);
3811f8f0
RZ		 1427 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1428 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1429 }
1430
1431 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1432 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
3f2ddfa8 1433 pp_support_state = PP_STATE_SUPPORT_LS;
8a19e7fa
RZ		 1434 pp_state = PP_STATE_LS;
1435 }
1436 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
3f2ddfa8 1437 pp_support_state |= PP_STATE_SUPPORT_CG;
8a19e7fa
RZ		 1438 pp_state |= PP_STATE_CG;
1439 }
1440 if (state == AMD_CG_STATE_UNGATE)
1441 pp_state = 0;
1442 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1443 PP_BLOCK_SYS_SDMA,
1444 pp_support_state,
1445 pp_state);
3811f8f0
RZ		 1446 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1447 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1448 }
1449
1450 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1451 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
3f2ddfa8 1452 pp_support_state = PP_STATE_SUPPORT_LS;
8a19e7fa
RZ		 1453 pp_state = PP_STATE_LS;
1454 }
1455 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
3f2ddfa8 1456 pp_support_state |= PP_STATE_SUPPORT_CG;
8a19e7fa
RZ		 1457 pp_state |= PP_STATE_CG;
1458 }
1459 if (state == AMD_CG_STATE_UNGATE)
1460 pp_state = 0;
1461 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1462 PP_BLOCK_SYS_HDP,
1463 pp_support_state,
1464 pp_state);
3811f8f0
RZ		 1465 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1466 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa 1467 }
1bb08f91 1468
8a19e7fa
RZ		 1469
1470 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1471 if (state == AMD_CG_STATE_UNGATE)
1472 pp_state = 0;
1473 else
1474 pp_state = PP_STATE_LS;
1475
1476 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1477 PP_BLOCK_SYS_BIF,
1478 PP_STATE_SUPPORT_LS,
1479 pp_state);
3811f8f0
RZ		 1480 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1481 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1482 }
1483 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1484 if (state == AMD_CG_STATE_UNGATE)
1485 pp_state = 0;
1486 else
1487 pp_state = PP_STATE_CG;
1488
1489 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1490 PP_BLOCK_SYS_BIF,
1491 PP_STATE_SUPPORT_CG,
1492 pp_state);
3811f8f0
RZ		 1493 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1494 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1495 }
1496
1497 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1498
1499 if (state == AMD_CG_STATE_UNGATE)
1500 pp_state = 0;
1501 else
1502 pp_state = PP_STATE_LS;
1503
1504 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1505 PP_BLOCK_SYS_DRM,
1506 PP_STATE_SUPPORT_LS,
1507 pp_state);
3811f8f0
RZ		 1508 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1509 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1510 }
1511
1512 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1513
1514 if (state == AMD_CG_STATE_UNGATE)
1515 pp_state = 0;
1516 else
1517 pp_state = PP_STATE_CG;
1518
1519 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1520 PP_BLOCK_SYS_ROM,
1521 PP_STATE_SUPPORT_CG,
1522 pp_state);
3811f8f0
RZ		 1523 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1524 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa 1525 }
1bb08f91
RZ		 1526 return 0;
1527}
1528
5fc3aeeb 1529static int vi_common_set_clockgating_state(void *handle,
c90766cf 1530 enum amd_clockgating_state state)
aaa36a97 1531{
6cec2655
EH		 1532 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1533
ce137c04
ML		 1534 if (amdgpu_sriov_vf(adev))
1535 return 0;
1536
6cec2655
EH		 1537 switch (adev->asic_type) {
1538 case CHIP_FIJI:
76f10b9a 1539 vi_update_bif_medium_grain_light_sleep(adev,
7e913664 1540 state == AMD_CG_STATE_GATE);
76f10b9a 1541 vi_update_hdp_medium_grain_clock_gating(adev,
7e913664 1542 state == AMD_CG_STATE_GATE);
76f10b9a 1543 vi_update_hdp_light_sleep(adev,
7e913664 1544 state == AMD_CG_STATE_GATE);
76f10b9a 1545 vi_update_rom_medium_grain_clock_gating(adev,
7e913664 1546 state == AMD_CG_STATE_GATE);
76f10b9a
AD		 1547 break;
1548 case CHIP_CARRIZO:
1549 case CHIP_STONEY:
1550 vi_update_bif_medium_grain_light_sleep(adev,
7e913664 1551 state == AMD_CG_STATE_GATE);
76f10b9a 1552 vi_update_hdp_medium_grain_clock_gating(adev,
7e913664 1553 state == AMD_CG_STATE_GATE);
76f10b9a 1554 vi_update_hdp_light_sleep(adev,
7e913664 1555 state == AMD_CG_STATE_GATE);
f6f534e2 1556 vi_update_drm_light_sleep(adev,
7e913664 1557 state == AMD_CG_STATE_GATE);
6cec2655 1558 break;
1bb08f91
RZ		 1559 case CHIP_TONGA:
1560 case CHIP_POLARIS10:
1561 case CHIP_POLARIS11:
c4642a47 1562 case CHIP_POLARIS12:
b51c5194 1563 case CHIP_VEGAM:
1bb08f91 1564 vi_common_set_clockgating_state_by_smu(adev, state);
6cec2655
EH		 1565 default:
1566 break;
1567 }
aaa36a97
AD		 1568 return 0;
1569}
1570
5fc3aeeb 1571static int vi_common_set_powergating_state(void *handle,
1572 enum amd_powergating_state state)
aaa36a97
AD		 1573{
1574 return 0;
1575}
1576
abd2c2fe
HR		 1577static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1578{
1579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1580 int data;
1581
ce137c04
ML		 1582 if (amdgpu_sriov_vf(adev))
1583 *flags = 0;
1584
abd2c2fe
HR		 1585 /* AMD_CG_SUPPORT_BIF_LS */
1586 data = RREG32_PCIE(ixPCIE_CNTL2);
1587 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1588 *flags |= AMD_CG_SUPPORT_BIF_LS;
1589
1590 /* AMD_CG_SUPPORT_HDP_LS */
1591 data = RREG32(mmHDP_MEM_POWER_LS);
1592 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1593 *flags |= AMD_CG_SUPPORT_HDP_LS;
1594
1595 /* AMD_CG_SUPPORT_HDP_MGCG */
1596 data = RREG32(mmHDP_HOST_PATH_CNTL);
1597 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1598 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1599
1600 /* AMD_CG_SUPPORT_ROM_MGCG */
1601 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1602 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1603 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1604}
1605
a1255107 1606static const struct amd_ip_funcs vi_common_ip_funcs = {
88a907d6 1607 .name = "vi_common",
aaa36a97 1608 .early_init = vi_common_early_init,
99581cc5 1609 .late_init = vi_common_late_init,
aaa36a97
AD		 1610 .sw_init = vi_common_sw_init,
1611 .sw_fini = vi_common_sw_fini,
1612 .hw_init = vi_common_hw_init,
1613 .hw_fini = vi_common_hw_fini,
1614 .suspend = vi_common_suspend,
1615 .resume = vi_common_resume,
1616 .is_idle = vi_common_is_idle,
1617 .wait_for_idle = vi_common_wait_for_idle,
1618 .soft_reset = vi_common_soft_reset,
aaa36a97
AD		 1619 .set_clockgating_state = vi_common_set_clockgating_state,
1620 .set_powergating_state = vi_common_set_powergating_state,
abd2c2fe 1621 .get_clockgating_state = vi_common_get_clockgating_state,
aaa36a97
AD		 1622};
1623
a1255107
AD		 1624static const struct amdgpu_ip_block_version vi_common_ip_block =
1625{
1626 .type = AMD_IP_BLOCK_TYPE_COMMON,
1627 .major = 1,
1628 .minor = 0,
1629 .rev = 0,
1630 .funcs = &vi_common_ip_funcs,
1631};
1632
1633int vi_set_ip_blocks(struct amdgpu_device *adev)
1634{
91caa081
XY		 1635 /* in early init stage, vbios code won't work */
1636 vi_detect_hw_virtualization(adev);
1637
99581cc5
XY		 1638 if (amdgpu_sriov_vf(adev))
1639 adev->virt.ops = &xgpu_vi_virt_ops;
1640
a1255107
AD		 1641 switch (adev->asic_type) {
1642 case CHIP_TOPAZ:
1643 /* topaz has no DCE, UVD, VCE */
2990a1fc
AD		 1644 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1645 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1646 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
71195ba6
RZ		 1647 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1648 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
b905090d 1649 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1650 if (adev->enable_virtual_display)
2990a1fc 1651 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
a1255107
AD		 1652 break;
1653 case CHIP_FIJI:
2990a1fc
AD		 1654 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1655 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1656 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
71195ba6
RZ		 1657 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1658 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1659 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
91caa081 1660 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 1661 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1662#if defined(CONFIG_DRM_AMD_DC)
1663 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1664 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1665#endif
a1255107 1666 else
2990a1fc 1667 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
91caa081 1668 if (!amdgpu_sriov_vf(adev)) {
2990a1fc
AD		 1669 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1670 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
91caa081 1671 }
a1255107
AD		 1672 break;
1673 case CHIP_TONGA:
2990a1fc
AD		 1674 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1675 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1676 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
71195ba6
RZ		 1677 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1678 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1679 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
91caa081 1680 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 1681 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1682#if defined(CONFIG_DRM_AMD_DC)
1683 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1684 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1685#endif
a1255107 1686 else
2990a1fc 1687 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
91caa081 1688 if (!amdgpu_sriov_vf(adev)) {
2990a1fc
AD		 1689 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1690 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
91caa081 1691 }
a1255107 1692 break;
a1255107 1693 case CHIP_POLARIS10:
b51c5194 1694 case CHIP_POLARIS11:
c4642a47 1695 case CHIP_POLARIS12:
b51c5194 1696 case CHIP_VEGAM:
2990a1fc
AD		 1697 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1698 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1699 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
71195ba6
RZ		 1700 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1701 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
b905090d 1702 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1703 if (adev->enable_virtual_display)
2990a1fc 1704 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1705#if defined(CONFIG_DRM_AMD_DC)
1706 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1707 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1708#endif
a1255107 1709 else
2990a1fc 1710 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
2990a1fc
AD		 1711 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1712 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
a1255107
AD		 1713 break;
1714 case CHIP_CARRIZO:
2990a1fc
AD		 1715 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1716 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1717 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
71195ba6
RZ		 1718 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1719 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1720 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1721 if (adev->enable_virtual_display)
2990a1fc 1722 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1723#if defined(CONFIG_DRM_AMD_DC)
1724 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1725 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1726#endif
a1255107 1727 else
2990a1fc 1728 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2990a1fc
AD		 1729 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1730 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
a1255107 1731#if defined(CONFIG_DRM_AMD_ACP)
2990a1fc 1732 amdgpu_device_ip_block_add(adev, &acp_ip_block);
a1255107
AD		 1733#endif
1734 break;
1735 case CHIP_STONEY:
2990a1fc
AD		 1736 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1737 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1738 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
71195ba6
RZ		 1739 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1740 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1741 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1742 if (adev->enable_virtual_display)
2990a1fc 1743 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1744#if defined(CONFIG_DRM_AMD_DC)
1745 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1746 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1747#endif
a1255107 1748 else
2990a1fc 1749 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2990a1fc
AD		 1750 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1751 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
a1255107 1752#if defined(CONFIG_DRM_AMD_ACP)
2990a1fc 1753 amdgpu_device_ip_block_add(adev, &acp_ip_block);
a1255107
AD		 1754#endif
1755 break;
1756 default:
1757 /* FIXME: not supported yet */
1758 return -EINVAL;
1759 }
1760
1761 return 0;
1762}
4e2c1ac2
OZ		 1763
1764void legacy_doorbell_index_init(struct amdgpu_device *adev)
1765{
1766 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1767 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1768 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1769 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1770 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1771 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1772 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1773 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1774 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1775 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
898e0d9d
OZ		 1776 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1777 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
4e2c1ac2
OZ		 1778 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1779 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1780}
Linux 6.x block layer and io_uring tree(s)