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drm/amd/powerplay: add basic powerplay framework
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / vi.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "atom.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40
41#include "bif/bif_5_0_d.h"
42#include "bif/bif_5_0_sh_mask.h"
43
44#include "gca/gfx_8_0_d.h"
45#include "gca/gfx_8_0_sh_mask.h"
46
47#include "smu/smu_7_1_1_d.h"
48#include "smu/smu_7_1_1_sh_mask.h"
49
50#include "uvd/uvd_5_0_d.h"
51#include "uvd/uvd_5_0_sh_mask.h"
52
53#include "vce/vce_3_0_d.h"
54#include "vce/vce_3_0_sh_mask.h"
55
56#include "dce/dce_10_0_d.h"
57#include "dce/dce_10_0_sh_mask.h"
58
59#include "vid.h"
60#include "vi.h"
61#include "vi_dpm.h"
62#include "gmc_v8_0.h"
63#include "gfx_v8_0.h"
64#include "sdma_v2_4.h"
65#include "sdma_v3_0.h"
66#include "dce_v10_0.h"
67#include "dce_v11_0.h"
68#include "iceland_ih.h"
69#include "tonga_ih.h"
70#include "cz_ih.h"
71#include "uvd_v5_0.h"
72#include "uvd_v6_0.h"
73#include "vce_v3_0.h"
1f7371b2 74#include "amdgpu_powerplay.h"
aaa36a97
AD		 75
76/*
77 * Indirect registers accessor
78 */
79static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
80{
81 unsigned long flags;
82 u32 r;
83
84 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
85 WREG32(mmPCIE_INDEX, reg);
86 (void)RREG32(mmPCIE_INDEX);
87 r = RREG32(mmPCIE_DATA);
88 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
89 return r;
90}
91
92static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
93{
94 unsigned long flags;
95
96 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
97 WREG32(mmPCIE_INDEX, reg);
98 (void)RREG32(mmPCIE_INDEX);
99 WREG32(mmPCIE_DATA, v);
100 (void)RREG32(mmPCIE_DATA);
101 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
102}
103
104static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
105{
106 unsigned long flags;
107 u32 r;
108
109 spin_lock_irqsave(&adev->smc_idx_lock, flags);
110 WREG32(mmSMC_IND_INDEX_0, (reg));
111 r = RREG32(mmSMC_IND_DATA_0);
112 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
113 return r;
114}
115
116static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
117{
118 unsigned long flags;
119
120 spin_lock_irqsave(&adev->smc_idx_lock, flags);
121 WREG32(mmSMC_IND_INDEX_0, (reg));
122 WREG32(mmSMC_IND_DATA_0, (v));
123 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
124}
125
7b92cdbf
AD		 126/* smu_8_0_d.h */
127#define mmMP0PUB_IND_INDEX 0x180
128#define mmMP0PUB_IND_DATA 0x181
129
130static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
131{
132 unsigned long flags;
133 u32 r;
134
135 spin_lock_irqsave(&adev->smc_idx_lock, flags);
136 WREG32(mmMP0PUB_IND_INDEX, (reg));
137 r = RREG32(mmMP0PUB_IND_DATA);
138 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
139 return r;
140}
141
142static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
143{
144 unsigned long flags;
145
146 spin_lock_irqsave(&adev->smc_idx_lock, flags);
147 WREG32(mmMP0PUB_IND_INDEX, (reg));
148 WREG32(mmMP0PUB_IND_DATA, (v));
149 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
150}
151
aaa36a97
AD		 152static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
153{
154 unsigned long flags;
155 u32 r;
156
157 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
158 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
159 r = RREG32(mmUVD_CTX_DATA);
160 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
161 return r;
162}
163
164static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
165{
166 unsigned long flags;
167
168 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
169 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
170 WREG32(mmUVD_CTX_DATA, (v));
171 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
172}
173
174static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
175{
176 unsigned long flags;
177 u32 r;
178
179 spin_lock_irqsave(&adev->didt_idx_lock, flags);
180 WREG32(mmDIDT_IND_INDEX, (reg));
181 r = RREG32(mmDIDT_IND_DATA);
182 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
183 return r;
184}
185
186static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
187{
188 unsigned long flags;
189
190 spin_lock_irqsave(&adev->didt_idx_lock, flags);
191 WREG32(mmDIDT_IND_INDEX, (reg));
192 WREG32(mmDIDT_IND_DATA, (v));
193 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
194}
195
196static const u32 tonga_mgcg_cgcg_init[] =
197{
198 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
199 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
200 mmPCIE_DATA, 0x000f0000, 0x00000000,
201 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
202 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
aaa36a97
AD		 203 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
204 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
205};
206
48299f95
DZ		 207static const u32 fiji_mgcg_cgcg_init[] =
208{
209 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
210 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
211 mmPCIE_DATA, 0x000f0000, 0x00000000,
212 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
213 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
214 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
215 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
216};
217
aaa36a97
AD		 218static const u32 iceland_mgcg_cgcg_init[] =
219{
220 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
221 mmPCIE_DATA, 0x000f0000, 0x00000000,
222 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
223 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
224 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
225};
226
227static const u32 cz_mgcg_cgcg_init[] =
228{
229 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
230 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
231 mmPCIE_DATA, 0x000f0000, 0x00000000,
aaa36a97
AD		 232 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
233 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
234};
235
39bb0c92
SL		 236static const u32 stoney_mgcg_cgcg_init[] =
237{
238 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
239 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
240 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
241};
242
aaa36a97
AD		 243static void vi_init_golden_registers(struct amdgpu_device *adev)
244{
245 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
246 mutex_lock(&adev->grbm_idx_mutex);
247
248 switch (adev->asic_type) {
249 case CHIP_TOPAZ:
250 amdgpu_program_register_sequence(adev,
251 iceland_mgcg_cgcg_init,
252 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
253 break;
48299f95
DZ		 254 case CHIP_FIJI:
255 amdgpu_program_register_sequence(adev,
256 fiji_mgcg_cgcg_init,
257 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
258 break;
aaa36a97
AD		 259 case CHIP_TONGA:
260 amdgpu_program_register_sequence(adev,
261 tonga_mgcg_cgcg_init,
262 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
263 break;
264 case CHIP_CARRIZO:
265 amdgpu_program_register_sequence(adev,
266 cz_mgcg_cgcg_init,
267 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
268 break;
39bb0c92
SL		 269 case CHIP_STONEY:
270 amdgpu_program_register_sequence(adev,
271 stoney_mgcg_cgcg_init,
272 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
273 break;
aaa36a97
AD		 274 default:
275 break;
276 }
277 mutex_unlock(&adev->grbm_idx_mutex);
278}
279
280/**
281 * vi_get_xclk - get the xclk
282 *
283 * @adev: amdgpu_device pointer
284 *
285 * Returns the reference clock used by the gfx engine
286 * (VI).
287 */
288static u32 vi_get_xclk(struct amdgpu_device *adev)
289{
290 u32 reference_clock = adev->clock.spll.reference_freq;
291 u32 tmp;
292
2f7d10b3 293 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 294 return reference_clock;
295
296 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
297 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
298 return 1000;
299
300 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
301 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
302 return reference_clock / 4;
303
304 return reference_clock;
305}
306
307/**
308 * vi_srbm_select - select specific register instances
309 *
310 * @adev: amdgpu_device pointer
311 * @me: selected ME (micro engine)
312 * @pipe: pipe
313 * @queue: queue
314 * @vmid: VMID
315 *
316 * Switches the currently active registers instances. Some
317 * registers are instanced per VMID, others are instanced per
318 * me/pipe/queue combination.
319 */
320void vi_srbm_select(struct amdgpu_device *adev,
321 u32 me, u32 pipe, u32 queue, u32 vmid)
322{
323 u32 srbm_gfx_cntl = 0;
324 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
325 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
326 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
327 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
328 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
329}
330
331static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
332{
333 /* todo */
334}
335
336static bool vi_read_disabled_bios(struct amdgpu_device *adev)
337{
338 u32 bus_cntl;
339 u32 d1vga_control = 0;
340 u32 d2vga_control = 0;
341 u32 vga_render_control = 0;
342 u32 rom_cntl;
343 bool r;
344
345 bus_cntl = RREG32(mmBUS_CNTL);
346 if (adev->mode_info.num_crtc) {
347 d1vga_control = RREG32(mmD1VGA_CONTROL);
348 d2vga_control = RREG32(mmD2VGA_CONTROL);
349 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
350 }
351 rom_cntl = RREG32_SMC(ixROM_CNTL);
352
353 /* enable the rom */
354 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
355 if (adev->mode_info.num_crtc) {
356 /* Disable VGA mode */
357 WREG32(mmD1VGA_CONTROL,
358 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
359 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
360 WREG32(mmD2VGA_CONTROL,
361 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
362 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
363 WREG32(mmVGA_RENDER_CONTROL,
364 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
365 }
366 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
367
368 r = amdgpu_read_bios(adev);
369
370 /* restore regs */
371 WREG32(mmBUS_CNTL, bus_cntl);
372 if (adev->mode_info.num_crtc) {
373 WREG32(mmD1VGA_CONTROL, d1vga_control);
374 WREG32(mmD2VGA_CONTROL, d2vga_control);
375 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
376 }
377 WREG32_SMC(ixROM_CNTL, rom_cntl);
378 return r;
379}
95addb2a
AD		 380
381static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
382 u8 *bios, u32 length_bytes)
383{
384 u32 *dw_ptr;
385 unsigned long flags;
386 u32 i, length_dw;
387
388 if (bios == NULL)
389 return false;
390 if (length_bytes == 0)
391 return false;
392 /* APU vbios image is part of sbios image */
393 if (adev->flags & AMD_IS_APU)
394 return false;
395
396 dw_ptr = (u32 *)bios;
397 length_dw = ALIGN(length_bytes, 4) / 4;
398 /* take the smc lock since we are using the smc index */
399 spin_lock_irqsave(&adev->smc_idx_lock, flags);
400 /* set rom index to 0 */
401 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
402 WREG32(mmSMC_IND_DATA_0, 0);
403 /* set index to data for continous read */
404 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
405 for (i = 0; i < length_dw; i++)
406 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
407 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
408
409 return true;
410}
411
aaa36a97
AD		 412static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
413 {mmGB_MACROTILE_MODE7, true},
414};
415
416static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
417 {mmGB_TILE_MODE7, true},
418 {mmGB_TILE_MODE12, true},
419 {mmGB_TILE_MODE17, true},
420 {mmGB_TILE_MODE23, true},
421 {mmGB_MACROTILE_MODE7, true},
422};
423
424static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
425 {mmGRBM_STATUS, false},
c7890fea
MO		 426 {mmGRBM_STATUS2, false},
427 {mmGRBM_STATUS_SE0, false},
428 {mmGRBM_STATUS_SE1, false},
429 {mmGRBM_STATUS_SE2, false},
430 {mmGRBM_STATUS_SE3, false},
431 {mmSRBM_STATUS, false},
432 {mmSRBM_STATUS2, false},
433 {mmSRBM_STATUS3, false},
434 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
435 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
436 {mmCP_STAT, false},
437 {mmCP_STALLED_STAT1, false},
438 {mmCP_STALLED_STAT2, false},
439 {mmCP_STALLED_STAT3, false},
440 {mmCP_CPF_BUSY_STAT, false},
441 {mmCP_CPF_STALLED_STAT1, false},
442 {mmCP_CPF_STATUS, false},
443 {mmCP_CPC_BUSY_STAT, false},
444 {mmCP_CPC_STALLED_STAT1, false},
445 {mmCP_CPC_STATUS, false},
aaa36a97
AD		 446 {mmGB_ADDR_CONFIG, false},
447 {mmMC_ARB_RAMCFG, false},
448 {mmGB_TILE_MODE0, false},
449 {mmGB_TILE_MODE1, false},
450 {mmGB_TILE_MODE2, false},
451 {mmGB_TILE_MODE3, false},
452 {mmGB_TILE_MODE4, false},
453 {mmGB_TILE_MODE5, false},
454 {mmGB_TILE_MODE6, false},
455 {mmGB_TILE_MODE7, false},
456 {mmGB_TILE_MODE8, false},
457 {mmGB_TILE_MODE9, false},
458 {mmGB_TILE_MODE10, false},
459 {mmGB_TILE_MODE11, false},
460 {mmGB_TILE_MODE12, false},
461 {mmGB_TILE_MODE13, false},
462 {mmGB_TILE_MODE14, false},
463 {mmGB_TILE_MODE15, false},
464 {mmGB_TILE_MODE16, false},
465 {mmGB_TILE_MODE17, false},
466 {mmGB_TILE_MODE18, false},
467 {mmGB_TILE_MODE19, false},
468 {mmGB_TILE_MODE20, false},
469 {mmGB_TILE_MODE21, false},
470 {mmGB_TILE_MODE22, false},
471 {mmGB_TILE_MODE23, false},
472 {mmGB_TILE_MODE24, false},
473 {mmGB_TILE_MODE25, false},
474 {mmGB_TILE_MODE26, false},
475 {mmGB_TILE_MODE27, false},
476 {mmGB_TILE_MODE28, false},
477 {mmGB_TILE_MODE29, false},
478 {mmGB_TILE_MODE30, false},
479 {mmGB_TILE_MODE31, false},
480 {mmGB_MACROTILE_MODE0, false},
481 {mmGB_MACROTILE_MODE1, false},
482 {mmGB_MACROTILE_MODE2, false},
483 {mmGB_MACROTILE_MODE3, false},
484 {mmGB_MACROTILE_MODE4, false},
485 {mmGB_MACROTILE_MODE5, false},
486 {mmGB_MACROTILE_MODE6, false},
487 {mmGB_MACROTILE_MODE7, false},
488 {mmGB_MACROTILE_MODE8, false},
489 {mmGB_MACROTILE_MODE9, false},
490 {mmGB_MACROTILE_MODE10, false},
491 {mmGB_MACROTILE_MODE11, false},
492 {mmGB_MACROTILE_MODE12, false},
493 {mmGB_MACROTILE_MODE13, false},
494 {mmGB_MACROTILE_MODE14, false},
495 {mmGB_MACROTILE_MODE15, false},
496 {mmCC_RB_BACKEND_DISABLE, false, true},
497 {mmGC_USER_RB_BACKEND_DISABLE, false, true},
498 {mmGB_BACKEND_MAP, false, false},
499 {mmPA_SC_RASTER_CONFIG, false, true},
500 {mmPA_SC_RASTER_CONFIG_1, false, true},
501};
502
503static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
504 u32 sh_num, u32 reg_offset)
505{
506 uint32_t val;
507
508 mutex_lock(&adev->grbm_idx_mutex);
509 if (se_num != 0xffffffff || sh_num != 0xffffffff)
510 gfx_v8_0_select_se_sh(adev, se_num, sh_num);
511
512 val = RREG32(reg_offset);
513
514 if (se_num != 0xffffffff || sh_num != 0xffffffff)
515 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
516 mutex_unlock(&adev->grbm_idx_mutex);
517 return val;
518}
519
520static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
521 u32 sh_num, u32 reg_offset, u32 *value)
522{
523 struct amdgpu_allowed_register_entry *asic_register_table = NULL;
524 struct amdgpu_allowed_register_entry *asic_register_entry;
525 uint32_t size, i;
526
527 *value = 0;
528 switch (adev->asic_type) {
529 case CHIP_TOPAZ:
530 asic_register_table = tonga_allowed_read_registers;
531 size = ARRAY_SIZE(tonga_allowed_read_registers);
532 break;
48299f95 533 case CHIP_FIJI:
aaa36a97
AD		 534 case CHIP_TONGA:
535 case CHIP_CARRIZO:
39bb0c92 536 case CHIP_STONEY:
aaa36a97
AD		 537 asic_register_table = cz_allowed_read_registers;
538 size = ARRAY_SIZE(cz_allowed_read_registers);
539 break;
540 default:
541 return -EINVAL;
542 }
543
544 if (asic_register_table) {
545 for (i = 0; i < size; i++) {
546 asic_register_entry = asic_register_table + i;
547 if (reg_offset != asic_register_entry->reg_offset)
548 continue;
549 if (!asic_register_entry->untouched)
550 *value = asic_register_entry->grbm_indexed ?
551 vi_read_indexed_register(adev, se_num,
552 sh_num, reg_offset) :
553 RREG32(reg_offset);
554 return 0;
555 }
556 }
557
558 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
559 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
560 continue;
561
562 if (!vi_allowed_read_registers[i].untouched)
563 *value = vi_allowed_read_registers[i].grbm_indexed ?
564 vi_read_indexed_register(adev, se_num,
565 sh_num, reg_offset) :
566 RREG32(reg_offset);
567 return 0;
568 }
569 return -EINVAL;
570}
571
572static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
573{
574 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
575 RREG32(mmGRBM_STATUS));
576 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
577 RREG32(mmGRBM_STATUS2));
578 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
579 RREG32(mmGRBM_STATUS_SE0));
580 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
581 RREG32(mmGRBM_STATUS_SE1));
582 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
583 RREG32(mmGRBM_STATUS_SE2));
584 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
585 RREG32(mmGRBM_STATUS_SE3));
586 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
587 RREG32(mmSRBM_STATUS));
588 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
589 RREG32(mmSRBM_STATUS2));
590 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
591 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
39bb0c92
SL		 592 if (adev->sdma.num_instances > 1) {
593 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
594 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
595 }
aaa36a97
AD		 596 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
597 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
598 RREG32(mmCP_STALLED_STAT1));
599 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
600 RREG32(mmCP_STALLED_STAT2));
601 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
602 RREG32(mmCP_STALLED_STAT3));
603 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
604 RREG32(mmCP_CPF_BUSY_STAT));
605 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
606 RREG32(mmCP_CPF_STALLED_STAT1));
607 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
608 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
609 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
610 RREG32(mmCP_CPC_STALLED_STAT1));
611 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
612}
613
614/**
615 * vi_gpu_check_soft_reset - check which blocks are busy
616 *
617 * @adev: amdgpu_device pointer
618 *
619 * Check which blocks are busy and return the relevant reset
620 * mask to be used by vi_gpu_soft_reset().
621 * Returns a mask of the blocks to be reset.
622 */
623u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
624{
625 u32 reset_mask = 0;
626 u32 tmp;
627
628 /* GRBM_STATUS */
629 tmp = RREG32(mmGRBM_STATUS);
630 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
631 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
632 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
633 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
634 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
635 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
636 reset_mask |= AMDGPU_RESET_GFX;
637
638 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
639 reset_mask |= AMDGPU_RESET_CP;
640
641 /* GRBM_STATUS2 */
642 tmp = RREG32(mmGRBM_STATUS2);
643 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
644 reset_mask |= AMDGPU_RESET_RLC;
645
646 if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
647 GRBM_STATUS2__CPC_BUSY_MASK |
648 GRBM_STATUS2__CPG_BUSY_MASK))
649 reset_mask |= AMDGPU_RESET_CP;
650
651 /* SRBM_STATUS2 */
652 tmp = RREG32(mmSRBM_STATUS2);
653 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
654 reset_mask |= AMDGPU_RESET_DMA;
655
656 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
657 reset_mask |= AMDGPU_RESET_DMA1;
658
659 /* SRBM_STATUS */
660 tmp = RREG32(mmSRBM_STATUS);
661
662 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
663 reset_mask |= AMDGPU_RESET_IH;
664
665 if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
666 reset_mask |= AMDGPU_RESET_SEM;
667
668 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
669 reset_mask |= AMDGPU_RESET_GRBM;
670
671 if (adev->asic_type != CHIP_TOPAZ) {
672 if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
673 SRBM_STATUS__UVD_BUSY_MASK))
674 reset_mask |= AMDGPU_RESET_UVD;
675 }
676
677 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
678 reset_mask |= AMDGPU_RESET_VMC;
679
680 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
681 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
682 reset_mask |= AMDGPU_RESET_MC;
683
684 /* SDMA0_STATUS_REG */
685 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
686 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
687 reset_mask |= AMDGPU_RESET_DMA;
688
689 /* SDMA1_STATUS_REG */
39bb0c92
SL		 690 if (adev->sdma.num_instances > 1) {
691 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
692 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
693 reset_mask |= AMDGPU_RESET_DMA1;
694 }
aaa36a97
AD		 695#if 0
696 /* VCE_STATUS */
697 if (adev->asic_type != CHIP_TOPAZ) {
698 tmp = RREG32(mmVCE_STATUS);
699 if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
700 reset_mask |= AMDGPU_RESET_VCE;
701 if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
702 reset_mask |= AMDGPU_RESET_VCE1;
703
704 }
705
706 if (adev->asic_type != CHIP_TOPAZ) {
707 if (amdgpu_display_is_display_hung(adev))
708 reset_mask |= AMDGPU_RESET_DISPLAY;
709 }
710#endif
711
712 /* Skip MC reset as it's mostly likely not hung, just busy */
713 if (reset_mask & AMDGPU_RESET_MC) {
714 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
715 reset_mask &= ~AMDGPU_RESET_MC;
716 }
717
718 return reset_mask;
719}
720
721/**
722 * vi_gpu_soft_reset - soft reset GPU
723 *
724 * @adev: amdgpu_device pointer
725 * @reset_mask: mask of which blocks to reset
726 *
727 * Soft reset the blocks specified in @reset_mask.
728 */
729static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
730{
731 struct amdgpu_mode_mc_save save;
732 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
733 u32 tmp;
734
735 if (reset_mask == 0)
736 return;
737
738 dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
739
740 vi_print_gpu_status_regs(adev);
741 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
742 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
743 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
744 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
745
746 /* disable CG/PG */
747
748 /* stop the rlc */
749 //XXX
750 //gfx_v8_0_rlc_stop(adev);
751
752 /* Disable GFX parsing/prefetching */
753 tmp = RREG32(mmCP_ME_CNTL);
754 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
755 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
756 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
757 WREG32(mmCP_ME_CNTL, tmp);
758
759 /* Disable MEC parsing/prefetching */
760 tmp = RREG32(mmCP_MEC_CNTL);
761 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
762 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
763 WREG32(mmCP_MEC_CNTL, tmp);
764
765 if (reset_mask & AMDGPU_RESET_DMA) {
766 /* sdma0 */
767 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
768 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
769 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
770 }
771 if (reset_mask & AMDGPU_RESET_DMA1) {
772 /* sdma1 */
773 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
774 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
775 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
776 }
777
778 gmc_v8_0_mc_stop(adev, &save);
779 if (amdgpu_asic_wait_for_mc_idle(adev)) {
780 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
781 }
782
783 if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
784 grbm_soft_reset =
785 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
786 grbm_soft_reset =
787 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
788 }
789
790 if (reset_mask & AMDGPU_RESET_CP) {
791 grbm_soft_reset =
792 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
793 srbm_soft_reset =
794 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
795 }
796
797 if (reset_mask & AMDGPU_RESET_DMA)
798 srbm_soft_reset =
799 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
800
801 if (reset_mask & AMDGPU_RESET_DMA1)
802 srbm_soft_reset =
803 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
804
805 if (reset_mask & AMDGPU_RESET_DISPLAY)
806 srbm_soft_reset =
807 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
808
809 if (reset_mask & AMDGPU_RESET_RLC)
810 grbm_soft_reset =
811 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
812
813 if (reset_mask & AMDGPU_RESET_SEM)
814 srbm_soft_reset =
815 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
816
817 if (reset_mask & AMDGPU_RESET_IH)
818 srbm_soft_reset =
819 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
820
821 if (reset_mask & AMDGPU_RESET_GRBM)
822 srbm_soft_reset =
823 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
824
825 if (reset_mask & AMDGPU_RESET_VMC)
826 srbm_soft_reset =
827 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
828
829 if (reset_mask & AMDGPU_RESET_UVD)
830 srbm_soft_reset =
831 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
832
833 if (reset_mask & AMDGPU_RESET_VCE)
834 srbm_soft_reset =
835 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
836
837 if (reset_mask & AMDGPU_RESET_VCE)
838 srbm_soft_reset =
839 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
840
2f7d10b3 841 if (!(adev->flags & AMD_IS_APU)) {
aaa36a97
AD		 842 if (reset_mask & AMDGPU_RESET_MC)
843 srbm_soft_reset =
844 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
845 }
846
847 if (grbm_soft_reset) {
848 tmp = RREG32(mmGRBM_SOFT_RESET);
849 tmp |= grbm_soft_reset;
850 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
851 WREG32(mmGRBM_SOFT_RESET, tmp);
852 tmp = RREG32(mmGRBM_SOFT_RESET);
853
854 udelay(50);
855
856 tmp &= ~grbm_soft_reset;
857 WREG32(mmGRBM_SOFT_RESET, tmp);
858 tmp = RREG32(mmGRBM_SOFT_RESET);
859 }
860
861 if (srbm_soft_reset) {
862 tmp = RREG32(mmSRBM_SOFT_RESET);
863 tmp |= srbm_soft_reset;
864 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
865 WREG32(mmSRBM_SOFT_RESET, tmp);
866 tmp = RREG32(mmSRBM_SOFT_RESET);
867
868 udelay(50);
869
870 tmp &= ~srbm_soft_reset;
871 WREG32(mmSRBM_SOFT_RESET, tmp);
872 tmp = RREG32(mmSRBM_SOFT_RESET);
873 }
874
875 /* Wait a little for things to settle down */
876 udelay(50);
877
878 gmc_v8_0_mc_resume(adev, &save);
879 udelay(50);
880
881 vi_print_gpu_status_regs(adev);
882}
883
884static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
885{
886 struct amdgpu_mode_mc_save save;
887 u32 tmp, i;
888
889 dev_info(adev->dev, "GPU pci config reset\n");
890
891 /* disable dpm? */
892
893 /* disable cg/pg */
894
895 /* Disable GFX parsing/prefetching */
896 tmp = RREG32(mmCP_ME_CNTL);
897 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
898 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
899 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
900 WREG32(mmCP_ME_CNTL, tmp);
901
902 /* Disable MEC parsing/prefetching */
903 tmp = RREG32(mmCP_MEC_CNTL);
904 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
905 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
906 WREG32(mmCP_MEC_CNTL, tmp);
907
908 /* Disable GFX parsing/prefetching */
909 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
910 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
911
912 /* Disable MEC parsing/prefetching */
913 WREG32(mmCP_MEC_CNTL,
914 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
915
916 /* sdma0 */
917 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
918 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
919 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
920
921 /* sdma1 */
922 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
923 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
924 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
925
926 /* XXX other engines? */
927
928 /* halt the rlc, disable cp internal ints */
929 //XXX
930 //gfx_v8_0_rlc_stop(adev);
931
932 udelay(50);
933
934 /* disable mem access */
935 gmc_v8_0_mc_stop(adev, &save);
936 if (amdgpu_asic_wait_for_mc_idle(adev)) {
937 dev_warn(adev->dev, "Wait for MC idle timed out !\n");
938 }
939
940 /* disable BM */
941 pci_clear_master(adev->pdev);
942 /* reset */
943 amdgpu_pci_config_reset(adev);
944
945 udelay(100);
946
947 /* wait for asic to come out of reset */
948 for (i = 0; i < adev->usec_timeout; i++) {
949 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
950 break;
951 udelay(1);
952 }
953
954}
955
956static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
957{
958 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
959
960 if (hung)
961 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
962 else
963 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
964
965 WREG32(mmBIOS_SCRATCH_3, tmp);
966}
967
968/**
969 * vi_asic_reset - soft reset GPU
970 *
971 * @adev: amdgpu_device pointer
972 *
973 * Look up which blocks are hung and attempt
974 * to reset them.
975 * Returns 0 for success.
976 */
977static int vi_asic_reset(struct amdgpu_device *adev)
978{
979 u32 reset_mask;
980
981 reset_mask = vi_gpu_check_soft_reset(adev);
982
983 if (reset_mask)
984 vi_set_bios_scratch_engine_hung(adev, true);
985
986 /* try soft reset */
987 vi_gpu_soft_reset(adev, reset_mask);
988
989 reset_mask = vi_gpu_check_soft_reset(adev);
990
991 /* try pci config reset */
992 if (reset_mask && amdgpu_hard_reset)
993 vi_gpu_pci_config_reset(adev);
994
995 reset_mask = vi_gpu_check_soft_reset(adev);
996
997 if (!reset_mask)
998 vi_set_bios_scratch_engine_hung(adev, false);
999
1000 return 0;
1001}
1002
1003static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1004 u32 cntl_reg, u32 status_reg)
1005{
1006 int r, i;
1007 struct atom_clock_dividers dividers;
1008 uint32_t tmp;
1009
1010 r = amdgpu_atombios_get_clock_dividers(adev,
1011 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1012 clock, false, &dividers);
1013 if (r)
1014 return r;
1015
1016 tmp = RREG32_SMC(cntl_reg);
1017 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
1018 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
1019 tmp |= dividers.post_divider;
1020 WREG32_SMC(cntl_reg, tmp);
1021
1022 for (i = 0; i < 100; i++) {
1023 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1024 break;
1025 mdelay(10);
1026 }
1027 if (i == 100)
1028 return -ETIMEDOUT;
1029
1030 return 0;
1031}
1032
1033static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1034{
1035 int r;
1036
1037 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1038 if (r)
1039 return r;
1040
1041 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1042
1043 return 0;
1044}
1045
1046static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1047{
1048 /* todo */
1049
1050 return 0;
1051}
1052
1053static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
1054{
1055 u32 mask;
1056 int ret;
1057
e79d5c08
AD		 1058 if (pci_is_root_bus(adev->pdev->bus))
1059 return;
1060
aaa36a97
AD		 1061 if (amdgpu_pcie_gen2 == 0)
1062 return;
1063
2f7d10b3 1064 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 1065 return;
1066
1067 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1068 if (ret != 0)
1069 return;
1070
1071 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1072 return;
1073
1074 /* todo */
1075}
1076
1077static void vi_program_aspm(struct amdgpu_device *adev)
1078{
1079
1080 if (amdgpu_aspm == 0)
1081 return;
1082
1083 /* todo */
1084}
1085
1086static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1087 bool enable)
1088{
1089 u32 tmp;
1090
1091 /* not necessary on CZ */
2f7d10b3 1092 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 1093 return;
1094
1095 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
1096 if (enable)
1097 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
1098 else
1099 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
1100
1101 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
1102}
1103
1104/* topaz has no DCE, UVD, VCE */
1105static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
1106{
1107 /* ORDER MATTERS! */
1108 {
5fc3aeeb 1109 .type = AMD_IP_BLOCK_TYPE_COMMON,
aaa36a97
AD		 1110 .major = 2,
1111 .minor = 0,
1112 .rev = 0,
1113 .funcs = &vi_common_ip_funcs,
1114 },
1115 {
5fc3aeeb 1116 .type = AMD_IP_BLOCK_TYPE_GMC,
aaa36a97
AD		 1117 .major = 8,
1118 .minor = 0,
1119 .rev = 0,
1120 .funcs = &gmc_v8_0_ip_funcs,
1121 },
1122 {
5fc3aeeb 1123 .type = AMD_IP_BLOCK_TYPE_IH,
aaa36a97
AD		 1124 .major = 2,
1125 .minor = 4,
1126 .rev = 0,
1127 .funcs = &iceland_ih_ip_funcs,
1128 },
1129 {
5fc3aeeb 1130 .type = AMD_IP_BLOCK_TYPE_SMC,
aaa36a97
AD		 1131 .major = 7,
1132 .minor = 1,
1133 .rev = 0,
1f7371b2 1134 .funcs = &amdgpu_pp_ip_funcs,
aaa36a97
AD		 1135 },
1136 {
5fc3aeeb 1137 .type = AMD_IP_BLOCK_TYPE_GFX,
aaa36a97
AD		 1138 .major = 8,
1139 .minor = 0,
1140 .rev = 0,
1141 .funcs = &gfx_v8_0_ip_funcs,
1142 },
1143 {
5fc3aeeb 1144 .type = AMD_IP_BLOCK_TYPE_SDMA,
aaa36a97
AD		 1145 .major = 2,
1146 .minor = 4,
1147 .rev = 0,
1148 .funcs = &sdma_v2_4_ip_funcs,
1149 },
1150};
1151
1152static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
1153{
1154 /* ORDER MATTERS! */
1155 {
5fc3aeeb 1156 .type = AMD_IP_BLOCK_TYPE_COMMON,
aaa36a97
AD		 1157 .major = 2,
1158 .minor = 0,
1159 .rev = 0,
1160 .funcs = &vi_common_ip_funcs,
1161 },
1162 {
5fc3aeeb 1163 .type = AMD_IP_BLOCK_TYPE_GMC,
aaa36a97
AD		 1164 .major = 8,
1165 .minor = 0,
1166 .rev = 0,
1167 .funcs = &gmc_v8_0_ip_funcs,
1168 },
1169 {
5fc3aeeb 1170 .type = AMD_IP_BLOCK_TYPE_IH,
aaa36a97
AD		 1171 .major = 3,
1172 .minor = 0,
1173 .rev = 0,
1174 .funcs = &tonga_ih_ip_funcs,
1175 },
1176 {
5fc3aeeb 1177 .type = AMD_IP_BLOCK_TYPE_SMC,
aaa36a97
AD		 1178 .major = 7,
1179 .minor = 1,
1180 .rev = 0,
1f7371b2 1181 .funcs = &amdgpu_pp_ip_funcs,
aaa36a97
AD		 1182 },
1183 {
5fc3aeeb 1184 .type = AMD_IP_BLOCK_TYPE_DCE,
aaa36a97
AD		 1185 .major = 10,
1186 .minor = 0,
1187 .rev = 0,
1188 .funcs = &dce_v10_0_ip_funcs,
1189 },
1190 {
5fc3aeeb 1191 .type = AMD_IP_BLOCK_TYPE_GFX,
aaa36a97
AD		 1192 .major = 8,
1193 .minor = 0,
1194 .rev = 0,
1195 .funcs = &gfx_v8_0_ip_funcs,
1196 },
1197 {
5fc3aeeb 1198 .type = AMD_IP_BLOCK_TYPE_SDMA,
aaa36a97
AD		 1199 .major = 3,
1200 .minor = 0,
1201 .rev = 0,
1202 .funcs = &sdma_v3_0_ip_funcs,
1203 },
1204 {
5fc3aeeb 1205 .type = AMD_IP_BLOCK_TYPE_UVD,
aaa36a97
AD		 1206 .major = 5,
1207 .minor = 0,
1208 .rev = 0,
1209 .funcs = &uvd_v5_0_ip_funcs,
1210 },
1211 {
5fc3aeeb 1212 .type = AMD_IP_BLOCK_TYPE_VCE,
aaa36a97
AD		 1213 .major = 3,
1214 .minor = 0,
1215 .rev = 0,
1216 .funcs = &vce_v3_0_ip_funcs,
1217 },
1218};
1219
48299f95
DZ		 1220static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
1221{
1222 /* ORDER MATTERS! */
1223 {
1224 .type = AMD_IP_BLOCK_TYPE_COMMON,
1225 .major = 2,
1226 .minor = 0,
1227 .rev = 0,
1228 .funcs = &vi_common_ip_funcs,
127a2628
DZ		 1229 },
1230 {
1231 .type = AMD_IP_BLOCK_TYPE_GMC,
1232 .major = 8,
1233 .minor = 5,
1234 .rev = 0,
1235 .funcs = &gmc_v8_0_ip_funcs,
1236 },
aa8a3b53
DZ		 1237 {
1238 .type = AMD_IP_BLOCK_TYPE_IH,
1239 .major = 3,
1240 .minor = 0,
1241 .rev = 0,
1242 .funcs = &tonga_ih_ip_funcs,
1243 },
8e711e1a
DZ		 1244 {
1245 .type = AMD_IP_BLOCK_TYPE_SMC,
1246 .major = 7,
1247 .minor = 1,
1248 .rev = 0,
1249 .funcs = &fiji_dpm_ip_funcs,
1250 },
84390860
DZ		 1251 {
1252 .type = AMD_IP_BLOCK_TYPE_DCE,
1253 .major = 10,
1254 .minor = 1,
1255 .rev = 0,
1256 .funcs = &dce_v10_0_ip_funcs,
1257 },
af15a2d5
DZ		 1258 {
1259 .type = AMD_IP_BLOCK_TYPE_GFX,
1260 .major = 8,
1261 .minor = 0,
1262 .rev = 0,
1263 .funcs = &gfx_v8_0_ip_funcs,
1264 },
1a5bbb66
DZ		 1265 {
1266 .type = AMD_IP_BLOCK_TYPE_SDMA,
1267 .major = 3,
1268 .minor = 0,
1269 .rev = 0,
1270 .funcs = &sdma_v3_0_ip_funcs,
1271 },
974ee3db
DZ		 1272 {
1273 .type = AMD_IP_BLOCK_TYPE_UVD,
1274 .major = 6,
1275 .minor = 0,
1276 .rev = 0,
1277 .funcs = &uvd_v6_0_ip_funcs,
1278 },
188a9bcd
AD		 1279 {
1280 .type = AMD_IP_BLOCK_TYPE_VCE,
1281 .major = 3,
1282 .minor = 0,
1283 .rev = 0,
1284 .funcs = &vce_v3_0_ip_funcs,
1285 },
48299f95
DZ		 1286};
1287
aaa36a97
AD		 1288static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1289{
1290 /* ORDER MATTERS! */
1291 {
5fc3aeeb 1292 .type = AMD_IP_BLOCK_TYPE_COMMON,
aaa36a97
AD		 1293 .major = 2,
1294 .minor = 0,
1295 .rev = 0,
1296 .funcs = &vi_common_ip_funcs,
1297 },
1298 {
5fc3aeeb 1299 .type = AMD_IP_BLOCK_TYPE_GMC,
aaa36a97
AD		 1300 .major = 8,
1301 .minor = 0,
1302 .rev = 0,
1303 .funcs = &gmc_v8_0_ip_funcs,
1304 },
1305 {
5fc3aeeb 1306 .type = AMD_IP_BLOCK_TYPE_IH,
aaa36a97
AD		 1307 .major = 3,
1308 .minor = 0,
1309 .rev = 0,
1310 .funcs = &cz_ih_ip_funcs,
1311 },
1312 {
5fc3aeeb 1313 .type = AMD_IP_BLOCK_TYPE_SMC,
aaa36a97
AD		 1314 .major = 8,
1315 .minor = 0,
1316 .rev = 0,
1f7371b2 1317 .funcs = &amdgpu_pp_ip_funcs
aaa36a97
AD		 1318 },
1319 {
5fc3aeeb 1320 .type = AMD_IP_BLOCK_TYPE_DCE,
aaa36a97
AD		 1321 .major = 11,
1322 .minor = 0,
1323 .rev = 0,
1324 .funcs = &dce_v11_0_ip_funcs,
1325 },
1326 {
5fc3aeeb 1327 .type = AMD_IP_BLOCK_TYPE_GFX,
aaa36a97
AD		 1328 .major = 8,
1329 .minor = 0,
1330 .rev = 0,
1331 .funcs = &gfx_v8_0_ip_funcs,
1332 },
1333 {
5fc3aeeb 1334 .type = AMD_IP_BLOCK_TYPE_SDMA,
aaa36a97
AD		 1335 .major = 3,
1336 .minor = 0,
1337 .rev = 0,
1338 .funcs = &sdma_v3_0_ip_funcs,
1339 },
1340 {
5fc3aeeb 1341 .type = AMD_IP_BLOCK_TYPE_UVD,
aaa36a97
AD		 1342 .major = 6,
1343 .minor = 0,
1344 .rev = 0,
1345 .funcs = &uvd_v6_0_ip_funcs,
1346 },
1347 {
5fc3aeeb 1348 .type = AMD_IP_BLOCK_TYPE_VCE,
aaa36a97
AD		 1349 .major = 3,
1350 .minor = 0,
1351 .rev = 0,
1352 .funcs = &vce_v3_0_ip_funcs,
1353 },
1354};
1355
1356int vi_set_ip_blocks(struct amdgpu_device *adev)
1357{
1358 switch (adev->asic_type) {
1359 case CHIP_TOPAZ:
1360 adev->ip_blocks = topaz_ip_blocks;
1361 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1362 break;
48299f95
DZ		 1363 case CHIP_FIJI:
1364 adev->ip_blocks = fiji_ip_blocks;
1365 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1366 break;
aaa36a97
AD		 1367 case CHIP_TONGA:
1368 adev->ip_blocks = tonga_ip_blocks;
1369 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1370 break;
1371 case CHIP_CARRIZO:
39bb0c92 1372 case CHIP_STONEY:
aaa36a97
AD		 1373 adev->ip_blocks = cz_ip_blocks;
1374 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1375 break;
1376 default:
1377 /* FIXME: not supported yet */
1378 return -EINVAL;
1379 }
1380
aaa36a97
AD		 1381 return 0;
1382}
1383
39bb0c92
SL		 1384#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1385#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1386#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1387
aaa36a97
AD		 1388static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1389{
abdfb850 1390 if (adev->flags & AMD_IS_APU)
39bb0c92
SL		 1391 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1392 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
aaa36a97 1393 else
abdfb850
FC		 1394 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1395 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
aaa36a97
AD		 1396}
1397
1398static const struct amdgpu_asic_funcs vi_asic_funcs =
1399{
1400 .read_disabled_bios = &vi_read_disabled_bios,
95addb2a 1401 .read_bios_from_rom = &vi_read_bios_from_rom,
aaa36a97
AD		 1402 .read_register = &vi_read_register,
1403 .reset = &vi_asic_reset,
1404 .set_vga_state = &vi_vga_set_state,
1405 .get_xclk = &vi_get_xclk,
1406 .set_uvd_clocks = &vi_set_uvd_clocks,
1407 .set_vce_clocks = &vi_set_vce_clocks,
1408 .get_cu_info = &gfx_v8_0_get_cu_info,
1409 /* these should be moved to their own ip modules */
1410 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1411 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1412};
1413
5fc3aeeb 1414static int vi_common_early_init(void *handle)
aaa36a97
AD		 1415{
1416 bool smc_enabled = false;
5fc3aeeb 1417 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 1418
2f7d10b3 1419 if (adev->flags & AMD_IS_APU) {
7b92cdbf
AD		 1420 adev->smc_rreg = &cz_smc_rreg;
1421 adev->smc_wreg = &cz_smc_wreg;
1422 } else {
1423 adev->smc_rreg = &vi_smc_rreg;
1424 adev->smc_wreg = &vi_smc_wreg;
1425 }
aaa36a97
AD		 1426 adev->pcie_rreg = &vi_pcie_rreg;
1427 adev->pcie_wreg = &vi_pcie_wreg;
1428 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1429 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1430 adev->didt_rreg = &vi_didt_rreg;
1431 adev->didt_wreg = &vi_didt_wreg;
1432
1433 adev->asic_funcs = &vi_asic_funcs;
1434
5fc3aeeb 1435 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1436 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
aaa36a97
AD		 1437 smc_enabled = true;
1438
1439 adev->rev_id = vi_get_rev_id(adev);
1440 adev->external_rev_id = 0xFF;
1441 switch (adev->asic_type) {
1442 case CHIP_TOPAZ:
1443 adev->has_uvd = false;
1444 adev->cg_flags = 0;
1445 adev->pg_flags = 0;
1446 adev->external_rev_id = 0x1;
aaa36a97 1447 break;
48299f95 1448 case CHIP_FIJI:
b6bc28ff
FC		 1449 adev->has_uvd = true;
1450 adev->cg_flags = 0;
1451 adev->pg_flags = 0;
1452 adev->external_rev_id = adev->rev_id + 0x3c;
1453 break;
aaa36a97
AD		 1454 case CHIP_TONGA:
1455 adev->has_uvd = true;
1456 adev->cg_flags = 0;
1457 adev->pg_flags = 0;
1458 adev->external_rev_id = adev->rev_id + 0x14;
aaa36a97
AD		 1459 break;
1460 case CHIP_CARRIZO:
39bb0c92 1461 case CHIP_STONEY:
aaa36a97
AD		 1462 adev->has_uvd = true;
1463 adev->cg_flags = 0;
1ee4478a
LL		 1464 /* Disable UVD pg */
1465 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
aaa36a97 1466 adev->external_rev_id = adev->rev_id + 0x1;
aaa36a97
AD		 1467 break;
1468 default:
1469 /* FIXME: not supported yet */
1470 return -EINVAL;
1471 }
1472
a3d08fa5
FC		 1473 if (amdgpu_smc_load_fw && smc_enabled)
1474 adev->firmware.smu_load = true;
1475
aaa36a97
AD		 1476 return 0;
1477}
1478
5fc3aeeb 1479static int vi_common_sw_init(void *handle)
aaa36a97
AD		 1480{
1481 return 0;
1482}
1483
5fc3aeeb 1484static int vi_common_sw_fini(void *handle)
aaa36a97
AD		 1485{
1486 return 0;
1487}
1488
5fc3aeeb 1489static int vi_common_hw_init(void *handle)
aaa36a97 1490{
5fc3aeeb 1491 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1492
aaa36a97
AD		 1493 /* move the golden regs per IP block */
1494 vi_init_golden_registers(adev);
1495 /* enable pcie gen2/3 link */
1496 vi_pcie_gen3_enable(adev);
1497 /* enable aspm */
1498 vi_program_aspm(adev);
1499 /* enable the doorbell aperture */
1500 vi_enable_doorbell_aperture(adev, true);
1501
1502 return 0;
1503}
1504
5fc3aeeb 1505static int vi_common_hw_fini(void *handle)
aaa36a97 1506{
5fc3aeeb 1507 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1508
aaa36a97
AD		 1509 /* enable the doorbell aperture */
1510 vi_enable_doorbell_aperture(adev, false);
1511
1512 return 0;
1513}
1514
5fc3aeeb 1515static int vi_common_suspend(void *handle)
aaa36a97 1516{
5fc3aeeb 1517 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1518
aaa36a97
AD		 1519 return vi_common_hw_fini(adev);
1520}
1521
5fc3aeeb 1522static int vi_common_resume(void *handle)
aaa36a97 1523{
5fc3aeeb 1524 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1525
aaa36a97
AD		 1526 return vi_common_hw_init(adev);
1527}
1528
5fc3aeeb 1529static bool vi_common_is_idle(void *handle)
aaa36a97
AD		 1530{
1531 return true;
1532}
1533
5fc3aeeb 1534static int vi_common_wait_for_idle(void *handle)
aaa36a97
AD		 1535{
1536 return 0;
1537}
1538
5fc3aeeb 1539static void vi_common_print_status(void *handle)
aaa36a97 1540{
5fc3aeeb 1541 return;
aaa36a97
AD		 1542}
1543
5fc3aeeb 1544static int vi_common_soft_reset(void *handle)
aaa36a97 1545{
aaa36a97
AD		 1546 return 0;
1547}
1548
5fc3aeeb 1549static int vi_common_set_clockgating_state(void *handle,
1550 enum amd_clockgating_state state)
aaa36a97
AD		 1551{
1552 return 0;
1553}
1554
5fc3aeeb 1555static int vi_common_set_powergating_state(void *handle,
1556 enum amd_powergating_state state)
aaa36a97
AD		 1557{
1558 return 0;
1559}
1560
5fc3aeeb 1561const struct amd_ip_funcs vi_common_ip_funcs = {
aaa36a97
AD		 1562 .early_init = vi_common_early_init,
1563 .late_init = NULL,
1564 .sw_init = vi_common_sw_init,
1565 .sw_fini = vi_common_sw_fini,
1566 .hw_init = vi_common_hw_init,
1567 .hw_fini = vi_common_hw_fini,
1568 .suspend = vi_common_suspend,
1569 .resume = vi_common_resume,
1570 .is_idle = vi_common_is_idle,
1571 .wait_for_idle = vi_common_wait_for_idle,
1572 .soft_reset = vi_common_soft_reset,
1573 .print_status = vi_common_print_status,
1574 .set_clockgating_state = vi_common_set_clockgating_state,
1575 .set_powergating_state = vi_common_set_powergating_state,
1576};
1577
Linux 6.x block layer and io_uring tree(s)