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Merge branch 'tty-splice' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds...
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / vi.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
47b757fb
SR		 23
24#include <linux/pci.h>
aaa36a97 25#include <linux/slab.h>
47b757fb 26
aaa36a97
AD		 27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "atom.h"
d0dd7f0c 34#include "amd_pcie.h"
aaa36a97
AD		 35
36#include "gmc/gmc_8_1_d.h"
37#include "gmc/gmc_8_1_sh_mask.h"
38
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "gca/gfx_8_0_d.h"
46#include "gca/gfx_8_0_sh_mask.h"
47
48#include "smu/smu_7_1_1_d.h"
49#include "smu/smu_7_1_1_sh_mask.h"
50
51#include "uvd/uvd_5_0_d.h"
52#include "uvd/uvd_5_0_sh_mask.h"
53
54#include "vce/vce_3_0_d.h"
55#include "vce/vce_3_0_sh_mask.h"
56
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
60#include "vid.h"
61#include "vi.h"
aaa36a97 62#include "gmc_v8_0.h"
429c45de 63#include "gmc_v7_0.h"
aaa36a97
AD		 64#include "gfx_v8_0.h"
65#include "sdma_v2_4.h"
66#include "sdma_v3_0.h"
67#include "dce_v10_0.h"
68#include "dce_v11_0.h"
69#include "iceland_ih.h"
70#include "tonga_ih.h"
71#include "cz_ih.h"
72#include "uvd_v5_0.h"
73#include "uvd_v6_0.h"
74#include "vce_v3_0.h"
a8fe58ce
MB		 75#if defined(CONFIG_DRM_AMD_ACP)
76#include "amdgpu_acp.h"
77#endif
e9ed3a67 78#include "dce_virtual.h"
99581cc5 79#include "mxgpu_vi.h"
4562236b 80#include "amdgpu_dm.h"
aaa36a97
AD		 81
82/*
83 * Indirect registers accessor
84 */
85static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
86{
87 unsigned long flags;
88 u32 r;
89
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
07944623
ED		 91 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
92 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
93 r = RREG32_NO_KIQ(mmPCIE_DATA);
aaa36a97
AD		 94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
95 return r;
96}
97
98static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
99{
100 unsigned long flags;
101
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
07944623
ED		 103 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
104 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
105 WREG32_NO_KIQ(mmPCIE_DATA, v);
106 (void)RREG32_NO_KIQ(mmPCIE_DATA);
aaa36a97
AD		 107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
108}
109
110static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
111{
112 unsigned long flags;
113 u32 r;
114
115 spin_lock_irqsave(&adev->smc_idx_lock, flags);
fa1d04e9
YT		 116 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
117 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
aaa36a97
AD		 118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
119 return r;
120}
121
122static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&adev->smc_idx_lock, flags);
07944623
ED		 127 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
128 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
aaa36a97
AD		 129 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
130}
131
7b92cdbf
AD		 132/* smu_8_0_d.h */
133#define mmMP0PUB_IND_INDEX 0x180
134#define mmMP0PUB_IND_DATA 0x181
135
136static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
137{
138 unsigned long flags;
139 u32 r;
140
141 spin_lock_irqsave(&adev->smc_idx_lock, flags);
142 WREG32(mmMP0PUB_IND_INDEX, (reg));
143 r = RREG32(mmMP0PUB_IND_DATA);
144 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
145 return r;
146}
147
148static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&adev->smc_idx_lock, flags);
153 WREG32(mmMP0PUB_IND_INDEX, (reg));
154 WREG32(mmMP0PUB_IND_DATA, (v));
155 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
156}
157
aaa36a97
AD		 158static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
159{
160 unsigned long flags;
161 u32 r;
162
163 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
164 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
165 r = RREG32(mmUVD_CTX_DATA);
166 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
167 return r;
168}
169
170static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
171{
172 unsigned long flags;
173
174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
175 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
176 WREG32(mmUVD_CTX_DATA, (v));
177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
178}
179
180static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
181{
182 unsigned long flags;
183 u32 r;
184
185 spin_lock_irqsave(&adev->didt_idx_lock, flags);
186 WREG32(mmDIDT_IND_INDEX, (reg));
187 r = RREG32(mmDIDT_IND_DATA);
188 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
189 return r;
190}
191
192static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
193{
194 unsigned long flags;
195
196 spin_lock_irqsave(&adev->didt_idx_lock, flags);
197 WREG32(mmDIDT_IND_INDEX, (reg));
198 WREG32(mmDIDT_IND_DATA, (v));
199 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
200}
201
ccdbb20a
RZ		 202static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
203{
204 unsigned long flags;
205 u32 r;
206
207 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
208 WREG32(mmGC_CAC_IND_INDEX, (reg));
209 r = RREG32(mmGC_CAC_IND_DATA);
210 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
211 return r;
212}
213
214static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
215{
216 unsigned long flags;
217
218 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
219 WREG32(mmGC_CAC_IND_INDEX, (reg));
220 WREG32(mmGC_CAC_IND_DATA, (v));
221 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
222}
223
224
aaa36a97
AD		 225static const u32 tonga_mgcg_cgcg_init[] =
226{
227 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
228 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
229 mmPCIE_DATA, 0x000f0000, 0x00000000,
230 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
231 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
aaa36a97
AD		 232 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
233 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
234};
235
48299f95
DZ		 236static const u32 fiji_mgcg_cgcg_init[] =
237{
238 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
239 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
240 mmPCIE_DATA, 0x000f0000, 0x00000000,
241 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
242 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
243 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
244 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
245};
246
aaa36a97
AD		 247static const u32 iceland_mgcg_cgcg_init[] =
248{
249 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
250 mmPCIE_DATA, 0x000f0000, 0x00000000,
251 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
252 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
253 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
254};
255
256static const u32 cz_mgcg_cgcg_init[] =
257{
258 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
259 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
260 mmPCIE_DATA, 0x000f0000, 0x00000000,
aaa36a97
AD		 261 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
262 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
263};
264
39bb0c92
SL		 265static const u32 stoney_mgcg_cgcg_init[] =
266{
267 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
268 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
269 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
270};
271
aaa36a97
AD		 272static void vi_init_golden_registers(struct amdgpu_device *adev)
273{
274 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
275 mutex_lock(&adev->grbm_idx_mutex);
276
99581cc5
XY		 277 if (amdgpu_sriov_vf(adev)) {
278 xgpu_vi_init_golden_registers(adev);
279 mutex_unlock(&adev->grbm_idx_mutex);
280 return;
281 }
282
aaa36a97
AD		 283 switch (adev->asic_type) {
284 case CHIP_TOPAZ:
9c3f2b54
AD		 285 amdgpu_device_program_register_sequence(adev,
286 iceland_mgcg_cgcg_init,
287 ARRAY_SIZE(iceland_mgcg_cgcg_init));
aaa36a97 288 break;
48299f95 289 case CHIP_FIJI:
9c3f2b54
AD		 290 amdgpu_device_program_register_sequence(adev,
291 fiji_mgcg_cgcg_init,
292 ARRAY_SIZE(fiji_mgcg_cgcg_init));
48299f95 293 break;
aaa36a97 294 case CHIP_TONGA:
9c3f2b54
AD		 295 amdgpu_device_program_register_sequence(adev,
296 tonga_mgcg_cgcg_init,
297 ARRAY_SIZE(tonga_mgcg_cgcg_init));
aaa36a97
AD		 298 break;
299 case CHIP_CARRIZO:
9c3f2b54
AD		 300 amdgpu_device_program_register_sequence(adev,
301 cz_mgcg_cgcg_init,
302 ARRAY_SIZE(cz_mgcg_cgcg_init));
aaa36a97 303 break;
39bb0c92 304 case CHIP_STONEY:
9c3f2b54
AD		 305 amdgpu_device_program_register_sequence(adev,
306 stoney_mgcg_cgcg_init,
307 ARRAY_SIZE(stoney_mgcg_cgcg_init));
39bb0c92 308 break;
2cc0c0b5 309 case CHIP_POLARIS10:
b51c5194 310 case CHIP_POLARIS11:
c4642a47 311 case CHIP_POLARIS12:
b51c5194 312 case CHIP_VEGAM:
aaa36a97
AD		 313 default:
314 break;
315 }
316 mutex_unlock(&adev->grbm_idx_mutex);
317}
318
319/**
320 * vi_get_xclk - get the xclk
321 *
322 * @adev: amdgpu_device pointer
323 *
324 * Returns the reference clock used by the gfx engine
325 * (VI).
326 */
327static u32 vi_get_xclk(struct amdgpu_device *adev)
328{
329 u32 reference_clock = adev->clock.spll.reference_freq;
330 u32 tmp;
331
2f7d10b3 332 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 333 return reference_clock;
334
335 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
337 return 1000;
338
339 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
340 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
341 return reference_clock / 4;
342
343 return reference_clock;
344}
345
346/**
347 * vi_srbm_select - select specific register instances
348 *
349 * @adev: amdgpu_device pointer
350 * @me: selected ME (micro engine)
351 * @pipe: pipe
352 * @queue: queue
353 * @vmid: VMID
354 *
355 * Switches the currently active registers instances. Some
356 * registers are instanced per VMID, others are instanced per
357 * me/pipe/queue combination.
358 */
359void vi_srbm_select(struct amdgpu_device *adev,
360 u32 me, u32 pipe, u32 queue, u32 vmid)
361{
362 u32 srbm_gfx_cntl = 0;
363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
365 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
366 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
367 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
368}
369
370static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
371{
372 /* todo */
373}
374
375static bool vi_read_disabled_bios(struct amdgpu_device *adev)
376{
377 u32 bus_cntl;
378 u32 d1vga_control = 0;
379 u32 d2vga_control = 0;
380 u32 vga_render_control = 0;
381 u32 rom_cntl;
382 bool r;
383
384 bus_cntl = RREG32(mmBUS_CNTL);
385 if (adev->mode_info.num_crtc) {
386 d1vga_control = RREG32(mmD1VGA_CONTROL);
387 d2vga_control = RREG32(mmD2VGA_CONTROL);
388 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
389 }
390 rom_cntl = RREG32_SMC(ixROM_CNTL);
391
392 /* enable the rom */
393 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
394 if (adev->mode_info.num_crtc) {
395 /* Disable VGA mode */
396 WREG32(mmD1VGA_CONTROL,
397 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
398 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
399 WREG32(mmD2VGA_CONTROL,
400 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
401 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
402 WREG32(mmVGA_RENDER_CONTROL,
403 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
404 }
405 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
406
407 r = amdgpu_read_bios(adev);
408
409 /* restore regs */
410 WREG32(mmBUS_CNTL, bus_cntl);
411 if (adev->mode_info.num_crtc) {
412 WREG32(mmD1VGA_CONTROL, d1vga_control);
413 WREG32(mmD2VGA_CONTROL, d2vga_control);
414 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
415 }
416 WREG32_SMC(ixROM_CNTL, rom_cntl);
417 return r;
418}
95addb2a
AD		 419
420static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
421 u8 *bios, u32 length_bytes)
422{
423 u32 *dw_ptr;
424 unsigned long flags;
425 u32 i, length_dw;
426
427 if (bios == NULL)
428 return false;
429 if (length_bytes == 0)
430 return false;
431 /* APU vbios image is part of sbios image */
432 if (adev->flags & AMD_IS_APU)
433 return false;
434
435 dw_ptr = (u32 *)bios;
436 length_dw = ALIGN(length_bytes, 4) / 4;
437 /* take the smc lock since we are using the smc index */
438 spin_lock_irqsave(&adev->smc_idx_lock, flags);
439 /* set rom index to 0 */
4bc10d16
ML		 440 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
441 WREG32(mmSMC_IND_DATA_11, 0);
95addb2a 442 /* set index to data for continous read */
4bc10d16 443 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
95addb2a 444 for (i = 0; i < length_dw; i++)
4bc10d16 445 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
95addb2a
AD		 446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
447
448 return true;
449}
450
eca2240f 451static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
97fcc76b
CK		 452 {mmGRBM_STATUS},
453 {mmGRBM_STATUS2},
454 {mmGRBM_STATUS_SE0},
455 {mmGRBM_STATUS_SE1},
456 {mmGRBM_STATUS_SE2},
457 {mmGRBM_STATUS_SE3},
458 {mmSRBM_STATUS},
459 {mmSRBM_STATUS2},
460 {mmSRBM_STATUS3},
461 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
462 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
463 {mmCP_STAT},
464 {mmCP_STALLED_STAT1},
465 {mmCP_STALLED_STAT2},
466 {mmCP_STALLED_STAT3},
467 {mmCP_CPF_BUSY_STAT},
468 {mmCP_CPF_STALLED_STAT1},
469 {mmCP_CPF_STATUS},
470 {mmCP_CPC_BUSY_STAT},
471 {mmCP_CPC_STALLED_STAT1},
472 {mmCP_CPC_STATUS},
473 {mmGB_ADDR_CONFIG},
474 {mmMC_ARB_RAMCFG},
475 {mmGB_TILE_MODE0},
476 {mmGB_TILE_MODE1},
477 {mmGB_TILE_MODE2},
478 {mmGB_TILE_MODE3},
479 {mmGB_TILE_MODE4},
480 {mmGB_TILE_MODE5},
481 {mmGB_TILE_MODE6},
482 {mmGB_TILE_MODE7},
483 {mmGB_TILE_MODE8},
484 {mmGB_TILE_MODE9},
485 {mmGB_TILE_MODE10},
486 {mmGB_TILE_MODE11},
487 {mmGB_TILE_MODE12},
488 {mmGB_TILE_MODE13},
489 {mmGB_TILE_MODE14},
490 {mmGB_TILE_MODE15},
491 {mmGB_TILE_MODE16},
492 {mmGB_TILE_MODE17},
493 {mmGB_TILE_MODE18},
494 {mmGB_TILE_MODE19},
495 {mmGB_TILE_MODE20},
496 {mmGB_TILE_MODE21},
497 {mmGB_TILE_MODE22},
498 {mmGB_TILE_MODE23},
499 {mmGB_TILE_MODE24},
500 {mmGB_TILE_MODE25},
501 {mmGB_TILE_MODE26},
502 {mmGB_TILE_MODE27},
503 {mmGB_TILE_MODE28},
504 {mmGB_TILE_MODE29},
505 {mmGB_TILE_MODE30},
506 {mmGB_TILE_MODE31},
507 {mmGB_MACROTILE_MODE0},
508 {mmGB_MACROTILE_MODE1},
509 {mmGB_MACROTILE_MODE2},
510 {mmGB_MACROTILE_MODE3},
511 {mmGB_MACROTILE_MODE4},
512 {mmGB_MACROTILE_MODE5},
513 {mmGB_MACROTILE_MODE6},
514 {mmGB_MACROTILE_MODE7},
515 {mmGB_MACROTILE_MODE8},
516 {mmGB_MACROTILE_MODE9},
517 {mmGB_MACROTILE_MODE10},
518 {mmGB_MACROTILE_MODE11},
519 {mmGB_MACROTILE_MODE12},
520 {mmGB_MACROTILE_MODE13},
521 {mmGB_MACROTILE_MODE14},
522 {mmGB_MACROTILE_MODE15},
523 {mmCC_RB_BACKEND_DISABLE, true},
524 {mmGC_USER_RB_BACKEND_DISABLE, true},
525 {mmGB_BACKEND_MAP, false},
526 {mmPA_SC_RASTER_CONFIG, true},
527 {mmPA_SC_RASTER_CONFIG_1, true},
aaa36a97
AD		 528};
529
db9635cc
AD		 530static uint32_t vi_get_register_value(struct amdgpu_device *adev,
531 bool indexed, u32 se_num,
532 u32 sh_num, u32 reg_offset)
aaa36a97 533{
db9635cc
AD		 534 if (indexed) {
535 uint32_t val;
536 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
537 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
538
539 switch (reg_offset) {
540 case mmCC_RB_BACKEND_DISABLE:
541 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
542 case mmGC_USER_RB_BACKEND_DISABLE:
543 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
544 case mmPA_SC_RASTER_CONFIG:
545 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
546 case mmPA_SC_RASTER_CONFIG_1:
547 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
548 }
aaa36a97 549
db9635cc
AD		 550 mutex_lock(&adev->grbm_idx_mutex);
551 if (se_num != 0xffffffff || sh_num != 0xffffffff)
552 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
553
554 val = RREG32(reg_offset);
555
556 if (se_num != 0xffffffff || sh_num != 0xffffffff)
557 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
558 mutex_unlock(&adev->grbm_idx_mutex);
559 return val;
560 } else {
561 unsigned idx;
562
563 switch (reg_offset) {
564 case mmGB_ADDR_CONFIG:
565 return adev->gfx.config.gb_addr_config;
566 case mmMC_ARB_RAMCFG:
567 return adev->gfx.config.mc_arb_ramcfg;
568 case mmGB_TILE_MODE0:
569 case mmGB_TILE_MODE1:
570 case mmGB_TILE_MODE2:
571 case mmGB_TILE_MODE3:
572 case mmGB_TILE_MODE4:
573 case mmGB_TILE_MODE5:
574 case mmGB_TILE_MODE6:
575 case mmGB_TILE_MODE7:
576 case mmGB_TILE_MODE8:
577 case mmGB_TILE_MODE9:
578 case mmGB_TILE_MODE10:
579 case mmGB_TILE_MODE11:
580 case mmGB_TILE_MODE12:
581 case mmGB_TILE_MODE13:
582 case mmGB_TILE_MODE14:
583 case mmGB_TILE_MODE15:
584 case mmGB_TILE_MODE16:
585 case mmGB_TILE_MODE17:
586 case mmGB_TILE_MODE18:
587 case mmGB_TILE_MODE19:
588 case mmGB_TILE_MODE20:
589 case mmGB_TILE_MODE21:
590 case mmGB_TILE_MODE22:
591 case mmGB_TILE_MODE23:
592 case mmGB_TILE_MODE24:
593 case mmGB_TILE_MODE25:
594 case mmGB_TILE_MODE26:
595 case mmGB_TILE_MODE27:
596 case mmGB_TILE_MODE28:
597 case mmGB_TILE_MODE29:
598 case mmGB_TILE_MODE30:
599 case mmGB_TILE_MODE31:
600 idx = (reg_offset - mmGB_TILE_MODE0);
601 return adev->gfx.config.tile_mode_array[idx];
602 case mmGB_MACROTILE_MODE0:
603 case mmGB_MACROTILE_MODE1:
604 case mmGB_MACROTILE_MODE2:
605 case mmGB_MACROTILE_MODE3:
606 case mmGB_MACROTILE_MODE4:
607 case mmGB_MACROTILE_MODE5:
608 case mmGB_MACROTILE_MODE6:
609 case mmGB_MACROTILE_MODE7:
610 case mmGB_MACROTILE_MODE8:
611 case mmGB_MACROTILE_MODE9:
612 case mmGB_MACROTILE_MODE10:
613 case mmGB_MACROTILE_MODE11:
614 case mmGB_MACROTILE_MODE12:
615 case mmGB_MACROTILE_MODE13:
616 case mmGB_MACROTILE_MODE14:
617 case mmGB_MACROTILE_MODE15:
618 idx = (reg_offset - mmGB_MACROTILE_MODE0);
619 return adev->gfx.config.macrotile_mode_array[idx];
620 default:
621 return RREG32(reg_offset);
622 }
623 }
aaa36a97
AD		 624}
625
626static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
627 u32 sh_num, u32 reg_offset, u32 *value)
628{
3032f350 629 uint32_t i;
aaa36a97
AD		 630
631 *value = 0;
aaa36a97 632 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
97fcc76b
CK		 633 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
634
aaa36a97
AD		 635 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
636 continue;
637
97fcc76b
CK		 638 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
639 reg_offset);
aaa36a97
AD		 640 return 0;
641 }
642 return -EINVAL;
643}
644
89a31827 645static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
aaa36a97 646{
a2c5c698 647 u32 i;
aaa36a97
AD		 648
649 dev_info(adev->dev, "GPU pci config reset\n");
650
aaa36a97
AD		 651 /* disable BM */
652 pci_clear_master(adev->pdev);
653 /* reset */
8111c387 654 amdgpu_device_pci_config_reset(adev);
aaa36a97
AD		 655
656 udelay(100);
657
658 /* wait for asic to come out of reset */
659 for (i = 0; i < adev->usec_timeout; i++) {
b314f9a9
CZ		 660 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
661 /* enable BM */
662 pci_set_master(adev->pdev);
c836fec5 663 adev->has_hw_reset = true;
89a31827 664 return 0;
b314f9a9 665 }
aaa36a97
AD		 666 udelay(1);
667 }
89a31827 668 return -EINVAL;
aaa36a97
AD		 669}
670
aaa36a97 671/**
97c002be 672 * vi_asic_pci_config_reset - soft reset GPU
aaa36a97
AD		 673 *
674 * @adev: amdgpu_device pointer
675 *
97c002be
AD		 676 * Use PCI Config method to reset the GPU.
677 *
aaa36a97
AD		 678 * Returns 0 for success.
679 */
97c002be 680static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
aaa36a97 681{
89a31827
CZ		 682 int r;
683
72a57438 684 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
aaa36a97 685
89a31827 686 r = vi_gpu_pci_config_reset(adev);
aaa36a97 687
72a57438 688 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
aaa36a97 689
89a31827 690 return r;
aaa36a97
AD		 691}
692
e45ed943
AD		 693static bool vi_asic_supports_baco(struct amdgpu_device *adev)
694{
e45ed943
AD		 695 switch (adev->asic_type) {
696 case CHIP_FIJI:
697 case CHIP_TONGA:
698 case CHIP_POLARIS10:
699 case CHIP_POLARIS11:
700 case CHIP_POLARIS12:
701 case CHIP_TOPAZ:
9530273e 702 return amdgpu_dpm_is_baco_supported(adev);
e45ed943 703 default:
9530273e 704 return false;
e45ed943 705 }
e45ed943
AD		 706}
707
9bc1932f
AD		 708static enum amd_reset_method
709vi_asic_reset_method(struct amdgpu_device *adev)
710{
97c002be
AD		 711 bool baco_reset;
712
273da6ff
WS		 713 if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY ||
714 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
715 return amdgpu_reset_method;
716
717 if (amdgpu_reset_method != -1)
718 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
719 amdgpu_reset_method);
720
97c002be
AD		 721 switch (adev->asic_type) {
722 case CHIP_FIJI:
723 case CHIP_TONGA:
724 case CHIP_POLARIS10:
725 case CHIP_POLARIS11:
726 case CHIP_POLARIS12:
727 case CHIP_TOPAZ:
9530273e 728 baco_reset = amdgpu_dpm_is_baco_supported(adev);
97c002be
AD		 729 break;
730 default:
731 baco_reset = false;
732 break;
733 }
734
735 if (baco_reset)
736 return AMD_RESET_METHOD_BACO;
737 else
738 return AMD_RESET_METHOD_LEGACY;
739}
740
741/**
742 * vi_asic_reset - soft reset GPU
743 *
744 * @adev: amdgpu_device pointer
745 *
746 * Look up which blocks are hung and attempt
747 * to reset them.
748 * Returns 0 for success.
749 */
750static int vi_asic_reset(struct amdgpu_device *adev)
751{
752 int r;
753
5149f082 754 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
11043b7a 755 dev_info(adev->dev, "BACO reset\n");
9530273e 756 r = amdgpu_dpm_baco_reset(adev);
5149f082 757 } else {
11043b7a 758 dev_info(adev->dev, "PCI CONFIG reset\n");
97c002be 759 r = vi_asic_pci_config_reset(adev);
5149f082 760 }
97c002be
AD		 761
762 return r;
9bc1932f
AD		 763}
764
bbf282d8
AD		 765static u32 vi_get_config_memsize(struct amdgpu_device *adev)
766{
767 return RREG32(mmCONFIG_MEMSIZE);
768}
769
aaa36a97
AD		 770static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
771 u32 cntl_reg, u32 status_reg)
772{
773 int r, i;
774 struct atom_clock_dividers dividers;
775 uint32_t tmp;
776
777 r = amdgpu_atombios_get_clock_dividers(adev,
778 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
779 clock, false, &dividers);
780 if (r)
781 return r;
782
783 tmp = RREG32_SMC(cntl_reg);
819a23f8
RZ		 784
785 if (adev->flags & AMD_IS_APU)
786 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
787 else
788 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
789 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
aaa36a97
AD		 790 tmp |= dividers.post_divider;
791 WREG32_SMC(cntl_reg, tmp);
792
793 for (i = 0; i < 100; i++) {
819a23f8
RZ		 794 tmp = RREG32_SMC(status_reg);
795 if (adev->flags & AMD_IS_APU) {
796 if (tmp & 0x10000)
797 break;
798 } else {
799 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
800 break;
801 }
aaa36a97
AD		 802 mdelay(10);
803 }
804 if (i == 100)
805 return -ETIMEDOUT;
aaa36a97
AD		 806 return 0;
807}
808
819a23f8
RZ		 809#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
810#define ixGNB_CLK1_STATUS 0xD822010C
811#define ixGNB_CLK2_DFS_CNTL 0xD8220110
812#define ixGNB_CLK2_STATUS 0xD822012C
08ebb6e9
RZ		 813#define ixGNB_CLK3_DFS_CNTL 0xD8220130
814#define ixGNB_CLK3_STATUS 0xD822014C
819a23f8 815
aaa36a97
AD		 816static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
817{
818 int r;
819
819a23f8
RZ		 820 if (adev->flags & AMD_IS_APU) {
821 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
822 if (r)
823 return r;
aaa36a97 824
819a23f8
RZ		 825 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
826 if (r)
827 return r;
828 } else {
829 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
830 if (r)
831 return r;
832
833 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
834 if (r)
835 return r;
836 }
aaa36a97
AD		 837
838 return 0;
839}
840
841static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
842{
714b1f53
RZ		 843 int r, i;
844 struct atom_clock_dividers dividers;
845 u32 tmp;
08ebb6e9
RZ		 846 u32 reg_ctrl;
847 u32 reg_status;
848 u32 status_mask;
849 u32 reg_mask;
850
851 if (adev->flags & AMD_IS_APU) {
852 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
853 reg_status = ixGNB_CLK3_STATUS;
854 status_mask = 0x00010000;
855 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
856 } else {
857 reg_ctrl = ixCG_ECLK_CNTL;
858 reg_status = ixCG_ECLK_STATUS;
859 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
860 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
861 }
714b1f53
RZ		 862
863 r = amdgpu_atombios_get_clock_dividers(adev,
864 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
865 ecclk, false, &dividers);
866 if (r)
867 return r;
868
869 for (i = 0; i < 100; i++) {
08ebb6e9 870 if (RREG32_SMC(reg_status) & status_mask)
714b1f53
RZ		 871 break;
872 mdelay(10);
873 }
08ebb6e9 874
714b1f53
RZ		 875 if (i == 100)
876 return -ETIMEDOUT;
877
08ebb6e9
RZ		 878 tmp = RREG32_SMC(reg_ctrl);
879 tmp &= ~reg_mask;
714b1f53 880 tmp |= dividers.post_divider;
08ebb6e9 881 WREG32_SMC(reg_ctrl, tmp);
714b1f53
RZ		 882
883 for (i = 0; i < 100; i++) {
08ebb6e9 884 if (RREG32_SMC(reg_status) & status_mask)
714b1f53
RZ		 885 break;
886 mdelay(10);
887 }
08ebb6e9 888
714b1f53
RZ		 889 if (i == 100)
890 return -ETIMEDOUT;
aaa36a97
AD		 891
892 return 0;
893}
894
895static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
896{
e79d5c08
AD		 897 if (pci_is_root_bus(adev->pdev->bus))
898 return;
899
aaa36a97
AD		 900 if (amdgpu_pcie_gen2 == 0)
901 return;
902
2f7d10b3 903 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 904 return;
905
d0dd7f0c
AD		 906 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
907 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
aaa36a97
AD		 908 return;
909
910 /* todo */
911}
912
913static void vi_program_aspm(struct amdgpu_device *adev)
914{
915
916 if (amdgpu_aspm == 0)
917 return;
918
919 /* todo */
920}
921
922static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
923 bool enable)
924{
925 u32 tmp;
926
927 /* not necessary on CZ */
2f7d10b3 928 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 929 return;
930
931 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
932 if (enable)
933 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
934 else
935 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
936
937 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
938}
939
39bb0c92
SL		 940#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
941#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
942#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
943
aaa36a97
AD		 944static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
945{
abdfb850 946 if (adev->flags & AMD_IS_APU)
39bb0c92
SL		 947 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
948 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
aaa36a97 949 else
abdfb850
FC		 950 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
951 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
aaa36a97
AD		 952}
953
69882565 954static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
dd8d07f2 955{
69882565
CK		 956 if (!ring || !ring->funcs->emit_wreg) {
957 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
958 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
959 } else {
960 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
961 }
dd8d07f2
AD		 962}
963
69882565
CK		 964static void vi_invalidate_hdp(struct amdgpu_device *adev,
965 struct amdgpu_ring *ring)
dd8d07f2 966{
69882565
CK		 967 if (!ring || !ring->funcs->emit_wreg) {
968 WREG32(mmHDP_DEBUG0, 1);
969 RREG32(mmHDP_DEBUG0);
970 } else {
971 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
972 }
dd8d07f2
AD		 973}
974
06082d9b
AD		 975static bool vi_need_full_reset(struct amdgpu_device *adev)
976{
977 switch (adev->asic_type) {
978 case CHIP_CARRIZO:
979 case CHIP_STONEY:
980 /* CZ has hang issues with full reset at the moment */
981 return false;
982 case CHIP_FIJI:
983 case CHIP_TONGA:
984 /* XXX: soft reset should work on fiji and tonga */
985 return true;
986 case CHIP_POLARIS10:
987 case CHIP_POLARIS11:
988 case CHIP_POLARIS12:
989 case CHIP_TOPAZ:
990 default:
991 /* change this when we support soft reset */
992 return true;
993 }
994}
995
b45e18ac
KR		 996static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
997 uint64_t *count1)
998{
999 uint32_t perfctr = 0;
1000 uint64_t cnt0_of, cnt1_of;
1001 int tmp;
1002
1003 /* This reports 0 on APUs, so return to avoid writing/reading registers
1004 * that may or may not be different from their GPU counterparts
1005 */
1006 if (adev->flags & AMD_IS_APU)
1007 return;
1008
1009 /* Set the 2 events that we wish to watch, defined above */
1010 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1011 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1012 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1013
1014 /* Write to enable desired perf counters */
1015 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1016 /* Zero out and enable the perf counters
1017 * Write 0x5:
1018 * Bit 0 = Start all counters(1)
1019 * Bit 2 = Global counter reset enable(1)
1020 */
1021 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1022
1023 msleep(1000);
1024
1025 /* Load the shadow and disable the perf counters
1026 * Write 0x2:
1027 * Bit 0 = Stop counters(0)
1028 * Bit 1 = Load the shadow counters(1)
1029 */
1030 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1031
1032 /* Read register values to get any >32bit overflow */
1033 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1034 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1035 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1036
1037 /* Get the values and add the overflow */
1038 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1039 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1040}
1041
dcea6e65
KR		 1042static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1043{
1044 uint64_t nak_r, nak_g;
1045
1046 /* Get the number of NAKs received and generated */
1047 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1048 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1049
1050 /* Add the total number of NAKs, i.e the number of replays */
1051 return (nak_r + nak_g);
1052}
1053
762e6f3f
AD		 1054static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1055{
1056 u32 clock_cntl, pc;
1057
1058 if (adev->flags & AMD_IS_APU)
1059 return false;
1060
1061 /* check if the SMC is already running */
1062 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1063 pc = RREG32_SMC(ixSMC_PC_C);
1064 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1065 (0x20100 <= pc))
1066 return true;
1067
1068 return false;
1069}
1070
cff6c7f9
AD		 1071static void vi_pre_asic_init(struct amdgpu_device *adev)
1072{
1073}
1074
aaa36a97
AD		 1075static const struct amdgpu_asic_funcs vi_asic_funcs =
1076{
1077 .read_disabled_bios = &vi_read_disabled_bios,
95addb2a 1078 .read_bios_from_rom = &vi_read_bios_from_rom,
aaa36a97
AD		 1079 .read_register = &vi_read_register,
1080 .reset = &vi_asic_reset,
9bc1932f 1081 .reset_method = &vi_asic_reset_method,
aaa36a97
AD		 1082 .set_vga_state = &vi_vga_set_state,
1083 .get_xclk = &vi_get_xclk,
1084 .set_uvd_clocks = &vi_set_uvd_clocks,
1085 .set_vce_clocks = &vi_set_vce_clocks,
bbf282d8 1086 .get_config_memsize = &vi_get_config_memsize,
dd8d07f2
AD		 1087 .flush_hdp = &vi_flush_hdp,
1088 .invalidate_hdp = &vi_invalidate_hdp,
06082d9b 1089 .need_full_reset = &vi_need_full_reset,
4e2c1ac2 1090 .init_doorbell_index = &legacy_doorbell_index_init,
b45e18ac 1091 .get_pcie_usage = &vi_get_pcie_usage,
762e6f3f 1092 .need_reset_on_init = &vi_need_reset_on_init,
dcea6e65 1093 .get_pcie_replay_count = &vi_get_pcie_replay_count,
e45ed943 1094 .supports_baco = &vi_asic_supports_baco,
cff6c7f9 1095 .pre_asic_init = &vi_pre_asic_init,
aaa36a97
AD		 1096};
1097
170d6e94
EH		 1098#define CZ_REV_BRISTOL(rev) \
1099 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1100
5fc3aeeb 1101static int vi_common_early_init(void *handle)
aaa36a97 1102{
5fc3aeeb 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 1104
2f7d10b3 1105 if (adev->flags & AMD_IS_APU) {
7b92cdbf
AD		 1106 adev->smc_rreg = &cz_smc_rreg;
1107 adev->smc_wreg = &cz_smc_wreg;
1108 } else {
1109 adev->smc_rreg = &vi_smc_rreg;
1110 adev->smc_wreg = &vi_smc_wreg;
1111 }
aaa36a97
AD		 1112 adev->pcie_rreg = &vi_pcie_rreg;
1113 adev->pcie_wreg = &vi_pcie_wreg;
1114 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1115 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1116 adev->didt_rreg = &vi_didt_rreg;
1117 adev->didt_wreg = &vi_didt_wreg;
ccdbb20a
RZ		 1118 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1119 adev->gc_cac_wreg = &vi_gc_cac_wreg;
aaa36a97
AD		 1120
1121 adev->asic_funcs = &vi_asic_funcs;
1122
aaa36a97
AD		 1123 adev->rev_id = vi_get_rev_id(adev);
1124 adev->external_rev_id = 0xFF;
1125 switch (adev->asic_type) {
1126 case CHIP_TOPAZ:
aaa36a97
AD		 1127 adev->cg_flags = 0;
1128 adev->pg_flags = 0;
1129 adev->external_rev_id = 0x1;
aaa36a97 1130 break;
48299f95 1131 case CHIP_FIJI:
14698b6c
AD		 1132 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1133 AMD_CG_SUPPORT_GFX_MGLS |
1134 AMD_CG_SUPPORT_GFX_RLC_LS |
1135 AMD_CG_SUPPORT_GFX_CP_LS |
1136 AMD_CG_SUPPORT_GFX_CGTS |
1137 AMD_CG_SUPPORT_GFX_CGTS_LS |
1138 AMD_CG_SUPPORT_GFX_CGCG |
e08d53cb
AD		 1139 AMD_CG_SUPPORT_GFX_CGLS |
1140 AMD_CG_SUPPORT_SDMA_MGCG |
c90766cf
AD		 1141 AMD_CG_SUPPORT_SDMA_LS |
1142 AMD_CG_SUPPORT_BIF_LS |
1143 AMD_CG_SUPPORT_HDP_MGCG |
1144 AMD_CG_SUPPORT_HDP_LS |
3fde56b8
AD		 1145 AMD_CG_SUPPORT_ROM_MGCG |
1146 AMD_CG_SUPPORT_MC_MGCG |
79abf1ad
RZ		 1147 AMD_CG_SUPPORT_MC_LS |
1148 AMD_CG_SUPPORT_UVD_MGCG;
b6bc28ff
FC		 1149 adev->pg_flags = 0;
1150 adev->external_rev_id = adev->rev_id + 0x3c;
1151 break;
aaa36a97 1152 case CHIP_TONGA:
ca18b849
RZ		 1153 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1154 AMD_CG_SUPPORT_GFX_CGCG |
1155 AMD_CG_SUPPORT_GFX_CGLS |
1156 AMD_CG_SUPPORT_SDMA_MGCG |
1157 AMD_CG_SUPPORT_SDMA_LS |
1158 AMD_CG_SUPPORT_BIF_LS |
1159 AMD_CG_SUPPORT_HDP_MGCG |
1160 AMD_CG_SUPPORT_HDP_LS |
1161 AMD_CG_SUPPORT_ROM_MGCG |
1162 AMD_CG_SUPPORT_MC_MGCG |
1163 AMD_CG_SUPPORT_MC_LS |
1164 AMD_CG_SUPPORT_DRM_LS |
1165 AMD_CG_SUPPORT_UVD_MGCG;
54971406 1166 adev->pg_flags = 0;
aaa36a97 1167 adev->external_rev_id = adev->rev_id + 0x14;
aaa36a97 1168 break;
2cc0c0b5 1169 case CHIP_POLARIS11:
ca18b849
RZ		 1170 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1171 AMD_CG_SUPPORT_GFX_RLC_LS |
1172 AMD_CG_SUPPORT_GFX_CP_LS |
1173 AMD_CG_SUPPORT_GFX_CGCG |
1174 AMD_CG_SUPPORT_GFX_CGLS |
1175 AMD_CG_SUPPORT_GFX_3D_CGCG |
1176 AMD_CG_SUPPORT_GFX_3D_CGLS |
1177 AMD_CG_SUPPORT_SDMA_MGCG |
1178 AMD_CG_SUPPORT_SDMA_LS |
1179 AMD_CG_SUPPORT_BIF_MGCG |
1180 AMD_CG_SUPPORT_BIF_LS |
1181 AMD_CG_SUPPORT_HDP_MGCG |
1182 AMD_CG_SUPPORT_HDP_LS |
1183 AMD_CG_SUPPORT_ROM_MGCG |
1184 AMD_CG_SUPPORT_MC_MGCG |
1185 AMD_CG_SUPPORT_MC_LS |
1186 AMD_CG_SUPPORT_DRM_LS |
1187 AMD_CG_SUPPORT_UVD_MGCG |
ecc2cf7c 1188 AMD_CG_SUPPORT_VCE_MGCG;
c0c1f579
FC		 1189 adev->pg_flags = 0;
1190 adev->external_rev_id = adev->rev_id + 0x5A;
1191 break;
2cc0c0b5 1192 case CHIP_POLARIS10:
ca18b849
RZ		 1193 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1194 AMD_CG_SUPPORT_GFX_RLC_LS |
1195 AMD_CG_SUPPORT_GFX_CP_LS |
1196 AMD_CG_SUPPORT_GFX_CGCG |
1197 AMD_CG_SUPPORT_GFX_CGLS |
1198 AMD_CG_SUPPORT_GFX_3D_CGCG |
1199 AMD_CG_SUPPORT_GFX_3D_CGLS |
1200 AMD_CG_SUPPORT_SDMA_MGCG |
1201 AMD_CG_SUPPORT_SDMA_LS |
1202 AMD_CG_SUPPORT_BIF_MGCG |
1203 AMD_CG_SUPPORT_BIF_LS |
1204 AMD_CG_SUPPORT_HDP_MGCG |
1205 AMD_CG_SUPPORT_HDP_LS |
1206 AMD_CG_SUPPORT_ROM_MGCG |
1207 AMD_CG_SUPPORT_MC_MGCG |
1208 AMD_CG_SUPPORT_MC_LS |
1209 AMD_CG_SUPPORT_DRM_LS |
1210 AMD_CG_SUPPORT_UVD_MGCG |
ecc2cf7c 1211 AMD_CG_SUPPORT_VCE_MGCG;
c0c1f579
FC		 1212 adev->pg_flags = 0;
1213 adev->external_rev_id = adev->rev_id + 0x50;
1214 break;
c4642a47 1215 case CHIP_POLARIS12:
739e9fff
RZ		 1216 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1217 AMD_CG_SUPPORT_GFX_RLC_LS |
1218 AMD_CG_SUPPORT_GFX_CP_LS |
1219 AMD_CG_SUPPORT_GFX_CGCG |
1220 AMD_CG_SUPPORT_GFX_CGLS |
1221 AMD_CG_SUPPORT_GFX_3D_CGCG |
1222 AMD_CG_SUPPORT_GFX_3D_CGLS |
1223 AMD_CG_SUPPORT_SDMA_MGCG |
1224 AMD_CG_SUPPORT_SDMA_LS |
1225 AMD_CG_SUPPORT_BIF_MGCG |
1226 AMD_CG_SUPPORT_BIF_LS |
1227 AMD_CG_SUPPORT_HDP_MGCG |
1228 AMD_CG_SUPPORT_HDP_LS |
1229 AMD_CG_SUPPORT_ROM_MGCG |
1230 AMD_CG_SUPPORT_MC_MGCG |
1231 AMD_CG_SUPPORT_MC_LS |
1232 AMD_CG_SUPPORT_DRM_LS |
1233 AMD_CG_SUPPORT_UVD_MGCG |
1234 AMD_CG_SUPPORT_VCE_MGCG;
c4642a47
JZ		 1235 adev->pg_flags = 0;
1236 adev->external_rev_id = adev->rev_id + 0x64;
1237 break;
b51c5194
LL		 1238 case CHIP_VEGAM:
1239 adev->cg_flags = 0;
1240 /*AMD_CG_SUPPORT_GFX_MGCG |
1241 AMD_CG_SUPPORT_GFX_RLC_LS |
1242 AMD_CG_SUPPORT_GFX_CP_LS |
1243 AMD_CG_SUPPORT_GFX_CGCG |
1244 AMD_CG_SUPPORT_GFX_CGLS |
1245 AMD_CG_SUPPORT_GFX_3D_CGCG |
1246 AMD_CG_SUPPORT_GFX_3D_CGLS |
1247 AMD_CG_SUPPORT_SDMA_MGCG |
1248 AMD_CG_SUPPORT_SDMA_LS |
1249 AMD_CG_SUPPORT_BIF_MGCG |
1250 AMD_CG_SUPPORT_BIF_LS |
1251 AMD_CG_SUPPORT_HDP_MGCG |
1252 AMD_CG_SUPPORT_HDP_LS |
1253 AMD_CG_SUPPORT_ROM_MGCG |
1254 AMD_CG_SUPPORT_MC_MGCG |
1255 AMD_CG_SUPPORT_MC_LS |
1256 AMD_CG_SUPPORT_DRM_LS |
1257 AMD_CG_SUPPORT_UVD_MGCG |
1258 AMD_CG_SUPPORT_VCE_MGCG;*/
1259 adev->pg_flags = 0;
1260 adev->external_rev_id = adev->rev_id + 0x6E;
1261 break;
aaa36a97 1262 case CHIP_CARRIZO:
f0f3a8fb
TSD		 1263 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1264 AMD_CG_SUPPORT_GFX_MGCG |
70eced9b
AD		 1265 AMD_CG_SUPPORT_GFX_MGLS |
1266 AMD_CG_SUPPORT_GFX_RLC_LS |
1267 AMD_CG_SUPPORT_GFX_CP_LS |
1268 AMD_CG_SUPPORT_GFX_CGTS |
70eced9b 1269 AMD_CG_SUPPORT_GFX_CGTS_LS |
fb4bbba2 1270 AMD_CG_SUPPORT_GFX_CGCG |
03c335d3
AD		 1271 AMD_CG_SUPPORT_GFX_CGLS |
1272 AMD_CG_SUPPORT_BIF_LS |
1273 AMD_CG_SUPPORT_HDP_MGCG |
6f17a257
AD		 1274 AMD_CG_SUPPORT_HDP_LS |
1275 AMD_CG_SUPPORT_SDMA_MGCG |
1af69a2c
TSD		 1276 AMD_CG_SUPPORT_SDMA_LS |
1277 AMD_CG_SUPPORT_VCE_MGCG;
f6ade304 1278 /* rev0 hardware requires workarounds to support PG */
0fd4af9e 1279 adev->pg_flags = 0;
170d6e94 1280 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
c2cade3d 1281 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
65b42622 1282 AMD_PG_SUPPORT_GFX_PIPELINE |
98fccc78 1283 AMD_PG_SUPPORT_CP |
2ed0936d
TSD		 1284 AMD_PG_SUPPORT_UVD |
1285 AMD_PG_SUPPORT_VCE;
f6ade304 1286 }
aaa36a97 1287 adev->external_rev_id = adev->rev_id + 0x1;
aaa36a97 1288 break;
cde64939 1289 case CHIP_STONEY:
64694905
AD		 1290 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1291 AMD_CG_SUPPORT_GFX_MGCG |
b6711d1b 1292 AMD_CG_SUPPORT_GFX_MGLS |
413cf600
TSD		 1293 AMD_CG_SUPPORT_GFX_RLC_LS |
1294 AMD_CG_SUPPORT_GFX_CP_LS |
1295 AMD_CG_SUPPORT_GFX_CGTS |
413cf600 1296 AMD_CG_SUPPORT_GFX_CGTS_LS |
413cf600 1297 AMD_CG_SUPPORT_GFX_CGLS |
b6711d1b
AD		 1298 AMD_CG_SUPPORT_BIF_LS |
1299 AMD_CG_SUPPORT_HDP_MGCG |
1bf912ff
AD		 1300 AMD_CG_SUPPORT_HDP_LS |
1301 AMD_CG_SUPPORT_SDMA_MGCG |
8ef583e9
TSD		 1302 AMD_CG_SUPPORT_SDMA_LS |
1303 AMD_CG_SUPPORT_VCE_MGCG;
e6b2a7d2 1304 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
4e86be75 1305 AMD_PG_SUPPORT_GFX_SMG |
c2cdb042 1306 AMD_PG_SUPPORT_GFX_PIPELINE |
98fccc78 1307 AMD_PG_SUPPORT_CP |
75419c43
TSD		 1308 AMD_PG_SUPPORT_UVD |
1309 AMD_PG_SUPPORT_VCE;
a47c78d9 1310 adev->external_rev_id = adev->rev_id + 0x61;
cde64939 1311 break;
aaa36a97
AD		 1312 default:
1313 /* FIXME: not supported yet */
1314 return -EINVAL;
1315 }
1316
ab276632
XY		 1317 if (amdgpu_sriov_vf(adev)) {
1318 amdgpu_virt_init_setting(adev);
1319 xgpu_vi_mailbox_set_irq_funcs(adev);
1320 }
1321
aaa36a97
AD		 1322 return 0;
1323}
1324
99581cc5
XY		 1325static int vi_common_late_init(void *handle)
1326{
1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328
1329 if (amdgpu_sriov_vf(adev))
1330 xgpu_vi_mailbox_get_irq(adev);
1331
1332 return 0;
1333}
1334
5fc3aeeb 1335static int vi_common_sw_init(void *handle)
aaa36a97 1336{
99581cc5
XY		 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338
1339 if (amdgpu_sriov_vf(adev))
1340 xgpu_vi_mailbox_add_irq_id(adev);
1341
aaa36a97
AD		 1342 return 0;
1343}
1344
5fc3aeeb 1345static int vi_common_sw_fini(void *handle)
aaa36a97
AD		 1346{
1347 return 0;
1348}
1349
5fc3aeeb 1350static int vi_common_hw_init(void *handle)
aaa36a97 1351{
5fc3aeeb 1352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1353
aaa36a97
AD		 1354 /* move the golden regs per IP block */
1355 vi_init_golden_registers(adev);
1356 /* enable pcie gen2/3 link */
1357 vi_pcie_gen3_enable(adev);
1358 /* enable aspm */
1359 vi_program_aspm(adev);
1360 /* enable the doorbell aperture */
1361 vi_enable_doorbell_aperture(adev, true);
1362
1363 return 0;
1364}
1365
5fc3aeeb 1366static int vi_common_hw_fini(void *handle)
aaa36a97 1367{
5fc3aeeb 1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
aaa36a97
AD		 1370 /* enable the doorbell aperture */
1371 vi_enable_doorbell_aperture(adev, false);
1372
63d24f88
XY		 1373 if (amdgpu_sriov_vf(adev))
1374 xgpu_vi_mailbox_put_irq(adev);
1375
aaa36a97
AD		 1376 return 0;
1377}
1378
5fc3aeeb 1379static int vi_common_suspend(void *handle)
aaa36a97 1380{
5fc3aeeb 1381 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1382
aaa36a97
AD		 1383 return vi_common_hw_fini(adev);
1384}
1385
5fc3aeeb 1386static int vi_common_resume(void *handle)
aaa36a97 1387{
5fc3aeeb 1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1389
aaa36a97
AD		 1390 return vi_common_hw_init(adev);
1391}
1392
5fc3aeeb 1393static bool vi_common_is_idle(void *handle)
aaa36a97
AD		 1394{
1395 return true;
1396}
1397
5fc3aeeb 1398static int vi_common_wait_for_idle(void *handle)
aaa36a97
AD		 1399{
1400 return 0;
1401}
1402
5fc3aeeb 1403static int vi_common_soft_reset(void *handle)
aaa36a97 1404{
aaa36a97
AD		 1405 return 0;
1406}
1407
76f10b9a
AD		 1408static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1409 bool enable)
6cec2655
EH		 1410{
1411 uint32_t temp, data;
1412
1413 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1414
c90766cf 1415 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
6cec2655
EH		 1416 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1417 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1418 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1419 else
1420 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1421 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1422 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1423
1424 if (temp != data)
1425 WREG32_PCIE(ixPCIE_CNTL2, data);
1426}
1427
76f10b9a
AD		 1428static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1429 bool enable)
6cec2655
EH		 1430{
1431 uint32_t temp, data;
1432
1433 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1434
c90766cf 1435 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
6cec2655
EH		 1436 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1437 else
1438 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1439
1440 if (temp != data)
1441 WREG32(mmHDP_HOST_PATH_CNTL, data);
1442}
1443
76f10b9a
AD		 1444static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1445 bool enable)
6cec2655
EH		 1446{
1447 uint32_t temp, data;
1448
1449 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1450
c90766cf 1451 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
6cec2655
EH		 1452 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1453 else
1454 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1455
1456 if (temp != data)
1457 WREG32(mmHDP_MEM_POWER_LS, data);
1458}
1459
f6f534e2
RZ		 1460static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1461 bool enable)
1462{
1463 uint32_t temp, data;
1464
1465 temp = data = RREG32(0x157a);
1466
1467 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1468 data |= 1;
1469 else
1470 data &= ~1;
1471
1472 if (temp != data)
1473 WREG32(0x157a, data);
1474}
1475
1476
76f10b9a
AD		 1477static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1478 bool enable)
6cec2655
EH		 1479{
1480 uint32_t temp, data;
1481
1482 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1483
c90766cf 1484 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
6cec2655
EH		 1485 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1486 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1487 else
1488 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1489 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1490
1491 if (temp != data)
1492 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1493}
1494
1bb08f91
RZ		 1495static int vi_common_set_clockgating_state_by_smu(void *handle,
1496 enum amd_clockgating_state state)
1497{
8a19e7fa
RZ		 1498 uint32_t msg_id, pp_state = 0;
1499 uint32_t pp_support_state = 0;
1bb08f91 1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1bb08f91 1501
8a19e7fa
RZ		 1502 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1503 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
3f2ddfa8 1504 pp_support_state = PP_STATE_SUPPORT_LS;
8a19e7fa
RZ		 1505 pp_state = PP_STATE_LS;
1506 }
1507 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
3f2ddfa8 1508 pp_support_state |= PP_STATE_SUPPORT_CG;
8a19e7fa
RZ		 1509 pp_state |= PP_STATE_CG;
1510 }
1511 if (state == AMD_CG_STATE_UNGATE)
1512 pp_state = 0;
1513 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1514 PP_BLOCK_SYS_MC,
1515 pp_support_state,
1516 pp_state);
b89e9eb6 1517 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1518 }
1519
1520 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1521 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
3f2ddfa8 1522 pp_support_state = PP_STATE_SUPPORT_LS;
8a19e7fa
RZ		 1523 pp_state = PP_STATE_LS;
1524 }
1525 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
3f2ddfa8 1526 pp_support_state |= PP_STATE_SUPPORT_CG;
8a19e7fa
RZ		 1527 pp_state |= PP_STATE_CG;
1528 }
1529 if (state == AMD_CG_STATE_UNGATE)
1530 pp_state = 0;
1531 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1532 PP_BLOCK_SYS_SDMA,
1533 pp_support_state,
1534 pp_state);
b89e9eb6 1535 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1536 }
1537
1538 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1539 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
3f2ddfa8 1540 pp_support_state = PP_STATE_SUPPORT_LS;
8a19e7fa
RZ		 1541 pp_state = PP_STATE_LS;
1542 }
1543 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
3f2ddfa8 1544 pp_support_state |= PP_STATE_SUPPORT_CG;
8a19e7fa
RZ		 1545 pp_state |= PP_STATE_CG;
1546 }
1547 if (state == AMD_CG_STATE_UNGATE)
1548 pp_state = 0;
1549 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1550 PP_BLOCK_SYS_HDP,
1551 pp_support_state,
1552 pp_state);
b89e9eb6 1553 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa 1554 }
1bb08f91 1555
8a19e7fa
RZ		 1556
1557 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1558 if (state == AMD_CG_STATE_UNGATE)
1559 pp_state = 0;
1560 else
1561 pp_state = PP_STATE_LS;
1562
1563 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1564 PP_BLOCK_SYS_BIF,
1565 PP_STATE_SUPPORT_LS,
1566 pp_state);
b89e9eb6 1567 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1568 }
1569 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1570 if (state == AMD_CG_STATE_UNGATE)
1571 pp_state = 0;
1572 else
1573 pp_state = PP_STATE_CG;
1574
1575 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1576 PP_BLOCK_SYS_BIF,
1577 PP_STATE_SUPPORT_CG,
1578 pp_state);
b89e9eb6 1579 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1580 }
1581
1582 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1583
1584 if (state == AMD_CG_STATE_UNGATE)
1585 pp_state = 0;
1586 else
1587 pp_state = PP_STATE_LS;
1588
1589 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1590 PP_BLOCK_SYS_DRM,
1591 PP_STATE_SUPPORT_LS,
1592 pp_state);
b89e9eb6 1593 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa
RZ		 1594 }
1595
1596 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1597
1598 if (state == AMD_CG_STATE_UNGATE)
1599 pp_state = 0;
1600 else
1601 pp_state = PP_STATE_CG;
1602
1603 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1604 PP_BLOCK_SYS_ROM,
1605 PP_STATE_SUPPORT_CG,
1606 pp_state);
b89e9eb6 1607 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
8a19e7fa 1608 }
1bb08f91
RZ		 1609 return 0;
1610}
1611
5fc3aeeb 1612static int vi_common_set_clockgating_state(void *handle,
c90766cf 1613 enum amd_clockgating_state state)
aaa36a97 1614{
6cec2655
EH		 1615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1616
ce137c04
ML		 1617 if (amdgpu_sriov_vf(adev))
1618 return 0;
1619
6cec2655
EH		 1620 switch (adev->asic_type) {
1621 case CHIP_FIJI:
76f10b9a 1622 vi_update_bif_medium_grain_light_sleep(adev,
7e913664 1623 state == AMD_CG_STATE_GATE);
76f10b9a 1624 vi_update_hdp_medium_grain_clock_gating(adev,
7e913664 1625 state == AMD_CG_STATE_GATE);
76f10b9a 1626 vi_update_hdp_light_sleep(adev,
7e913664 1627 state == AMD_CG_STATE_GATE);
76f10b9a 1628 vi_update_rom_medium_grain_clock_gating(adev,
7e913664 1629 state == AMD_CG_STATE_GATE);
76f10b9a
AD		 1630 break;
1631 case CHIP_CARRIZO:
1632 case CHIP_STONEY:
1633 vi_update_bif_medium_grain_light_sleep(adev,
7e913664 1634 state == AMD_CG_STATE_GATE);
76f10b9a 1635 vi_update_hdp_medium_grain_clock_gating(adev,
7e913664 1636 state == AMD_CG_STATE_GATE);
76f10b9a 1637 vi_update_hdp_light_sleep(adev,
7e913664 1638 state == AMD_CG_STATE_GATE);
f6f534e2 1639 vi_update_drm_light_sleep(adev,
7e913664 1640 state == AMD_CG_STATE_GATE);
6cec2655 1641 break;
1bb08f91
RZ		 1642 case CHIP_TONGA:
1643 case CHIP_POLARIS10:
1644 case CHIP_POLARIS11:
c4642a47 1645 case CHIP_POLARIS12:
b51c5194 1646 case CHIP_VEGAM:
1bb08f91 1647 vi_common_set_clockgating_state_by_smu(adev, state);
9304ca4d 1648 break;
6cec2655
EH		 1649 default:
1650 break;
1651 }
aaa36a97
AD		 1652 return 0;
1653}
1654
5fc3aeeb 1655static int vi_common_set_powergating_state(void *handle,
1656 enum amd_powergating_state state)
aaa36a97
AD		 1657{
1658 return 0;
1659}
1660
abd2c2fe
HR		 1661static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1662{
1663 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1664 int data;
1665
ce137c04
ML		 1666 if (amdgpu_sriov_vf(adev))
1667 *flags = 0;
1668
abd2c2fe
HR		 1669 /* AMD_CG_SUPPORT_BIF_LS */
1670 data = RREG32_PCIE(ixPCIE_CNTL2);
1671 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1672 *flags |= AMD_CG_SUPPORT_BIF_LS;
1673
1674 /* AMD_CG_SUPPORT_HDP_LS */
1675 data = RREG32(mmHDP_MEM_POWER_LS);
1676 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1677 *flags |= AMD_CG_SUPPORT_HDP_LS;
1678
1679 /* AMD_CG_SUPPORT_HDP_MGCG */
1680 data = RREG32(mmHDP_HOST_PATH_CNTL);
1681 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1682 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1683
1684 /* AMD_CG_SUPPORT_ROM_MGCG */
1685 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1686 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1687 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1688}
1689
a1255107 1690static const struct amd_ip_funcs vi_common_ip_funcs = {
88a907d6 1691 .name = "vi_common",
aaa36a97 1692 .early_init = vi_common_early_init,
99581cc5 1693 .late_init = vi_common_late_init,
aaa36a97
AD		 1694 .sw_init = vi_common_sw_init,
1695 .sw_fini = vi_common_sw_fini,
1696 .hw_init = vi_common_hw_init,
1697 .hw_fini = vi_common_hw_fini,
1698 .suspend = vi_common_suspend,
1699 .resume = vi_common_resume,
1700 .is_idle = vi_common_is_idle,
1701 .wait_for_idle = vi_common_wait_for_idle,
1702 .soft_reset = vi_common_soft_reset,
aaa36a97
AD		 1703 .set_clockgating_state = vi_common_set_clockgating_state,
1704 .set_powergating_state = vi_common_set_powergating_state,
abd2c2fe 1705 .get_clockgating_state = vi_common_get_clockgating_state,
aaa36a97
AD		 1706};
1707
a1255107
AD		 1708static const struct amdgpu_ip_block_version vi_common_ip_block =
1709{
1710 .type = AMD_IP_BLOCK_TYPE_COMMON,
1711 .major = 1,
1712 .minor = 0,
1713 .rev = 0,
1714 .funcs = &vi_common_ip_funcs,
1715};
1716
c1299461 1717void vi_set_virt_ops(struct amdgpu_device *adev)
a1255107 1718{
c1299461
WS		 1719 adev->virt.ops = &xgpu_vi_virt_ops;
1720}
99581cc5 1721
c1299461
WS		 1722int vi_set_ip_blocks(struct amdgpu_device *adev)
1723{
a1255107
AD		 1724 switch (adev->asic_type) {
1725 case CHIP_TOPAZ:
1726 /* topaz has no DCE, UVD, VCE */
2990a1fc
AD		 1727 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1728 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1729 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
71195ba6
RZ		 1730 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1731 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
b905090d 1732 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1733 if (adev->enable_virtual_display)
2990a1fc 1734 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
a1255107
AD		 1735 break;
1736 case CHIP_FIJI:
2990a1fc
AD		 1737 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1738 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1739 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
71195ba6
RZ		 1740 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1741 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1742 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
91caa081 1743 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 1744 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1745#if defined(CONFIG_DRM_AMD_DC)
1746 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1747 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1748#endif
a1255107 1749 else
2990a1fc 1750 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
91caa081 1751 if (!amdgpu_sriov_vf(adev)) {
2990a1fc
AD		 1752 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1753 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
91caa081 1754 }
a1255107
AD		 1755 break;
1756 case CHIP_TONGA:
2990a1fc
AD		 1757 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1758 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1759 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
71195ba6
RZ		 1760 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1761 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1762 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
91caa081 1763 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 1764 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1765#if defined(CONFIG_DRM_AMD_DC)
1766 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1767 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1768#endif
a1255107 1769 else
2990a1fc 1770 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
91caa081 1771 if (!amdgpu_sriov_vf(adev)) {
2990a1fc
AD		 1772 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1773 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
91caa081 1774 }
a1255107 1775 break;
a1255107 1776 case CHIP_POLARIS10:
b51c5194 1777 case CHIP_POLARIS11:
c4642a47 1778 case CHIP_POLARIS12:
b51c5194 1779 case CHIP_VEGAM:
2990a1fc
AD		 1780 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1781 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1782 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
71195ba6
RZ		 1783 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1784 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
b905090d 1785 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1786 if (adev->enable_virtual_display)
2990a1fc 1787 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1788#if defined(CONFIG_DRM_AMD_DC)
1789 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1790 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1791#endif
a1255107 1792 else
2990a1fc 1793 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
2990a1fc
AD		 1794 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1795 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
a1255107
AD		 1796 break;
1797 case CHIP_CARRIZO:
2990a1fc
AD		 1798 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1799 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1800 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
71195ba6
RZ		 1801 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1802 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1803 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1804 if (adev->enable_virtual_display)
2990a1fc 1805 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1806#if defined(CONFIG_DRM_AMD_DC)
1807 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1808 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1809#endif
a1255107 1810 else
2990a1fc 1811 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2990a1fc
AD		 1812 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1813 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
a1255107 1814#if defined(CONFIG_DRM_AMD_ACP)
2990a1fc 1815 amdgpu_device_ip_block_add(adev, &acp_ip_block);
a1255107
AD		 1816#endif
1817 break;
1818 case CHIP_STONEY:
2990a1fc
AD		 1819 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1820 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1821 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
71195ba6
RZ		 1822 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1823 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
b905090d 1824 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
a1255107 1825 if (adev->enable_virtual_display)
2990a1fc 1826 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
4562236b
HW		 1827#if defined(CONFIG_DRM_AMD_DC)
1828 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 1829 amdgpu_device_ip_block_add(adev, &dm_ip_block);
4562236b 1830#endif
a1255107 1831 else
2990a1fc 1832 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2990a1fc
AD		 1833 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1834 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
a1255107 1835#if defined(CONFIG_DRM_AMD_ACP)
2990a1fc 1836 amdgpu_device_ip_block_add(adev, &acp_ip_block);
a1255107
AD		 1837#endif
1838 break;
1839 default:
1840 /* FIXME: not supported yet */
1841 return -EINVAL;
1842 }
1843
1844 return 0;
1845}
4e2c1ac2
OZ		 1846
1847void legacy_doorbell_index_init(struct amdgpu_device *adev)
1848{
1849 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1850 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1851 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1852 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1853 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1854 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1855 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1856 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1857 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1858 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
898e0d9d
OZ		 1859 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1860 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
4e2c1ac2
OZ		 1861 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1862 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1863}
Linux 6.x block layer and io_uring tree(s)