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282aae55 KW |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
248a1d6f | 23 | #include <drm/drmP.h> |
282aae55 KW |
24 | #include "amdgpu.h" |
25 | #include "amdgpu_ih.h" | |
26 | #include "soc15.h" | |
27 | ||
8af7454e FX |
28 | #include "oss/osssys_4_0_offset.h" |
29 | #include "oss/osssys_4_0_sh_mask.h" | |
282aae55 KW |
30 | |
31 | #include "soc15_common.h" | |
32 | #include "vega10_ih.h" | |
33 | ||
34 | ||
35 | ||
36 | static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); | |
37 | ||
38 | /** | |
39 | * vega10_ih_enable_interrupts - Enable the interrupt ring buffer | |
40 | * | |
41 | * @adev: amdgpu_device pointer | |
42 | * | |
43 | * Enable the interrupt ring buffer (VEGA10). | |
44 | */ | |
45 | static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) | |
46 | { | |
b2b7e457 | 47 | u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); |
282aae55 KW |
48 | |
49 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); | |
50 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); | |
b2b7e457 | 51 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); |
282aae55 KW |
52 | adev->irq.ih.enabled = true; |
53 | } | |
54 | ||
55 | /** | |
56 | * vega10_ih_disable_interrupts - Disable the interrupt ring buffer | |
57 | * | |
58 | * @adev: amdgpu_device pointer | |
59 | * | |
60 | * Disable the interrupt ring buffer (VEGA10). | |
61 | */ | |
62 | static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) | |
63 | { | |
b2b7e457 | 64 | u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); |
282aae55 KW |
65 | |
66 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); | |
67 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); | |
b2b7e457 | 68 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); |
282aae55 | 69 | /* set rptr, wptr to 0 */ |
b2b7e457 HZ |
70 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); |
71 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); | |
282aae55 KW |
72 | adev->irq.ih.enabled = false; |
73 | adev->irq.ih.rptr = 0; | |
74 | } | |
75 | ||
76 | /** | |
77 | * vega10_ih_irq_init - init and enable the interrupt ring | |
78 | * | |
79 | * @adev: amdgpu_device pointer | |
80 | * | |
81 | * Allocate a ring buffer for the interrupt controller, | |
82 | * enable the RLC, disable interrupts, enable the IH | |
83 | * ring buffer and enable it (VI). | |
84 | * Called at device load and reume. | |
85 | * Returns 0 for success, errors for failure. | |
86 | */ | |
87 | static int vega10_ih_irq_init(struct amdgpu_device *adev) | |
88 | { | |
89 | int ret = 0; | |
90 | int rb_bufsz; | |
91 | u32 ih_rb_cntl, ih_doorbell_rtpr; | |
92 | u32 tmp; | |
93 | u64 wptr_off; | |
94 | ||
95 | /* disable irqs */ | |
96 | vega10_ih_disable_interrupts(adev); | |
97 | ||
bf383fb6 | 98 | adev->nbio_funcs->ih_control(adev); |
282aae55 | 99 | |
b2b7e457 | 100 | ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); |
282aae55 KW |
101 | /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ |
102 | if (adev->irq.ih.use_bus_addr) { | |
b2b7e457 HZ |
103 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); |
104 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); | |
282aae55 KW |
105 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); |
106 | } else { | |
b2b7e457 HZ |
107 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); |
108 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff); | |
282aae55 KW |
109 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); |
110 | } | |
111 | rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); | |
112 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); | |
113 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); | |
114 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); | |
115 | /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ | |
116 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); | |
117 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); | |
118 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); | |
119 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); | |
120 | ||
121 | if (adev->irq.msi_enabled) | |
122 | ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); | |
123 | ||
b2b7e457 | 124 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); |
282aae55 KW |
125 | |
126 | /* set the writeback address whether it's enabled or not */ | |
127 | if (adev->irq.ih.use_bus_addr) | |
128 | wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); | |
129 | else | |
130 | wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); | |
b2b7e457 HZ |
131 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); |
132 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); | |
282aae55 KW |
133 | |
134 | /* set rptr, wptr to 0 */ | |
b2b7e457 HZ |
135 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); |
136 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); | |
282aae55 | 137 | |
b2b7e457 | 138 | ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); |
282aae55 KW |
139 | if (adev->irq.ih.use_doorbell) { |
140 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, | |
141 | OFFSET, adev->irq.ih.doorbell_index); | |
142 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, | |
143 | ENABLE, 1); | |
144 | } else { | |
145 | ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, | |
146 | ENABLE, 0); | |
147 | } | |
b2b7e457 | 148 | WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); |
bf383fb6 AD |
149 | adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, |
150 | adev->irq.ih.doorbell_index); | |
282aae55 | 151 | |
b2b7e457 | 152 | tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); |
282aae55 KW |
153 | tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, |
154 | CLIENT18_IS_STORM_CLIENT, 1); | |
b2b7e457 | 155 | WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); |
282aae55 | 156 | |
b2b7e457 | 157 | tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); |
282aae55 | 158 | tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); |
b2b7e457 | 159 | WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); |
282aae55 KW |
160 | |
161 | pci_set_master(adev->pdev); | |
162 | ||
163 | /* enable interrupts */ | |
164 | vega10_ih_enable_interrupts(adev); | |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
169 | /** | |
170 | * vega10_ih_irq_disable - disable interrupts | |
171 | * | |
172 | * @adev: amdgpu_device pointer | |
173 | * | |
174 | * Disable interrupts on the hw (VEGA10). | |
175 | */ | |
176 | static void vega10_ih_irq_disable(struct amdgpu_device *adev) | |
177 | { | |
178 | vega10_ih_disable_interrupts(adev); | |
179 | ||
180 | /* Wait and acknowledge irq */ | |
181 | mdelay(1); | |
182 | } | |
183 | ||
184 | /** | |
185 | * vega10_ih_get_wptr - get the IH ring buffer wptr | |
186 | * | |
187 | * @adev: amdgpu_device pointer | |
188 | * | |
189 | * Get the IH ring buffer wptr from either the register | |
190 | * or the writeback memory buffer (VEGA10). Also check for | |
191 | * ring buffer overflow and deal with it. | |
192 | * Returns the value of the wptr. | |
193 | */ | |
194 | static u32 vega10_ih_get_wptr(struct amdgpu_device *adev) | |
195 | { | |
196 | u32 wptr, tmp; | |
197 | ||
198 | if (adev->irq.ih.use_bus_addr) | |
199 | wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); | |
200 | else | |
201 | wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); | |
202 | ||
203 | if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { | |
204 | wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); | |
205 | ||
206 | /* When a ring buffer overflow happen start parsing interrupt | |
207 | * from the last not overwritten vector (wptr + 32). Hopefully | |
208 | * this should allow us to catchup. | |
209 | */ | |
210 | tmp = (wptr + 32) & adev->irq.ih.ptr_mask; | |
211 | dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", | |
212 | wptr, adev->irq.ih.rptr, tmp); | |
213 | adev->irq.ih.rptr = tmp; | |
214 | ||
7c3f2167 | 215 | tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); |
282aae55 | 216 | tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); |
7c3f2167 | 217 | WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp); |
282aae55 KW |
218 | } |
219 | return (wptr & adev->irq.ih.ptr_mask); | |
220 | } | |
221 | ||
00ecd8a2 FK |
222 | /** |
223 | * vega10_ih_prescreen_iv - prescreen an interrupt vector | |
224 | * | |
225 | * @adev: amdgpu_device pointer | |
226 | * | |
227 | * Returns true if the interrupt vector should be further processed. | |
228 | */ | |
229 | static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev) | |
230 | { | |
a2f14820 FK |
231 | u32 ring_index = adev->irq.ih.rptr >> 2; |
232 | u32 dw0, dw3, dw4, dw5; | |
233 | u16 pasid; | |
234 | u64 addr, key; | |
235 | struct amdgpu_vm *vm; | |
236 | int r; | |
237 | ||
238 | dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); | |
239 | dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); | |
240 | dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]); | |
241 | dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]); | |
242 | ||
243 | /* Filter retry page faults, let only the first one pass. If | |
244 | * there are too many outstanding faults, ignore them until | |
245 | * some faults get cleared. | |
246 | */ | |
247 | switch (dw0 & 0xff) { | |
248 | case AMDGPU_IH_CLIENTID_VMC: | |
249 | case AMDGPU_IH_CLIENTID_UTCL2: | |
250 | break; | |
251 | default: | |
252 | /* Not a VM fault */ | |
253 | return true; | |
254 | } | |
255 | ||
a2f14820 FK |
256 | pasid = dw3 & 0xffff; |
257 | /* No PASID, can't identify faulting process */ | |
258 | if (!pasid) | |
259 | return true; | |
260 | ||
c98171cc FK |
261 | /* Not a retry fault, check fault credit */ |
262 | if (!(dw5 & 0x80)) { | |
263 | if (!amdgpu_vm_pasid_fault_credit(adev, pasid)) | |
264 | goto ignore_iv; | |
265 | return true; | |
266 | } | |
267 | ||
a2f14820 FK |
268 | addr = ((u64)(dw5 & 0xf) << 44) | ((u64)dw4 << 12); |
269 | key = AMDGPU_VM_FAULT(pasid, addr); | |
270 | r = amdgpu_ih_add_fault(adev, key); | |
271 | ||
272 | /* Hash table is full or the fault is already being processed, | |
273 | * ignore further page faults | |
274 | */ | |
275 | if (r != 0) | |
276 | goto ignore_iv; | |
277 | ||
278 | /* Track retry faults in per-VM fault FIFO. */ | |
279 | spin_lock(&adev->vm_manager.pasid_lock); | |
280 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
281 | spin_unlock(&adev->vm_manager.pasid_lock); | |
282 | if (WARN_ON_ONCE(!vm)) { | |
283 | /* VM not found, process it normally */ | |
284 | amdgpu_ih_clear_fault(adev, key); | |
285 | return true; | |
286 | } | |
287 | /* No locking required with single writer and single reader */ | |
288 | r = kfifo_put(&vm->faults, key); | |
289 | if (!r) { | |
290 | /* FIFO is full. Ignore it until there is space */ | |
291 | amdgpu_ih_clear_fault(adev, key); | |
292 | goto ignore_iv; | |
293 | } | |
294 | ||
295 | /* It's the first fault for this address, process it normally */ | |
00ecd8a2 | 296 | return true; |
a2f14820 FK |
297 | |
298 | ignore_iv: | |
299 | adev->irq.ih.rptr += 32; | |
300 | return false; | |
00ecd8a2 FK |
301 | } |
302 | ||
282aae55 KW |
303 | /** |
304 | * vega10_ih_decode_iv - decode an interrupt vector | |
305 | * | |
306 | * @adev: amdgpu_device pointer | |
307 | * | |
308 | * Decodes the interrupt vector at the current rptr | |
309 | * position and also advance the position. | |
310 | */ | |
311 | static void vega10_ih_decode_iv(struct amdgpu_device *adev, | |
312 | struct amdgpu_iv_entry *entry) | |
313 | { | |
314 | /* wptr/rptr are in bytes! */ | |
315 | u32 ring_index = adev->irq.ih.rptr >> 2; | |
316 | uint32_t dw[8]; | |
317 | ||
318 | dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); | |
319 | dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); | |
320 | dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); | |
321 | dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); | |
322 | dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]); | |
323 | dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]); | |
324 | dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]); | |
325 | dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]); | |
326 | ||
327 | entry->client_id = dw[0] & 0xff; | |
328 | entry->src_id = (dw[0] >> 8) & 0xff; | |
329 | entry->ring_id = (dw[0] >> 16) & 0xff; | |
c4f46f22 CK |
330 | entry->vmid = (dw[0] >> 24) & 0xf; |
331 | entry->vmid_src = (dw[0] >> 31); | |
282aae55 KW |
332 | entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); |
333 | entry->timestamp_src = dw[2] >> 31; | |
334 | entry->pas_id = dw[3] & 0xffff; | |
335 | entry->pasid_src = dw[3] >> 31; | |
336 | entry->src_data[0] = dw[4]; | |
337 | entry->src_data[1] = dw[5]; | |
338 | entry->src_data[2] = dw[6]; | |
339 | entry->src_data[3] = dw[7]; | |
340 | ||
341 | ||
342 | /* wptr/rptr are in bytes! */ | |
343 | adev->irq.ih.rptr += 32; | |
344 | } | |
345 | ||
346 | /** | |
347 | * vega10_ih_set_rptr - set the IH ring buffer rptr | |
348 | * | |
349 | * @adev: amdgpu_device pointer | |
350 | * | |
351 | * Set the IH ring buffer rptr. | |
352 | */ | |
353 | static void vega10_ih_set_rptr(struct amdgpu_device *adev) | |
354 | { | |
355 | if (adev->irq.ih.use_doorbell) { | |
356 | /* XXX check if swapping is necessary on BE */ | |
357 | if (adev->irq.ih.use_bus_addr) | |
358 | adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; | |
359 | else | |
360 | adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; | |
361 | WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); | |
362 | } else { | |
b2b7e457 | 363 | WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr); |
282aae55 KW |
364 | } |
365 | } | |
366 | ||
367 | static int vega10_ih_early_init(void *handle) | |
368 | { | |
369 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
370 | ||
371 | vega10_ih_set_interrupt_funcs(adev); | |
372 | return 0; | |
373 | } | |
374 | ||
375 | static int vega10_ih_sw_init(void *handle) | |
376 | { | |
377 | int r; | |
378 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
379 | ||
380 | r = amdgpu_ih_ring_init(adev, 256 * 1024, true); | |
381 | if (r) | |
382 | return r; | |
383 | ||
384 | adev->irq.ih.use_doorbell = true; | |
385 | adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1; | |
386 | ||
a2f14820 FK |
387 | adev->irq.ih.faults = kmalloc(sizeof(*adev->irq.ih.faults), GFP_KERNEL); |
388 | if (!adev->irq.ih.faults) | |
389 | return -ENOMEM; | |
390 | INIT_CHASH_TABLE(adev->irq.ih.faults->hash, | |
391 | AMDGPU_PAGEFAULT_HASH_BITS, 8, 0); | |
392 | spin_lock_init(&adev->irq.ih.faults->lock); | |
393 | adev->irq.ih.faults->count = 0; | |
394 | ||
282aae55 KW |
395 | r = amdgpu_irq_init(adev); |
396 | ||
397 | return r; | |
398 | } | |
399 | ||
400 | static int vega10_ih_sw_fini(void *handle) | |
401 | { | |
402 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
403 | ||
404 | amdgpu_irq_fini(adev); | |
405 | amdgpu_ih_ring_fini(adev); | |
406 | ||
a2f14820 FK |
407 | kfree(adev->irq.ih.faults); |
408 | adev->irq.ih.faults = NULL; | |
409 | ||
282aae55 KW |
410 | return 0; |
411 | } | |
412 | ||
413 | static int vega10_ih_hw_init(void *handle) | |
414 | { | |
415 | int r; | |
416 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
417 | ||
418 | r = vega10_ih_irq_init(adev); | |
419 | if (r) | |
420 | return r; | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | static int vega10_ih_hw_fini(void *handle) | |
426 | { | |
427 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
428 | ||
429 | vega10_ih_irq_disable(adev); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | static int vega10_ih_suspend(void *handle) | |
435 | { | |
436 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
437 | ||
438 | return vega10_ih_hw_fini(adev); | |
439 | } | |
440 | ||
441 | static int vega10_ih_resume(void *handle) | |
442 | { | |
443 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
444 | ||
445 | return vega10_ih_hw_init(adev); | |
446 | } | |
447 | ||
448 | static bool vega10_ih_is_idle(void *handle) | |
449 | { | |
450 | /* todo */ | |
451 | return true; | |
452 | } | |
453 | ||
454 | static int vega10_ih_wait_for_idle(void *handle) | |
455 | { | |
456 | /* todo */ | |
457 | return -ETIMEDOUT; | |
458 | } | |
459 | ||
460 | static int vega10_ih_soft_reset(void *handle) | |
461 | { | |
462 | /* todo */ | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int vega10_ih_set_clockgating_state(void *handle, | |
468 | enum amd_clockgating_state state) | |
469 | { | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static int vega10_ih_set_powergating_state(void *handle, | |
474 | enum amd_powergating_state state) | |
475 | { | |
476 | return 0; | |
477 | } | |
478 | ||
479 | const struct amd_ip_funcs vega10_ih_ip_funcs = { | |
480 | .name = "vega10_ih", | |
481 | .early_init = vega10_ih_early_init, | |
482 | .late_init = NULL, | |
483 | .sw_init = vega10_ih_sw_init, | |
484 | .sw_fini = vega10_ih_sw_fini, | |
485 | .hw_init = vega10_ih_hw_init, | |
486 | .hw_fini = vega10_ih_hw_fini, | |
487 | .suspend = vega10_ih_suspend, | |
488 | .resume = vega10_ih_resume, | |
489 | .is_idle = vega10_ih_is_idle, | |
490 | .wait_for_idle = vega10_ih_wait_for_idle, | |
491 | .soft_reset = vega10_ih_soft_reset, | |
492 | .set_clockgating_state = vega10_ih_set_clockgating_state, | |
493 | .set_powergating_state = vega10_ih_set_powergating_state, | |
494 | }; | |
495 | ||
496 | static const struct amdgpu_ih_funcs vega10_ih_funcs = { | |
497 | .get_wptr = vega10_ih_get_wptr, | |
00ecd8a2 | 498 | .prescreen_iv = vega10_ih_prescreen_iv, |
282aae55 KW |
499 | .decode_iv = vega10_ih_decode_iv, |
500 | .set_rptr = vega10_ih_set_rptr | |
501 | }; | |
502 | ||
503 | static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev) | |
504 | { | |
505 | if (adev->irq.ih_funcs == NULL) | |
506 | adev->irq.ih_funcs = &vega10_ih_funcs; | |
507 | } | |
508 | ||
509 | const struct amdgpu_ip_block_version vega10_ih_ip_block = | |
510 | { | |
511 | .type = AMD_IP_BLOCK_TYPE_IH, | |
512 | .major = 4, | |
513 | .minor = 0, | |
514 | .rev = 0, | |
515 | .funcs = &vega10_ih_ip_funcs, | |
516 | }; |