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drm/amdgpu/vcn2.0: remove intermediate variable
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / vcn_v3_0.c
CommitLineData
cf14826c
LL		 1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include "amdgpu.h"
26#include "amdgpu_vcn.h"
27#include "amdgpu_pm.h"
28#include "soc15.h"
29#include "soc15d.h"
30#include "vcn_v2_0.h"
1f61a43f 31#include "mmsch_v3_0.h"
cf14826c
LL		 32
33#include "vcn/vcn_3_0_0_offset.h"
34#include "vcn/vcn_3_0_0_sh_mask.h"
35#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
36
f89f8c6b
AG		 37#include <drm/drm_drv.h>
38
cf14826c
LL		 39#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
40#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
41#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
42#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
43#define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
44#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
45#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
46
47#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
48#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
a971887e 49#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
cf14826c
LL		 50#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
51
a971887e 52#define VCN_INSTANCES_SIENNA_CICHLID 2
52f9535c 53#define DEC_SW_RING_ENABLED FALSE
cf14826c 54
87cc7f9e
CK		 55#define RDECODE_MSG_CREATE 0x00000000
56#define RDECODE_MESSAGE_CREATE 0x00000001
57
1f61a43f
JZ		 58static int amdgpu_ih_clientid_vcns[] = {
59 SOC15_IH_CLIENTID_VCN,
60 SOC15_IH_CLIENTID_VCN1
61};
62
63static int amdgpu_ucode_id_vcns[] = {
a971887e
DV		 64 AMDGPU_UCODE_ID_VCN,
65 AMDGPU_UCODE_ID_VCN1
1f61a43f
JZ		 66};
67
68static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
cf14826c
LL		 69static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
70static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
71static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
72static int vcn_v3_0_set_powergating_state(void *handle,
73 enum amd_powergating_state state);
cfcc06cd
BZ		 74static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
75 int inst_idx, struct dpg_pause_state *new_state);
cf14826c 76
1f61a43f
JZ		 77static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
78static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
cf14826c
LL		 79
80/**
81 * vcn_v3_0_early_init - set function pointers
82 *
83 * @handle: amdgpu_device pointer
84 *
85 * Set ring and irq function pointers
86 */
87static int vcn_v3_0_early_init(void *handle)
88{
89 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
cf14826c 90
1f61a43f 91 if (amdgpu_sriov_vf(adev)) {
564e3dcf 92 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
1f61a43f
JZ		 93 adev->vcn.harvest_config = 0;
94 adev->vcn.num_enc_rings = 1;
cf14826c 95
1f61a43f 96 } else {
f1741615
AD		 97 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
98 AMDGPU_VCN_HARVEST_VCN1))
99 /* both instances are harvested, disable the block */
100 return -ENOENT;
1f61a43f 101
1d789535 102 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33))
f703d4b6
VG		 103 adev->vcn.num_enc_rings = 0;
104 else
105 adev->vcn.num_enc_rings = 2;
1f61a43f 106 }
cf14826c
LL		 107
108 vcn_v3_0_set_dec_ring_funcs(adev);
109 vcn_v3_0_set_enc_ring_funcs(adev);
110 vcn_v3_0_set_irq_funcs(adev);
111
112 return 0;
113}
114
115/**
116 * vcn_v3_0_sw_init - sw init for VCN block
117 *
118 * @handle: amdgpu_device pointer
119 *
120 * Load firmware and sw initialization
121 */
122static int vcn_v3_0_sw_init(void *handle)
123{
124 struct amdgpu_ring *ring;
125 int i, j, r;
1f61a43f 126 int vcn_doorbell_index = 0;
cf14826c
LL		 127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
128
129 r = amdgpu_vcn_sw_init(adev);
130 if (r)
131 return r;
132
c5dd5667 133 amdgpu_vcn_setup_ucode(adev);
cf14826c
LL		 134
135 r = amdgpu_vcn_resume(adev);
136 if (r)
137 return r;
138
25a35065
BZ		 139 /*
140 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines
141 * Formula:
142 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
143 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1)
144 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j
145 */
1f61a43f
JZ		 146 if (amdgpu_sriov_vf(adev)) {
147 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1;
148 /* get DWORD offset */
149 vcn_doorbell_index = vcn_doorbell_index << 1;
150 }
151
cf14826c 152 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
a76087cf 153 volatile struct amdgpu_fw_shared *fw_shared;
c62dfdbb 154
cf14826c
LL		 155 if (adev->vcn.harvest_config & (1 << i))
156 continue;
157
158 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
159 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
160 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
161 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
162 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
163 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
164
165 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
166 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
167 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
168 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
169 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
170 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
171 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
172 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
173 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
174 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
175
176 /* VCN DEC TRAP */
177 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
178 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
179 if (r)
180 return r;
181
c62dfdbb
CK		 182 atomic_set(&adev->vcn.inst[i].sched_score, 0);
183
cf14826c
LL		 184 ring = &adev->vcn.inst[i].ring_dec;
185 ring->use_doorbell = true;
1f61a43f 186 if (amdgpu_sriov_vf(adev)) {
25a35065 187 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);
1f61a43f
JZ		 188 } else {
189 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
190 }
cf14826c
LL		 191 sprintf(ring->name, "vcn_dec_%d", i);
192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
c62dfdbb
CK		 193 AMDGPU_RING_PRIO_DEFAULT,
194 &adev->vcn.inst[i].sched_score);
cf14826c
LL		 195 if (r)
196 return r;
197
198 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
0ad29a4e
SS		 199 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
200
cf14826c
LL		 201 /* VCN ENC TRAP */
202 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
203 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
204 if (r)
205 return r;
206
207 ring = &adev->vcn.inst[i].ring_enc[j];
208 ring->use_doorbell = true;
1f61a43f 209 if (amdgpu_sriov_vf(adev)) {
25a35065 210 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;
1f61a43f
JZ		 211 } else {
212 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
213 }
cf14826c
LL		 214 sprintf(ring->name, "vcn_enc_%d.%d", i, j);
215 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
0ad29a4e 216 hw_prio, &adev->vcn.inst[i].sched_score);
cf14826c
LL		 217 if (r)
218 return r;
219 }
a76087cf
JZ		 220
221 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
e42dd87e 222 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
b2576c3b
SJ		 223 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
224 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
a76087cf 225 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
cf14826c
LL		 226 }
227
1f61a43f
JZ		 228 if (amdgpu_sriov_vf(adev)) {
229 r = amdgpu_virt_alloc_mm_table(adev);
230 if (r)
231 return r;
232 }
cfcc06cd
BZ		 233 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
234 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
235
cf14826c
LL		 236 return 0;
237}
238
239/**
240 * vcn_v3_0_sw_fini - sw fini for VCN block
241 *
242 * @handle: amdgpu_device pointer
243 *
244 * VCN suspend and free up sw allocation
245 */
246static int vcn_v3_0_sw_fini(void *handle)
247{
248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f89f8c6b 249 int i, r, idx;
a76087cf 250
c58a863b 251 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
f89f8c6b
AG		 252 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
253 volatile struct amdgpu_fw_shared *fw_shared;
a76087cf 254
f89f8c6b
AG		 255 if (adev->vcn.harvest_config & (1 << i))
256 continue;
257 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
258 fw_shared->present_flag_0 = 0;
259 fw_shared->sw_ring.is_enabled = false;
260 }
261
262 drm_dev_exit(idx);
a76087cf 263 }
cf14826c 264
1f61a43f
JZ		 265 if (amdgpu_sriov_vf(adev))
266 amdgpu_virt_free_mm_table(adev);
267
cf14826c
LL		 268 r = amdgpu_vcn_suspend(adev);
269 if (r)
270 return r;
271
272 r = amdgpu_vcn_sw_fini(adev);
273
274 return r;
275}
276
277/**
278 * vcn_v3_0_hw_init - start and test VCN block
279 *
280 * @handle: amdgpu_device pointer
281 *
282 * Initialize the hardware, boot up the VCPU and do some testing
283 */
284static int vcn_v3_0_hw_init(void *handle)
285{
286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
287 struct amdgpu_ring *ring;
288 int i, j, r;
289
1f61a43f
JZ		 290 if (amdgpu_sriov_vf(adev)) {
291 r = vcn_v3_0_start_sriov(adev);
292 if (r)
293 goto done;
cf14826c 294
1f61a43f
JZ		 295 /* initialize VCN dec and enc ring buffers */
296 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
297 if (adev->vcn.harvest_config & (1 << i))
298 continue;
299
300 ring = &adev->vcn.inst[i].ring_dec;
564e3dcf
PJZ		 301 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) {
302 ring->sched.ready = false;
303 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
304 } else {
376002f4
BZ		 305 ring->wptr = 0;
306 ring->wptr_old = 0;
564e3dcf 307 vcn_v3_0_dec_ring_set_wptr(ring);
376002f4 308 ring->sched.ready = true;
1f61a43f 309 }
564e3dcf
PJZ		 310
311 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
312 ring = &adev->vcn.inst[i].ring_enc[j];
313 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
314 ring->sched.ready = false;
315 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
316 } else {
317 ring->wptr = 0;
318 ring->wptr_old = 0;
319 vcn_v3_0_enc_ring_set_wptr(ring);
320 ring->sched.ready = true;
321 }
322 }
1f61a43f
JZ		 323 }
324 } else {
325 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
326 if (adev->vcn.harvest_config & (1 << i))
327 continue;
cf14826c 328
1f61a43f 329 ring = &adev->vcn.inst[i].ring_dec;
cf14826c 330
1f61a43f
JZ		 331 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
332 ring->doorbell_index, i);
cf14826c 333
cf14826c
LL		 334 r = amdgpu_ring_test_helper(ring);
335 if (r)
336 goto done;
1f61a43f
JZ		 337
338 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
339 ring = &adev->vcn.inst[i].ring_enc[j];
340 r = amdgpu_ring_test_helper(ring);
341 if (r)
342 goto done;
343 }
cf14826c
LL		 344 }
345 }
346
347done:
348 if (!r)
d00b0fa9
BZ		 349 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
350 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
cf14826c
LL		 351
352 return r;
353}
354
355/**
356 * vcn_v3_0_hw_fini - stop the hardware block
357 *
358 * @handle: amdgpu_device pointer
359 *
360 * Stop the VCN block, mark ring as not ready any more
361 */
362static int vcn_v3_0_hw_fini(void *handle)
363{
364 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
81db370c 365 int i;
cf14826c 366
41884cdd
JZ		 367 cancel_delayed_work_sync(&adev->vcn.idle_work);
368
cf14826c
LL		 369 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
370 if (adev->vcn.harvest_config & (1 << i))
371 continue;
372
c8466cc0
JZ		 373 if (!amdgpu_sriov_vf(adev)) {
374 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
375 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
376 RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
377 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
378 }
379 }
cf14826c
LL		 380 }
381
382 return 0;
383}
384
385/**
386 * vcn_v3_0_suspend - suspend VCN block
387 *
388 * @handle: amdgpu_device pointer
389 *
390 * HW fini and suspend VCN block
391 */
392static int vcn_v3_0_suspend(void *handle)
393{
394 int r;
395 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
396
397 r = vcn_v3_0_hw_fini(adev);
398 if (r)
399 return r;
400
401 r = amdgpu_vcn_suspend(adev);
402
403 return r;
404}
405
406/**
407 * vcn_v3_0_resume - resume VCN block
408 *
409 * @handle: amdgpu_device pointer
410 *
411 * Resume firmware and hw init VCN block
412 */
413static int vcn_v3_0_resume(void *handle)
414{
415 int r;
416 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
417
418 r = amdgpu_vcn_resume(adev);
419 if (r)
420 return r;
421
422 r = vcn_v3_0_hw_init(adev);
423
424 return r;
425}
426
427/**
428 * vcn_v3_0_mc_resume - memory controller programming
429 *
430 * @adev: amdgpu_device pointer
431 * @inst: instance number
432 *
433 * Let the VCN memory controller know it's offsets
434 */
435static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
436{
437 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
438 uint32_t offset;
439
440 /* cache window 0: fw */
441 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
442 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
07d8e891 443 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
cf14826c 444 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
07d8e891 445 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
cf14826c
LL		 446 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
447 offset = 0;
448 } else {
449 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
450 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
451 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
452 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
453 offset = size;
cf14826c
LL		 454 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
455 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
cf14826c
LL		 456 }
457 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
458
459 /* cache window 1: stack */
460 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
461 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
462 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
463 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
464 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
465 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
466
467 /* cache window 2: context */
468 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
469 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
470 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
471 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
472 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
473 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
a76087cf
JZ		 474
475 /* non-cache window */
476 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
477 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
478 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
479 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
480 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
481 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
482 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
cf14826c
LL		 483}
484
99541f39
BZ		 485static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
486{
487 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
488 uint32_t offset;
489
490 /* cache window 0: fw */
491 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
492 if (!indirect) {
4d319ed6 493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 494 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
495 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
4d319ed6 496 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 497 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
498 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
4d319ed6 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 500 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
501 } else {
4d319ed6 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39 503 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
4d319ed6 504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39 505 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
4d319ed6 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 507 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
508 }
509 offset = 0;
510 } else {
4d319ed6 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 512 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
513 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
4d319ed6 514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 515 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
516 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
517 offset = size;
4d319ed6 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 519 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
520 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
521 }
522
523 if (!indirect)
4d319ed6 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 525 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
526 else
4d319ed6 527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 528 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
529
530 /* cache window 1: stack */
531 if (!indirect) {
4d319ed6 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 533 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
534 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
4d319ed6 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 536 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
537 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
4d319ed6 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 539 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
540 } else {
4d319ed6 541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39 542 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
4d319ed6 543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39 544 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
4d319ed6 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 546 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
547 }
4d319ed6 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 549 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
550
551 /* cache window 2: context */
4d319ed6 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 553 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
554 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
4d319ed6 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 556 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
557 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
4d319ed6 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39 559 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
4d319ed6 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39
BZ		 561 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
562
563 /* non-cache window */
4d319ed6 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
a76087cf
JZ		 565 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
566 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
4d319ed6 567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
a76087cf
JZ		 568 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
569 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
4d319ed6 570 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
99541f39 571 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
4d319ed6 572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
a76087cf
JZ		 573 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
574 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
8bf073ca
BN		 575
576 /* VCN global tiling registers */
577 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
578 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
99541f39
BZ		 579}
580
fedac015
LL		 581static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
582{
583 uint32_t data = 0;
fedac015
LL		 584
585 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
586 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
587 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
588 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
589 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
590 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
591 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
592 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
593 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
594 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
595 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
596 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
597 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
598 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
599 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
600
601 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
602 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
450da2ef 603 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
fedac015
LL		 604 } else {
605 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
606 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
607 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
608 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
609 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
610 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
611 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
612 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
613 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
614 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
615 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
616 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
617 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
618 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
619 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
450da2ef 620 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF);
fedac015
LL		 621 }
622
623 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
624 data &= ~0x103;
625 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
626 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
627 UVD_POWER_STATUS__UVD_PG_EN_MASK;
628
629 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
630}
631
632static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
633{
634 uint32_t data;
fedac015
LL		 635
636 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
637 /* Before power off, this indicator has to be turned on */
638 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
639 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
640 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
641 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
642
643 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
644 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
645 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
646 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
647 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
648 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
649 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
650 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
651 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
652 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
653 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
654 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
655 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
656 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
657 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
658
659 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
660 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
661 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
662 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
663 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
664 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
665 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
666 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
667 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
668 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
669 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
670 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
671 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
672 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
450da2ef 673 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
fedac015
LL		 674 }
675}
676
677/**
678 * vcn_v3_0_disable_clock_gating - disable VCN clock gating
679 *
680 * @adev: amdgpu_device pointer
681 * @inst: instance number
682 *
683 * Disable clock gating for VCN block
684 */
685static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
686{
687 uint32_t data;
fedac015
LL		 688
689 /* VCN disable CGC */
690 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
691 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
692 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
693 else
694 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
695 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
696 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
697 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
698
699 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
700 data &= ~(UVD_CGC_GATE__SYS_MASK
701 | UVD_CGC_GATE__UDEC_MASK
702 | UVD_CGC_GATE__MPEG2_MASK
703 | UVD_CGC_GATE__REGS_MASK
704 | UVD_CGC_GATE__RBC_MASK
705 | UVD_CGC_GATE__LMI_MC_MASK
706 | UVD_CGC_GATE__LMI_UMC_MASK
707 | UVD_CGC_GATE__IDCT_MASK
708 | UVD_CGC_GATE__MPRD_MASK
709 | UVD_CGC_GATE__MPC_MASK
710 | UVD_CGC_GATE__LBSI_MASK
711 | UVD_CGC_GATE__LRBBM_MASK
712 | UVD_CGC_GATE__UDEC_RE_MASK
713 | UVD_CGC_GATE__UDEC_CM_MASK
714 | UVD_CGC_GATE__UDEC_IT_MASK
715 | UVD_CGC_GATE__UDEC_DB_MASK
716 | UVD_CGC_GATE__UDEC_MP_MASK
717 | UVD_CGC_GATE__WCB_MASK
718 | UVD_CGC_GATE__VCPU_MASK
719 | UVD_CGC_GATE__MMSCH_MASK);
720
721 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
722
450da2ef 723 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
fedac015
LL		 724
725 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
726 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
727 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
728 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
729 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
730 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
731 | UVD_CGC_CTRL__SYS_MODE_MASK
732 | UVD_CGC_CTRL__UDEC_MODE_MASK
733 | UVD_CGC_CTRL__MPEG2_MODE_MASK
734 | UVD_CGC_CTRL__REGS_MODE_MASK
735 | UVD_CGC_CTRL__RBC_MODE_MASK
736 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
737 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
738 | UVD_CGC_CTRL__IDCT_MODE_MASK
739 | UVD_CGC_CTRL__MPRD_MODE_MASK
740 | UVD_CGC_CTRL__MPC_MODE_MASK
741 | UVD_CGC_CTRL__LBSI_MODE_MASK
742 | UVD_CGC_CTRL__LRBBM_MODE_MASK
743 | UVD_CGC_CTRL__WCB_MODE_MASK
744 | UVD_CGC_CTRL__VCPU_MODE_MASK
745 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
746 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
747
748 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
749 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
750 | UVD_SUVD_CGC_GATE__SIT_MASK
751 | UVD_SUVD_CGC_GATE__SMP_MASK
752 | UVD_SUVD_CGC_GATE__SCM_MASK
753 | UVD_SUVD_CGC_GATE__SDB_MASK
754 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
755 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
756 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
757 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
758 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
759 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
760 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
761 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
762 | UVD_SUVD_CGC_GATE__SCLR_MASK
763 | UVD_SUVD_CGC_GATE__ENT_MASK
764 | UVD_SUVD_CGC_GATE__IME_MASK
765 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
766 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
767 | UVD_SUVD_CGC_GATE__SITE_MASK
768 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
769 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
770 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
771 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
772 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
773 | UVD_SUVD_CGC_GATE__EFC_MASK
774 | UVD_SUVD_CGC_GATE__SAOE_MASK
d9ed8cb5 775 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK
fedac015
LL		 776 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
777 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
d9ed8cb5 778 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK
fedac015
LL		 779 | UVD_SUVD_CGC_GATE__SMPA_MASK);
780 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
781
782 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
783 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
784 | UVD_SUVD_CGC_GATE2__MPBE1_MASK
d9ed8cb5
AD		 785 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
786 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
fedac015
LL		 787 | UVD_SUVD_CGC_GATE2__MPC1_MASK);
788 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
789
790 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
791 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
792 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
793 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
794 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
795 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
796 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
797 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
798 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
799 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
800 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
801 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
802 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
803 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
804 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
d9ed8cb5
AD		 805 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
806 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
fedac015
LL		 807 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
808 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
809 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
810 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
811}
812
063cabd8
BZ		 813static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
814 uint8_t sram_sel, int inst_idx, uint8_t indirect)
815{
816 uint32_t reg_data = 0;
817
818 /* enable sw clock gating control */
819 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
820 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
821 else
822 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
823 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
824 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
825 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
826 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
827 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
828 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
829 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
830 UVD_CGC_CTRL__SYS_MODE_MASK |
831 UVD_CGC_CTRL__UDEC_MODE_MASK |
832 UVD_CGC_CTRL__MPEG2_MODE_MASK |
833 UVD_CGC_CTRL__REGS_MODE_MASK |
834 UVD_CGC_CTRL__RBC_MODE_MASK |
835 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
836 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
837 UVD_CGC_CTRL__IDCT_MODE_MASK |
838 UVD_CGC_CTRL__MPRD_MODE_MASK |
839 UVD_CGC_CTRL__MPC_MODE_MASK |
840 UVD_CGC_CTRL__LBSI_MODE_MASK |
841 UVD_CGC_CTRL__LRBBM_MODE_MASK |
842 UVD_CGC_CTRL__WCB_MODE_MASK |
843 UVD_CGC_CTRL__VCPU_MODE_MASK |
844 UVD_CGC_CTRL__MMSCH_MODE_MASK);
4d319ed6 845 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
063cabd8
BZ		 846 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
847
848 /* turn off clock gating */
4d319ed6 849 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
063cabd8
BZ		 850 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
851
852 /* turn on SUVD clock gating */
4d319ed6 853 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
063cabd8
BZ		 854 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
855
856 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
4d319ed6 857 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
063cabd8
BZ		 858 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
859}
860
fedac015
LL		 861/**
862 * vcn_v3_0_enable_clock_gating - enable VCN clock gating
863 *
864 * @adev: amdgpu_device pointer
865 * @inst: instance number
866 *
867 * Enable clock gating for VCN block
868 */
869static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
870{
871 uint32_t data;
872
873 /* enable VCN CGC */
874 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
875 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
876 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
877 else
878 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
879 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
880 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
881 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
882
883 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
884 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
885 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
886 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
887 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
888 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
889 | UVD_CGC_CTRL__SYS_MODE_MASK
890 | UVD_CGC_CTRL__UDEC_MODE_MASK
891 | UVD_CGC_CTRL__MPEG2_MODE_MASK
892 | UVD_CGC_CTRL__REGS_MODE_MASK
893 | UVD_CGC_CTRL__RBC_MODE_MASK
894 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
895 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
896 | UVD_CGC_CTRL__IDCT_MODE_MASK
897 | UVD_CGC_CTRL__MPRD_MODE_MASK
898 | UVD_CGC_CTRL__MPC_MODE_MASK
899 | UVD_CGC_CTRL__LBSI_MODE_MASK
900 | UVD_CGC_CTRL__LRBBM_MODE_MASK
901 | UVD_CGC_CTRL__WCB_MODE_MASK
902 | UVD_CGC_CTRL__VCPU_MODE_MASK
903 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
904 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
905
906 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
907 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
908 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
909 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
910 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
911 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
912 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
913 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
914 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
915 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
916 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
917 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
918 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
919 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
920 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
d9ed8cb5
AD		 921 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
922 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
fedac015
LL		 923 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
924 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
925 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
926 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
927}
928
ec2d0577
BZ		 929static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
930{
e42dd87e 931 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
ec2d0577
BZ		 932 struct amdgpu_ring *ring;
933 uint32_t rb_bufsz, tmp;
934
935 /* disable register anti-hang mechanism */
936 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
937 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
938 /* enable dynamic power gating mode */
939 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
940 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
941 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
942 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
943
944 if (indirect)
715c84ff 945 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
ec2d0577
BZ		 946
947 /* enable clock gating */
948 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
949
950 /* enable VCPU clock */
951 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
952 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
953 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
4d319ed6 954 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 955 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
956
957 /* disable master interupt */
4d319ed6 958 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 959 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
960
961 /* setup mmUVD_LMI_CTRL */
962 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
963 UVD_LMI_CTRL__REQ_MODE_MASK |
964 UVD_LMI_CTRL__CRC_RESET_MASK |
965 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
966 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
967 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
968 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
969 0x00100000L);
4d319ed6 970 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 971 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
972
4d319ed6 973 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 974 VCN, inst_idx, mmUVD_MPC_CNTL),
975 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
976
4d319ed6 977 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 978 VCN, inst_idx, mmUVD_MPC_SET_MUXA0),
979 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
980 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
981 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
982 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
983
4d319ed6 984 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 985 VCN, inst_idx, mmUVD_MPC_SET_MUXB0),
986 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
987 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
988 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
989 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
990
4d319ed6 991 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 992 VCN, inst_idx, mmUVD_MPC_SET_MUX),
993 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
994 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
995 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
996
997 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
998
4d319ed6 999 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577 1000 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
4d319ed6 1001 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 1002 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
1003
1004 /* enable LMI MC and UMC channels */
4d319ed6 1005 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 1006 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
1007
1008 /* unblock VCPU register access */
4d319ed6 1009 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 1010 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
1011
1012 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1013 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
4d319ed6 1014 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 1015 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1016
1017 /* enable master interrupt */
4d319ed6 1018 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 1019 VCN, inst_idx, mmUVD_MASTINT_EN),
1020 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1021
1022 /* add nop to workaround PSP size check */
4d319ed6 1023 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
ec2d0577
BZ		 1024 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1025
1026 if (indirect)
1027 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1028 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1029 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
1030
1031 ring = &adev->vcn.inst[inst_idx].ring_dec;
1032 /* force RBC into idle state */
1033 rb_bufsz = order_base_2(ring->ring_size);
1034 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1035 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1036 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1037 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1038 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1039 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
1040
7643023e
BZ		 1041 /* Stall DPG before WPTR/RPTR reset */
1042 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1043 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1044 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
e42dd87e 1045 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
7643023e 1046
ec2d0577
BZ		 1047 /* set the write pointer delay */
1048 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
1049
1050 /* set the wb address */
1051 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
1052 (upper_32_bits(ring->gpu_addr) >> 2));
1053
1054 /* programm the RB_BASE for ring buffer */
1055 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1056 lower_32_bits(ring->gpu_addr));
1057 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1058 upper_32_bits(ring->gpu_addr));
1059
1060 /* Initialize the ring buffer's read and write pointers */
1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
1062
1063 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
1064
1065 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1066 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1067 lower_32_bits(ring->wptr));
1068
b2576c3b
SJ		 1069 /* Reset FW shared memory RBC WPTR/RPTR */
1070 fw_shared->rb.rptr = 0;
1071 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1072
1073 /*resetting done, fw can check RB ring */
e42dd87e 1074 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
b2576c3b 1075
7643023e
BZ		 1076 /* Unstall DPG */
1077 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1078 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1079
ec2d0577
BZ		 1080 return 0;
1081}
1082
cf14826c
LL		 1083static int vcn_v3_0_start(struct amdgpu_device *adev)
1084{
e42dd87e 1085 volatile struct amdgpu_fw_shared *fw_shared;
cf14826c
LL		 1086 struct amdgpu_ring *ring;
1087 uint32_t rb_bufsz, tmp;
1088 int i, j, k, r;
1089
1090 if (adev->pm.dpm_enabled)
1091 amdgpu_dpm_enable_uvd(adev, true);
1092
1093 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1094 if (adev->vcn.harvest_config & (1 << i))
1095 continue;
1096
ec2d0577
BZ		 1097 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){
1098 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1099 continue;
1100 }
1101
fedac015
LL		 1102 /* disable VCN power gating */
1103 vcn_v3_0_disable_static_power_gating(adev, i);
1104
cf14826c
LL		 1105 /* set VCN status busy */
1106 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1107 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
1108
fedac015
LL		 1109 /*SW clock gating */
1110 vcn_v3_0_disable_clock_gating(adev, i);
1111
cf14826c
LL		 1112 /* enable VCPU clock */
1113 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1114 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1115
1116 /* disable master interrupt */
1117 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1118 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1119
d6b0185b
LL		 1120 /* enable LMI MC and UMC channels */
1121 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1122 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1123
1124 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1125 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1126 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1127 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1128
cf14826c
LL		 1129 /* setup mmUVD_LMI_CTRL */
1130 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1131 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
1132 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1133 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1134 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1135 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1136
1137 /* setup mmUVD_MPC_CNTL */
1138 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1139 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1140 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1141 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1142
1143 /* setup UVD_MPC_SET_MUXA0 */
1144 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1145 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1146 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1147 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1148 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1149
1150 /* setup UVD_MPC_SET_MUXB0 */
1151 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1152 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1153 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1154 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1155 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1156
1157 /* setup mmUVD_MPC_SET_MUX */
1158 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1159 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1160 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1161 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1162
1163 vcn_v3_0_mc_resume(adev, i);
1164
1165 /* VCN global tiling registers */
1166 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
1167 adev->gfx.config.gb_addr_config);
1168
cf14826c
LL		 1169 /* unblock VCPU register access */
1170 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1171 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1172
1173 /* release VCPU reset to boot */
1174 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1175 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1176
1177 for (j = 0; j < 10; ++j) {
1178 uint32_t status;
1179
1180 for (k = 0; k < 100; ++k) {
1181 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1182 if (status & 2)
1183 break;
1184 mdelay(10);
1185 }
1186 r = 0;
1187 if (status & 2)
1188 break;
1189
1190 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
1191 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1192 UVD_VCPU_CNTL__BLK_RST_MASK,
1193 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1194 mdelay(10);
1195 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1196 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1197
1198 mdelay(10);
1199 r = -1;
1200 }
1201
1202 if (r) {
1203 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
1204 return r;
1205 }
1206
1207 /* enable master interrupt */
1208 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1209 UVD_MASTINT_EN__VCPU_EN_MASK,
1210 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1211
1212 /* clear the busy bit of VCN_STATUS */
1213 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1214 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1215
1216 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1217
1218 ring = &adev->vcn.inst[i].ring_dec;
1219 /* force RBC into idle state */
1220 rb_bufsz = order_base_2(ring->ring_size);
1221 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1222 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1223 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1224 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1225 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1226 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1227
e42dd87e
SJ		 1228 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
1229 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1230
cf14826c
LL		 1231 /* programm the RB_BASE for ring buffer */
1232 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1233 lower_32_bits(ring->gpu_addr));
1234 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1235 upper_32_bits(ring->gpu_addr));
1236
1237 /* Initialize the ring buffer's read and write pointers */
1238 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1239
b2576c3b 1240 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
cf14826c
LL		 1241 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1242 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1243 lower_32_bits(ring->wptr));
b2576c3b 1244 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
e42dd87e
SJ		 1245 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1246
1d789535 1247 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
f703d4b6
VG		 1248 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1249 ring = &adev->vcn.inst[i].ring_enc[0];
1250 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1251 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1252 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1253 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1254 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1255 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1256
1257 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1258 ring = &adev->vcn.inst[i].ring_enc[1];
1259 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1260 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1261 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1262 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1263 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1264 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1265 }
cf14826c
LL		 1266 }
1267
1268 return 0;
1269}
1270
1f61a43f
JZ		 1271static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1272{
1273 int i, j;
1274 struct amdgpu_ring *ring;
1275 uint64_t cache_addr;
1276 uint64_t rb_addr;
1277 uint64_t ctx_addr;
1278 uint32_t param, resp, expected;
1279 uint32_t offset, cache_size;
1280 uint32_t tmp, timeout;
1281 uint32_t id;
1282
1283 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1284 uint32_t *table_loc;
1285 uint32_t table_size;
1286 uint32_t size, size_dw;
1287
1288 struct mmsch_v3_0_cmd_direct_write
1289 direct_wt = { {0} };
1290 struct mmsch_v3_0_cmd_direct_read_modify_write
1291 direct_rd_mod_wt = { {0} };
1f61a43f
JZ		 1292 struct mmsch_v3_0_cmd_end end = { {0} };
1293 struct mmsch_v3_0_init_header header;
1294
1295 direct_wt.cmd_header.command_type =
1296 MMSCH_COMMAND__DIRECT_REG_WRITE;
1297 direct_rd_mod_wt.cmd_header.command_type =
1298 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1f61a43f
JZ		 1299 end.cmd_header.command_type =
1300 MMSCH_COMMAND__END;
1301
1302 header.version = MMSCH_VERSION;
1303 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1304 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1305 header.inst[i].init_status = 0;
1306 header.inst[i].table_offset = 0;
1307 header.inst[i].table_size = 0;
1308 }
1309
1310 table_loc = (uint32_t *)table->cpu_addr;
1311 table_loc += header.total_size;
1312 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1313 if (adev->vcn.harvest_config & (1 << i))
1314 continue;
1315
1316 table_size = 0;
1317
1318 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1319 mmUVD_STATUS),
1320 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1321
1322 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1323
1324 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1325 id = amdgpu_ucode_id_vcns[i];
1326 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1327 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1328 adev->firmware.ucode[id].tmr_mc_addr_lo);
1329 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1330 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1331 adev->firmware.ucode[id].tmr_mc_addr_hi);
1332 offset = 0;
1333 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1334 mmUVD_VCPU_CACHE_OFFSET0),
1335 0);
1336 } else {
1337 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1338 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1339 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1340 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1341 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1342 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1343 offset = cache_size;
1344 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1345 mmUVD_VCPU_CACHE_OFFSET0),
1346 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1347 }
1348
1349 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1350 mmUVD_VCPU_CACHE_SIZE0),
1351 cache_size);
1352
1353 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1354 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1355 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1356 lower_32_bits(cache_addr));
1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1358 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1359 upper_32_bits(cache_addr));
1360 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1361 mmUVD_VCPU_CACHE_OFFSET1),
1362 0);
1363 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1364 mmUVD_VCPU_CACHE_SIZE1),
1365 AMDGPU_VCN_STACK_SIZE);
1366
1367 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1368 AMDGPU_VCN_STACK_SIZE;
1369 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1370 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1371 lower_32_bits(cache_addr));
1372 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1373 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1374 upper_32_bits(cache_addr));
1375 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1376 mmUVD_VCPU_CACHE_OFFSET2),
1377 0);
1378 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1379 mmUVD_VCPU_CACHE_SIZE2),
1380 AMDGPU_VCN_CONTEXT_SIZE);
1381
1382 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1383 ring = &adev->vcn.inst[i].ring_enc[j];
1384 ring->wptr = 0;
1385 rb_addr = ring->gpu_addr;
1386 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1387 mmUVD_RB_BASE_LO),
1388 lower_32_bits(rb_addr));
1389 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1390 mmUVD_RB_BASE_HI),
1391 upper_32_bits(rb_addr));
1392 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1393 mmUVD_RB_SIZE),
1394 ring->ring_size / 4);
1395 }
1396
1397 ring = &adev->vcn.inst[i].ring_dec;
1398 ring->wptr = 0;
1399 rb_addr = ring->gpu_addr;
1400 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1401 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1402 lower_32_bits(rb_addr));
1403 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1404 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1405 upper_32_bits(rb_addr));
1406 /* force RBC into idle state */
1407 tmp = order_base_2(ring->ring_size);
1408 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1409 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1410 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1411 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1412 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1413 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1414 mmUVD_RBC_RB_CNTL),
1415 tmp);
1416
1417 /* add end packet */
1418 MMSCH_V3_0_INSERT_END();
1419
1420 /* refine header */
3617e579 1421 header.inst[i].init_status = 0;
1f61a43f
JZ		 1422 header.inst[i].table_offset = header.total_size;
1423 header.inst[i].table_size = table_size;
1424 header.total_size += table_size;
1425 }
1426
1427 /* Update init table header in memory */
a971887e 1428 size = sizeof(struct mmsch_v3_0_init_header);
1f61a43f
JZ		 1429 table_loc = (uint32_t *)table->cpu_addr;
1430 memcpy((void *)table_loc, &header, size);
1431
1432 /* message MMSCH (in VCN[0]) to initialize this client
1433 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1434 * of memory descriptor location
1435 */
1436 ctx_addr = table->gpu_addr;
1437 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1438 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1439
1440 /* 2, update vmid of descriptor */
1441 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1442 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1443 /* use domain0 for MM scheduler */
1444 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1445 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1446
1447 /* 3, notify mmsch about the size of this descriptor */
1448 size = header.total_size;
1449 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1450
1451 /* 4, set resp to zero */
1452 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1453
1454 /* 5, kick off the initialization and wait until
1455 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1456 */
1457 param = 0x10000001;
1458 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1459 tmp = 0;
1460 timeout = 1000;
1461 resp = 0;
1462 expected = param + 1;
1463 while (resp != expected) {
1464 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1465 if (resp == expected)
1466 break;
1467
1468 udelay(10);
1469 tmp = tmp + 10;
1470 if (tmp >= timeout) {
1471 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1472 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1473 "(expected=0x%08x, readback=0x%08x)\n",
1474 tmp, expected, resp);
1475 return -EBUSY;
1476 }
1477 }
1478
1479 return 0;
1480}
1481
65b17cc8
BZ		 1482static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1483{
65b17cc8
BZ		 1484 uint32_t tmp;
1485
1486 /* Wait for power status to be 1 */
1487 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
450da2ef 1488 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
65b17cc8
BZ		 1489
1490 /* wait for read ptr to be equal to write ptr */
1491 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
450da2ef 1492 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
65b17cc8
BZ		 1493
1494 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
450da2ef 1495 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
65b17cc8
BZ		 1496
1497 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
450da2ef 1498 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
65b17cc8
BZ		 1499
1500 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
450da2ef 1501 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
65b17cc8
BZ		 1502
1503 /* disable dynamic power gating mode */
1504 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1505 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1506
1507 return 0;
1508}
1509
cf14826c
LL		 1510static int vcn_v3_0_stop(struct amdgpu_device *adev)
1511{
1512 uint32_t tmp;
1513 int i, r = 0;
1514
1515 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1516 if (adev->vcn.harvest_config & (1 << i))
1517 continue;
1518
65b17cc8
BZ		 1519 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1520 r = vcn_v3_0_stop_dpg_mode(adev, i);
1521 continue;
1522 }
1523
cf14826c 1524 /* wait for vcn idle */
450da2ef 1525 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
cf14826c
LL		 1526 if (r)
1527 return r;
1528
1529 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1530 UVD_LMI_STATUS__READ_CLEAN_MASK |
1531 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1532 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
450da2ef 1533 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
cf14826c
LL		 1534 if (r)
1535 return r;
1536
1537 /* disable LMI UMC channel */
1538 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1539 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1540 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1541 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1542 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
450da2ef 1543 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
cf14826c
LL		 1544 if (r)
1545 return r;
1546
1547 /* block VCPU register access */
1548 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1549 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1550 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1551
1552 /* reset VCPU */
1553 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1554 UVD_VCPU_CNTL__BLK_RST_MASK,
1555 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1556
1557 /* disable VCPU clock */
1558 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1559 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1560
1561 /* apply soft reset */
1562 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1563 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1564 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1565 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1566 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1567 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1568
1569 /* clear status */
1570 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
fedac015
LL		 1571
1572 /* apply HW clock gating */
1573 vcn_v3_0_enable_clock_gating(adev, i);
1574
1575 /* enable VCN power gating */
1576 vcn_v3_0_enable_static_power_gating(adev, i);
cf14826c
LL		 1577 }
1578
1579 if (adev->pm.dpm_enabled)
1580 amdgpu_dpm_enable_uvd(adev, false);
1581
1582 return 0;
1583}
1584
cfcc06cd
BZ		 1585static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
1586 int inst_idx, struct dpg_pause_state *new_state)
1587{
e42dd87e 1588 volatile struct amdgpu_fw_shared *fw_shared;
cfcc06cd
BZ		 1589 struct amdgpu_ring *ring;
1590 uint32_t reg_data = 0;
1591 int ret_code;
1592
1593 /* pause/unpause if state is changed */
1594 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1595 DRM_DEBUG("dpg pause state changed %d -> %d",
1596 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1597 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1598 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1599
1600 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
450da2ef
JZ		 1601 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1602 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
cfcc06cd
BZ		 1603
1604 if (!ret_code) {
1605 /* pause DPG */
1606 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1607 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1608
1609 /* wait for ACK */
1610 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1611 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
450da2ef 1612 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
cfcc06cd 1613
7643023e
BZ		 1614 /* Stall DPG before WPTR/RPTR reset */
1615 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1616 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1617 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1618
1d789535 1619 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
f703d4b6
VG		 1620 /* Restore */
1621 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
1622 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1623 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1624 ring->wptr = 0;
1625 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1626 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1627 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1628 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1629 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1630 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1631
1632 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1633 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1634 ring->wptr = 0;
1635 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1636 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1637 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1638 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1639 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1640 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1641
1642 /* restore wptr/rptr with pointers saved in FW shared memory*/
1643 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
1644 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);
1645 }
b2576c3b 1646
7643023e
BZ		 1647 /* Unstall DPG */
1648 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1649 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1650
cfcc06cd 1651 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
450da2ef 1652 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
cfcc06cd
BZ		 1653 }
1654 } else {
1655 /* unpause dpg, no need to wait */
1656 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1657 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1658 }
1659 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1660 }
1661
1662 return 0;
1663}
1664
cf14826c
LL		 1665/**
1666 * vcn_v3_0_dec_ring_get_rptr - get read pointer
1667 *
1668 * @ring: amdgpu_ring pointer
1669 *
1670 * Returns the current hardware read pointer
1671 */
1672static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1673{
1674 struct amdgpu_device *adev = ring->adev;
1675
1676 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1677}
1678
1679/**
1680 * vcn_v3_0_dec_ring_get_wptr - get write pointer
1681 *
1682 * @ring: amdgpu_ring pointer
1683 *
1684 * Returns the current hardware write pointer
1685 */
1686static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1687{
1688 struct amdgpu_device *adev = ring->adev;
1689
1690 if (ring->use_doorbell)
1691 return adev->wb.wb[ring->wptr_offs];
1692 else
1693 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1694}
1695
1696/**
1697 * vcn_v3_0_dec_ring_set_wptr - set write pointer
1698 *
1699 * @ring: amdgpu_ring pointer
1700 *
1701 * Commits the write pointer to the hardware
1702 */
1703static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1704{
1705 struct amdgpu_device *adev = ring->adev;
b2576c3b
SJ		 1706 volatile struct amdgpu_fw_shared *fw_shared;
1707
1708 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1709 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */
1710 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr;
1711 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1712 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
1713 lower_32_bits(ring->wptr));
1714 }
cf14826c
LL		 1715
1716 if (ring->use_doorbell) {
1717 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1718 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1719 } else {
1720 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1721 }
1722}
1723
91a7f887 1724static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
52f9535c
JZ		 1725 u64 seq, uint32_t flags)
1726{
1727 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1728
1729 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
1730 amdgpu_ring_write(ring, addr);
1731 amdgpu_ring_write(ring, upper_32_bits(addr));
1732 amdgpu_ring_write(ring, seq);
1733 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
1734}
1735
91a7f887 1736static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
52f9535c
JZ		 1737{
1738 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
1739}
1740
91a7f887 1741static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
52f9535c
JZ		 1742 struct amdgpu_job *job,
1743 struct amdgpu_ib *ib,
1744 uint32_t flags)
1745{
1746 uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
1747
1748 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
1749 amdgpu_ring_write(ring, vmid);
1750 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1751 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1752 amdgpu_ring_write(ring, ib->length_dw);
1753}
1754
91a7f887 1755static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
52f9535c
JZ		 1756 uint32_t val, uint32_t mask)
1757{
1758 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
1759 amdgpu_ring_write(ring, reg << 2);
1760 amdgpu_ring_write(ring, mask);
1761 amdgpu_ring_write(ring, val);
1762}
1763
91a7f887 1764static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
52f9535c
JZ		 1765 uint32_t vmid, uint64_t pd_addr)
1766{
1767 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1768 uint32_t data0, data1, mask;
1769
1770 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1771
1772 /* wait for register write */
1773 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1774 data1 = lower_32_bits(pd_addr);
1775 mask = 0xffffffff;
1776 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
1777}
1778
91a7f887 1779static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
52f9535c
JZ		 1780{
1781 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
1782 amdgpu_ring_write(ring, reg << 2);
1783 amdgpu_ring_write(ring, val);
1784}
1785
1786static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
1787 .type = AMDGPU_RING_TYPE_VCN_DEC,
1788 .align_mask = 0x3f,
1789 .nop = VCN_DEC_SW_CMD_NO_OP,
1790 .vmhub = AMDGPU_MMHUB_0,
1791 .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1792 .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1793 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1794 .emit_frame_size =
1795 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1796 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1797 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */
1798 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */
1799 1, /* vcn_v3_0_dec_sw_ring_insert_end */
1800 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */
1801 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib,
1802 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence,
1803 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush,
1804 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
1805 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib,
1806 .insert_nop = amdgpu_ring_insert_nop,
1807 .insert_end = vcn_v3_0_dec_sw_ring_insert_end,
1808 .pad_ib = amdgpu_ring_generic_pad_ib,
1809 .begin_use = amdgpu_vcn_ring_begin_use,
1810 .end_use = amdgpu_vcn_ring_end_use,
1811 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg,
1812 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait,
1813 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1814};
1815
87cc7f9e
CK		 1816static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p)
1817{
1818 struct drm_gpu_scheduler **scheds;
1819
1820 /* The create msg must be in the first IB submitted */
1821 if (atomic_read(&p->entity->fence_seq))
1822 return -EINVAL;
1823
1824 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
1825 [AMDGPU_RING_PRIO_DEFAULT].sched;
1826 drm_sched_entity_modify_sched(p->entity, scheds, 1);
1827 return 0;
1828}
1829
1830static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
1831{
1832 struct ttm_operation_ctx ctx = { false, false };
1833 struct amdgpu_bo_va_mapping *map;
1834 uint32_t *msg, num_buffers;
1835 struct amdgpu_bo *bo;
1836 uint64_t start, end;
1837 unsigned int i;
1838 void * ptr;
1839 int r;
1840
1841 addr &= AMDGPU_GMC_HOLE_MASK;
1842 r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1843 if (r) {
1844 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
1845 return r;
1846 }
1847
1848 start = map->start * AMDGPU_GPU_PAGE_SIZE;
1849 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1850 if (addr & 0x7) {
1851 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1852 return -EINVAL;
1853 }
1854
1855 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1856 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1857 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1858 if (r) {
1859 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1860 return r;
1861 }
1862
1863 r = amdgpu_bo_kmap(bo, &ptr);
1864 if (r) {
1865 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1866 return r;
1867 }
1868
1869 msg = ptr + addr - start;
1870
1871 /* Check length */
1872 if (msg[1] > end - addr) {
1873 r = -EINVAL;
1874 goto out;
1875 }
1876
1877 if (msg[3] != RDECODE_MSG_CREATE)
1878 goto out;
1879
1880 num_buffers = msg[2];
1881 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1882 uint32_t offset, size, *create;
1883
1884 if (msg[0] != RDECODE_MESSAGE_CREATE)
1885 continue;
1886
1887 offset = msg[1];
1888 size = msg[2];
1889
1890 if (offset + size > end) {
1891 r = -EINVAL;
1892 goto out;
1893 }
1894
1895 create = ptr + addr + offset - start;
1896
1897 /* H246, HEVC and VP9 can run on any instance */
1898 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1899 continue;
1900
1901 r = vcn_v3_0_limit_sched(p);
1902 if (r)
1903 goto out;
1904 }
1905
1906out:
1907 amdgpu_bo_kunmap(bo);
1908 return r;
1909}
1910
1911static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1912 uint32_t ib_idx)
1913{
1914 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1915 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1916 uint32_t msg_lo = 0, msg_hi = 0;
1917 unsigned i;
1918 int r;
1919
1920 /* The first instance can decode anything */
1921 if (!ring->me)
1922 return 0;
1923
1924 for (i = 0; i < ib->length_dw; i += 2) {
1925 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1926 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1);
1927
1928 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
1929 msg_lo = val;
1930 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
1931 msg_hi = val;
1932 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
1933 val == 0) {
1934 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo);
1935 if (r)
1936 return r;
1937 }
1938 }
1939 return 0;
1940}
1941
cf14826c
LL		 1942static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
1943 .type = AMDGPU_RING_TYPE_VCN_DEC,
1944 .align_mask = 0xf,
1945 .vmhub = AMDGPU_MMHUB_0,
1946 .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1947 .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1948 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
87cc7f9e 1949 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place,
cf14826c
LL		 1950 .emit_frame_size =
1951 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1952 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1953 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1954 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1955 6,
1956 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1957 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1958 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1959 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
c5079f35 1960 .test_ring = vcn_v2_0_dec_ring_test_ring,
cf14826c
LL		 1961 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1962 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1963 .insert_start = vcn_v2_0_dec_ring_insert_start,
1964 .insert_end = vcn_v2_0_dec_ring_insert_end,
1965 .pad_ib = amdgpu_ring_generic_pad_ib,
1966 .begin_use = amdgpu_vcn_ring_begin_use,
1967 .end_use = amdgpu_vcn_ring_end_use,
1968 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1969 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1970 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1971};
1972
1973/**
1974 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer
1975 *
1976 * @ring: amdgpu_ring pointer
1977 *
1978 * Returns the current hardware enc read pointer
1979 */
1980static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1981{
1982 struct amdgpu_device *adev = ring->adev;
1983
1984 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1985 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1986 else
1987 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1988}
1989
1990/**
1991 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer
1992 *
1993 * @ring: amdgpu_ring pointer
1994 *
1995 * Returns the current hardware enc write pointer
1996 */
1997static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1998{
1999 struct amdgpu_device *adev = ring->adev;
2000
2001 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2002 if (ring->use_doorbell)
2003 return adev->wb.wb[ring->wptr_offs];
2004 else
2005 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
2006 } else {
2007 if (ring->use_doorbell)
2008 return adev->wb.wb[ring->wptr_offs];
2009 else
2010 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
2011 }
2012}
2013
2014/**
2015 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer
2016 *
2017 * @ring: amdgpu_ring pointer
2018 *
2019 * Commits the enc write pointer to the hardware
2020 */
2021static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
2022{
2023 struct amdgpu_device *adev = ring->adev;
2024
2025 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2026 if (ring->use_doorbell) {
2027 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2028 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2029 } else {
2030 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
2031 }
2032 } else {
2033 if (ring->use_doorbell) {
2034 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2035 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2036 } else {
2037 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
2038 }
2039 }
2040}
2041
2042static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
2043 .type = AMDGPU_RING_TYPE_VCN_ENC,
2044 .align_mask = 0x3f,
2045 .nop = VCN_ENC_CMD_NO_OP,
2046 .vmhub = AMDGPU_MMHUB_0,
2047 .get_rptr = vcn_v3_0_enc_ring_get_rptr,
2048 .get_wptr = vcn_v3_0_enc_ring_get_wptr,
2049 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
2050 .emit_frame_size =
2051 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2052 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2053 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2054 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2055 1, /* vcn_v2_0_enc_ring_insert_end */
2056 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2057 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2058 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2059 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2060 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2061 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2062 .insert_nop = amdgpu_ring_insert_nop,
2063 .insert_end = vcn_v2_0_enc_ring_insert_end,
2064 .pad_ib = amdgpu_ring_generic_pad_ib,
2065 .begin_use = amdgpu_vcn_ring_begin_use,
2066 .end_use = amdgpu_vcn_ring_end_use,
2067 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2068 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2069 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2070};
2071
2072static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2073{
2074 int i;
2075
2076 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2077 if (adev->vcn.harvest_config & (1 << i))
2078 continue;
2079
52f9535c
JZ		 2080 if (!DEC_SW_RING_ENABLED)
2081 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
2082 else
2083 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
cf14826c 2084 adev->vcn.inst[i].ring_dec.me = i;
52f9535c
JZ		 2085 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i,
2086 DEC_SW_RING_ENABLED?"(Software Ring)":"");
cf14826c
LL		 2087 }
2088}
2089
2090static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2091{
2092 int i, j;
2093
2094 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2095 if (adev->vcn.harvest_config & (1 << i))
2096 continue;
2097
2098 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
2099 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
2100 adev->vcn.inst[i].ring_enc[j].me = i;
2101 }
f703d4b6
VG		 2102 if (adev->vcn.num_enc_rings > 0)
2103 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
cf14826c
LL		 2104 }
2105}
2106
2107static bool vcn_v3_0_is_idle(void *handle)
2108{
2109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2110 int i, ret = 1;
2111
2112 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2113 if (adev->vcn.harvest_config & (1 << i))
2114 continue;
2115
2116 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
2117 }
2118
2119 return ret;
2120}
2121
2122static int vcn_v3_0_wait_for_idle(void *handle)
2123{
2124 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2125 int i, ret = 0;
2126
2127 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2128 if (adev->vcn.harvest_config & (1 << i))
2129 continue;
2130
450da2ef
JZ		 2131 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
2132 UVD_STATUS__IDLE);
cf14826c
LL		 2133 if (ret)
2134 return ret;
2135 }
2136
2137 return ret;
2138}
2139
2140static int vcn_v3_0_set_clockgating_state(void *handle,
2141 enum amd_clockgating_state state)
2142{
fedac015
LL		 2143 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2144 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
2145 int i;
2146
2147 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2148 if (adev->vcn.harvest_config & (1 << i))
2149 continue;
2150
2151 if (enable) {
df3183b3 2152 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
fedac015
LL		 2153 return -EBUSY;
2154 vcn_v3_0_enable_clock_gating(adev, i);
2155 } else {
2156 vcn_v3_0_disable_clock_gating(adev, i);
2157 }
2158 }
2159
cf14826c
LL		 2160 return 0;
2161}
2162
2163static int vcn_v3_0_set_powergating_state(void *handle,
2164 enum amd_powergating_state state)
2165{
2166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2167 int ret;
2168
c8466cc0
JZ		 2169 /* for SRIOV, guest should not control VCN Power-gating
2170 * MMSCH FW should control Power-gating and clock-gating
2171 * guest should avoid touching CGC and PG
2172 */
2173 if (amdgpu_sriov_vf(adev)) {
2174 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2175 return 0;
2176 }
2177
cf14826c
LL		 2178 if(state == adev->vcn.cur_state)
2179 return 0;
2180
2181 if (state == AMD_PG_STATE_GATE)
2182 ret = vcn_v3_0_stop(adev);
2183 else
2184 ret = vcn_v3_0_start(adev);
2185
2186 if(!ret)
2187 adev->vcn.cur_state = state;
2188
2189 return ret;
2190}
2191
2192static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev,
2193 struct amdgpu_irq_src *source,
2194 unsigned type,
2195 enum amdgpu_interrupt_state state)
2196{
2197 return 0;
2198}
2199
2200static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev,
2201 struct amdgpu_irq_src *source,
2202 struct amdgpu_iv_entry *entry)
2203{
2204 uint32_t ip_instance;
2205
2206 switch (entry->client_id) {
2207 case SOC15_IH_CLIENTID_VCN:
2208 ip_instance = 0;
2209 break;
2210 case SOC15_IH_CLIENTID_VCN1:
2211 ip_instance = 1;
2212 break;
2213 default:
2214 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2215 return 0;
2216 }
2217
2218 DRM_DEBUG("IH: VCN TRAP\n");
2219
2220 switch (entry->src_id) {
2221 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
2222 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
2223 break;
2224 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2225 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2226 break;
2227 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
2228 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
2229 break;
2230 default:
2231 DRM_ERROR("Unhandled interrupt: %d %d\n",
2232 entry->src_id, entry->src_data[0]);
2233 break;
2234 }
2235
2236 return 0;
2237}
2238
2239static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
2240 .set = vcn_v3_0_set_interrupt_state,
2241 .process = vcn_v3_0_process_interrupt,
2242};
2243
2244static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
2245{
2246 int i;
2247
2248 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2249 if (adev->vcn.harvest_config & (1 << i))
2250 continue;
2251
2252 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2253 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
2254 }
2255}
2256
2257static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
2258 .name = "vcn_v3_0",
2259 .early_init = vcn_v3_0_early_init,
2260 .late_init = NULL,
2261 .sw_init = vcn_v3_0_sw_init,
2262 .sw_fini = vcn_v3_0_sw_fini,
2263 .hw_init = vcn_v3_0_hw_init,
2264 .hw_fini = vcn_v3_0_hw_fini,
2265 .suspend = vcn_v3_0_suspend,
2266 .resume = vcn_v3_0_resume,
2267 .is_idle = vcn_v3_0_is_idle,
2268 .wait_for_idle = vcn_v3_0_wait_for_idle,
2269 .check_soft_reset = NULL,
2270 .pre_soft_reset = NULL,
2271 .soft_reset = NULL,
2272 .post_soft_reset = NULL,
2273 .set_clockgating_state = vcn_v3_0_set_clockgating_state,
2274 .set_powergating_state = vcn_v3_0_set_powergating_state,
2275};
2276
2277const struct amdgpu_ip_block_version vcn_v3_0_ip_block =
2278{
2279 .type = AMD_IP_BLOCK_TYPE_VCN,
2280 .major = 3,
2281 .minor = 0,
2282 .rev = 0,
2283 .funcs = &vcn_v3_0_ip_funcs,
2284};
Linux 6.x block layer and io_uring tree(s)