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drm/amdgpu: sync ring type and drm hw_ip type
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / vcn_v2_0.c
CommitLineData
1b61de45
LL		 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
9a2ffeb5 25
1b61de45
LL		 26#include "amdgpu.h"
27#include "amdgpu_vcn.h"
28#include "soc15.h"
29#include "soc15d.h"
c113ba15 30#include "amdgpu_pm.h"
dc8ae677 31#include "amdgpu_psp.h"
dd26858a 32#include "mmsch_v2_0.h"
1b61de45
LL		 33
34#include "vcn/vcn_2_0_0_offset.h"
35#include "vcn/vcn_2_0_0_sh_mask.h"
36#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
37
38#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
39#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
40#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
41#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
42#define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
43#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
44#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
45
46#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
47#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
48#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
49#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
1b61de45 50
1b61de45
LL		 51static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
52static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
1b61de45
LL		 53static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
54static int vcn_v2_0_set_powergating_state(void *handle,
55 enum amd_powergating_state state);
7282da0b 56static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
597e6ac3 57 int inst_idx, struct dpg_pause_state *new_state);
dd26858a 58static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
1b61de45
LL		 59/**
60 * vcn_v2_0_early_init - set function pointers
61 *
62 * @handle: amdgpu_device pointer
63 *
64 * Set ring and irq function pointers
65 */
66static int vcn_v2_0_early_init(void *handle)
67{
68 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
69
c01b6a1d 70 adev->vcn.num_vcn_inst = 1;
dd26858a
ML		 71 if (amdgpu_sriov_vf(adev))
72 adev->vcn.num_enc_rings = 1;
73 else
74 adev->vcn.num_enc_rings = 2;
1b61de45
LL		 75
76 vcn_v2_0_set_dec_ring_funcs(adev);
77 vcn_v2_0_set_enc_ring_funcs(adev);
1b61de45
LL		 78 vcn_v2_0_set_irq_funcs(adev);
79
80 return 0;
81}
82
83/**
84 * vcn_v2_0_sw_init - sw init for VCN block
85 *
86 * @handle: amdgpu_device pointer
87 *
88 * Load firmware and sw initialization
89 */
90static int vcn_v2_0_sw_init(void *handle)
91{
92 struct amdgpu_ring *ring;
93 int i, r;
94 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93521410 95 volatile struct amdgpu_fw_shared *fw_shared;
1b61de45
LL		 96
97 /* VCN DEC TRAP */
98 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
99 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
c01b6a1d 100 &adev->vcn.inst->irq);
1b61de45
LL		 101 if (r)
102 return r;
103
104 /* VCN ENC TRAP */
105 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
106 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
107 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
c01b6a1d 108 &adev->vcn.inst->irq);
1b61de45
LL		 109 if (r)
110 return r;
111 }
112
1b61de45
LL		 113 r = amdgpu_vcn_sw_init(adev);
114 if (r)
115 return r;
116
117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
118 const struct common_firmware_header *hdr;
119 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
120 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
121 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
122 adev->firmware.fw_size +=
123 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
124 DRM_INFO("PSP loading VCN firmware\n");
125 }
126
127 r = amdgpu_vcn_resume(adev);
128 if (r)
129 return r;
130
c01b6a1d 131 ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 132
133 ring->use_doorbell = true;
134 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
135
136 sprintf(ring->name, "vcn_dec");
c01b6a1d 137 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
1b61de45
LL		 138 if (r)
139 return r;
140
22a8f442
LL		 141 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
142 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
143 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
144 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
145 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
146 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
147
1b61de45 148 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
c01b6a1d 149 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
1b61de45 150 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
c01b6a1d 151 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
1b61de45 152 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
c01b6a1d 153 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
1b61de45 154 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
c01b6a1d 155 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
1b61de45 156 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
c01b6a1d 157 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
1b61de45
LL		 158
159 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
c01b6a1d 160 ring = &adev->vcn.inst->ring_enc[i];
1b61de45 161 ring->use_doorbell = true;
dd26858a
ML		 162 if (!amdgpu_sriov_vf(adev))
163 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
164 else
165 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
1b61de45 166 sprintf(ring->name, "vcn_enc%d", i);
c01b6a1d 167 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
1b61de45
LL		 168 if (r)
169 return r;
170 }
171
7282da0b
LL		 172 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
173
dd26858a
ML		 174 r = amdgpu_virt_alloc_mm_table(adev);
175 if (r)
176 return r;
177
93521410
JZ		 178 fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
179 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
1b61de45
LL		 180 return 0;
181}
182
183/**
184 * vcn_v2_0_sw_fini - sw fini for VCN block
185 *
186 * @handle: amdgpu_device pointer
187 *
188 * VCN suspend and free up sw allocation
189 */
190static int vcn_v2_0_sw_fini(void *handle)
191{
192 int r;
193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93521410
JZ		 194 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
195
196 fw_shared->present_flag_0 = 0;
1b61de45 197
dd26858a
ML		 198 amdgpu_virt_free_mm_table(adev);
199
1b61de45
LL		 200 r = amdgpu_vcn_suspend(adev);
201 if (r)
202 return r;
203
204 r = amdgpu_vcn_sw_fini(adev);
205
206 return r;
207}
208
209/**
210 * vcn_v2_0_hw_init - start and test VCN block
211 *
212 * @handle: amdgpu_device pointer
213 *
214 * Initialize the hardware, boot up the VCPU and do some testing
215 */
216static int vcn_v2_0_hw_init(void *handle)
217{
218 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c01b6a1d 219 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 220 int i, r;
221
bebc0762 222 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
989b6a05 223 ring->doorbell_index, 0);
1b61de45 224
dd26858a
ML		 225 if (amdgpu_sriov_vf(adev))
226 vcn_v2_0_start_sriov(adev);
227
fd287c8c
LL		 228 r = amdgpu_ring_test_helper(ring);
229 if (r)
1b61de45 230 goto done;
1b61de45 231
ad31da43
ED		 232 //Disable vcn decode for sriov
233 if (amdgpu_sriov_vf(adev))
234 ring->sched.ready = false;
235
1b61de45 236 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
c01b6a1d 237 ring = &adev->vcn.inst->ring_enc[i];
fd287c8c
LL		 238 r = amdgpu_ring_test_helper(ring);
239 if (r)
1b61de45 240 goto done;
1b61de45
LL		 241 }
242
1b61de45
LL		 243done:
244 if (!r)
bf4865b5
LL		 245 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
246 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
1b61de45
LL		 247
248 return r;
249}
250
251/**
252 * vcn_v2_0_hw_fini - stop the hardware block
253 *
254 * @handle: amdgpu_device pointer
255 *
256 * Stop the VCN block, mark ring as not ready any more
257 */
258static int vcn_v2_0_hw_fini(void *handle)
259{
260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1b61de45 261
bf4865b5
LL		 262 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
263 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
264 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
1b61de45
LL		 265 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
266
1b61de45
LL		 267 return 0;
268}
269
270/**
271 * vcn_v2_0_suspend - suspend VCN block
272 *
273 * @handle: amdgpu_device pointer
274 *
275 * HW fini and suspend VCN block
276 */
277static int vcn_v2_0_suspend(void *handle)
278{
279 int r;
280 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
281
282 r = vcn_v2_0_hw_fini(adev);
283 if (r)
284 return r;
285
286 r = amdgpu_vcn_suspend(adev);
287
288 return r;
289}
290
291/**
292 * vcn_v2_0_resume - resume VCN block
293 *
294 * @handle: amdgpu_device pointer
295 *
296 * Resume firmware and hw init VCN block
297 */
298static int vcn_v2_0_resume(void *handle)
299{
300 int r;
301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
302
303 r = amdgpu_vcn_resume(adev);
304 if (r)
305 return r;
306
307 r = vcn_v2_0_hw_init(adev);
308
309 return r;
310}
311
312/**
313 * vcn_v2_0_mc_resume - memory controller programming
314 *
315 * @adev: amdgpu_device pointer
316 *
317 * Let the VCN memory controller know it's offsets
318 */
319static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
320{
321 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
322 uint32_t offset;
323
cc9f2fba
ML		 324 if (amdgpu_sriov_vf(adev))
325 return;
326
1b61de45
LL		 327 /* cache window 0: fw */
328 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
329 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
330 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
331 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
332 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
333 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
334 offset = 0;
335 } else {
336 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
c01b6a1d 337 lower_32_bits(adev->vcn.inst->gpu_addr));
1b61de45 338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
c01b6a1d 339 upper_32_bits(adev->vcn.inst->gpu_addr));
1b61de45 340 offset = size;
1b61de45
LL		 341 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
342 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1b61de45
LL		 343 }
344
345 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
346
347 /* cache window 1: stack */
348 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
c01b6a1d 349 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1b61de45 350 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
c01b6a1d 351 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1b61de45
LL		 352 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
353 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
354
355 /* cache window 2: context */
356 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
c01b6a1d 357 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
1b61de45 358 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
c01b6a1d 359 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
1b61de45
LL		 360 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
361 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
362
93521410
JZ		 363 /* non-cache window */
364 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
365 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
366 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
367 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
368 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
369 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
370 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
371
1b61de45 372 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1b61de45
LL		 373}
374
bf4865b5
LL		 375static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
376{
377 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
378 uint32_t offset;
379
380 /* cache window 0: fw */
381 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
dc8ae677 382 if (!indirect) {
5db86843 383 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 384 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
385 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
5db86843 386 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 387 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
388 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
5db86843 389 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 390 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
391 } else {
5db86843 392 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 393 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
5db86843 394 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 395 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
5db86843 396 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 397 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
398 }
bf4865b5
LL		 399 offset = 0;
400 } else {
5db86843 401 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 402 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
c01b6a1d 403 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
5db86843 404 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 405 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
c01b6a1d 406 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
bf4865b5 407 offset = size;
5db86843 408 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 409 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
410 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
411 }
412
dc8ae677 413 if (!indirect)
5db86843 414 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 415 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
416 else
5db86843 417 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 418 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
bf4865b5
LL		 419
420 /* cache window 1: stack */
dc8ae677 421 if (!indirect) {
5db86843 422 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 423 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
c01b6a1d 424 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
5db86843 425 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 426 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
c01b6a1d 427 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
5db86843 428 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 429 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
430 } else {
5db86843 431 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 432 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
5db86843 433 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677 434 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
5db86843 435 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
dc8ae677
LL		 436 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
437 }
5db86843 438 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 439 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
440
441 /* cache window 2: context */
5db86843 442 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 443 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
c01b6a1d 444 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5db86843 445 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 446 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
c01b6a1d 447 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
5db86843 448 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 449 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
5db86843 450 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 451 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
452
453 /* non-cache window */
5db86843 454 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
93521410
JZ		 455 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
456 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
5db86843 457 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
93521410
JZ		 458 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
459 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
5db86843 460 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 461 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
5db86843 462 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
93521410
JZ		 463 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
464 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
bf4865b5
LL		 465
466 /* VCN global tiling registers */
5db86843 467 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 468 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
469}
470
1b61de45
LL		 471/**
472 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
473 *
474 * @adev: amdgpu_device pointer
475 * @sw: enable SW clock gating
476 *
477 * Disable clock gating for VCN block
478 */
479static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
480{
481 uint32_t data;
482
cc9f2fba
ML		 483 if (amdgpu_sriov_vf(adev))
484 return;
485
1b61de45
LL		 486 /* UVD disable CGC */
487 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
488 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
489 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
490 else
491 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
492 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
493 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
494 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
495
496 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
497 data &= ~(UVD_CGC_GATE__SYS_MASK
498 | UVD_CGC_GATE__UDEC_MASK
499 | UVD_CGC_GATE__MPEG2_MASK
500 | UVD_CGC_GATE__REGS_MASK
501 | UVD_CGC_GATE__RBC_MASK
502 | UVD_CGC_GATE__LMI_MC_MASK
503 | UVD_CGC_GATE__LMI_UMC_MASK
504 | UVD_CGC_GATE__IDCT_MASK
505 | UVD_CGC_GATE__MPRD_MASK
506 | UVD_CGC_GATE__MPC_MASK
507 | UVD_CGC_GATE__LBSI_MASK
508 | UVD_CGC_GATE__LRBBM_MASK
509 | UVD_CGC_GATE__UDEC_RE_MASK
510 | UVD_CGC_GATE__UDEC_CM_MASK
511 | UVD_CGC_GATE__UDEC_IT_MASK
512 | UVD_CGC_GATE__UDEC_DB_MASK
513 | UVD_CGC_GATE__UDEC_MP_MASK
514 | UVD_CGC_GATE__WCB_MASK
515 | UVD_CGC_GATE__VCPU_MASK
516 | UVD_CGC_GATE__SCPU_MASK);
517 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
518
519 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
520 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
521 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
522 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
523 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
524 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
525 | UVD_CGC_CTRL__SYS_MODE_MASK
526 | UVD_CGC_CTRL__UDEC_MODE_MASK
527 | UVD_CGC_CTRL__MPEG2_MODE_MASK
528 | UVD_CGC_CTRL__REGS_MODE_MASK
529 | UVD_CGC_CTRL__RBC_MODE_MASK
530 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
531 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
532 | UVD_CGC_CTRL__IDCT_MODE_MASK
533 | UVD_CGC_CTRL__MPRD_MODE_MASK
534 | UVD_CGC_CTRL__MPC_MODE_MASK
535 | UVD_CGC_CTRL__LBSI_MODE_MASK
536 | UVD_CGC_CTRL__LRBBM_MODE_MASK
537 | UVD_CGC_CTRL__WCB_MODE_MASK
538 | UVD_CGC_CTRL__VCPU_MODE_MASK
539 | UVD_CGC_CTRL__SCPU_MODE_MASK);
540 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
541
542 /* turn on */
543 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
544 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
545 | UVD_SUVD_CGC_GATE__SIT_MASK
546 | UVD_SUVD_CGC_GATE__SMP_MASK
547 | UVD_SUVD_CGC_GATE__SCM_MASK
548 | UVD_SUVD_CGC_GATE__SDB_MASK
549 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
550 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
551 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
552 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
553 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
554 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
555 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
556 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
557 | UVD_SUVD_CGC_GATE__SCLR_MASK
558 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
559 | UVD_SUVD_CGC_GATE__ENT_MASK
560 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
561 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
562 | UVD_SUVD_CGC_GATE__SITE_MASK
563 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
564 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
565 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
566 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
567 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
568 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
569
570 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
571 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
572 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
573 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
574 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
575 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
576 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
577 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
578 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
579 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
580 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
581 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
582}
583
bf4865b5
LL		 584static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
585 uint8_t sram_sel, uint8_t indirect)
586{
587 uint32_t reg_data = 0;
588
589 /* enable sw clock gating control */
590 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
591 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
592 else
593 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
594 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
595 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
596 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
597 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
598 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
599 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
600 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
601 UVD_CGC_CTRL__SYS_MODE_MASK |
602 UVD_CGC_CTRL__UDEC_MODE_MASK |
603 UVD_CGC_CTRL__MPEG2_MODE_MASK |
604 UVD_CGC_CTRL__REGS_MODE_MASK |
605 UVD_CGC_CTRL__RBC_MODE_MASK |
606 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
607 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
608 UVD_CGC_CTRL__IDCT_MODE_MASK |
609 UVD_CGC_CTRL__MPRD_MODE_MASK |
610 UVD_CGC_CTRL__MPC_MODE_MASK |
611 UVD_CGC_CTRL__LBSI_MODE_MASK |
612 UVD_CGC_CTRL__LRBBM_MODE_MASK |
613 UVD_CGC_CTRL__WCB_MODE_MASK |
614 UVD_CGC_CTRL__VCPU_MODE_MASK |
615 UVD_CGC_CTRL__SCPU_MODE_MASK);
5db86843 616 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 617 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
618
619 /* turn off clock gating */
5db86843 620 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 621 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
622
623 /* turn on SUVD clock gating */
5db86843 624 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 625 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
626
627 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
5db86843 628 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 629 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
630}
631
1b61de45
LL		 632/**
633 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
634 *
635 * @adev: amdgpu_device pointer
636 * @sw: enable SW clock gating
637 *
638 * Enable clock gating for VCN block
639 */
640static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
641{
642 uint32_t data = 0;
643
cc9f2fba
ML		 644 if (amdgpu_sriov_vf(adev))
645 return;
646
1b61de45
LL		 647 /* enable UVD CGC */
648 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
649 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
650 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
651 else
652 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
653 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
654 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
655 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
656
657 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
658 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
659 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
660 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
661 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
662 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
663 | UVD_CGC_CTRL__SYS_MODE_MASK
664 | UVD_CGC_CTRL__UDEC_MODE_MASK
665 | UVD_CGC_CTRL__MPEG2_MODE_MASK
666 | UVD_CGC_CTRL__REGS_MODE_MASK
667 | UVD_CGC_CTRL__RBC_MODE_MASK
668 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
669 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
670 | UVD_CGC_CTRL__IDCT_MODE_MASK
671 | UVD_CGC_CTRL__MPRD_MODE_MASK
672 | UVD_CGC_CTRL__MPC_MODE_MASK
673 | UVD_CGC_CTRL__LBSI_MODE_MASK
674 | UVD_CGC_CTRL__LRBBM_MODE_MASK
675 | UVD_CGC_CTRL__WCB_MODE_MASK
676 | UVD_CGC_CTRL__VCPU_MODE_MASK
677 | UVD_CGC_CTRL__SCPU_MODE_MASK);
678 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
679
680 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
681 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
682 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
683 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
684 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
685 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
686 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
687 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
688 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
689 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
690 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
691 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
692}
693
694static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
695{
696 uint32_t data = 0;
697 int ret;
698
cc9f2fba
ML		 699 if (amdgpu_sriov_vf(adev))
700 return;
701
1b61de45
LL		 702 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
703 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
704 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
705 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
706 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
707 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
708 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
709 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
710 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
711 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 712 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45
LL		 713
714 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
715 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
863dd269 716 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
1b61de45
LL		 717 } else {
718 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
719 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
720 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
721 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
722 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
723 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
724 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
725 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
726 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 727 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45 728 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
863dd269 729 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret);
1b61de45
LL		 730 }
731
732 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
733 * UVDU_PWR_STATUS are 0 (power on) */
734
735 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
736 data &= ~0x103;
737 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
738 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
739 UVD_POWER_STATUS__UVD_PG_EN_MASK;
740
741 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
742}
743
744static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
745{
746 uint32_t data = 0;
747 int ret;
748
cc9f2fba
ML		 749 if (amdgpu_sriov_vf(adev))
750 return;
751
1b61de45
LL		 752 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
753 /* Before power off, this indicator has to be turned on */
754 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
755 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
756 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
757 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
758
759
760 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
761 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
762 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
763 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
764 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
765 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
766 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
767 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
768 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
863dd269 769 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
1b61de45
LL		 770
771 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
772
773 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
774 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
775 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
776 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
777 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
778 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
779 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
780 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
781 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
863dd269
LL		 782 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
783 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
1b61de45
LL		 784 }
785}
786
bf4865b5
LL		 787static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
788{
93521410 789 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
c01b6a1d 790 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
bf4865b5
LL		 791 uint32_t rb_bufsz, tmp;
792
793 vcn_v2_0_enable_static_power_gating(adev);
794
795 /* enable dynamic power gating mode */
796 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
797 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
798 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
799 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
800
dc8ae677 801 if (indirect)
5db86843 802 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
dc8ae677 803
bf4865b5
LL		 804 /* enable clock gating */
805 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
806
807 /* enable VCPU clock */
808 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
809 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
810 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
5db86843 811 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 812 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
813
814 /* disable master interupt */
5db86843 815 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 816 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
817
818 /* setup mmUVD_LMI_CTRL */
819 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
820 UVD_LMI_CTRL__REQ_MODE_MASK |
821 UVD_LMI_CTRL__CRC_RESET_MASK |
822 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
823 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
824 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
825 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
826 0x00100000L);
5db86843 827 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 828 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
829
5db86843 830 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 831 UVD, 0, mmUVD_MPC_CNTL),
832 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
833
5db86843 834 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 835 UVD, 0, mmUVD_MPC_SET_MUXA0),
836 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
837 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
838 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
839 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
840
5db86843 841 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 842 UVD, 0, mmUVD_MPC_SET_MUXB0),
843 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
844 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
845 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
846 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
847
5db86843 848 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 849 UVD, 0, mmUVD_MPC_SET_MUX),
850 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
851 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
852 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
853
854 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
855
5db86843 856 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5 857 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
5db86843 858 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 859 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
860
861 /* release VCPU reset to boot */
5db86843 862 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 863 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
864
865 /* enable LMI MC and UMC channels */
5db86843 866 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 867 UVD, 0, mmUVD_LMI_CTRL2),
868 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
869
870 /* enable master interrupt */
5db86843 871 WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
bf4865b5
LL		 872 UVD, 0, mmUVD_MASTINT_EN),
873 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
874
dc8ae677 875 if (indirect)
5db86843
JZ		 876 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
877 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
878 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
dc8ae677 879
bf4865b5
LL		 880 /* force RBC into idle state */
881 rb_bufsz = order_base_2(ring->ring_size);
882 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
883 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
884 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
885 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
886 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
887 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
888
ef563ff4
JZ		 889 /* Stall DPG before WPTR/RPTR reset */
890 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
891 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
892 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
93521410
JZ		 893 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
894
bf4865b5
LL		 895 /* set the write pointer delay */
896 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
897
898 /* set the wb address */
899 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
900 (upper_32_bits(ring->gpu_addr) >> 2));
901
902 /* programm the RB_BASE for ring buffer */
903 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
904 lower_32_bits(ring->gpu_addr));
905 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
906 upper_32_bits(ring->gpu_addr));
907
908 /* Initialize the ring buffer's read and write pointers */
909 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
910
911 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
912
913 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
914 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
915 lower_32_bits(ring->wptr));
916
93521410 917 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
ef563ff4
JZ		 918 /* Unstall DPG */
919 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
920 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
bf4865b5
LL		 921 return 0;
922}
923
1b61de45
LL		 924static int vcn_v2_0_start(struct amdgpu_device *adev)
925{
93521410 926 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
c01b6a1d 927 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1b61de45
LL		 928 uint32_t rb_bufsz, tmp;
929 uint32_t lmi_swap_cntl;
930 int i, j, r;
931
c113ba15
JX		 932 if (adev->pm.dpm_enabled)
933 amdgpu_dpm_enable_uvd(adev, true);
934
b0f3cd31
LL		 935 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
936 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
bf4865b5 937
1b61de45
LL		 938 vcn_v2_0_disable_static_power_gating(adev);
939
940 /* set uvd status busy */
941 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
942 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
943
944 /*SW clock gating */
945 vcn_v2_0_disable_clock_gating(adev);
946
947 /* enable VCPU clock */
948 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
949 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
950
951 /* disable master interrupt */
952 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
953 ~UVD_MASTINT_EN__VCPU_EN_MASK);
954
955 /* setup mmUVD_LMI_CTRL */
956 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
957 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
958 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
959 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
960 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
961 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
962
963 /* setup mmUVD_MPC_CNTL */
964 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
965 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
966 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
967 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
968
969 /* setup UVD_MPC_SET_MUXA0 */
970 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
971 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
972 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
973 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
974 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
975
976 /* setup UVD_MPC_SET_MUXB0 */
977 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
978 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
979 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
980 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
981 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
982
983 /* setup mmUVD_MPC_SET_MUX */
984 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
985 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
986 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
987 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
988
989 vcn_v2_0_mc_resume(adev);
990
991 /* release VCPU reset to boot */
992 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
993 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
994
995 /* enable LMI MC and UMC channels */
996 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
997 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
998
999 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1000 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1001 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1002 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1003
1004 /* disable byte swapping */
1005 lmi_swap_cntl = 0;
1006#ifdef __BIG_ENDIAN
1007 /* swap (8 in 32) RB and IB */
1008 lmi_swap_cntl = 0xa;
1009#endif
1010 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1011
1012 for (i = 0; i < 10; ++i) {
1013 uint32_t status;
1014
1015 for (j = 0; j < 100; ++j) {
1016 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1017 if (status & 2)
1018 break;
1019 mdelay(10);
1020 }
1021 r = 0;
1022 if (status & 2)
1023 break;
1024
1025 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1026 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1027 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1028 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1029 mdelay(10);
1030 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1031 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1032 mdelay(10);
1033 r = -1;
1034 }
1035
1036 if (r) {
1037 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1038 return r;
1039 }
1040
1041 /* enable master interrupt */
1042 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1043 UVD_MASTINT_EN__VCPU_EN_MASK,
1044 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1045
1046 /* clear the busy bit of VCN_STATUS */
1047 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1048 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1049
1050 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1051
1052 /* force RBC into idle state */
1053 rb_bufsz = order_base_2(ring->ring_size);
1054 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1055 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1056 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1057 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1058 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1059 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1060
93521410 1061 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1b61de45
LL		 1062 /* programm the RB_BASE for ring buffer */
1063 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1064 lower_32_bits(ring->gpu_addr));
1065 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1066 upper_32_bits(ring->gpu_addr));
1067
1068 /* Initialize the ring buffer's read and write pointers */
1069 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1070
1071 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1072 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1073 lower_32_bits(ring->wptr));
93521410 1074 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1b61de45 1075
93521410 1076 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1077 ring = &adev->vcn.inst->ring_enc[0];
1b61de45
LL		 1078 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1079 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1080 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1081 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1082 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
93521410 1083 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1b61de45 1084
93521410 1085 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1086 ring = &adev->vcn.inst->ring_enc[1];
1b61de45
LL		 1087 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1088 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1089 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1090 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1091 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
93521410 1092 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1b61de45 1093
b0f3cd31 1094 return 0;
1b61de45
LL		 1095}
1096
bf4865b5
LL		 1097static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1098{
1099 int ret_code = 0;
1100 uint32_t tmp;
1101
1102 /* Wait for power status to be 1 */
1103 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1104 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1105
1106 /* wait for read ptr to be equal to write ptr */
1107 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1108 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1109
1110 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1111 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code);
1112
bf4865b5
LL		 1113 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1115
1116 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1117 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1118
1119 /* disable dynamic power gating mode */
1120 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1121 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1122
1123 return 0;
1124}
1125
1b61de45
LL		 1126static int vcn_v2_0_stop(struct amdgpu_device *adev)
1127{
1128 uint32_t tmp;
1129 int r;
1130
bf4865b5
LL		 1131 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1132 r = vcn_v2_0_stop_dpg_mode(adev);
1133 if (r)
1134 return r;
1135 goto power_off;
1136 }
1137
1b61de45
LL		 1138 /* wait for uvd idle */
1139 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
1140 if (r)
1141 return r;
1142
1143 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1144 UVD_LMI_STATUS__READ_CLEAN_MASK |
1145 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1146 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1147 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1148 if (r)
1149 return r;
1150
1151 /* stall UMC channel */
1152 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1153 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1154 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1155
1156 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1157 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1158 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r);
1159 if (r)
1160 return r;
1161
1162 /* disable VCPU clock */
1163 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1164 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1165
1166 /* reset LMI UMC */
1167 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1168 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1169 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1170
1171 /* reset LMI */
1172 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1173 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1174 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1175
1176 /* reset VCPU */
1177 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1178 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1179 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1180
1181 /* clear status */
1182 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1183
1184 vcn_v2_0_enable_clock_gating(adev);
1185 vcn_v2_0_enable_static_power_gating(adev);
1186
bf4865b5 1187power_off:
c113ba15
JX		 1188 if (adev->pm.dpm_enabled)
1189 amdgpu_dpm_enable_uvd(adev, false);
1190
1b61de45
LL		 1191 return 0;
1192}
1193
7282da0b 1194static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
597e6ac3 1195 int inst_idx, struct dpg_pause_state *new_state)
7282da0b
LL		 1196{
1197 struct amdgpu_ring *ring;
1198 uint32_t reg_data = 0;
1199 int ret_code;
1200
1201 /* pause/unpause if state is changed */
f4d0242b 1202 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
7282da0b 1203 DRM_DEBUG("dpg pause state changed %d -> %d",
f4d0242b 1204 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
7282da0b
LL		 1205 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1206 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1207
1208 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1209 ret_code = 0;
1210 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1211 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1212
1213 if (!ret_code) {
93521410 1214 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
7282da0b
LL		 1215 /* pause DPG */
1216 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1217 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1218
1219 /* wait for ACK */
1220 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1221 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1222 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
1223
ef563ff4
JZ		 1224 /* Stall DPG before WPTR/RPTR reset */
1225 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1226 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1227 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
7282da0b 1228 /* Restore */
93521410 1229 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1230 ring = &adev->vcn.inst->ring_enc[0];
ef563ff4 1231 ring->wptr = 0;
7282da0b
LL		 1232 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1233 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1234 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1235 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1236 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
93521410 1237 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
7282da0b 1238
93521410 1239 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
c01b6a1d 1240 ring = &adev->vcn.inst->ring_enc[1];
ef563ff4 1241 ring->wptr = 0;
7282da0b
LL		 1242 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1243 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1244 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1245 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1246 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
93521410 1247 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
7282da0b 1248
93521410 1249 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
7282da0b
LL		 1250 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1251 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
93521410 1252 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
ef563ff4
JZ		 1253 /* Unstall DPG */
1254 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1255 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
7282da0b
LL		 1256
1257 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1258 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1259 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1260 }
1261 } else {
1262 /* unpause dpg, no need to wait */
1263 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1264 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1265 }
f4d0242b 1266 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
7282da0b
LL		 1267 }
1268
1269 return 0;
1270}
1271
1b61de45
LL		 1272static bool vcn_v2_0_is_idle(void *handle)
1273{
1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1275
1276 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1277}
1278
1279static int vcn_v2_0_wait_for_idle(void *handle)
1280{
1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1282 int ret = 0;
1283
1284 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1285 UVD_STATUS__IDLE, ret);
1286
1287 return ret;
1288}
1289
1290static int vcn_v2_0_set_clockgating_state(void *handle,
1291 enum amd_clockgating_state state)
1292{
1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a9d4fe2f 1294 bool enable = (state == AMD_CG_STATE_GATE);
1b61de45 1295
cc9f2fba
ML		 1296 if (amdgpu_sriov_vf(adev))
1297 return 0;
1298
1b61de45
LL		 1299 if (enable) {
1300 /* wait for STATUS to clear */
23edf7f1 1301 if (!vcn_v2_0_is_idle(handle))
1b61de45
LL		 1302 return -EBUSY;
1303 vcn_v2_0_enable_clock_gating(adev);
1304 } else {
1305 /* disable HW gating and enable Sw gating */
1306 vcn_v2_0_disable_clock_gating(adev);
1307 }
1308 return 0;
1309}
1310
1311/**
1312 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1313 *
1314 * @ring: amdgpu_ring pointer
1315 *
1316 * Returns the current hardware read pointer
1317 */
1318static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1319{
1320 struct amdgpu_device *adev = ring->adev;
1321
1322 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1323}
1324
1325/**
1326 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1327 *
1328 * @ring: amdgpu_ring pointer
1329 *
1330 * Returns the current hardware write pointer
1331 */
1332static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1333{
1334 struct amdgpu_device *adev = ring->adev;
1335
1336 if (ring->use_doorbell)
1337 return adev->wb.wb[ring->wptr_offs];
1338 else
1339 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1340}
1341
1342/**
1343 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1344 *
1345 * @ring: amdgpu_ring pointer
1346 *
1347 * Commits the write pointer to the hardware
1348 */
1349static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1350{
1351 struct amdgpu_device *adev = ring->adev;
1352
7282da0b
LL		 1353 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1354 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1355 lower_32_bits(ring->wptr) | 0x80000000);
1356
1b61de45
LL		 1357 if (ring->use_doorbell) {
1358 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1359 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1360 } else {
1361 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1362 }
1363}
1364
1365/**
1366 * vcn_v2_0_dec_ring_insert_start - insert a start command
1367 *
1368 * @ring: amdgpu_ring pointer
1369 *
1370 * Write a start command to the ring.
1371 */
cdbd115e 1372void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1b61de45 1373{
22a8f442
LL		 1374 struct amdgpu_device *adev = ring->adev;
1375
1376 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45 1377 amdgpu_ring_write(ring, 0);
22a8f442 1378 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1379 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1b61de45
LL		 1380}
1381
1382/**
1383 * vcn_v2_0_dec_ring_insert_end - insert a end command
1384 *
1385 * @ring: amdgpu_ring pointer
1386 *
1387 * Write a end command to the ring.
1388 */
cdbd115e 1389void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1b61de45 1390{
22a8f442
LL		 1391 struct amdgpu_device *adev = ring->adev;
1392
1393 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1394 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1b61de45
LL		 1395}
1396
1397/**
1398 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1399 *
1400 * @ring: amdgpu_ring pointer
1401 *
1402 * Write a nop command to the ring.
1403 */
cdbd115e 1404void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1b61de45 1405{
22a8f442 1406 struct amdgpu_device *adev = ring->adev;
1b61de45
LL		 1407 int i;
1408
1409 WARN_ON(ring->wptr % 2 || count % 2);
1410
1411 for (i = 0; i < count / 2; i++) {
22a8f442 1412 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1b61de45
LL		 1413 amdgpu_ring_write(ring, 0);
1414 }
1415}
1416
1417/**
1418 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1419 *
1420 * @ring: amdgpu_ring pointer
1421 * @fence: fence to emit
1422 *
1423 * Write a fence and a trap command to the ring.
1424 */
cdbd115e
LL		 1425void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1426 unsigned flags)
1b61de45 1427{
22a8f442 1428 struct amdgpu_device *adev = ring->adev;
1b61de45 1429
22a8f442
LL		 1430 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1431 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1b61de45
LL		 1432 amdgpu_ring_write(ring, seq);
1433
22a8f442 1434 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1435 amdgpu_ring_write(ring, addr & 0xffffffff);
1436
22a8f442 1437 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1438 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1439
22a8f442 1440 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
333fe325 1441 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1b61de45 1442
22a8f442 1443 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1444 amdgpu_ring_write(ring, 0);
1445
22a8f442 1446 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1447 amdgpu_ring_write(ring, 0);
1448
22a8f442 1449 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1450
333fe325 1451 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1b61de45
LL		 1452}
1453
1454/**
1455 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1456 *
1457 * @ring: amdgpu_ring pointer
1458 * @ib: indirect buffer to execute
1459 *
1460 * Write ring commands to execute the indirect buffer
1461 */
cdbd115e
LL		 1462void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1463 struct amdgpu_job *job,
1464 struct amdgpu_ib *ib,
1465 uint32_t flags)
1b61de45 1466{
22a8f442 1467 struct amdgpu_device *adev = ring->adev;
1b61de45
LL		 1468 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1469
22a8f442 1470 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1b61de45
LL		 1471 amdgpu_ring_write(ring, vmid);
1472
22a8f442 1473 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1b61de45 1474 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
22a8f442 1475 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1b61de45 1476 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
22a8f442 1477 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1b61de45
LL		 1478 amdgpu_ring_write(ring, ib->length_dw);
1479}
1480
cdbd115e
LL		 1481void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1482 uint32_t val, uint32_t mask)
1b61de45 1483{
22a8f442
LL		 1484 struct amdgpu_device *adev = ring->adev;
1485
1486 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1487 amdgpu_ring_write(ring, reg << 2);
1488
22a8f442 1489 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1490 amdgpu_ring_write(ring, val);
1491
22a8f442 1492 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1b61de45
LL		 1493 amdgpu_ring_write(ring, mask);
1494
22a8f442 1495 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1496
333fe325 1497 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1b61de45
LL		 1498}
1499
cdbd115e
LL		 1500void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1501 unsigned vmid, uint64_t pd_addr)
1b61de45
LL		 1502{
1503 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1504 uint32_t data0, data1, mask;
1505
1506 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1507
1508 /* wait for register write */
1509 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1510 data1 = lower_32_bits(pd_addr);
1511 mask = 0xffffffff;
1512 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1513}
1514
cdbd115e
LL		 1515void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1516 uint32_t reg, uint32_t val)
1b61de45 1517{
22a8f442
LL		 1518 struct amdgpu_device *adev = ring->adev;
1519
1520 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1b61de45
LL		 1521 amdgpu_ring_write(ring, reg << 2);
1522
22a8f442 1523 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1b61de45
LL		 1524 amdgpu_ring_write(ring, val);
1525
22a8f442 1526 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1b61de45 1527
333fe325 1528 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1b61de45
LL		 1529}
1530
1531/**
1532 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1533 *
1534 * @ring: amdgpu_ring pointer
1535 *
1536 * Returns the current hardware enc read pointer
1537 */
1538static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1539{
1540 struct amdgpu_device *adev = ring->adev;
1541
c01b6a1d 1542 if (ring == &adev->vcn.inst->ring_enc[0])
1b61de45
LL		 1543 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1544 else
1545 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1546}
1547
1548 /**
1549 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1550 *
1551 * @ring: amdgpu_ring pointer
1552 *
1553 * Returns the current hardware enc write pointer
1554 */
1555static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1556{
1557 struct amdgpu_device *adev = ring->adev;
1558
c01b6a1d 1559 if (ring == &adev->vcn.inst->ring_enc[0]) {
1b61de45
LL		 1560 if (ring->use_doorbell)
1561 return adev->wb.wb[ring->wptr_offs];
1562 else
1563 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1564 } else {
1565 if (ring->use_doorbell)
1566 return adev->wb.wb[ring->wptr_offs];
1567 else
1568 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1569 }
1570}
1571
1572 /**
1573 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1574 *
1575 * @ring: amdgpu_ring pointer
1576 *
1577 * Commits the enc write pointer to the hardware
1578 */
1579static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1580{
1581 struct amdgpu_device *adev = ring->adev;
1582
c01b6a1d 1583 if (ring == &adev->vcn.inst->ring_enc[0]) {
1b61de45
LL		 1584 if (ring->use_doorbell) {
1585 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1586 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1587 } else {
1588 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1589 }
1590 } else {
1591 if (ring->use_doorbell) {
1592 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1593 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1594 } else {
1595 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1596 }
1597 }
1598}
1599
1600/**
1601 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1602 *
1603 * @ring: amdgpu_ring pointer
1604 * @fence: fence to emit
1605 *
1606 * Write enc a fence and a trap command to the ring.
1607 */
cdbd115e
LL		 1608void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1609 u64 seq, unsigned flags)
1b61de45
LL		 1610{
1611 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1612
1613 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1614 amdgpu_ring_write(ring, addr);
1615 amdgpu_ring_write(ring, upper_32_bits(addr));
1616 amdgpu_ring_write(ring, seq);
1617 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1618}
1619
cdbd115e 1620void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1b61de45
LL		 1621{
1622 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1623}
1624
1625/**
1626 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1627 *
1628 * @ring: amdgpu_ring pointer
1629 * @ib: indirect buffer to execute
1630 *
1631 * Write enc ring commands to execute the indirect buffer
1632 */
cdbd115e
LL		 1633void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1634 struct amdgpu_job *job,
1635 struct amdgpu_ib *ib,
1636 uint32_t flags)
1b61de45
LL		 1637{
1638 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1639
1640 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1641 amdgpu_ring_write(ring, vmid);
1642 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1643 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1644 amdgpu_ring_write(ring, ib->length_dw);
1645}
1646
cdbd115e
LL		 1647void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1648 uint32_t val, uint32_t mask)
1b61de45
LL		 1649{
1650 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1651 amdgpu_ring_write(ring, reg << 2);
1652 amdgpu_ring_write(ring, mask);
1653 amdgpu_ring_write(ring, val);
1654}
1655
cdbd115e
LL		 1656void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1657 unsigned int vmid, uint64_t pd_addr)
1b61de45
LL		 1658{
1659 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1660
1661 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1662
1663 /* wait for reg writes */
1664 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1665 lower_32_bits(pd_addr), 0xffffffff);
1666}
1667
cdbd115e 1668void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1b61de45
LL		 1669{
1670 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1671 amdgpu_ring_write(ring, reg << 2);
1672 amdgpu_ring_write(ring, val);
1673}
1674
1b61de45
LL		 1675static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1676 struct amdgpu_irq_src *source,
1677 unsigned type,
1678 enum amdgpu_interrupt_state state)
1679{
1680 return 0;
1681}
1682
1683static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1684 struct amdgpu_irq_src *source,
1685 struct amdgpu_iv_entry *entry)
1686{
1687 DRM_DEBUG("IH: VCN TRAP\n");
1688
1689 switch (entry->src_id) {
1690 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
c01b6a1d 1691 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1b61de45
LL		 1692 break;
1693 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
c01b6a1d 1694 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1b61de45
LL		 1695 break;
1696 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
c01b6a1d 1697 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1b61de45 1698 break;
1b61de45
LL		 1699 default:
1700 DRM_ERROR("Unhandled interrupt: %d %d\n",
1701 entry->src_id, entry->src_data[0]);
1702 break;
1703 }
1704
1705 return 0;
1706}
1707
b6501217 1708int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
c74dbe44
TT		 1709{
1710 struct amdgpu_device *adev = ring->adev;
1711 uint32_t tmp = 0;
1712 unsigned i;
1713 int r;
1714
68430c6b
ML		 1715 if (amdgpu_sriov_vf(adev))
1716 return 0;
1717
c74dbe44
TT		 1718 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1719 r = amdgpu_ring_alloc(ring, 4);
1720 if (r)
1721 return r;
1722 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1723 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1724 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1725 amdgpu_ring_write(ring, 0xDEADBEEF);
1726 amdgpu_ring_commit(ring);
1727 for (i = 0; i < adev->usec_timeout; i++) {
1728 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1729 if (tmp == 0xDEADBEEF)
1730 break;
9a2ffeb5 1731 udelay(1);
c74dbe44
TT		 1732 }
1733
1734 if (i >= adev->usec_timeout)
1735 r = -ETIMEDOUT;
1736
1737 return r;
1738}
1739
1740
1b61de45
LL		 1741static int vcn_v2_0_set_powergating_state(void *handle,
1742 enum amd_powergating_state state)
1743{
1744 /* This doesn't actually powergate the VCN block.
1745 * That's done in the dpm code via the SMC. This
1746 * just re-inits the block as necessary. The actual
1747 * gating still happens in the dpm code. We should
1748 * revisit this when there is a cleaner line between
1749 * the smc and the hw blocks
1750 */
1751 int ret;
1752 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1753
cc9f2fba
ML		 1754 if (amdgpu_sriov_vf(adev)) {
1755 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1756 return 0;
1757 }
1758
1b61de45
LL		 1759 if (state == adev->vcn.cur_state)
1760 return 0;
1761
1762 if (state == AMD_PG_STATE_GATE)
1763 ret = vcn_v2_0_stop(adev);
1764 else
1765 ret = vcn_v2_0_start(adev);
1766
1767 if (!ret)
1768 adev->vcn.cur_state = state;
1769 return ret;
1770}
1771
dd26858a
ML		 1772static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1773 struct amdgpu_mm_table *table)
1774{
1775 uint32_t data = 0, loop;
1776 uint64_t addr = table->gpu_addr;
1777 struct mmsch_v2_0_init_header *header;
1778 uint32_t size;
1779 int i;
1780
1781 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1782 size = header->header_size + header->vcn_table_size;
1783
1784 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1785 * of memory descriptor location
1786 */
1787 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1788 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1789
1790 /* 2, update vmid of descriptor */
1791 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1792 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1793 /* use domain0 for MM scheduler */
1794 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1795 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1796
1797 /* 3, notify mmsch about the size of this descriptor */
1798 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1799
1800 /* 4, set resp to zero */
1801 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1802
1803 adev->vcn.inst->ring_dec.wptr = 0;
1804 adev->vcn.inst->ring_dec.wptr_old = 0;
1805 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1806
1807 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1808 adev->vcn.inst->ring_enc[i].wptr = 0;
1809 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1810 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1811 }
1812
1813 /* 5, kick off the initialization and wait until
1814 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1815 */
1816 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1817
1818 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1819 loop = 1000;
1820 while ((data & 0x10000002) != 0x10000002) {
1821 udelay(10);
1822 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1823 loop--;
1824 if (!loop)
1825 break;
1826 }
1827
1828 if (!loop) {
1829 DRM_ERROR("failed to init MMSCH, " \
1830 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1831 return -EBUSY;
1832 }
1833
1834 return 0;
1835}
1836
1837static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1838{
1839 int r;
1840 uint32_t tmp;
1841 struct amdgpu_ring *ring;
1842 uint32_t offset, size;
1843 uint32_t table_size = 0;
1844 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1845 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1846 struct mmsch_v2_0_cmd_direct_polling direct_poll = { {0} };
1847 struct mmsch_v2_0_cmd_end end = { {0} };
1848 struct mmsch_v2_0_init_header *header;
1849 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1850 uint8_t i = 0;
1851
1852 header = (struct mmsch_v2_0_init_header *)init_table;
1853 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1854 direct_rd_mod_wt.cmd_header.command_type =
1855 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1856 direct_poll.cmd_header.command_type =
1857 MMSCH_COMMAND__DIRECT_REG_POLLING;
1858 end.cmd_header.command_type = MMSCH_COMMAND__END;
1859
1860 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1861 header->version = MMSCH_VERSION;
1862 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1863
1864 header->vcn_table_offset = header->header_size;
1865
1866 init_table += header->vcn_table_offset;
1867
1868 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1869
1870 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1871 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1872 0xFFFFFFFF, 0x00000004);
1873
1874 /* mc resume*/
1875 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1876 tmp = AMDGPU_UCODE_ID_VCN;
1877 MMSCH_V2_0_INSERT_DIRECT_WT(
1878 SOC15_REG_OFFSET(UVD, i,
1879 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1880 adev->firmware.ucode[tmp].tmr_mc_addr_lo);
1881 MMSCH_V2_0_INSERT_DIRECT_WT(
1882 SOC15_REG_OFFSET(UVD, i,
1883 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1884 adev->firmware.ucode[tmp].tmr_mc_addr_hi);
1885 offset = 0;
1886 } else {
1887 MMSCH_V2_0_INSERT_DIRECT_WT(
1888 SOC15_REG_OFFSET(UVD, i,
1889 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1890 lower_32_bits(adev->vcn.inst->gpu_addr));
1891 MMSCH_V2_0_INSERT_DIRECT_WT(
1892 SOC15_REG_OFFSET(UVD, i,
1893 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1894 upper_32_bits(adev->vcn.inst->gpu_addr));
1895 offset = size;
1896 }
1897
1898 MMSCH_V2_0_INSERT_DIRECT_WT(
1899 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1900 0);
1901 MMSCH_V2_0_INSERT_DIRECT_WT(
1902 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1903 size);
1904
1905 MMSCH_V2_0_INSERT_DIRECT_WT(
1906 SOC15_REG_OFFSET(UVD, i,
1907 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1908 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1909 MMSCH_V2_0_INSERT_DIRECT_WT(
1910 SOC15_REG_OFFSET(UVD, i,
1911 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1912 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1913 MMSCH_V2_0_INSERT_DIRECT_WT(
1914 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1915 0);
1916 MMSCH_V2_0_INSERT_DIRECT_WT(
1917 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1918 AMDGPU_VCN_STACK_SIZE);
1919
1920 MMSCH_V2_0_INSERT_DIRECT_WT(
1921 SOC15_REG_OFFSET(UVD, i,
1922 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1923 lower_32_bits(adev->vcn.inst->gpu_addr + offset +
1924 AMDGPU_VCN_STACK_SIZE));
1925 MMSCH_V2_0_INSERT_DIRECT_WT(
1926 SOC15_REG_OFFSET(UVD, i,
1927 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1928 upper_32_bits(adev->vcn.inst->gpu_addr + offset +
1929 AMDGPU_VCN_STACK_SIZE));
1930 MMSCH_V2_0_INSERT_DIRECT_WT(
1931 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1932 0);
1933 MMSCH_V2_0_INSERT_DIRECT_WT(
1934 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1935 AMDGPU_VCN_CONTEXT_SIZE);
1936
1937 for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
1938 ring = &adev->vcn.inst->ring_enc[r];
1939 ring->wptr = 0;
1940 MMSCH_V2_0_INSERT_DIRECT_WT(
1941 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1942 lower_32_bits(ring->gpu_addr));
1943 MMSCH_V2_0_INSERT_DIRECT_WT(
1944 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1945 upper_32_bits(ring->gpu_addr));
1946 MMSCH_V2_0_INSERT_DIRECT_WT(
1947 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1948 ring->ring_size / 4);
1949 }
1950
1951 ring = &adev->vcn.inst->ring_dec;
1952 ring->wptr = 0;
1953 MMSCH_V2_0_INSERT_DIRECT_WT(
1954 SOC15_REG_OFFSET(UVD, i,
1955 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1956 lower_32_bits(ring->gpu_addr));
1957 MMSCH_V2_0_INSERT_DIRECT_WT(
1958 SOC15_REG_OFFSET(UVD, i,
1959 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1960 upper_32_bits(ring->gpu_addr));
1961 /* force RBC into idle state */
1962 tmp = order_base_2(ring->ring_size);
1963 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1964 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1965 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1966 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1967 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1968 MMSCH_V2_0_INSERT_DIRECT_WT(
1969 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1970
1971 /* add end packet */
1972 tmp = sizeof(struct mmsch_v2_0_cmd_end);
1973 memcpy((void *)init_table, &end, tmp);
1974 table_size += (tmp / 4);
1975 header->vcn_table_size = table_size;
1976
1977 }
1978 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
1979}
1980
1b61de45
LL		 1981static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1982 .name = "vcn_v2_0",
1983 .early_init = vcn_v2_0_early_init,
1984 .late_init = NULL,
1985 .sw_init = vcn_v2_0_sw_init,
1986 .sw_fini = vcn_v2_0_sw_fini,
1987 .hw_init = vcn_v2_0_hw_init,
1988 .hw_fini = vcn_v2_0_hw_fini,
1989 .suspend = vcn_v2_0_suspend,
1990 .resume = vcn_v2_0_resume,
1991 .is_idle = vcn_v2_0_is_idle,
1992 .wait_for_idle = vcn_v2_0_wait_for_idle,
1993 .check_soft_reset = NULL,
1994 .pre_soft_reset = NULL,
1995 .soft_reset = NULL,
1996 .post_soft_reset = NULL,
1997 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
1998 .set_powergating_state = vcn_v2_0_set_powergating_state,
1999};
2000
2001static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2002 .type = AMDGPU_RING_TYPE_VCN_DEC,
2003 .align_mask = 0xf,
a2d15ed7 2004 .vmhub = AMDGPU_MMHUB_0,
1b61de45
LL		 2005 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
2006 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
2007 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2008 .emit_frame_size =
2009 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2010 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2011 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2012 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2013 6,
2014 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2015 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2016 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2017 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
c74dbe44 2018 .test_ring = vcn_v2_0_dec_ring_test_ring,
1b61de45
LL		 2019 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2020 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2021 .insert_start = vcn_v2_0_dec_ring_insert_start,
2022 .insert_end = vcn_v2_0_dec_ring_insert_end,
2023 .pad_ib = amdgpu_ring_generic_pad_ib,
2024 .begin_use = amdgpu_vcn_ring_begin_use,
2025 .end_use = amdgpu_vcn_ring_end_use,
2026 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2027 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2028 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2029};
2030
2031static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2032 .type = AMDGPU_RING_TYPE_VCN_ENC,
2033 .align_mask = 0x3f,
2034 .nop = VCN_ENC_CMD_NO_OP,
a2d15ed7 2035 .vmhub = AMDGPU_MMHUB_0,
1b61de45
LL		 2036 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2037 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2038 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2039 .emit_frame_size =
2040 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2041 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2042 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2043 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2044 1, /* vcn_v2_0_enc_ring_insert_end */
2045 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2046 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2047 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2048 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2049 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2050 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2051 .insert_nop = amdgpu_ring_insert_nop,
2052 .insert_end = vcn_v2_0_enc_ring_insert_end,
2053 .pad_ib = amdgpu_ring_generic_pad_ib,
2054 .begin_use = amdgpu_vcn_ring_begin_use,
2055 .end_use = amdgpu_vcn_ring_end_use,
2056 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2057 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2058 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2059};
2060
1b61de45
LL		 2061static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2062{
c01b6a1d 2063 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
1b61de45
LL		 2064 DRM_INFO("VCN decode is enabled in VM mode\n");
2065}
2066
2067static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2068{
2069 int i;
2070
2071 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
c01b6a1d 2072 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
1b61de45
LL		 2073
2074 DRM_INFO("VCN encode is enabled in VM mode\n");
2075}
2076
1b61de45
LL		 2077static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2078 .set = vcn_v2_0_set_interrupt_state,
2079 .process = vcn_v2_0_process_interrupt,
2080};
2081
2082static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2083{
21a174f5 2084 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
c01b6a1d 2085 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
1b61de45
LL		 2086}
2087
2088const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2089{
2090 .type = AMD_IP_BLOCK_TYPE_VCN,
2091 .major = 2,
2092 .minor = 0,
2093 .rev = 0,
2094 .funcs = &vcn_v2_0_ip_funcs,
2095};
Linux 6.x block layer and io_uring tree(s)