Commit | Line | Data |
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aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | * Authors: Christian König <christian.koenig@amd.com> | |
26 | */ | |
27 | ||
28 | #include <linux/firmware.h> | |
47b757fb | 29 | |
aaa36a97 AD |
30 | #include "amdgpu.h" |
31 | #include "amdgpu_vce.h" | |
32 | #include "vid.h" | |
33 | #include "vce/vce_3_0_d.h" | |
34 | #include "vce/vce_3_0_sh_mask.h" | |
be4f38e2 AD |
35 | #include "oss/oss_3_0_d.h" |
36 | #include "oss/oss_3_0_sh_mask.h" | |
5bbc553a | 37 | #include "gca/gfx_8_0_d.h" |
6a585777 AD |
38 | #include "smu/smu_7_1_2_d.h" |
39 | #include "smu/smu_7_1_2_sh_mask.h" | |
115933a5 | 40 | #include "gca/gfx_8_0_sh_mask.h" |
091aec0b | 41 | #include "ivsrcid/ivsrcid_vislands30.h" |
115933a5 | 42 | |
5bbc553a LL |
43 | |
44 | #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04 | |
45 | #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10 | |
50a1ebc7 RZ |
46 | #define GRBM_GFX_INDEX__VCE_ALL_PIPE 0x07 |
47 | ||
edf600da CK |
48 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616 |
49 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617 | |
50 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618 | |
50a1ebc7 RZ |
51 | #define mmGRBM_GFX_INDEX_DEFAULT 0xE0000000 |
52 | ||
567e6e29 | 53 | #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 |
aaa36a97 | 54 | |
e9822622 LL |
55 | #define VCE_V3_0_FW_SIZE (384 * 1024) |
56 | #define VCE_V3_0_STACK_SIZE (64 * 1024) | |
57 | #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) | |
58 | ||
ef6239e0 AD |
59 | #define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8)) |
60 | ||
50a1ebc7 RZ |
61 | #define GET_VCE_INSTANCE(i) ((i) << GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT \ |
62 | | GRBM_GFX_INDEX__VCE_ALL_PIPE) | |
63 | ||
5bbc553a | 64 | static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); |
aaa36a97 AD |
65 | static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); |
66 | static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); | |
567e6e29 | 67 | static int vce_v3_0_wait_for_idle(void *handle); |
26679899 RZ |
68 | static int vce_v3_0_set_clockgating_state(void *handle, |
69 | enum amd_clockgating_state state); | |
aaa36a97 AD |
70 | /** |
71 | * vce_v3_0_ring_get_rptr - get read pointer | |
72 | * | |
73 | * @ring: amdgpu_ring pointer | |
74 | * | |
75 | * Returns the current hardware read pointer | |
76 | */ | |
536fbf94 | 77 | static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) |
aaa36a97 AD |
78 | { |
79 | struct amdgpu_device *adev = ring->adev; | |
45cc6586 LL |
80 | u32 v; |
81 | ||
82 | mutex_lock(&adev->grbm_idx_mutex); | |
83 | if (adev->vce.harvest_config == 0 || | |
84 | adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) | |
85 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); | |
86 | else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) | |
87 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); | |
aaa36a97 | 88 | |
5d4af988 | 89 | if (ring->me == 0) |
45cc6586 | 90 | v = RREG32(mmVCE_RB_RPTR); |
5d4af988 | 91 | else if (ring->me == 1) |
45cc6586 | 92 | v = RREG32(mmVCE_RB_RPTR2); |
6f0359ff | 93 | else |
45cc6586 LL |
94 | v = RREG32(mmVCE_RB_RPTR3); |
95 | ||
96 | WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); | |
97 | mutex_unlock(&adev->grbm_idx_mutex); | |
98 | ||
99 | return v; | |
aaa36a97 AD |
100 | } |
101 | ||
102 | /** | |
103 | * vce_v3_0_ring_get_wptr - get write pointer | |
104 | * | |
105 | * @ring: amdgpu_ring pointer | |
106 | * | |
107 | * Returns the current hardware write pointer | |
108 | */ | |
536fbf94 | 109 | static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) |
aaa36a97 AD |
110 | { |
111 | struct amdgpu_device *adev = ring->adev; | |
45cc6586 LL |
112 | u32 v; |
113 | ||
114 | mutex_lock(&adev->grbm_idx_mutex); | |
115 | if (adev->vce.harvest_config == 0 || | |
116 | adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) | |
117 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); | |
118 | else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) | |
119 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); | |
aaa36a97 | 120 | |
5d4af988 | 121 | if (ring->me == 0) |
45cc6586 | 122 | v = RREG32(mmVCE_RB_WPTR); |
5d4af988 | 123 | else if (ring->me == 1) |
45cc6586 | 124 | v = RREG32(mmVCE_RB_WPTR2); |
6f0359ff | 125 | else |
45cc6586 LL |
126 | v = RREG32(mmVCE_RB_WPTR3); |
127 | ||
128 | WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); | |
129 | mutex_unlock(&adev->grbm_idx_mutex); | |
130 | ||
131 | return v; | |
aaa36a97 AD |
132 | } |
133 | ||
134 | /** | |
135 | * vce_v3_0_ring_set_wptr - set write pointer | |
136 | * | |
137 | * @ring: amdgpu_ring pointer | |
138 | * | |
139 | * Commits the write pointer to the hardware | |
140 | */ | |
141 | static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) | |
142 | { | |
143 | struct amdgpu_device *adev = ring->adev; | |
144 | ||
45cc6586 LL |
145 | mutex_lock(&adev->grbm_idx_mutex); |
146 | if (adev->vce.harvest_config == 0 || | |
147 | adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) | |
148 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); | |
149 | else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) | |
150 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); | |
151 | ||
5d4af988 | 152 | if (ring->me == 0) |
536fbf94 | 153 | WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); |
5d4af988 | 154 | else if (ring->me == 1) |
536fbf94 | 155 | WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); |
6f0359ff | 156 | else |
536fbf94 | 157 | WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); |
45cc6586 LL |
158 | |
159 | WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); | |
160 | mutex_unlock(&adev->grbm_idx_mutex); | |
aaa36a97 AD |
161 | } |
162 | ||
0689a570 EH |
163 | static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override) |
164 | { | |
f3f0ea95 | 165 | WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0); |
0689a570 EH |
166 | } |
167 | ||
168 | static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev, | |
169 | bool gated) | |
170 | { | |
f3f0ea95 | 171 | u32 data; |
f16fe6d3 | 172 | |
0689a570 EH |
173 | /* Set Override to disable Clock Gating */ |
174 | vce_v3_0_override_vce_clock_gating(adev, true); | |
175 | ||
6f906814 TSD |
176 | /* This function enables MGCG which is controlled by firmware. |
177 | With the clocks in the gated state the core is still | |
178 | accessible but the firmware will throttle the clocks on the | |
179 | fly as necessary. | |
180 | */ | |
ecc2cf7c | 181 | if (!gated) { |
f3f0ea95 | 182 | data = RREG32(mmVCE_CLOCK_GATING_B); |
0689a570 EH |
183 | data |= 0x1ff; |
184 | data &= ~0xef0000; | |
f3f0ea95 | 185 | WREG32(mmVCE_CLOCK_GATING_B, data); |
0689a570 | 186 | |
f3f0ea95 | 187 | data = RREG32(mmVCE_UENC_CLOCK_GATING); |
0689a570 EH |
188 | data |= 0x3ff000; |
189 | data &= ~0xffc00000; | |
f3f0ea95 | 190 | WREG32(mmVCE_UENC_CLOCK_GATING, data); |
0689a570 | 191 | |
f3f0ea95 | 192 | data = RREG32(mmVCE_UENC_CLOCK_GATING_2); |
0689a570 | 193 | data |= 0x2; |
6f906814 | 194 | data &= ~0x00010000; |
f3f0ea95 | 195 | WREG32(mmVCE_UENC_CLOCK_GATING_2, data); |
0689a570 | 196 | |
f3f0ea95 | 197 | data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); |
0689a570 | 198 | data |= 0x37f; |
f3f0ea95 | 199 | WREG32(mmVCE_UENC_REG_CLOCK_GATING, data); |
0689a570 | 200 | |
f3f0ea95 | 201 | data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); |
0689a570 | 202 | data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK | |
f16fe6d3 TSD |
203 | VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK | |
204 | VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK | | |
205 | 0x8; | |
f3f0ea95 | 206 | WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data); |
0689a570 | 207 | } else { |
f3f0ea95 | 208 | data = RREG32(mmVCE_CLOCK_GATING_B); |
0689a570 EH |
209 | data &= ~0x80010; |
210 | data |= 0xe70008; | |
f3f0ea95 | 211 | WREG32(mmVCE_CLOCK_GATING_B, data); |
6f906814 | 212 | |
f3f0ea95 | 213 | data = RREG32(mmVCE_UENC_CLOCK_GATING); |
0689a570 | 214 | data |= 0xffc00000; |
f3f0ea95 | 215 | WREG32(mmVCE_UENC_CLOCK_GATING, data); |
6f906814 | 216 | |
f3f0ea95 | 217 | data = RREG32(mmVCE_UENC_CLOCK_GATING_2); |
0689a570 | 218 | data |= 0x10000; |
f3f0ea95 | 219 | WREG32(mmVCE_UENC_CLOCK_GATING_2, data); |
6f906814 | 220 | |
f3f0ea95 | 221 | data = RREG32(mmVCE_UENC_REG_CLOCK_GATING); |
e05208de | 222 | data &= ~0x3ff; |
f3f0ea95 | 223 | WREG32(mmVCE_UENC_REG_CLOCK_GATING, data); |
6f906814 | 224 | |
f3f0ea95 | 225 | data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); |
0689a570 | 226 | data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK | |
f16fe6d3 TSD |
227 | VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK | |
228 | VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK | | |
229 | 0x8); | |
f3f0ea95 | 230 | WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data); |
0689a570 EH |
231 | } |
232 | vce_v3_0_override_vce_clock_gating(adev, false); | |
233 | } | |
234 | ||
567e6e29 | 235 | static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev) |
236 | { | |
237 | int i, j; | |
567e6e29 | 238 | |
239 | for (i = 0; i < 10; ++i) { | |
240 | for (j = 0; j < 100; ++j) { | |
b7e2e9f7 | 241 | uint32_t status = RREG32(mmVCE_STATUS); |
242 | ||
567e6e29 | 243 | if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK) |
244 | return 0; | |
245 | mdelay(10); | |
246 | } | |
247 | ||
248 | DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); | |
f3f0ea95 | 249 | WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); |
567e6e29 | 250 | mdelay(10); |
f3f0ea95 | 251 | WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); |
567e6e29 | 252 | mdelay(10); |
253 | } | |
254 | ||
255 | return -ETIMEDOUT; | |
256 | } | |
257 | ||
aaa36a97 AD |
258 | /** |
259 | * vce_v3_0_start - start VCE block | |
260 | * | |
261 | * @adev: amdgpu_device pointer | |
262 | * | |
263 | * Setup and start the VCE block | |
264 | */ | |
265 | static int vce_v3_0_start(struct amdgpu_device *adev) | |
266 | { | |
267 | struct amdgpu_ring *ring; | |
567e6e29 | 268 | int idx, r; |
269 | ||
5bbc553a LL |
270 | mutex_lock(&adev->grbm_idx_mutex); |
271 | for (idx = 0; idx < 2; ++idx) { | |
6a585777 AD |
272 | if (adev->vce.harvest_config & (1 << idx)) |
273 | continue; | |
274 | ||
50a1ebc7 | 275 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); |
45cc6586 LL |
276 | |
277 | /* Program instance 0 reg space for two instances or instance 0 case | |
278 | program instance 1 reg space for only instance 1 available case */ | |
279 | if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) { | |
280 | ring = &adev->vce.ring[0]; | |
281 | WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); | |
282 | WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); | |
283 | WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); | |
284 | WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); | |
285 | WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); | |
286 | ||
287 | ring = &adev->vce.ring[1]; | |
288 | WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); | |
289 | WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); | |
290 | WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); | |
291 | WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); | |
292 | WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); | |
293 | ||
294 | ring = &adev->vce.ring[2]; | |
295 | WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); | |
296 | WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); | |
297 | WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); | |
298 | WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); | |
299 | WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4); | |
300 | } | |
301 | ||
5bbc553a | 302 | vce_v3_0_mc_resume(adev, idx); |
f3f0ea95 | 303 | WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1); |
567e6e29 | 304 | |
3c0ff9f1 LL |
305 | if (adev->asic_type >= CHIP_STONEY) |
306 | WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); | |
307 | else | |
f3f0ea95 | 308 | WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); |
5bbc553a | 309 | |
f3f0ea95 | 310 | WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); |
567e6e29 | 311 | mdelay(100); |
312 | ||
313 | r = vce_v3_0_firmware_loaded(adev); | |
5bbc553a LL |
314 | |
315 | /* clear BUSY flag */ | |
f3f0ea95 | 316 | WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0); |
aaa36a97 | 317 | |
5bbc553a LL |
318 | if (r) { |
319 | DRM_ERROR("VCE not responding, giving up!!!\n"); | |
320 | mutex_unlock(&adev->grbm_idx_mutex); | |
321 | return r; | |
322 | } | |
323 | } | |
aaa36a97 | 324 | |
50a1ebc7 | 325 | WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); |
5bbc553a | 326 | mutex_unlock(&adev->grbm_idx_mutex); |
aaa36a97 | 327 | |
567e6e29 | 328 | return 0; |
329 | } | |
aaa36a97 | 330 | |
567e6e29 | 331 | static int vce_v3_0_stop(struct amdgpu_device *adev) |
332 | { | |
333 | int idx; | |
334 | ||
335 | mutex_lock(&adev->grbm_idx_mutex); | |
336 | for (idx = 0; idx < 2; ++idx) { | |
337 | if (adev->vce.harvest_config & (1 << idx)) | |
338 | continue; | |
339 | ||
50a1ebc7 | 340 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); |
567e6e29 | 341 | |
342 | if (adev->asic_type >= CHIP_STONEY) | |
343 | WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001); | |
344 | else | |
f3f0ea95 TSD |
345 | WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0); |
346 | ||
567e6e29 | 347 | /* hold on ECPU */ |
f3f0ea95 | 348 | WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); |
567e6e29 | 349 | |
26679899 RZ |
350 | /* clear VCE STATUS */ |
351 | WREG32(mmVCE_STATUS, 0); | |
567e6e29 | 352 | } |
353 | ||
50a1ebc7 | 354 | WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); |
567e6e29 | 355 | mutex_unlock(&adev->grbm_idx_mutex); |
aaa36a97 | 356 | |
aaa36a97 AD |
357 | return 0; |
358 | } | |
359 | ||
6a585777 AD |
360 | #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074 |
361 | #define VCE_HARVEST_FUSE_MACRO__SHIFT 27 | |
362 | #define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000 | |
363 | ||
364 | static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) | |
365 | { | |
366 | u32 tmp; | |
6a585777 | 367 | |
cfaba566 | 368 | if ((adev->asic_type == CHIP_FIJI) || |
32bec2af | 369 | (adev->asic_type == CHIP_STONEY)) |
1dab5f06 | 370 | return AMDGPU_VCE_HARVEST_VCE1; |
188a9bcd | 371 | |
2f7d10b3 | 372 | if (adev->flags & AMD_IS_APU) |
6a585777 AD |
373 | tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & |
374 | VCE_HARVEST_FUSE_MACRO__MASK) >> | |
375 | VCE_HARVEST_FUSE_MACRO__SHIFT; | |
376 | else | |
377 | tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & | |
378 | CC_HARVEST_FUSES__VCE_DISABLE_MASK) >> | |
379 | CC_HARVEST_FUSES__VCE_DISABLE__SHIFT; | |
380 | ||
381 | switch (tmp) { | |
382 | case 1: | |
1dab5f06 | 383 | return AMDGPU_VCE_HARVEST_VCE0; |
6a585777 | 384 | case 2: |
1dab5f06 | 385 | return AMDGPU_VCE_HARVEST_VCE1; |
6a585777 | 386 | case 3: |
1dab5f06 | 387 | return AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1; |
6a585777 | 388 | default: |
32bec2af LL |
389 | if ((adev->asic_type == CHIP_POLARIS10) || |
390 | (adev->asic_type == CHIP_POLARIS11) || | |
a7712897 LL |
391 | (adev->asic_type == CHIP_POLARIS12) || |
392 | (adev->asic_type == CHIP_VEGAM)) | |
32bec2af LL |
393 | return AMDGPU_VCE_HARVEST_VCE1; |
394 | ||
1dab5f06 | 395 | return 0; |
6a585777 | 396 | } |
6a585777 AD |
397 | } |
398 | ||
5fc3aeeb | 399 | static int vce_v3_0_early_init(void *handle) |
aaa36a97 | 400 | { |
5fc3aeeb | 401 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
402 | ||
6a585777 AD |
403 | adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev); |
404 | ||
405 | if ((adev->vce.harvest_config & | |
406 | (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) == | |
407 | (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) | |
408 | return -ENOENT; | |
409 | ||
6f0359ff | 410 | adev->vce.num_rings = 3; |
75c65480 | 411 | |
aaa36a97 AD |
412 | vce_v3_0_set_ring_funcs(adev); |
413 | vce_v3_0_set_irq_funcs(adev); | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
5fc3aeeb | 418 | static int vce_v3_0_sw_init(void *handle) |
aaa36a97 | 419 | { |
5fc3aeeb | 420 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 | 421 | struct amdgpu_ring *ring; |
75c65480 | 422 | int r, i; |
aaa36a97 AD |
423 | |
424 | /* VCE */ | |
1ffdeca6 | 425 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq); |
aaa36a97 AD |
426 | if (r) |
427 | return r; | |
428 | ||
e9822622 LL |
429 | r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + |
430 | (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2); | |
aaa36a97 AD |
431 | if (r) |
432 | return r; | |
433 | ||
ef6239e0 AD |
434 | /* 52.8.3 required for 3 ring support */ |
435 | if (adev->vce.fw_version < FW_52_8_3) | |
436 | adev->vce.num_rings = 2; | |
aaa36a97 AD |
437 | |
438 | r = amdgpu_vce_resume(adev); | |
439 | if (r) | |
440 | return r; | |
441 | ||
75c65480 | 442 | for (i = 0; i < adev->vce.num_rings; i++) { |
080e613c SS |
443 | enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i); |
444 | ||
75c65480 AD |
445 | ring = &adev->vce.ring[i]; |
446 | sprintf(ring->name, "vce%d", i); | |
1c6d567b | 447 | r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, |
080e613c | 448 | hw_prio, NULL); |
75c65480 AD |
449 | if (r) |
450 | return r; | |
451 | } | |
aaa36a97 | 452 | |
20acbed4 ED |
453 | r = amdgpu_vce_entity_init(adev); |
454 | ||
aaa36a97 AD |
455 | return r; |
456 | } | |
457 | ||
5fc3aeeb | 458 | static int vce_v3_0_sw_fini(void *handle) |
aaa36a97 AD |
459 | { |
460 | int r; | |
5fc3aeeb | 461 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
462 | |
463 | r = amdgpu_vce_suspend(adev); | |
464 | if (r) | |
465 | return r; | |
466 | ||
50237287 | 467 | return amdgpu_vce_sw_fini(adev); |
aaa36a97 AD |
468 | } |
469 | ||
5fc3aeeb | 470 | static int vce_v3_0_hw_init(void *handle) |
aaa36a97 | 471 | { |
691ca86a | 472 | int r, i; |
5fc3aeeb | 473 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 | 474 | |
6fc11b0e | 475 | vce_v3_0_override_vce_clock_gating(adev, true); |
08ebb6e9 RZ |
476 | |
477 | amdgpu_asic_set_vce_clocks(adev, 10000, 10000); | |
aaa36a97 | 478 | |
75c65480 | 479 | for (i = 0; i < adev->vce.num_rings; i++) { |
c66ed765 | 480 | r = amdgpu_ring_test_helper(&adev->vce.ring[i]); |
691ca86a TSD |
481 | if (r) |
482 | return r; | |
aaa36a97 AD |
483 | } |
484 | ||
485 | DRM_INFO("VCE initialized successfully.\n"); | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
5fc3aeeb | 490 | static int vce_v3_0_hw_fini(void *handle) |
aaa36a97 | 491 | { |
567e6e29 | 492 | int r; |
493 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
494 | ||
d82e2c24 AG |
495 | cancel_delayed_work_sync(&adev->vce.idle_work); |
496 | ||
497 | r = vce_v3_0_wait_for_idle(handle); | |
498 | if (r) | |
499 | return r; | |
500 | ||
501 | vce_v3_0_stop(adev); | |
502 | return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); | |
503 | } | |
504 | ||
505 | static int vce_v3_0_suspend(void *handle) | |
506 | { | |
507 | int r; | |
508 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
509 | ||
bf756fb8 EQ |
510 | /* |
511 | * Proper cleanups before halting the HW engine: | |
512 | * - cancel the delayed idle work | |
513 | * - enable powergating | |
514 | * - enable clockgating | |
515 | * - disable dpm | |
516 | * | |
517 | * TODO: to align with the VCN implementation, move the | |
518 | * jobs for clockgating/powergating/dpm setting to | |
519 | * ->set_powergating_state(). | |
520 | */ | |
521 | cancel_delayed_work_sync(&adev->vce.idle_work); | |
522 | ||
523 | if (adev->pm.dpm_enabled) { | |
524 | amdgpu_dpm_enable_vce(adev, false); | |
525 | } else { | |
526 | amdgpu_asic_set_vce_clocks(adev, 0, 0); | |
527 | amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, | |
528 | AMD_PG_STATE_GATE); | |
529 | amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, | |
530 | AMD_CG_STATE_GATE); | |
531 | } | |
532 | ||
aaa36a97 AD |
533 | r = vce_v3_0_hw_fini(adev); |
534 | if (r) | |
535 | return r; | |
536 | ||
50237287 | 537 | return amdgpu_vce_suspend(adev); |
aaa36a97 AD |
538 | } |
539 | ||
5fc3aeeb | 540 | static int vce_v3_0_resume(void *handle) |
aaa36a97 AD |
541 | { |
542 | int r; | |
5fc3aeeb | 543 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
544 | |
545 | r = amdgpu_vce_resume(adev); | |
546 | if (r) | |
547 | return r; | |
548 | ||
50237287 | 549 | return vce_v3_0_hw_init(adev); |
aaa36a97 AD |
550 | } |
551 | ||
5bbc553a | 552 | static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) |
aaa36a97 AD |
553 | { |
554 | uint32_t offset, size; | |
555 | ||
556 | WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); | |
557 | WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); | |
558 | WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); | |
6f906814 | 559 | WREG32(mmVCE_CLOCK_GATING_B, 0x1FF); |
aaa36a97 AD |
560 | |
561 | WREG32(mmVCE_LMI_CTRL, 0x00398000); | |
562 | WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); | |
563 | WREG32(mmVCE_LMI_SWAP_CNTL, 0); | |
564 | WREG32(mmVCE_LMI_SWAP_CNTL1, 0); | |
565 | WREG32(mmVCE_LMI_VM_CTRL, 0); | |
d50e5c24 AH |
566 | WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); |
567 | ||
3c0ff9f1 LL |
568 | if (adev->asic_type >= CHIP_STONEY) { |
569 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); | |
570 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); | |
571 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8)); | |
572 | } else | |
573 | WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); | |
aaa36a97 | 574 | offset = AMDGPU_VCE_FIRMWARE_OFFSET; |
e9822622 | 575 | size = VCE_V3_0_FW_SIZE; |
aaa36a97 AD |
576 | WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); |
577 | WREG32(mmVCE_VCPU_CACHE_SIZE0, size); | |
578 | ||
5bbc553a LL |
579 | if (idx == 0) { |
580 | offset += size; | |
581 | size = VCE_V3_0_STACK_SIZE; | |
582 | WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); | |
583 | WREG32(mmVCE_VCPU_CACHE_SIZE1, size); | |
584 | offset += size; | |
585 | size = VCE_V3_0_DATA_SIZE; | |
586 | WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); | |
587 | WREG32(mmVCE_VCPU_CACHE_SIZE2, size); | |
588 | } else { | |
589 | offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE; | |
590 | size = VCE_V3_0_STACK_SIZE; | |
591 | WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff); | |
592 | WREG32(mmVCE_VCPU_CACHE_SIZE1, size); | |
593 | offset += size; | |
594 | size = VCE_V3_0_DATA_SIZE; | |
595 | WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff); | |
596 | WREG32(mmVCE_VCPU_CACHE_SIZE2, size); | |
597 | } | |
aaa36a97 AD |
598 | |
599 | WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); | |
f3f0ea95 | 600 | WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); |
aaa36a97 AD |
601 | } |
602 | ||
5fc3aeeb | 603 | static bool vce_v3_0_is_idle(void *handle) |
aaa36a97 | 604 | { |
5fc3aeeb | 605 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
be4f38e2 | 606 | u32 mask = 0; |
be4f38e2 | 607 | |
74af1276 TSD |
608 | mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK; |
609 | mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK; | |
be4f38e2 AD |
610 | |
611 | return !(RREG32(mmSRBM_STATUS2) & mask); | |
aaa36a97 AD |
612 | } |
613 | ||
5fc3aeeb | 614 | static int vce_v3_0_wait_for_idle(void *handle) |
aaa36a97 AD |
615 | { |
616 | unsigned i; | |
5fc3aeeb | 617 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
be4f38e2 | 618 | |
92988e60 TSD |
619 | for (i = 0; i < adev->usec_timeout; i++) |
620 | if (vce_v3_0_is_idle(handle)) | |
aaa36a97 | 621 | return 0; |
92988e60 | 622 | |
aaa36a97 AD |
623 | return -ETIMEDOUT; |
624 | } | |
625 | ||
ac8e3f30 RZ |
626 | #define VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK 0x00000008L /* AUTO_BUSY */ |
627 | #define VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK 0x00000010L /* RB0_BUSY */ | |
628 | #define VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK 0x00000020L /* RB1_BUSY */ | |
629 | #define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \ | |
630 | VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK) | |
115933a5 | 631 | |
da146d3b | 632 | static bool vce_v3_0_check_soft_reset(void *handle) |
115933a5 CZ |
633 | { |
634 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
635 | u32 srbm_soft_reset = 0; | |
115933a5 | 636 | |
115933a5 CZ |
637 | /* According to VCE team , we should use VCE_STATUS instead |
638 | * SRBM_STATUS.VCE_BUSY bit for busy status checking. | |
639 | * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE | |
640 | * instance's registers are accessed | |
641 | * (0 for 1st instance, 10 for 2nd instance). | |
642 | * | |
643 | *VCE_STATUS | |
644 | *|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 | |FW_LOADED|JOB | | |
645 | *|----+----+-----------+----+----+----+----------+---------+----| | |
646 | *|bit8|bit7| bit6 |bit5|bit4|bit3| bit2 | bit1 |bit0| | |
647 | * | |
648 | * VCE team suggest use bit 3--bit 6 for busy status check | |
649 | */ | |
9aeb774c | 650 | mutex_lock(&adev->grbm_idx_mutex); |
50a1ebc7 | 651 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); |
115933a5 CZ |
652 | if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { |
653 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1); | |
654 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); | |
655 | } | |
50a1ebc7 | 656 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); |
115933a5 CZ |
657 | if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { |
658 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1); | |
659 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); | |
660 | } | |
50a1ebc7 | 661 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); |
da146d3b | 662 | mutex_unlock(&adev->grbm_idx_mutex); |
115933a5 | 663 | |
115933a5 | 664 | if (srbm_soft_reset) { |
115933a5 | 665 | adev->vce.srbm_soft_reset = srbm_soft_reset; |
da146d3b | 666 | return true; |
115933a5 | 667 | } else { |
115933a5 | 668 | adev->vce.srbm_soft_reset = 0; |
da146d3b | 669 | return false; |
115933a5 | 670 | } |
115933a5 CZ |
671 | } |
672 | ||
5fc3aeeb | 673 | static int vce_v3_0_soft_reset(void *handle) |
aaa36a97 | 674 | { |
5fc3aeeb | 675 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
115933a5 CZ |
676 | u32 srbm_soft_reset; |
677 | ||
da146d3b | 678 | if (!adev->vce.srbm_soft_reset) |
115933a5 CZ |
679 | return 0; |
680 | srbm_soft_reset = adev->vce.srbm_soft_reset; | |
681 | ||
682 | if (srbm_soft_reset) { | |
683 | u32 tmp; | |
be4f38e2 | 684 | |
115933a5 CZ |
685 | tmp = RREG32(mmSRBM_SOFT_RESET); |
686 | tmp |= srbm_soft_reset; | |
687 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
688 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
689 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
690 | ||
691 | udelay(50); | |
692 | ||
693 | tmp &= ~srbm_soft_reset; | |
694 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
695 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
696 | ||
697 | /* Wait a little for things to settle down */ | |
698 | udelay(50); | |
699 | } | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
704 | static int vce_v3_0_pre_soft_reset(void *handle) | |
705 | { | |
706 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
707 | ||
da146d3b | 708 | if (!adev->vce.srbm_soft_reset) |
115933a5 CZ |
709 | return 0; |
710 | ||
711 | mdelay(5); | |
712 | ||
713 | return vce_v3_0_suspend(adev); | |
714 | } | |
715 | ||
716 | ||
717 | static int vce_v3_0_post_soft_reset(void *handle) | |
718 | { | |
719 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
720 | ||
da146d3b | 721 | if (!adev->vce.srbm_soft_reset) |
115933a5 | 722 | return 0; |
5fc3aeeb | 723 | |
aaa36a97 AD |
724 | mdelay(5); |
725 | ||
115933a5 | 726 | return vce_v3_0_resume(adev); |
aaa36a97 AD |
727 | } |
728 | ||
aaa36a97 AD |
729 | static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, |
730 | struct amdgpu_irq_src *source, | |
731 | unsigned type, | |
732 | enum amdgpu_interrupt_state state) | |
733 | { | |
734 | uint32_t val = 0; | |
735 | ||
736 | if (state == AMDGPU_IRQ_STATE_ENABLE) | |
737 | val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; | |
738 | ||
739 | WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); | |
740 | return 0; | |
741 | } | |
742 | ||
743 | static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, | |
744 | struct amdgpu_irq_src *source, | |
745 | struct amdgpu_iv_entry *entry) | |
746 | { | |
747 | DRM_DEBUG("IH: VCE\n"); | |
d6c29c30 | 748 | |
f3f0ea95 | 749 | WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1); |
d6c29c30 | 750 | |
7ccf5aa8 | 751 | switch (entry->src_data[0]) { |
aaa36a97 | 752 | case 0: |
aaa36a97 | 753 | case 1: |
6f0359ff | 754 | case 2: |
7ccf5aa8 | 755 | amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); |
aaa36a97 AD |
756 | break; |
757 | default: | |
758 | DRM_ERROR("Unhandled interrupt: %d %d\n", | |
7ccf5aa8 | 759 | entry->src_id, entry->src_data[0]); |
aaa36a97 AD |
760 | break; |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
5fc3aeeb | 766 | static int vce_v3_0_set_clockgating_state(void *handle, |
767 | enum amd_clockgating_state state) | |
aaa36a97 | 768 | { |
0689a570 | 769 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
a9d4fe2f | 770 | bool enable = (state == AMD_CG_STATE_GATE); |
0689a570 EH |
771 | int i; |
772 | ||
e3b04bc7 | 773 | if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) |
0689a570 EH |
774 | return 0; |
775 | ||
776 | mutex_lock(&adev->grbm_idx_mutex); | |
777 | for (i = 0; i < 2; i++) { | |
778 | /* Program VCE Instance 0 or 1 if not harvested */ | |
779 | if (adev->vce.harvest_config & (1 << i)) | |
780 | continue; | |
781 | ||
50a1ebc7 | 782 | WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i)); |
0689a570 | 783 | |
26679899 | 784 | if (!enable) { |
0689a570 EH |
785 | /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */ |
786 | uint32_t data = RREG32(mmVCE_CLOCK_GATING_A); | |
787 | data &= ~(0xf | 0xff0); | |
788 | data |= ((0x0 << 0) | (0x04 << 4)); | |
789 | WREG32(mmVCE_CLOCK_GATING_A, data); | |
790 | ||
791 | /* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */ | |
792 | data = RREG32(mmVCE_UENC_CLOCK_GATING); | |
793 | data &= ~(0xf | 0xff0); | |
794 | data |= ((0x0 << 0) | (0x04 << 4)); | |
795 | WREG32(mmVCE_UENC_CLOCK_GATING, data); | |
796 | } | |
797 | ||
798 | vce_v3_0_set_vce_sw_clock_gating(adev, enable); | |
799 | } | |
800 | ||
50a1ebc7 | 801 | WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); |
0689a570 EH |
802 | mutex_unlock(&adev->grbm_idx_mutex); |
803 | ||
aaa36a97 AD |
804 | return 0; |
805 | } | |
806 | ||
5fc3aeeb | 807 | static int vce_v3_0_set_powergating_state(void *handle, |
808 | enum amd_powergating_state state) | |
aaa36a97 AD |
809 | { |
810 | /* This doesn't actually powergate the VCE block. | |
811 | * That's done in the dpm code via the SMC. This | |
812 | * just re-inits the block as necessary. The actual | |
813 | * gating still happens in the dpm code. We should | |
814 | * revisit this when there is a cleaner line between | |
815 | * the smc and the hw blocks | |
816 | */ | |
5fc3aeeb | 817 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c79b5561 | 818 | int ret = 0; |
5fc3aeeb | 819 | |
c79b5561 | 820 | if (state == AMD_PG_STATE_GATE) { |
6fc11b0e RZ |
821 | ret = vce_v3_0_stop(adev); |
822 | if (ret) | |
823 | goto out; | |
c79b5561 HR |
824 | } else { |
825 | ret = vce_v3_0_start(adev); | |
826 | if (ret) | |
827 | goto out; | |
c79b5561 HR |
828 | } |
829 | ||
830 | out: | |
831 | return ret; | |
832 | } | |
833 | ||
25faeddc | 834 | static void vce_v3_0_get_clockgating_state(void *handle, u64 *flags) |
c79b5561 HR |
835 | { |
836 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
837 | int data; | |
838 | ||
839 | mutex_lock(&adev->pm.mutex); | |
840 | ||
1c622002 RZ |
841 | if (adev->flags & AMD_IS_APU) |
842 | data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); | |
843 | else | |
844 | data = RREG32_SMC(ixCURRENT_PG_STATUS); | |
845 | ||
846 | if (data & CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) { | |
c79b5561 HR |
847 | DRM_INFO("Cannot get clockgating state when VCE is powergated.\n"); |
848 | goto out; | |
849 | } | |
850 | ||
851 | WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); | |
852 | ||
853 | /* AMD_CG_SUPPORT_VCE_MGCG */ | |
854 | data = RREG32(mmVCE_CLOCK_GATING_A); | |
855 | if (data & (0x04 << 4)) | |
856 | *flags |= AMD_CG_SUPPORT_VCE_MGCG; | |
857 | ||
858 | out: | |
859 | mutex_unlock(&adev->pm.mutex); | |
aaa36a97 AD |
860 | } |
861 | ||
ea4a8c1d | 862 | static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring, |
34955e03 RZ |
863 | struct amdgpu_job *job, |
864 | struct amdgpu_ib *ib, | |
c4c905ec | 865 | uint32_t flags) |
ea4a8c1d | 866 | { |
34955e03 RZ |
867 | unsigned vmid = AMDGPU_JOB_GET_VMID(job); |
868 | ||
ea4a8c1d | 869 | amdgpu_ring_write(ring, VCE_CMD_IB_VM); |
c4f46f22 | 870 | amdgpu_ring_write(ring, vmid); |
ea4a8c1d MSB |
871 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); |
872 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
873 | amdgpu_ring_write(ring, ib->length_dw); | |
874 | } | |
875 | ||
876 | static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring, | |
c633c00b | 877 | unsigned int vmid, uint64_t pd_addr) |
ea4a8c1d MSB |
878 | { |
879 | amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB); | |
c4f46f22 | 880 | amdgpu_ring_write(ring, vmid); |
ea4a8c1d MSB |
881 | amdgpu_ring_write(ring, pd_addr >> 12); |
882 | ||
883 | amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB); | |
c4f46f22 | 884 | amdgpu_ring_write(ring, vmid); |
ea4a8c1d MSB |
885 | amdgpu_ring_write(ring, VCE_CMD_END); |
886 | } | |
887 | ||
888 | static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring) | |
889 | { | |
890 | uint32_t seq = ring->fence_drv.sync_seq; | |
891 | uint64_t addr = ring->fence_drv.gpu_addr; | |
892 | ||
893 | amdgpu_ring_write(ring, VCE_CMD_WAIT_GE); | |
894 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
895 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
896 | amdgpu_ring_write(ring, seq); | |
897 | } | |
898 | ||
a1255107 | 899 | static const struct amd_ip_funcs vce_v3_0_ip_funcs = { |
88a907d6 | 900 | .name = "vce_v3_0", |
aaa36a97 AD |
901 | .early_init = vce_v3_0_early_init, |
902 | .late_init = NULL, | |
903 | .sw_init = vce_v3_0_sw_init, | |
904 | .sw_fini = vce_v3_0_sw_fini, | |
905 | .hw_init = vce_v3_0_hw_init, | |
906 | .hw_fini = vce_v3_0_hw_fini, | |
907 | .suspend = vce_v3_0_suspend, | |
908 | .resume = vce_v3_0_resume, | |
909 | .is_idle = vce_v3_0_is_idle, | |
910 | .wait_for_idle = vce_v3_0_wait_for_idle, | |
115933a5 CZ |
911 | .check_soft_reset = vce_v3_0_check_soft_reset, |
912 | .pre_soft_reset = vce_v3_0_pre_soft_reset, | |
aaa36a97 | 913 | .soft_reset = vce_v3_0_soft_reset, |
115933a5 | 914 | .post_soft_reset = vce_v3_0_post_soft_reset, |
aaa36a97 AD |
915 | .set_clockgating_state = vce_v3_0_set_clockgating_state, |
916 | .set_powergating_state = vce_v3_0_set_powergating_state, | |
c79b5561 | 917 | .get_clockgating_state = vce_v3_0_get_clockgating_state, |
aaa36a97 AD |
918 | }; |
919 | ||
ea4a8c1d | 920 | static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { |
21cd942e | 921 | .type = AMDGPU_RING_TYPE_VCE, |
79887142 CK |
922 | .align_mask = 0xf, |
923 | .nop = VCE_CMD_NO_OP, | |
536fbf94 | 924 | .support_64bit_ptrs = false, |
f61334b5 | 925 | .no_user_fence = true, |
aaa36a97 AD |
926 | .get_rptr = vce_v3_0_ring_get_rptr, |
927 | .get_wptr = vce_v3_0_ring_get_wptr, | |
928 | .set_wptr = vce_v3_0_ring_set_wptr, | |
929 | .parse_cs = amdgpu_vce_ring_parse_cs, | |
e12f3d7a CK |
930 | .emit_frame_size = |
931 | 4 + /* vce_v3_0_emit_pipeline_sync */ | |
932 | 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */ | |
3413accb | 933 | .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */ |
aaa36a97 AD |
934 | .emit_ib = amdgpu_vce_ring_emit_ib, |
935 | .emit_fence = amdgpu_vce_ring_emit_fence, | |
aaa36a97 AD |
936 | .test_ring = amdgpu_vce_ring_test_ring, |
937 | .test_ib = amdgpu_vce_ring_test_ib, | |
edff0e28 | 938 | .insert_nop = amdgpu_ring_insert_nop, |
9e5d5309 | 939 | .pad_ib = amdgpu_ring_generic_pad_ib, |
ebff485e CK |
940 | .begin_use = amdgpu_vce_ring_begin_use, |
941 | .end_use = amdgpu_vce_ring_end_use, | |
aaa36a97 AD |
942 | }; |
943 | ||
ea4a8c1d | 944 | static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { |
21cd942e | 945 | .type = AMDGPU_RING_TYPE_VCE, |
79887142 CK |
946 | .align_mask = 0xf, |
947 | .nop = VCE_CMD_NO_OP, | |
536fbf94 | 948 | .support_64bit_ptrs = false, |
f61334b5 | 949 | .no_user_fence = true, |
ea4a8c1d MSB |
950 | .get_rptr = vce_v3_0_ring_get_rptr, |
951 | .get_wptr = vce_v3_0_ring_get_wptr, | |
952 | .set_wptr = vce_v3_0_ring_set_wptr, | |
98614701 | 953 | .parse_cs = amdgpu_vce_ring_parse_cs_vm, |
e12f3d7a CK |
954 | .emit_frame_size = |
955 | 6 + /* vce_v3_0_emit_vm_flush */ | |
956 | 4 + /* vce_v3_0_emit_pipeline_sync */ | |
957 | 6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */ | |
3413accb | 958 | .emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */ |
ea4a8c1d MSB |
959 | .emit_ib = vce_v3_0_ring_emit_ib, |
960 | .emit_vm_flush = vce_v3_0_emit_vm_flush, | |
961 | .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync, | |
962 | .emit_fence = amdgpu_vce_ring_emit_fence, | |
963 | .test_ring = amdgpu_vce_ring_test_ring, | |
964 | .test_ib = amdgpu_vce_ring_test_ib, | |
965 | .insert_nop = amdgpu_ring_insert_nop, | |
966 | .pad_ib = amdgpu_ring_generic_pad_ib, | |
967 | .begin_use = amdgpu_vce_ring_begin_use, | |
968 | .end_use = amdgpu_vce_ring_end_use, | |
969 | }; | |
970 | ||
aaa36a97 AD |
971 | static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) |
972 | { | |
75c65480 AD |
973 | int i; |
974 | ||
ea4a8c1d | 975 | if (adev->asic_type >= CHIP_STONEY) { |
5d4af988 | 976 | for (i = 0; i < adev->vce.num_rings; i++) { |
ea4a8c1d | 977 | adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs; |
5d4af988 AD |
978 | adev->vce.ring[i].me = i; |
979 | } | |
ea4a8c1d MSB |
980 | DRM_INFO("VCE enabled in VM mode\n"); |
981 | } else { | |
5d4af988 | 982 | for (i = 0; i < adev->vce.num_rings; i++) { |
ea4a8c1d | 983 | adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs; |
5d4af988 AD |
984 | adev->vce.ring[i].me = i; |
985 | } | |
ea4a8c1d MSB |
986 | DRM_INFO("VCE enabled in physical mode\n"); |
987 | } | |
aaa36a97 AD |
988 | } |
989 | ||
990 | static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = { | |
991 | .set = vce_v3_0_set_interrupt_state, | |
992 | .process = vce_v3_0_process_interrupt, | |
993 | }; | |
994 | ||
995 | static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev) | |
996 | { | |
997 | adev->vce.irq.num_types = 1; | |
998 | adev->vce.irq.funcs = &vce_v3_0_irq_funcs; | |
999 | }; | |
a1255107 AD |
1000 | |
1001 | const struct amdgpu_ip_block_version vce_v3_0_ip_block = | |
1002 | { | |
1003 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1004 | .major = 3, | |
1005 | .minor = 0, | |
1006 | .rev = 0, | |
1007 | .funcs = &vce_v3_0_ip_funcs, | |
1008 | }; | |
1009 | ||
1010 | const struct amdgpu_ip_block_version vce_v3_1_ip_block = | |
1011 | { | |
1012 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1013 | .major = 3, | |
1014 | .minor = 1, | |
1015 | .rev = 0, | |
1016 | .funcs = &vce_v3_0_ip_funcs, | |
1017 | }; | |
1018 | ||
1019 | const struct amdgpu_ip_block_version vce_v3_4_ip_block = | |
1020 | { | |
1021 | .type = AMD_IP_BLOCK_TYPE_VCE, | |
1022 | .major = 3, | |
1023 | .minor = 4, | |
1024 | .rev = 0, | |
1025 | .funcs = &vce_v3_0_ip_funcs, | |
1026 | }; |