[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / vce_v2_0.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * Authors: Christian König <christian.koenig@amd.com>
 */

#include <linux/firmware.h>
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_vce.h"
#include "cikd.h"
#include "vce/vce_2_0_d.h"
#include "vce/vce_2_0_sh_mask.h"
#include "smu/smu_7_0_1_d.h"
#include "smu/smu_7_0_1_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"

#define VCE_V2_0_FW_SIZE	(256 * 1024)
#define VCE_V2_0_STACK_SIZE	(64 * 1024)
#define VCE_V2_0_DATA_SIZE	(23552 * AMDGPU_MAX_VCE_HANDLES)
#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK	0x02

static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
static int vce_v2_0_wait_for_idle(void *handle);
/**
 * vce_v2_0_ring_get_rptr - get read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware read pointer
 */
static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		return RREG32(mmVCE_RB_RPTR);
	else
		return RREG32(mmVCE_RB_RPTR2);
}

/**
 * vce_v2_0_ring_get_wptr - get write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware write pointer
 */
static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		return RREG32(mmVCE_RB_WPTR);
	else
		return RREG32(mmVCE_RB_WPTR2);
}

/**
 * vce_v2_0_ring_set_wptr - set write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the write pointer to the hardware
 */
static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		WREG32(mmVCE_RB_WPTR, ring->wptr);
	else
		WREG32(mmVCE_RB_WPTR2, ring->wptr);
}

static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
{
	int i, j;

	for (i = 0; i < 10; ++i) {
		for (j = 0; j < 100; ++j) {
			uint32_t status = RREG32(mmVCE_LMI_STATUS);

			if (status & 0x337f)
				return 0;
			mdelay(10);
		}
	}

	return -ETIMEDOUT;
}

static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
{
	int i, j;

	for (i = 0; i < 10; ++i) {
		for (j = 0; j < 100; ++j) {
			uint32_t status = RREG32(mmVCE_STATUS);

			if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
				return 0;
			mdelay(10);
		}

		DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
		WREG32_P(mmVCE_SOFT_RESET,
			VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
			~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(10);
		WREG32_P(mmVCE_SOFT_RESET, 0,
			~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(10);
	}

	return -ETIMEDOUT;
}

/**
 * vce_v2_0_start - start VCE block
 *
 * @adev: amdgpu_device pointer
 *
 * Setup and start the VCE block
 */
static int vce_v2_0_start(struct amdgpu_device *adev)
{
	struct amdgpu_ring *ring;
	int r;

	vce_v2_0_mc_resume(adev);

	/* set BUSY flag */
	WREG32_P(mmVCE_STATUS, 1, ~1);

	ring = &adev->vce.ring[0];
	WREG32(mmVCE_RB_RPTR, ring->wptr);
	WREG32(mmVCE_RB_WPTR, ring->wptr);
	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);

	ring = &adev->vce.ring[1];
	WREG32(mmVCE_RB_RPTR2, ring->wptr);
	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);

	WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
	mdelay(100);
	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);

	r = vce_v2_0_firmware_loaded(adev);

	/* clear BUSY flag */
	WREG32_P(mmVCE_STATUS, 0, ~1);

	if (r) {
		DRM_ERROR("VCE not responding, giving up!!!\n");
		return r;
	}

	return 0;
}

static int vce_v2_0_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	adev->vce.num_rings = 2;

	vce_v2_0_set_ring_funcs(adev);
	vce_v2_0_set_irq_funcs(adev);

	return 0;
}

static int vce_v2_0_sw_init(void *handle)
{
	struct amdgpu_ring *ring;
	int r, i;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* VCE */
	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
	if (r)
		return r;

	r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
		VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
	if (r)
		return r;

	r = amdgpu_vce_resume(adev);
	if (r)
		return r;

	for (i = 0; i < adev->vce.num_rings; i++) {
		ring = &adev->vce.ring[i];
		sprintf(ring->name, "vce%d", i);
		r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
				     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
		if (r)
			return r;
	}

	return r;
}

static int vce_v2_0_sw_fini(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_vce_suspend(adev);
	if (r)
		return r;

	r = amdgpu_vce_sw_fini(adev);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_hw_init(void *handle)
{
	int r, i;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = vce_v2_0_start(adev);
	/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
	if (r)
		return 0;

	for (i = 0; i < adev->vce.num_rings; i++)
		adev->vce.ring[i].ready = false;

	for (i = 0; i < adev->vce.num_rings; i++) {
		r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
		if (r)
			return r;
		else
			adev->vce.ring[i].ready = true;
	}

	DRM_INFO("VCE initialized successfully.\n");

	return 0;
}

static int vce_v2_0_hw_fini(void *handle)
{
	return 0;
}

static int vce_v2_0_suspend(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = vce_v2_0_hw_fini(adev);
	if (r)
		return r;

	r = amdgpu_vce_suspend(adev);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_resume(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_vce_resume(adev);
	if (r)
		return r;

	r = vce_v2_0_hw_init(adev);
	if (r)
		return r;

	return r;
}

static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
{
	u32 tmp;

	if (gated) {
		tmp = RREG32(mmVCE_CLOCK_GATING_B);
		tmp |= 0xe70000;
		WREG32(mmVCE_CLOCK_GATING_B, tmp);

		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
		tmp |= 0xff000000;
		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
		tmp &= ~0x3fc;
		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	} else {
		tmp = RREG32(mmVCE_CLOCK_GATING_B);
		tmp |= 0xe7;
		tmp &= ~0xe70000;
		WREG32(mmVCE_CLOCK_GATING_B, tmp);

		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
		tmp |= 0x1fe000;
		tmp &= ~0xff000000;
		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
		tmp |= 0x3fc;
		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	}
}

static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
{
	if (vce_v2_0_wait_for_idle(adev)) {
		DRM_INFO("VCE is busy, Can't set clock gateing");
		return;
	}

	WREG32_P(mmVCE_LMI_CTRL2, 0x100, ~0x100);

	if (vce_v2_0_lmi_clean(adev)) {
		DRM_INFO("LMI is busy, Can't set clock gateing");
		return;
	}

	WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	WREG32_P(mmVCE_SOFT_RESET,
		 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
		 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	WREG32(mmVCE_STATUS, 0);

	if (gated)
		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	/* LMI_MC/LMI_UMC always set in dynamic, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0} */
	if (gated) {
		/* Force CLOCK OFF , set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {*, 1} */
		WREG32(mmVCE_CLOCK_GATING_B, 0xe90010);
	} else {
		/* Force CLOCK ON, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {1, 0} */
		WREG32(mmVCE_CLOCK_GATING_B, 0x800f1);
	}

	/* Set VCE_UENC_CLOCK_GATING always in dynamic mode {*_FORCE_ON, *_FORCE_OFF} = {0, 0}*/;
	WREG32(mmVCE_UENC_CLOCK_GATING, 0x40);

	/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
	WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);

	WREG32_P(mmVCE_LMI_CTRL2, 0, ~0x100);
	if(!gated) {
		WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
		mdelay(100);
		WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);

		vce_v2_0_firmware_loaded(adev);
		WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
	}
}

static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
{
	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
}

static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
{
	bool sw_cg = false;

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
		if (sw_cg)
			vce_v2_0_set_sw_cg(adev, true);
		else
			vce_v2_0_set_dyn_cg(adev, true);
	} else {
		vce_v2_0_disable_cg(adev);

		if (sw_cg)
			vce_v2_0_set_sw_cg(adev, false);
		else
			vce_v2_0_set_dyn_cg(adev, false);
	}
}

static void vce_v2_0_init_cg(struct amdgpu_device *adev)
{
	u32 tmp;

	tmp = RREG32(mmVCE_CLOCK_GATING_A);
	tmp &= ~0xfff;
	tmp |= ((0 << 0) | (4 << 4));
	tmp |= 0x40000;
	WREG32(mmVCE_CLOCK_GATING_A, tmp);

	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	tmp &= ~0xfff;
	tmp |= ((0 << 0) | (4 << 4));
	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	tmp |= 0x10;
	tmp &= ~0x100000;
	WREG32(mmVCE_CLOCK_GATING_B, tmp);
}

static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
{
	uint64_t addr = adev->vce.gpu_addr;
	uint32_t size;

	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);

	WREG32(mmVCE_LMI_CTRL, 0x00398000);
	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
	WREG32(mmVCE_LMI_VM_CTRL, 0);

	addr += AMDGPU_VCE_FIRMWARE_OFFSET;
	size = VCE_V2_0_FW_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);

	addr += size;
	size = VCE_V2_0_STACK_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);

	addr += size;
	size = VCE_V2_0_DATA_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);

	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
	WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);

	vce_v2_0_init_cg(adev);
}

static bool vce_v2_0_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
}

static int vce_v2_0_wait_for_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	unsigned i;

	for (i = 0; i < adev->usec_timeout; i++) {
		if (vce_v2_0_is_idle(handle))
			return 0;
	}
	return -ETIMEDOUT;
}

static int vce_v2_0_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
	mdelay(5);

	return vce_v2_0_start(adev);
}

static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					unsigned type,
					enum amdgpu_interrupt_state state)
{
	uint32_t val = 0;

	if (state == AMDGPU_IRQ_STATE_ENABLE)
		val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;

	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
	return 0;
}

static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{
	DRM_DEBUG("IH: VCE\n");
	switch (entry->src_data) {
	case 0:
	case 1:
		amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
		break;
	default:
		DRM_ERROR("Unhandled interrupt: %d %d\n",
			  entry->src_id, entry->src_data);
		break;
	}

	return 0;
}

static void vce_v2_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
{
	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);

	if (enable)
		tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
	else
		tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;

	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
}


static int vce_v2_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	bool gate = false;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;


	vce_v2_0_set_bypass_mode(adev, enable);

	if (state == AMD_CG_STATE_GATE)
		gate = true;

	vce_v2_0_enable_mgcg(adev, gate);

	return 0;
}

static int vce_v2_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	/* This doesn't actually powergate the VCE block.
	 * That's done in the dpm code via the SMC.  This
	 * just re-inits the block as necessary.  The actual
	 * gating still happens in the dpm code.  We should
	 * revisit this when there is a cleaner line between
	 * the smc and the hw blocks
	 */
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
		return 0;

	if (state == AMD_PG_STATE_GATE)
		/* XXX do we need a vce_v2_0_stop()? */
		return 0;
	else
		return vce_v2_0_start(adev);
}

const struct amd_ip_funcs vce_v2_0_ip_funcs = {
	.name = "vce_v2_0",
	.early_init = vce_v2_0_early_init,
	.late_init = NULL,
	.sw_init = vce_v2_0_sw_init,
	.sw_fini = vce_v2_0_sw_fini,
	.hw_init = vce_v2_0_hw_init,
	.hw_fini = vce_v2_0_hw_fini,
	.suspend = vce_v2_0_suspend,
	.resume = vce_v2_0_resume,
	.is_idle = vce_v2_0_is_idle,
	.wait_for_idle = vce_v2_0_wait_for_idle,
	.soft_reset = vce_v2_0_soft_reset,
	.set_clockgating_state = vce_v2_0_set_clockgating_state,
	.set_powergating_state = vce_v2_0_set_powergating_state,
};

static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
	.get_rptr = vce_v2_0_ring_get_rptr,
	.get_wptr = vce_v2_0_ring_get_wptr,
	.set_wptr = vce_v2_0_ring_set_wptr,
	.parse_cs = amdgpu_vce_ring_parse_cs,
	.emit_ib = amdgpu_vce_ring_emit_ib,
	.emit_fence = amdgpu_vce_ring_emit_fence,
	.test_ring = amdgpu_vce_ring_test_ring,
	.test_ib = amdgpu_vce_ring_test_ib,
	.insert_nop = amdgpu_ring_insert_nop,
	.pad_ib = amdgpu_ring_generic_pad_ib,
	.begin_use = amdgpu_vce_ring_begin_use,
	.end_use = amdgpu_vce_ring_end_use,
	.get_emit_ib_size = amdgpu_vce_ring_get_emit_ib_size,
	.get_dma_frame_size = amdgpu_vce_ring_get_dma_frame_size,
};

static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
{
	int i;

	for (i = 0; i < adev->vce.num_rings; i++)
		adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;
}

static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
	.set = vce_v2_0_set_interrupt_state,
	.process = vce_v2_0_process_interrupt,
};

static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
{
	adev->vce.irq.num_types = 1;
	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
};
Commit	Line	Data
a2e73f56 AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	* Authors: Christian König <christian.koenig@amd.com>
	26	*/
	27
	28	#include <linux/firmware.h>
	29	#include <drm/drmP.h>
	30	#include "amdgpu.h"
	31	#include "amdgpu_vce.h"
	32	#include "cikd.h"
a2e73f56 AD	33	#include "vce/vce_2_0_d.h"
a2e73f56 AD	34	#include "vce/vce_2_0_sh_mask.h"
cbb2fe8e RZ	35	#include "smu/smu_7_0_1_d.h"
cbb2fe8e RZ	36	#include "smu/smu_7_0_1_sh_mask.h"
a2e73f56 AD	37	#include "oss/oss_2_0_d.h"
	38	#include "oss/oss_2_0_sh_mask.h"
	39
e9822622 LL	40	#define VCE_V2_0_FW_SIZE (256 * 1024)
	41	#define VCE_V2_0_STACK_SIZE (64 * 1024)
	42	#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
abc8c1ce	43	#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
e9822622	44
a2e73f56 AD	45	static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
	46	static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
	47	static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
cb48a13e	48	static int vce_v2_0_wait_for_idle(void *handle);
a2e73f56 AD	49	/**
	50	* vce_v2_0_ring_get_rptr - get read pointer
	51	*
	52	* @ring: amdgpu_ring pointer
	53	*
	54	* Returns the current hardware read pointer
	55	*/
	56	static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
	57	{
	58	struct amdgpu_device *adev = ring->adev;
	59
	60	if (ring == &adev->vce.ring[0])
	61	return RREG32(mmVCE_RB_RPTR);
	62	else
	63	return RREG32(mmVCE_RB_RPTR2);
	64	}
	65
	66	/**
	67	* vce_v2_0_ring_get_wptr - get write pointer
	68	*
	69	* @ring: amdgpu_ring pointer
	70	*
	71	* Returns the current hardware write pointer
	72	*/
	73	static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
	74	{
	75	struct amdgpu_device *adev = ring->adev;
	76
	77	if (ring == &adev->vce.ring[0])
	78	return RREG32(mmVCE_RB_WPTR);
	79	else
	80	return RREG32(mmVCE_RB_WPTR2);
	81	}
	82
	83	/**
	84	* vce_v2_0_ring_set_wptr - set write pointer
	85	*
	86	* @ring: amdgpu_ring pointer
	87	*
	88	* Commits the write pointer to the hardware
	89	*/
	90	static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
	91	{
	92	struct amdgpu_device *adev = ring->adev;
	93
	94	if (ring == &adev->vce.ring[0])
	95	WREG32(mmVCE_RB_WPTR, ring->wptr);
	96	else
	97	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	98	}
	99
abc8c1ce	100	static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
	101	{
	102	int i, j;
	103
	104	for (i = 0; i < 10; ++i) {
	105	for (j = 0; j < 100; ++j) {
	106	uint32_t status = RREG32(mmVCE_LMI_STATUS);
	107
	108	if (status & 0x337f)
	109	return 0;
	110	mdelay(10);
	111	}
	112	}
	113
	114	return -ETIMEDOUT;
	115	}
	116
	117	static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
	118	{
	119	int i, j;
	120
	121	for (i = 0; i < 10; ++i) {
	122	for (j = 0; j < 100; ++j) {
	123	uint32_t status = RREG32(mmVCE_STATUS);
	124
	125	if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
	126	return 0;
	127	mdelay(10);
	128	}
	129
	130	DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
	131	WREG32_P(mmVCE_SOFT_RESET,
	132	VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
	133	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	134	mdelay(10);
	135	WREG32_P(mmVCE_SOFT_RESET, 0,
	136	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	137	mdelay(10);
	138	}
	139
	140	return -ETIMEDOUT;
	141	}
	142
a2e73f56 AD	143	/**
	144	* vce_v2_0_start - start VCE block
	145	*
	146	* @adev: amdgpu_device pointer
	147	*
	148	* Setup and start the VCE block
	149	*/
	150	static int vce_v2_0_start(struct amdgpu_device *adev)
	151	{
	152	struct amdgpu_ring *ring;
abc8c1ce	153	int r;
a2e73f56 AD	154
	155	vce_v2_0_mc_resume(adev);
	156
	157	/* set BUSY flag */
	158	WREG32_P(mmVCE_STATUS, 1, ~1);
	159
	160	ring = &adev->vce.ring[0];
	161	WREG32(mmVCE_RB_RPTR, ring->wptr);
	162	WREG32(mmVCE_RB_WPTR, ring->wptr);
	163	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
	164	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
	165	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
	166
	167	ring = &adev->vce.ring[1];
	168	WREG32(mmVCE_RB_RPTR2, ring->wptr);
	169	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	170	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
	171	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
	172	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
	173
21d3cbbe TSD	174	WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
21d3cbbe TSD	175	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
a2e73f56	176	mdelay(100);
21d3cbbe	177	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
a2e73f56	178
abc8c1ce	179	r = vce_v2_0_firmware_loaded(adev);
a2e73f56 AD	180
	181	/* clear BUSY flag */
	182	WREG32_P(mmVCE_STATUS, 0, ~1);
	183
	184	if (r) {
	185	DRM_ERROR("VCE not responding, giving up!!!\n");
	186	return r;
	187	}
	188
	189	return 0;
	190	}
	191
5fc3aeeb	192	static int vce_v2_0_early_init(void *handle)
a2e73f56	193	{
5fc3aeeb	194	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	195
75c65480 AD	196	adev->vce.num_rings = 2;
75c65480 AD	197
a2e73f56 AD	198	vce_v2_0_set_ring_funcs(adev);
	199	vce_v2_0_set_irq_funcs(adev);
	200
	201	return 0;
	202	}
	203
5fc3aeeb	204	static int vce_v2_0_sw_init(void *handle)
a2e73f56 AD	205	{
a2e73f56 AD	206	struct amdgpu_ring *ring;
75c65480	207	int r, i;
5fc3aeeb	208	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	209
	210	/* VCE */
	211	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
	212	if (r)
	213	return r;
	214
e9822622 LL	215	r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
e9822622 LL	216	VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
a2e73f56 AD	217	if (r)
	218	return r;
	219
	220	r = amdgpu_vce_resume(adev);
	221	if (r)
	222	return r;
	223
75c65480 AD	224	for (i = 0; i < adev->vce.num_rings; i++) {
	225	ring = &adev->vce.ring[i];
	226	sprintf(ring->name, "vce%d", i);
	227	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
	228	&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	229	if (r)
	230	return r;
	231	}
a2e73f56 AD	232
	233	return r;
	234	}
	235
5fc3aeeb	236	static int vce_v2_0_sw_fini(void *handle)
a2e73f56 AD	237	{
a2e73f56 AD	238	int r;
5fc3aeeb	239	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	240
	241	r = amdgpu_vce_suspend(adev);
	242	if (r)
	243	return r;
	244
	245	r = amdgpu_vce_sw_fini(adev);
	246	if (r)
	247	return r;
	248
	249	return r;
	250	}
	251
5fc3aeeb	252	static int vce_v2_0_hw_init(void *handle)
a2e73f56	253	{
75c65480	254	int r, i;
5fc3aeeb	255	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	256
a2e73f56 AD	257	r = vce_v2_0_start(adev);
75c65480	258	/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
a2e73f56	259	if (r)
976accc1	260	return 0;
a2e73f56	261
75c65480 AD	262	for (i = 0; i < adev->vce.num_rings; i++)
75c65480 AD	263	adev->vce.ring[i].ready = false;
a2e73f56	264
75c65480 AD	265	for (i = 0; i < adev->vce.num_rings; i++) {
	266	r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
	267	if (r)
	268	return r;
	269	else
	270	adev->vce.ring[i].ready = true;
a2e73f56 AD	271	}
	272
	273	DRM_INFO("VCE initialized successfully.\n");
	274
	275	return 0;
	276	}
	277
5fc3aeeb	278	static int vce_v2_0_hw_fini(void *handle)
a2e73f56	279	{
a2e73f56 AD	280	return 0;
	281	}
	282
5fc3aeeb	283	static int vce_v2_0_suspend(void *handle)
a2e73f56 AD	284	{
a2e73f56 AD	285	int r;
5fc3aeeb	286	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	287
	288	r = vce_v2_0_hw_fini(adev);
	289	if (r)
	290	return r;
	291
	292	r = amdgpu_vce_suspend(adev);
	293	if (r)
	294	return r;
	295
	296	return r;
	297	}
	298
5fc3aeeb	299	static int vce_v2_0_resume(void *handle)
a2e73f56 AD	300	{
a2e73f56 AD	301	int r;
5fc3aeeb	302	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	303
	304	r = amdgpu_vce_resume(adev);
	305	if (r)
	306	return r;
	307
	308	r = vce_v2_0_hw_init(adev);
	309	if (r)
	310	return r;
	311
	312	return r;
	313	}
	314
	315	static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
	316	{
	317	u32 tmp;
	318
	319	if (gated) {
	320	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	321	tmp \|= 0xe70000;
	322	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	323
	324	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	325	tmp \|= 0xff000000;
	326	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	327
	328	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	329	tmp &= ~0x3fc;
	330	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	331
	332	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
70f0f5fb	333	} else {
a2e73f56 AD	334	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	335	tmp \|= 0xe7;
	336	tmp &= ~0xe70000;
	337	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	338
	339	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	340	tmp \|= 0x1fe000;
	341	tmp &= ~0xff000000;
	342	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	343
	344	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	345	tmp \|= 0x3fc;
	346	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	347	}
	348	}
	349
	350	static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
	351	{
abc8c1ce	352	if (vce_v2_0_wait_for_idle(adev)) {
	353	DRM_INFO("VCE is busy, Can't set clock gateing");
	354	return;
	355	}
a2e73f56	356
abc8c1ce	357	WREG32_P(mmVCE_LMI_CTRL2, 0x100, ~0x100);
	358
	359	if (vce_v2_0_lmi_clean(adev)) {
	360	DRM_INFO("LMI is busy, Can't set clock gateing");
	361	return;
cb48a13e RZ	362	}
cb48a13e RZ	363
abc8c1ce	364	WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	365	WREG32_P(mmVCE_SOFT_RESET,
	366	VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
	367	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	368	WREG32(mmVCE_STATUS, 0);
	369
	370	if (gated)
	371	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	372	/* LMI_MC/LMI_UMC always set in dynamic, set {CGC__GATE_MODE, CGC__SW_GATE} = {0, 0} */
a2e73f56	373	if (gated) {
abc8c1ce	374	/* Force CLOCK OFF , set {CGC__GATE_MODE, CGC__SW_GATE} = {, 1} /
abc8c1ce	375	WREG32(mmVCE_CLOCK_GATING_B, 0xe90010);
a2e73f56	376	} else {
abc8c1ce	377	/* Force CLOCK ON, set {CGC__GATE_MODE, CGC__SW_GATE} = {1, 0} */
abc8c1ce	378	WREG32(mmVCE_CLOCK_GATING_B, 0x800f1);
a2e73f56	379	}
a2e73f56	380
abc8c1ce	381	/* Set VCE_UENC_CLOCK_GATING always in dynamic mode {_FORCE_ON, _FORCE_OFF} = {0, 0}*/;
abc8c1ce	382	WREG32(mmVCE_UENC_CLOCK_GATING, 0x40);
a2e73f56	383
abc8c1ce	384	/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
abc8c1ce	385	WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
a2e73f56	386
abc8c1ce	387	WREG32_P(mmVCE_LMI_CTRL2, 0, ~0x100);
	388	if(!gated) {
	389	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	390	mdelay(100);
	391	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	392
	393	vce_v2_0_firmware_loaded(adev);
	394	WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
	395	}
a2e73f56 AD	396	}
	397
	398	static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
	399	{
	400	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
	401	}
	402
	403	static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
	404	{
	405	bool sw_cg = false;
	406
e3b04bc7	407	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
a2e73f56 AD	408	if (sw_cg)
	409	vce_v2_0_set_sw_cg(adev, true);
	410	else
	411	vce_v2_0_set_dyn_cg(adev, true);
	412	} else {
	413	vce_v2_0_disable_cg(adev);
	414
	415	if (sw_cg)
	416	vce_v2_0_set_sw_cg(adev, false);
	417	else
	418	vce_v2_0_set_dyn_cg(adev, false);
	419	}
	420	}
	421
	422	static void vce_v2_0_init_cg(struct amdgpu_device *adev)
	423	{
	424	u32 tmp;
	425
	426	tmp = RREG32(mmVCE_CLOCK_GATING_A);
	427	tmp &= ~0xfff;
	428	tmp \|= ((0 << 0) \| (4 << 4));
	429	tmp \|= 0x40000;
	430	WREG32(mmVCE_CLOCK_GATING_A, tmp);
	431
	432	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	433	tmp &= ~0xfff;
	434	tmp \|= ((0 << 0) \| (4 << 4));
	435	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	436
	437	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	438	tmp \|= 0x10;
	439	tmp &= ~0x100000;
	440	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	441	}
	442
	443	static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
	444	{
	445	uint64_t addr = adev->vce.gpu_addr;
	446	uint32_t size;
	447
	448	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
	449	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
	450	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
	451	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
	452
	453	WREG32(mmVCE_LMI_CTRL, 0x00398000);
	454	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
	455	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
	456	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
	457	WREG32(mmVCE_LMI_VM_CTRL, 0);
	458
	459	addr += AMDGPU_VCE_FIRMWARE_OFFSET;
e9822622	460	size = VCE_V2_0_FW_SIZE;
a2e73f56 AD	461	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
	462	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
	463
	464	addr += size;
e9822622	465	size = VCE_V2_0_STACK_SIZE;
a2e73f56 AD	466	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
	467	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
	468
	469	addr += size;
e9822622	470	size = VCE_V2_0_DATA_SIZE;
a2e73f56 AD	471	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
	472	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
	473
	474	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
21d3cbbe	475	WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
a2e73f56 AD	476
	477	vce_v2_0_init_cg(adev);
	478	}
	479
5fc3aeeb	480	static bool vce_v2_0_is_idle(void *handle)
a2e73f56	481	{
5fc3aeeb	482	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	483
a2e73f56 AD	484	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
	485	}
	486
5fc3aeeb	487	static int vce_v2_0_wait_for_idle(void *handle)
a2e73f56	488	{
5fc3aeeb	489	struct amdgpu_device adev = (struct amdgpu_device )handle;
21d3cbbe	490	unsigned i;
a2e73f56 AD	491
a2e73f56 AD	492	for (i = 0; i < adev->usec_timeout; i++) {
21d3cbbe	493	if (vce_v2_0_is_idle(handle))
a2e73f56 AD	494	return 0;
	495	}
	496	return -ETIMEDOUT;
	497	}
	498
5fc3aeeb	499	static int vce_v2_0_soft_reset(void *handle)
a2e73f56	500	{
5fc3aeeb	501	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	502
21d3cbbe	503	WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
a2e73f56 AD	504	mdelay(5);
	505
	506	return vce_v2_0_start(adev);
	507	}
	508
a2e73f56 AD	509	static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
	510	struct amdgpu_irq_src *source,
	511	unsigned type,
	512	enum amdgpu_interrupt_state state)
	513	{
	514	uint32_t val = 0;
	515
	516	if (state == AMDGPU_IRQ_STATE_ENABLE)
	517	val \|= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
	518
	519	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
	520	return 0;
	521	}
	522
	523	static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
	524	struct amdgpu_irq_src *source,
	525	struct amdgpu_iv_entry *entry)
	526	{
	527	DRM_DEBUG("IH: VCE\n");
	528	switch (entry->src_data) {
	529	case 0:
a2e73f56	530	case 1:
21d3cbbe	531	amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
a2e73f56 AD	532	break;
	533	default:
	534	DRM_ERROR("Unhandled interrupt: %d %d\n",
	535	entry->src_id, entry->src_data);
	536	break;
	537	}
	538
	539	return 0;
	540	}
	541
cbb2fe8e RZ	542	static void vce_v2_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
	543	{
	544	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
	545
	546	if (enable)
	547	tmp \|= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
	548	else
	549	tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
	550
	551	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
	552	}
	553
	554
5fc3aeeb	555	static int vce_v2_0_set_clockgating_state(void *handle,
5fc3aeeb	556	enum amd_clockgating_state state)
a2e73f56 AD	557	{
a2e73f56 AD	558	bool gate = false;
5fc3aeeb	559	struct amdgpu_device adev = (struct amdgpu_device )handle;
cbb2fe8e RZ	560	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
	561
	562
	563	vce_v2_0_set_bypass_mode(adev, enable);
a2e73f56	564
5fc3aeeb	565	if (state == AMD_CG_STATE_GATE)
a2e73f56 AD	566	gate = true;
	567
	568	vce_v2_0_enable_mgcg(adev, gate);
	569
	570	return 0;
	571	}
	572
5fc3aeeb	573	static int vce_v2_0_set_powergating_state(void *handle,
5fc3aeeb	574	enum amd_powergating_state state)
a2e73f56 AD	575	{
	576	/* This doesn't actually powergate the VCE block.
	577	* That's done in the dpm code via the SMC. This
	578	* just re-inits the block as necessary. The actual
	579	* gating still happens in the dpm code. We should
	580	* revisit this when there is a cleaner line between
	581	* the smc and the hw blocks
	582	*/
5fc3aeeb	583	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	584
e3b04bc7	585	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
808a934f AD	586	return 0;
808a934f AD	587
5fc3aeeb	588	if (state == AMD_PG_STATE_GATE)
a2e73f56 AD	589	/* XXX do we need a vce_v2_0_stop()? */
	590	return 0;
	591	else
	592	return vce_v2_0_start(adev);
	593	}
	594
5fc3aeeb	595	const struct amd_ip_funcs vce_v2_0_ip_funcs = {
88a907d6	596	.name = "vce_v2_0",
a2e73f56 AD	597	.early_init = vce_v2_0_early_init,
	598	.late_init = NULL,
	599	.sw_init = vce_v2_0_sw_init,
	600	.sw_fini = vce_v2_0_sw_fini,
	601	.hw_init = vce_v2_0_hw_init,
	602	.hw_fini = vce_v2_0_hw_fini,
	603	.suspend = vce_v2_0_suspend,
	604	.resume = vce_v2_0_resume,
	605	.is_idle = vce_v2_0_is_idle,
	606	.wait_for_idle = vce_v2_0_wait_for_idle,
	607	.soft_reset = vce_v2_0_soft_reset,
a2e73f56 AD	608	.set_clockgating_state = vce_v2_0_set_clockgating_state,
	609	.set_powergating_state = vce_v2_0_set_powergating_state,
	610	};
	611
	612	static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
	613	.get_rptr = vce_v2_0_ring_get_rptr,
	614	.get_wptr = vce_v2_0_ring_get_wptr,
	615	.set_wptr = vce_v2_0_ring_set_wptr,
	616	.parse_cs = amdgpu_vce_ring_parse_cs,
	617	.emit_ib = amdgpu_vce_ring_emit_ib,
	618	.emit_fence = amdgpu_vce_ring_emit_fence,
a2e73f56 AD	619	.test_ring = amdgpu_vce_ring_test_ring,
a2e73f56 AD	620	.test_ib = amdgpu_vce_ring_test_ib,
edff0e28	621	.insert_nop = amdgpu_ring_insert_nop,
9e5d5309	622	.pad_ib = amdgpu_ring_generic_pad_ib,
ebff485e CK	623	.begin_use = amdgpu_vce_ring_begin_use,
ebff485e CK	624	.end_use = amdgpu_vce_ring_end_use,
9d6b7a64 AD	625	.get_emit_ib_size = amdgpu_vce_ring_get_emit_ib_size,
9d6b7a64 AD	626	.get_dma_frame_size = amdgpu_vce_ring_get_dma_frame_size,
a2e73f56 AD	627	};
	628
	629	static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
	630	{
75c65480 AD	631	int i;
	632
	633	for (i = 0; i < adev->vce.num_rings; i++)
	634	adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;
a2e73f56 AD	635	}
	636
	637	static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
	638	.set = vce_v2_0_set_interrupt_state,
	639	.process = vce_v2_0_process_interrupt,
	640	};
	641
	642	static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
	643	{
	644	adev->vce.irq.num_types = 1;
	645	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
	646	};