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09bfb891 LL |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_uvd.h" | |
9096d6e5 | 28 | #include "soc15.h" |
09bfb891 LL |
29 | #include "soc15d.h" |
30 | #include "soc15_common.h" | |
247ac951 | 31 | #include "mmsch_v1_0.h" |
09bfb891 | 32 | |
5d735f83 FX |
33 | #include "uvd/uvd_7_0_offset.h" |
34 | #include "uvd/uvd_7_0_sh_mask.h" | |
18297a21 FX |
35 | #include "vce/vce_4_0_offset.h" |
36 | #include "vce/vce_4_0_default.h" | |
37 | #include "vce/vce_4_0_sh_mask.h" | |
daad67b5 | 38 | #include "nbif/nbif_6_1_offset.h" |
75199b8c | 39 | #include "hdp/hdp_4_0_offset.h" |
65417d9f FX |
40 | #include "mmhub/mmhub_1_0_offset.h" |
41 | #include "mmhub/mmhub_1_0_sh_mask.h" | |
44a99b65 | 42 | #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" |
09bfb891 | 43 | |
9181dba6 JZ |
44 | #define UVD7_MAX_HW_INSTANCES_VEGA20 2 |
45 | ||
09bfb891 LL |
46 | static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); |
47 | static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); | |
48 | static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); | |
49 | static int uvd_v7_0_start(struct amdgpu_device *adev); | |
50 | static void uvd_v7_0_stop(struct amdgpu_device *adev); | |
247ac951 | 51 | static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); |
09bfb891 | 52 | |
b53a6ebc JZ |
53 | static int amdgpu_ih_clientid_uvds[] = { |
54 | SOC15_IH_CLIENTID_UVD, | |
55 | SOC15_IH_CLIENTID_UVD1 | |
56 | }; | |
57 | ||
09bfb891 LL |
58 | /** |
59 | * uvd_v7_0_ring_get_rptr - get read pointer | |
60 | * | |
61 | * @ring: amdgpu_ring pointer | |
62 | * | |
63 | * Returns the current hardware read pointer | |
64 | */ | |
65 | static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) | |
66 | { | |
67 | struct amdgpu_device *adev = ring->adev; | |
68 | ||
10dd74ea | 69 | return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); |
09bfb891 LL |
70 | } |
71 | ||
72 | /** | |
73 | * uvd_v7_0_enc_ring_get_rptr - get enc read pointer | |
74 | * | |
75 | * @ring: amdgpu_ring pointer | |
76 | * | |
77 | * Returns the current hardware enc read pointer | |
78 | */ | |
79 | static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) | |
80 | { | |
81 | struct amdgpu_device *adev = ring->adev; | |
82 | ||
10dd74ea JZ |
83 | if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) |
84 | return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); | |
09bfb891 | 85 | else |
10dd74ea | 86 | return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); |
09bfb891 LL |
87 | } |
88 | ||
89 | /** | |
90 | * uvd_v7_0_ring_get_wptr - get write pointer | |
91 | * | |
92 | * @ring: amdgpu_ring pointer | |
93 | * | |
94 | * Returns the current hardware write pointer | |
95 | */ | |
96 | static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) | |
97 | { | |
98 | struct amdgpu_device *adev = ring->adev; | |
99 | ||
10dd74ea | 100 | return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); |
09bfb891 LL |
101 | } |
102 | ||
103 | /** | |
104 | * uvd_v7_0_enc_ring_get_wptr - get enc write pointer | |
105 | * | |
106 | * @ring: amdgpu_ring pointer | |
107 | * | |
108 | * Returns the current hardware enc write pointer | |
109 | */ | |
110 | static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) | |
111 | { | |
112 | struct amdgpu_device *adev = ring->adev; | |
113 | ||
beb2ced5 FM |
114 | if (ring->use_doorbell) |
115 | return adev->wb.wb[ring->wptr_offs]; | |
116 | ||
10dd74ea JZ |
117 | if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) |
118 | return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); | |
09bfb891 | 119 | else |
10dd74ea | 120 | return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); |
09bfb891 LL |
121 | } |
122 | ||
123 | /** | |
124 | * uvd_v7_0_ring_set_wptr - set write pointer | |
125 | * | |
126 | * @ring: amdgpu_ring pointer | |
127 | * | |
128 | * Commits the write pointer to the hardware | |
129 | */ | |
130 | static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) | |
131 | { | |
132 | struct amdgpu_device *adev = ring->adev; | |
133 | ||
10dd74ea | 134 | WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); |
09bfb891 LL |
135 | } |
136 | ||
137 | /** | |
138 | * uvd_v7_0_enc_ring_set_wptr - set enc write pointer | |
139 | * | |
140 | * @ring: amdgpu_ring pointer | |
141 | * | |
142 | * Commits the enc write pointer to the hardware | |
143 | */ | |
144 | static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) | |
145 | { | |
146 | struct amdgpu_device *adev = ring->adev; | |
147 | ||
beb2ced5 FM |
148 | if (ring->use_doorbell) { |
149 | /* XXX check if swapping is necessary on BE */ | |
150 | adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); | |
151 | WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); | |
152 | return; | |
153 | } | |
154 | ||
10dd74ea JZ |
155 | if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) |
156 | WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, | |
09bfb891 LL |
157 | lower_32_bits(ring->wptr)); |
158 | else | |
10dd74ea | 159 | WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, |
09bfb891 LL |
160 | lower_32_bits(ring->wptr)); |
161 | } | |
162 | ||
163 | /** | |
164 | * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working | |
165 | * | |
166 | * @ring: the engine to test on | |
167 | * | |
168 | */ | |
169 | static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) | |
170 | { | |
171 | struct amdgpu_device *adev = ring->adev; | |
172 | uint32_t rptr = amdgpu_ring_get_rptr(ring); | |
173 | unsigned i; | |
174 | int r; | |
175 | ||
a1b9022a FM |
176 | if (amdgpu_sriov_vf(adev)) |
177 | return 0; | |
178 | ||
09bfb891 LL |
179 | r = amdgpu_ring_alloc(ring, 16); |
180 | if (r) { | |
2bb795f5 JZ |
181 | DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n", |
182 | ring->me, ring->idx, r); | |
09bfb891 LL |
183 | return r; |
184 | } | |
185 | amdgpu_ring_write(ring, HEVC_ENC_CMD_END); | |
186 | amdgpu_ring_commit(ring); | |
187 | ||
188 | for (i = 0; i < adev->usec_timeout; i++) { | |
189 | if (amdgpu_ring_get_rptr(ring) != rptr) | |
190 | break; | |
191 | DRM_UDELAY(1); | |
192 | } | |
193 | ||
194 | if (i < adev->usec_timeout) { | |
2bb795f5 JZ |
195 | DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n", |
196 | ring->me, ring->idx, i); | |
09bfb891 | 197 | } else { |
2bb795f5 JZ |
198 | DRM_ERROR("amdgpu: (%d)ring %d test failed\n", |
199 | ring->me, ring->idx); | |
09bfb891 LL |
200 | r = -ETIMEDOUT; |
201 | } | |
202 | ||
203 | return r; | |
204 | } | |
205 | ||
206 | /** | |
207 | * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg | |
208 | * | |
209 | * @adev: amdgpu_device pointer | |
210 | * @ring: ring we should submit the msg to | |
211 | * @handle: session handle to use | |
212 | * @fence: optional fence to return | |
213 | * | |
214 | * Open up a stream for HW test | |
215 | */ | |
216 | static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, | |
217 | struct dma_fence **fence) | |
218 | { | |
219 | const unsigned ib_size_dw = 16; | |
220 | struct amdgpu_job *job; | |
221 | struct amdgpu_ib *ib; | |
222 | struct dma_fence *f = NULL; | |
223 | uint64_t dummy; | |
224 | int i, r; | |
225 | ||
226 | r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); | |
227 | if (r) | |
228 | return r; | |
229 | ||
230 | ib = &job->ibs[0]; | |
231 | dummy = ib->gpu_addr + 1024; | |
232 | ||
233 | ib->length_dw = 0; | |
234 | ib->ptr[ib->length_dw++] = 0x00000018; | |
235 | ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ | |
236 | ib->ptr[ib->length_dw++] = handle; | |
237 | ib->ptr[ib->length_dw++] = 0x00000000; | |
238 | ib->ptr[ib->length_dw++] = upper_32_bits(dummy); | |
239 | ib->ptr[ib->length_dw++] = dummy; | |
240 | ||
241 | ib->ptr[ib->length_dw++] = 0x00000014; | |
242 | ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ | |
243 | ib->ptr[ib->length_dw++] = 0x0000001c; | |
244 | ib->ptr[ib->length_dw++] = 0x00000000; | |
245 | ib->ptr[ib->length_dw++] = 0x00000000; | |
246 | ||
247 | ib->ptr[ib->length_dw++] = 0x00000008; | |
248 | ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ | |
249 | ||
250 | for (i = ib->length_dw; i < ib_size_dw; ++i) | |
251 | ib->ptr[i] = 0x0; | |
252 | ||
ee913fd9 | 253 | r = amdgpu_job_submit_direct(job, ring, &f); |
09bfb891 LL |
254 | if (r) |
255 | goto err; | |
256 | ||
09bfb891 LL |
257 | if (fence) |
258 | *fence = dma_fence_get(f); | |
259 | dma_fence_put(f); | |
260 | return 0; | |
261 | ||
262 | err: | |
263 | amdgpu_job_free(job); | |
264 | return r; | |
265 | } | |
266 | ||
267 | /** | |
268 | * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg | |
269 | * | |
270 | * @adev: amdgpu_device pointer | |
271 | * @ring: ring we should submit the msg to | |
272 | * @handle: session handle to use | |
273 | * @fence: optional fence to return | |
274 | * | |
275 | * Close up a stream for HW test or if userspace failed to do so | |
276 | */ | |
277 | int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, | |
278 | bool direct, struct dma_fence **fence) | |
279 | { | |
280 | const unsigned ib_size_dw = 16; | |
281 | struct amdgpu_job *job; | |
282 | struct amdgpu_ib *ib; | |
283 | struct dma_fence *f = NULL; | |
284 | uint64_t dummy; | |
285 | int i, r; | |
286 | ||
287 | r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job); | |
288 | if (r) | |
289 | return r; | |
290 | ||
291 | ib = &job->ibs[0]; | |
292 | dummy = ib->gpu_addr + 1024; | |
293 | ||
294 | ib->length_dw = 0; | |
295 | ib->ptr[ib->length_dw++] = 0x00000018; | |
296 | ib->ptr[ib->length_dw++] = 0x00000001; | |
297 | ib->ptr[ib->length_dw++] = handle; | |
298 | ib->ptr[ib->length_dw++] = 0x00000000; | |
299 | ib->ptr[ib->length_dw++] = upper_32_bits(dummy); | |
300 | ib->ptr[ib->length_dw++] = dummy; | |
301 | ||
302 | ib->ptr[ib->length_dw++] = 0x00000014; | |
303 | ib->ptr[ib->length_dw++] = 0x00000002; | |
304 | ib->ptr[ib->length_dw++] = 0x0000001c; | |
305 | ib->ptr[ib->length_dw++] = 0x00000000; | |
306 | ib->ptr[ib->length_dw++] = 0x00000000; | |
307 | ||
308 | ib->ptr[ib->length_dw++] = 0x00000008; | |
309 | ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ | |
310 | ||
311 | for (i = ib->length_dw; i < ib_size_dw; ++i) | |
312 | ib->ptr[i] = 0x0; | |
313 | ||
ee913fd9 CK |
314 | if (direct) |
315 | r = amdgpu_job_submit_direct(job, ring, &f); | |
316 | else | |
0e28b10f | 317 | r = amdgpu_job_submit(job, &ring->adev->vce.entity, |
09bfb891 | 318 | AMDGPU_FENCE_OWNER_UNDEFINED, &f); |
ee913fd9 CK |
319 | if (r) |
320 | goto err; | |
09bfb891 LL |
321 | |
322 | if (fence) | |
323 | *fence = dma_fence_get(f); | |
324 | dma_fence_put(f); | |
325 | return 0; | |
326 | ||
327 | err: | |
328 | amdgpu_job_free(job); | |
329 | return r; | |
330 | } | |
331 | ||
332 | /** | |
333 | * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working | |
334 | * | |
335 | * @ring: the engine to test on | |
336 | * | |
337 | */ | |
338 | static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) | |
339 | { | |
340 | struct dma_fence *fence = NULL; | |
341 | long r; | |
342 | ||
343 | r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL); | |
344 | if (r) { | |
2bb795f5 | 345 | DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r); |
09bfb891 LL |
346 | goto error; |
347 | } | |
348 | ||
349 | r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence); | |
350 | if (r) { | |
2bb795f5 | 351 | DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r); |
09bfb891 LL |
352 | goto error; |
353 | } | |
354 | ||
355 | r = dma_fence_wait_timeout(fence, false, timeout); | |
356 | if (r == 0) { | |
2bb795f5 | 357 | DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me); |
09bfb891 LL |
358 | r = -ETIMEDOUT; |
359 | } else if (r < 0) { | |
2bb795f5 | 360 | DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r); |
09bfb891 | 361 | } else { |
2bb795f5 | 362 | DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx); |
09bfb891 LL |
363 | r = 0; |
364 | } | |
365 | error: | |
366 | dma_fence_put(fence); | |
367 | return r; | |
368 | } | |
369 | ||
370 | static int uvd_v7_0_early_init(void *handle) | |
371 | { | |
372 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
9181dba6 JZ |
373 | if (adev->asic_type == CHIP_VEGA20) |
374 | adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; | |
375 | else | |
376 | adev->uvd.num_uvd_inst = 1; | |
09bfb891 | 377 | |
6fa336a7 FM |
378 | if (amdgpu_sriov_vf(adev)) |
379 | adev->uvd.num_enc_rings = 1; | |
380 | else | |
381 | adev->uvd.num_enc_rings = 2; | |
09bfb891 LL |
382 | uvd_v7_0_set_ring_funcs(adev); |
383 | uvd_v7_0_set_enc_ring_funcs(adev); | |
384 | uvd_v7_0_set_irq_funcs(adev); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static int uvd_v7_0_sw_init(void *handle) | |
390 | { | |
391 | struct amdgpu_ring *ring; | |
10dd74ea | 392 | int i, j, r; |
09bfb891 LL |
393 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
394 | ||
10dd74ea JZ |
395 | for (j = 0; j < adev->uvd.num_uvd_inst; j++) { |
396 | /* UVD TRAP */ | |
44a99b65 | 397 | r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); |
09bfb891 LL |
398 | if (r) |
399 | return r; | |
10dd74ea JZ |
400 | |
401 | /* UVD ENC TRAP */ | |
402 | for (i = 0; i < adev->uvd.num_enc_rings; ++i) { | |
44a99b65 | 403 | r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); |
10dd74ea JZ |
404 | if (r) |
405 | return r; | |
406 | } | |
09bfb891 LL |
407 | } |
408 | ||
409 | r = amdgpu_uvd_sw_init(adev); | |
410 | if (r) | |
411 | return r; | |
412 | ||
413 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
414 | const struct common_firmware_header *hdr; | |
415 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; | |
416 | adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; | |
417 | adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; | |
418 | adev->firmware.fw_size += | |
419 | ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); | |
420 | DRM_INFO("PSP loading UVD firmware\n"); | |
421 | } | |
422 | ||
09bfb891 LL |
423 | r = amdgpu_uvd_resume(adev); |
424 | if (r) | |
425 | return r; | |
426 | ||
10dd74ea JZ |
427 | for (j = 0; j < adev->uvd.num_uvd_inst; j++) { |
428 | if (!amdgpu_sriov_vf(adev)) { | |
429 | ring = &adev->uvd.inst[j].ring; | |
430 | sprintf(ring->name, "uvd<%d>", j); | |
431 | r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); | |
432 | if (r) | |
433 | return r; | |
434 | } | |
435 | ||
436 | for (i = 0; i < adev->uvd.num_enc_rings; ++i) { | |
437 | ring = &adev->uvd.inst[j].ring_enc[i]; | |
438 | sprintf(ring->name, "uvd_enc%d<%d>", i, j); | |
439 | if (amdgpu_sriov_vf(adev)) { | |
440 | ring->use_doorbell = true; | |
441 | ||
442 | /* currently only use the first enconding ring for | |
443 | * sriov, so set unused location for other unused rings. | |
444 | */ | |
445 | if (i == 0) | |
446 | ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; | |
447 | else | |
448 | ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1; | |
449 | } | |
450 | r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0); | |
451 | if (r) | |
452 | return r; | |
beb2ced5 | 453 | } |
09bfb891 LL |
454 | } |
455 | ||
6fa336a7 FM |
456 | r = amdgpu_virt_alloc_mm_table(adev); |
457 | if (r) | |
458 | return r; | |
459 | ||
09bfb891 LL |
460 | return r; |
461 | } | |
462 | ||
463 | static int uvd_v7_0_sw_fini(void *handle) | |
464 | { | |
10dd74ea | 465 | int i, j, r; |
09bfb891 LL |
466 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
467 | ||
6fa336a7 FM |
468 | amdgpu_virt_free_mm_table(adev); |
469 | ||
09bfb891 LL |
470 | r = amdgpu_uvd_suspend(adev); |
471 | if (r) | |
472 | return r; | |
473 | ||
10dd74ea | 474 | for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { |
10dd74ea JZ |
475 | for (i = 0; i < adev->uvd.num_enc_rings; ++i) |
476 | amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); | |
477 | } | |
50237287 | 478 | return amdgpu_uvd_sw_fini(adev); |
09bfb891 LL |
479 | } |
480 | ||
481 | /** | |
482 | * uvd_v7_0_hw_init - start and test UVD block | |
483 | * | |
484 | * @adev: amdgpu_device pointer | |
485 | * | |
486 | * Initialize the hardware, boot up the VCPU and do some testing | |
487 | */ | |
488 | static int uvd_v7_0_hw_init(void *handle) | |
489 | { | |
490 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
10dd74ea | 491 | struct amdgpu_ring *ring; |
09bfb891 | 492 | uint32_t tmp; |
10dd74ea | 493 | int i, j, r; |
09bfb891 | 494 | |
6fa336a7 FM |
495 | if (amdgpu_sriov_vf(adev)) |
496 | r = uvd_v7_0_sriov_start(adev); | |
497 | else | |
498 | r = uvd_v7_0_start(adev); | |
09bfb891 LL |
499 | if (r) |
500 | goto done; | |
501 | ||
10dd74ea JZ |
502 | for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { |
503 | ring = &adev->uvd.inst[j].ring; | |
504 | ||
505 | if (!amdgpu_sriov_vf(adev)) { | |
506 | ring->ready = true; | |
507 | r = amdgpu_ring_test_ring(ring); | |
508 | if (r) { | |
509 | ring->ready = false; | |
510 | goto done; | |
511 | } | |
512 | ||
513 | r = amdgpu_ring_alloc(ring, 10); | |
514 | if (r) { | |
515 | DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); | |
516 | goto done; | |
517 | } | |
518 | ||
519 | tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, | |
520 | mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); | |
521 | amdgpu_ring_write(ring, tmp); | |
522 | amdgpu_ring_write(ring, 0xFFFFF); | |
523 | ||
524 | tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, | |
525 | mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); | |
526 | amdgpu_ring_write(ring, tmp); | |
527 | amdgpu_ring_write(ring, 0xFFFFF); | |
528 | ||
529 | tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, | |
530 | mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); | |
531 | amdgpu_ring_write(ring, tmp); | |
532 | amdgpu_ring_write(ring, 0xFFFFF); | |
533 | ||
534 | /* Clear timeout status bits */ | |
535 | amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, | |
536 | mmUVD_SEMA_TIMEOUT_STATUS), 0)); | |
537 | amdgpu_ring_write(ring, 0x8); | |
538 | ||
539 | amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, | |
540 | mmUVD_SEMA_CNTL), 0)); | |
541 | amdgpu_ring_write(ring, 3); | |
542 | ||
543 | amdgpu_ring_commit(ring); | |
6fa336a7 | 544 | } |
09bfb891 | 545 | |
10dd74ea JZ |
546 | for (i = 0; i < adev->uvd.num_enc_rings; ++i) { |
547 | ring = &adev->uvd.inst[j].ring_enc[i]; | |
548 | ring->ready = true; | |
549 | r = amdgpu_ring_test_ring(ring); | |
550 | if (r) { | |
551 | ring->ready = false; | |
552 | goto done; | |
553 | } | |
6fa336a7 | 554 | } |
6fa336a7 | 555 | } |
09bfb891 LL |
556 | done: |
557 | if (!r) | |
558 | DRM_INFO("UVD and UVD ENC initialized successfully.\n"); | |
559 | ||
560 | return r; | |
561 | } | |
562 | ||
563 | /** | |
564 | * uvd_v7_0_hw_fini - stop the hardware block | |
565 | * | |
566 | * @adev: amdgpu_device pointer | |
567 | * | |
568 | * Stop the UVD block, mark ring as not ready any more | |
569 | */ | |
570 | static int uvd_v7_0_hw_fini(void *handle) | |
571 | { | |
572 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
10dd74ea | 573 | int i; |
09bfb891 | 574 | |
5dd696ae TH |
575 | if (!amdgpu_sriov_vf(adev)) |
576 | uvd_v7_0_stop(adev); | |
577 | else { | |
578 | /* full access mode, so don't touch any UVD register */ | |
579 | DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); | |
580 | } | |
581 | ||
10dd74ea JZ |
582 | for (i = 0; i < adev->uvd.num_uvd_inst; ++i) |
583 | adev->uvd.inst[i].ring.ready = false; | |
09bfb891 LL |
584 | |
585 | return 0; | |
586 | } | |
587 | ||
588 | static int uvd_v7_0_suspend(void *handle) | |
589 | { | |
590 | int r; | |
591 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
592 | ||
593 | r = uvd_v7_0_hw_fini(adev); | |
594 | if (r) | |
595 | return r; | |
596 | ||
4a0144bf | 597 | return amdgpu_uvd_suspend(adev); |
09bfb891 LL |
598 | } |
599 | ||
600 | static int uvd_v7_0_resume(void *handle) | |
601 | { | |
602 | int r; | |
603 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
604 | ||
4a0144bf TSD |
605 | r = amdgpu_uvd_resume(adev); |
606 | if (r) | |
607 | return r; | |
608 | ||
50237287 | 609 | return uvd_v7_0_hw_init(adev); |
09bfb891 LL |
610 | } |
611 | ||
612 | /** | |
613 | * uvd_v7_0_mc_resume - memory controller programming | |
614 | * | |
615 | * @adev: amdgpu_device pointer | |
616 | * | |
617 | * Let the UVD memory controller know it's offsets | |
618 | */ | |
619 | static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) | |
620 | { | |
c1fe75c9 | 621 | uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); |
09bfb891 | 622 | uint32_t offset; |
10dd74ea | 623 | int i; |
09bfb891 | 624 | |
10dd74ea JZ |
625 | for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { |
626 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
627 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, | |
628 | lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); | |
629 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, | |
630 | upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); | |
631 | offset = 0; | |
632 | } else { | |
633 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, | |
634 | lower_32_bits(adev->uvd.inst[i].gpu_addr)); | |
635 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, | |
636 | upper_32_bits(adev->uvd.inst[i].gpu_addr)); | |
637 | offset = size; | |
638 | } | |
09bfb891 | 639 | |
10dd74ea JZ |
640 | WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, |
641 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3); | |
642 | WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); | |
643 | ||
644 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, | |
645 | lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); | |
646 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, | |
647 | upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); | |
648 | WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); | |
649 | WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); | |
650 | ||
651 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, | |
652 | lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); | |
653 | WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, | |
654 | upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); | |
655 | WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); | |
656 | WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, | |
657 | AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); | |
658 | ||
659 | WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, | |
660 | adev->gfx.config.gb_addr_config); | |
661 | WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, | |
662 | adev->gfx.config.gb_addr_config); | |
663 | WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, | |
664 | adev->gfx.config.gb_addr_config); | |
665 | ||
666 | WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); | |
667 | } | |
09bfb891 LL |
668 | } |
669 | ||
247ac951 FM |
670 | static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, |
671 | struct amdgpu_mm_table *table) | |
672 | { | |
673 | uint32_t data = 0, loop; | |
674 | uint64_t addr = table->gpu_addr; | |
675 | struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; | |
676 | uint32_t size; | |
10dd74ea | 677 | int i; |
247ac951 FM |
678 | |
679 | size = header->header_size + header->vce_table_size + header->uvd_table_size; | |
680 | ||
681 | /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ | |
4ad5751a TSD |
682 | WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); |
683 | WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); | |
247ac951 FM |
684 | |
685 | /* 2, update vmid of descriptor */ | |
4ad5751a | 686 | data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); |
247ac951 FM |
687 | data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; |
688 | data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ | |
4ad5751a | 689 | WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); |
247ac951 FM |
690 | |
691 | /* 3, notify mmsch about the size of this descriptor */ | |
4ad5751a | 692 | WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); |
247ac951 FM |
693 | |
694 | /* 4, set resp to zero */ | |
4ad5751a | 695 | WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); |
247ac951 | 696 | |
10dd74ea JZ |
697 | for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { |
698 | WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); | |
699 | adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; | |
700 | adev->uvd.inst[i].ring_enc[0].wptr = 0; | |
701 | adev->uvd.inst[i].ring_enc[0].wptr_old = 0; | |
702 | } | |
247ac951 | 703 | /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ |
4ad5751a | 704 | WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); |
247ac951 | 705 | |
4ad5751a | 706 | data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); |
247ac951 FM |
707 | loop = 1000; |
708 | while ((data & 0x10000002) != 0x10000002) { | |
709 | udelay(10); | |
4ad5751a | 710 | data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); |
247ac951 FM |
711 | loop--; |
712 | if (!loop) | |
713 | break; | |
714 | } | |
715 | ||
716 | if (!loop) { | |
717 | dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); | |
718 | return -EBUSY; | |
719 | } | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
724 | static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) | |
725 | { | |
726 | struct amdgpu_ring *ring; | |
727 | uint32_t offset, size, tmp; | |
728 | uint32_t table_size = 0; | |
729 | struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; | |
730 | struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; | |
731 | struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; | |
247ac951 FM |
732 | struct mmsch_v1_0_cmd_end end = { {0} }; |
733 | uint32_t *init_table = adev->virt.mm_table.cpu_addr; | |
734 | struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; | |
10dd74ea | 735 | uint8_t i = 0; |
247ac951 FM |
736 | |
737 | direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; | |
738 | direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; | |
739 | direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; | |
740 | end.cmd_header.command_type = MMSCH_COMMAND__END; | |
741 | ||
742 | if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { | |
743 | header->version = MMSCH_VERSION; | |
744 | header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; | |
745 | ||
746 | if (header->vce_table_offset == 0 && header->vce_table_size == 0) | |
747 | header->uvd_table_offset = header->header_size; | |
748 | else | |
749 | header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; | |
750 | ||
751 | init_table += header->uvd_table_offset; | |
752 | ||
10dd74ea JZ |
753 | for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { |
754 | ring = &adev->uvd.inst[i].ring; | |
755 | ring->wptr = 0; | |
756 | size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); | |
757 | ||
758 | MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), | |
759 | 0xFFFFFFFF, 0x00000004); | |
760 | /* mc resume*/ | |
761 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { | |
762 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), | |
763 | lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); | |
764 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), | |
765 | upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr)); | |
766 | offset = 0; | |
767 | } else { | |
768 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), | |
769 | lower_32_bits(adev->uvd.inst[i].gpu_addr)); | |
770 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), | |
771 | upper_32_bits(adev->uvd.inst[i].gpu_addr)); | |
772 | offset = size; | |
773 | } | |
774 | ||
775 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), | |
776 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3); | |
777 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); | |
778 | ||
779 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), | |
780 | lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); | |
781 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), | |
782 | upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); | |
783 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); | |
784 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); | |
785 | ||
786 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), | |
787 | lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); | |
788 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), | |
789 | upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); | |
790 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); | |
791 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), | |
792 | AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); | |
793 | ||
794 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); | |
795 | /* mc resume end*/ | |
796 | ||
797 | /* disable clock gating */ | |
798 | MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), | |
799 | ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); | |
800 | ||
801 | /* disable interupt */ | |
802 | MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), | |
803 | ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); | |
804 | ||
805 | /* stall UMC and register bus before resetting VCPU */ | |
806 | MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), | |
807 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, | |
808 | UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); | |
809 | ||
810 | /* put LMI, VCPU, RBC etc... into reset */ | |
811 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), | |
812 | (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | | |
813 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | | |
814 | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | | |
815 | UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | | |
816 | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | | |
817 | UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | | |
818 | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | | |
819 | UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); | |
820 | ||
821 | /* initialize UVD memory controller */ | |
822 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), | |
823 | (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | | |
824 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | | |
825 | UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | | |
826 | UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | | |
827 | UVD_LMI_CTRL__REQ_MODE_MASK | | |
828 | 0x00100000L)); | |
829 | ||
830 | /* take all subblocks out of reset, except VCPU */ | |
831 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), | |
832 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
833 | ||
834 | /* enable VCPU clock */ | |
835 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), | |
836 | UVD_VCPU_CNTL__CLK_EN_MASK); | |
837 | ||
838 | /* enable master interrupt */ | |
839 | MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), | |
840 | ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), | |
841 | (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); | |
842 | ||
843 | /* clear the bit 4 of UVD_STATUS */ | |
844 | MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), | |
845 | ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); | |
846 | ||
847 | /* force RBC into idle state */ | |
848 | size = order_base_2(ring->ring_size); | |
849 | tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); | |
850 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); | |
851 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); | |
852 | ||
853 | ring = &adev->uvd.inst[i].ring_enc[0]; | |
854 | ring->wptr = 0; | |
855 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); | |
856 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); | |
857 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); | |
858 | ||
859 | /* boot up the VCPU */ | |
860 | MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); | |
861 | ||
862 | /* enable UMC */ | |
863 | MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), | |
864 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); | |
865 | ||
866 | MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); | |
247ac951 | 867 | } |
247ac951 FM |
868 | /* add end packet */ |
869 | memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); | |
870 | table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; | |
871 | header->uvd_table_size = table_size; | |
872 | ||
247ac951 | 873 | } |
257deb8c | 874 | return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); |
247ac951 FM |
875 | } |
876 | ||
09bfb891 LL |
877 | /** |
878 | * uvd_v7_0_start - start UVD block | |
879 | * | |
880 | * @adev: amdgpu_device pointer | |
881 | * | |
882 | * Setup and start the UVD block | |
883 | */ | |
884 | static int uvd_v7_0_start(struct amdgpu_device *adev) | |
885 | { | |
10dd74ea | 886 | struct amdgpu_ring *ring; |
09bfb891 LL |
887 | uint32_t rb_bufsz, tmp; |
888 | uint32_t lmi_swap_cntl; | |
889 | uint32_t mp_swap_cntl; | |
10dd74ea | 890 | int i, j, k, r; |
09bfb891 | 891 | |
10dd74ea JZ |
892 | for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { |
893 | /* disable DPG */ | |
894 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, | |
895 | ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); | |
896 | } | |
09bfb891 LL |
897 | |
898 | /* disable byte swapping */ | |
899 | lmi_swap_cntl = 0; | |
900 | mp_swap_cntl = 0; | |
901 | ||
902 | uvd_v7_0_mc_resume(adev); | |
903 | ||
10dd74ea JZ |
904 | for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { |
905 | ring = &adev->uvd.inst[k].ring; | |
906 | /* disable clock gating */ | |
907 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, | |
908 | ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); | |
09bfb891 | 909 | |
10dd74ea JZ |
910 | /* disable interupt */ |
911 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, | |
912 | ~UVD_MASTINT_EN__VCPU_EN_MASK); | |
913 | ||
914 | /* stall UMC and register bus before resetting VCPU */ | |
915 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), | |
916 | UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, | |
917 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); | |
918 | mdelay(1); | |
919 | ||
920 | /* put LMI, VCPU, RBC etc... into reset */ | |
921 | WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, | |
922 | UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | | |
923 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | | |
924 | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | | |
925 | UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | | |
926 | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | | |
927 | UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | | |
928 | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | | |
929 | UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); | |
930 | mdelay(5); | |
931 | ||
932 | /* initialize UVD memory controller */ | |
933 | WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, | |
934 | (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | | |
935 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | | |
936 | UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | | |
937 | UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | | |
938 | UVD_LMI_CTRL__REQ_MODE_MASK | | |
939 | 0x00100000L); | |
09bfb891 LL |
940 | |
941 | #ifdef __BIG_ENDIAN | |
10dd74ea JZ |
942 | /* swap (8 in 32) RB and IB */ |
943 | lmi_swap_cntl = 0xa; | |
944 | mp_swap_cntl = 0; | |
09bfb891 | 945 | #endif |
10dd74ea JZ |
946 | WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); |
947 | WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); | |
09bfb891 | 948 | |
10dd74ea JZ |
949 | WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); |
950 | WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); | |
951 | WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); | |
952 | WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); | |
953 | WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); | |
954 | WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); | |
09bfb891 | 955 | |
10dd74ea JZ |
956 | /* take all subblocks out of reset, except VCPU */ |
957 | WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, | |
958 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
959 | mdelay(5); | |
09bfb891 | 960 | |
10dd74ea JZ |
961 | /* enable VCPU clock */ |
962 | WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, | |
963 | UVD_VCPU_CNTL__CLK_EN_MASK); | |
09bfb891 | 964 | |
10dd74ea JZ |
965 | /* enable UMC */ |
966 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, | |
967 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); | |
09bfb891 | 968 | |
10dd74ea JZ |
969 | /* boot up the VCPU */ |
970 | WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); | |
971 | mdelay(10); | |
972 | ||
973 | for (i = 0; i < 10; ++i) { | |
974 | uint32_t status; | |
975 | ||
976 | for (j = 0; j < 100; ++j) { | |
977 | status = RREG32_SOC15(UVD, k, mmUVD_STATUS); | |
978 | if (status & 2) | |
979 | break; | |
980 | mdelay(10); | |
981 | } | |
982 | r = 0; | |
09bfb891 LL |
983 | if (status & 2) |
984 | break; | |
10dd74ea JZ |
985 | |
986 | DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); | |
987 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), | |
988 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, | |
989 | ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
990 | mdelay(10); | |
991 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, | |
992 | ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
09bfb891 | 993 | mdelay(10); |
10dd74ea | 994 | r = -1; |
09bfb891 | 995 | } |
09bfb891 | 996 | |
10dd74ea JZ |
997 | if (r) { |
998 | DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); | |
999 | return r; | |
1000 | } | |
1001 | /* enable master interrupt */ | |
1002 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), | |
1003 | (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), | |
1004 | ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); | |
09bfb891 | 1005 | |
10dd74ea JZ |
1006 | /* clear the bit 4 of UVD_STATUS */ |
1007 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, | |
1008 | ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); | |
09bfb891 | 1009 | |
10dd74ea JZ |
1010 | /* force RBC into idle state */ |
1011 | rb_bufsz = order_base_2(ring->ring_size); | |
1012 | tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); | |
1013 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); | |
1014 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); | |
1015 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); | |
1016 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); | |
1017 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); | |
1018 | WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); | |
1019 | ||
1020 | /* set the write pointer delay */ | |
1021 | WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); | |
1022 | ||
1023 | /* set the wb address */ | |
1024 | WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, | |
1025 | (upper_32_bits(ring->gpu_addr) >> 2)); | |
1026 | ||
1027 | /* programm the RB_BASE for ring buffer */ | |
1028 | WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, | |
1029 | lower_32_bits(ring->gpu_addr)); | |
1030 | WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, | |
1031 | upper_32_bits(ring->gpu_addr)); | |
1032 | ||
1033 | /* Initialize the ring buffer's read and write pointers */ | |
1034 | WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); | |
1035 | ||
1036 | ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); | |
1037 | WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, | |
1038 | lower_32_bits(ring->wptr)); | |
1039 | ||
1040 | WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, | |
1041 | ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); | |
1042 | ||
1043 | ring = &adev->uvd.inst[k].ring_enc[0]; | |
1044 | WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); | |
1045 | WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); | |
1046 | WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); | |
1047 | WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); | |
1048 | WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); | |
1049 | ||
1050 | ring = &adev->uvd.inst[k].ring_enc[1]; | |
1051 | WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); | |
1052 | WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); | |
1053 | WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); | |
1054 | WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); | |
1055 | WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); | |
1056 | } | |
09bfb891 LL |
1057 | return 0; |
1058 | } | |
1059 | ||
1060 | /** | |
1061 | * uvd_v7_0_stop - stop UVD block | |
1062 | * | |
1063 | * @adev: amdgpu_device pointer | |
1064 | * | |
1065 | * stop the UVD block | |
1066 | */ | |
1067 | static void uvd_v7_0_stop(struct amdgpu_device *adev) | |
1068 | { | |
10dd74ea JZ |
1069 | uint8_t i = 0; |
1070 | ||
1071 | for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { | |
1072 | /* force RBC into idle state */ | |
1073 | WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); | |
09bfb891 | 1074 | |
10dd74ea JZ |
1075 | /* Stall UMC and register bus before resetting VCPU */ |
1076 | WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), | |
1077 | UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, | |
1078 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); | |
1079 | mdelay(1); | |
09bfb891 | 1080 | |
10dd74ea JZ |
1081 | /* put VCPU into reset */ |
1082 | WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, | |
1083 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); | |
1084 | mdelay(5); | |
1085 | ||
1086 | /* disable VCPU clock */ | |
1087 | WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); | |
1088 | ||
1089 | /* Unstall UMC and register bus */ | |
1090 | WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, | |
1091 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); | |
1092 | } | |
09bfb891 LL |
1093 | } |
1094 | ||
1095 | /** | |
1096 | * uvd_v7_0_ring_emit_fence - emit an fence & trap command | |
1097 | * | |
1098 | * @ring: amdgpu_ring pointer | |
1099 | * @fence: fence to emit | |
1100 | * | |
1101 | * Write a fence and a trap command to the ring. | |
1102 | */ | |
1103 | static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
1104 | unsigned flags) | |
1105 | { | |
cd29253f SL |
1106 | struct amdgpu_device *adev = ring->adev; |
1107 | ||
09bfb891 LL |
1108 | WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); |
1109 | ||
1110 | amdgpu_ring_write(ring, | |
10dd74ea | 1111 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); |
09bfb891 LL |
1112 | amdgpu_ring_write(ring, seq); |
1113 | amdgpu_ring_write(ring, | |
10dd74ea | 1114 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); |
09bfb891 LL |
1115 | amdgpu_ring_write(ring, addr & 0xffffffff); |
1116 | amdgpu_ring_write(ring, | |
10dd74ea | 1117 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); |
09bfb891 LL |
1118 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); |
1119 | amdgpu_ring_write(ring, | |
10dd74ea | 1120 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); |
09bfb891 LL |
1121 | amdgpu_ring_write(ring, 0); |
1122 | ||
1123 | amdgpu_ring_write(ring, | |
10dd74ea | 1124 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); |
09bfb891 LL |
1125 | amdgpu_ring_write(ring, 0); |
1126 | amdgpu_ring_write(ring, | |
10dd74ea | 1127 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); |
09bfb891 LL |
1128 | amdgpu_ring_write(ring, 0); |
1129 | amdgpu_ring_write(ring, | |
10dd74ea | 1130 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); |
09bfb891 LL |
1131 | amdgpu_ring_write(ring, 2); |
1132 | } | |
1133 | ||
1134 | /** | |
1135 | * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command | |
1136 | * | |
1137 | * @ring: amdgpu_ring pointer | |
1138 | * @fence: fence to emit | |
1139 | * | |
1140 | * Write enc a fence and a trap command to the ring. | |
1141 | */ | |
1142 | static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, | |
1143 | u64 seq, unsigned flags) | |
1144 | { | |
cd29253f | 1145 | |
09bfb891 LL |
1146 | WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); |
1147 | ||
1148 | amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); | |
1149 | amdgpu_ring_write(ring, addr); | |
1150 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
1151 | amdgpu_ring_write(ring, seq); | |
1152 | amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); | |
1153 | } | |
1154 | ||
996cab95 CK |
1155 | /** |
1156 | * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing | |
1157 | * | |
1158 | * @ring: amdgpu_ring pointer | |
1159 | */ | |
1160 | static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) | |
1161 | { | |
1162 | /* The firmware doesn't seem to like touching registers at this point. */ | |
1163 | } | |
1164 | ||
09bfb891 LL |
1165 | /** |
1166 | * uvd_v7_0_ring_test_ring - register write test | |
1167 | * | |
1168 | * @ring: amdgpu_ring pointer | |
1169 | * | |
1170 | * Test if we can successfully write to the context register | |
1171 | */ | |
1172 | static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) | |
1173 | { | |
1174 | struct amdgpu_device *adev = ring->adev; | |
1175 | uint32_t tmp = 0; | |
1176 | unsigned i; | |
1177 | int r; | |
1178 | ||
10dd74ea | 1179 | WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); |
09bfb891 LL |
1180 | r = amdgpu_ring_alloc(ring, 3); |
1181 | if (r) { | |
2bb795f5 JZ |
1182 | DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n", |
1183 | ring->me, ring->idx, r); | |
09bfb891 LL |
1184 | return r; |
1185 | } | |
1186 | amdgpu_ring_write(ring, | |
10dd74ea | 1187 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); |
09bfb891 LL |
1188 | amdgpu_ring_write(ring, 0xDEADBEEF); |
1189 | amdgpu_ring_commit(ring); | |
1190 | for (i = 0; i < adev->usec_timeout; i++) { | |
10dd74ea | 1191 | tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); |
09bfb891 LL |
1192 | if (tmp == 0xDEADBEEF) |
1193 | break; | |
1194 | DRM_UDELAY(1); | |
1195 | } | |
1196 | ||
1197 | if (i < adev->usec_timeout) { | |
2bb795f5 JZ |
1198 | DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n", |
1199 | ring->me, ring->idx, i); | |
09bfb891 | 1200 | } else { |
2bb795f5 JZ |
1201 | DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n", |
1202 | ring->me, ring->idx, tmp); | |
09bfb891 LL |
1203 | r = -EINVAL; |
1204 | } | |
1205 | return r; | |
1206 | } | |
1207 | ||
66c28d6d CK |
1208 | /** |
1209 | * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. | |
1210 | * | |
1211 | * @p: the CS parser with the IBs | |
1212 | * @ib_idx: which IB to patch | |
1213 | * | |
1214 | */ | |
1215 | static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, | |
1216 | uint32_t ib_idx) | |
1217 | { | |
1218 | struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; | |
1219 | unsigned i; | |
1220 | ||
1221 | /* No patching necessary for the first instance */ | |
1222 | if (!p->ring->me) | |
1223 | return 0; | |
1224 | ||
1225 | for (i = 0; i < ib->length_dw; i += 2) { | |
1226 | uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); | |
1227 | ||
1228 | reg -= p->adev->reg_offset[UVD_HWIP][0][1]; | |
1229 | reg += p->adev->reg_offset[UVD_HWIP][1][1]; | |
1230 | ||
1231 | amdgpu_set_ib_value(p, ib_idx, i, reg); | |
1232 | } | |
1233 | return 0; | |
1234 | } | |
1235 | ||
09bfb891 LL |
1236 | /** |
1237 | * uvd_v7_0_ring_emit_ib - execute indirect buffer | |
1238 | * | |
1239 | * @ring: amdgpu_ring pointer | |
1240 | * @ib: indirect buffer to execute | |
1241 | * | |
1242 | * Write ring commands to execute the indirect buffer | |
1243 | */ | |
1244 | static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, | |
1245 | struct amdgpu_ib *ib, | |
c4f46f22 | 1246 | unsigned vmid, bool ctx_switch) |
09bfb891 | 1247 | { |
cd29253f SL |
1248 | struct amdgpu_device *adev = ring->adev; |
1249 | ||
09bfb891 | 1250 | amdgpu_ring_write(ring, |
10dd74ea | 1251 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); |
c4f46f22 | 1252 | amdgpu_ring_write(ring, vmid); |
09bfb891 LL |
1253 | |
1254 | amdgpu_ring_write(ring, | |
10dd74ea | 1255 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); |
09bfb891 LL |
1256 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); |
1257 | amdgpu_ring_write(ring, | |
10dd74ea | 1258 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); |
09bfb891 LL |
1259 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
1260 | amdgpu_ring_write(ring, | |
10dd74ea | 1261 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); |
09bfb891 LL |
1262 | amdgpu_ring_write(ring, ib->length_dw); |
1263 | } | |
1264 | ||
1265 | /** | |
1266 | * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer | |
1267 | * | |
1268 | * @ring: amdgpu_ring pointer | |
1269 | * @ib: indirect buffer to execute | |
1270 | * | |
1271 | * Write enc ring commands to execute the indirect buffer | |
1272 | */ | |
1273 | static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, | |
c4f46f22 | 1274 | struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) |
09bfb891 LL |
1275 | { |
1276 | amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); | |
c4f46f22 | 1277 | amdgpu_ring_write(ring, vmid); |
09bfb891 LL |
1278 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); |
1279 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
1280 | amdgpu_ring_write(ring, ib->length_dw); | |
1281 | } | |
1282 | ||
b6cb3b5c CK |
1283 | static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, |
1284 | uint32_t reg, uint32_t val) | |
09bfb891 | 1285 | { |
cd29253f SL |
1286 | struct amdgpu_device *adev = ring->adev; |
1287 | ||
09bfb891 | 1288 | amdgpu_ring_write(ring, |
10dd74ea | 1289 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); |
b6cb3b5c | 1290 | amdgpu_ring_write(ring, reg << 2); |
09bfb891 | 1291 | amdgpu_ring_write(ring, |
10dd74ea | 1292 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); |
b6cb3b5c | 1293 | amdgpu_ring_write(ring, val); |
09bfb891 | 1294 | amdgpu_ring_write(ring, |
10dd74ea | 1295 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); |
09bfb891 LL |
1296 | amdgpu_ring_write(ring, 8); |
1297 | } | |
1298 | ||
38d32a75 CK |
1299 | static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, |
1300 | uint32_t val, uint32_t mask) | |
09bfb891 | 1301 | { |
cd29253f SL |
1302 | struct amdgpu_device *adev = ring->adev; |
1303 | ||
09bfb891 | 1304 | amdgpu_ring_write(ring, |
10dd74ea | 1305 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); |
38d32a75 | 1306 | amdgpu_ring_write(ring, reg << 2); |
09bfb891 | 1307 | amdgpu_ring_write(ring, |
10dd74ea | 1308 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); |
38d32a75 | 1309 | amdgpu_ring_write(ring, val); |
09bfb891 | 1310 | amdgpu_ring_write(ring, |
10dd74ea | 1311 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); |
09bfb891 LL |
1312 | amdgpu_ring_write(ring, mask); |
1313 | amdgpu_ring_write(ring, | |
10dd74ea | 1314 | PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); |
09bfb891 LL |
1315 | amdgpu_ring_write(ring, 12); |
1316 | } | |
1317 | ||
1318 | static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
c633c00b | 1319 | unsigned vmid, uint64_t pd_addr) |
09bfb891 | 1320 | { |
2e819849 | 1321 | struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; |
3de676d8 | 1322 | uint32_t data0, data1, mask; |
09bfb891 | 1323 | |
c633c00b | 1324 | pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
2e819849 | 1325 | |
9096d6e5 | 1326 | /* wait for reg writes */ |
38d32a75 | 1327 | data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; |
2e819849 CK |
1328 | data1 = lower_32_bits(pd_addr); |
1329 | mask = 0xffffffff; | |
38d32a75 | 1330 | uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); |
09bfb891 LL |
1331 | } |
1332 | ||
946a4d5b SL |
1333 | static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
1334 | { | |
946a4d5b | 1335 | struct amdgpu_device *adev = ring->adev; |
cbb7a239 | 1336 | int i; |
946a4d5b | 1337 | |
cbb7a239 | 1338 | WARN_ON(ring->wptr % 2 || count % 2); |
946a4d5b | 1339 | |
cbb7a239 LL |
1340 | for (i = 0; i < count / 2; i++) { |
1341 | amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); | |
1342 | amdgpu_ring_write(ring, 0); | |
1343 | } | |
946a4d5b SL |
1344 | } |
1345 | ||
09bfb891 LL |
1346 | static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) |
1347 | { | |
1348 | amdgpu_ring_write(ring, HEVC_ENC_CMD_END); | |
1349 | } | |
1350 | ||
38d32a75 CK |
1351 | static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, |
1352 | uint32_t reg, uint32_t val, | |
1353 | uint32_t mask) | |
1354 | { | |
1355 | amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); | |
1356 | amdgpu_ring_write(ring, reg << 2); | |
1357 | amdgpu_ring_write(ring, mask); | |
1358 | amdgpu_ring_write(ring, val); | |
1359 | } | |
1360 | ||
09bfb891 | 1361 | static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, |
c633c00b | 1362 | unsigned int vmid, uint64_t pd_addr) |
09bfb891 | 1363 | { |
2e819849 | 1364 | struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; |
09bfb891 | 1365 | |
c633c00b | 1366 | pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
2e819849 | 1367 | |
9096d6e5 | 1368 | /* wait for reg writes */ |
38d32a75 CK |
1369 | uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, |
1370 | lower_32_bits(pd_addr), 0xffffffff); | |
09bfb891 LL |
1371 | } |
1372 | ||
b6cb3b5c CK |
1373 | static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, |
1374 | uint32_t reg, uint32_t val) | |
1375 | { | |
1376 | amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); | |
1377 | amdgpu_ring_write(ring, reg << 2); | |
1378 | amdgpu_ring_write(ring, val); | |
1379 | } | |
1380 | ||
09bfb891 LL |
1381 | #if 0 |
1382 | static bool uvd_v7_0_is_idle(void *handle) | |
1383 | { | |
1384 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1385 | ||
1386 | return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); | |
1387 | } | |
1388 | ||
1389 | static int uvd_v7_0_wait_for_idle(void *handle) | |
1390 | { | |
1391 | unsigned i; | |
1392 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1393 | ||
1394 | for (i = 0; i < adev->usec_timeout; i++) { | |
1395 | if (uvd_v7_0_is_idle(handle)) | |
1396 | return 0; | |
1397 | } | |
1398 | return -ETIMEDOUT; | |
1399 | } | |
1400 | ||
1401 | #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd | |
1402 | static bool uvd_v7_0_check_soft_reset(void *handle) | |
1403 | { | |
1404 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1405 | u32 srbm_soft_reset = 0; | |
1406 | u32 tmp = RREG32(mmSRBM_STATUS); | |
1407 | ||
1408 | if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || | |
1409 | REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || | |
10dd74ea | 1410 | (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & |
4ad5751a | 1411 | AMDGPU_UVD_STATUS_BUSY_MASK)) |
09bfb891 LL |
1412 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, |
1413 | SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); | |
1414 | ||
1415 | if (srbm_soft_reset) { | |
10dd74ea | 1416 | adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; |
09bfb891 LL |
1417 | return true; |
1418 | } else { | |
10dd74ea | 1419 | adev->uvd.inst[ring->me].srbm_soft_reset = 0; |
09bfb891 LL |
1420 | return false; |
1421 | } | |
1422 | } | |
1423 | ||
1424 | static int uvd_v7_0_pre_soft_reset(void *handle) | |
1425 | { | |
1426 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1427 | ||
10dd74ea | 1428 | if (!adev->uvd.inst[ring->me].srbm_soft_reset) |
09bfb891 LL |
1429 | return 0; |
1430 | ||
1431 | uvd_v7_0_stop(adev); | |
1432 | return 0; | |
1433 | } | |
1434 | ||
1435 | static int uvd_v7_0_soft_reset(void *handle) | |
1436 | { | |
1437 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1438 | u32 srbm_soft_reset; | |
1439 | ||
10dd74ea | 1440 | if (!adev->uvd.inst[ring->me].srbm_soft_reset) |
09bfb891 | 1441 | return 0; |
10dd74ea | 1442 | srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; |
09bfb891 LL |
1443 | |
1444 | if (srbm_soft_reset) { | |
1445 | u32 tmp; | |
1446 | ||
1447 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1448 | tmp |= srbm_soft_reset; | |
1449 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1450 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1451 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1452 | ||
1453 | udelay(50); | |
1454 | ||
1455 | tmp &= ~srbm_soft_reset; | |
1456 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1457 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1458 | ||
1459 | /* Wait a little for things to settle down */ | |
1460 | udelay(50); | |
1461 | } | |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | ||
1466 | static int uvd_v7_0_post_soft_reset(void *handle) | |
1467 | { | |
1468 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1469 | ||
10dd74ea | 1470 | if (!adev->uvd.inst[ring->me].srbm_soft_reset) |
09bfb891 LL |
1471 | return 0; |
1472 | ||
1473 | mdelay(5); | |
1474 | ||
1475 | return uvd_v7_0_start(adev); | |
1476 | } | |
1477 | #endif | |
1478 | ||
1479 | static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, | |
1480 | struct amdgpu_irq_src *source, | |
1481 | unsigned type, | |
1482 | enum amdgpu_interrupt_state state) | |
1483 | { | |
1484 | // TODO | |
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, | |
1489 | struct amdgpu_irq_src *source, | |
1490 | struct amdgpu_iv_entry *entry) | |
1491 | { | |
10dd74ea JZ |
1492 | uint32_t ip_instance; |
1493 | ||
1494 | switch (entry->client_id) { | |
1495 | case SOC15_IH_CLIENTID_UVD: | |
1496 | ip_instance = 0; | |
1497 | break; | |
b53a6ebc JZ |
1498 | case SOC15_IH_CLIENTID_UVD1: |
1499 | ip_instance = 1; | |
1500 | break; | |
10dd74ea JZ |
1501 | default: |
1502 | DRM_ERROR("Unhandled client id: %d\n", entry->client_id); | |
1503 | return 0; | |
1504 | } | |
1505 | ||
09bfb891 | 1506 | DRM_DEBUG("IH: UVD TRAP\n"); |
10dd74ea | 1507 | |
09bfb891 LL |
1508 | switch (entry->src_id) { |
1509 | case 124: | |
10dd74ea | 1510 | amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); |
09bfb891 LL |
1511 | break; |
1512 | case 119: | |
10dd74ea | 1513 | amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); |
09bfb891 LL |
1514 | break; |
1515 | case 120: | |
6fa336a7 | 1516 | if (!amdgpu_sriov_vf(adev)) |
10dd74ea | 1517 | amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); |
09bfb891 LL |
1518 | break; |
1519 | default: | |
1520 | DRM_ERROR("Unhandled interrupt: %d %d\n", | |
1521 | entry->src_id, entry->src_data[0]); | |
1522 | break; | |
1523 | } | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | #if 0 | |
1529 | static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) | |
1530 | { | |
1531 | uint32_t data, data1, data2, suvd_flags; | |
1532 | ||
10dd74ea JZ |
1533 | data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); |
1534 | data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); | |
1535 | data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); | |
09bfb891 LL |
1536 | |
1537 | data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | | |
1538 | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); | |
1539 | ||
1540 | suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | | |
1541 | UVD_SUVD_CGC_GATE__SIT_MASK | | |
1542 | UVD_SUVD_CGC_GATE__SMP_MASK | | |
1543 | UVD_SUVD_CGC_GATE__SCM_MASK | | |
1544 | UVD_SUVD_CGC_GATE__SDB_MASK; | |
1545 | ||
1546 | data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | | |
1547 | (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | | |
1548 | (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); | |
1549 | ||
1550 | data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | | |
1551 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK | | |
1552 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK | | |
1553 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK | | |
1554 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK | | |
1555 | UVD_CGC_CTRL__SYS_MODE_MASK | | |
1556 | UVD_CGC_CTRL__UDEC_MODE_MASK | | |
1557 | UVD_CGC_CTRL__MPEG2_MODE_MASK | | |
1558 | UVD_CGC_CTRL__REGS_MODE_MASK | | |
1559 | UVD_CGC_CTRL__RBC_MODE_MASK | | |
1560 | UVD_CGC_CTRL__LMI_MC_MODE_MASK | | |
1561 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK | | |
1562 | UVD_CGC_CTRL__IDCT_MODE_MASK | | |
1563 | UVD_CGC_CTRL__MPRD_MODE_MASK | | |
1564 | UVD_CGC_CTRL__MPC_MODE_MASK | | |
1565 | UVD_CGC_CTRL__LBSI_MODE_MASK | | |
1566 | UVD_CGC_CTRL__LRBBM_MODE_MASK | | |
1567 | UVD_CGC_CTRL__WCB_MODE_MASK | | |
1568 | UVD_CGC_CTRL__VCPU_MODE_MASK | | |
1569 | UVD_CGC_CTRL__JPEG_MODE_MASK | | |
1570 | UVD_CGC_CTRL__JPEG2_MODE_MASK | | |
1571 | UVD_CGC_CTRL__SCPU_MODE_MASK); | |
1572 | data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | | |
1573 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | | |
1574 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | | |
1575 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | | |
1576 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); | |
1577 | data1 |= suvd_flags; | |
1578 | ||
10dd74ea JZ |
1579 | WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); |
1580 | WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); | |
1581 | WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); | |
1582 | WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); | |
09bfb891 LL |
1583 | } |
1584 | ||
1585 | static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) | |
1586 | { | |
1587 | uint32_t data, data1, cgc_flags, suvd_flags; | |
1588 | ||
10dd74ea JZ |
1589 | data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); |
1590 | data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); | |
09bfb891 LL |
1591 | |
1592 | cgc_flags = UVD_CGC_GATE__SYS_MASK | | |
1593 | UVD_CGC_GATE__UDEC_MASK | | |
1594 | UVD_CGC_GATE__MPEG2_MASK | | |
1595 | UVD_CGC_GATE__RBC_MASK | | |
1596 | UVD_CGC_GATE__LMI_MC_MASK | | |
1597 | UVD_CGC_GATE__IDCT_MASK | | |
1598 | UVD_CGC_GATE__MPRD_MASK | | |
1599 | UVD_CGC_GATE__MPC_MASK | | |
1600 | UVD_CGC_GATE__LBSI_MASK | | |
1601 | UVD_CGC_GATE__LRBBM_MASK | | |
1602 | UVD_CGC_GATE__UDEC_RE_MASK | | |
1603 | UVD_CGC_GATE__UDEC_CM_MASK | | |
1604 | UVD_CGC_GATE__UDEC_IT_MASK | | |
1605 | UVD_CGC_GATE__UDEC_DB_MASK | | |
1606 | UVD_CGC_GATE__UDEC_MP_MASK | | |
1607 | UVD_CGC_GATE__WCB_MASK | | |
1608 | UVD_CGC_GATE__VCPU_MASK | | |
1609 | UVD_CGC_GATE__SCPU_MASK | | |
1610 | UVD_CGC_GATE__JPEG_MASK | | |
1611 | UVD_CGC_GATE__JPEG2_MASK; | |
1612 | ||
1613 | suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | | |
1614 | UVD_SUVD_CGC_GATE__SIT_MASK | | |
1615 | UVD_SUVD_CGC_GATE__SMP_MASK | | |
1616 | UVD_SUVD_CGC_GATE__SCM_MASK | | |
1617 | UVD_SUVD_CGC_GATE__SDB_MASK; | |
1618 | ||
1619 | data |= cgc_flags; | |
1620 | data1 |= suvd_flags; | |
1621 | ||
10dd74ea JZ |
1622 | WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); |
1623 | WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); | |
09bfb891 LL |
1624 | } |
1625 | ||
1626 | static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) | |
1627 | { | |
1628 | u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); | |
1629 | ||
1630 | if (enable) | |
1631 | tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | | |
1632 | GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); | |
1633 | else | |
1634 | tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | | |
1635 | GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); | |
1636 | ||
1637 | WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); | |
1638 | } | |
1639 | ||
1640 | ||
1641 | static int uvd_v7_0_set_clockgating_state(void *handle, | |
1642 | enum amd_clockgating_state state) | |
1643 | { | |
1644 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1645 | bool enable = (state == AMD_CG_STATE_GATE) ? true : false; | |
1646 | ||
1647 | uvd_v7_0_set_bypass_mode(adev, enable); | |
1648 | ||
1649 | if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) | |
1650 | return 0; | |
1651 | ||
1652 | if (enable) { | |
1653 | /* disable HW gating and enable Sw gating */ | |
1654 | uvd_v7_0_set_sw_clock_gating(adev); | |
1655 | } else { | |
1656 | /* wait for STATUS to clear */ | |
1657 | if (uvd_v7_0_wait_for_idle(handle)) | |
1658 | return -EBUSY; | |
1659 | ||
1660 | /* enable HW gates because UVD is idle */ | |
1661 | /* uvd_v7_0_set_hw_clock_gating(adev); */ | |
1662 | } | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static int uvd_v7_0_set_powergating_state(void *handle, | |
1668 | enum amd_powergating_state state) | |
1669 | { | |
1670 | /* This doesn't actually powergate the UVD block. | |
1671 | * That's done in the dpm code via the SMC. This | |
1672 | * just re-inits the block as necessary. The actual | |
1673 | * gating still happens in the dpm code. We should | |
1674 | * revisit this when there is a cleaner line between | |
1675 | * the smc and the hw blocks | |
1676 | */ | |
1677 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1678 | ||
1679 | if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) | |
1680 | return 0; | |
1681 | ||
10dd74ea | 1682 | WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); |
09bfb891 LL |
1683 | |
1684 | if (state == AMD_PG_STATE_GATE) { | |
1685 | uvd_v7_0_stop(adev); | |
1686 | return 0; | |
1687 | } else { | |
1688 | return uvd_v7_0_start(adev); | |
1689 | } | |
1690 | } | |
1691 | #endif | |
1692 | ||
1693 | static int uvd_v7_0_set_clockgating_state(void *handle, | |
1694 | enum amd_clockgating_state state) | |
1695 | { | |
1696 | /* needed for driver unload*/ | |
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | const struct amd_ip_funcs uvd_v7_0_ip_funcs = { | |
1701 | .name = "uvd_v7_0", | |
1702 | .early_init = uvd_v7_0_early_init, | |
1703 | .late_init = NULL, | |
1704 | .sw_init = uvd_v7_0_sw_init, | |
1705 | .sw_fini = uvd_v7_0_sw_fini, | |
1706 | .hw_init = uvd_v7_0_hw_init, | |
1707 | .hw_fini = uvd_v7_0_hw_fini, | |
1708 | .suspend = uvd_v7_0_suspend, | |
1709 | .resume = uvd_v7_0_resume, | |
1710 | .is_idle = NULL /* uvd_v7_0_is_idle */, | |
1711 | .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, | |
1712 | .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, | |
1713 | .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, | |
1714 | .soft_reset = NULL /* uvd_v7_0_soft_reset */, | |
1715 | .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, | |
1716 | .set_clockgating_state = uvd_v7_0_set_clockgating_state, | |
1717 | .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, | |
1718 | }; | |
1719 | ||
1720 | static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { | |
1721 | .type = AMDGPU_RING_TYPE_UVD, | |
1722 | .align_mask = 0xf, | |
09bfb891 | 1723 | .support_64bit_ptrs = false, |
0eeb68b3 | 1724 | .vmhub = AMDGPU_MMHUB, |
09bfb891 LL |
1725 | .get_rptr = uvd_v7_0_ring_get_rptr, |
1726 | .get_wptr = uvd_v7_0_ring_get_wptr, | |
1727 | .set_wptr = uvd_v7_0_ring_set_wptr, | |
66c28d6d | 1728 | .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, |
09bfb891 | 1729 | .emit_frame_size = |
996cab95 | 1730 | 6 + /* hdp invalidate */ |
f732b6b3 CK |
1731 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + |
1732 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + | |
1733 | 8 + /* uvd_v7_0_ring_emit_vm_flush */ | |
09bfb891 LL |
1734 | 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ |
1735 | .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ | |
1736 | .emit_ib = uvd_v7_0_ring_emit_ib, | |
1737 | .emit_fence = uvd_v7_0_ring_emit_fence, | |
1738 | .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, | |
996cab95 | 1739 | .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, |
09bfb891 LL |
1740 | .test_ring = uvd_v7_0_ring_test_ring, |
1741 | .test_ib = amdgpu_uvd_ring_test_ib, | |
946a4d5b | 1742 | .insert_nop = uvd_v7_0_ring_insert_nop, |
09bfb891 LL |
1743 | .pad_ib = amdgpu_ring_generic_pad_ib, |
1744 | .begin_use = amdgpu_uvd_ring_begin_use, | |
1745 | .end_use = amdgpu_uvd_ring_end_use, | |
b6cb3b5c | 1746 | .emit_wreg = uvd_v7_0_ring_emit_wreg, |
38d32a75 | 1747 | .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, |
f3336254 | 1748 | .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, |
09bfb891 LL |
1749 | }; |
1750 | ||
1751 | static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { | |
1752 | .type = AMDGPU_RING_TYPE_UVD_ENC, | |
1753 | .align_mask = 0x3f, | |
1754 | .nop = HEVC_ENC_CMD_NO_OP, | |
1755 | .support_64bit_ptrs = false, | |
0eeb68b3 | 1756 | .vmhub = AMDGPU_MMHUB, |
09bfb891 LL |
1757 | .get_rptr = uvd_v7_0_enc_ring_get_rptr, |
1758 | .get_wptr = uvd_v7_0_enc_ring_get_wptr, | |
1759 | .set_wptr = uvd_v7_0_enc_ring_set_wptr, | |
1760 | .emit_frame_size = | |
2ee150cd | 1761 | 3 + 3 + /* hdp flush / invalidate */ |
f732b6b3 CK |
1762 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + |
1763 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + | |
1764 | 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ | |
09bfb891 LL |
1765 | 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ |
1766 | 1, /* uvd_v7_0_enc_ring_insert_end */ | |
1767 | .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ | |
1768 | .emit_ib = uvd_v7_0_enc_ring_emit_ib, | |
1769 | .emit_fence = uvd_v7_0_enc_ring_emit_fence, | |
1770 | .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, | |
1771 | .test_ring = uvd_v7_0_enc_ring_test_ring, | |
1772 | .test_ib = uvd_v7_0_enc_ring_test_ib, | |
1773 | .insert_nop = amdgpu_ring_insert_nop, | |
1774 | .insert_end = uvd_v7_0_enc_ring_insert_end, | |
1775 | .pad_ib = amdgpu_ring_generic_pad_ib, | |
1776 | .begin_use = amdgpu_uvd_ring_begin_use, | |
1777 | .end_use = amdgpu_uvd_ring_end_use, | |
b6cb3b5c | 1778 | .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, |
38d32a75 | 1779 | .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, |
1ab0c9a7 | 1780 | .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, |
09bfb891 LL |
1781 | }; |
1782 | ||
1783 | static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) | |
1784 | { | |
10dd74ea JZ |
1785 | int i; |
1786 | ||
1787 | for (i = 0; i < adev->uvd.num_uvd_inst; i++) { | |
1788 | adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; | |
1789 | adev->uvd.inst[i].ring.me = i; | |
1790 | DRM_INFO("UVD(%d) is enabled in VM mode\n", i); | |
1791 | } | |
09bfb891 LL |
1792 | } |
1793 | ||
1794 | static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) | |
1795 | { | |
10dd74ea | 1796 | int i, j; |
09bfb891 | 1797 | |
10dd74ea JZ |
1798 | for (j = 0; j < adev->uvd.num_uvd_inst; j++) { |
1799 | for (i = 0; i < adev->uvd.num_enc_rings; ++i) { | |
1800 | adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; | |
1801 | adev->uvd.inst[j].ring_enc[i].me = j; | |
1802 | } | |
09bfb891 | 1803 | |
10dd74ea JZ |
1804 | DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); |
1805 | } | |
09bfb891 LL |
1806 | } |
1807 | ||
1808 | static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { | |
1809 | .set = uvd_v7_0_set_interrupt_state, | |
1810 | .process = uvd_v7_0_process_interrupt, | |
1811 | }; | |
1812 | ||
1813 | static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) | |
1814 | { | |
10dd74ea JZ |
1815 | int i; |
1816 | ||
1817 | for (i = 0; i < adev->uvd.num_uvd_inst; i++) { | |
1818 | adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; | |
1819 | adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; | |
1820 | } | |
09bfb891 LL |
1821 | } |
1822 | ||
1823 | const struct amdgpu_ip_block_version uvd_v7_0_ip_block = | |
1824 | { | |
1825 | .type = AMD_IP_BLOCK_TYPE_UVD, | |
1826 | .major = 7, | |
1827 | .minor = 0, | |
1828 | .rev = 0, | |
1829 | .funcs = &uvd_v7_0_ip_funcs, | |
1830 | }; |