projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu: Skip uvd and vce ring test for SRIOV
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / uvd_v7_0.c
CommitLineData
09bfb891
LL		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_uvd.h"
28#include "soc15d.h"
29#include "soc15_common.h"
247ac951 30#include "mmsch_v1_0.h"
09bfb891
LL		 31
32#include "vega10/soc15ip.h"
33#include "vega10/UVD/uvd_7_0_offset.h"
34#include "vega10/UVD/uvd_7_0_sh_mask.h"
247ac951
FM		 35#include "vega10/VCE/vce_4_0_offset.h"
36#include "vega10/VCE/vce_4_0_default.h"
37#include "vega10/VCE/vce_4_0_sh_mask.h"
09bfb891
LL		 38#include "vega10/NBIF/nbif_6_1_offset.h"
39#include "vega10/HDP/hdp_4_0_offset.h"
40#include "vega10/MMHUB/mmhub_1_0_offset.h"
41#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
42
43static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
44static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
45static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
46static int uvd_v7_0_start(struct amdgpu_device *adev);
47static void uvd_v7_0_stop(struct amdgpu_device *adev);
247ac951 48static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
09bfb891
LL		 49
50/**
51 * uvd_v7_0_ring_get_rptr - get read pointer
52 *
53 * @ring: amdgpu_ring pointer
54 *
55 * Returns the current hardware read pointer
56 */
57static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
58{
59 struct amdgpu_device *adev = ring->adev;
60
4ad5751a 61 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
09bfb891
LL		 62}
63
64/**
65 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
66 *
67 * @ring: amdgpu_ring pointer
68 *
69 * Returns the current hardware enc read pointer
70 */
71static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
72{
73 struct amdgpu_device *adev = ring->adev;
74
75 if (ring == &adev->uvd.ring_enc[0])
4ad5751a 76 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
09bfb891 77 else
4ad5751a 78 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
09bfb891
LL		 79}
80
81/**
82 * uvd_v7_0_ring_get_wptr - get write pointer
83 *
84 * @ring: amdgpu_ring pointer
85 *
86 * Returns the current hardware write pointer
87 */
88static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
89{
90 struct amdgpu_device *adev = ring->adev;
91
4ad5751a 92 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
09bfb891
LL		 93}
94
95/**
96 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
97 *
98 * @ring: amdgpu_ring pointer
99 *
100 * Returns the current hardware enc write pointer
101 */
102static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
103{
104 struct amdgpu_device *adev = ring->adev;
105
beb2ced5
FM		 106 if (ring->use_doorbell)
107 return adev->wb.wb[ring->wptr_offs];
108
09bfb891 109 if (ring == &adev->uvd.ring_enc[0])
4ad5751a 110 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
09bfb891 111 else
4ad5751a 112 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
09bfb891
LL		 113}
114
115/**
116 * uvd_v7_0_ring_set_wptr - set write pointer
117 *
118 * @ring: amdgpu_ring pointer
119 *
120 * Commits the write pointer to the hardware
121 */
122static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
123{
124 struct amdgpu_device *adev = ring->adev;
125
4ad5751a 126 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
09bfb891
LL		 127}
128
129/**
130 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
131 *
132 * @ring: amdgpu_ring pointer
133 *
134 * Commits the enc write pointer to the hardware
135 */
136static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
137{
138 struct amdgpu_device *adev = ring->adev;
139
beb2ced5
FM		 140 if (ring->use_doorbell) {
141 /* XXX check if swapping is necessary on BE */
142 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
143 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
144 return;
145 }
146
09bfb891 147 if (ring == &adev->uvd.ring_enc[0])
4ad5751a 148 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
09bfb891
LL		 149 lower_32_bits(ring->wptr));
150 else
4ad5751a 151 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
09bfb891
LL		 152 lower_32_bits(ring->wptr));
153}
154
155/**
156 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
157 *
158 * @ring: the engine to test on
159 *
160 */
161static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
162{
163 struct amdgpu_device *adev = ring->adev;
164 uint32_t rptr = amdgpu_ring_get_rptr(ring);
165 unsigned i;
166 int r;
167
a1b9022a
FM		 168 if (amdgpu_sriov_vf(adev))
169 return 0;
170
09bfb891
LL		 171 r = amdgpu_ring_alloc(ring, 16);
172 if (r) {
173 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
174 ring->idx, r);
175 return r;
176 }
177 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
178 amdgpu_ring_commit(ring);
179
180 for (i = 0; i < adev->usec_timeout; i++) {
181 if (amdgpu_ring_get_rptr(ring) != rptr)
182 break;
183 DRM_UDELAY(1);
184 }
185
186 if (i < adev->usec_timeout) {
187 DRM_INFO("ring test on %d succeeded in %d usecs\n",
188 ring->idx, i);
189 } else {
190 DRM_ERROR("amdgpu: ring %d test failed\n",
191 ring->idx);
192 r = -ETIMEDOUT;
193 }
194
195 return r;
196}
197
198/**
199 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
200 *
201 * @adev: amdgpu_device pointer
202 * @ring: ring we should submit the msg to
203 * @handle: session handle to use
204 * @fence: optional fence to return
205 *
206 * Open up a stream for HW test
207 */
208static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
209 struct dma_fence **fence)
210{
211 const unsigned ib_size_dw = 16;
212 struct amdgpu_job *job;
213 struct amdgpu_ib *ib;
214 struct dma_fence *f = NULL;
215 uint64_t dummy;
216 int i, r;
217
218 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
219 if (r)
220 return r;
221
222 ib = &job->ibs[0];
223 dummy = ib->gpu_addr + 1024;
224
225 ib->length_dw = 0;
226 ib->ptr[ib->length_dw++] = 0x00000018;
227 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
228 ib->ptr[ib->length_dw++] = handle;
229 ib->ptr[ib->length_dw++] = 0x00000000;
230 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
231 ib->ptr[ib->length_dw++] = dummy;
232
233 ib->ptr[ib->length_dw++] = 0x00000014;
234 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
235 ib->ptr[ib->length_dw++] = 0x0000001c;
236 ib->ptr[ib->length_dw++] = 0x00000000;
237 ib->ptr[ib->length_dw++] = 0x00000000;
238
239 ib->ptr[ib->length_dw++] = 0x00000008;
240 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
241
242 for (i = ib->length_dw; i < ib_size_dw; ++i)
243 ib->ptr[i] = 0x0;
244
245 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
246 job->fence = dma_fence_get(f);
247 if (r)
248 goto err;
249
250 amdgpu_job_free(job);
251 if (fence)
252 *fence = dma_fence_get(f);
253 dma_fence_put(f);
254 return 0;
255
256err:
257 amdgpu_job_free(job);
258 return r;
259}
260
261/**
262 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
263 *
264 * @adev: amdgpu_device pointer
265 * @ring: ring we should submit the msg to
266 * @handle: session handle to use
267 * @fence: optional fence to return
268 *
269 * Close up a stream for HW test or if userspace failed to do so
270 */
271int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
272 bool direct, struct dma_fence **fence)
273{
274 const unsigned ib_size_dw = 16;
275 struct amdgpu_job *job;
276 struct amdgpu_ib *ib;
277 struct dma_fence *f = NULL;
278 uint64_t dummy;
279 int i, r;
280
281 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
282 if (r)
283 return r;
284
285 ib = &job->ibs[0];
286 dummy = ib->gpu_addr + 1024;
287
288 ib->length_dw = 0;
289 ib->ptr[ib->length_dw++] = 0x00000018;
290 ib->ptr[ib->length_dw++] = 0x00000001;
291 ib->ptr[ib->length_dw++] = handle;
292 ib->ptr[ib->length_dw++] = 0x00000000;
293 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
294 ib->ptr[ib->length_dw++] = dummy;
295
296 ib->ptr[ib->length_dw++] = 0x00000014;
297 ib->ptr[ib->length_dw++] = 0x00000002;
298 ib->ptr[ib->length_dw++] = 0x0000001c;
299 ib->ptr[ib->length_dw++] = 0x00000000;
300 ib->ptr[ib->length_dw++] = 0x00000000;
301
302 ib->ptr[ib->length_dw++] = 0x00000008;
303 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
304
305 for (i = ib->length_dw; i < ib_size_dw; ++i)
306 ib->ptr[i] = 0x0;
307
308 if (direct) {
309 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
310 job->fence = dma_fence_get(f);
311 if (r)
312 goto err;
313
314 amdgpu_job_free(job);
315 } else {
316 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
317 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
318 if (r)
319 goto err;
320 }
321
322 if (fence)
323 *fence = dma_fence_get(f);
324 dma_fence_put(f);
325 return 0;
326
327err:
328 amdgpu_job_free(job);
329 return r;
330}
331
332/**
333 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
334 *
335 * @ring: the engine to test on
336 *
337 */
338static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
339{
340 struct dma_fence *fence = NULL;
341 long r;
342
343 r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
344 if (r) {
345 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
346 goto error;
347 }
348
349 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
350 if (r) {
351 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
352 goto error;
353 }
354
355 r = dma_fence_wait_timeout(fence, false, timeout);
356 if (r == 0) {
357 DRM_ERROR("amdgpu: IB test timed out.\n");
358 r = -ETIMEDOUT;
359 } else if (r < 0) {
360 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
361 } else {
362 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
363 r = 0;
364 }
365error:
366 dma_fence_put(fence);
367 return r;
368}
369
370static int uvd_v7_0_early_init(void *handle)
371{
372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
373
6fa336a7
FM		 374 if (amdgpu_sriov_vf(adev))
375 adev->uvd.num_enc_rings = 1;
376 else
377 adev->uvd.num_enc_rings = 2;
09bfb891
LL		 378 uvd_v7_0_set_ring_funcs(adev);
379 uvd_v7_0_set_enc_ring_funcs(adev);
380 uvd_v7_0_set_irq_funcs(adev);
381
382 return 0;
383}
384
385static int uvd_v7_0_sw_init(void *handle)
386{
387 struct amdgpu_ring *ring;
388 struct amd_sched_rq *rq;
389 int i, r;
390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
391
392 /* UVD TRAP */
393 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
394 if (r)
395 return r;
396
397 /* UVD ENC TRAP */
398 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
399 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
400 if (r)
401 return r;
402 }
403
404 r = amdgpu_uvd_sw_init(adev);
405 if (r)
406 return r;
407
408 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
409 const struct common_firmware_header *hdr;
410 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
411 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
412 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
413 adev->firmware.fw_size +=
414 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
415 DRM_INFO("PSP loading UVD firmware\n");
416 }
417
418 ring = &adev->uvd.ring_enc[0];
419 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
420 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
421 rq, amdgpu_sched_jobs);
422 if (r) {
423 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
424 return r;
425 }
426
427 r = amdgpu_uvd_resume(adev);
428 if (r)
429 return r;
6fa336a7
FM		 430 if (!amdgpu_sriov_vf(adev)) {
431 ring = &adev->uvd.ring;
432 sprintf(ring->name, "uvd");
433 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
434 if (r)
435 return r;
436 }
09bfb891 437
09bfb891
LL		 438
439 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
440 ring = &adev->uvd.ring_enc[i];
441 sprintf(ring->name, "uvd_enc%d", i);
beb2ced5
FM		 442 if (amdgpu_sriov_vf(adev)) {
443 ring->use_doorbell = true;
444 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
445 }
09bfb891
LL		 446 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
447 if (r)
448 return r;
449 }
450
6fa336a7
FM		 451 r = amdgpu_virt_alloc_mm_table(adev);
452 if (r)
453 return r;
454
09bfb891
LL		 455 return r;
456}
457
458static int uvd_v7_0_sw_fini(void *handle)
459{
460 int i, r;
461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
462
6fa336a7
FM		 463 amdgpu_virt_free_mm_table(adev);
464
09bfb891
LL		 465 r = amdgpu_uvd_suspend(adev);
466 if (r)
467 return r;
468
469 amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
470
471 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
472 amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
473
50237287 474 return amdgpu_uvd_sw_fini(adev);
09bfb891
LL		 475}
476
477/**
478 * uvd_v7_0_hw_init - start and test UVD block
479 *
480 * @adev: amdgpu_device pointer
481 *
482 * Initialize the hardware, boot up the VCPU and do some testing
483 */
484static int uvd_v7_0_hw_init(void *handle)
485{
486 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
487 struct amdgpu_ring *ring = &adev->uvd.ring;
488 uint32_t tmp;
489 int i, r;
490
6fa336a7
FM		 491 if (amdgpu_sriov_vf(adev))
492 r = uvd_v7_0_sriov_start(adev);
493 else
494 r = uvd_v7_0_start(adev);
09bfb891
LL		 495 if (r)
496 goto done;
497
6fa336a7
FM		 498 if (!amdgpu_sriov_vf(adev)) {
499 ring->ready = true;
500 r = amdgpu_ring_test_ring(ring);
501 if (r) {
502 ring->ready = false;
503 goto done;
504 }
09bfb891 505
6fa336a7
FM		 506 r = amdgpu_ring_alloc(ring, 10);
507 if (r) {
508 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
509 goto done;
510 }
09bfb891 511
6fa336a7
FM		 512 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
513 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
514 amdgpu_ring_write(ring, tmp);
515 amdgpu_ring_write(ring, 0xFFFFF);
09bfb891 516
6fa336a7
FM		 517 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
518 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
519 amdgpu_ring_write(ring, tmp);
520 amdgpu_ring_write(ring, 0xFFFFF);
09bfb891 521
6fa336a7
FM		 522 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
523 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
524 amdgpu_ring_write(ring, tmp);
525 amdgpu_ring_write(ring, 0xFFFFF);
09bfb891 526
6fa336a7
FM		 527 /* Clear timeout status bits */
528 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
529 mmUVD_SEMA_TIMEOUT_STATUS), 0));
530 amdgpu_ring_write(ring, 0x8);
09bfb891 531
6fa336a7
FM		 532 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
533 mmUVD_SEMA_CNTL), 0));
534 amdgpu_ring_write(ring, 3);
09bfb891 535
6fa336a7
FM		 536 amdgpu_ring_commit(ring);
537 }
09bfb891
LL		 538
539 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
540 ring = &adev->uvd.ring_enc[i];
541 ring->ready = true;
542 r = amdgpu_ring_test_ring(ring);
543 if (r) {
544 ring->ready = false;
545 goto done;
546 }
547 }
548
549done:
550 if (!r)
551 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
552
553 return r;
554}
555
556/**
557 * uvd_v7_0_hw_fini - stop the hardware block
558 *
559 * @adev: amdgpu_device pointer
560 *
561 * Stop the UVD block, mark ring as not ready any more
562 */
563static int uvd_v7_0_hw_fini(void *handle)
564{
565 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
566 struct amdgpu_ring *ring = &adev->uvd.ring;
567
5dd696ae
TH		 568 if (!amdgpu_sriov_vf(adev))
569 uvd_v7_0_stop(adev);
570 else {
571 /* full access mode, so don't touch any UVD register */
572 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
573 }
574
09bfb891
LL		 575 ring->ready = false;
576
577 return 0;
578}
579
580static int uvd_v7_0_suspend(void *handle)
581{
582 int r;
583 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
584
585 r = uvd_v7_0_hw_fini(adev);
586 if (r)
587 return r;
588
589 /* Skip this for APU for now */
50237287 590 if (!(adev->flags & AMD_IS_APU))
09bfb891 591 r = amdgpu_uvd_suspend(adev);
09bfb891
LL		 592
593 return r;
594}
595
596static int uvd_v7_0_resume(void *handle)
597{
598 int r;
599 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
600
601 /* Skip this for APU for now */
602 if (!(adev->flags & AMD_IS_APU)) {
603 r = amdgpu_uvd_resume(adev);
604 if (r)
605 return r;
606 }
50237287 607 return uvd_v7_0_hw_init(adev);
09bfb891
LL		 608}
609
610/**
611 * uvd_v7_0_mc_resume - memory controller programming
612 *
613 * @adev: amdgpu_device pointer
614 *
615 * Let the UVD memory controller know it's offsets
616 */
617static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
618{
619 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
620 uint32_t offset;
621
622 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4ad5751a 623 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
09bfb891 624 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
4ad5751a 625 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
09bfb891
LL		 626 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
627 offset = 0;
628 } else {
4ad5751a 629 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
09bfb891 630 lower_32_bits(adev->uvd.gpu_addr));
4ad5751a 631 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
09bfb891
LL		 632 upper_32_bits(adev->uvd.gpu_addr));
633 offset = size;
634 }
635
4ad5751a 636 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
09bfb891 637 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
4ad5751a 638 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
09bfb891 639
4ad5751a 640 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
09bfb891 641 lower_32_bits(adev->uvd.gpu_addr + offset));
4ad5751a 642 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
09bfb891 643 upper_32_bits(adev->uvd.gpu_addr + offset));
4ad5751a
TSD		 644 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
645 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
09bfb891 646
4ad5751a 647 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
09bfb891 648 lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
4ad5751a 649 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
09bfb891 650 upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
4ad5751a
TSD		 651 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
652 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
09bfb891
LL		 653 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
654
4ad5751a 655 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
09bfb891 656 adev->gfx.config.gb_addr_config);
4ad5751a 657 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
09bfb891 658 adev->gfx.config.gb_addr_config);
4ad5751a 659 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
09bfb891
LL		 660 adev->gfx.config.gb_addr_config);
661
4ad5751a 662 WREG32_SOC15(UVD, 0, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
09bfb891
LL		 663}
664
247ac951
FM		 665static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
666 struct amdgpu_mm_table *table)
667{
668 uint32_t data = 0, loop;
669 uint64_t addr = table->gpu_addr;
670 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
671 uint32_t size;
672
673 size = header->header_size + header->vce_table_size + header->uvd_table_size;
674
675 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
4ad5751a
TSD		 676 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
677 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
247ac951
FM		 678
679 /* 2, update vmid of descriptor */
4ad5751a 680 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
247ac951
FM		 681 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
682 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
4ad5751a 683 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
247ac951
FM		 684
685 /* 3, notify mmsch about the size of this descriptor */
4ad5751a 686 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
247ac951
FM		 687
688 /* 4, set resp to zero */
4ad5751a 689 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
247ac951 690
ab2b2e4f
FM		 691 WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
692 adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
693 adev->uvd.ring_enc[0].wptr = 0;
694 adev->uvd.ring_enc[0].wptr_old = 0;
695
247ac951 696 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
4ad5751a 697 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
247ac951 698
4ad5751a 699 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
247ac951
FM		 700 loop = 1000;
701 while ((data & 0x10000002) != 0x10000002) {
702 udelay(10);
4ad5751a 703 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
247ac951
FM		 704 loop--;
705 if (!loop)
706 break;
707 }
708
709 if (!loop) {
710 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
711 return -EBUSY;
712 }
713
714 return 0;
715}
716
717static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
718{
719 struct amdgpu_ring *ring;
720 uint32_t offset, size, tmp;
721 uint32_t table_size = 0;
722 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
723 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
724 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
247ac951
FM		 725 struct mmsch_v1_0_cmd_end end = { {0} };
726 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
727 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
728
729 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
730 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
731 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
732 end.cmd_header.command_type = MMSCH_COMMAND__END;
733
734 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
735 header->version = MMSCH_VERSION;
736 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
737
738 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
739 header->uvd_table_offset = header->header_size;
740 else
741 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
742
743 init_table += header->uvd_table_offset;
744
745 ring = &adev->uvd.ring;
746 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
747
748 /* disable clock gating */
749 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
750 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0);
751 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
752 0xFFFFFFFF, 0x00000004);
753 /* mc resume*/
754 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
755 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
756 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
757 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
758 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
759 offset = 0;
760 } else {
761 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
762 lower_32_bits(adev->uvd.gpu_addr));
763 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
764 upper_32_bits(adev->uvd.gpu_addr));
765 offset = size;
766 }
767
768 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
769 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
770 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
771
772 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
773 lower_32_bits(adev->uvd.gpu_addr + offset));
774 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
775 upper_32_bits(adev->uvd.gpu_addr + offset));
776 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
777 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
778
779 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
780 lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
781 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
782 upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
783 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
784 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
785 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
786
787 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
788 adev->gfx.config.gb_addr_config);
789 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG),
790 adev->gfx.config.gb_addr_config);
791 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG),
792 adev->gfx.config.gb_addr_config);
793 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
794 /* mc resume end*/
795
796 /* disable clock gating */
797 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL),
798 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
799
800 /* disable interupt */
801 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
802 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
803
804 /* stall UMC and register bus before resetting VCPU */
805 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
806 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
807 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
808
809 /* put LMI, VCPU, RBC etc... into reset */
810 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
811 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
812 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
813 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
814 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
815 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
816 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
817 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
818 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
819
820 /* initialize UVD memory controller */
821 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
822 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
823 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
824 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
825 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
826 UVD_LMI_CTRL__REQ_MODE_MASK |
827 0x00100000L));
828
829 /* disable byte swapping */
830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), 0);
831 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), 0);
832
833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040);
834 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0);
835 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040);
836 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0);
837 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0);
838 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88);
839
840 /* take all subblocks out of reset, except VCPU */
841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
842 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
843
844 /* enable VCPU clock */
845 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
846 UVD_VCPU_CNTL__CLK_EN_MASK);
847
848 /* enable UMC */
849 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
850 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
851
852 /* boot up the VCPU */
853 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
854
855 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02);
856
857 /* enable master interrupt */
858 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
859 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
860 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
861
862 /* clear the bit 4 of UVD_STATUS */
863 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
864 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
865
866 /* force RBC into idle state */
867 size = order_base_2(ring->ring_size);
868 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
869 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
870 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
871 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
872 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
873 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
874 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
875
876 /* set the write pointer delay */
877 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0);
878
879 /* set the wb address */
880 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR),
881 (upper_32_bits(ring->gpu_addr) >> 2));
882
883 /* programm the RB_BASE for ring buffer */
884 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
885 lower_32_bits(ring->gpu_addr));
886 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
887 upper_32_bits(ring->gpu_addr));
888
889 ring->wptr = 0;
890 ring = &adev->uvd.ring_enc[0];
891 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
892 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
893 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
894
247ac951
FM		 895 /* add end packet */
896 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
897 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
898 header->uvd_table_size = table_size;
899
247ac951 900 }
257deb8c 901 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
247ac951
FM		 902}
903
09bfb891
LL		 904/**
905 * uvd_v7_0_start - start UVD block
906 *
907 * @adev: amdgpu_device pointer
908 *
909 * Setup and start the UVD block
910 */
911static int uvd_v7_0_start(struct amdgpu_device *adev)
912{
913 struct amdgpu_ring *ring = &adev->uvd.ring;
914 uint32_t rb_bufsz, tmp;
915 uint32_t lmi_swap_cntl;
916 uint32_t mp_swap_cntl;
917 int i, j, r;
918
919 /* disable DPG */
920 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
921 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
922
923 /* disable byte swapping */
924 lmi_swap_cntl = 0;
925 mp_swap_cntl = 0;
926
927 uvd_v7_0_mc_resume(adev);
928
929 /* disable clock gating */
930 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
931 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
932
933 /* disable interupt */
934 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
935 ~UVD_MASTINT_EN__VCPU_EN_MASK);
936
937 /* stall UMC and register bus before resetting VCPU */
938 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
939 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
940 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
941 mdelay(1);
942
943 /* put LMI, VCPU, RBC etc... into reset */
4ad5751a 944 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
09bfb891
LL		 945 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
946 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
947 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
948 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
949 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
950 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
951 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
952 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
953 mdelay(5);
954
955 /* initialize UVD memory controller */
4ad5751a 956 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
09bfb891
LL		 957 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
958 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
959 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
960 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
961 UVD_LMI_CTRL__REQ_MODE_MASK |
962 0x00100000L);
963
964#ifdef __BIG_ENDIAN
965 /* swap (8 in 32) RB and IB */
966 lmi_swap_cntl = 0xa;
967 mp_swap_cntl = 0;
968#endif
4ad5751a
TSD		 969 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
970 WREG32_SOC15(UVD, 0, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
09bfb891 971
4ad5751a
TSD		 972 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
973 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
974 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
975 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
976 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
977 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
09bfb891
LL		 978
979 /* take all subblocks out of reset, except VCPU */
4ad5751a 980 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
09bfb891
LL		 981 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
982 mdelay(5);
983
984 /* enable VCPU clock */
4ad5751a 985 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
09bfb891
LL		 986 UVD_VCPU_CNTL__CLK_EN_MASK);
987
988 /* enable UMC */
989 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
990 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
991
992 /* boot up the VCPU */
4ad5751a 993 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
09bfb891
LL		 994 mdelay(10);
995
996 for (i = 0; i < 10; ++i) {
997 uint32_t status;
998
999 for (j = 0; j < 100; ++j) {
4ad5751a 1000 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
09bfb891
LL		 1001 if (status & 2)
1002 break;
1003 mdelay(10);
1004 }
1005 r = 0;
1006 if (status & 2)
1007 break;
1008
1009 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
1010 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1011 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1012 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1013 mdelay(10);
1014 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1015 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1016 mdelay(10);
1017 r = -1;
1018 }
1019
1020 if (r) {
1021 DRM_ERROR("UVD not responding, giving up!!!\n");
1022 return r;
1023 }
1024 /* enable master interrupt */
1025 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1026 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1027 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1028
1029 /* clear the bit 4 of UVD_STATUS */
1030 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1031 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1032
1033 /* force RBC into idle state */
1034 rb_bufsz = order_base_2(ring->ring_size);
1035 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1036 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1037 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1038 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1039 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1040 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
4ad5751a 1041 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
09bfb891
LL		 1042
1043 /* set the write pointer delay */
4ad5751a 1044 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
09bfb891
LL		 1045
1046 /* set the wb address */
4ad5751a 1047 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
09bfb891
LL		 1048 (upper_32_bits(ring->gpu_addr) >> 2));
1049
1050 /* programm the RB_BASE for ring buffer */
4ad5751a 1051 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
09bfb891 1052 lower_32_bits(ring->gpu_addr));
4ad5751a 1053 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
09bfb891
LL		 1054 upper_32_bits(ring->gpu_addr));
1055
1056 /* Initialize the ring buffer's read and write pointers */
4ad5751a 1057 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
09bfb891 1058
4ad5751a
TSD		 1059 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1060 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
09bfb891
LL		 1061 lower_32_bits(ring->wptr));
1062
1063 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1064 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1065
1066 ring = &adev->uvd.ring_enc[0];
4ad5751a
TSD		 1067 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1068 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1069 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1070 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1071 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
09bfb891
LL		 1072
1073 ring = &adev->uvd.ring_enc[1];
4ad5751a
TSD		 1074 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1075 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1076 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1077 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1078 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
09bfb891
LL		 1079
1080 return 0;
1081}
1082
1083/**
1084 * uvd_v7_0_stop - stop UVD block
1085 *
1086 * @adev: amdgpu_device pointer
1087 *
1088 * stop the UVD block
1089 */
1090static void uvd_v7_0_stop(struct amdgpu_device *adev)
1091{
1092 /* force RBC into idle state */
4ad5751a 1093 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
09bfb891
LL		 1094
1095 /* Stall UMC and register bus before resetting VCPU */
1096 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1097 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1098 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1099 mdelay(1);
1100
1101 /* put VCPU into reset */
4ad5751a 1102 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
09bfb891
LL		 1103 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1104 mdelay(5);
1105
1106 /* disable VCPU clock */
4ad5751a 1107 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
09bfb891
LL		 1108
1109 /* Unstall UMC and register bus */
1110 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1111 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1112}
1113
1114/**
1115 * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1116 *
1117 * @ring: amdgpu_ring pointer
1118 * @fence: fence to emit
1119 *
1120 * Write a fence and a trap command to the ring.
1121 */
1122static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1123 unsigned flags)
1124{
1125 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1126
1127 amdgpu_ring_write(ring,
1128 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1129 amdgpu_ring_write(ring, seq);
1130 amdgpu_ring_write(ring,
1131 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1132 amdgpu_ring_write(ring, addr & 0xffffffff);
1133 amdgpu_ring_write(ring,
1134 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1135 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1136 amdgpu_ring_write(ring,
1137 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1138 amdgpu_ring_write(ring, 0);
1139
1140 amdgpu_ring_write(ring,
1141 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1142 amdgpu_ring_write(ring, 0);
1143 amdgpu_ring_write(ring,
1144 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1145 amdgpu_ring_write(ring, 0);
1146 amdgpu_ring_write(ring,
1147 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1148 amdgpu_ring_write(ring, 2);
1149}
1150
1151/**
1152 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1153 *
1154 * @ring: amdgpu_ring pointer
1155 * @fence: fence to emit
1156 *
1157 * Write enc a fence and a trap command to the ring.
1158 */
1159static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1160 u64 seq, unsigned flags)
1161{
1162 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1163
1164 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1165 amdgpu_ring_write(ring, addr);
1166 amdgpu_ring_write(ring, upper_32_bits(addr));
1167 amdgpu_ring_write(ring, seq);
1168 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1169}
1170
1171/**
1172 * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush
1173 *
1174 * @ring: amdgpu_ring pointer
1175 *
1176 * Emits an hdp flush.
1177 */
1178static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1179{
1180 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
1181 mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
1182 amdgpu_ring_write(ring, 0);
1183}
1184
1185/**
1186 * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate
1187 *
1188 * @ring: amdgpu_ring pointer
1189 *
1190 * Emits an hdp invalidate.
1191 */
1192static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1193{
1194 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
1195 amdgpu_ring_write(ring, 1);
1196}
1197
1198/**
1199 * uvd_v7_0_ring_test_ring - register write test
1200 *
1201 * @ring: amdgpu_ring pointer
1202 *
1203 * Test if we can successfully write to the context register
1204 */
1205static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1206{
1207 struct amdgpu_device *adev = ring->adev;
1208 uint32_t tmp = 0;
1209 unsigned i;
1210 int r;
1211
4ad5751a 1212 WREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
09bfb891
LL		 1213 r = amdgpu_ring_alloc(ring, 3);
1214 if (r) {
1215 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
1216 ring->idx, r);
1217 return r;
1218 }
1219 amdgpu_ring_write(ring,
1220 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1221 amdgpu_ring_write(ring, 0xDEADBEEF);
1222 amdgpu_ring_commit(ring);
1223 for (i = 0; i < adev->usec_timeout; i++) {
4ad5751a 1224 tmp = RREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID);
09bfb891
LL		 1225 if (tmp == 0xDEADBEEF)
1226 break;
1227 DRM_UDELAY(1);
1228 }
1229
1230 if (i < adev->usec_timeout) {
1231 DRM_INFO("ring test on %d succeeded in %d usecs\n",
1232 ring->idx, i);
1233 } else {
1234 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1235 ring->idx, tmp);
1236 r = -EINVAL;
1237 }
1238 return r;
1239}
1240
1241/**
1242 * uvd_v7_0_ring_emit_ib - execute indirect buffer
1243 *
1244 * @ring: amdgpu_ring pointer
1245 * @ib: indirect buffer to execute
1246 *
1247 * Write ring commands to execute the indirect buffer
1248 */
1249static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1250 struct amdgpu_ib *ib,
1251 unsigned vm_id, bool ctx_switch)
1252{
1253 amdgpu_ring_write(ring,
1254 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1255 amdgpu_ring_write(ring, vm_id);
1256
1257 amdgpu_ring_write(ring,
1258 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1260 amdgpu_ring_write(ring,
1261 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1262 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1263 amdgpu_ring_write(ring,
1264 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1265 amdgpu_ring_write(ring, ib->length_dw);
1266}
1267
1268/**
1269 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1270 *
1271 * @ring: amdgpu_ring pointer
1272 * @ib: indirect buffer to execute
1273 *
1274 * Write enc ring commands to execute the indirect buffer
1275 */
1276static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1277 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
1278{
1279 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1280 amdgpu_ring_write(ring, vm_id);
1281 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1282 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1283 amdgpu_ring_write(ring, ib->length_dw);
1284}
1285
1286static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
1287 uint32_t data0, uint32_t data1)
1288{
1289 amdgpu_ring_write(ring,
1290 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1291 amdgpu_ring_write(ring, data0);
1292 amdgpu_ring_write(ring,
1293 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1294 amdgpu_ring_write(ring, data1);
1295 amdgpu_ring_write(ring,
1296 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1297 amdgpu_ring_write(ring, 8);
1298}
1299
1300static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
1301 uint32_t data0, uint32_t data1, uint32_t mask)
1302{
1303 amdgpu_ring_write(ring,
1304 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1305 amdgpu_ring_write(ring, data0);
1306 amdgpu_ring_write(ring,
1307 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1308 amdgpu_ring_write(ring, data1);
1309 amdgpu_ring_write(ring,
1310 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1311 amdgpu_ring_write(ring, mask);
1312 amdgpu_ring_write(ring,
1313 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1314 amdgpu_ring_write(ring, 12);
1315}
1316
1317static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1318 unsigned vm_id, uint64_t pd_addr)
1319{
2e819849 1320 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
03f89feb 1321 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
09bfb891 1322 uint32_t data0, data1, mask;
4789c463 1323 unsigned eng = ring->vm_inv_eng;
09bfb891 1324
b1166325
CK		 1325 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1326 pd_addr |= AMDGPU_PTE_VALID;
09bfb891 1327
2e819849
CK		 1328 data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
1329 data1 = upper_32_bits(pd_addr);
1330 uvd_v7_0_vm_reg_write(ring, data0, data1);
1331
1332 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1333 data1 = lower_32_bits(pd_addr);
1334 uvd_v7_0_vm_reg_write(ring, data0, data1);
1335
1336 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1337 data1 = lower_32_bits(pd_addr);
1338 mask = 0xffffffff;
1339 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1340
1341 /* flush TLB */
1342 data0 = (hub->vm_inv_eng0_req + eng) << 2;
1343 data1 = req;
1344 uvd_v7_0_vm_reg_write(ring, data0, data1);
1345
1346 /* wait for flush */
1347 data0 = (hub->vm_inv_eng0_ack + eng) << 2;
1348 data1 = 1 << vm_id;
1349 mask = 1 << vm_id;
1350 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
09bfb891
LL		 1351}
1352
1353static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1354{
1355 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1356}
1357
1358static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1359 unsigned int vm_id, uint64_t pd_addr)
1360{
2e819849 1361 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
03f89feb 1362 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 1363 unsigned eng = ring->vm_inv_eng;
09bfb891 1364
b1166325
CK		 1365 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1366 pd_addr |= AMDGPU_PTE_VALID;
09bfb891 1367
2e819849
CK		 1368 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1369 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
1370 amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1371
1372 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1373 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1374 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1375
1376 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1377 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1378 amdgpu_ring_write(ring, 0xffffffff);
1379 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1380
1381 /* flush TLB */
1382 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1383 amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2);
1384 amdgpu_ring_write(ring, req);
1385
1386 /* wait for flush */
1387 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1388 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1389 amdgpu_ring_write(ring, 1 << vm_id);
1390 amdgpu_ring_write(ring, 1 << vm_id);
09bfb891
LL		 1391}
1392
1393#if 0
1394static bool uvd_v7_0_is_idle(void *handle)
1395{
1396 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1397
1398 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1399}
1400
1401static int uvd_v7_0_wait_for_idle(void *handle)
1402{
1403 unsigned i;
1404 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1405
1406 for (i = 0; i < adev->usec_timeout; i++) {
1407 if (uvd_v7_0_is_idle(handle))
1408 return 0;
1409 }
1410 return -ETIMEDOUT;
1411}
1412
1413#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd
1414static bool uvd_v7_0_check_soft_reset(void *handle)
1415{
1416 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1417 u32 srbm_soft_reset = 0;
1418 u32 tmp = RREG32(mmSRBM_STATUS);
1419
1420 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1421 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
4ad5751a
TSD		 1422 (RREG32_SOC15(UVD, 0, mmUVD_STATUS) &
1423 AMDGPU_UVD_STATUS_BUSY_MASK))
09bfb891
LL		 1424 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1425 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1426
1427 if (srbm_soft_reset) {
1428 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1429 return true;
1430 } else {
1431 adev->uvd.srbm_soft_reset = 0;
1432 return false;
1433 }
1434}
1435
1436static int uvd_v7_0_pre_soft_reset(void *handle)
1437{
1438 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1439
1440 if (!adev->uvd.srbm_soft_reset)
1441 return 0;
1442
1443 uvd_v7_0_stop(adev);
1444 return 0;
1445}
1446
1447static int uvd_v7_0_soft_reset(void *handle)
1448{
1449 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1450 u32 srbm_soft_reset;
1451
1452 if (!adev->uvd.srbm_soft_reset)
1453 return 0;
1454 srbm_soft_reset = adev->uvd.srbm_soft_reset;
1455
1456 if (srbm_soft_reset) {
1457 u32 tmp;
1458
1459 tmp = RREG32(mmSRBM_SOFT_RESET);
1460 tmp |= srbm_soft_reset;
1461 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1462 WREG32(mmSRBM_SOFT_RESET, tmp);
1463 tmp = RREG32(mmSRBM_SOFT_RESET);
1464
1465 udelay(50);
1466
1467 tmp &= ~srbm_soft_reset;
1468 WREG32(mmSRBM_SOFT_RESET, tmp);
1469 tmp = RREG32(mmSRBM_SOFT_RESET);
1470
1471 /* Wait a little for things to settle down */
1472 udelay(50);
1473 }
1474
1475 return 0;
1476}
1477
1478static int uvd_v7_0_post_soft_reset(void *handle)
1479{
1480 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1481
1482 if (!adev->uvd.srbm_soft_reset)
1483 return 0;
1484
1485 mdelay(5);
1486
1487 return uvd_v7_0_start(adev);
1488}
1489#endif
1490
1491static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1492 struct amdgpu_irq_src *source,
1493 unsigned type,
1494 enum amdgpu_interrupt_state state)
1495{
1496 // TODO
1497 return 0;
1498}
1499
1500static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1501 struct amdgpu_irq_src *source,
1502 struct amdgpu_iv_entry *entry)
1503{
1504 DRM_DEBUG("IH: UVD TRAP\n");
1505 switch (entry->src_id) {
1506 case 124:
1507 amdgpu_fence_process(&adev->uvd.ring);
1508 break;
1509 case 119:
1510 amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1511 break;
1512 case 120:
6fa336a7
FM		 1513 if (!amdgpu_sriov_vf(adev))
1514 amdgpu_fence_process(&adev->uvd.ring_enc[1]);
09bfb891
LL		 1515 break;
1516 default:
1517 DRM_ERROR("Unhandled interrupt: %d %d\n",
1518 entry->src_id, entry->src_data[0]);
1519 break;
1520 }
1521
1522 return 0;
1523}
1524
1525#if 0
1526static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1527{
1528 uint32_t data, data1, data2, suvd_flags;
1529
4ad5751a
TSD		 1530 data = RREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL);
1531 data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
1532 data2 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL);
09bfb891
LL		 1533
1534 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1535 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1536
1537 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1538 UVD_SUVD_CGC_GATE__SIT_MASK |
1539 UVD_SUVD_CGC_GATE__SMP_MASK |
1540 UVD_SUVD_CGC_GATE__SCM_MASK |
1541 UVD_SUVD_CGC_GATE__SDB_MASK;
1542
1543 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1544 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1545 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1546
1547 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1548 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1549 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1550 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1551 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1552 UVD_CGC_CTRL__SYS_MODE_MASK |
1553 UVD_CGC_CTRL__UDEC_MODE_MASK |
1554 UVD_CGC_CTRL__MPEG2_MODE_MASK |
1555 UVD_CGC_CTRL__REGS_MODE_MASK |
1556 UVD_CGC_CTRL__RBC_MODE_MASK |
1557 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1558 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1559 UVD_CGC_CTRL__IDCT_MODE_MASK |
1560 UVD_CGC_CTRL__MPRD_MODE_MASK |
1561 UVD_CGC_CTRL__MPC_MODE_MASK |
1562 UVD_CGC_CTRL__LBSI_MODE_MASK |
1563 UVD_CGC_CTRL__LRBBM_MODE_MASK |
1564 UVD_CGC_CTRL__WCB_MODE_MASK |
1565 UVD_CGC_CTRL__VCPU_MODE_MASK |
1566 UVD_CGC_CTRL__JPEG_MODE_MASK |
1567 UVD_CGC_CTRL__JPEG2_MODE_MASK |
1568 UVD_CGC_CTRL__SCPU_MODE_MASK);
1569 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1570 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1571 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1572 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1573 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1574 data1 |= suvd_flags;
1575
4ad5751a
TSD		 1576 WREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL, data);
1577 WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, 0);
1578 WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
1579 WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL, data2);
09bfb891
LL		 1580}
1581
1582static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1583{
1584 uint32_t data, data1, cgc_flags, suvd_flags;
1585
4ad5751a
TSD		 1586 data = RREG32_SOC15(UVD, 0, mmUVD_CGC_GATE);
1587 data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
09bfb891
LL		 1588
1589 cgc_flags = UVD_CGC_GATE__SYS_MASK |
1590 UVD_CGC_GATE__UDEC_MASK |
1591 UVD_CGC_GATE__MPEG2_MASK |
1592 UVD_CGC_GATE__RBC_MASK |
1593 UVD_CGC_GATE__LMI_MC_MASK |
1594 UVD_CGC_GATE__IDCT_MASK |
1595 UVD_CGC_GATE__MPRD_MASK |
1596 UVD_CGC_GATE__MPC_MASK |
1597 UVD_CGC_GATE__LBSI_MASK |
1598 UVD_CGC_GATE__LRBBM_MASK |
1599 UVD_CGC_GATE__UDEC_RE_MASK |
1600 UVD_CGC_GATE__UDEC_CM_MASK |
1601 UVD_CGC_GATE__UDEC_IT_MASK |
1602 UVD_CGC_GATE__UDEC_DB_MASK |
1603 UVD_CGC_GATE__UDEC_MP_MASK |
1604 UVD_CGC_GATE__WCB_MASK |
1605 UVD_CGC_GATE__VCPU_MASK |
1606 UVD_CGC_GATE__SCPU_MASK |
1607 UVD_CGC_GATE__JPEG_MASK |
1608 UVD_CGC_GATE__JPEG2_MASK;
1609
1610 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1611 UVD_SUVD_CGC_GATE__SIT_MASK |
1612 UVD_SUVD_CGC_GATE__SMP_MASK |
1613 UVD_SUVD_CGC_GATE__SCM_MASK |
1614 UVD_SUVD_CGC_GATE__SDB_MASK;
1615
1616 data |= cgc_flags;
1617 data1 |= suvd_flags;
1618
4ad5751a
TSD		 1619 WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, data);
1620 WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
09bfb891
LL		 1621}
1622
1623static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1624{
1625 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1626
1627 if (enable)
1628 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1629 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1630 else
1631 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1632 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1633
1634 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1635}
1636
1637
1638static int uvd_v7_0_set_clockgating_state(void *handle,
1639 enum amd_clockgating_state state)
1640{
1641 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1642 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1643
1644 uvd_v7_0_set_bypass_mode(adev, enable);
1645
1646 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1647 return 0;
1648
1649 if (enable) {
1650 /* disable HW gating and enable Sw gating */
1651 uvd_v7_0_set_sw_clock_gating(adev);
1652 } else {
1653 /* wait for STATUS to clear */
1654 if (uvd_v7_0_wait_for_idle(handle))
1655 return -EBUSY;
1656
1657 /* enable HW gates because UVD is idle */
1658 /* uvd_v7_0_set_hw_clock_gating(adev); */
1659 }
1660
1661 return 0;
1662}
1663
1664static int uvd_v7_0_set_powergating_state(void *handle,
1665 enum amd_powergating_state state)
1666{
1667 /* This doesn't actually powergate the UVD block.
1668 * That's done in the dpm code via the SMC. This
1669 * just re-inits the block as necessary. The actual
1670 * gating still happens in the dpm code. We should
1671 * revisit this when there is a cleaner line between
1672 * the smc and the hw blocks
1673 */
1674 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1675
1676 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1677 return 0;
1678
4ad5751a 1679 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
09bfb891
LL		 1680
1681 if (state == AMD_PG_STATE_GATE) {
1682 uvd_v7_0_stop(adev);
1683 return 0;
1684 } else {
1685 return uvd_v7_0_start(adev);
1686 }
1687}
1688#endif
1689
1690static int uvd_v7_0_set_clockgating_state(void *handle,
1691 enum amd_clockgating_state state)
1692{
1693 /* needed for driver unload*/
1694 return 0;
1695}
1696
1697const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1698 .name = "uvd_v7_0",
1699 .early_init = uvd_v7_0_early_init,
1700 .late_init = NULL,
1701 .sw_init = uvd_v7_0_sw_init,
1702 .sw_fini = uvd_v7_0_sw_fini,
1703 .hw_init = uvd_v7_0_hw_init,
1704 .hw_fini = uvd_v7_0_hw_fini,
1705 .suspend = uvd_v7_0_suspend,
1706 .resume = uvd_v7_0_resume,
1707 .is_idle = NULL /* uvd_v7_0_is_idle */,
1708 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1709 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1710 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1711 .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1712 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1713 .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1714 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1715};
1716
1717static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1718 .type = AMDGPU_RING_TYPE_UVD,
1719 .align_mask = 0xf,
1720 .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
1721 .support_64bit_ptrs = false,
0eeb68b3 1722 .vmhub = AMDGPU_MMHUB,
09bfb891
LL		 1723 .get_rptr = uvd_v7_0_ring_get_rptr,
1724 .get_wptr = uvd_v7_0_ring_get_wptr,
1725 .set_wptr = uvd_v7_0_ring_set_wptr,
1726 .emit_frame_size =
1727 2 + /* uvd_v7_0_ring_emit_hdp_flush */
1728 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
2e819849 1729 34 + /* uvd_v7_0_ring_emit_vm_flush */
09bfb891
LL		 1730 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1731 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1732 .emit_ib = uvd_v7_0_ring_emit_ib,
1733 .emit_fence = uvd_v7_0_ring_emit_fence,
1734 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1735 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1736 .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
1737 .test_ring = uvd_v7_0_ring_test_ring,
1738 .test_ib = amdgpu_uvd_ring_test_ib,
1739 .insert_nop = amdgpu_ring_insert_nop,
1740 .pad_ib = amdgpu_ring_generic_pad_ib,
1741 .begin_use = amdgpu_uvd_ring_begin_use,
1742 .end_use = amdgpu_uvd_ring_end_use,
1743};
1744
1745static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1746 .type = AMDGPU_RING_TYPE_UVD_ENC,
1747 .align_mask = 0x3f,
1748 .nop = HEVC_ENC_CMD_NO_OP,
1749 .support_64bit_ptrs = false,
0eeb68b3 1750 .vmhub = AMDGPU_MMHUB,
09bfb891
LL		 1751 .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1752 .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1753 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1754 .emit_frame_size =
2e819849 1755 17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
09bfb891
LL		 1756 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1757 1, /* uvd_v7_0_enc_ring_insert_end */
1758 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1759 .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1760 .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1761 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1762 .test_ring = uvd_v7_0_enc_ring_test_ring,
1763 .test_ib = uvd_v7_0_enc_ring_test_ib,
1764 .insert_nop = amdgpu_ring_insert_nop,
1765 .insert_end = uvd_v7_0_enc_ring_insert_end,
1766 .pad_ib = amdgpu_ring_generic_pad_ib,
1767 .begin_use = amdgpu_uvd_ring_begin_use,
1768 .end_use = amdgpu_uvd_ring_end_use,
1769};
1770
1771static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1772{
1773 adev->uvd.ring.funcs = &uvd_v7_0_ring_vm_funcs;
1774 DRM_INFO("UVD is enabled in VM mode\n");
1775}
1776
1777static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1778{
1779 int i;
1780
1781 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1782 adev->uvd.ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1783
1784 DRM_INFO("UVD ENC is enabled in VM mode\n");
1785}
1786
1787static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1788 .set = uvd_v7_0_set_interrupt_state,
1789 .process = uvd_v7_0_process_interrupt,
1790};
1791
1792static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1793{
1794 adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1795 adev->uvd.irq.funcs = &uvd_v7_0_irq_funcs;
1796}
1797
1798const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1799{
1800 .type = AMD_IP_BLOCK_TYPE_UVD,
1801 .major = 7,
1802 .minor = 0,
1803 .rev = 0,
1804 .funcs = &uvd_v7_0_ip_funcs,
1805};
Linux 6.x block layer and io_uring tree(s)