projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amdgpu:hdp flush should be put it initialized
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / uvd_v7_0.c
CommitLineData
09bfb891
LL		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_uvd.h"
28#include "soc15d.h"
29#include "soc15_common.h"
247ac951 30#include "mmsch_v1_0.h"
09bfb891
LL		 31
32#include "vega10/soc15ip.h"
33#include "vega10/UVD/uvd_7_0_offset.h"
34#include "vega10/UVD/uvd_7_0_sh_mask.h"
247ac951
FM		 35#include "vega10/VCE/vce_4_0_offset.h"
36#include "vega10/VCE/vce_4_0_default.h"
37#include "vega10/VCE/vce_4_0_sh_mask.h"
09bfb891
LL		 38#include "vega10/NBIF/nbif_6_1_offset.h"
39#include "vega10/HDP/hdp_4_0_offset.h"
40#include "vega10/MMHUB/mmhub_1_0_offset.h"
41#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
42
43static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
44static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
45static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
46static int uvd_v7_0_start(struct amdgpu_device *adev);
47static void uvd_v7_0_stop(struct amdgpu_device *adev);
247ac951 48static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
09bfb891
LL		 49
50/**
51 * uvd_v7_0_ring_get_rptr - get read pointer
52 *
53 * @ring: amdgpu_ring pointer
54 *
55 * Returns the current hardware read pointer
56 */
57static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
58{
59 struct amdgpu_device *adev = ring->adev;
60
4ad5751a 61 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
09bfb891
LL		 62}
63
64/**
65 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
66 *
67 * @ring: amdgpu_ring pointer
68 *
69 * Returns the current hardware enc read pointer
70 */
71static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
72{
73 struct amdgpu_device *adev = ring->adev;
74
75 if (ring == &adev->uvd.ring_enc[0])
4ad5751a 76 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
09bfb891 77 else
4ad5751a 78 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
09bfb891
LL		 79}
80
81/**
82 * uvd_v7_0_ring_get_wptr - get write pointer
83 *
84 * @ring: amdgpu_ring pointer
85 *
86 * Returns the current hardware write pointer
87 */
88static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
89{
90 struct amdgpu_device *adev = ring->adev;
91
4ad5751a 92 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
09bfb891
LL		 93}
94
95/**
96 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
97 *
98 * @ring: amdgpu_ring pointer
99 *
100 * Returns the current hardware enc write pointer
101 */
102static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
103{
104 struct amdgpu_device *adev = ring->adev;
105
beb2ced5
FM		 106 if (ring->use_doorbell)
107 return adev->wb.wb[ring->wptr_offs];
108
09bfb891 109 if (ring == &adev->uvd.ring_enc[0])
4ad5751a 110 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
09bfb891 111 else
4ad5751a 112 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
09bfb891
LL		 113}
114
115/**
116 * uvd_v7_0_ring_set_wptr - set write pointer
117 *
118 * @ring: amdgpu_ring pointer
119 *
120 * Commits the write pointer to the hardware
121 */
122static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
123{
124 struct amdgpu_device *adev = ring->adev;
125
4ad5751a 126 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
09bfb891
LL		 127}
128
129/**
130 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
131 *
132 * @ring: amdgpu_ring pointer
133 *
134 * Commits the enc write pointer to the hardware
135 */
136static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
137{
138 struct amdgpu_device *adev = ring->adev;
139
beb2ced5
FM		 140 if (ring->use_doorbell) {
141 /* XXX check if swapping is necessary on BE */
142 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
143 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
144 return;
145 }
146
09bfb891 147 if (ring == &adev->uvd.ring_enc[0])
4ad5751a 148 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
09bfb891
LL		 149 lower_32_bits(ring->wptr));
150 else
4ad5751a 151 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
09bfb891
LL		 152 lower_32_bits(ring->wptr));
153}
154
155/**
156 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
157 *
158 * @ring: the engine to test on
159 *
160 */
161static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
162{
163 struct amdgpu_device *adev = ring->adev;
164 uint32_t rptr = amdgpu_ring_get_rptr(ring);
165 unsigned i;
166 int r;
167
a1b9022a
FM		 168 if (amdgpu_sriov_vf(adev))
169 return 0;
170
09bfb891
LL		 171 r = amdgpu_ring_alloc(ring, 16);
172 if (r) {
173 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
174 ring->idx, r);
175 return r;
176 }
177 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
178 amdgpu_ring_commit(ring);
179
180 for (i = 0; i < adev->usec_timeout; i++) {
181 if (amdgpu_ring_get_rptr(ring) != rptr)
182 break;
183 DRM_UDELAY(1);
184 }
185
186 if (i < adev->usec_timeout) {
187 DRM_INFO("ring test on %d succeeded in %d usecs\n",
188 ring->idx, i);
189 } else {
190 DRM_ERROR("amdgpu: ring %d test failed\n",
191 ring->idx);
192 r = -ETIMEDOUT;
193 }
194
195 return r;
196}
197
198/**
199 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
200 *
201 * @adev: amdgpu_device pointer
202 * @ring: ring we should submit the msg to
203 * @handle: session handle to use
204 * @fence: optional fence to return
205 *
206 * Open up a stream for HW test
207 */
208static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
209 struct dma_fence **fence)
210{
211 const unsigned ib_size_dw = 16;
212 struct amdgpu_job *job;
213 struct amdgpu_ib *ib;
214 struct dma_fence *f = NULL;
215 uint64_t dummy;
216 int i, r;
217
218 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
219 if (r)
220 return r;
221
222 ib = &job->ibs[0];
223 dummy = ib->gpu_addr + 1024;
224
225 ib->length_dw = 0;
226 ib->ptr[ib->length_dw++] = 0x00000018;
227 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
228 ib->ptr[ib->length_dw++] = handle;
229 ib->ptr[ib->length_dw++] = 0x00000000;
230 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
231 ib->ptr[ib->length_dw++] = dummy;
232
233 ib->ptr[ib->length_dw++] = 0x00000014;
234 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
235 ib->ptr[ib->length_dw++] = 0x0000001c;
236 ib->ptr[ib->length_dw++] = 0x00000000;
237 ib->ptr[ib->length_dw++] = 0x00000000;
238
239 ib->ptr[ib->length_dw++] = 0x00000008;
240 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
241
242 for (i = ib->length_dw; i < ib_size_dw; ++i)
243 ib->ptr[i] = 0x0;
244
245 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
246 job->fence = dma_fence_get(f);
247 if (r)
248 goto err;
249
250 amdgpu_job_free(job);
251 if (fence)
252 *fence = dma_fence_get(f);
253 dma_fence_put(f);
254 return 0;
255
256err:
257 amdgpu_job_free(job);
258 return r;
259}
260
261/**
262 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
263 *
264 * @adev: amdgpu_device pointer
265 * @ring: ring we should submit the msg to
266 * @handle: session handle to use
267 * @fence: optional fence to return
268 *
269 * Close up a stream for HW test or if userspace failed to do so
270 */
271int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
272 bool direct, struct dma_fence **fence)
273{
274 const unsigned ib_size_dw = 16;
275 struct amdgpu_job *job;
276 struct amdgpu_ib *ib;
277 struct dma_fence *f = NULL;
278 uint64_t dummy;
279 int i, r;
280
281 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
282 if (r)
283 return r;
284
285 ib = &job->ibs[0];
286 dummy = ib->gpu_addr + 1024;
287
288 ib->length_dw = 0;
289 ib->ptr[ib->length_dw++] = 0x00000018;
290 ib->ptr[ib->length_dw++] = 0x00000001;
291 ib->ptr[ib->length_dw++] = handle;
292 ib->ptr[ib->length_dw++] = 0x00000000;
293 ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
294 ib->ptr[ib->length_dw++] = dummy;
295
296 ib->ptr[ib->length_dw++] = 0x00000014;
297 ib->ptr[ib->length_dw++] = 0x00000002;
298 ib->ptr[ib->length_dw++] = 0x0000001c;
299 ib->ptr[ib->length_dw++] = 0x00000000;
300 ib->ptr[ib->length_dw++] = 0x00000000;
301
302 ib->ptr[ib->length_dw++] = 0x00000008;
303 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
304
305 for (i = ib->length_dw; i < ib_size_dw; ++i)
306 ib->ptr[i] = 0x0;
307
308 if (direct) {
309 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
310 job->fence = dma_fence_get(f);
311 if (r)
312 goto err;
313
314 amdgpu_job_free(job);
315 } else {
316 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
317 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
318 if (r)
319 goto err;
320 }
321
322 if (fence)
323 *fence = dma_fence_get(f);
324 dma_fence_put(f);
325 return 0;
326
327err:
328 amdgpu_job_free(job);
329 return r;
330}
331
332/**
333 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
334 *
335 * @ring: the engine to test on
336 *
337 */
338static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
339{
340 struct dma_fence *fence = NULL;
341 long r;
342
343 r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
344 if (r) {
345 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
346 goto error;
347 }
348
349 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
350 if (r) {
351 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
352 goto error;
353 }
354
355 r = dma_fence_wait_timeout(fence, false, timeout);
356 if (r == 0) {
357 DRM_ERROR("amdgpu: IB test timed out.\n");
358 r = -ETIMEDOUT;
359 } else if (r < 0) {
360 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
361 } else {
362 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
363 r = 0;
364 }
365error:
366 dma_fence_put(fence);
367 return r;
368}
369
370static int uvd_v7_0_early_init(void *handle)
371{
372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
373
6fa336a7
FM		 374 if (amdgpu_sriov_vf(adev))
375 adev->uvd.num_enc_rings = 1;
376 else
377 adev->uvd.num_enc_rings = 2;
09bfb891
LL		 378 uvd_v7_0_set_ring_funcs(adev);
379 uvd_v7_0_set_enc_ring_funcs(adev);
380 uvd_v7_0_set_irq_funcs(adev);
381
382 return 0;
383}
384
385static int uvd_v7_0_sw_init(void *handle)
386{
387 struct amdgpu_ring *ring;
388 struct amd_sched_rq *rq;
389 int i, r;
390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
391
392 /* UVD TRAP */
393 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
394 if (r)
395 return r;
396
397 /* UVD ENC TRAP */
398 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
399 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
400 if (r)
401 return r;
402 }
403
404 r = amdgpu_uvd_sw_init(adev);
405 if (r)
406 return r;
407
408 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
409 const struct common_firmware_header *hdr;
410 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
411 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
412 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
413 adev->firmware.fw_size +=
414 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
415 DRM_INFO("PSP loading UVD firmware\n");
416 }
417
418 ring = &adev->uvd.ring_enc[0];
419 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
420 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
421 rq, amdgpu_sched_jobs);
422 if (r) {
423 DRM_ERROR("Failed setting up UVD ENC run queue.\n");
424 return r;
425 }
426
427 r = amdgpu_uvd_resume(adev);
428 if (r)
429 return r;
6fa336a7
FM		 430 if (!amdgpu_sriov_vf(adev)) {
431 ring = &adev->uvd.ring;
432 sprintf(ring->name, "uvd");
433 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
434 if (r)
435 return r;
436 }
09bfb891 437
09bfb891
LL		 438 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
439 ring = &adev->uvd.ring_enc[i];
440 sprintf(ring->name, "uvd_enc%d", i);
beb2ced5
FM		 441 if (amdgpu_sriov_vf(adev)) {
442 ring->use_doorbell = true;
4ed11d79
FM		 443
444 /* currently only use the first enconding ring for
445 * sriov, so set unused location for other unused rings.
446 */
447 if (i == 0)
448 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
449 else
450 ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
beb2ced5 451 }
09bfb891
LL		 452 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
453 if (r)
454 return r;
455 }
456
6fa336a7
FM		 457 r = amdgpu_virt_alloc_mm_table(adev);
458 if (r)
459 return r;
460
09bfb891
LL		 461 return r;
462}
463
464static int uvd_v7_0_sw_fini(void *handle)
465{
466 int i, r;
467 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
468
6fa336a7
FM		 469 amdgpu_virt_free_mm_table(adev);
470
09bfb891
LL		 471 r = amdgpu_uvd_suspend(adev);
472 if (r)
473 return r;
474
475 amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
476
477 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
478 amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
479
50237287 480 return amdgpu_uvd_sw_fini(adev);
09bfb891
LL		 481}
482
483/**
484 * uvd_v7_0_hw_init - start and test UVD block
485 *
486 * @adev: amdgpu_device pointer
487 *
488 * Initialize the hardware, boot up the VCPU and do some testing
489 */
490static int uvd_v7_0_hw_init(void *handle)
491{
492 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
493 struct amdgpu_ring *ring = &adev->uvd.ring;
494 uint32_t tmp;
495 int i, r;
496
6fa336a7
FM		 497 if (amdgpu_sriov_vf(adev))
498 r = uvd_v7_0_sriov_start(adev);
499 else
500 r = uvd_v7_0_start(adev);
09bfb891
LL		 501 if (r)
502 goto done;
503
6fa336a7
FM		 504 if (!amdgpu_sriov_vf(adev)) {
505 ring->ready = true;
506 r = amdgpu_ring_test_ring(ring);
507 if (r) {
508 ring->ready = false;
509 goto done;
510 }
09bfb891 511
6fa336a7
FM		 512 r = amdgpu_ring_alloc(ring, 10);
513 if (r) {
514 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
515 goto done;
516 }
09bfb891 517
6fa336a7
FM		 518 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
519 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
520 amdgpu_ring_write(ring, tmp);
521 amdgpu_ring_write(ring, 0xFFFFF);
09bfb891 522
6fa336a7
FM		 523 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
524 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
525 amdgpu_ring_write(ring, tmp);
526 amdgpu_ring_write(ring, 0xFFFFF);
09bfb891 527
6fa336a7
FM		 528 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
529 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
530 amdgpu_ring_write(ring, tmp);
531 amdgpu_ring_write(ring, 0xFFFFF);
09bfb891 532
6fa336a7
FM		 533 /* Clear timeout status bits */
534 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
535 mmUVD_SEMA_TIMEOUT_STATUS), 0));
536 amdgpu_ring_write(ring, 0x8);
09bfb891 537
6fa336a7
FM		 538 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
539 mmUVD_SEMA_CNTL), 0));
540 amdgpu_ring_write(ring, 3);
09bfb891 541
6fa336a7
FM		 542 amdgpu_ring_commit(ring);
543 }
09bfb891
LL		 544
545 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
546 ring = &adev->uvd.ring_enc[i];
547 ring->ready = true;
548 r = amdgpu_ring_test_ring(ring);
549 if (r) {
550 ring->ready = false;
551 goto done;
552 }
553 }
554
555done:
556 if (!r)
557 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
558
559 return r;
560}
561
562/**
563 * uvd_v7_0_hw_fini - stop the hardware block
564 *
565 * @adev: amdgpu_device pointer
566 *
567 * Stop the UVD block, mark ring as not ready any more
568 */
569static int uvd_v7_0_hw_fini(void *handle)
570{
571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
572 struct amdgpu_ring *ring = &adev->uvd.ring;
573
5dd696ae
TH		 574 if (!amdgpu_sriov_vf(adev))
575 uvd_v7_0_stop(adev);
576 else {
577 /* full access mode, so don't touch any UVD register */
578 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
579 }
580
09bfb891
LL		 581 ring->ready = false;
582
583 return 0;
584}
585
586static int uvd_v7_0_suspend(void *handle)
587{
588 int r;
589 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
590
591 r = uvd_v7_0_hw_fini(adev);
592 if (r)
593 return r;
594
595 /* Skip this for APU for now */
50237287 596 if (!(adev->flags & AMD_IS_APU))
09bfb891 597 r = amdgpu_uvd_suspend(adev);
09bfb891
LL		 598
599 return r;
600}
601
602static int uvd_v7_0_resume(void *handle)
603{
604 int r;
605 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
606
607 /* Skip this for APU for now */
608 if (!(adev->flags & AMD_IS_APU)) {
609 r = amdgpu_uvd_resume(adev);
610 if (r)
611 return r;
612 }
50237287 613 return uvd_v7_0_hw_init(adev);
09bfb891
LL		 614}
615
616/**
617 * uvd_v7_0_mc_resume - memory controller programming
618 *
619 * @adev: amdgpu_device pointer
620 *
621 * Let the UVD memory controller know it's offsets
622 */
623static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
624{
625 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
626 uint32_t offset;
627
628 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4ad5751a 629 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
09bfb891 630 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
4ad5751a 631 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
09bfb891
LL		 632 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
633 offset = 0;
634 } else {
4ad5751a 635 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
09bfb891 636 lower_32_bits(adev->uvd.gpu_addr));
4ad5751a 637 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
09bfb891
LL		 638 upper_32_bits(adev->uvd.gpu_addr));
639 offset = size;
640 }
641
4ad5751a 642 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
09bfb891 643 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
4ad5751a 644 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
09bfb891 645
4ad5751a 646 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
09bfb891 647 lower_32_bits(adev->uvd.gpu_addr + offset));
4ad5751a 648 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
09bfb891 649 upper_32_bits(adev->uvd.gpu_addr + offset));
4ad5751a
TSD		 650 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
651 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
09bfb891 652
4ad5751a 653 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
09bfb891 654 lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
4ad5751a 655 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
09bfb891 656 upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
4ad5751a
TSD		 657 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
658 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
09bfb891
LL		 659 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
660
4ad5751a 661 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
09bfb891 662 adev->gfx.config.gb_addr_config);
4ad5751a 663 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
09bfb891 664 adev->gfx.config.gb_addr_config);
4ad5751a 665 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
09bfb891
LL		 666 adev->gfx.config.gb_addr_config);
667
4ad5751a 668 WREG32_SOC15(UVD, 0, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
09bfb891
LL		 669}
670
247ac951
FM		 671static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
672 struct amdgpu_mm_table *table)
673{
674 uint32_t data = 0, loop;
675 uint64_t addr = table->gpu_addr;
676 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
677 uint32_t size;
678
679 size = header->header_size + header->vce_table_size + header->uvd_table_size;
680
681 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
4ad5751a
TSD		 682 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
683 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
247ac951
FM		 684
685 /* 2, update vmid of descriptor */
4ad5751a 686 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
247ac951
FM		 687 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
688 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
4ad5751a 689 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
247ac951
FM		 690
691 /* 3, notify mmsch about the size of this descriptor */
4ad5751a 692 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
247ac951
FM		 693
694 /* 4, set resp to zero */
4ad5751a 695 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
247ac951 696
ab2b2e4f
FM		 697 WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
698 adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
699 adev->uvd.ring_enc[0].wptr = 0;
700 adev->uvd.ring_enc[0].wptr_old = 0;
701
247ac951 702 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
4ad5751a 703 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
247ac951 704
4ad5751a 705 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
247ac951
FM		 706 loop = 1000;
707 while ((data & 0x10000002) != 0x10000002) {
708 udelay(10);
4ad5751a 709 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
247ac951
FM		 710 loop--;
711 if (!loop)
712 break;
713 }
714
715 if (!loop) {
716 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
717 return -EBUSY;
718 }
719
720 return 0;
721}
722
723static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
724{
725 struct amdgpu_ring *ring;
726 uint32_t offset, size, tmp;
727 uint32_t table_size = 0;
728 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
729 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
730 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
247ac951
FM		 731 struct mmsch_v1_0_cmd_end end = { {0} };
732 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
733 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
734
735 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
736 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
737 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
738 end.cmd_header.command_type = MMSCH_COMMAND__END;
739
740 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
741 header->version = MMSCH_VERSION;
742 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
743
744 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
745 header->uvd_table_offset = header->header_size;
746 else
747 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
748
749 init_table += header->uvd_table_offset;
750
751 ring = &adev->uvd.ring;
81fe3f35 752 ring->wptr = 0;
247ac951
FM		 753 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
754
247ac951
FM		 755 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
756 0xFFFFFFFF, 0x00000004);
757 /* mc resume*/
758 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
759 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
760 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
761 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
762 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
763 offset = 0;
764 } else {
765 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
766 lower_32_bits(adev->uvd.gpu_addr));
767 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
768 upper_32_bits(adev->uvd.gpu_addr));
769 offset = size;
770 }
771
772 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
773 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
774 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
775
776 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
777 lower_32_bits(adev->uvd.gpu_addr + offset));
778 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
779 upper_32_bits(adev->uvd.gpu_addr + offset));
780 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
781 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
782
783 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
784 lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
785 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
786 upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
787 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
788 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
789 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
790
247ac951
FM		 791 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
792 /* mc resume end*/
793
794 /* disable clock gating */
795 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL),
796 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
797
798 /* disable interupt */
799 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
800 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
801
802 /* stall UMC and register bus before resetting VCPU */
803 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
804 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
805 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
806
807 /* put LMI, VCPU, RBC etc... into reset */
808 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
809 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
810 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
811 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
812 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
813 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
814 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
815 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
816 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
817
818 /* initialize UVD memory controller */
819 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
820 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
821 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
822 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
823 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
824 UVD_LMI_CTRL__REQ_MODE_MASK |
825 0x00100000L));
826
247ac951
FM		 827 /* take all subblocks out of reset, except VCPU */
828 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
829 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
830
831 /* enable VCPU clock */
832 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
833 UVD_VCPU_CNTL__CLK_EN_MASK);
834
247ac951
FM		 835 /* enable master interrupt */
836 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
837 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
838 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
839
840 /* clear the bit 4 of UVD_STATUS */
841 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
842 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
843
844 /* force RBC into idle state */
845 size = order_base_2(ring->ring_size);
846 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
247ac951 847 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
247ac951
FM		 848 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
849
247ac951 850 ring = &adev->uvd.ring_enc[0];
81fe3f35 851 ring->wptr = 0;
247ac951
FM		 852 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
853 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
854 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
855
81fe3f35
FM		 856 /* boot up the VCPU */
857 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
858
859 /* enable UMC */
860 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
861 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
862
863 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02);
864
247ac951
FM		 865 /* add end packet */
866 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
867 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
868 header->uvd_table_size = table_size;
869
247ac951 870 }
257deb8c 871 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
247ac951
FM		 872}
873
09bfb891
LL		 874/**
875 * uvd_v7_0_start - start UVD block
876 *
877 * @adev: amdgpu_device pointer
878 *
879 * Setup and start the UVD block
880 */
881static int uvd_v7_0_start(struct amdgpu_device *adev)
882{
883 struct amdgpu_ring *ring = &adev->uvd.ring;
884 uint32_t rb_bufsz, tmp;
885 uint32_t lmi_swap_cntl;
886 uint32_t mp_swap_cntl;
887 int i, j, r;
888
889 /* disable DPG */
890 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
891 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
892
893 /* disable byte swapping */
894 lmi_swap_cntl = 0;
895 mp_swap_cntl = 0;
896
897 uvd_v7_0_mc_resume(adev);
898
899 /* disable clock gating */
900 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
901 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
902
903 /* disable interupt */
904 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
905 ~UVD_MASTINT_EN__VCPU_EN_MASK);
906
907 /* stall UMC and register bus before resetting VCPU */
908 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
909 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
910 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
911 mdelay(1);
912
913 /* put LMI, VCPU, RBC etc... into reset */
4ad5751a 914 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
09bfb891
LL		 915 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
916 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
917 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
918 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
919 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
920 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
921 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
922 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
923 mdelay(5);
924
925 /* initialize UVD memory controller */
4ad5751a 926 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
09bfb891
LL		 927 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
928 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
929 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
930 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
931 UVD_LMI_CTRL__REQ_MODE_MASK |
932 0x00100000L);
933
934#ifdef __BIG_ENDIAN
935 /* swap (8 in 32) RB and IB */
936 lmi_swap_cntl = 0xa;
937 mp_swap_cntl = 0;
938#endif
4ad5751a
TSD		 939 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
940 WREG32_SOC15(UVD, 0, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
09bfb891 941
4ad5751a
TSD		 942 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
943 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
944 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
945 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
946 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
947 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
09bfb891
LL		 948
949 /* take all subblocks out of reset, except VCPU */
4ad5751a 950 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
09bfb891
LL		 951 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
952 mdelay(5);
953
954 /* enable VCPU clock */
4ad5751a 955 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
09bfb891
LL		 956 UVD_VCPU_CNTL__CLK_EN_MASK);
957
958 /* enable UMC */
959 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
960 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
961
962 /* boot up the VCPU */
4ad5751a 963 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
09bfb891
LL		 964 mdelay(10);
965
966 for (i = 0; i < 10; ++i) {
967 uint32_t status;
968
969 for (j = 0; j < 100; ++j) {
4ad5751a 970 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
09bfb891
LL		 971 if (status & 2)
972 break;
973 mdelay(10);
974 }
975 r = 0;
976 if (status & 2)
977 break;
978
979 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
980 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
981 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
982 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
983 mdelay(10);
984 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
985 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
986 mdelay(10);
987 r = -1;
988 }
989
990 if (r) {
991 DRM_ERROR("UVD not responding, giving up!!!\n");
992 return r;
993 }
994 /* enable master interrupt */
995 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
996 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
997 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
998
999 /* clear the bit 4 of UVD_STATUS */
1000 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1001 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1002
1003 /* force RBC into idle state */
1004 rb_bufsz = order_base_2(ring->ring_size);
1005 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1006 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1007 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1008 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1009 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1010 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
4ad5751a 1011 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
09bfb891
LL		 1012
1013 /* set the write pointer delay */
4ad5751a 1014 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
09bfb891
LL		 1015
1016 /* set the wb address */
4ad5751a 1017 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
09bfb891
LL		 1018 (upper_32_bits(ring->gpu_addr) >> 2));
1019
1020 /* programm the RB_BASE for ring buffer */
4ad5751a 1021 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
09bfb891 1022 lower_32_bits(ring->gpu_addr));
4ad5751a 1023 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
09bfb891
LL		 1024 upper_32_bits(ring->gpu_addr));
1025
1026 /* Initialize the ring buffer's read and write pointers */
4ad5751a 1027 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
09bfb891 1028
4ad5751a
TSD		 1029 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1030 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
09bfb891
LL		 1031 lower_32_bits(ring->wptr));
1032
1033 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1034 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1035
1036 ring = &adev->uvd.ring_enc[0];
4ad5751a
TSD		 1037 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1038 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1039 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1040 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1041 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
09bfb891
LL		 1042
1043 ring = &adev->uvd.ring_enc[1];
4ad5751a
TSD		 1044 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1045 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1046 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1047 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1048 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
09bfb891
LL		 1049
1050 return 0;
1051}
1052
1053/**
1054 * uvd_v7_0_stop - stop UVD block
1055 *
1056 * @adev: amdgpu_device pointer
1057 *
1058 * stop the UVD block
1059 */
1060static void uvd_v7_0_stop(struct amdgpu_device *adev)
1061{
1062 /* force RBC into idle state */
4ad5751a 1063 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
09bfb891
LL		 1064
1065 /* Stall UMC and register bus before resetting VCPU */
1066 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1067 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1068 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1069 mdelay(1);
1070
1071 /* put VCPU into reset */
4ad5751a 1072 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
09bfb891
LL		 1073 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1074 mdelay(5);
1075
1076 /* disable VCPU clock */
4ad5751a 1077 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
09bfb891
LL		 1078
1079 /* Unstall UMC and register bus */
1080 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1081 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1082}
1083
1084/**
1085 * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1086 *
1087 * @ring: amdgpu_ring pointer
1088 * @fence: fence to emit
1089 *
1090 * Write a fence and a trap command to the ring.
1091 */
1092static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1093 unsigned flags)
1094{
1095 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1096
1097 amdgpu_ring_write(ring,
1098 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1099 amdgpu_ring_write(ring, seq);
1100 amdgpu_ring_write(ring,
1101 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1102 amdgpu_ring_write(ring, addr & 0xffffffff);
1103 amdgpu_ring_write(ring,
1104 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1105 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1106 amdgpu_ring_write(ring,
1107 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1108 amdgpu_ring_write(ring, 0);
1109
1110 amdgpu_ring_write(ring,
1111 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1112 amdgpu_ring_write(ring, 0);
1113 amdgpu_ring_write(ring,
1114 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1115 amdgpu_ring_write(ring, 0);
1116 amdgpu_ring_write(ring,
1117 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1118 amdgpu_ring_write(ring, 2);
1119}
1120
1121/**
1122 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1123 *
1124 * @ring: amdgpu_ring pointer
1125 * @fence: fence to emit
1126 *
1127 * Write enc a fence and a trap command to the ring.
1128 */
1129static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1130 u64 seq, unsigned flags)
1131{
1132 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1133
1134 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1135 amdgpu_ring_write(ring, addr);
1136 amdgpu_ring_write(ring, upper_32_bits(addr));
1137 amdgpu_ring_write(ring, seq);
1138 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1139}
1140
1141/**
1142 * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush
1143 *
1144 * @ring: amdgpu_ring pointer
1145 *
1146 * Emits an hdp flush.
1147 */
1148static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1149{
1150 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,
1151 mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0));
1152 amdgpu_ring_write(ring, 0);
1153}
1154
1155/**
1156 * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate
1157 *
1158 * @ring: amdgpu_ring pointer
1159 *
1160 * Emits an hdp invalidate.
1161 */
1162static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1163{
1164 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
1165 amdgpu_ring_write(ring, 1);
1166}
1167
1168/**
1169 * uvd_v7_0_ring_test_ring - register write test
1170 *
1171 * @ring: amdgpu_ring pointer
1172 *
1173 * Test if we can successfully write to the context register
1174 */
1175static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1176{
1177 struct amdgpu_device *adev = ring->adev;
1178 uint32_t tmp = 0;
1179 unsigned i;
1180 int r;
1181
4ad5751a 1182 WREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
09bfb891
LL		 1183 r = amdgpu_ring_alloc(ring, 3);
1184 if (r) {
1185 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
1186 ring->idx, r);
1187 return r;
1188 }
1189 amdgpu_ring_write(ring,
1190 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1191 amdgpu_ring_write(ring, 0xDEADBEEF);
1192 amdgpu_ring_commit(ring);
1193 for (i = 0; i < adev->usec_timeout; i++) {
4ad5751a 1194 tmp = RREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID);
09bfb891
LL		 1195 if (tmp == 0xDEADBEEF)
1196 break;
1197 DRM_UDELAY(1);
1198 }
1199
1200 if (i < adev->usec_timeout) {
1201 DRM_INFO("ring test on %d succeeded in %d usecs\n",
1202 ring->idx, i);
1203 } else {
1204 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1205 ring->idx, tmp);
1206 r = -EINVAL;
1207 }
1208 return r;
1209}
1210
1211/**
1212 * uvd_v7_0_ring_emit_ib - execute indirect buffer
1213 *
1214 * @ring: amdgpu_ring pointer
1215 * @ib: indirect buffer to execute
1216 *
1217 * Write ring commands to execute the indirect buffer
1218 */
1219static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1220 struct amdgpu_ib *ib,
1221 unsigned vm_id, bool ctx_switch)
1222{
1223 amdgpu_ring_write(ring,
1224 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1225 amdgpu_ring_write(ring, vm_id);
1226
1227 amdgpu_ring_write(ring,
1228 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1229 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1230 amdgpu_ring_write(ring,
1231 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1232 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1233 amdgpu_ring_write(ring,
1234 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1235 amdgpu_ring_write(ring, ib->length_dw);
1236}
1237
1238/**
1239 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1240 *
1241 * @ring: amdgpu_ring pointer
1242 * @ib: indirect buffer to execute
1243 *
1244 * Write enc ring commands to execute the indirect buffer
1245 */
1246static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1247 struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
1248{
1249 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1250 amdgpu_ring_write(ring, vm_id);
1251 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1252 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1253 amdgpu_ring_write(ring, ib->length_dw);
1254}
1255
1256static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring,
1257 uint32_t data0, uint32_t data1)
1258{
1259 amdgpu_ring_write(ring,
1260 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1261 amdgpu_ring_write(ring, data0);
1262 amdgpu_ring_write(ring,
1263 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1264 amdgpu_ring_write(ring, data1);
1265 amdgpu_ring_write(ring,
1266 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1267 amdgpu_ring_write(ring, 8);
1268}
1269
1270static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
1271 uint32_t data0, uint32_t data1, uint32_t mask)
1272{
1273 amdgpu_ring_write(ring,
1274 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1275 amdgpu_ring_write(ring, data0);
1276 amdgpu_ring_write(ring,
1277 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1278 amdgpu_ring_write(ring, data1);
1279 amdgpu_ring_write(ring,
1280 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1281 amdgpu_ring_write(ring, mask);
1282 amdgpu_ring_write(ring,
1283 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1284 amdgpu_ring_write(ring, 12);
1285}
1286
1287static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1288 unsigned vm_id, uint64_t pd_addr)
1289{
2e819849 1290 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
03f89feb 1291 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
09bfb891 1292 uint32_t data0, data1, mask;
4789c463 1293 unsigned eng = ring->vm_inv_eng;
09bfb891 1294
b1166325
CK		 1295 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1296 pd_addr |= AMDGPU_PTE_VALID;
09bfb891 1297
2e819849
CK		 1298 data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
1299 data1 = upper_32_bits(pd_addr);
1300 uvd_v7_0_vm_reg_write(ring, data0, data1);
1301
1302 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1303 data1 = lower_32_bits(pd_addr);
1304 uvd_v7_0_vm_reg_write(ring, data0, data1);
1305
1306 data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
1307 data1 = lower_32_bits(pd_addr);
1308 mask = 0xffffffff;
1309 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
1310
1311 /* flush TLB */
1312 data0 = (hub->vm_inv_eng0_req + eng) << 2;
1313 data1 = req;
1314 uvd_v7_0_vm_reg_write(ring, data0, data1);
1315
1316 /* wait for flush */
1317 data0 = (hub->vm_inv_eng0_ack + eng) << 2;
1318 data1 = 1 << vm_id;
1319 mask = 1 << vm_id;
1320 uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
09bfb891
LL		 1321}
1322
1323static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1324{
1325 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1326}
1327
1328static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1329 unsigned int vm_id, uint64_t pd_addr)
1330{
2e819849 1331 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
03f89feb 1332 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
4789c463 1333 unsigned eng = ring->vm_inv_eng;
09bfb891 1334
b1166325
CK		 1335 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1336 pd_addr |= AMDGPU_PTE_VALID;
09bfb891 1337
2e819849
CK		 1338 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1339 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
1340 amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1341
1342 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1343 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1344 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1345
1346 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1347 amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
1348 amdgpu_ring_write(ring, 0xffffffff);
1349 amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1350
1351 /* flush TLB */
1352 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1353 amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2);
1354 amdgpu_ring_write(ring, req);
1355
1356 /* wait for flush */
1357 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1358 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1359 amdgpu_ring_write(ring, 1 << vm_id);
1360 amdgpu_ring_write(ring, 1 << vm_id);
09bfb891
LL		 1361}
1362
1363#if 0
1364static bool uvd_v7_0_is_idle(void *handle)
1365{
1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1367
1368 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1369}
1370
1371static int uvd_v7_0_wait_for_idle(void *handle)
1372{
1373 unsigned i;
1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1375
1376 for (i = 0; i < adev->usec_timeout; i++) {
1377 if (uvd_v7_0_is_idle(handle))
1378 return 0;
1379 }
1380 return -ETIMEDOUT;
1381}
1382
1383#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd
1384static bool uvd_v7_0_check_soft_reset(void *handle)
1385{
1386 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1387 u32 srbm_soft_reset = 0;
1388 u32 tmp = RREG32(mmSRBM_STATUS);
1389
1390 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1391 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
4ad5751a
TSD		 1392 (RREG32_SOC15(UVD, 0, mmUVD_STATUS) &
1393 AMDGPU_UVD_STATUS_BUSY_MASK))
09bfb891
LL		 1394 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1395 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1396
1397 if (srbm_soft_reset) {
1398 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1399 return true;
1400 } else {
1401 adev->uvd.srbm_soft_reset = 0;
1402 return false;
1403 }
1404}
1405
1406static int uvd_v7_0_pre_soft_reset(void *handle)
1407{
1408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1409
1410 if (!adev->uvd.srbm_soft_reset)
1411 return 0;
1412
1413 uvd_v7_0_stop(adev);
1414 return 0;
1415}
1416
1417static int uvd_v7_0_soft_reset(void *handle)
1418{
1419 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420 u32 srbm_soft_reset;
1421
1422 if (!adev->uvd.srbm_soft_reset)
1423 return 0;
1424 srbm_soft_reset = adev->uvd.srbm_soft_reset;
1425
1426 if (srbm_soft_reset) {
1427 u32 tmp;
1428
1429 tmp = RREG32(mmSRBM_SOFT_RESET);
1430 tmp |= srbm_soft_reset;
1431 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1432 WREG32(mmSRBM_SOFT_RESET, tmp);
1433 tmp = RREG32(mmSRBM_SOFT_RESET);
1434
1435 udelay(50);
1436
1437 tmp &= ~srbm_soft_reset;
1438 WREG32(mmSRBM_SOFT_RESET, tmp);
1439 tmp = RREG32(mmSRBM_SOFT_RESET);
1440
1441 /* Wait a little for things to settle down */
1442 udelay(50);
1443 }
1444
1445 return 0;
1446}
1447
1448static int uvd_v7_0_post_soft_reset(void *handle)
1449{
1450 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1451
1452 if (!adev->uvd.srbm_soft_reset)
1453 return 0;
1454
1455 mdelay(5);
1456
1457 return uvd_v7_0_start(adev);
1458}
1459#endif
1460
1461static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1462 struct amdgpu_irq_src *source,
1463 unsigned type,
1464 enum amdgpu_interrupt_state state)
1465{
1466 // TODO
1467 return 0;
1468}
1469
1470static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1471 struct amdgpu_irq_src *source,
1472 struct amdgpu_iv_entry *entry)
1473{
1474 DRM_DEBUG("IH: UVD TRAP\n");
1475 switch (entry->src_id) {
1476 case 124:
1477 amdgpu_fence_process(&adev->uvd.ring);
1478 break;
1479 case 119:
1480 amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1481 break;
1482 case 120:
6fa336a7
FM		 1483 if (!amdgpu_sriov_vf(adev))
1484 amdgpu_fence_process(&adev->uvd.ring_enc[1]);
09bfb891
LL		 1485 break;
1486 default:
1487 DRM_ERROR("Unhandled interrupt: %d %d\n",
1488 entry->src_id, entry->src_data[0]);
1489 break;
1490 }
1491
1492 return 0;
1493}
1494
1495#if 0
1496static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1497{
1498 uint32_t data, data1, data2, suvd_flags;
1499
4ad5751a
TSD		 1500 data = RREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL);
1501 data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
1502 data2 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL);
09bfb891
LL		 1503
1504 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1505 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1506
1507 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1508 UVD_SUVD_CGC_GATE__SIT_MASK |
1509 UVD_SUVD_CGC_GATE__SMP_MASK |
1510 UVD_SUVD_CGC_GATE__SCM_MASK |
1511 UVD_SUVD_CGC_GATE__SDB_MASK;
1512
1513 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1514 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1515 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1516
1517 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1518 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1519 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1520 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1521 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1522 UVD_CGC_CTRL__SYS_MODE_MASK |
1523 UVD_CGC_CTRL__UDEC_MODE_MASK |
1524 UVD_CGC_CTRL__MPEG2_MODE_MASK |
1525 UVD_CGC_CTRL__REGS_MODE_MASK |
1526 UVD_CGC_CTRL__RBC_MODE_MASK |
1527 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1528 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1529 UVD_CGC_CTRL__IDCT_MODE_MASK |
1530 UVD_CGC_CTRL__MPRD_MODE_MASK |
1531 UVD_CGC_CTRL__MPC_MODE_MASK |
1532 UVD_CGC_CTRL__LBSI_MODE_MASK |
1533 UVD_CGC_CTRL__LRBBM_MODE_MASK |
1534 UVD_CGC_CTRL__WCB_MODE_MASK |
1535 UVD_CGC_CTRL__VCPU_MODE_MASK |
1536 UVD_CGC_CTRL__JPEG_MODE_MASK |
1537 UVD_CGC_CTRL__JPEG2_MODE_MASK |
1538 UVD_CGC_CTRL__SCPU_MODE_MASK);
1539 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1540 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1541 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1542 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1543 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1544 data1 |= suvd_flags;
1545
4ad5751a
TSD		 1546 WREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL, data);
1547 WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, 0);
1548 WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
1549 WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL, data2);
09bfb891
LL		 1550}
1551
1552static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1553{
1554 uint32_t data, data1, cgc_flags, suvd_flags;
1555
4ad5751a
TSD		 1556 data = RREG32_SOC15(UVD, 0, mmUVD_CGC_GATE);
1557 data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
09bfb891
LL		 1558
1559 cgc_flags = UVD_CGC_GATE__SYS_MASK |
1560 UVD_CGC_GATE__UDEC_MASK |
1561 UVD_CGC_GATE__MPEG2_MASK |
1562 UVD_CGC_GATE__RBC_MASK |
1563 UVD_CGC_GATE__LMI_MC_MASK |
1564 UVD_CGC_GATE__IDCT_MASK |
1565 UVD_CGC_GATE__MPRD_MASK |
1566 UVD_CGC_GATE__MPC_MASK |
1567 UVD_CGC_GATE__LBSI_MASK |
1568 UVD_CGC_GATE__LRBBM_MASK |
1569 UVD_CGC_GATE__UDEC_RE_MASK |
1570 UVD_CGC_GATE__UDEC_CM_MASK |
1571 UVD_CGC_GATE__UDEC_IT_MASK |
1572 UVD_CGC_GATE__UDEC_DB_MASK |
1573 UVD_CGC_GATE__UDEC_MP_MASK |
1574 UVD_CGC_GATE__WCB_MASK |
1575 UVD_CGC_GATE__VCPU_MASK |
1576 UVD_CGC_GATE__SCPU_MASK |
1577 UVD_CGC_GATE__JPEG_MASK |
1578 UVD_CGC_GATE__JPEG2_MASK;
1579
1580 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1581 UVD_SUVD_CGC_GATE__SIT_MASK |
1582 UVD_SUVD_CGC_GATE__SMP_MASK |
1583 UVD_SUVD_CGC_GATE__SCM_MASK |
1584 UVD_SUVD_CGC_GATE__SDB_MASK;
1585
1586 data |= cgc_flags;
1587 data1 |= suvd_flags;
1588
4ad5751a
TSD		 1589 WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, data);
1590 WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
09bfb891
LL		 1591}
1592
1593static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1594{
1595 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1596
1597 if (enable)
1598 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1599 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1600 else
1601 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1602 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1603
1604 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1605}
1606
1607
1608static int uvd_v7_0_set_clockgating_state(void *handle,
1609 enum amd_clockgating_state state)
1610{
1611 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1612 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1613
1614 uvd_v7_0_set_bypass_mode(adev, enable);
1615
1616 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1617 return 0;
1618
1619 if (enable) {
1620 /* disable HW gating and enable Sw gating */
1621 uvd_v7_0_set_sw_clock_gating(adev);
1622 } else {
1623 /* wait for STATUS to clear */
1624 if (uvd_v7_0_wait_for_idle(handle))
1625 return -EBUSY;
1626
1627 /* enable HW gates because UVD is idle */
1628 /* uvd_v7_0_set_hw_clock_gating(adev); */
1629 }
1630
1631 return 0;
1632}
1633
1634static int uvd_v7_0_set_powergating_state(void *handle,
1635 enum amd_powergating_state state)
1636{
1637 /* This doesn't actually powergate the UVD block.
1638 * That's done in the dpm code via the SMC. This
1639 * just re-inits the block as necessary. The actual
1640 * gating still happens in the dpm code. We should
1641 * revisit this when there is a cleaner line between
1642 * the smc and the hw blocks
1643 */
1644 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1645
1646 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1647 return 0;
1648
4ad5751a 1649 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
09bfb891
LL		 1650
1651 if (state == AMD_PG_STATE_GATE) {
1652 uvd_v7_0_stop(adev);
1653 return 0;
1654 } else {
1655 return uvd_v7_0_start(adev);
1656 }
1657}
1658#endif
1659
1660static int uvd_v7_0_set_clockgating_state(void *handle,
1661 enum amd_clockgating_state state)
1662{
1663 /* needed for driver unload*/
1664 return 0;
1665}
1666
1667const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1668 .name = "uvd_v7_0",
1669 .early_init = uvd_v7_0_early_init,
1670 .late_init = NULL,
1671 .sw_init = uvd_v7_0_sw_init,
1672 .sw_fini = uvd_v7_0_sw_fini,
1673 .hw_init = uvd_v7_0_hw_init,
1674 .hw_fini = uvd_v7_0_hw_fini,
1675 .suspend = uvd_v7_0_suspend,
1676 .resume = uvd_v7_0_resume,
1677 .is_idle = NULL /* uvd_v7_0_is_idle */,
1678 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1679 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1680 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1681 .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1682 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1683 .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1684 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1685};
1686
1687static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1688 .type = AMDGPU_RING_TYPE_UVD,
1689 .align_mask = 0xf,
1690 .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
1691 .support_64bit_ptrs = false,
0eeb68b3 1692 .vmhub = AMDGPU_MMHUB,
09bfb891
LL		 1693 .get_rptr = uvd_v7_0_ring_get_rptr,
1694 .get_wptr = uvd_v7_0_ring_get_wptr,
1695 .set_wptr = uvd_v7_0_ring_set_wptr,
1696 .emit_frame_size =
1697 2 + /* uvd_v7_0_ring_emit_hdp_flush */
1698 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
2e819849 1699 34 + /* uvd_v7_0_ring_emit_vm_flush */
09bfb891
LL		 1700 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1701 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1702 .emit_ib = uvd_v7_0_ring_emit_ib,
1703 .emit_fence = uvd_v7_0_ring_emit_fence,
1704 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1705 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1706 .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate,
1707 .test_ring = uvd_v7_0_ring_test_ring,
1708 .test_ib = amdgpu_uvd_ring_test_ib,
1709 .insert_nop = amdgpu_ring_insert_nop,
1710 .pad_ib = amdgpu_ring_generic_pad_ib,
1711 .begin_use = amdgpu_uvd_ring_begin_use,
1712 .end_use = amdgpu_uvd_ring_end_use,
1713};
1714
1715static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1716 .type = AMDGPU_RING_TYPE_UVD_ENC,
1717 .align_mask = 0x3f,
1718 .nop = HEVC_ENC_CMD_NO_OP,
1719 .support_64bit_ptrs = false,
0eeb68b3 1720 .vmhub = AMDGPU_MMHUB,
09bfb891
LL		 1721 .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1722 .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1723 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1724 .emit_frame_size =
2e819849 1725 17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
09bfb891
LL		 1726 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1727 1, /* uvd_v7_0_enc_ring_insert_end */
1728 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1729 .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1730 .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1731 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1732 .test_ring = uvd_v7_0_enc_ring_test_ring,
1733 .test_ib = uvd_v7_0_enc_ring_test_ib,
1734 .insert_nop = amdgpu_ring_insert_nop,
1735 .insert_end = uvd_v7_0_enc_ring_insert_end,
1736 .pad_ib = amdgpu_ring_generic_pad_ib,
1737 .begin_use = amdgpu_uvd_ring_begin_use,
1738 .end_use = amdgpu_uvd_ring_end_use,
1739};
1740
1741static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1742{
1743 adev->uvd.ring.funcs = &uvd_v7_0_ring_vm_funcs;
1744 DRM_INFO("UVD is enabled in VM mode\n");
1745}
1746
1747static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1748{
1749 int i;
1750
1751 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1752 adev->uvd.ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1753
1754 DRM_INFO("UVD ENC is enabled in VM mode\n");
1755}
1756
1757static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1758 .set = uvd_v7_0_set_interrupt_state,
1759 .process = uvd_v7_0_process_interrupt,
1760};
1761
1762static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1763{
1764 adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1765 adev->uvd.irq.funcs = &uvd_v7_0_irq_funcs;
1766}
1767
1768const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1769{
1770 .type = AMD_IP_BLOCK_TYPE_UVD,
1771 .major = 7,
1772 .minor = 0,
1773 .rev = 0,
1774 .funcs = &uvd_v7_0_ip_funcs,
1775};
Linux 6.x block layer and io_uring tree(s)