[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / tonga_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/pci.h>

#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "vid.h"

#include "oss/oss_3_0_d.h"
#include "oss/oss_3_0_sh_mask.h"

#include "bif/bif_5_1_d.h"
#include "bif/bif_5_1_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (VI).
 */
static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	adev->irq.ih.enabled = true;
}

/**
 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (VI).
 */
static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
{
	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);
	adev->irq.ih.enabled = false;
	adev->irq.ih.rptr = 0;
}

/**
 * tonga_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (VI).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int tonga_ih_irq_init(struct amdgpu_device *adev)
{
	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
	struct amdgpu_ih_ring *ih = &adev->irq.ih;
	int rb_bufsz;

	/* disable irqs */
	tonga_ih_disable_interrupts(adev);

	/* setup interrupt control */
	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
	WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);

	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

	if (adev->irq.msi_enabled)
		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

	WREG32(mmIH_RB_CNTL, ih_rb_cntl);

	/* set the writeback address whether it's enabled or not */
	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);

	/* set rptr, wptr to 0 */
	WREG32(mmIH_RB_RPTR, 0);
	WREG32(mmIH_RB_WPTR, 0);

	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
	if (adev->irq.ih.use_doorbell) {
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 OFFSET, adev->irq.ih.doorbell_index);
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 ENABLE, 1);
	} else {
		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
						 ENABLE, 0);
	}
	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);

	pci_set_master(adev->pdev);

	/* enable interrupts */
	tonga_ih_enable_interrupts(adev);

	return 0;
}

/**
 * tonga_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (VI).
 */
static void tonga_ih_irq_disable(struct amdgpu_device *adev)
{
	tonga_ih_disable_interrupts(adev);

	/* Wait and acknowledge irq */
	mdelay(1);
}

/**
 * tonga_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to fetch wptr
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (VI).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cz_irq_process(VI).
 * Returns the value of the wptr.
 */
static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
			     struct amdgpu_ih_ring *ih)
{
	u32 wptr, tmp;

	wptr = le32_to_cpu(*ih->wptr_cpu);

	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
		goto out;

	/* Double check that the overflow wasn't already cleared. */
	wptr = RREG32(mmIH_RB_WPTR);

	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
		goto out;

	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

	/* When a ring buffer overflow happen start parsing interrupt
	 * from the last not overwritten vector (wptr + 16). Hopefully
	 * this should allow us to catchup.
	 */

	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
		wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
	ih->rptr = (wptr + 16) & ih->ptr_mask;
	tmp = RREG32(mmIH_RB_CNTL);
	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	WREG32(mmIH_RB_CNTL, tmp);

	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
	 * can be detected.
	 */
	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
	WREG32(mmIH_RB_CNTL, tmp);

out:
	return (wptr & ih->ptr_mask);
}

/**
 * tonga_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to decode
 * @entry: IV entry to place decoded information into
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void tonga_ih_decode_iv(struct amdgpu_device *adev,
			       struct amdgpu_ih_ring *ih,
			       struct amdgpu_iv_entry *entry)
{
	/* wptr/rptr are in bytes! */
	u32 ring_index = ih->rptr >> 2;
	uint32_t dw[4];

	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);

	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
	entry->src_id = dw[0] & 0xff;
	entry->src_data[0] = dw[1] & 0xfffffff;
	entry->ring_id = dw[2] & 0xff;
	entry->vmid = (dw[2] >> 8) & 0xff;
	entry->pasid = (dw[2] >> 16) & 0xffff;

	/* wptr/rptr are in bytes! */
	ih->rptr += 16;
}

/**
 * tonga_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to set rptr
 *
 * Set the IH ring buffer rptr.
 */
static void tonga_ih_set_rptr(struct amdgpu_device *adev,
			      struct amdgpu_ih_ring *ih)
{
	if (ih->use_doorbell) {
		/* XXX check if swapping is necessary on BE */
		*ih->rptr_cpu = ih->rptr;
		WDOORBELL32(ih->doorbell_index, ih->rptr);
	} else {
		WREG32(mmIH_RB_RPTR, ih->rptr);
	}
}

static int tonga_ih_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret;

	ret = amdgpu_irq_add_domain(adev);
	if (ret)
		return ret;

	tonga_ih_set_interrupt_funcs(adev);

	return 0;
}

static int tonga_ih_sw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
	if (r)
		return r;

	adev->irq.ih.use_doorbell = true;
	adev->irq.ih.doorbell_index = adev->doorbell_index.ih;

	r = amdgpu_irq_init(adev);

	return r;
}

static int tonga_ih_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_irq_fini_sw(adev);
	amdgpu_irq_remove_domain(adev);

	return 0;
}

static int tonga_ih_hw_init(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = tonga_ih_irq_init(adev);
	if (r)
		return r;

	return 0;
}

static int tonga_ih_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	tonga_ih_irq_disable(adev);

	return 0;
}

static int tonga_ih_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return tonga_ih_hw_fini(adev);
}

static int tonga_ih_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return tonga_ih_hw_init(adev);
}

static bool tonga_ih_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
		return false;

	return true;
}

static int tonga_ih_wait_for_idle(void *handle)
{
	unsigned i;
	u32 tmp;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	for (i = 0; i < adev->usec_timeout; i++) {
		/* read MC_STATUS */
		tmp = RREG32(mmSRBM_STATUS);
		if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
			return 0;
		udelay(1);
	}
	return -ETIMEDOUT;
}

static bool tonga_ih_check_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 srbm_soft_reset = 0;
	u32 tmp = RREG32(mmSRBM_STATUS);

	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
		srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
						SOFT_RESET_IH, 1);

	if (srbm_soft_reset) {
		adev->irq.srbm_soft_reset = srbm_soft_reset;
		return true;
	} else {
		adev->irq.srbm_soft_reset = 0;
		return false;
	}
}

static int tonga_ih_pre_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!adev->irq.srbm_soft_reset)
		return 0;

	return tonga_ih_hw_fini(adev);
}

static int tonga_ih_post_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!adev->irq.srbm_soft_reset)
		return 0;

	return tonga_ih_hw_init(adev);
}

static int tonga_ih_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	u32 srbm_soft_reset;

	if (!adev->irq.srbm_soft_reset)
		return 0;
	srbm_soft_reset = adev->irq.srbm_soft_reset;

	if (srbm_soft_reset) {
		u32 tmp;

		tmp = RREG32(mmSRBM_SOFT_RESET);
		tmp |= srbm_soft_reset;
		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		udelay(50);

		tmp &= ~srbm_soft_reset;
		WREG32(mmSRBM_SOFT_RESET, tmp);
		tmp = RREG32(mmSRBM_SOFT_RESET);

		/* Wait a little for things to settle down */
		udelay(50);
	}

	return 0;
}

static int tonga_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	return 0;
}

static int tonga_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	return 0;
}

static const struct amd_ip_funcs tonga_ih_ip_funcs = {
	.name = "tonga_ih",
	.early_init = tonga_ih_early_init,
	.late_init = NULL,
	.sw_init = tonga_ih_sw_init,
	.sw_fini = tonga_ih_sw_fini,
	.hw_init = tonga_ih_hw_init,
	.hw_fini = tonga_ih_hw_fini,
	.suspend = tonga_ih_suspend,
	.resume = tonga_ih_resume,
	.is_idle = tonga_ih_is_idle,
	.wait_for_idle = tonga_ih_wait_for_idle,
	.check_soft_reset = tonga_ih_check_soft_reset,
	.pre_soft_reset = tonga_ih_pre_soft_reset,
	.soft_reset = tonga_ih_soft_reset,
	.post_soft_reset = tonga_ih_post_soft_reset,
	.set_clockgating_state = tonga_ih_set_clockgating_state,
	.set_powergating_state = tonga_ih_set_powergating_state,
};

static const struct amdgpu_ih_funcs tonga_ih_funcs = {
	.get_wptr = tonga_ih_get_wptr,
	.decode_iv = tonga_ih_decode_iv,
	.set_rptr = tonga_ih_set_rptr
};

static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{
	adev->irq.ih_funcs = &tonga_ih_funcs;
}

const struct amdgpu_ip_block_version tonga_ih_ip_block = {
	.type = AMD_IP_BLOCK_TYPE_IH,
	.major = 3,
	.minor = 0,
	.rev = 0,
	.funcs = &tonga_ih_ip_funcs,
};
Commit	Line	Data
aaa36a97 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
47b757fb SR	23
	24	#include <linux/pci.h>
	25
aaa36a97 AD	26	#include "amdgpu.h"
	27	#include "amdgpu_ih.h"
	28	#include "vid.h"
	29
	30	#include "oss/oss_3_0_d.h"
	31	#include "oss/oss_3_0_sh_mask.h"
	32
	33	#include "bif/bif_5_1_d.h"
	34	#include "bif/bif_5_1_sh_mask.h"
	35
	36	/*
	37	* Interrupts
	38	* Starting with r6xx, interrupts are handled via a ring buffer.
	39	* Ring buffers are areas of GPU accessible memory that the GPU
	40	* writes interrupt vectors into and the host reads vectors out of.
	41	* There is a rptr (read pointer) that determines where the
	42	* host is currently reading, and a wptr (write pointer)
	43	* which determines where the GPU has written. When the
	44	* pointers are equal, the ring is idle. When the GPU
	45	* writes vectors to the ring buffer, it increments the
	46	* wptr. When there is an interrupt, the host then starts
	47	* fetching commands and processing them until the pointers are
	48	* equal again at which point it updates the rptr.
	49	*/
	50
	51	static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
	52
	53	/**
	54	* tonga_ih_enable_interrupts - Enable the interrupt ring buffer
	55	*
	56	* @adev: amdgpu_device pointer
	57	*
	58	* Enable the interrupt ring buffer (VI).
	59	*/
	60	static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
	61	{
	62	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	63
	64	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
	65	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
	66	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	67	adev->irq.ih.enabled = true;
	68	}
	69
	70	/**
	71	* tonga_ih_disable_interrupts - Disable the interrupt ring buffer
	72	*
	73	* @adev: amdgpu_device pointer
	74	*
	75	* Disable the interrupt ring buffer (VI).
	76	*/
	77	static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
	78	{
	79	u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
	80
	81	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
	82	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
	83	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	84	/* set rptr, wptr to 0 */
	85	WREG32(mmIH_RB_RPTR, 0);
	86	WREG32(mmIH_RB_WPTR, 0);
	87	adev->irq.ih.enabled = false;
	88	adev->irq.ih.rptr = 0;
	89	}
90
91	/**
92	* tonga_ih_irq_init - init and enable the interrupt ring
93	*
94	* @adev: amdgpu_device pointer
95	*
96	* Allocate a ring buffer for the interrupt controller,
97	* enable the RLC, disable interrupts, enable the IH
98	* ring buffer and enable it (VI).
99	* Called at device load and reume.
100	* Returns 0 for success, errors for failure.
101	*/
102	static int tonga_ih_irq_init(struct amdgpu_device *adev)
103	{
aaa36a97	104	u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
d81f78b4 CK	105	struct amdgpu_ih_ring *ih = &adev->irq.ih;
d81f78b4 CK	106	int rb_bufsz;
aaa36a97 AD	107
	108	/* disable irqs */
	109	tonga_ih_disable_interrupts(adev);
	110
	111	/* setup interrupt control */
92e71b06	112	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
aaa36a97 AD	113	interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
	114	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	115	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	116	*/
	117	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	118	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	119	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	120	WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
	121
	122	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
d81f78b4	123	WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
aaa36a97 AD	124
	125	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
	126	ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	127	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
	128	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
	129	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
	130	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
	131
	132	if (adev->irq.msi_enabled)
	133	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
	134
	135	WREG32(mmIH_RB_CNTL, ih_rb_cntl);
	136
	137	/* set the writeback address whether it's enabled or not */
d81f78b4 CK	138	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
d81f78b4 CK	139	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
aaa36a97 AD	140
	141	/* set rptr, wptr to 0 */
	142	WREG32(mmIH_RB_RPTR, 0);
	143	WREG32(mmIH_RB_WPTR, 0);
	144
	145	ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
	146	if (adev->irq.ih.use_doorbell) {
	147	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
	148	OFFSET, adev->irq.ih.doorbell_index);
	149	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
	150	ENABLE, 1);
	151	} else {
	152	ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
	153	ENABLE, 0);
	154	}
	155	WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
	156
	157	pci_set_master(adev->pdev);
	158
	159	/* enable interrupts */
	160	tonga_ih_enable_interrupts(adev);
	161
2f46b2a5	162	return 0;
aaa36a97 AD	163	}
	164
	165	/**
	166	* tonga_ih_irq_disable - disable interrupts
	167	*
	168	* @adev: amdgpu_device pointer
	169	*
	170	* Disable interrupts on the hw (VI).
	171	*/
	172	static void tonga_ih_irq_disable(struct amdgpu_device *adev)
	173	{
	174	tonga_ih_disable_interrupts(adev);
	175
	176	/* Wait and acknowledge irq */
	177	mdelay(1);
	178	}
	179
	180	/**
	181	* tonga_ih_get_wptr - get the IH ring buffer wptr
	182	*
	183	* @adev: amdgpu_device pointer
39902109	184	* @ih: IH ring buffer to fetch wptr
aaa36a97 AD	185	*
	186	* Get the IH ring buffer wptr from either the register
	187	* or the writeback memory buffer (VI). Also check for
	188	* ring buffer overflow and deal with it.
	189	* Used by cz_irq_process(VI).
	190	* Returns the value of the wptr.
	191	*/
8bb9eb48 CK	192	static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
8bb9eb48 CK	193	struct amdgpu_ih_ring *ih)
aaa36a97 AD	194	{
	195	u32 wptr, tmp;
	196
d81f78b4	197	wptr = le32_to_cpu(*ih->wptr_cpu);
aaa36a97	198
e4180c42 DB	199	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
	200	goto out;
	201
	202	/* Double check that the overflow wasn't already cleared. */
	203	wptr = RREG32(mmIH_RB_WPTR);
	204
	205	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
	206	goto out;
	207
	208	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
	209
	210	/* When a ring buffer overflow happen start parsing interrupt
	211	* from the last not overwritten vector (wptr + 16). Hopefully
	212	* this should allow us to catchup.
	213	*/
	214
	215	dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
	216	wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
	217	ih->rptr = (wptr + 16) & ih->ptr_mask;
	218	tmp = RREG32(mmIH_RB_CNTL);
	219	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
	220	WREG32(mmIH_RB_CNTL, tmp);
	221
9217b91c FV	222	/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
	223	* can be detected.
	224	*/
	225	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
	226	WREG32(mmIH_RB_CNTL, tmp);
	227
e4180c42	228	out:
8bb9eb48	229	return (wptr & ih->ptr_mask);
aaa36a97 AD	230	}
	231
	232	/**
	233	* tonga_ih_decode_iv - decode an interrupt vector
	234	*
	235	* @adev: amdgpu_device pointer
39902109 LJ	236	* @ih: IH ring buffer to decode
39902109 LJ	237	* @entry: IV entry to place decoded information into
aaa36a97 AD	238	*
	239	* Decodes the interrupt vector at the current rptr
	240	* position and also advance the position.
	241	*/
	242	static void tonga_ih_decode_iv(struct amdgpu_device *adev,
8bb9eb48 CK	243	struct amdgpu_ih_ring *ih,
8bb9eb48 CK	244	struct amdgpu_iv_entry *entry)
aaa36a97 AD	245	{
aaa36a97 AD	246	/* wptr/rptr are in bytes! */
8bb9eb48	247	u32 ring_index = ih->rptr >> 2;
aaa36a97 AD	248	uint32_t dw[4];
aaa36a97 AD	249
8bb9eb48 CK	250	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
	251	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
	252	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
	253	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
aaa36a97	254
1ffdeca6	255	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
aaa36a97	256	entry->src_id = dw[0] & 0xff;
7ccf5aa8	257	entry->src_data[0] = dw[1] & 0xfffffff;
aaa36a97	258	entry->ring_id = dw[2] & 0xff;
c4f46f22	259	entry->vmid = (dw[2] >> 8) & 0xff;
3816e42f	260	entry->pasid = (dw[2] >> 16) & 0xffff;
aaa36a97 AD	261
aaa36a97 AD	262	/* wptr/rptr are in bytes! */
8bb9eb48	263	ih->rptr += 16;
aaa36a97 AD	264	}
	265
	266	/**
	267	* tonga_ih_set_rptr - set the IH ring buffer rptr
	268	*
	269	* @adev: amdgpu_device pointer
39902109	270	* @ih: IH ring buffer to set rptr
aaa36a97 AD	271	*
	272	* Set the IH ring buffer rptr.
	273	*/
8bb9eb48 CK	274	static void tonga_ih_set_rptr(struct amdgpu_device *adev,
8bb9eb48 CK	275	struct amdgpu_ih_ring *ih)
aaa36a97	276	{
8bb9eb48	277	if (ih->use_doorbell) {
aaa36a97	278	/* XXX check if swapping is necessary on BE */
d81f78b4	279	*ih->rptr_cpu = ih->rptr;
8bb9eb48	280	WDOORBELL32(ih->doorbell_index, ih->rptr);
aaa36a97	281	} else {
8bb9eb48	282	WREG32(mmIH_RB_RPTR, ih->rptr);
aaa36a97 AD	283	}
	284	}
	285
5fc3aeeb	286	static int tonga_ih_early_init(void *handle)
aaa36a97	287	{
5fc3aeeb	288	struct amdgpu_device adev = (struct amdgpu_device )handle;
5f232365 AD	289	int ret;
	290
	291	ret = amdgpu_irq_add_domain(adev);
	292	if (ret)
	293	return ret;
5fc3aeeb	294
aaa36a97	295	tonga_ih_set_interrupt_funcs(adev);
5f232365	296
aaa36a97 AD	297	return 0;
	298	}
	299
5fc3aeeb	300	static int tonga_ih_sw_init(void *handle)
aaa36a97 AD	301	{
aaa36a97 AD	302	int r;
5fc3aeeb	303	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97	304
425c3143	305	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true);
aaa36a97 AD	306	if (r)
	307	return r;
	308
	309	adev->irq.ih.use_doorbell = true;
9564f192	310	adev->irq.ih.doorbell_index = adev->doorbell_index.ih;
aaa36a97 AD	311
	312	r = amdgpu_irq_init(adev);
	313
	314	return r;
	315	}
	316
5fc3aeeb	317	static int tonga_ih_sw_fini(void *handle)
aaa36a97	318	{
5fc3aeeb	319	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	320
72c8c97b	321	amdgpu_irq_fini_sw(adev);
303f551c	322	amdgpu_irq_remove_domain(adev);
aaa36a97 AD	323
	324	return 0;
	325	}
	326
5fc3aeeb	327	static int tonga_ih_hw_init(void *handle)
aaa36a97 AD	328	{
aaa36a97 AD	329	int r;
5fc3aeeb	330	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	331
	332	r = tonga_ih_irq_init(adev);
	333	if (r)
	334	return r;
	335
	336	return 0;
	337	}
	338
5fc3aeeb	339	static int tonga_ih_hw_fini(void *handle)
aaa36a97	340	{
5fc3aeeb	341	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	342
aaa36a97 AD	343	tonga_ih_irq_disable(adev);
	344
	345	return 0;
	346	}
	347
5fc3aeeb	348	static int tonga_ih_suspend(void *handle)
aaa36a97	349	{
5fc3aeeb	350	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	351
aaa36a97 AD	352	return tonga_ih_hw_fini(adev);
	353	}
	354
5fc3aeeb	355	static int tonga_ih_resume(void *handle)
aaa36a97	356	{
5fc3aeeb	357	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	358
aaa36a97 AD	359	return tonga_ih_hw_init(adev);
	360	}
	361
5fc3aeeb	362	static bool tonga_ih_is_idle(void *handle)
aaa36a97	363	{
5fc3aeeb	364	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	365	u32 tmp = RREG32(mmSRBM_STATUS);
	366
	367	if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	368	return false;
	369
	370	return true;
	371	}
	372
5fc3aeeb	373	static int tonga_ih_wait_for_idle(void *handle)
aaa36a97 AD	374	{
	375	unsigned i;
	376	u32 tmp;
5fc3aeeb	377	struct amdgpu_device adev = (struct amdgpu_device )handle;
aaa36a97 AD	378
	379	for (i = 0; i < adev->usec_timeout; i++) {
	380	/* read MC_STATUS */
	381	tmp = RREG32(mmSRBM_STATUS);
	382	if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
	383	return 0;
	384	udelay(1);
	385	}
	386	return -ETIMEDOUT;
	387	}
	388
da146d3b	389	static bool tonga_ih_check_soft_reset(void *handle)
aaa36a97	390	{
5fc3aeeb	391	struct amdgpu_device adev = (struct amdgpu_device )handle;
1015a1b1	392	u32 srbm_soft_reset = 0;
aaa36a97 AD	393	u32 tmp = RREG32(mmSRBM_STATUS);
	394
	395	if (tmp & SRBM_STATUS__IH_BUSY_MASK)
	396	srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
	397	SOFT_RESET_IH, 1);
	398
	399	if (srbm_soft_reset) {
1015a1b1	400	adev->irq.srbm_soft_reset = srbm_soft_reset;
da146d3b	401	return true;
1015a1b1	402	} else {
1015a1b1	403	adev->irq.srbm_soft_reset = 0;
da146d3b	404	return false;
1015a1b1	405	}
1015a1b1 CZ	406	}
	407
	408	static int tonga_ih_pre_soft_reset(void *handle)
	409	{
	410	struct amdgpu_device adev = (struct amdgpu_device )handle;
	411
da146d3b	412	if (!adev->irq.srbm_soft_reset)
1015a1b1 CZ	413	return 0;
	414
	415	return tonga_ih_hw_fini(adev);
	416	}
	417
	418	static int tonga_ih_post_soft_reset(void *handle)
	419	{
	420	struct amdgpu_device adev = (struct amdgpu_device )handle;
	421
da146d3b	422	if (!adev->irq.srbm_soft_reset)
1015a1b1 CZ	423	return 0;
	424
	425	return tonga_ih_hw_init(adev);
	426	}
	427
	428	static int tonga_ih_soft_reset(void *handle)
	429	{
	430	struct amdgpu_device adev = (struct amdgpu_device )handle;
	431	u32 srbm_soft_reset;
	432
da146d3b	433	if (!adev->irq.srbm_soft_reset)
1015a1b1 CZ	434	return 0;
	435	srbm_soft_reset = adev->irq.srbm_soft_reset;
	436
	437	if (srbm_soft_reset) {
	438	u32 tmp;
	439
aaa36a97 AD	440	tmp = RREG32(mmSRBM_SOFT_RESET);
	441	tmp \|= srbm_soft_reset;
	442	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
	443	WREG32(mmSRBM_SOFT_RESET, tmp);
	444	tmp = RREG32(mmSRBM_SOFT_RESET);
	445
	446	udelay(50);
	447
	448	tmp &= ~srbm_soft_reset;
	449	WREG32(mmSRBM_SOFT_RESET, tmp);
	450	tmp = RREG32(mmSRBM_SOFT_RESET);
	451
	452	/* Wait a little for things to settle down */
	453	udelay(50);
aaa36a97 AD	454	}
	455
	456	return 0;
	457	}
	458
5fc3aeeb	459	static int tonga_ih_set_clockgating_state(void *handle,
5fc3aeeb	460	enum amd_clockgating_state state)
aaa36a97	461	{
aaa36a97 AD	462	return 0;
	463	}
	464
5fc3aeeb	465	static int tonga_ih_set_powergating_state(void *handle,
5fc3aeeb	466	enum amd_powergating_state state)
aaa36a97	467	{
aaa36a97 AD	468	return 0;
	469	}
	470
a1255107	471	static const struct amd_ip_funcs tonga_ih_ip_funcs = {
88a907d6	472	.name = "tonga_ih",
aaa36a97 AD	473	.early_init = tonga_ih_early_init,
	474	.late_init = NULL,
	475	.sw_init = tonga_ih_sw_init,
	476	.sw_fini = tonga_ih_sw_fini,
	477	.hw_init = tonga_ih_hw_init,
	478	.hw_fini = tonga_ih_hw_fini,
	479	.suspend = tonga_ih_suspend,
	480	.resume = tonga_ih_resume,
	481	.is_idle = tonga_ih_is_idle,
	482	.wait_for_idle = tonga_ih_wait_for_idle,
1015a1b1 CZ	483	.check_soft_reset = tonga_ih_check_soft_reset,
1015a1b1 CZ	484	.pre_soft_reset = tonga_ih_pre_soft_reset,
aaa36a97	485	.soft_reset = tonga_ih_soft_reset,
1015a1b1	486	.post_soft_reset = tonga_ih_post_soft_reset,
aaa36a97 AD	487	.set_clockgating_state = tonga_ih_set_clockgating_state,
	488	.set_powergating_state = tonga_ih_set_powergating_state,
	489	};
	490
	491	static const struct amdgpu_ih_funcs tonga_ih_funcs = {
	492	.get_wptr = tonga_ih_get_wptr,
	493	.decode_iv = tonga_ih_decode_iv,
	494	.set_rptr = tonga_ih_set_rptr
	495	};
	496
	497	static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
	498	{
f54b30d7	499	adev->irq.ih_funcs = &tonga_ih_funcs;
aaa36a97 AD	500	}
aaa36a97 AD	501
7bb8c4f6	502	const struct amdgpu_ip_block_version tonga_ih_ip_block = {
a1255107 AD	503	.type = AMD_IP_BLOCK_TYPE_IH,
	504	.major = 3,
	505	.minor = 0,
	506	.rev = 0,
	507	.funcs = &tonga_ih_ip_funcs,
	508	};