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1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/pci.h> | |
27 | ||
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_atombios.h" | |
30 | #include "amdgpu_ih.h" | |
31 | #include "amdgpu_uvd.h" | |
32 | #include "amdgpu_vce.h" | |
33 | #include "amdgpu_ucode.h" | |
34 | #include "amdgpu_psp.h" | |
35 | #include "amdgpu_smu.h" | |
36 | #include "atom.h" | |
37 | #include "amd_pcie.h" | |
38 | ||
39 | #include "gc/gc_11_0_0_offset.h" | |
40 | #include "gc/gc_11_0_0_sh_mask.h" | |
41 | #include "mp/mp_13_0_0_offset.h" | |
42 | ||
43 | #include "soc15.h" | |
44 | #include "soc15_common.h" | |
45 | ||
46 | static const struct amd_ip_funcs soc21_common_ip_funcs; | |
47 | ||
48 | /* | |
49 | * Indirect registers accessor | |
50 | */ | |
51 | static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg) | |
52 | { | |
53 | unsigned long address, data; | |
54 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
55 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
56 | ||
57 | return amdgpu_device_indirect_rreg(adev, address, data, reg); | |
58 | } | |
59 | ||
60 | static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
61 | { | |
62 | unsigned long address, data; | |
63 | ||
64 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
65 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
66 | ||
67 | amdgpu_device_indirect_wreg(adev, address, data, reg, v); | |
68 | } | |
69 | ||
70 | static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg) | |
71 | { | |
72 | unsigned long address, data; | |
73 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
74 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
75 | ||
76 | return amdgpu_device_indirect_rreg64(adev, address, data, reg); | |
77 | } | |
78 | ||
79 | static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) | |
80 | { | |
81 | unsigned long address, data; | |
82 | ||
83 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
84 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
85 | ||
86 | amdgpu_device_indirect_wreg64(adev, address, data, reg, v); | |
87 | } | |
88 | ||
89 | static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) | |
90 | { | |
91 | unsigned long flags, address, data; | |
92 | u32 r; | |
93 | ||
94 | address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); | |
95 | data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); | |
96 | ||
97 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
98 | WREG32(address, (reg)); | |
99 | r = RREG32(data); | |
100 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
101 | return r; | |
102 | } | |
103 | ||
104 | static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
105 | { | |
106 | unsigned long flags, address, data; | |
107 | ||
108 | address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); | |
109 | data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); | |
110 | ||
111 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
112 | WREG32(address, (reg)); | |
113 | WREG32(data, (v)); | |
114 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
115 | } | |
116 | ||
117 | static u32 soc21_get_config_memsize(struct amdgpu_device *adev) | |
118 | { | |
119 | return adev->nbio.funcs->get_memsize(adev); | |
120 | } | |
121 | ||
122 | static u32 soc21_get_xclk(struct amdgpu_device *adev) | |
123 | { | |
124 | return adev->clock.spll.reference_freq; | |
125 | } | |
126 | ||
127 | ||
128 | void soc21_grbm_select(struct amdgpu_device *adev, | |
129 | u32 me, u32 pipe, u32 queue, u32 vmid) | |
130 | { | |
131 | u32 grbm_gfx_cntl = 0; | |
132 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); | |
133 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); | |
134 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); | |
135 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); | |
136 | ||
137 | WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL), grbm_gfx_cntl); | |
138 | } | |
139 | ||
140 | static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) | |
141 | { | |
142 | /* todo */ | |
143 | } | |
144 | ||
145 | static bool soc21_read_disabled_bios(struct amdgpu_device *adev) | |
146 | { | |
147 | /* todo */ | |
148 | return false; | |
149 | } | |
150 | ||
151 | static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { | |
152 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, | |
153 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, | |
154 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, | |
155 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, | |
156 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, | |
157 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, | |
158 | { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, | |
159 | { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, | |
160 | { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, | |
161 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, | |
162 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, | |
163 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, | |
164 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, | |
165 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, | |
166 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, | |
167 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, | |
168 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, | |
169 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, | |
170 | { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, | |
171 | }; | |
172 | ||
173 | static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, | |
174 | u32 sh_num, u32 reg_offset) | |
175 | { | |
176 | uint32_t val; | |
177 | ||
178 | mutex_lock(&adev->grbm_idx_mutex); | |
179 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
180 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); | |
181 | ||
182 | val = RREG32(reg_offset); | |
183 | ||
184 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
185 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
186 | mutex_unlock(&adev->grbm_idx_mutex); | |
187 | return val; | |
188 | } | |
189 | ||
190 | static uint32_t soc21_get_register_value(struct amdgpu_device *adev, | |
191 | bool indexed, u32 se_num, | |
192 | u32 sh_num, u32 reg_offset) | |
193 | { | |
194 | if (indexed) { | |
195 | return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); | |
196 | } else { | |
197 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) | |
198 | return adev->gfx.config.gb_addr_config; | |
199 | return RREG32(reg_offset); | |
200 | } | |
201 | } | |
202 | ||
203 | static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, | |
204 | u32 sh_num, u32 reg_offset, u32 *value) | |
205 | { | |
206 | uint32_t i; | |
207 | struct soc15_allowed_register_entry *en; | |
208 | ||
209 | *value = 0; | |
210 | for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { | |
211 | en = &soc21_allowed_read_registers[i]; | |
212 | if (reg_offset != | |
213 | (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) | |
214 | continue; | |
215 | ||
216 | *value = soc21_get_register_value(adev, | |
217 | soc21_allowed_read_registers[i].grbm_indexed, | |
218 | se_num, sh_num, reg_offset); | |
219 | return 0; | |
220 | } | |
221 | return -EINVAL; | |
222 | } | |
223 | ||
224 | #if 0 | |
225 | static int soc21_asic_mode1_reset(struct amdgpu_device *adev) | |
226 | { | |
227 | u32 i; | |
228 | int ret = 0; | |
229 | ||
230 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
231 | ||
232 | /* disable BM */ | |
233 | pci_clear_master(adev->pdev); | |
234 | ||
235 | amdgpu_device_cache_pci_state(adev->pdev); | |
236 | ||
237 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
238 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
239 | ret = amdgpu_dpm_mode1_reset(adev); | |
240 | } else { | |
241 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
242 | ret = psp_gpu_reset(adev); | |
243 | } | |
244 | ||
245 | if (ret) | |
246 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
247 | amdgpu_device_load_pci_state(adev->pdev); | |
248 | ||
249 | /* wait for asic to come out of reset */ | |
250 | for (i = 0; i < adev->usec_timeout; i++) { | |
251 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
252 | ||
253 | if (memsize != 0xffffffff) | |
254 | break; | |
255 | udelay(1); | |
256 | } | |
257 | ||
258 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
259 | ||
260 | return ret; | |
261 | } | |
262 | #endif | |
263 | ||
264 | static enum amd_reset_method | |
265 | soc21_asic_reset_method(struct amdgpu_device *adev) | |
266 | { | |
267 | if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || | |
268 | amdgpu_reset_method == AMD_RESET_METHOD_BACO) | |
269 | return amdgpu_reset_method; | |
270 | ||
271 | if (amdgpu_reset_method != -1) | |
272 | dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", | |
273 | amdgpu_reset_method); | |
274 | ||
275 | switch (adev->ip_versions[MP1_HWIP][0]) { | |
276 | case IP_VERSION(13, 0, 0): | |
277 | return AMD_RESET_METHOD_MODE1; | |
278 | default: | |
279 | if (amdgpu_dpm_is_baco_supported(adev)) | |
280 | return AMD_RESET_METHOD_BACO; | |
281 | else | |
282 | return AMD_RESET_METHOD_MODE1; | |
283 | } | |
284 | } | |
285 | ||
286 | static int soc21_asic_reset(struct amdgpu_device *adev) | |
287 | { | |
288 | int ret = 0; | |
289 | ||
290 | switch (soc21_asic_reset_method(adev)) { | |
291 | case AMD_RESET_METHOD_PCI: | |
292 | dev_info(adev->dev, "PCI reset\n"); | |
293 | ret = amdgpu_device_pci_reset(adev); | |
294 | break; | |
295 | case AMD_RESET_METHOD_BACO: | |
296 | dev_info(adev->dev, "BACO reset\n"); | |
297 | ret = amdgpu_dpm_baco_reset(adev); | |
298 | break; | |
299 | default: | |
300 | dev_info(adev->dev, "MODE1 reset\n"); | |
301 | ret = amdgpu_device_mode1_reset(adev); | |
302 | break; | |
303 | } | |
304 | ||
305 | return ret; | |
306 | } | |
307 | ||
308 | static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) | |
309 | { | |
310 | /* todo */ | |
311 | return 0; | |
312 | } | |
313 | ||
314 | static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) | |
315 | { | |
316 | /* todo */ | |
317 | return 0; | |
318 | } | |
319 | ||
320 | static void soc21_pcie_gen3_enable(struct amdgpu_device *adev) | |
321 | { | |
322 | if (pci_is_root_bus(adev->pdev->bus)) | |
323 | return; | |
324 | ||
325 | if (amdgpu_pcie_gen2 == 0) | |
326 | return; | |
327 | ||
328 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
329 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) | |
330 | return; | |
331 | ||
332 | /* todo */ | |
333 | } | |
334 | ||
335 | static void soc21_program_aspm(struct amdgpu_device *adev) | |
336 | { | |
337 | ||
338 | if (amdgpu_aspm == 0) | |
339 | return; | |
340 | ||
341 | /* todo */ | |
342 | } | |
343 | ||
344 | static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, | |
345 | bool enable) | |
346 | { | |
347 | adev->nbio.funcs->enable_doorbell_aperture(adev, enable); | |
348 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); | |
349 | } | |
350 | ||
351 | const struct amdgpu_ip_block_version soc21_common_ip_block = | |
352 | { | |
353 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
354 | .major = 1, | |
355 | .minor = 0, | |
356 | .rev = 0, | |
357 | .funcs = &soc21_common_ip_funcs, | |
358 | }; | |
359 | ||
360 | static uint32_t soc21_get_rev_id(struct amdgpu_device *adev) | |
361 | { | |
362 | return adev->nbio.funcs->get_rev_id(adev); | |
363 | } | |
364 | ||
365 | static bool soc21_need_full_reset(struct amdgpu_device *adev) | |
366 | { | |
367 | return true; | |
368 | } | |
369 | ||
370 | static bool soc21_need_reset_on_init(struct amdgpu_device *adev) | |
371 | { | |
372 | u32 sol_reg; | |
373 | ||
374 | if (adev->flags & AMD_IS_APU) | |
375 | return false; | |
376 | ||
377 | /* Check sOS sign of life register to confirm sys driver and sOS | |
378 | * are already been loaded. | |
379 | */ | |
380 | sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); | |
381 | if (sol_reg) | |
382 | return true; | |
383 | ||
384 | return false; | |
385 | } | |
386 | ||
387 | static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev) | |
388 | { | |
389 | ||
390 | /* TODO | |
391 | * dummy implement for pcie_replay_count sysfs interface | |
392 | * */ | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | static void soc21_init_doorbell_index(struct amdgpu_device *adev) | |
398 | { | |
399 | adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; | |
400 | adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; | |
401 | adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; | |
402 | adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; | |
403 | adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; | |
404 | adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; | |
405 | adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; | |
406 | adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; | |
407 | adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; | |
408 | adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; | |
409 | adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; | |
410 | adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; | |
411 | adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; | |
412 | adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; | |
413 | adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; | |
414 | adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; | |
415 | adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; | |
416 | adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; | |
417 | adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; | |
418 | adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; | |
419 | adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; | |
420 | adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; | |
421 | adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; | |
422 | ||
423 | adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; | |
424 | adev->doorbell_index.sdma_doorbell_range = 20; | |
425 | } | |
426 | ||
427 | static void soc21_pre_asic_init(struct amdgpu_device *adev) | |
428 | { | |
429 | } | |
430 | ||
431 | static const struct amdgpu_asic_funcs soc21_asic_funcs = | |
432 | { | |
433 | .read_disabled_bios = &soc21_read_disabled_bios, | |
434 | .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, | |
435 | .read_register = &soc21_read_register, | |
436 | .reset = &soc21_asic_reset, | |
437 | .reset_method = &soc21_asic_reset_method, | |
438 | .set_vga_state = &soc21_vga_set_state, | |
439 | .get_xclk = &soc21_get_xclk, | |
440 | .set_uvd_clocks = &soc21_set_uvd_clocks, | |
441 | .set_vce_clocks = &soc21_set_vce_clocks, | |
442 | .get_config_memsize = &soc21_get_config_memsize, | |
443 | .init_doorbell_index = &soc21_init_doorbell_index, | |
444 | .need_full_reset = &soc21_need_full_reset, | |
445 | .need_reset_on_init = &soc21_need_reset_on_init, | |
446 | .get_pcie_replay_count = &soc21_get_pcie_replay_count, | |
447 | .supports_baco = &amdgpu_dpm_is_baco_supported, | |
448 | .pre_asic_init = &soc21_pre_asic_init, | |
449 | }; | |
450 | ||
451 | static int soc21_common_early_init(void *handle) | |
452 | { | |
453 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) | |
454 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
455 | ||
456 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; | |
457 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; | |
458 | adev->smc_rreg = NULL; | |
459 | adev->smc_wreg = NULL; | |
460 | adev->pcie_rreg = &soc21_pcie_rreg; | |
461 | adev->pcie_wreg = &soc21_pcie_wreg; | |
462 | adev->pcie_rreg64 = &soc21_pcie_rreg64; | |
463 | adev->pcie_wreg64 = &soc21_pcie_wreg64; | |
464 | ||
465 | /* TODO: will add them during VCN v2 implementation */ | |
466 | adev->uvd_ctx_rreg = NULL; | |
467 | adev->uvd_ctx_wreg = NULL; | |
468 | ||
469 | adev->didt_rreg = &soc21_didt_rreg; | |
470 | adev->didt_wreg = &soc21_didt_wreg; | |
471 | ||
472 | adev->asic_funcs = &soc21_asic_funcs; | |
473 | ||
474 | adev->rev_id = soc21_get_rev_id(adev); | |
475 | adev->external_rev_id = 0xff; | |
476 | switch (adev->ip_versions[GC_HWIP][0]) { | |
477 | case IP_VERSION(11, 0, 0): | |
478 | adev->cg_flags = 0; | |
479 | adev->pg_flags = 0; | |
480 | adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update | |
481 | break; | |
482 | default: | |
483 | /* FIXME: not supported yet */ | |
484 | return -EINVAL; | |
485 | } | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static int soc21_common_late_init(void *handle) | |
491 | { | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static int soc21_common_sw_init(void *handle) | |
496 | { | |
497 | return 0; | |
498 | } | |
499 | ||
500 | static int soc21_common_sw_fini(void *handle) | |
501 | { | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static int soc21_common_hw_init(void *handle) | |
506 | { | |
507 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
508 | ||
509 | /* enable pcie gen2/3 link */ | |
510 | soc21_pcie_gen3_enable(adev); | |
511 | /* enable aspm */ | |
512 | soc21_program_aspm(adev); | |
513 | /* setup nbio registers */ | |
514 | adev->nbio.funcs->init_registers(adev); | |
515 | /* remap HDP registers to a hole in mmio space, | |
516 | * for the purpose of expose those registers | |
517 | * to process space | |
518 | */ | |
519 | if (adev->nbio.funcs->remap_hdp_registers) | |
520 | adev->nbio.funcs->remap_hdp_registers(adev); | |
521 | /* enable the doorbell aperture */ | |
522 | soc21_enable_doorbell_aperture(adev, true); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static int soc21_common_hw_fini(void *handle) | |
528 | { | |
529 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
530 | ||
531 | /* disable the doorbell aperture */ | |
532 | soc21_enable_doorbell_aperture(adev, false); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | static int soc21_common_suspend(void *handle) | |
538 | { | |
539 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
540 | ||
541 | return soc21_common_hw_fini(adev); | |
542 | } | |
543 | ||
544 | static int soc21_common_resume(void *handle) | |
545 | { | |
546 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
547 | ||
548 | return soc21_common_hw_init(adev); | |
549 | } | |
550 | ||
551 | static bool soc21_common_is_idle(void *handle) | |
552 | { | |
553 | return true; | |
554 | } | |
555 | ||
556 | static int soc21_common_wait_for_idle(void *handle) | |
557 | { | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static int soc21_common_soft_reset(void *handle) | |
562 | { | |
563 | return 0; | |
564 | } | |
565 | ||
566 | static int soc21_common_set_clockgating_state(void *handle, | |
567 | enum amd_clockgating_state state) | |
568 | { | |
569 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
570 | ||
571 | switch (adev->ip_versions[NBIO_HWIP][0]) { | |
572 | case IP_VERSION(4, 3, 0): | |
573 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, | |
574 | state == AMD_CG_STATE_GATE); | |
575 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, | |
576 | state == AMD_CG_STATE_GATE); | |
577 | adev->hdp.funcs->update_clock_gating(adev, | |
578 | state == AMD_CG_STATE_GATE); | |
579 | break; | |
580 | default: | |
581 | break; | |
582 | } | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static int soc21_common_set_powergating_state(void *handle, | |
587 | enum amd_powergating_state state) | |
588 | { | |
589 | /* TODO */ | |
590 | return 0; | |
591 | } | |
592 | ||
593 | static void soc21_common_get_clockgating_state(void *handle, u64 *flags) | |
594 | { | |
595 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
596 | ||
597 | adev->nbio.funcs->get_clockgating_state(adev, flags); | |
598 | ||
599 | adev->hdp.funcs->get_clock_gating_state(adev, flags); | |
600 | ||
601 | return; | |
602 | } | |
603 | ||
604 | static const struct amd_ip_funcs soc21_common_ip_funcs = { | |
605 | .name = "soc21_common", | |
606 | .early_init = soc21_common_early_init, | |
607 | .late_init = soc21_common_late_init, | |
608 | .sw_init = soc21_common_sw_init, | |
609 | .sw_fini = soc21_common_sw_fini, | |
610 | .hw_init = soc21_common_hw_init, | |
611 | .hw_fini = soc21_common_hw_fini, | |
612 | .suspend = soc21_common_suspend, | |
613 | .resume = soc21_common_resume, | |
614 | .is_idle = soc21_common_is_idle, | |
615 | .wait_for_idle = soc21_common_wait_for_idle, | |
616 | .soft_reset = soc21_common_soft_reset, | |
617 | .set_clockgating_state = soc21_common_set_clockgating_state, | |
618 | .set_powergating_state = soc21_common_set_powergating_state, | |
619 | .get_clockgating_state = soc21_common_get_clockgating_state, | |
620 | }; |