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drm/amdgpu: Use function for IP version check
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / soc21.c
CommitLineData
71199aa4
SY		 1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "amdgpu_smu.h"
36#include "atom.h"
37#include "amd_pcie.h"
38
39#include "gc/gc_11_0_0_offset.h"
40#include "gc/gc_11_0_0_sh_mask.h"
41#include "mp/mp_13_0_0_offset.h"
42
43#include "soc15.h"
44#include "soc15_common.h"
caa5eadc 45#include "soc21.h"
39dd895d 46#include "mxgpu_nv.h"
71199aa4
SY		 47
48static const struct amd_ip_funcs soc21_common_ip_funcs;
49
9ac0edaa 50/* SOC21 */
06d82d87 51static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
9ac0edaa
JZ		 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
f732e2b3 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
9ac0edaa
JZ		 55};
56
06d82d87 57static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
a6de636e
AD		 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
60};
61
06d82d87 62static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
a6de636e
AD		 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
9ac0edaa
JZ		 65};
66
06d82d87 67static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
a6de636e
AD		 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
70};
71
06d82d87 72static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
65009bf2 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
9ac0edaa
JZ		 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
78};
79
06d82d87 80static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
a6de636e
AD		 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
85};
86
06d82d87 87static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
a6de636e
AD		 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
90};
91
06d82d87 92static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
a6de636e
AD		 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
9ac0edaa
JZ		 95};
96
dcaf5000
JJ		 97/* SRIOV SOC21, not const since data is controlled by host */
98static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102};
103
104static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
107};
108
109static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
112};
113
114static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
117};
118
119static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
128};
129
130static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
136 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
137 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
138};
139
140static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
141 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
142 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
143};
144
145static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
146 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
147 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
148};
149
9ac0edaa
JZ		 150static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
151 const struct amdgpu_video_codecs **codecs)
152{
a6de636e
AD		 153 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
154 return -EINVAL;
9ac0edaa 155
4e8303cf 156 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
9ac0edaa 157 case IP_VERSION(4, 0, 0):
1c0a9036 158 case IP_VERSION(4, 0, 2):
d068b700 159 case IP_VERSION(4, 0, 4):
c64f3895 160 case IP_VERSION(4, 0, 5):
dcaf5000
JJ		 161 if (amdgpu_sriov_vf(adev)) {
162 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
163 !amdgpu_sriov_is_av1_support(adev)) {
164 if (encode)
165 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
166 else
167 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
168 } else {
169 if (encode)
170 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
171 else
172 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
173 }
a6de636e 174 } else {
dcaf5000
JJ		 175 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
176 if (encode)
177 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
178 else
179 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
180 } else {
181 if (encode)
182 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
183 else
184 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
185 }
a6de636e 186 }
9ac0edaa
JZ		 187 return 0;
188 default:
189 return -EINVAL;
190 }
191}
71199aa4
SY		 192
193static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
194{
195 unsigned long flags, address, data;
196 u32 r;
197
198 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
199 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
200
201 spin_lock_irqsave(&adev->didt_idx_lock, flags);
202 WREG32(address, (reg));
203 r = RREG32(data);
204 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
205 return r;
206}
207
208static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
209{
210 unsigned long flags, address, data;
211
212 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
213 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
214
215 spin_lock_irqsave(&adev->didt_idx_lock, flags);
216 WREG32(address, (reg));
217 WREG32(data, (v));
218 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
219}
220
221static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
222{
223 return adev->nbio.funcs->get_memsize(adev);
224}
225
226static u32 soc21_get_xclk(struct amdgpu_device *adev)
227{
228 return adev->clock.spll.reference_freq;
229}
230
231
232void soc21_grbm_select(struct amdgpu_device *adev,
233 u32 me, u32 pipe, u32 queue, u32 vmid)
234{
235 u32 grbm_gfx_cntl = 0;
236 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
237 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
238 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
239 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
240
bbb860d4 241 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
71199aa4
SY		 242}
243
71199aa4
SY		 244static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
245{
246 /* todo */
247 return false;
248}
249
250static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
251 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
252 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
253 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
254 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
255 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
256 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
257 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
258 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
259 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
260 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
261 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
262 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
263 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
264 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
265 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
266 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
267 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
268 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
269 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
270};
271
272static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
273 u32 sh_num, u32 reg_offset)
274{
275 uint32_t val;
276
277 mutex_lock(&adev->grbm_idx_mutex);
278 if (se_num != 0xffffffff || sh_num != 0xffffffff)
d51ac6d0 279 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
71199aa4
SY		 280
281 val = RREG32(reg_offset);
282
283 if (se_num != 0xffffffff || sh_num != 0xffffffff)
d51ac6d0 284 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
71199aa4
SY		 285 mutex_unlock(&adev->grbm_idx_mutex);
286 return val;
287}
288
289static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
290 bool indexed, u32 se_num,
291 u32 sh_num, u32 reg_offset)
292{
293 if (indexed) {
294 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
295 } else {
296 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
297 return adev->gfx.config.gb_addr_config;
298 return RREG32(reg_offset);
299 }
300}
301
302static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
303 u32 sh_num, u32 reg_offset, u32 *value)
304{
305 uint32_t i;
306 struct soc15_allowed_register_entry *en;
307
308 *value = 0;
309 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
310 en = &soc21_allowed_read_registers[i];
ba137e64
AD		 311 if (!adev->reg_offset[en->hwip][en->inst])
312 continue;
313 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
314 + en->reg_offset))
71199aa4
SY		 315 continue;
316
317 *value = soc21_get_register_value(adev,
318 soc21_allowed_read_registers[i].grbm_indexed,
319 se_num, sh_num, reg_offset);
320 return 0;
321 }
322 return -EINVAL;
323}
324
325#if 0
326static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
327{
328 u32 i;
329 int ret = 0;
330
331 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
332
333 /* disable BM */
334 pci_clear_master(adev->pdev);
335
336 amdgpu_device_cache_pci_state(adev->pdev);
337
338 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
339 dev_info(adev->dev, "GPU smu mode1 reset\n");
340 ret = amdgpu_dpm_mode1_reset(adev);
341 } else {
342 dev_info(adev->dev, "GPU psp mode1 reset\n");
343 ret = psp_gpu_reset(adev);
344 }
345
346 if (ret)
347 dev_err(adev->dev, "GPU mode1 reset failed\n");
348 amdgpu_device_load_pci_state(adev->pdev);
349
350 /* wait for asic to come out of reset */
351 for (i = 0; i < adev->usec_timeout; i++) {
352 u32 memsize = adev->nbio.funcs->get_memsize(adev);
353
354 if (memsize != 0xffffffff)
355 break;
356 udelay(1);
357 }
358
359 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
360
361 return ret;
362}
363#endif
364
365static enum amd_reset_method
366soc21_asic_reset_method(struct amdgpu_device *adev)
367{
368 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
ea64228d 369 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
71199aa4
SY		 370 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
371 return amdgpu_reset_method;
372
373 if (amdgpu_reset_method != -1)
374 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
375 amdgpu_reset_method);
376
4e8303cf 377 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
71199aa4 378 case IP_VERSION(13, 0, 0):
a53bc321 379 case IP_VERSION(13, 0, 7):
60cfad32 380 case IP_VERSION(13, 0, 10):
71199aa4 381 return AMD_RESET_METHOD_MODE1;
ea64228d 382 case IP_VERSION(13, 0, 4):
18ad1885 383 case IP_VERSION(13, 0, 11):
ea64228d 384 return AMD_RESET_METHOD_MODE2;
71199aa4
SY		 385 default:
386 if (amdgpu_dpm_is_baco_supported(adev))
387 return AMD_RESET_METHOD_BACO;
388 else
389 return AMD_RESET_METHOD_MODE1;
390 }
391}
392
393static int soc21_asic_reset(struct amdgpu_device *adev)
394{
395 int ret = 0;
396
397 switch (soc21_asic_reset_method(adev)) {
398 case AMD_RESET_METHOD_PCI:
399 dev_info(adev->dev, "PCI reset\n");
400 ret = amdgpu_device_pci_reset(adev);
401 break;
402 case AMD_RESET_METHOD_BACO:
403 dev_info(adev->dev, "BACO reset\n");
404 ret = amdgpu_dpm_baco_reset(adev);
405 break;
ea64228d
AD		 406 case AMD_RESET_METHOD_MODE2:
407 dev_info(adev->dev, "MODE2 reset\n");
408 ret = amdgpu_dpm_mode2_reset(adev);
409 break;
71199aa4
SY		 410 default:
411 dev_info(adev->dev, "MODE1 reset\n");
412 ret = amdgpu_device_mode1_reset(adev);
413 break;
414 }
415
416 return ret;
417}
418
419static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
420{
421 /* todo */
422 return 0;
423}
424
425static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
426{
427 /* todo */
428 return 0;
429}
430
71199aa4
SY		 431static void soc21_program_aspm(struct amdgpu_device *adev)
432{
62f8f5c3 433 if (!amdgpu_device_should_use_aspm(adev))
71199aa4
SY		 434 return;
435
62f8f5c3
EQ		 436 if (!(adev->flags & AMD_IS_APU) &&
437 (adev->nbio.funcs->program_aspm))
438 adev->nbio.funcs->program_aspm(adev);
71199aa4
SY		 439}
440
06d82d87 441const struct amdgpu_ip_block_version soc21_common_ip_block = {
71199aa4
SY		 442 .type = AMD_IP_BLOCK_TYPE_COMMON,
443 .major = 1,
444 .minor = 0,
445 .rev = 0,
446 .funcs = &soc21_common_ip_funcs,
447};
448
71199aa4
SY		 449static bool soc21_need_full_reset(struct amdgpu_device *adev)
450{
4e8303cf 451 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
c0ff84cb 452 case IP_VERSION(11, 0, 0):
34dfca89 453 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
c0ff84cb 454 case IP_VERSION(11, 0, 2):
2e26bf1e 455 case IP_VERSION(11, 0, 3):
c0ff84cb
LG		 456 return false;
457 default:
458 return true;
459 }
71199aa4
SY		 460}
461
462static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
463{
464 u32 sol_reg;
465
466 if (adev->flags & AMD_IS_APU)
467 return false;
468
469 /* Check sOS sign of life register to confirm sys driver and sOS
470 * are already been loaded.
471 */
472 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
473 if (sol_reg)
474 return true;
475
476 return false;
477}
478
71199aa4
SY		 479static void soc21_init_doorbell_index(struct amdgpu_device *adev)
480{
481 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
482 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
483 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
484 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
485 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
486 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
487 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
488 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
489 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
490 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
491 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
492 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
493 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
fd0ed91a
JX		 494 adev->doorbell_index.gfx_userqueue_start =
495 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
496 adev->doorbell_index.gfx_userqueue_end =
497 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
b608e785
JX		 498 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
499 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
71199aa4
SY		 500 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
501 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
502 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
503 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
504 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
505 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
506 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
2f3916be 507 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE;
71199aa4
SY		 508 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
509 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
510
511 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
512 adev->doorbell_index.sdma_doorbell_range = 20;
513}
514
515static void soc21_pre_asic_init(struct amdgpu_device *adev)
516{
517}
518
72010239
LG		 519static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
520 bool enter)
521{
522 if (enter)
86b20703 523 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
72010239 524 else
86b20703 525 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
72010239
LG		 526
527 if (adev->gfx.funcs->update_perfmon_mgcg)
528 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
529
530 return 0;
531}
532
06d82d87 533static const struct amdgpu_asic_funcs soc21_asic_funcs = {
71199aa4
SY		 534 .read_disabled_bios = &soc21_read_disabled_bios,
535 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
536 .read_register = &soc21_read_register,
537 .reset = &soc21_asic_reset,
538 .reset_method = &soc21_asic_reset_method,
71199aa4
SY		 539 .get_xclk = &soc21_get_xclk,
540 .set_uvd_clocks = &soc21_set_uvd_clocks,
541 .set_vce_clocks = &soc21_set_vce_clocks,
542 .get_config_memsize = &soc21_get_config_memsize,
543 .init_doorbell_index = &soc21_init_doorbell_index,
544 .need_full_reset = &soc21_need_full_reset,
545 .need_reset_on_init = &soc21_need_reset_on_init,
36f3f375 546 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
71199aa4
SY		 547 .supports_baco = &amdgpu_dpm_is_baco_supported,
548 .pre_asic_init = &soc21_pre_asic_init,
9ac0edaa 549 .query_video_codecs = &soc21_query_video_codecs,
72010239 550 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
71199aa4
SY		 551};
552
553static int soc21_common_early_init(void *handle)
554{
555#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
556 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
557
558 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
559 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
560 adev->smc_rreg = NULL;
561 adev->smc_wreg = NULL;
65ba96e9
HZ		 562 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
563 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
564 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
565 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
bafd6cbe
XD		 566 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
567 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
71199aa4
SY		 568
569 /* TODO: will add them during VCN v2 implementation */
570 adev->uvd_ctx_rreg = NULL;
571 adev->uvd_ctx_wreg = NULL;
572
573 adev->didt_rreg = &soc21_didt_rreg;
574 adev->didt_wreg = &soc21_didt_wreg;
575
576 adev->asic_funcs = &soc21_asic_funcs;
577
dabc114e 578 adev->rev_id = amdgpu_device_get_rev_id(adev);
71199aa4 579 adev->external_rev_id = 0xff;
4e8303cf 580 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
71199aa4 581 case IP_VERSION(11, 0, 0):
390db4b8 582 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
b21348a2 583 AMD_CG_SUPPORT_GFX_CGLS |
1b586595 584#if 0
915b5ce7
EQ		 585 AMD_CG_SUPPORT_GFX_3D_CGCG |
586 AMD_CG_SUPPORT_GFX_3D_CGLS |
1b586595 587#endif
915b5ce7 588 AMD_CG_SUPPORT_GFX_MGCG |
8b719b96 589 AMD_CG_SUPPORT_REPEATER_FGCG |
915b5ce7
EQ		 590 AMD_CG_SUPPORT_GFX_FGCG |
591 AMD_CG_SUPPORT_GFX_PERF_CLK |
7c507d35 592 AMD_CG_SUPPORT_VCN_MGCG |
c649ed05
EQ		 593 AMD_CG_SUPPORT_JPEG_MGCG |
594 AMD_CG_SUPPORT_ATHUB_MGCG |
7ccf6eb0
EQ		 595 AMD_CG_SUPPORT_ATHUB_LS |
596 AMD_CG_SUPPORT_MC_MGCG |
20139069 597 AMD_CG_SUPPORT_MC_LS |
d386f645
EQ		 598 AMD_CG_SUPPORT_IH_CG |
599 AMD_CG_SUPPORT_HDP_SD;
8b719b96 600 adev->pg_flags = AMD_PG_SUPPORT_VCN |
04270390 601 AMD_PG_SUPPORT_VCN_DPG |
7c507d35 602 AMD_PG_SUPPORT_JPEG |
8b719b96 603 AMD_PG_SUPPORT_ATHUB |
a6dec868 604 AMD_PG_SUPPORT_MMHUB;
71199aa4
SY		 605 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
606 break;
92fd2153 607 case IP_VERSION(11, 0, 2):
71dae221 608 adev->cg_flags =
9503a944
LG		 609 AMD_CG_SUPPORT_GFX_CGCG |
610 AMD_CG_SUPPORT_GFX_CGLS |
49401d3a 611 AMD_CG_SUPPORT_REPEATER_FGCG |
7ece9314 612 AMD_CG_SUPPORT_VCN_MGCG |
49401d3a
KF		 613 AMD_CG_SUPPORT_JPEG_MGCG |
614 AMD_CG_SUPPORT_ATHUB_MGCG |
b4ddb27d
KF		 615 AMD_CG_SUPPORT_ATHUB_LS |
616 AMD_CG_SUPPORT_IH_CG |
617 AMD_CG_SUPPORT_HDP_SD;
ebac66a3 618 adev->pg_flags =
143a34a0 619 AMD_PG_SUPPORT_VCN |
ec9db74e 620 AMD_PG_SUPPORT_VCN_DPG |
27e3911c
KF		 621 AMD_PG_SUPPORT_JPEG |
622 AMD_PG_SUPPORT_ATHUB |
623 AMD_PG_SUPPORT_MMHUB;
92fd2153
FC		 624 adev->external_rev_id = adev->rev_id + 0x10;
625 break;
11417a92 626 case IP_VERSION(11, 0, 1):
47231d5e 627 adev->cg_flags =
8df436d5
TH		 628 AMD_CG_SUPPORT_GFX_CGCG |
629 AMD_CG_SUPPORT_GFX_CGLS |
630 AMD_CG_SUPPORT_GFX_MGCG |
631 AMD_CG_SUPPORT_GFX_FGCG |
632 AMD_CG_SUPPORT_REPEATER_FGCG |
633 AMD_CG_SUPPORT_GFX_PERF_CLK |
adcd15dc
TH		 634 AMD_CG_SUPPORT_MC_MGCG |
635 AMD_CG_SUPPORT_MC_LS |
7e4a77de
TH		 636 AMD_CG_SUPPORT_HDP_MGCG |
637 AMD_CG_SUPPORT_HDP_LS |
8e78c7c4
TH		 638 AMD_CG_SUPPORT_ATHUB_MGCG |
639 AMD_CG_SUPPORT_ATHUB_LS |
fa0bbd3b 640 AMD_CG_SUPPORT_IH_CG |
9407feac
TH		 641 AMD_CG_SUPPORT_BIF_MGCG |
642 AMD_CG_SUPPORT_BIF_LS |
47231d5e
SJ		 643 AMD_CG_SUPPORT_VCN_MGCG |
644 AMD_CG_SUPPORT_JPEG_MGCG;
645 adev->pg_flags =
dc0a096b 646 AMD_PG_SUPPORT_GFX_PG |
e626d9b9 647 AMD_PG_SUPPORT_VCN |
0b37f474 648 AMD_PG_SUPPORT_VCN_DPG |
47231d5e 649 AMD_PG_SUPPORT_JPEG;
11417a92
HR		 650 adev->external_rev_id = adev->rev_id + 0x1;
651 break;
6b46251c 652 case IP_VERSION(11, 0, 3):
0f05a2e5 653 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
4ecdb30e
KF		 654 AMD_CG_SUPPORT_JPEG_MGCG |
655 AMD_CG_SUPPORT_GFX_CGCG |
656 AMD_CG_SUPPORT_GFX_CGLS |
657 AMD_CG_SUPPORT_REPEATER_FGCG |
20e6220b 658 AMD_CG_SUPPORT_GFX_MGCG |
ad1cebb6
KF		 659 AMD_CG_SUPPORT_HDP_SD |
660 AMD_CG_SUPPORT_ATHUB_MGCG |
661 AMD_CG_SUPPORT_ATHUB_LS;
0f05a2e5
SJ		 662 adev->pg_flags = AMD_PG_SUPPORT_VCN |
663 AMD_PG_SUPPORT_VCN_DPG |
664 AMD_PG_SUPPORT_JPEG;
6b46251c
HZ		 665 adev->external_rev_id = adev->rev_id + 0x20;
666 break;
311d5236 667 case IP_VERSION(11, 0, 4):
f2b91e5a
TH		 668 adev->cg_flags =
669 AMD_CG_SUPPORT_GFX_CGCG |
670 AMD_CG_SUPPORT_GFX_CGLS |
671 AMD_CG_SUPPORT_GFX_MGCG |
672 AMD_CG_SUPPORT_GFX_FGCG |
673 AMD_CG_SUPPORT_REPEATER_FGCG |
674 AMD_CG_SUPPORT_GFX_PERF_CLK |
675 AMD_CG_SUPPORT_MC_MGCG |
676 AMD_CG_SUPPORT_MC_LS |
677 AMD_CG_SUPPORT_HDP_MGCG |
678 AMD_CG_SUPPORT_HDP_LS |
679 AMD_CG_SUPPORT_ATHUB_MGCG |
680 AMD_CG_SUPPORT_ATHUB_LS |
681 AMD_CG_SUPPORT_IH_CG |
682 AMD_CG_SUPPORT_BIF_MGCG |
683 AMD_CG_SUPPORT_BIF_LS |
684 AMD_CG_SUPPORT_VCN_MGCG |
2a0fe2ca
SJ		 685 AMD_CG_SUPPORT_JPEG_MGCG;
686 adev->pg_flags = AMD_PG_SUPPORT_VCN |
9c705b96 687 AMD_PG_SUPPORT_VCN_DPG |
2a0fe2ca
SJ		 688 AMD_PG_SUPPORT_GFX_PG |
689 AMD_PG_SUPPORT_JPEG;
6d99f3f4 690 adev->external_rev_id = adev->rev_id + 0x80;
311d5236
YZ		 691 break;
692
0d1db799
PL		 693
694 case IP_VERSION(11, 5, 0):
cc308acc
SJ		 695 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
696 AMD_CG_SUPPORT_JPEG_MGCG;
697 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
6be6e74b
SJ		 698 AMD_PG_SUPPORT_VCN |
699 AMD_PG_SUPPORT_JPEG |
cc308acc 700 AMD_PG_SUPPORT_GFX_PG;
0d1db799
PL		 701 adev->external_rev_id = adev->rev_id + 0x1;
702 break;
71199aa4
SY		 703 default:
704 /* FIXME: not supported yet */
705 return -EINVAL;
706 }
707
39dd895d 708 if (amdgpu_sriov_vf(adev)) {
0cfce240 709 amdgpu_virt_init_setting(adev);
39dd895d
YW		 710 xgpu_nv_mailbox_set_irq_funcs(adev);
711 }
0cfce240 712
71199aa4
SY		 713 return 0;
714}
715
716static int soc21_common_late_init(void *handle)
717{
39dd895d
YW		 718 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
719
dcaf5000 720 if (amdgpu_sriov_vf(adev)) {
39dd895d 721 xgpu_nv_mailbox_get_irq(adev);
dcaf5000
JJ		 722 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
723 !amdgpu_sriov_is_av1_support(adev)) {
724 amdgpu_virt_update_sriov_video_codec(adev,
725 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
726 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
727 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
728 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
729 } else {
730 amdgpu_virt_update_sriov_video_codec(adev,
731 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
732 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
733 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
734 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
735 }
9af357bc
HZ		 736 } else {
737 if (adev->nbio.ras &&
738 adev->nbio.ras_err_event_athub_irq.funcs)
739 /* don't need to fail gpu late init
740 * if enabling athub_err_event interrupt failed
741 * nbio v4_3 only support fatal error hanlding
742 * just enable the interrupt directly */
743 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
dcaf5000 744 }
39dd895d 745
1c312e81
SX		 746 /* Enable selfring doorbell aperture late because doorbell BAR
747 * aperture will change if resize BAR successfully in gmc sw_init.
748 */
749 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
750
71199aa4
SY		 751 return 0;
752}
753
754static int soc21_common_sw_init(void *handle)
755{
39dd895d
YW		 756 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
757
758 if (amdgpu_sriov_vf(adev))
759 xgpu_nv_mailbox_add_irq_id(adev);
760
71199aa4
SY		 761 return 0;
762}
763
764static int soc21_common_sw_fini(void *handle)
765{
766 return 0;
767}
768
769static int soc21_common_hw_init(void *handle)
770{
771 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
772
71199aa4
SY		 773 /* enable aspm */
774 soc21_program_aspm(adev);
775 /* setup nbio registers */
776 adev->nbio.funcs->init_registers(adev);
777 /* remap HDP registers to a hole in mmio space,
778 * for the purpose of expose those registers
779 * to process space
780 */
8a6e26e7 781 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
71199aa4
SY		 782 adev->nbio.funcs->remap_hdp_registers(adev);
783 /* enable the doorbell aperture */
1c312e81 784 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
71199aa4
SY		 785
786 return 0;
787}
788
789static int soc21_common_hw_fini(void *handle)
790{
791 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
792
1c312e81
SX		 793 /* Disable the doorbell aperture and selfring doorbell aperture
794 * separately in hw_fini because soc21_enable_doorbell_aperture
795 * has been removed and there is no need to delay disabling
796 * selfring doorbell.
797 */
798 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
799 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
71199aa4 800
9af357bc 801 if (amdgpu_sriov_vf(adev)) {
39dd895d 802 xgpu_nv_mailbox_put_irq(adev);
9af357bc
HZ		 803 } else {
804 if (adev->nbio.ras &&
805 adev->nbio.ras_err_event_athub_irq.funcs)
806 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
807 }
39dd895d 808
71199aa4
SY		 809 return 0;
810}
811
812static int soc21_common_suspend(void *handle)
813{
814 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
815
816 return soc21_common_hw_fini(adev);
817}
818
819static int soc21_common_resume(void *handle)
820{
821 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
822
823 return soc21_common_hw_init(adev);
824}
825
826static bool soc21_common_is_idle(void *handle)
827{
828 return true;
829}
830
831static int soc21_common_wait_for_idle(void *handle)
832{
833 return 0;
834}
835
836static int soc21_common_soft_reset(void *handle)
837{
838 return 0;
839}
840
841static int soc21_common_set_clockgating_state(void *handle,
842 enum amd_clockgating_state state)
843{
844 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
845
4e8303cf 846 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
71199aa4 847 case IP_VERSION(4, 3, 0):
b4ddb27d 848 case IP_VERSION(4, 3, 1):
9407feac 849 case IP_VERSION(7, 7, 0):
71199aa4
SY		 850 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
851 state == AMD_CG_STATE_GATE);
852 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
853 state == AMD_CG_STATE_GATE);
854 adev->hdp.funcs->update_clock_gating(adev,
855 state == AMD_CG_STATE_GATE);
856 break;
857 default:
858 break;
859 }
860 return 0;
861}
862
863static int soc21_common_set_powergating_state(void *handle,
864 enum amd_powergating_state state)
865{
41967850
LG		 866 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
867
4e8303cf 868 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
41967850 869 case IP_VERSION(6, 0, 0):
362c3c70 870 case IP_VERSION(6, 0, 2):
41967850
LG		 871 adev->lsdma.funcs->update_memory_power_gating(adev,
872 state == AMD_PG_STATE_GATE);
873 break;
874 default:
875 break;
876 }
877
71199aa4
SY		 878 return 0;
879}
880
881static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
882{
883 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
884
885 adev->nbio.funcs->get_clockgating_state(adev, flags);
886
887 adev->hdp.funcs->get_clock_gating_state(adev, flags);
888
889 return;
890}
891
892static const struct amd_ip_funcs soc21_common_ip_funcs = {
893 .name = "soc21_common",
894 .early_init = soc21_common_early_init,
895 .late_init = soc21_common_late_init,
896 .sw_init = soc21_common_sw_init,
897 .sw_fini = soc21_common_sw_fini,
898 .hw_init = soc21_common_hw_init,
899 .hw_fini = soc21_common_hw_fini,
900 .suspend = soc21_common_suspend,
901 .resume = soc21_common_resume,
902 .is_idle = soc21_common_is_idle,
903 .wait_for_idle = soc21_common_wait_for_idle,
904 .soft_reset = soc21_common_soft_reset,
905 .set_clockgating_state = soc21_common_set_clockgating_state,
906 .set_powergating_state = soc21_common_set_powergating_state,
907 .get_clockgating_state = soc21_common_get_clockgating_state,
908};
Linux 6.x block layer and io_uring tree(s)