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71199aa4 SY |
1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/pci.h> | |
27 | ||
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_atombios.h" | |
30 | #include "amdgpu_ih.h" | |
31 | #include "amdgpu_uvd.h" | |
32 | #include "amdgpu_vce.h" | |
33 | #include "amdgpu_ucode.h" | |
34 | #include "amdgpu_psp.h" | |
35 | #include "amdgpu_smu.h" | |
36 | #include "atom.h" | |
37 | #include "amd_pcie.h" | |
38 | ||
39 | #include "gc/gc_11_0_0_offset.h" | |
40 | #include "gc/gc_11_0_0_sh_mask.h" | |
41 | #include "mp/mp_13_0_0_offset.h" | |
42 | ||
43 | #include "soc15.h" | |
44 | #include "soc15_common.h" | |
45 | ||
46 | static const struct amd_ip_funcs soc21_common_ip_funcs; | |
47 | ||
9ac0edaa JZ |
48 | /* SOC21 */ |
49 | static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] = | |
50 | { | |
51 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, | |
52 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, | |
53 | }; | |
54 | ||
55 | static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode = | |
56 | { | |
57 | .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array), | |
58 | .codec_array = vcn_4_0_0_video_codecs_encode_array, | |
59 | }; | |
60 | ||
61 | static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array[] = | |
62 | { | |
63 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, | |
64 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, | |
65 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, | |
66 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, | |
67 | {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, | |
68 | }; | |
69 | ||
70 | static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode = | |
71 | { | |
72 | .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array), | |
73 | .codec_array = vcn_4_0_0_video_codecs_decode_array, | |
74 | }; | |
75 | ||
76 | static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, | |
77 | const struct amdgpu_video_codecs **codecs) | |
78 | { | |
79 | switch (adev->ip_versions[UVD_HWIP][0]) { | |
80 | ||
81 | case IP_VERSION(4, 0, 0): | |
82 | if (encode) | |
83 | *codecs = &vcn_4_0_0_video_codecs_encode; | |
84 | else | |
85 | *codecs = &vcn_4_0_0_video_codecs_decode; | |
86 | return 0; | |
87 | default: | |
88 | return -EINVAL; | |
89 | } | |
90 | } | |
71199aa4 SY |
91 | /* |
92 | * Indirect registers accessor | |
93 | */ | |
94 | static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg) | |
95 | { | |
96 | unsigned long address, data; | |
97 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
98 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
99 | ||
100 | return amdgpu_device_indirect_rreg(adev, address, data, reg); | |
101 | } | |
102 | ||
103 | static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
104 | { | |
105 | unsigned long address, data; | |
106 | ||
107 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
108 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
109 | ||
110 | amdgpu_device_indirect_wreg(adev, address, data, reg, v); | |
111 | } | |
112 | ||
113 | static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg) | |
114 | { | |
115 | unsigned long address, data; | |
116 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
117 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
118 | ||
119 | return amdgpu_device_indirect_rreg64(adev, address, data, reg); | |
120 | } | |
121 | ||
122 | static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) | |
123 | { | |
124 | unsigned long address, data; | |
125 | ||
126 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
127 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
128 | ||
129 | amdgpu_device_indirect_wreg64(adev, address, data, reg, v); | |
130 | } | |
131 | ||
132 | static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) | |
133 | { | |
134 | unsigned long flags, address, data; | |
135 | u32 r; | |
136 | ||
137 | address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); | |
138 | data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); | |
139 | ||
140 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
141 | WREG32(address, (reg)); | |
142 | r = RREG32(data); | |
143 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
144 | return r; | |
145 | } | |
146 | ||
147 | static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
148 | { | |
149 | unsigned long flags, address, data; | |
150 | ||
151 | address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); | |
152 | data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); | |
153 | ||
154 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
155 | WREG32(address, (reg)); | |
156 | WREG32(data, (v)); | |
157 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
158 | } | |
159 | ||
160 | static u32 soc21_get_config_memsize(struct amdgpu_device *adev) | |
161 | { | |
162 | return adev->nbio.funcs->get_memsize(adev); | |
163 | } | |
164 | ||
165 | static u32 soc21_get_xclk(struct amdgpu_device *adev) | |
166 | { | |
167 | return adev->clock.spll.reference_freq; | |
168 | } | |
169 | ||
170 | ||
171 | void soc21_grbm_select(struct amdgpu_device *adev, | |
172 | u32 me, u32 pipe, u32 queue, u32 vmid) | |
173 | { | |
174 | u32 grbm_gfx_cntl = 0; | |
175 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); | |
176 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); | |
177 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); | |
178 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); | |
179 | ||
180 | WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL), grbm_gfx_cntl); | |
181 | } | |
182 | ||
183 | static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) | |
184 | { | |
185 | /* todo */ | |
186 | } | |
187 | ||
188 | static bool soc21_read_disabled_bios(struct amdgpu_device *adev) | |
189 | { | |
190 | /* todo */ | |
191 | return false; | |
192 | } | |
193 | ||
194 | static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { | |
195 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, | |
196 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, | |
197 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, | |
198 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, | |
199 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, | |
200 | { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, | |
201 | { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, | |
202 | { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, | |
203 | { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, | |
204 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, | |
205 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, | |
206 | { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, | |
207 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, | |
208 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, | |
209 | { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, | |
210 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, | |
211 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, | |
212 | { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, | |
213 | { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, | |
214 | }; | |
215 | ||
216 | static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, | |
217 | u32 sh_num, u32 reg_offset) | |
218 | { | |
219 | uint32_t val; | |
220 | ||
221 | mutex_lock(&adev->grbm_idx_mutex); | |
222 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
223 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); | |
224 | ||
225 | val = RREG32(reg_offset); | |
226 | ||
227 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
228 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
229 | mutex_unlock(&adev->grbm_idx_mutex); | |
230 | return val; | |
231 | } | |
232 | ||
233 | static uint32_t soc21_get_register_value(struct amdgpu_device *adev, | |
234 | bool indexed, u32 se_num, | |
235 | u32 sh_num, u32 reg_offset) | |
236 | { | |
237 | if (indexed) { | |
238 | return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); | |
239 | } else { | |
240 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) | |
241 | return adev->gfx.config.gb_addr_config; | |
242 | return RREG32(reg_offset); | |
243 | } | |
244 | } | |
245 | ||
246 | static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, | |
247 | u32 sh_num, u32 reg_offset, u32 *value) | |
248 | { | |
249 | uint32_t i; | |
250 | struct soc15_allowed_register_entry *en; | |
251 | ||
252 | *value = 0; | |
253 | for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { | |
254 | en = &soc21_allowed_read_registers[i]; | |
bf1781e1 AD |
255 | if (adev->reg_offset[en->hwip][en->inst] && |
256 | reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] | |
257 | + en->reg_offset)) | |
71199aa4 SY |
258 | continue; |
259 | ||
260 | *value = soc21_get_register_value(adev, | |
261 | soc21_allowed_read_registers[i].grbm_indexed, | |
262 | se_num, sh_num, reg_offset); | |
263 | return 0; | |
264 | } | |
265 | return -EINVAL; | |
266 | } | |
267 | ||
268 | #if 0 | |
269 | static int soc21_asic_mode1_reset(struct amdgpu_device *adev) | |
270 | { | |
271 | u32 i; | |
272 | int ret = 0; | |
273 | ||
274 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
275 | ||
276 | /* disable BM */ | |
277 | pci_clear_master(adev->pdev); | |
278 | ||
279 | amdgpu_device_cache_pci_state(adev->pdev); | |
280 | ||
281 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
282 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
283 | ret = amdgpu_dpm_mode1_reset(adev); | |
284 | } else { | |
285 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
286 | ret = psp_gpu_reset(adev); | |
287 | } | |
288 | ||
289 | if (ret) | |
290 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
291 | amdgpu_device_load_pci_state(adev->pdev); | |
292 | ||
293 | /* wait for asic to come out of reset */ | |
294 | for (i = 0; i < adev->usec_timeout; i++) { | |
295 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
296 | ||
297 | if (memsize != 0xffffffff) | |
298 | break; | |
299 | udelay(1); | |
300 | } | |
301 | ||
302 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
303 | ||
304 | return ret; | |
305 | } | |
306 | #endif | |
307 | ||
308 | static enum amd_reset_method | |
309 | soc21_asic_reset_method(struct amdgpu_device *adev) | |
310 | { | |
311 | if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || | |
312 | amdgpu_reset_method == AMD_RESET_METHOD_BACO) | |
313 | return amdgpu_reset_method; | |
314 | ||
315 | if (amdgpu_reset_method != -1) | |
316 | dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", | |
317 | amdgpu_reset_method); | |
318 | ||
319 | switch (adev->ip_versions[MP1_HWIP][0]) { | |
320 | case IP_VERSION(13, 0, 0): | |
321 | return AMD_RESET_METHOD_MODE1; | |
322 | default: | |
323 | if (amdgpu_dpm_is_baco_supported(adev)) | |
324 | return AMD_RESET_METHOD_BACO; | |
325 | else | |
326 | return AMD_RESET_METHOD_MODE1; | |
327 | } | |
328 | } | |
329 | ||
330 | static int soc21_asic_reset(struct amdgpu_device *adev) | |
331 | { | |
332 | int ret = 0; | |
333 | ||
334 | switch (soc21_asic_reset_method(adev)) { | |
335 | case AMD_RESET_METHOD_PCI: | |
336 | dev_info(adev->dev, "PCI reset\n"); | |
337 | ret = amdgpu_device_pci_reset(adev); | |
338 | break; | |
339 | case AMD_RESET_METHOD_BACO: | |
340 | dev_info(adev->dev, "BACO reset\n"); | |
341 | ret = amdgpu_dpm_baco_reset(adev); | |
342 | break; | |
343 | default: | |
344 | dev_info(adev->dev, "MODE1 reset\n"); | |
345 | ret = amdgpu_device_mode1_reset(adev); | |
346 | break; | |
347 | } | |
348 | ||
349 | return ret; | |
350 | } | |
351 | ||
352 | static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) | |
353 | { | |
354 | /* todo */ | |
355 | return 0; | |
356 | } | |
357 | ||
358 | static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) | |
359 | { | |
360 | /* todo */ | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static void soc21_pcie_gen3_enable(struct amdgpu_device *adev) | |
365 | { | |
366 | if (pci_is_root_bus(adev->pdev->bus)) | |
367 | return; | |
368 | ||
369 | if (amdgpu_pcie_gen2 == 0) | |
370 | return; | |
371 | ||
372 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
373 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) | |
374 | return; | |
375 | ||
376 | /* todo */ | |
377 | } | |
378 | ||
379 | static void soc21_program_aspm(struct amdgpu_device *adev) | |
380 | { | |
381 | ||
382 | if (amdgpu_aspm == 0) | |
383 | return; | |
384 | ||
385 | /* todo */ | |
386 | } | |
387 | ||
388 | static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, | |
389 | bool enable) | |
390 | { | |
391 | adev->nbio.funcs->enable_doorbell_aperture(adev, enable); | |
392 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); | |
393 | } | |
394 | ||
395 | const struct amdgpu_ip_block_version soc21_common_ip_block = | |
396 | { | |
397 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
398 | .major = 1, | |
399 | .minor = 0, | |
400 | .rev = 0, | |
401 | .funcs = &soc21_common_ip_funcs, | |
402 | }; | |
403 | ||
404 | static uint32_t soc21_get_rev_id(struct amdgpu_device *adev) | |
405 | { | |
406 | return adev->nbio.funcs->get_rev_id(adev); | |
407 | } | |
408 | ||
409 | static bool soc21_need_full_reset(struct amdgpu_device *adev) | |
410 | { | |
411 | return true; | |
412 | } | |
413 | ||
414 | static bool soc21_need_reset_on_init(struct amdgpu_device *adev) | |
415 | { | |
416 | u32 sol_reg; | |
417 | ||
418 | if (adev->flags & AMD_IS_APU) | |
419 | return false; | |
420 | ||
421 | /* Check sOS sign of life register to confirm sys driver and sOS | |
422 | * are already been loaded. | |
423 | */ | |
424 | sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); | |
425 | if (sol_reg) | |
426 | return true; | |
427 | ||
428 | return false; | |
429 | } | |
430 | ||
431 | static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev) | |
432 | { | |
433 | ||
434 | /* TODO | |
435 | * dummy implement for pcie_replay_count sysfs interface | |
436 | * */ | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | static void soc21_init_doorbell_index(struct amdgpu_device *adev) | |
442 | { | |
443 | adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; | |
444 | adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; | |
445 | adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; | |
446 | adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; | |
447 | adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; | |
448 | adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; | |
449 | adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; | |
450 | adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; | |
451 | adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; | |
452 | adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; | |
453 | adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; | |
454 | adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; | |
455 | adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; | |
fd0ed91a JX |
456 | adev->doorbell_index.gfx_userqueue_start = |
457 | AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; | |
458 | adev->doorbell_index.gfx_userqueue_end = | |
459 | AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; | |
b608e785 JX |
460 | adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; |
461 | adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; | |
71199aa4 SY |
462 | adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; |
463 | adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; | |
464 | adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; | |
465 | adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; | |
466 | adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; | |
467 | adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; | |
468 | adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; | |
469 | adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; | |
470 | adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; | |
471 | ||
472 | adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; | |
473 | adev->doorbell_index.sdma_doorbell_range = 20; | |
474 | } | |
475 | ||
476 | static void soc21_pre_asic_init(struct amdgpu_device *adev) | |
477 | { | |
478 | } | |
479 | ||
480 | static const struct amdgpu_asic_funcs soc21_asic_funcs = | |
481 | { | |
482 | .read_disabled_bios = &soc21_read_disabled_bios, | |
483 | .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, | |
484 | .read_register = &soc21_read_register, | |
485 | .reset = &soc21_asic_reset, | |
486 | .reset_method = &soc21_asic_reset_method, | |
487 | .set_vga_state = &soc21_vga_set_state, | |
488 | .get_xclk = &soc21_get_xclk, | |
489 | .set_uvd_clocks = &soc21_set_uvd_clocks, | |
490 | .set_vce_clocks = &soc21_set_vce_clocks, | |
491 | .get_config_memsize = &soc21_get_config_memsize, | |
492 | .init_doorbell_index = &soc21_init_doorbell_index, | |
493 | .need_full_reset = &soc21_need_full_reset, | |
494 | .need_reset_on_init = &soc21_need_reset_on_init, | |
495 | .get_pcie_replay_count = &soc21_get_pcie_replay_count, | |
496 | .supports_baco = &amdgpu_dpm_is_baco_supported, | |
497 | .pre_asic_init = &soc21_pre_asic_init, | |
9ac0edaa | 498 | .query_video_codecs = &soc21_query_video_codecs, |
71199aa4 SY |
499 | }; |
500 | ||
501 | static int soc21_common_early_init(void *handle) | |
502 | { | |
503 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) | |
504 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
505 | ||
506 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; | |
507 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; | |
508 | adev->smc_rreg = NULL; | |
509 | adev->smc_wreg = NULL; | |
510 | adev->pcie_rreg = &soc21_pcie_rreg; | |
511 | adev->pcie_wreg = &soc21_pcie_wreg; | |
512 | adev->pcie_rreg64 = &soc21_pcie_rreg64; | |
513 | adev->pcie_wreg64 = &soc21_pcie_wreg64; | |
bafd6cbe XD |
514 | adev->pciep_rreg = amdgpu_device_pcie_port_rreg; |
515 | adev->pciep_wreg = amdgpu_device_pcie_port_wreg; | |
71199aa4 SY |
516 | |
517 | /* TODO: will add them during VCN v2 implementation */ | |
518 | adev->uvd_ctx_rreg = NULL; | |
519 | adev->uvd_ctx_wreg = NULL; | |
520 | ||
521 | adev->didt_rreg = &soc21_didt_rreg; | |
522 | adev->didt_wreg = &soc21_didt_wreg; | |
523 | ||
524 | adev->asic_funcs = &soc21_asic_funcs; | |
525 | ||
526 | adev->rev_id = soc21_get_rev_id(adev); | |
527 | adev->external_rev_id = 0xff; | |
528 | switch (adev->ip_versions[GC_HWIP][0]) { | |
529 | case IP_VERSION(11, 0, 0): | |
390db4b8 | 530 | adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | |
b21348a2 | 531 | AMD_CG_SUPPORT_GFX_CGLS | |
915b5ce7 EQ |
532 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
533 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
534 | AMD_CG_SUPPORT_GFX_MGCG | | |
8b719b96 | 535 | AMD_CG_SUPPORT_REPEATER_FGCG | |
915b5ce7 EQ |
536 | AMD_CG_SUPPORT_GFX_FGCG | |
537 | AMD_CG_SUPPORT_GFX_PERF_CLK | | |
7c507d35 | 538 | AMD_CG_SUPPORT_VCN_MGCG | |
c649ed05 EQ |
539 | AMD_CG_SUPPORT_JPEG_MGCG | |
540 | AMD_CG_SUPPORT_ATHUB_MGCG | | |
7ccf6eb0 EQ |
541 | AMD_CG_SUPPORT_ATHUB_LS | |
542 | AMD_CG_SUPPORT_MC_MGCG | | |
20139069 | 543 | AMD_CG_SUPPORT_MC_LS | |
d386f645 EQ |
544 | AMD_CG_SUPPORT_IH_CG | |
545 | AMD_CG_SUPPORT_HDP_SD; | |
8b719b96 | 546 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
04270390 | 547 | AMD_PG_SUPPORT_VCN_DPG | |
7c507d35 | 548 | AMD_PG_SUPPORT_JPEG | |
8b719b96 | 549 | AMD_PG_SUPPORT_ATHUB | |
a6dec868 | 550 | AMD_PG_SUPPORT_MMHUB; |
71199aa4 SY |
551 | adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update |
552 | break; | |
92fd2153 | 553 | case IP_VERSION(11, 0, 2): |
71dae221 | 554 | adev->cg_flags = |
9503a944 LG |
555 | AMD_CG_SUPPORT_GFX_CGCG | |
556 | AMD_CG_SUPPORT_GFX_CGLS | | |
7ece9314 | 557 | AMD_CG_SUPPORT_VCN_MGCG | |
71dae221 | 558 | AMD_CG_SUPPORT_JPEG_MGCG; |
ebac66a3 | 559 | adev->pg_flags = |
143a34a0 | 560 | AMD_PG_SUPPORT_VCN | |
ec9db74e | 561 | AMD_PG_SUPPORT_VCN_DPG | |
27e3911c KF |
562 | AMD_PG_SUPPORT_JPEG | |
563 | AMD_PG_SUPPORT_ATHUB | | |
564 | AMD_PG_SUPPORT_MMHUB; | |
92fd2153 FC |
565 | adev->external_rev_id = adev->rev_id + 0x10; |
566 | break; | |
11417a92 HR |
567 | case IP_VERSION(11, 0, 1): |
568 | adev->cg_flags = 0; | |
569 | adev->pg_flags = 0; | |
570 | adev->external_rev_id = adev->rev_id + 0x1; | |
571 | break; | |
71199aa4 SY |
572 | default: |
573 | /* FIXME: not supported yet */ | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | static int soc21_common_late_init(void *handle) | |
581 | { | |
582 | return 0; | |
583 | } | |
584 | ||
585 | static int soc21_common_sw_init(void *handle) | |
586 | { | |
587 | return 0; | |
588 | } | |
589 | ||
590 | static int soc21_common_sw_fini(void *handle) | |
591 | { | |
592 | return 0; | |
593 | } | |
594 | ||
595 | static int soc21_common_hw_init(void *handle) | |
596 | { | |
597 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
598 | ||
599 | /* enable pcie gen2/3 link */ | |
600 | soc21_pcie_gen3_enable(adev); | |
601 | /* enable aspm */ | |
602 | soc21_program_aspm(adev); | |
603 | /* setup nbio registers */ | |
604 | adev->nbio.funcs->init_registers(adev); | |
605 | /* remap HDP registers to a hole in mmio space, | |
606 | * for the purpose of expose those registers | |
607 | * to process space | |
608 | */ | |
609 | if (adev->nbio.funcs->remap_hdp_registers) | |
610 | adev->nbio.funcs->remap_hdp_registers(adev); | |
611 | /* enable the doorbell aperture */ | |
612 | soc21_enable_doorbell_aperture(adev, true); | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | static int soc21_common_hw_fini(void *handle) | |
618 | { | |
619 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
620 | ||
621 | /* disable the doorbell aperture */ | |
622 | soc21_enable_doorbell_aperture(adev, false); | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | static int soc21_common_suspend(void *handle) | |
628 | { | |
629 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
630 | ||
631 | return soc21_common_hw_fini(adev); | |
632 | } | |
633 | ||
634 | static int soc21_common_resume(void *handle) | |
635 | { | |
636 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
637 | ||
638 | return soc21_common_hw_init(adev); | |
639 | } | |
640 | ||
641 | static bool soc21_common_is_idle(void *handle) | |
642 | { | |
643 | return true; | |
644 | } | |
645 | ||
646 | static int soc21_common_wait_for_idle(void *handle) | |
647 | { | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static int soc21_common_soft_reset(void *handle) | |
652 | { | |
653 | return 0; | |
654 | } | |
655 | ||
656 | static int soc21_common_set_clockgating_state(void *handle, | |
657 | enum amd_clockgating_state state) | |
658 | { | |
659 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
660 | ||
661 | switch (adev->ip_versions[NBIO_HWIP][0]) { | |
662 | case IP_VERSION(4, 3, 0): | |
663 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, | |
664 | state == AMD_CG_STATE_GATE); | |
665 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, | |
666 | state == AMD_CG_STATE_GATE); | |
667 | adev->hdp.funcs->update_clock_gating(adev, | |
668 | state == AMD_CG_STATE_GATE); | |
669 | break; | |
670 | default: | |
671 | break; | |
672 | } | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static int soc21_common_set_powergating_state(void *handle, | |
677 | enum amd_powergating_state state) | |
678 | { | |
41967850 LG |
679 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
680 | ||
681 | switch (adev->ip_versions[LSDMA_HWIP][0]) { | |
682 | case IP_VERSION(6, 0, 0): | |
362c3c70 | 683 | case IP_VERSION(6, 0, 2): |
41967850 LG |
684 | adev->lsdma.funcs->update_memory_power_gating(adev, |
685 | state == AMD_PG_STATE_GATE); | |
686 | break; | |
687 | default: | |
688 | break; | |
689 | } | |
690 | ||
71199aa4 SY |
691 | return 0; |
692 | } | |
693 | ||
694 | static void soc21_common_get_clockgating_state(void *handle, u64 *flags) | |
695 | { | |
696 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
697 | ||
698 | adev->nbio.funcs->get_clockgating_state(adev, flags); | |
699 | ||
700 | adev->hdp.funcs->get_clock_gating_state(adev, flags); | |
701 | ||
702 | return; | |
703 | } | |
704 | ||
705 | static const struct amd_ip_funcs soc21_common_ip_funcs = { | |
706 | .name = "soc21_common", | |
707 | .early_init = soc21_common_early_init, | |
708 | .late_init = soc21_common_late_init, | |
709 | .sw_init = soc21_common_sw_init, | |
710 | .sw_fini = soc21_common_sw_fini, | |
711 | .hw_init = soc21_common_hw_init, | |
712 | .hw_fini = soc21_common_hw_fini, | |
713 | .suspend = soc21_common_suspend, | |
714 | .resume = soc21_common_resume, | |
715 | .is_idle = soc21_common_is_idle, | |
716 | .wait_for_idle = soc21_common_wait_for_idle, | |
717 | .soft_reset = soc21_common_soft_reset, | |
718 | .set_clockgating_state = soc21_common_set_clockgating_state, | |
719 | .set_powergating_state = soc21_common_set_powergating_state, | |
720 | .get_clockgating_state = soc21_common_get_clockgating_state, | |
721 | }; |