projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/amd/amdgpu: Fix warnings in amdgpu _object, _ring.c
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / soc21.c
CommitLineData
71199aa4
SY		 1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "amdgpu_smu.h"
36#include "atom.h"
37#include "amd_pcie.h"
38
39#include "gc/gc_11_0_0_offset.h"
40#include "gc/gc_11_0_0_sh_mask.h"
41#include "mp/mp_13_0_0_offset.h"
42
43#include "soc15.h"
44#include "soc15_common.h"
caa5eadc 45#include "soc21.h"
39dd895d 46#include "mxgpu_nv.h"
71199aa4
SY		 47
48static const struct amd_ip_funcs soc21_common_ip_funcs;
49
9ac0edaa 50/* SOC21 */
a6de636e 51static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] =
9ac0edaa
JZ		 52{
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
f732e2b3 55 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
9ac0edaa
JZ		 56};
57
a6de636e 58static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] =
9ac0edaa 59{
a6de636e
AD		 60 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
61 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
62};
63
64static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 =
65{
66 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
67 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
9ac0edaa
JZ		 68};
69
a6de636e
AD		 70static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 =
71{
72 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
73 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
74};
75
76static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] =
9ac0edaa 77{
65009bf2 78 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
9ac0edaa
JZ		 79 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
80 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
83};
84
a6de636e 85static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] =
9ac0edaa 86{
a6de636e
AD		 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
91};
92
93static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 =
94{
95 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
96 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
97};
98
99static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =
100{
101 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
102 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
9ac0edaa
JZ		 103};
104
dcaf5000
JJ		 105/* SRIOV SOC21, not const since data is controlled by host */
106static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
110};
111
112static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
115};
116
117static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
118 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
119 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
120};
121
122static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
123 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
124 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
125};
126
127static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
136};
137
138static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
146};
147
148static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
149 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
150 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
151};
152
153static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
154 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
155 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
156};
157
9ac0edaa
JZ		 158static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
159 const struct amdgpu_video_codecs **codecs)
160{
a6de636e
AD		 161 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
162 return -EINVAL;
9ac0edaa 163
a6de636e 164 switch (adev->ip_versions[UVD_HWIP][0]) {
9ac0edaa 165 case IP_VERSION(4, 0, 0):
1c0a9036 166 case IP_VERSION(4, 0, 2):
d068b700 167 case IP_VERSION(4, 0, 4):
dcaf5000
JJ		 168 if (amdgpu_sriov_vf(adev)) {
169 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
170 !amdgpu_sriov_is_av1_support(adev)) {
171 if (encode)
172 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
173 else
174 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
175 } else {
176 if (encode)
177 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
178 else
179 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
180 }
a6de636e 181 } else {
dcaf5000
JJ		 182 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
183 if (encode)
184 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
185 else
186 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
187 } else {
188 if (encode)
189 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
190 else
191 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
192 }
a6de636e 193 }
9ac0edaa
JZ		 194 return 0;
195 default:
196 return -EINVAL;
197 }
198}
71199aa4
SY		 199
200static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
201{
202 unsigned long flags, address, data;
203 u32 r;
204
205 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
206 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
207
208 spin_lock_irqsave(&adev->didt_idx_lock, flags);
209 WREG32(address, (reg));
210 r = RREG32(data);
211 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
212 return r;
213}
214
215static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
216{
217 unsigned long flags, address, data;
218
219 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
220 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
221
222 spin_lock_irqsave(&adev->didt_idx_lock, flags);
223 WREG32(address, (reg));
224 WREG32(data, (v));
225 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
226}
227
228static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
229{
230 return adev->nbio.funcs->get_memsize(adev);
231}
232
233static u32 soc21_get_xclk(struct amdgpu_device *adev)
234{
235 return adev->clock.spll.reference_freq;
236}
237
238
239void soc21_grbm_select(struct amdgpu_device *adev,
240 u32 me, u32 pipe, u32 queue, u32 vmid)
241{
242 u32 grbm_gfx_cntl = 0;
243 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
244 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
245 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
246 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
247
bbb860d4 248 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
71199aa4
SY		 249}
250
251static void soc21_vga_set_state(struct amdgpu_device *adev, bool state)
252{
253 /* todo */
254}
255
256static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
257{
258 /* todo */
259 return false;
260}
261
262static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
263 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
264 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
265 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
266 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
267 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
268 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
269 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
270 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
271 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
272 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
273 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
274 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
275 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
276 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
277 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
278 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
279 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
280 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
281 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
282};
283
284static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
285 u32 sh_num, u32 reg_offset)
286{
287 uint32_t val;
288
289 mutex_lock(&adev->grbm_idx_mutex);
290 if (se_num != 0xffffffff || sh_num != 0xffffffff)
d51ac6d0 291 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
71199aa4
SY		 292
293 val = RREG32(reg_offset);
294
295 if (se_num != 0xffffffff || sh_num != 0xffffffff)
d51ac6d0 296 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
71199aa4
SY		 297 mutex_unlock(&adev->grbm_idx_mutex);
298 return val;
299}
300
301static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
302 bool indexed, u32 se_num,
303 u32 sh_num, u32 reg_offset)
304{
305 if (indexed) {
306 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
307 } else {
308 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
309 return adev->gfx.config.gb_addr_config;
310 return RREG32(reg_offset);
311 }
312}
313
314static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
315 u32 sh_num, u32 reg_offset, u32 *value)
316{
317 uint32_t i;
318 struct soc15_allowed_register_entry *en;
319
320 *value = 0;
321 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
322 en = &soc21_allowed_read_registers[i];
ba137e64
AD		 323 if (!adev->reg_offset[en->hwip][en->inst])
324 continue;
325 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
326 + en->reg_offset))
71199aa4
SY		 327 continue;
328
329 *value = soc21_get_register_value(adev,
330 soc21_allowed_read_registers[i].grbm_indexed,
331 se_num, sh_num, reg_offset);
332 return 0;
333 }
334 return -EINVAL;
335}
336
337#if 0
338static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
339{
340 u32 i;
341 int ret = 0;
342
343 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
344
345 /* disable BM */
346 pci_clear_master(adev->pdev);
347
348 amdgpu_device_cache_pci_state(adev->pdev);
349
350 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
351 dev_info(adev->dev, "GPU smu mode1 reset\n");
352 ret = amdgpu_dpm_mode1_reset(adev);
353 } else {
354 dev_info(adev->dev, "GPU psp mode1 reset\n");
355 ret = psp_gpu_reset(adev);
356 }
357
358 if (ret)
359 dev_err(adev->dev, "GPU mode1 reset failed\n");
360 amdgpu_device_load_pci_state(adev->pdev);
361
362 /* wait for asic to come out of reset */
363 for (i = 0; i < adev->usec_timeout; i++) {
364 u32 memsize = adev->nbio.funcs->get_memsize(adev);
365
366 if (memsize != 0xffffffff)
367 break;
368 udelay(1);
369 }
370
371 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
372
373 return ret;
374}
375#endif
376
377static enum amd_reset_method
378soc21_asic_reset_method(struct amdgpu_device *adev)
379{
380 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
ea64228d 381 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
71199aa4
SY		 382 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
383 return amdgpu_reset_method;
384
385 if (amdgpu_reset_method != -1)
386 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
387 amdgpu_reset_method);
388
389 switch (adev->ip_versions[MP1_HWIP][0]) {
390 case IP_VERSION(13, 0, 0):
a53bc321 391 case IP_VERSION(13, 0, 7):
60cfad32 392 case IP_VERSION(13, 0, 10):
71199aa4 393 return AMD_RESET_METHOD_MODE1;
ea64228d 394 case IP_VERSION(13, 0, 4):
18ad1885 395 case IP_VERSION(13, 0, 11):
ea64228d 396 return AMD_RESET_METHOD_MODE2;
71199aa4
SY		 397 default:
398 if (amdgpu_dpm_is_baco_supported(adev))
399 return AMD_RESET_METHOD_BACO;
400 else
401 return AMD_RESET_METHOD_MODE1;
402 }
403}
404
405static int soc21_asic_reset(struct amdgpu_device *adev)
406{
407 int ret = 0;
408
409 switch (soc21_asic_reset_method(adev)) {
410 case AMD_RESET_METHOD_PCI:
411 dev_info(adev->dev, "PCI reset\n");
412 ret = amdgpu_device_pci_reset(adev);
413 break;
414 case AMD_RESET_METHOD_BACO:
415 dev_info(adev->dev, "BACO reset\n");
416 ret = amdgpu_dpm_baco_reset(adev);
417 break;
ea64228d
AD		 418 case AMD_RESET_METHOD_MODE2:
419 dev_info(adev->dev, "MODE2 reset\n");
420 ret = amdgpu_dpm_mode2_reset(adev);
421 break;
71199aa4
SY		 422 default:
423 dev_info(adev->dev, "MODE1 reset\n");
424 ret = amdgpu_device_mode1_reset(adev);
425 break;
426 }
427
428 return ret;
429}
430
431static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
432{
433 /* todo */
434 return 0;
435}
436
437static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
438{
439 /* todo */
440 return 0;
441}
442
71199aa4
SY		 443static void soc21_program_aspm(struct amdgpu_device *adev)
444{
62f8f5c3 445 if (!amdgpu_device_should_use_aspm(adev))
71199aa4
SY		 446 return;
447
62f8f5c3
EQ		 448 if (!(adev->flags & AMD_IS_APU) &&
449 (adev->nbio.funcs->program_aspm))
450 adev->nbio.funcs->program_aspm(adev);
71199aa4
SY		 451}
452
71199aa4
SY		 453const struct amdgpu_ip_block_version soc21_common_ip_block =
454{
455 .type = AMD_IP_BLOCK_TYPE_COMMON,
456 .major = 1,
457 .minor = 0,
458 .rev = 0,
459 .funcs = &soc21_common_ip_funcs,
460};
461
71199aa4
SY		 462static bool soc21_need_full_reset(struct amdgpu_device *adev)
463{
c0ff84cb
LG		 464 switch (adev->ip_versions[GC_HWIP][0]) {
465 case IP_VERSION(11, 0, 0):
34dfca89 466 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
c0ff84cb 467 case IP_VERSION(11, 0, 2):
2e26bf1e 468 case IP_VERSION(11, 0, 3):
c0ff84cb
LG		 469 return false;
470 default:
471 return true;
472 }
71199aa4
SY		 473}
474
475static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
476{
477 u32 sol_reg;
478
479 if (adev->flags & AMD_IS_APU)
480 return false;
481
482 /* Check sOS sign of life register to confirm sys driver and sOS
483 * are already been loaded.
484 */
485 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
486 if (sol_reg)
487 return true;
488
489 return false;
490}
491
492static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev)
493{
494
495 /* TODO
496 * dummy implement for pcie_replay_count sysfs interface
497 * */
498
499 return 0;
500}
501
502static void soc21_init_doorbell_index(struct amdgpu_device *adev)
503{
504 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
505 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
506 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
507 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
508 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
509 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
510 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
511 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
512 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
513 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
514 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
515 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
516 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
fd0ed91a
JX		 517 adev->doorbell_index.gfx_userqueue_start =
518 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
519 adev->doorbell_index.gfx_userqueue_end =
520 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
b608e785
JX		 521 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
522 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
71199aa4
SY		 523 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
524 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
525 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
526 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
527 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
528 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
529 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
530 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
531 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
532
533 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
534 adev->doorbell_index.sdma_doorbell_range = 20;
535}
536
537static void soc21_pre_asic_init(struct amdgpu_device *adev)
538{
539}
540
72010239
LG		 541static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
542 bool enter)
543{
544 if (enter)
86b20703 545 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
72010239 546 else
86b20703 547 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
72010239
LG		 548
549 if (adev->gfx.funcs->update_perfmon_mgcg)
550 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
551
552 return 0;
553}
554
71199aa4
SY		 555static const struct amdgpu_asic_funcs soc21_asic_funcs =
556{
557 .read_disabled_bios = &soc21_read_disabled_bios,
558 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
559 .read_register = &soc21_read_register,
560 .reset = &soc21_asic_reset,
561 .reset_method = &soc21_asic_reset_method,
562 .set_vga_state = &soc21_vga_set_state,
563 .get_xclk = &soc21_get_xclk,
564 .set_uvd_clocks = &soc21_set_uvd_clocks,
565 .set_vce_clocks = &soc21_set_vce_clocks,
566 .get_config_memsize = &soc21_get_config_memsize,
567 .init_doorbell_index = &soc21_init_doorbell_index,
568 .need_full_reset = &soc21_need_full_reset,
569 .need_reset_on_init = &soc21_need_reset_on_init,
570 .get_pcie_replay_count = &soc21_get_pcie_replay_count,
571 .supports_baco = &amdgpu_dpm_is_baco_supported,
572 .pre_asic_init = &soc21_pre_asic_init,
9ac0edaa 573 .query_video_codecs = &soc21_query_video_codecs,
72010239 574 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
71199aa4
SY		 575};
576
577static int soc21_common_early_init(void *handle)
578{
579#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
581
582 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
583 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
584 adev->smc_rreg = NULL;
585 adev->smc_wreg = NULL;
65ba96e9
HZ		 586 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
587 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
588 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
589 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
bafd6cbe
XD		 590 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
591 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
71199aa4
SY		 592
593 /* TODO: will add them during VCN v2 implementation */
594 adev->uvd_ctx_rreg = NULL;
595 adev->uvd_ctx_wreg = NULL;
596
597 adev->didt_rreg = &soc21_didt_rreg;
598 adev->didt_wreg = &soc21_didt_wreg;
599
600 adev->asic_funcs = &soc21_asic_funcs;
601
dabc114e 602 adev->rev_id = amdgpu_device_get_rev_id(adev);
71199aa4
SY		 603 adev->external_rev_id = 0xff;
604 switch (adev->ip_versions[GC_HWIP][0]) {
605 case IP_VERSION(11, 0, 0):
390db4b8 606 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
b21348a2 607 AMD_CG_SUPPORT_GFX_CGLS |
1b586595 608#if 0
915b5ce7
EQ		 609 AMD_CG_SUPPORT_GFX_3D_CGCG |
610 AMD_CG_SUPPORT_GFX_3D_CGLS |
1b586595 611#endif
915b5ce7 612 AMD_CG_SUPPORT_GFX_MGCG |
8b719b96 613 AMD_CG_SUPPORT_REPEATER_FGCG |
915b5ce7
EQ		 614 AMD_CG_SUPPORT_GFX_FGCG |
615 AMD_CG_SUPPORT_GFX_PERF_CLK |
7c507d35 616 AMD_CG_SUPPORT_VCN_MGCG |
c649ed05
EQ		 617 AMD_CG_SUPPORT_JPEG_MGCG |
618 AMD_CG_SUPPORT_ATHUB_MGCG |
7ccf6eb0
EQ		 619 AMD_CG_SUPPORT_ATHUB_LS |
620 AMD_CG_SUPPORT_MC_MGCG |
20139069 621 AMD_CG_SUPPORT_MC_LS |
d386f645
EQ		 622 AMD_CG_SUPPORT_IH_CG |
623 AMD_CG_SUPPORT_HDP_SD;
8b719b96 624 adev->pg_flags = AMD_PG_SUPPORT_VCN |
04270390 625 AMD_PG_SUPPORT_VCN_DPG |
7c507d35 626 AMD_PG_SUPPORT_JPEG |
8b719b96 627 AMD_PG_SUPPORT_ATHUB |
a6dec868 628 AMD_PG_SUPPORT_MMHUB;
71199aa4
SY		 629 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
630 break;
92fd2153 631 case IP_VERSION(11, 0, 2):
71dae221 632 adev->cg_flags =
9503a944
LG		 633 AMD_CG_SUPPORT_GFX_CGCG |
634 AMD_CG_SUPPORT_GFX_CGLS |
49401d3a 635 AMD_CG_SUPPORT_REPEATER_FGCG |
7ece9314 636 AMD_CG_SUPPORT_VCN_MGCG |
49401d3a
KF		 637 AMD_CG_SUPPORT_JPEG_MGCG |
638 AMD_CG_SUPPORT_ATHUB_MGCG |
b4ddb27d
KF		 639 AMD_CG_SUPPORT_ATHUB_LS |
640 AMD_CG_SUPPORT_IH_CG |
641 AMD_CG_SUPPORT_HDP_SD;
ebac66a3 642 adev->pg_flags =
143a34a0 643 AMD_PG_SUPPORT_VCN |
ec9db74e 644 AMD_PG_SUPPORT_VCN_DPG |
27e3911c
KF		 645 AMD_PG_SUPPORT_JPEG |
646 AMD_PG_SUPPORT_ATHUB |
647 AMD_PG_SUPPORT_MMHUB;
92fd2153
FC		 648 adev->external_rev_id = adev->rev_id + 0x10;
649 break;
11417a92 650 case IP_VERSION(11, 0, 1):
47231d5e 651 adev->cg_flags =
8df436d5
TH		 652 AMD_CG_SUPPORT_GFX_CGCG |
653 AMD_CG_SUPPORT_GFX_CGLS |
654 AMD_CG_SUPPORT_GFX_MGCG |
655 AMD_CG_SUPPORT_GFX_FGCG |
656 AMD_CG_SUPPORT_REPEATER_FGCG |
657 AMD_CG_SUPPORT_GFX_PERF_CLK |
adcd15dc
TH		 658 AMD_CG_SUPPORT_MC_MGCG |
659 AMD_CG_SUPPORT_MC_LS |
7e4a77de
TH		 660 AMD_CG_SUPPORT_HDP_MGCG |
661 AMD_CG_SUPPORT_HDP_LS |
8e78c7c4
TH		 662 AMD_CG_SUPPORT_ATHUB_MGCG |
663 AMD_CG_SUPPORT_ATHUB_LS |
fa0bbd3b 664 AMD_CG_SUPPORT_IH_CG |
9407feac
TH		 665 AMD_CG_SUPPORT_BIF_MGCG |
666 AMD_CG_SUPPORT_BIF_LS |
47231d5e
SJ		 667 AMD_CG_SUPPORT_VCN_MGCG |
668 AMD_CG_SUPPORT_JPEG_MGCG;
669 adev->pg_flags =
dc0a096b 670 AMD_PG_SUPPORT_GFX_PG |
e626d9b9 671 AMD_PG_SUPPORT_VCN |
0b37f474 672 AMD_PG_SUPPORT_VCN_DPG |
47231d5e 673 AMD_PG_SUPPORT_JPEG;
11417a92
HR		 674 adev->external_rev_id = adev->rev_id + 0x1;
675 break;
6b46251c 676 case IP_VERSION(11, 0, 3):
0f05a2e5 677 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
4ecdb30e
KF		 678 AMD_CG_SUPPORT_JPEG_MGCG |
679 AMD_CG_SUPPORT_GFX_CGCG |
680 AMD_CG_SUPPORT_GFX_CGLS |
681 AMD_CG_SUPPORT_REPEATER_FGCG |
20e6220b 682 AMD_CG_SUPPORT_GFX_MGCG |
ad1cebb6
KF		 683 AMD_CG_SUPPORT_HDP_SD |
684 AMD_CG_SUPPORT_ATHUB_MGCG |
685 AMD_CG_SUPPORT_ATHUB_LS;
0f05a2e5
SJ		 686 adev->pg_flags = AMD_PG_SUPPORT_VCN |
687 AMD_PG_SUPPORT_VCN_DPG |
688 AMD_PG_SUPPORT_JPEG;
6b46251c
HZ		 689 adev->external_rev_id = adev->rev_id + 0x20;
690 break;
311d5236 691 case IP_VERSION(11, 0, 4):
f2b91e5a
TH		 692 adev->cg_flags =
693 AMD_CG_SUPPORT_GFX_CGCG |
694 AMD_CG_SUPPORT_GFX_CGLS |
695 AMD_CG_SUPPORT_GFX_MGCG |
696 AMD_CG_SUPPORT_GFX_FGCG |
697 AMD_CG_SUPPORT_REPEATER_FGCG |
698 AMD_CG_SUPPORT_GFX_PERF_CLK |
699 AMD_CG_SUPPORT_MC_MGCG |
700 AMD_CG_SUPPORT_MC_LS |
701 AMD_CG_SUPPORT_HDP_MGCG |
702 AMD_CG_SUPPORT_HDP_LS |
703 AMD_CG_SUPPORT_ATHUB_MGCG |
704 AMD_CG_SUPPORT_ATHUB_LS |
705 AMD_CG_SUPPORT_IH_CG |
706 AMD_CG_SUPPORT_BIF_MGCG |
707 AMD_CG_SUPPORT_BIF_LS |
708 AMD_CG_SUPPORT_VCN_MGCG |
2a0fe2ca
SJ		 709 AMD_CG_SUPPORT_JPEG_MGCG;
710 adev->pg_flags = AMD_PG_SUPPORT_VCN |
9c705b96 711 AMD_PG_SUPPORT_VCN_DPG |
2a0fe2ca
SJ		 712 AMD_PG_SUPPORT_GFX_PG |
713 AMD_PG_SUPPORT_JPEG;
311d5236
YZ		 714 adev->external_rev_id = adev->rev_id + 0x1;
715 break;
716
71199aa4
SY		 717 default:
718 /* FIXME: not supported yet */
719 return -EINVAL;
720 }
721
39dd895d 722 if (amdgpu_sriov_vf(adev)) {
0cfce240 723 amdgpu_virt_init_setting(adev);
39dd895d
YW		 724 xgpu_nv_mailbox_set_irq_funcs(adev);
725 }
0cfce240 726
71199aa4
SY		 727 return 0;
728}
729
730static int soc21_common_late_init(void *handle)
731{
39dd895d
YW		 732 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
733
dcaf5000 734 if (amdgpu_sriov_vf(adev)) {
39dd895d 735 xgpu_nv_mailbox_get_irq(adev);
dcaf5000
JJ		 736 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
737 !amdgpu_sriov_is_av1_support(adev)) {
738 amdgpu_virt_update_sriov_video_codec(adev,
739 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
740 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
741 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
742 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
743 } else {
744 amdgpu_virt_update_sriov_video_codec(adev,
745 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
746 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
747 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
748 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
749 }
9af357bc
HZ		 750 } else {
751 if (adev->nbio.ras &&
752 adev->nbio.ras_err_event_athub_irq.funcs)
753 /* don't need to fail gpu late init
754 * if enabling athub_err_event interrupt failed
755 * nbio v4_3 only support fatal error hanlding
756 * just enable the interrupt directly */
757 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
dcaf5000 758 }
39dd895d 759
1c312e81
SX		 760 /* Enable selfring doorbell aperture late because doorbell BAR
761 * aperture will change if resize BAR successfully in gmc sw_init.
762 */
763 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
764
71199aa4
SY		 765 return 0;
766}
767
768static int soc21_common_sw_init(void *handle)
769{
39dd895d
YW		 770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 if (amdgpu_sriov_vf(adev))
773 xgpu_nv_mailbox_add_irq_id(adev);
774
71199aa4
SY		 775 return 0;
776}
777
778static int soc21_common_sw_fini(void *handle)
779{
780 return 0;
781}
782
783static int soc21_common_hw_init(void *handle)
784{
785 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
786
71199aa4
SY		 787 /* enable aspm */
788 soc21_program_aspm(adev);
789 /* setup nbio registers */
790 adev->nbio.funcs->init_registers(adev);
791 /* remap HDP registers to a hole in mmio space,
792 * for the purpose of expose those registers
793 * to process space
794 */
795 if (adev->nbio.funcs->remap_hdp_registers)
796 adev->nbio.funcs->remap_hdp_registers(adev);
797 /* enable the doorbell aperture */
1c312e81 798 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
71199aa4
SY		 799
800 return 0;
801}
802
803static int soc21_common_hw_fini(void *handle)
804{
805 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
806
1c312e81
SX		 807 /* Disable the doorbell aperture and selfring doorbell aperture
808 * separately in hw_fini because soc21_enable_doorbell_aperture
809 * has been removed and there is no need to delay disabling
810 * selfring doorbell.
811 */
812 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
813 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
71199aa4 814
9af357bc 815 if (amdgpu_sriov_vf(adev)) {
39dd895d 816 xgpu_nv_mailbox_put_irq(adev);
9af357bc
HZ		 817 } else {
818 if (adev->nbio.ras &&
819 adev->nbio.ras_err_event_athub_irq.funcs)
820 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
821 }
39dd895d 822
71199aa4
SY		 823 return 0;
824}
825
826static int soc21_common_suspend(void *handle)
827{
828 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
829
830 return soc21_common_hw_fini(adev);
831}
832
833static int soc21_common_resume(void *handle)
834{
835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
836
837 return soc21_common_hw_init(adev);
838}
839
840static bool soc21_common_is_idle(void *handle)
841{
842 return true;
843}
844
845static int soc21_common_wait_for_idle(void *handle)
846{
847 return 0;
848}
849
850static int soc21_common_soft_reset(void *handle)
851{
852 return 0;
853}
854
855static int soc21_common_set_clockgating_state(void *handle,
856 enum amd_clockgating_state state)
857{
858 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
859
860 switch (adev->ip_versions[NBIO_HWIP][0]) {
861 case IP_VERSION(4, 3, 0):
b4ddb27d 862 case IP_VERSION(4, 3, 1):
9407feac 863 case IP_VERSION(7, 7, 0):
71199aa4
SY		 864 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
865 state == AMD_CG_STATE_GATE);
866 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
867 state == AMD_CG_STATE_GATE);
868 adev->hdp.funcs->update_clock_gating(adev,
869 state == AMD_CG_STATE_GATE);
870 break;
871 default:
872 break;
873 }
874 return 0;
875}
876
877static int soc21_common_set_powergating_state(void *handle,
878 enum amd_powergating_state state)
879{
41967850
LG		 880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
881
882 switch (adev->ip_versions[LSDMA_HWIP][0]) {
883 case IP_VERSION(6, 0, 0):
362c3c70 884 case IP_VERSION(6, 0, 2):
41967850
LG		 885 adev->lsdma.funcs->update_memory_power_gating(adev,
886 state == AMD_PG_STATE_GATE);
887 break;
888 default:
889 break;
890 }
891
71199aa4
SY		 892 return 0;
893}
894
895static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
896{
897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
898
899 adev->nbio.funcs->get_clockgating_state(adev, flags);
900
901 adev->hdp.funcs->get_clock_gating_state(adev, flags);
902
903 return;
904}
905
906static const struct amd_ip_funcs soc21_common_ip_funcs = {
907 .name = "soc21_common",
908 .early_init = soc21_common_early_init,
909 .late_init = soc21_common_late_init,
910 .sw_init = soc21_common_sw_init,
911 .sw_fini = soc21_common_sw_fini,
912 .hw_init = soc21_common_hw_init,
913 .hw_fini = soc21_common_hw_fini,
914 .suspend = soc21_common_suspend,
915 .resume = soc21_common_resume,
916 .is_idle = soc21_common_is_idle,
917 .wait_for_idle = soc21_common_wait_for_idle,
918 .soft_reset = soc21_common_soft_reset,
919 .set_clockgating_state = soc21_common_set_clockgating_state,
920 .set_powergating_state = soc21_common_set_powergating_state,
921 .get_clockgating_state = soc21_common_get_clockgating_state,
922};
Linux 6.x block layer and io_uring tree(s)