[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __SOC15_H__
#define __SOC15_H__

#include "nbio_v6_1.h"
#include "nbio_v7_0.h"
#include "nbio_v7_4.h"
#include "amdgpu_reg_state.h"

extern const struct amdgpu_ip_block_version vega10_common_ip_block;

#define SOC15_FLUSH_GPU_TLB_NUM_WREG		6
#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT	3

struct soc15_reg_golden {
	u32	hwip;
	u32	instance;
	u32	segment;
	u32	reg;
	u32	and_mask;
	u32	or_mask;
};

struct soc15_reg_rlcg {
	u32	hwip;
	u32	instance;
	u32	segment;
	u32	reg;
};

struct soc15_reg {
	uint32_t hwip;
	uint32_t inst;
	uint32_t seg;
	uint32_t reg_offset;
};

struct soc15_reg_entry {
	uint32_t hwip;
	uint32_t inst;
	uint32_t seg;
	uint32_t reg_offset;
	uint32_t reg_value;
	uint32_t se_num;
	uint32_t instance;
};

struct soc15_allowed_register_entry {
	uint32_t hwip;
	uint32_t inst;
	uint32_t seg;
	uint32_t reg_offset;
	bool grbm_indexed;
};

struct soc15_ras_field_entry {
	const char *name;
	uint32_t hwip;
	uint32_t inst;
	uint32_t seg;
	uint32_t reg_offset;
	uint32_t sec_count_mask;
	uint32_t sec_count_shift;
	uint32_t ded_count_mask;
	uint32_t ded_count_shift;
};

#define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg
#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }

#define SOC15_REG_ENTRY_OFFSET(entry)	(adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)

/* Over ride the instance id */
#define SOC15_REG_ENTRY_OFFSET_INST(entry, inst) \
	(adev->reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)

#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }

#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT

#define SOC15_REG_FIELD_VAL(val, mask, shift)	(((val) & mask) >> shift)

#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)

void soc15_grbm_select(struct amdgpu_device *adev,
		    u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
void soc15_set_virt_ops(struct amdgpu_device *adev);

void soc15_program_register_sequence(struct amdgpu_device *adev,
					     const struct soc15_reg_golden *registers,
					     const u32 array_size);

int vega10_reg_base_init(struct amdgpu_device *adev);
int vega20_reg_base_init(struct amdgpu_device *adev);
int arct_reg_base_init(struct amdgpu_device *adev);
int aldebaran_reg_base_init(struct amdgpu_device *adev);
void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev);
u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);
int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);
ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,
				    enum amdgpu_reg_state reg_state, void *buf,
				    size_t max_size);

void vega10_doorbell_index_init(struct amdgpu_device *adev);
void vega20_doorbell_index_init(struct amdgpu_device *adev);
void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev);
#endif
Commit	Line	Data
8e3153ba KW	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __SOC15_H__
	25	#define __SOC15_H__
	26
	27	#include "nbio_v6_1.h"
aecbe64f	28	#include "nbio_v7_0.h"
fe3c9489	29	#include "nbio_v7_4.h"
081a6eda	30	#include "amdgpu_reg_state.h"
8e3153ba	31
994470b2 AD	32	extern const struct amdgpu_ip_block_version vega10_common_ip_block;
994470b2 AD	33
4ed8a037	34	#define SOC15_FLUSH_GPU_TLB_NUM_WREG 6
4ed8a037	35	#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3
9096d6e5	36
946a4d5b SL	37	struct soc15_reg_golden {
	38	u32 hwip;
	39	u32 instance;
	40	u32 segment;
	41	u32 reg;
	42	u32 and_mask;
	43	u32 or_mask;
	44	};
	45
2e0cc4d4 ML	46	struct soc15_reg_rlcg {
	47	u32 hwip;
	48	u32 instance;
	49	u32 segment;
	50	u32 reg;
	51	};
	52
22616eb5 DL	53	struct soc15_reg {
	54	uint32_t hwip;
	55	uint32_t inst;
	56	uint32_t seg;
	57	uint32_t reg_offset;
	58	};
	59
5326ad54 JZ	60	struct soc15_reg_entry {
	61	uint32_t hwip;
	62	uint32_t inst;
	63	uint32_t seg;
	64	uint32_t reg_offset;
	65	uint32_t reg_value;
052af915 JZ	66	uint32_t se_num;
052af915 JZ	67	uint32_t instance;
5326ad54 JZ	68	};
5326ad54 JZ	69
44f1bb1f HZ	70	struct soc15_allowed_register_entry {
	71	uint32_t hwip;
	72	uint32_t inst;
	73	uint32_t seg;
	74	uint32_t reg_offset;
	75	bool grbm_indexed;
	76	};
	77
46f71969 DL	78	struct soc15_ras_field_entry {
	79	const char *name;
	80	uint32_t hwip;
	81	uint32_t inst;
	82	uint32_t seg;
	83	uint32_t reg_offset;
	84	uint32_t sec_count_mask;
	85	uint32_t sec_count_shift;
	86	uint32_t ded_count_mask;
	87	uint32_t ded_count_shift;
	88	};
	89
946a4d5b	90	#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
c395dbb6 SK	91	#define SOC15_REG_ENTRY_STR(ip, inst, reg) \
c395dbb6 SK	92	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg }
946a4d5b	93
5326ad54 JZ	94	#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
5326ad54 JZ	95
50d10d92 SK	96	/* Over ride the instance id */
	97	#define SOC15_REG_ENTRY_OFFSET_INST(entry, inst) \
	98	(adev->reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)
	99
946a4d5b SL	100	#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
	101	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
	102
13ba0344 DL	103	#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
13ba0344 DL	104
22616eb5 DL	105	#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift)
22616eb5 DL	106
4abc2567	107	#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
22616eb5	108
8e3153ba	109	void soc15_grbm_select(struct amdgpu_device *adev,
5aa998ba	110	u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
c1299461	111	void soc15_set_virt_ops(struct amdgpu_device *adev);
8e3153ba	112
946a4d5b SL	113	void soc15_program_register_sequence(struct amdgpu_device *adev,
	114	const struct soc15_reg_golden *registers,
	115	const u32 array_size);
	116
4522824c	117	int vega10_reg_base_init(struct amdgpu_device *adev);
8ee273e5	118	int vega20_reg_base_init(struct amdgpu_device *adev);
e78705ec	119	int arct_reg_base_init(struct amdgpu_device *adev);
42b72608	120	int aldebaran_reg_base_init(struct amdgpu_device *adev);
cab7d478	121	void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev);
2fa480d3	122	u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);
e56c9ef6	123	int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);
081a6eda LL	124	ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,
	125	enum amdgpu_reg_state reg_state, void *buf,
	126	size_t max_size);
4522824c	127
062f3807	128	void vega10_doorbell_index_init(struct amdgpu_device *adev);
c93aa775	129	void vega20_doorbell_index_init(struct amdgpu_device *adev);
1dfcdc30	130	void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev);
8e3153ba	131	#endif