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drm/amdgpu/vega20: use mode1 reset for RAS and XGMI
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
248a1d6f 26#include <drm/drmP.h>
220ab9bd 27#include "amdgpu.h"
d05da0e2 28#include "amdgpu_atombios.h"
220ab9bd
KW		 29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
5d735f83 37#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 38#include "gc/gc_9_0_offset.h"
39#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 40#include "sdma0/sdma0_4_0_offset.h"
41#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 42#include "hdp/hdp_4_0_offset.h"
43#include "hdp/hdp_4_0_sh_mask.h"
424d9bb4
FX		 44#include "smuio/smuio_9_0_offset.h"
45#include "smuio/smuio_9_0_sh_mask.h"
b45e18ac 46#include "nbio/nbio_7_0_default.h"
88807dc8 47#include "nbio/nbio_7_0_offset.h"
b45e18ac
KR		 48#include "nbio/nbio_7_0_sh_mask.h"
49#include "nbio/nbio_7_0_smn.h"
9281f12c 50#include "mp/mp_9_0_offset.h"
220ab9bd
KW		 51
52#include "soc15.h"
53#include "soc15_common.h"
54#include "gfx_v9_0.h"
55#include "gmc_v9_0.h"
56#include "gfxhub_v1_0.h"
57#include "mmhub_v1_0.h"
070706c0 58#include "df_v1_7.h"
698758bb 59#include "df_v3_6.h"
220ab9bd
KW		 60#include "vega10_ih.h"
61#include "sdma_v4_0.h"
62#include "uvd_v7_0.h"
63#include "vce_v4_0.h"
f2d7e707 64#include "vcn_v1_0.h"
796b6568 65#include "dce_virtual.h"
f1a34465 66#include "mxgpu_ai.h"
2da5410b 67#include "amdgpu_smu.h"
e74609cb
AD		 68#include "amdgpu_ras.h"
69#include "amdgpu_xgmi.h"
88807dc8 70#include <uapi/linux/kfd_ioctl.h>
220ab9bd 71
220ab9bd
KW		 72#define mmMP0_MISC_CGTT_CTRL0 0x01b9
73#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
74#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
75#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
76
a5d0f456
KF		 77/* for Vega20 register name change */
78#define mmHDP_MEM_POWER_CTRL 0x00d4
79#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
80#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
81#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
82#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
83#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
220ab9bd
KW		 84/*
85 * Indirect registers accessor
86 */
87static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
88{
89 unsigned long flags, address, data;
90 u32 r;
946a4d5b
SL		 91 address = adev->nbio_funcs->get_pcie_index_offset(adev);
92 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 93
94 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
95 WREG32(address, reg);
96 (void)RREG32(address);
97 r = RREG32(data);
98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
99 return r;
100}
101
102static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
103{
104 unsigned long flags, address, data;
220ab9bd 105
946a4d5b
SL		 106 address = adev->nbio_funcs->get_pcie_index_offset(adev);
107 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 108
109 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
110 WREG32(address, reg);
111 (void)RREG32(address);
112 WREG32(data, v);
113 (void)RREG32(data);
114 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
115}
116
117static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
118{
119 unsigned long flags, address, data;
120 u32 r;
121
122 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
123 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
124
125 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
126 WREG32(address, ((reg) & 0x1ff));
127 r = RREG32(data);
128 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
129 return r;
130}
131
132static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
133{
134 unsigned long flags, address, data;
135
136 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
137 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
138
139 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
140 WREG32(address, ((reg) & 0x1ff));
141 WREG32(data, (v));
142 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
143}
144
145static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
146{
147 unsigned long flags, address, data;
148 u32 r;
149
150 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
151 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
152
153 spin_lock_irqsave(&adev->didt_idx_lock, flags);
154 WREG32(address, (reg));
155 r = RREG32(data);
156 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
157 return r;
158}
159
160static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
161{
162 unsigned long flags, address, data;
163
164 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
165 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
166
167 spin_lock_irqsave(&adev->didt_idx_lock, flags);
168 WREG32(address, (reg));
169 WREG32(data, (v));
170 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
171}
172
560460f2
EQ		 173static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
174{
175 unsigned long flags;
176 u32 r;
177
178 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
179 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
180 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
181 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
182 return r;
183}
184
185static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
186{
187 unsigned long flags;
188
189 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
190 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
191 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
192 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
193}
194
2f11fb02
EQ		 195static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
196{
197 unsigned long flags;
198 u32 r;
199
200 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
201 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
202 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
203 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
204 return r;
205}
206
207static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
208{
209 unsigned long flags;
210
211 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
212 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
213 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
214 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
215}
216
220ab9bd
KW		 217static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
218{
bf383fb6 219 return adev->nbio_funcs->get_memsize(adev);
220ab9bd
KW		 220}
221
220ab9bd
KW		 222static u32 soc15_get_xclk(struct amdgpu_device *adev)
223{
76d6172b 224 return adev->clock.spll.reference_freq;
220ab9bd
KW		 225}
226
227
228void soc15_grbm_select(struct amdgpu_device *adev,
229 u32 me, u32 pipe, u32 queue, u32 vmid)
230{
231 u32 grbm_gfx_cntl = 0;
232 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
233 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
234 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
235 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
236
1bff7f6c 237 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
220ab9bd
KW		 238}
239
240static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
241{
242 /* todo */
243}
244
245static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
246{
247 /* todo */
248 return false;
249}
250
251static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
252 u8 *bios, u32 length_bytes)
253{
254 u32 *dw_ptr;
255 u32 i, length_dw;
256
257 if (bios == NULL)
258 return false;
259 if (length_bytes == 0)
260 return false;
261 /* APU vbios image is part of sbios image */
262 if (adev->flags & AMD_IS_APU)
263 return false;
264
265 dw_ptr = (u32 *)bios;
266 length_dw = ALIGN(length_bytes, 4) / 4;
267
268 /* set rom index to 0 */
269 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
270 /* read out the rom data */
271 for (i = 0; i < length_dw; i++)
272 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
273
274 return true;
275}
276
946a4d5b
SL		 277struct soc15_allowed_register_entry {
278 uint32_t hwip;
279 uint32_t inst;
280 uint32_t seg;
281 uint32_t reg_offset;
282 bool grbm_indexed;
283};
284
285
286static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
287 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
288 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
289 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
290 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
291 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
292 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
293 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
294 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
295 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
296 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
297 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
298 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
299 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
300 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
301 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
302 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
303 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
304 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
5eeae247 305 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
220ab9bd
KW		 306};
307
308static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
309 u32 sh_num, u32 reg_offset)
310{
311 uint32_t val;
312
313 mutex_lock(&adev->grbm_idx_mutex);
314 if (se_num != 0xffffffff || sh_num != 0xffffffff)
315 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
316
317 val = RREG32(reg_offset);
318
319 if (se_num != 0xffffffff || sh_num != 0xffffffff)
320 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
321 mutex_unlock(&adev->grbm_idx_mutex);
322 return val;
323}
324
c013cea2
AD		 325static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
326 bool indexed, u32 se_num,
327 u32 sh_num, u32 reg_offset)
328{
329 if (indexed) {
330 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
331 } else {
cd29253f 332 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 333 return adev->gfx.config.gb_addr_config;
5eeae247
AD		 334 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
335 return adev->gfx.config.db_debug2;
cd29253f 336 return RREG32(reg_offset);
c013cea2
AD		 337 }
338}
339
220ab9bd
KW		 340static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
341 u32 sh_num, u32 reg_offset, u32 *value)
342{
3032f350 343 uint32_t i;
946a4d5b 344 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 345
346 *value = 0;
220ab9bd 347 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 348 en = &soc15_allowed_read_registers[i];
349 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
350 + en->reg_offset))
220ab9bd
KW		 351 continue;
352
97fcc76b
CK		 353 *value = soc15_get_register_value(adev,
354 soc15_allowed_read_registers[i].grbm_indexed,
355 se_num, sh_num, reg_offset);
220ab9bd
KW		 356 return 0;
357 }
358 return -EINVAL;
359}
360
946a4d5b
SL		 361
362/**
363 * soc15_program_register_sequence - program an array of registers.
364 *
365 * @adev: amdgpu_device pointer
366 * @regs: pointer to the register array
367 * @array_size: size of the register array
368 *
369 * Programs an array or registers with and and or masks.
370 * This is a helper for setting golden registers.
371 */
372
373void soc15_program_register_sequence(struct amdgpu_device *adev,
374 const struct soc15_reg_golden *regs,
375 const u32 array_size)
376{
377 const struct soc15_reg_golden *entry;
378 u32 tmp, reg;
379 int i;
380
381 for (i = 0; i < array_size; ++i) {
382 entry = &regs[i];
383 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
384
385 if (entry->and_mask == 0xffffffff) {
386 tmp = entry->or_mask;
387 } else {
388 tmp = RREG32(reg);
389 tmp &= ~(entry->and_mask);
390 tmp |= entry->or_mask;
391 }
1bff7f6c
TH		 392
393 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
394 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
395 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
396 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
397 WREG32_RLC(reg, tmp);
398 else
399 WREG32(reg, tmp);
400
946a4d5b
SL		 401 }
402
403}
404
e2b6d053 405static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
220ab9bd
KW		 406{
407 u32 i;
39fee32b 408 int ret = 0;
220ab9bd 409
98512bb8
KW		 410 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
411
e2b6d053 412 dev_info(adev->dev, "GPU mode1 reset\n");
220ab9bd
KW		 413
414 /* disable BM */
415 pci_clear_master(adev->pdev);
220ab9bd 416
98512bb8
KW		 417 pci_save_state(adev->pdev);
418
39fee32b
EQ		 419 ret = psp_gpu_reset(adev);
420 if (ret)
421 dev_err(adev->dev, "GPU mode1 reset failed\n");
98512bb8
KW		 422
423 pci_restore_state(adev->pdev);
220ab9bd
KW		 424
425 /* wait for asic to come out of reset */
426 for (i = 0; i < adev->usec_timeout; i++) {
bf383fb6
AD		 427 u32 memsize = adev->nbio_funcs->get_memsize(adev);
428
aecbe64f 429 if (memsize != 0xffffffff)
220ab9bd
KW		 430 break;
431 udelay(1);
432 }
433
d05da0e2 434 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd 435
39fee32b 436 return ret;
220ab9bd
KW		 437}
438
e2b6d053
JQ		 439static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
440{
441 void *pp_handle = adev->powerplay.pp_handle;
442 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
443
444 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
445 *cap = false;
1f46df61 446 return -ENOENT;
e2b6d053
JQ		 447 }
448
449 return pp_funcs->get_asic_baco_capability(pp_handle, cap);
450}
451
452static int soc15_asic_baco_reset(struct amdgpu_device *adev)
453{
454 void *pp_handle = adev->powerplay.pp_handle;
455 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
456
457 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
1f46df61 458 return -ENOENT;
e2b6d053
JQ		 459
460 /* enter BACO state */
461 if (pp_funcs->set_asic_baco_state(pp_handle, 1))
1f46df61 462 return -EIO;
e2b6d053
JQ		 463
464 /* exit BACO state */
465 if (pp_funcs->set_asic_baco_state(pp_handle, 0))
1f46df61 466 return -EIO;
e2b6d053
JQ		 467
468 dev_info(adev->dev, "GPU BACO reset\n");
469
0c5ccf14
EQ		 470 adev->in_baco_reset = 1;
471
e2b6d053
JQ		 472 return 0;
473}
474
475static int soc15_asic_reset(struct amdgpu_device *adev)
476{
477 int ret;
478 bool baco_reset;
479
480 switch (adev->asic_type) {
481 case CHIP_VEGA10:
f8b18cf4 482 case CHIP_VEGA12:
e2b6d053
JQ		 483 soc15_asic_get_baco_capability(adev, &baco_reset);
484 break;
017d75f1
EQ		 485 case CHIP_VEGA20:
486 if (adev->psp.sos_fw_version >= 0x80067)
487 soc15_asic_get_baco_capability(adev, &baco_reset);
488 else
489 baco_reset = false;
e74609cb
AD		 490 if (baco_reset) {
491 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
492 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
493
494 if (hive || (ras && ras->supported))
495 baco_reset = false;
496 }
017d75f1 497 break;
e2b6d053
JQ		 498 default:
499 baco_reset = false;
500 break;
501 }
502
503 if (baco_reset)
504 ret = soc15_asic_baco_reset(adev);
505 else
506 ret = soc15_asic_mode1_reset(adev);
507
508 return ret;
509}
510
220ab9bd
KW		 511/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
512 u32 cntl_reg, u32 status_reg)
513{
514 return 0;
515}*/
516
517static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
518{
519 /*int r;
520
521 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
522 if (r)
523 return r;
524
525 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
526 */
527 return 0;
528}
529
530static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
531{
532 /* todo */
533
534 return 0;
535}
536
537static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
538{
539 if (pci_is_root_bus(adev->pdev->bus))
540 return;
541
542 if (amdgpu_pcie_gen2 == 0)
543 return;
544
545 if (adev->flags & AMD_IS_APU)
546 return;
547
548 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
549 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
550 return;
551
552 /* todo */
553}
554
555static void soc15_program_aspm(struct amdgpu_device *adev)
556{
557
558 if (amdgpu_aspm == 0)
559 return;
560
561 /* todo */
562}
563
564static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 565 bool enable)
220ab9bd 566{
bf383fb6
AD		 567 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
568 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 569}
570
571static const struct amdgpu_ip_block_version vega10_common_ip_block =
572{
573 .type = AMD_IP_BLOCK_TYPE_COMMON,
574 .major = 2,
575 .minor = 0,
576 .rev = 0,
577 .funcs = &soc15_common_ip_funcs,
578};
579
4cb0becb
HR		 580static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
581{
582 return adev->nbio_funcs->get_rev_id(adev);
583}
584
220ab9bd
KW		 585int soc15_set_ip_blocks(struct amdgpu_device *adev)
586{
4522824c
SL		 587 /* Set IP register base before any HW register access */
588 switch (adev->asic_type) {
589 case CHIP_VEGA10:
3084eb00 590 case CHIP_VEGA12:
4522824c
SL		 591 case CHIP_RAVEN:
592 vega10_reg_base_init(adev);
593 break;
8ee273e5
FX		 594 case CHIP_VEGA20:
595 vega20_reg_base_init(adev);
596 break;
4522824c
SL		 597 default:
598 return -EINVAL;
599 }
600
47622ba0
AD		 601 if (adev->asic_type == CHIP_VEGA20)
602 adev->gmc.xgmi.supported = true;
603
bf383fb6
AD		 604 if (adev->flags & AMD_IS_APU)
605 adev->nbio_funcs = &nbio_v7_0_funcs;
fe3c9489
FX		 606 else if (adev->asic_type == CHIP_VEGA20)
607 adev->nbio_funcs = &nbio_v7_4_funcs;
bf383fb6
AD		 608 else
609 adev->nbio_funcs = &nbio_v6_1_funcs;
610
698758bb
FX		 611 if (adev->asic_type == CHIP_VEGA20)
612 adev->df_funcs = &df_v3_6_funcs;
613 else
614 adev->df_funcs = &df_v1_7_funcs;
4cb0becb
HR		 615
616 adev->rev_id = soc15_get_rev_id(adev);
bf383fb6 617 adev->nbio_funcs->detect_hw_virt(adev);
1b922423 618
f1a34465
XY		 619 if (amdgpu_sriov_vf(adev))
620 adev->virt.ops = &xgpu_ai_virt_ops;
621
220ab9bd
KW		 622 switch (adev->asic_type) {
623 case CHIP_VEGA10:
692069a1 624 case CHIP_VEGA12:
7c7af6c1 625 case CHIP_VEGA20:
2990a1fc
AD		 626 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
627 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2d11fd3f
TH		 628
629 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
630 if (amdgpu_sriov_vf(adev)) {
631 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
632 if (adev->asic_type == CHIP_VEGA20)
633 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
634 else
635 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
636 }
637 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
638 } else {
639 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
640 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
641 if (adev->asic_type == CHIP_VEGA20)
642 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
643 else
644 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
645 }
3680b2a5 646 }
009d9ed6
RZ		 647 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
648 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2da5410b 649 if (!amdgpu_sriov_vf(adev)) {
dc8e3a0c 650 if (is_support_sw_smu(adev))
2da5410b
HR		 651 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
652 else
653 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
654 }
f8445307 655 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 656 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 657#if defined(CONFIG_DRM_AMD_DC)
658 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 659 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a
AD		 660#else
661# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
662#endif
846311ae
FM		 663 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
664 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
665 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
666 }
220ab9bd 667 break;
1023b797 668 case CHIP_RAVEN:
40c2358b
HR		 669 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
670 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2990a1fc 671 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
3680b2a5
EQ		 672 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
673 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
009d9ed6
RZ		 674 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
675 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b905090d 676 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 677 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 678 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 679#if defined(CONFIG_DRM_AMD_DC)
680 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 681 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1
AD		 682#else
683# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
684#endif
2990a1fc 685 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 686 break;
220ab9bd
KW		 687 default:
688 return -EINVAL;
689 }
690
691 return 0;
692}
693
69882565 694static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 695{
69882565 696 adev->nbio_funcs->hdp_flush(adev, ring);
73c73240
AD		 697}
698
69882565
CK		 699static void soc15_invalidate_hdp(struct amdgpu_device *adev,
700 struct amdgpu_ring *ring)
73c73240 701{
69882565
CK		 702 if (!ring || !ring->funcs->emit_wreg)
703 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
704 else
705 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
706 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 707}
708
adbd4f89
AD		 709static bool soc15_need_full_reset(struct amdgpu_device *adev)
710{
711 /* change this when we implement soft reset */
712 return true;
713}
b45e18ac
KR		 714static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
715 uint64_t *count1)
716{
717 uint32_t perfctr = 0;
718 uint64_t cnt0_of, cnt1_of;
719 int tmp;
720
721 /* This reports 0 on APUs, so return to avoid writing/reading registers
722 * that may or may not be different from their GPU counterparts
723 */
724 if (adev->flags & AMD_IS_APU)
725 return;
726
727 /* Set the 2 events that we wish to watch, defined above */
728 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
729 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
730 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
731
732 /* Write to enable desired perf counters */
733 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
734 /* Zero out and enable the perf counters
735 * Write 0x5:
736 * Bit 0 = Start all counters(1)
737 * Bit 2 = Global counter reset enable(1)
738 */
739 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
740
741 msleep(1000);
742
743 /* Load the shadow and disable the perf counters
744 * Write 0x2:
745 * Bit 0 = Stop counters(0)
746 * Bit 1 = Load the shadow counters(1)
747 */
748 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
749
750 /* Read register values to get any >32bit overflow */
751 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
752 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
753 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
754
755 /* Get the values and add the overflow */
756 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
757 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
758}
adbd4f89 759
9281f12c
AD		 760static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
761{
762 u32 sol_reg;
763
764 if (adev->flags & AMD_IS_APU)
765 return false;
766
767 /* Check sOS sign of life register to confirm sys driver and sOS
768 * are already been loaded.
769 */
770 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
771 if (sol_reg)
772 return true;
773
774 return false;
775}
776
dcea6e65
KR		 777static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
778{
779 uint64_t nak_r, nak_g;
780
781 /* Get the number of NAKs received and generated */
782 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
783 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
784
785 /* Add the total number of NAKs, i.e the number of replays */
786 return (nak_r + nak_g);
787}
788
220ab9bd
KW		 789static const struct amdgpu_asic_funcs soc15_asic_funcs =
790{
791 .read_disabled_bios = &soc15_read_disabled_bios,
792 .read_bios_from_rom = &soc15_read_bios_from_rom,
793 .read_register = &soc15_read_register,
794 .reset = &soc15_asic_reset,
795 .set_vga_state = &soc15_vga_set_state,
796 .get_xclk = &soc15_get_xclk,
797 .set_uvd_clocks = &soc15_set_uvd_clocks,
798 .set_vce_clocks = &soc15_set_vce_clocks,
799 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 800 .flush_hdp = &soc15_flush_hdp,
801 .invalidate_hdp = &soc15_invalidate_hdp,
adbd4f89 802 .need_full_reset = &soc15_need_full_reset,
062f3807 803 .init_doorbell_index = &vega10_doorbell_index_init,
b45e18ac 804 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 805 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 806 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
220ab9bd
KW		 807};
808
c93aa775
OZ		 809static const struct amdgpu_asic_funcs vega20_asic_funcs =
810{
811 .read_disabled_bios = &soc15_read_disabled_bios,
812 .read_bios_from_rom = &soc15_read_bios_from_rom,
813 .read_register = &soc15_read_register,
814 .reset = &soc15_asic_reset,
815 .set_vga_state = &soc15_vga_set_state,
816 .get_xclk = &soc15_get_xclk,
817 .set_uvd_clocks = &soc15_set_uvd_clocks,
818 .set_vce_clocks = &soc15_set_vce_clocks,
819 .get_config_memsize = &soc15_get_config_memsize,
820 .flush_hdp = &soc15_flush_hdp,
821 .invalidate_hdp = &soc15_invalidate_hdp,
822 .need_full_reset = &soc15_need_full_reset,
823 .init_doorbell_index = &vega20_doorbell_index_init,
b45e18ac 824 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 825 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 826 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
220ab9bd
KW		 827};
828
829static int soc15_common_early_init(void *handle)
830{
88807dc8 831#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
220ab9bd
KW		 832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
833
88807dc8
OZ		 834 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
835 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
220ab9bd
KW		 836 adev->smc_rreg = NULL;
837 adev->smc_wreg = NULL;
838 adev->pcie_rreg = &soc15_pcie_rreg;
839 adev->pcie_wreg = &soc15_pcie_wreg;
840 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
841 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
842 adev->didt_rreg = &soc15_didt_rreg;
843 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 844 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
845 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 846 adev->se_cac_rreg = &soc15_se_cac_rreg;
847 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd 848
220ab9bd 849
220ab9bd
KW		 850 adev->external_rev_id = 0xFF;
851 switch (adev->asic_type) {
852 case CHIP_VEGA10:
c93aa775 853 adev->asic_funcs = &soc15_asic_funcs;
220ab9bd
KW		 854 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
855 AMD_CG_SUPPORT_GFX_MGLS |
856 AMD_CG_SUPPORT_GFX_RLC_LS |
857 AMD_CG_SUPPORT_GFX_CP_LS |
858 AMD_CG_SUPPORT_GFX_3D_CGCG |
859 AMD_CG_SUPPORT_GFX_3D_CGLS |
860 AMD_CG_SUPPORT_GFX_CGCG |
861 AMD_CG_SUPPORT_GFX_CGLS |
862 AMD_CG_SUPPORT_BIF_MGCG |
863 AMD_CG_SUPPORT_BIF_LS |
864 AMD_CG_SUPPORT_HDP_LS |
865 AMD_CG_SUPPORT_DRM_MGCG |
866 AMD_CG_SUPPORT_DRM_LS |
867 AMD_CG_SUPPORT_ROM_MGCG |
868 AMD_CG_SUPPORT_DF_MGCG |
869 AMD_CG_SUPPORT_SDMA_MGCG |
870 AMD_CG_SUPPORT_SDMA_LS |
871 AMD_CG_SUPPORT_MC_MGCG |
872 AMD_CG_SUPPORT_MC_LS;
873 adev->pg_flags = 0;
874 adev->external_rev_id = 0x1;
875 break;
692069a1 876 case CHIP_VEGA12:
c93aa775 877 adev->asic_funcs = &soc15_asic_funcs;
e4a38755
EQ		 878 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
879 AMD_CG_SUPPORT_GFX_MGLS |
880 AMD_CG_SUPPORT_GFX_CGCG |
881 AMD_CG_SUPPORT_GFX_CGLS |
882 AMD_CG_SUPPORT_GFX_3D_CGCG |
883 AMD_CG_SUPPORT_GFX_3D_CGLS |
884 AMD_CG_SUPPORT_GFX_CP_LS |
885 AMD_CG_SUPPORT_MC_LS |
886 AMD_CG_SUPPORT_MC_MGCG |
887 AMD_CG_SUPPORT_SDMA_MGCG |
888 AMD_CG_SUPPORT_SDMA_LS |
889 AMD_CG_SUPPORT_BIF_MGCG |
890 AMD_CG_SUPPORT_BIF_LS |
891 AMD_CG_SUPPORT_HDP_MGCG |
892 AMD_CG_SUPPORT_HDP_LS |
893 AMD_CG_SUPPORT_ROM_MGCG |
894 AMD_CG_SUPPORT_VCE_MGCG |
895 AMD_CG_SUPPORT_UVD_MGCG;
692069a1 896 adev->pg_flags = 0;
f559fe2b 897 adev->external_rev_id = adev->rev_id + 0x14;
692069a1 898 break;
935be7a0 899 case CHIP_VEGA20:
c93aa775 900 adev->asic_funcs = &vega20_asic_funcs;
3fdbab5f
EQ		 901 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
902 AMD_CG_SUPPORT_GFX_MGLS |
903 AMD_CG_SUPPORT_GFX_CGCG |
904 AMD_CG_SUPPORT_GFX_CGLS |
905 AMD_CG_SUPPORT_GFX_3D_CGCG |
906 AMD_CG_SUPPORT_GFX_3D_CGLS |
907 AMD_CG_SUPPORT_GFX_CP_LS |
908 AMD_CG_SUPPORT_MC_LS |
909 AMD_CG_SUPPORT_MC_MGCG |
910 AMD_CG_SUPPORT_SDMA_MGCG |
911 AMD_CG_SUPPORT_SDMA_LS |
912 AMD_CG_SUPPORT_BIF_MGCG |
913 AMD_CG_SUPPORT_BIF_LS |
914 AMD_CG_SUPPORT_HDP_MGCG |
102e4940 915 AMD_CG_SUPPORT_HDP_LS |
3fdbab5f
EQ		 916 AMD_CG_SUPPORT_ROM_MGCG |
917 AMD_CG_SUPPORT_VCE_MGCG |
918 AMD_CG_SUPPORT_UVD_MGCG;
935be7a0
FX		 919 adev->pg_flags = 0;
920 adev->external_rev_id = adev->rev_id + 0x28;
921 break;
957c6fe1 922 case CHIP_RAVEN:
c93aa775 923 adev->asic_funcs = &soc15_asic_funcs;
520cbe0f 924 if (adev->rev_id >= 0x8)
7e4545d3 925 adev->external_rev_id = adev->rev_id + 0x79;
741deade
AD		 926 else if (adev->pdev->device == 0x15d8)
927 adev->external_rev_id = adev->rev_id + 0x41;
7e4545d3
HR		 928 else if (adev->rev_id == 1)
929 adev->external_rev_id = adev->rev_id + 0x20;
741deade 930 else
7e4545d3 931 adev->external_rev_id = adev->rev_id + 0x01;
741deade
AD		 932
933 if (adev->rev_id >= 0x8) {
520cbe0f
HR		 934 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
935 AMD_CG_SUPPORT_GFX_MGLS |
936 AMD_CG_SUPPORT_GFX_CP_LS |
937 AMD_CG_SUPPORT_GFX_3D_CGCG |
938 AMD_CG_SUPPORT_GFX_3D_CGLS |
939 AMD_CG_SUPPORT_GFX_CGCG |
940 AMD_CG_SUPPORT_GFX_CGLS |
941 AMD_CG_SUPPORT_BIF_LS |
942 AMD_CG_SUPPORT_HDP_LS |
943 AMD_CG_SUPPORT_ROM_MGCG |
944 AMD_CG_SUPPORT_MC_MGCG |
945 AMD_CG_SUPPORT_MC_LS |
946 AMD_CG_SUPPORT_SDMA_MGCG |
947 AMD_CG_SUPPORT_SDMA_LS |
948 AMD_CG_SUPPORT_VCN_MGCG;
741deade
AD		 949
950 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
951 } else if (adev->pdev->device == 0x15d8) {
fced5c70
LG		 952 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
953 AMD_CG_SUPPORT_GFX_MGLS |
741deade
AD		 954 AMD_CG_SUPPORT_GFX_CP_LS |
955 AMD_CG_SUPPORT_GFX_3D_CGCG |
956 AMD_CG_SUPPORT_GFX_3D_CGLS |
957 AMD_CG_SUPPORT_GFX_CGCG |
958 AMD_CG_SUPPORT_GFX_CGLS |
959 AMD_CG_SUPPORT_BIF_LS |
960 AMD_CG_SUPPORT_HDP_LS |
961 AMD_CG_SUPPORT_ROM_MGCG |
962 AMD_CG_SUPPORT_MC_MGCG |
963 AMD_CG_SUPPORT_MC_LS |
964 AMD_CG_SUPPORT_SDMA_MGCG |
965 AMD_CG_SUPPORT_SDMA_LS;
966
967 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
968 AMD_PG_SUPPORT_MMHUB |
a3716d3a
JZ		 969 AMD_PG_SUPPORT_VCN |
970 AMD_PG_SUPPORT_VCN_DPG;
741deade 971 } else {
520cbe0f
HR		 972 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
973 AMD_CG_SUPPORT_GFX_MGLS |
974 AMD_CG_SUPPORT_GFX_RLC_LS |
975 AMD_CG_SUPPORT_GFX_CP_LS |
976 AMD_CG_SUPPORT_GFX_3D_CGCG |
977 AMD_CG_SUPPORT_GFX_3D_CGLS |
978 AMD_CG_SUPPORT_GFX_CGCG |
979 AMD_CG_SUPPORT_GFX_CGLS |
980 AMD_CG_SUPPORT_BIF_MGCG |
981 AMD_CG_SUPPORT_BIF_LS |
982 AMD_CG_SUPPORT_HDP_MGCG |
983 AMD_CG_SUPPORT_HDP_LS |
984 AMD_CG_SUPPORT_DRM_MGCG |
985 AMD_CG_SUPPORT_DRM_LS |
986 AMD_CG_SUPPORT_ROM_MGCG |
987 AMD_CG_SUPPORT_MC_MGCG |
988 AMD_CG_SUPPORT_MC_LS |
989 AMD_CG_SUPPORT_SDMA_MGCG |
990 AMD_CG_SUPPORT_SDMA_LS |
991 AMD_CG_SUPPORT_VCN_MGCG;
61c8e90d 992
741deade
AD		 993 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
994 }
a4494fda 995
3b94fb10 996 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
8c7bf583
KF		 997 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
998 AMD_PG_SUPPORT_CP |
999 AMD_PG_SUPPORT_RLC_SMU_HS;
ad5a67a7 1000 break;
220ab9bd
KW		 1001 default:
1002 /* FIXME: not supported yet */
1003 return -EINVAL;
1004 }
1005
ab276632
XY		 1006 if (amdgpu_sriov_vf(adev)) {
1007 amdgpu_virt_init_setting(adev);
1008 xgpu_ai_mailbox_set_irq_funcs(adev);
1009 }
1010
220ab9bd
KW		 1011 return 0;
1012}
1013
81758c55
ML		 1014static int soc15_common_late_init(void *handle)
1015{
1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1017
1018 if (amdgpu_sriov_vf(adev))
1019 xgpu_ai_mailbox_get_irq(adev);
1020
1021 return 0;
1022}
1023
220ab9bd
KW		 1024static int soc15_common_sw_init(void *handle)
1025{
81758c55
ML		 1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028 if (amdgpu_sriov_vf(adev))
1029 xgpu_ai_mailbox_add_irq_id(adev);
1030
220ab9bd
KW		 1031 return 0;
1032}
1033
1034static int soc15_common_sw_fini(void *handle)
1035{
1036 return 0;
1037}
1038
7c94bc82
OZ		 1039static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1040{
1041 int i;
1042 struct amdgpu_ring *ring;
1043
98cad2de
TH		 1044 /* Two reasons to skip
1045 * 1, Host driver already programmed them
1046 * 2, To avoid registers program violations in SR-IOV
1047 */
1048 if (!amdgpu_virt_support_skip_setting(adev)) {
1049 for (i = 0; i < adev->sdma.num_instances; i++) {
1050 ring = &adev->sdma.instance[i].ring;
1051 adev->nbio_funcs->sdma_doorbell_range(adev, i,
1052 ring->use_doorbell, ring->doorbell_index,
1053 adev->doorbell_index.sdma_doorbell_range);
1054 }
7c94bc82
OZ		 1055 }
1056
1057 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1058 adev->irq.ih.doorbell_index);
1059}
1060
220ab9bd
KW		 1061static int soc15_common_hw_init(void *handle)
1062{
1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1064
220ab9bd
KW		 1065 /* enable pcie gen2/3 link */
1066 soc15_pcie_gen3_enable(adev);
1067 /* enable aspm */
1068 soc15_program_aspm(adev);
833fa075 1069 /* setup nbio registers */
bf383fb6 1070 adev->nbio_funcs->init_registers(adev);
88807dc8
OZ		 1071 /* remap HDP registers to a hole in mmio space,
1072 * for the purpose of expose those registers
1073 * to process space
1074 */
1075 if (adev->nbio_funcs->remap_hdp_registers)
1076 adev->nbio_funcs->remap_hdp_registers(adev);
220ab9bd
KW		 1077 /* enable the doorbell aperture */
1078 soc15_enable_doorbell_aperture(adev, true);
7c94bc82
OZ		 1079 /* HW doorbell routing policy: doorbell writing not
1080 * in SDMA/IH/MM/ACV range will be routed to CP. So
1081 * we need to init SDMA/IH/MM/ACV doorbell range prior
1082 * to CP ip block init and ring test.
1083 */
1084 soc15_doorbell_range_init(adev);
220ab9bd
KW		 1085
1086 return 0;
1087}
1088
1089static int soc15_common_hw_fini(void *handle)
1090{
1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092
1093 /* disable the doorbell aperture */
1094 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 1095 if (amdgpu_sriov_vf(adev))
1096 xgpu_ai_mailbox_put_irq(adev);
220ab9bd
KW		 1097
1098 return 0;
1099}
1100
1101static int soc15_common_suspend(void *handle)
1102{
1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1104
1105 return soc15_common_hw_fini(adev);
1106}
1107
1108static int soc15_common_resume(void *handle)
1109{
1110 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111
1112 return soc15_common_hw_init(adev);
1113}
1114
1115static bool soc15_common_is_idle(void *handle)
1116{
1117 return true;
1118}
1119
1120static int soc15_common_wait_for_idle(void *handle)
1121{
1122 return 0;
1123}
1124
1125static int soc15_common_soft_reset(void *handle)
1126{
1127 return 0;
1128}
1129
1130static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1131{
1132 uint32_t def, data;
1133
a5d0f456
KF		 1134 if (adev->asic_type == CHIP_VEGA20) {
1135 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
220ab9bd 1136
a5d0f456
KF		 1137 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1138 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1139 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1140 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1141 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1142 else
1143 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1144 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1145 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1146 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
220ab9bd 1147
a5d0f456
KF		 1148 if (def != data)
1149 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1150 } else {
1151 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1152
1153 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1154 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1155 else
1156 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1157
1158 if (def != data)
1159 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1160 }
220ab9bd
KW		 1161}
1162
1163static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1164{
1165 uint32_t def, data;
1166
1167 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1168
1169 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1170 data &= ~(0x01000000 |
1171 0x02000000 |
1172 0x04000000 |
1173 0x08000000 |
1174 0x10000000 |
1175 0x20000000 |
1176 0x40000000 |
1177 0x80000000);
1178 else
1179 data |= (0x01000000 |
1180 0x02000000 |
1181 0x04000000 |
1182 0x08000000 |
1183 0x10000000 |
1184 0x20000000 |
1185 0x40000000 |
1186 0x80000000);
1187
1188 if (def != data)
1189 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1190}
1191
1192static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1193{
1194 uint32_t def, data;
1195
1196 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1197
1198 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1199 data |= 1;
1200 else
1201 data &= ~1;
1202
1203 if (def != data)
1204 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1205}
1206
1207static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1208 bool enable)
1209{
1210 uint32_t def, data;
1211
1212 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1213
1214 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1215 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1216 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1217 else
1218 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1219 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1220
1221 if (def != data)
1222 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1223}
1224
220ab9bd
KW		 1225static int soc15_common_set_clockgating_state(void *handle,
1226 enum amd_clockgating_state state)
1227{
1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229
6e9dc861
ML		 1230 if (amdgpu_sriov_vf(adev))
1231 return 0;
1232
220ab9bd
KW		 1233 switch (adev->asic_type) {
1234 case CHIP_VEGA10:
692069a1 1235 case CHIP_VEGA12:
f980d127 1236 case CHIP_VEGA20:
bf383fb6 1237 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
220ab9bd 1238 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1239 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 1240 state == AMD_CG_STATE_GATE ? true : false);
1241 soc15_update_hdp_light_sleep(adev,
1242 state == AMD_CG_STATE_GATE ? true : false);
1243 soc15_update_drm_clock_gating(adev,
1244 state == AMD_CG_STATE_GATE ? true : false);
1245 soc15_update_drm_light_sleep(adev,
1246 state == AMD_CG_STATE_GATE ? true : false);
1247 soc15_update_rom_medium_grain_clock_gating(adev,
1248 state == AMD_CG_STATE_GATE ? true : false);
070706c0 1249 adev->df_funcs->update_medium_grain_clock_gating(adev,
220ab9bd
KW		 1250 state == AMD_CG_STATE_GATE ? true : false);
1251 break;
9e5a9eb4 1252 case CHIP_RAVEN:
bf383fb6 1253 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 1254 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1255 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 1256 state == AMD_CG_STATE_GATE ? true : false);
1257 soc15_update_hdp_light_sleep(adev,
1258 state == AMD_CG_STATE_GATE ? true : false);
1259 soc15_update_drm_clock_gating(adev,
1260 state == AMD_CG_STATE_GATE ? true : false);
1261 soc15_update_drm_light_sleep(adev,
1262 state == AMD_CG_STATE_GATE ? true : false);
1263 soc15_update_rom_medium_grain_clock_gating(adev,
1264 state == AMD_CG_STATE_GATE ? true : false);
1265 break;
220ab9bd
KW		 1266 default:
1267 break;
1268 }
1269 return 0;
1270}
1271
f9abe35c
HR		 1272static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1273{
1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1275 int data;
1276
1277 if (amdgpu_sriov_vf(adev))
1278 *flags = 0;
1279
bf383fb6 1280 adev->nbio_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1281
1282 /* AMD_CG_SUPPORT_HDP_LS */
1283 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1284 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1285 *flags |= AMD_CG_SUPPORT_HDP_LS;
1286
1287 /* AMD_CG_SUPPORT_DRM_MGCG */
1288 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1289 if (!(data & 0x01000000))
1290 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1291
1292 /* AMD_CG_SUPPORT_DRM_LS */
1293 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1294 if (data & 0x1)
1295 *flags |= AMD_CG_SUPPORT_DRM_LS;
1296
1297 /* AMD_CG_SUPPORT_ROM_MGCG */
1298 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1299 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1300 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1301
070706c0 1302 adev->df_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1303}
1304
220ab9bd
KW		 1305static int soc15_common_set_powergating_state(void *handle,
1306 enum amd_powergating_state state)
1307{
1308 /* todo */
1309 return 0;
1310}
1311
1312const struct amd_ip_funcs soc15_common_ip_funcs = {
1313 .name = "soc15_common",
1314 .early_init = soc15_common_early_init,
81758c55 1315 .late_init = soc15_common_late_init,
220ab9bd
KW		 1316 .sw_init = soc15_common_sw_init,
1317 .sw_fini = soc15_common_sw_fini,
1318 .hw_init = soc15_common_hw_init,
1319 .hw_fini = soc15_common_hw_fini,
1320 .suspend = soc15_common_suspend,
1321 .resume = soc15_common_resume,
1322 .is_idle = soc15_common_is_idle,
1323 .wait_for_idle = soc15_common_wait_for_idle,
1324 .soft_reset = soc15_common_soft_reset,
1325 .set_clockgating_state = soc15_common_set_clockgating_state,
1326 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 1327 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 1328};
Linux 6.x block layer and io_uring tree(s)