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220ab9bd KW |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/module.h> | |
47b757fb SR |
26 | #include <linux/pci.h> |
27 | ||
6f786950 AD |
28 | #include <drm/amdgpu_drm.h> |
29 | ||
220ab9bd | 30 | #include "amdgpu.h" |
d05da0e2 | 31 | #include "amdgpu_atombios.h" |
220ab9bd KW |
32 | #include "amdgpu_ih.h" |
33 | #include "amdgpu_uvd.h" | |
34 | #include "amdgpu_vce.h" | |
35 | #include "amdgpu_ucode.h" | |
36 | #include "amdgpu_psp.h" | |
37 | #include "atom.h" | |
38 | #include "amd_pcie.h" | |
39 | ||
5d735f83 | 40 | #include "uvd/uvd_7_0_offset.h" |
cde5c34f FX |
41 | #include "gc/gc_9_0_offset.h" |
42 | #include "gc/gc_9_0_sh_mask.h" | |
812f77b7 FX |
43 | #include "sdma0/sdma0_4_0_offset.h" |
44 | #include "sdma1/sdma1_4_0_offset.h" | |
b45e18ac | 45 | #include "nbio/nbio_7_0_default.h" |
88807dc8 | 46 | #include "nbio/nbio_7_0_offset.h" |
b45e18ac KR |
47 | #include "nbio/nbio_7_0_sh_mask.h" |
48 | #include "nbio/nbio_7_0_smn.h" | |
9281f12c | 49 | #include "mp/mp_9_0_offset.h" |
220ab9bd KW |
50 | |
51 | #include "soc15.h" | |
52 | #include "soc15_common.h" | |
53 | #include "gfx_v9_0.h" | |
54 | #include "gmc_v9_0.h" | |
55 | #include "gfxhub_v1_0.h" | |
56 | #include "mmhub_v1_0.h" | |
070706c0 | 57 | #include "df_v1_7.h" |
698758bb | 58 | #include "df_v3_6.h" |
bebc0762 HZ |
59 | #include "nbio_v6_1.h" |
60 | #include "nbio_v7_0.h" | |
61 | #include "nbio_v7_4.h" | |
455d40c9 | 62 | #include "hdp_v4_0.h" |
220ab9bd | 63 | #include "vega10_ih.h" |
320a2e0c | 64 | #include "vega20_ih.h" |
c1059360 | 65 | #include "navi10_ih.h" |
220ab9bd KW |
66 | #include "sdma_v4_0.h" |
67 | #include "uvd_v7_0.h" | |
68 | #include "vce_v4_0.h" | |
f2d7e707 | 69 | #include "vcn_v1_0.h" |
279ba48e | 70 | #include "vcn_v2_0.h" |
5be45a26 | 71 | #include "jpeg_v2_0.h" |
08249a3a | 72 | #include "vcn_v2_5.h" |
8c74e590 | 73 | #include "jpeg_v2_5.h" |
0e961589 HZ |
74 | #include "smuio_v9_0.h" |
75 | #include "smuio_v11_0.h" | |
7914a0cd | 76 | #include "smuio_v13_0.h" |
796b6568 | 77 | #include "dce_virtual.h" |
f1a34465 | 78 | #include "mxgpu_ai.h" |
e74609cb AD |
79 | #include "amdgpu_ras.h" |
80 | #include "amdgpu_xgmi.h" | |
88807dc8 | 81 | #include <uapi/linux/kfd_ioctl.h> |
220ab9bd | 82 | |
220ab9bd KW |
83 | #define mmMP0_MISC_CGTT_CTRL0 0x01b9 |
84 | #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 | |
85 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba | |
86 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 | |
87 | ||
3b246e8b AD |
88 | /* Vega, Raven, Arcturus */ |
89 | static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = | |
90 | { | |
91 | { | |
6f786950 | 92 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
93 | .max_width = 4096, |
94 | .max_height = 2304, | |
95 | .max_pixels_per_frame = 4096 * 2304, | |
96 | .max_level = 0, | |
97 | }, | |
98 | { | |
6f786950 | 99 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
100 | .max_width = 4096, |
101 | .max_height = 2304, | |
102 | .max_pixels_per_frame = 4096 * 2304, | |
103 | .max_level = 0, | |
104 | }, | |
105 | }; | |
106 | ||
107 | static const struct amdgpu_video_codecs vega_video_codecs_encode = | |
108 | { | |
109 | .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), | |
110 | .codec_array = vega_video_codecs_encode_array, | |
111 | }; | |
112 | ||
113 | /* Vega */ | |
114 | static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = | |
115 | { | |
116 | { | |
6f786950 | 117 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
118 | .max_width = 4096, |
119 | .max_height = 4096, | |
120 | .max_pixels_per_frame = 4096 * 4096, | |
121 | .max_level = 3, | |
122 | }, | |
123 | { | |
6f786950 | 124 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
125 | .max_width = 4096, |
126 | .max_height = 4096, | |
127 | .max_pixels_per_frame = 4096 * 4096, | |
128 | .max_level = 5, | |
129 | }, | |
130 | { | |
6f786950 | 131 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
132 | .max_width = 4096, |
133 | .max_height = 4096, | |
134 | .max_pixels_per_frame = 4096 * 4096, | |
135 | .max_level = 52, | |
136 | }, | |
137 | { | |
6f786950 | 138 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
139 | .max_width = 4096, |
140 | .max_height = 4096, | |
141 | .max_pixels_per_frame = 4096 * 4096, | |
142 | .max_level = 4, | |
143 | }, | |
144 | { | |
6f786950 | 145 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
146 | .max_width = 4096, |
147 | .max_height = 4096, | |
148 | .max_pixels_per_frame = 4096 * 4096, | |
149 | .max_level = 186, | |
150 | }, | |
151 | { | |
6f786950 | 152 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
153 | .max_width = 4096, |
154 | .max_height = 4096, | |
155 | .max_pixels_per_frame = 4096 * 4096, | |
156 | .max_level = 0, | |
157 | }, | |
158 | }; | |
159 | ||
160 | static const struct amdgpu_video_codecs vega_video_codecs_decode = | |
161 | { | |
162 | .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), | |
163 | .codec_array = vega_video_codecs_decode_array, | |
164 | }; | |
165 | ||
166 | /* Raven */ | |
167 | static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = | |
168 | { | |
169 | { | |
6f786950 | 170 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
171 | .max_width = 4096, |
172 | .max_height = 4096, | |
173 | .max_pixels_per_frame = 4096 * 4096, | |
174 | .max_level = 3, | |
175 | }, | |
176 | { | |
6f786950 | 177 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
178 | .max_width = 4096, |
179 | .max_height = 4096, | |
180 | .max_pixels_per_frame = 4096 * 4096, | |
181 | .max_level = 5, | |
182 | }, | |
183 | { | |
6f786950 | 184 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
185 | .max_width = 4096, |
186 | .max_height = 4096, | |
187 | .max_pixels_per_frame = 4096 * 4096, | |
188 | .max_level = 52, | |
189 | }, | |
190 | { | |
6f786950 | 191 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
192 | .max_width = 4096, |
193 | .max_height = 4096, | |
194 | .max_pixels_per_frame = 4096 * 4096, | |
195 | .max_level = 4, | |
196 | }, | |
197 | { | |
6f786950 | 198 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
199 | .max_width = 4096, |
200 | .max_height = 4096, | |
201 | .max_pixels_per_frame = 4096 * 4096, | |
202 | .max_level = 186, | |
203 | }, | |
204 | { | |
6f786950 | 205 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
206 | .max_width = 4096, |
207 | .max_height = 4096, | |
208 | .max_pixels_per_frame = 4096 * 4096, | |
209 | .max_level = 0, | |
210 | }, | |
211 | { | |
6f786950 | 212 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, |
3b246e8b AD |
213 | .max_width = 4096, |
214 | .max_height = 4096, | |
215 | .max_pixels_per_frame = 4096 * 4096, | |
216 | .max_level = 0, | |
217 | }, | |
218 | }; | |
219 | ||
220 | static const struct amdgpu_video_codecs rv_video_codecs_decode = | |
221 | { | |
222 | .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), | |
223 | .codec_array = rv_video_codecs_decode_array, | |
224 | }; | |
225 | ||
226 | /* Renoir, Arcturus */ | |
227 | static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = | |
228 | { | |
229 | { | |
6f786950 | 230 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
231 | .max_width = 4096, |
232 | .max_height = 4096, | |
233 | .max_pixels_per_frame = 4096 * 4096, | |
234 | .max_level = 3, | |
235 | }, | |
236 | { | |
6f786950 | 237 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
238 | .max_width = 4096, |
239 | .max_height = 4096, | |
240 | .max_pixels_per_frame = 4096 * 4096, | |
241 | .max_level = 5, | |
242 | }, | |
243 | { | |
6f786950 | 244 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
245 | .max_width = 4096, |
246 | .max_height = 4096, | |
247 | .max_pixels_per_frame = 4096 * 4096, | |
248 | .max_level = 52, | |
249 | }, | |
250 | { | |
6f786950 | 251 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
252 | .max_width = 4096, |
253 | .max_height = 4096, | |
254 | .max_pixels_per_frame = 4096 * 4096, | |
255 | .max_level = 4, | |
256 | }, | |
257 | { | |
6f786950 | 258 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
259 | .max_width = 8192, |
260 | .max_height = 4352, | |
261 | .max_pixels_per_frame = 4096 * 4096, | |
262 | .max_level = 186, | |
263 | }, | |
264 | { | |
6f786950 | 265 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
266 | .max_width = 4096, |
267 | .max_height = 4096, | |
268 | .max_pixels_per_frame = 4096 * 4096, | |
269 | .max_level = 0, | |
270 | }, | |
271 | { | |
6f786950 | 272 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, |
3b246e8b AD |
273 | .max_width = 8192, |
274 | .max_height = 4352, | |
275 | .max_pixels_per_frame = 4096 * 4096, | |
276 | .max_level = 0, | |
277 | }, | |
278 | }; | |
279 | ||
280 | static const struct amdgpu_video_codecs rn_video_codecs_decode = | |
281 | { | |
282 | .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), | |
283 | .codec_array = rn_video_codecs_decode_array, | |
284 | }; | |
285 | ||
286 | static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, | |
287 | const struct amdgpu_video_codecs **codecs) | |
288 | { | |
289 | switch (adev->asic_type) { | |
290 | case CHIP_VEGA20: | |
291 | case CHIP_VEGA10: | |
292 | case CHIP_VEGA12: | |
293 | if (encode) | |
294 | *codecs = &vega_video_codecs_encode; | |
295 | else | |
296 | *codecs = &vega_video_codecs_decode; | |
297 | return 0; | |
298 | case CHIP_RAVEN: | |
299 | if (encode) | |
300 | *codecs = &vega_video_codecs_encode; | |
301 | else | |
302 | *codecs = &rv_video_codecs_decode; | |
303 | return 0; | |
304 | case CHIP_ARCTURUS: | |
295c4f51 | 305 | case CHIP_ALDEBARAN: |
3b246e8b AD |
306 | case CHIP_RENOIR: |
307 | if (encode) | |
308 | *codecs = &vega_video_codecs_encode; | |
309 | else | |
310 | *codecs = &rn_video_codecs_decode; | |
311 | return 0; | |
312 | default: | |
313 | return -EINVAL; | |
314 | } | |
315 | } | |
316 | ||
220ab9bd KW |
317 | /* |
318 | * Indirect registers accessor | |
319 | */ | |
320 | static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) | |
321 | { | |
705a2b5b | 322 | unsigned long address, data; |
bebc0762 HZ |
323 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
324 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
220ab9bd | 325 | |
705a2b5b | 326 | return amdgpu_device_indirect_rreg(adev, address, data, reg); |
220ab9bd KW |
327 | } |
328 | ||
329 | static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
330 | { | |
705a2b5b | 331 | unsigned long address, data; |
220ab9bd | 332 | |
bebc0762 HZ |
333 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
334 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
220ab9bd | 335 | |
705a2b5b | 336 | amdgpu_device_indirect_wreg(adev, address, data, reg, v); |
220ab9bd KW |
337 | } |
338 | ||
4fa1c6a6 TZ |
339 | static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) |
340 | { | |
705a2b5b | 341 | unsigned long address, data; |
bebc0762 HZ |
342 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
343 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
4fa1c6a6 | 344 | |
705a2b5b | 345 | return amdgpu_device_indirect_rreg64(adev, address, data, reg); |
4fa1c6a6 TZ |
346 | } |
347 | ||
348 | static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) | |
349 | { | |
705a2b5b | 350 | unsigned long address, data; |
4fa1c6a6 | 351 | |
bebc0762 HZ |
352 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
353 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
4fa1c6a6 | 354 | |
705a2b5b | 355 | amdgpu_device_indirect_wreg64(adev, address, data, reg, v); |
4fa1c6a6 TZ |
356 | } |
357 | ||
220ab9bd KW |
358 | static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) |
359 | { | |
360 | unsigned long flags, address, data; | |
361 | u32 r; | |
362 | ||
363 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); | |
364 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); | |
365 | ||
366 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); | |
367 | WREG32(address, ((reg) & 0x1ff)); | |
368 | r = RREG32(data); | |
369 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); | |
370 | return r; | |
371 | } | |
372 | ||
373 | static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
374 | { | |
375 | unsigned long flags, address, data; | |
376 | ||
377 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); | |
378 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); | |
379 | ||
380 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); | |
381 | WREG32(address, ((reg) & 0x1ff)); | |
382 | WREG32(data, (v)); | |
383 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); | |
384 | } | |
385 | ||
386 | static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) | |
387 | { | |
388 | unsigned long flags, address, data; | |
389 | u32 r; | |
390 | ||
391 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); | |
392 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); | |
393 | ||
394 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
395 | WREG32(address, (reg)); | |
396 | r = RREG32(data); | |
397 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
398 | return r; | |
399 | } | |
400 | ||
401 | static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
402 | { | |
403 | unsigned long flags, address, data; | |
404 | ||
405 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); | |
406 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); | |
407 | ||
408 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
409 | WREG32(address, (reg)); | |
410 | WREG32(data, (v)); | |
411 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
412 | } | |
413 | ||
560460f2 EQ |
414 | static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) |
415 | { | |
416 | unsigned long flags; | |
417 | u32 r; | |
418 | ||
419 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); | |
420 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); | |
421 | r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); | |
422 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); | |
423 | return r; | |
424 | } | |
425 | ||
426 | static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
427 | { | |
428 | unsigned long flags; | |
429 | ||
430 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); | |
431 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); | |
432 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); | |
433 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); | |
434 | } | |
435 | ||
2f11fb02 EQ |
436 | static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) |
437 | { | |
438 | unsigned long flags; | |
439 | u32 r; | |
440 | ||
441 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); | |
442 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); | |
443 | r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); | |
444 | spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); | |
445 | return r; | |
446 | } | |
447 | ||
448 | static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
449 | { | |
450 | unsigned long flags; | |
451 | ||
452 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); | |
453 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); | |
454 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); | |
455 | spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); | |
456 | } | |
457 | ||
220ab9bd KW |
458 | static u32 soc15_get_config_memsize(struct amdgpu_device *adev) |
459 | { | |
bebc0762 | 460 | return adev->nbio.funcs->get_memsize(adev); |
220ab9bd KW |
461 | } |
462 | ||
220ab9bd KW |
463 | static u32 soc15_get_xclk(struct amdgpu_device *adev) |
464 | { | |
b90c4d66 AD |
465 | u32 reference_clock = adev->clock.spll.reference_freq; |
466 | ||
6e80fb8a AD |
467 | if (adev->asic_type == CHIP_RENOIR) |
468 | return 10000; | |
b90c4d66 AD |
469 | if (adev->asic_type == CHIP_RAVEN) |
470 | return reference_clock / 4; | |
471 | ||
472 | return reference_clock; | |
220ab9bd KW |
473 | } |
474 | ||
475 | ||
476 | void soc15_grbm_select(struct amdgpu_device *adev, | |
477 | u32 me, u32 pipe, u32 queue, u32 vmid) | |
478 | { | |
479 | u32 grbm_gfx_cntl = 0; | |
480 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); | |
481 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); | |
482 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); | |
483 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); | |
484 | ||
1bff7f6c | 485 | WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); |
220ab9bd KW |
486 | } |
487 | ||
488 | static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) | |
489 | { | |
490 | /* todo */ | |
491 | } | |
492 | ||
493 | static bool soc15_read_disabled_bios(struct amdgpu_device *adev) | |
494 | { | |
495 | /* todo */ | |
496 | return false; | |
497 | } | |
498 | ||
499 | static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, | |
500 | u8 *bios, u32 length_bytes) | |
501 | { | |
502 | u32 *dw_ptr; | |
503 | u32 i, length_dw; | |
1a0dd3d9 HZ |
504 | uint32_t rom_index_offset; |
505 | uint32_t rom_data_offset; | |
220ab9bd KW |
506 | |
507 | if (bios == NULL) | |
508 | return false; | |
509 | if (length_bytes == 0) | |
510 | return false; | |
511 | /* APU vbios image is part of sbios image */ | |
512 | if (adev->flags & AMD_IS_APU) | |
513 | return false; | |
514 | ||
515 | dw_ptr = (u32 *)bios; | |
516 | length_dw = ALIGN(length_bytes, 4) / 4; | |
517 | ||
0e961589 HZ |
518 | rom_index_offset = |
519 | adev->smuio.funcs->get_rom_index_offset(adev); | |
520 | rom_data_offset = | |
521 | adev->smuio.funcs->get_rom_data_offset(adev); | |
1a0dd3d9 | 522 | |
220ab9bd | 523 | /* set rom index to 0 */ |
1a0dd3d9 | 524 | WREG32(rom_index_offset, 0); |
220ab9bd KW |
525 | /* read out the rom data */ |
526 | for (i = 0; i < length_dw; i++) | |
1a0dd3d9 | 527 | dw_ptr[i] = RREG32(rom_data_offset); |
220ab9bd KW |
528 | |
529 | return true; | |
530 | } | |
531 | ||
946a4d5b SL |
532 | static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { |
533 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, | |
534 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, | |
535 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, | |
536 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, | |
537 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, | |
538 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, | |
539 | { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, | |
540 | { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, | |
541 | { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, | |
542 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, | |
543 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, | |
544 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, | |
545 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, | |
546 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, | |
547 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, | |
664fe85a | 548 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, |
946a4d5b SL |
549 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, |
550 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, | |
551 | { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, | |
5eeae247 | 552 | { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, |
220ab9bd KW |
553 | }; |
554 | ||
555 | static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, | |
556 | u32 sh_num, u32 reg_offset) | |
557 | { | |
558 | uint32_t val; | |
559 | ||
560 | mutex_lock(&adev->grbm_idx_mutex); | |
561 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
562 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); | |
563 | ||
564 | val = RREG32(reg_offset); | |
565 | ||
566 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
567 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
568 | mutex_unlock(&adev->grbm_idx_mutex); | |
569 | return val; | |
570 | } | |
571 | ||
c013cea2 AD |
572 | static uint32_t soc15_get_register_value(struct amdgpu_device *adev, |
573 | bool indexed, u32 se_num, | |
574 | u32 sh_num, u32 reg_offset) | |
575 | { | |
576 | if (indexed) { | |
577 | return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); | |
578 | } else { | |
cd29253f | 579 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) |
c013cea2 | 580 | return adev->gfx.config.gb_addr_config; |
5eeae247 AD |
581 | else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) |
582 | return adev->gfx.config.db_debug2; | |
cd29253f | 583 | return RREG32(reg_offset); |
c013cea2 AD |
584 | } |
585 | } | |
586 | ||
220ab9bd KW |
587 | static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, |
588 | u32 sh_num, u32 reg_offset, u32 *value) | |
589 | { | |
3032f350 | 590 | uint32_t i; |
946a4d5b | 591 | struct soc15_allowed_register_entry *en; |
220ab9bd KW |
592 | |
593 | *value = 0; | |
220ab9bd | 594 | for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { |
946a4d5b | 595 | en = &soc15_allowed_read_registers[i]; |
207f0f13 PL |
596 | if (adev->reg_offset[en->hwip][en->inst] && |
597 | reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] | |
946a4d5b | 598 | + en->reg_offset)) |
220ab9bd KW |
599 | continue; |
600 | ||
97fcc76b CK |
601 | *value = soc15_get_register_value(adev, |
602 | soc15_allowed_read_registers[i].grbm_indexed, | |
603 | se_num, sh_num, reg_offset); | |
220ab9bd KW |
604 | return 0; |
605 | } | |
606 | return -EINVAL; | |
607 | } | |
608 | ||
946a4d5b SL |
609 | |
610 | /** | |
611 | * soc15_program_register_sequence - program an array of registers. | |
612 | * | |
613 | * @adev: amdgpu_device pointer | |
614 | * @regs: pointer to the register array | |
615 | * @array_size: size of the register array | |
616 | * | |
617 | * Programs an array or registers with and and or masks. | |
618 | * This is a helper for setting golden registers. | |
619 | */ | |
620 | ||
621 | void soc15_program_register_sequence(struct amdgpu_device *adev, | |
622 | const struct soc15_reg_golden *regs, | |
623 | const u32 array_size) | |
624 | { | |
625 | const struct soc15_reg_golden *entry; | |
626 | u32 tmp, reg; | |
627 | int i; | |
628 | ||
629 | for (i = 0; i < array_size; ++i) { | |
630 | entry = ®s[i]; | |
631 | reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; | |
632 | ||
633 | if (entry->and_mask == 0xffffffff) { | |
634 | tmp = entry->or_mask; | |
635 | } else { | |
636 | tmp = RREG32(reg); | |
637 | tmp &= ~(entry->and_mask); | |
e0d07657 | 638 | tmp |= (entry->or_mask & entry->and_mask); |
946a4d5b | 639 | } |
1bff7f6c TH |
640 | |
641 | if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || | |
642 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || | |
643 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || | |
644 | reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) | |
645 | WREG32_RLC(reg, tmp); | |
646 | else | |
647 | WREG32(reg, tmp); | |
648 | ||
946a4d5b SL |
649 | } |
650 | ||
651 | } | |
652 | ||
e2b6d053 JQ |
653 | static int soc15_asic_baco_reset(struct amdgpu_device *adev) |
654 | { | |
956f6705 | 655 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 656 | int ret = 0; |
e2b6d053 | 657 | |
956f6705 | 658 | /* avoid NBIF got stuck when do RAS recovery in BACO reset */ |
8ab0d6f0 | 659 | if (ras && adev->ras_enabled) |
956f6705 LM |
660 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
661 | ||
9530273e EQ |
662 | ret = amdgpu_dpm_baco_reset(adev); |
663 | if (ret) | |
664 | return ret; | |
e2b6d053 | 665 | |
956f6705 | 666 | /* re-enable doorbell interrupt after BACO exit */ |
8ab0d6f0 | 667 | if (ras && adev->ras_enabled) |
956f6705 LM |
668 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
669 | ||
e2b6d053 JQ |
670 | return 0; |
671 | } | |
672 | ||
ee360c0b AD |
673 | static enum amd_reset_method |
674 | soc15_asic_reset_method(struct amdgpu_device *adev) | |
e2b6d053 | 675 | { |
feffbaac | 676 | bool baco_reset = false; |
5c03e584 | 677 | bool connected_to_cpu = false; |
feffbaac | 678 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
e2b6d053 | 679 | |
5c03e584 FX |
680 | if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) |
681 | connected_to_cpu = true; | |
682 | ||
273da6ff WS |
683 | if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || |
684 | amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || | |
1176a1e0 | 685 | amdgpu_reset_method == AMD_RESET_METHOD_BACO || |
5c03e584 FX |
686 | amdgpu_reset_method == AMD_RESET_METHOD_PCI) { |
687 | /* If connected to cpu, driver only support mode2 */ | |
688 | if (connected_to_cpu) | |
689 | return AMD_RESET_METHOD_MODE2; | |
690 | return amdgpu_reset_method; | |
691 | } | |
273da6ff WS |
692 | |
693 | if (amdgpu_reset_method != -1) | |
694 | dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", | |
695 | amdgpu_reset_method); | |
696 | ||
e2b6d053 | 697 | switch (adev->asic_type) { |
ee360c0b | 698 | case CHIP_RAVEN: |
90a08351 | 699 | case CHIP_RENOIR: |
ee360c0b | 700 | return AMD_RESET_METHOD_MODE2; |
e2b6d053 | 701 | case CHIP_VEGA10: |
f8b18cf4 | 702 | case CHIP_VEGA12: |
0a650c1d | 703 | case CHIP_ARCTURUS: |
9530273e | 704 | baco_reset = amdgpu_dpm_is_baco_supported(adev); |
e2b6d053 | 705 | break; |
017d75f1 EQ |
706 | case CHIP_VEGA20: |
707 | if (adev->psp.sos_fw_version >= 0x80067) | |
9530273e | 708 | baco_reset = amdgpu_dpm_is_baco_supported(adev); |
e74609cb | 709 | |
feffbaac LM |
710 | /* |
711 | * 1. PMFW version > 0x284300: all cases use baco | |
712 | * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco | |
713 | */ | |
8ab0d6f0 | 714 | if (ras && adev->ras_enabled && |
acdae216 | 715 | adev->pm.fw_version <= 0x283400) |
feffbaac | 716 | baco_reset = false; |
017d75f1 | 717 | break; |
5c03e584 FX |
718 | case CHIP_ALDEBARAN: |
719 | /* | |
720 | * 1.connected to cpu: driver issue mode2 reset | |
721 | * 2.discret gpu: driver issue mode1 reset | |
722 | */ | |
723 | if (connected_to_cpu) | |
724 | return AMD_RESET_METHOD_MODE2; | |
725 | break; | |
e2b6d053 | 726 | default: |
e2b6d053 JQ |
727 | break; |
728 | } | |
729 | ||
730 | if (baco_reset) | |
ee360c0b AD |
731 | return AMD_RESET_METHOD_BACO; |
732 | else | |
733 | return AMD_RESET_METHOD_MODE1; | |
734 | } | |
735 | ||
736 | static int soc15_asic_reset(struct amdgpu_device *adev) | |
737 | { | |
276cc929 | 738 | /* original raven doesn't have full asic reset */ |
54f78a76 AD |
739 | if ((adev->apu_flags & AMD_APU_IS_RAVEN) && |
740 | !(adev->apu_flags & AMD_APU_IS_RAVEN2)) | |
276cc929 AD |
741 | return 0; |
742 | ||
c43b849f | 743 | switch (soc15_asic_reset_method(adev)) { |
1176a1e0 AD |
744 | case AMD_RESET_METHOD_PCI: |
745 | dev_info(adev->dev, "PCI reset\n"); | |
746 | return amdgpu_device_pci_reset(adev); | |
747 | case AMD_RESET_METHOD_BACO: | |
748 | dev_info(adev->dev, "BACO reset\n"); | |
749 | return soc15_asic_baco_reset(adev); | |
750 | case AMD_RESET_METHOD_MODE2: | |
751 | dev_info(adev->dev, "MODE2 reset\n"); | |
752 | return amdgpu_dpm_mode2_reset(adev); | |
753 | default: | |
754 | dev_info(adev->dev, "MODE1 reset\n"); | |
5c03e584 | 755 | return amdgpu_device_mode1_reset(adev); |
c43b849f | 756 | } |
e2b6d053 JQ |
757 | } |
758 | ||
988eb9ff AD |
759 | static bool soc15_supports_baco(struct amdgpu_device *adev) |
760 | { | |
988eb9ff AD |
761 | switch (adev->asic_type) { |
762 | case CHIP_VEGA10: | |
763 | case CHIP_VEGA12: | |
b8ab58f3 | 764 | case CHIP_ARCTURUS: |
9530273e | 765 | return amdgpu_dpm_is_baco_supported(adev); |
988eb9ff AD |
766 | case CHIP_VEGA20: |
767 | if (adev->psp.sos_fw_version >= 0x80067) | |
9530273e EQ |
768 | return amdgpu_dpm_is_baco_supported(adev); |
769 | return false; | |
988eb9ff AD |
770 | default: |
771 | return false; | |
772 | } | |
988eb9ff AD |
773 | } |
774 | ||
220ab9bd KW |
775 | /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, |
776 | u32 cntl_reg, u32 status_reg) | |
777 | { | |
778 | return 0; | |
779 | }*/ | |
780 | ||
781 | static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) | |
782 | { | |
783 | /*int r; | |
784 | ||
785 | r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); | |
786 | if (r) | |
787 | return r; | |
788 | ||
789 | r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); | |
790 | */ | |
791 | return 0; | |
792 | } | |
793 | ||
794 | static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) | |
795 | { | |
796 | /* todo */ | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) | |
802 | { | |
803 | if (pci_is_root_bus(adev->pdev->bus)) | |
804 | return; | |
805 | ||
806 | if (amdgpu_pcie_gen2 == 0) | |
807 | return; | |
808 | ||
809 | if (adev->flags & AMD_IS_APU) | |
810 | return; | |
811 | ||
812 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
813 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) | |
814 | return; | |
815 | ||
816 | /* todo */ | |
817 | } | |
818 | ||
819 | static void soc15_program_aspm(struct amdgpu_device *adev) | |
820 | { | |
0064b0ce | 821 | if (!amdgpu_aspm) |
220ab9bd KW |
822 | return; |
823 | ||
9d015c0d KF |
824 | if (!(adev->flags & AMD_IS_APU) && |
825 | (adev->nbio.funcs->program_aspm)) | |
826 | adev->nbio.funcs->program_aspm(adev); | |
220ab9bd KW |
827 | } |
828 | ||
829 | static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, | |
bf383fb6 | 830 | bool enable) |
220ab9bd | 831 | { |
bebc0762 HZ |
832 | adev->nbio.funcs->enable_doorbell_aperture(adev, enable); |
833 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); | |
220ab9bd KW |
834 | } |
835 | ||
836 | static const struct amdgpu_ip_block_version vega10_common_ip_block = | |
837 | { | |
838 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
839 | .major = 2, | |
840 | .minor = 0, | |
841 | .rev = 0, | |
842 | .funcs = &soc15_common_ip_funcs, | |
843 | }; | |
844 | ||
4cb0becb HR |
845 | static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) |
846 | { | |
bebc0762 | 847 | return adev->nbio.funcs->get_rev_id(adev); |
4cb0becb HR |
848 | } |
849 | ||
d95f09ac | 850 | static void soc15_reg_base_init(struct amdgpu_device *adev) |
220ab9bd | 851 | { |
c1cf79ca AD |
852 | int r; |
853 | ||
4522824c SL |
854 | /* Set IP register base before any HW register access */ |
855 | switch (adev->asic_type) { | |
856 | case CHIP_VEGA10: | |
3084eb00 | 857 | case CHIP_VEGA12: |
4522824c SL |
858 | case CHIP_RAVEN: |
859 | vega10_reg_base_init(adev); | |
860 | break; | |
c1cf79ca | 861 | case CHIP_RENOIR: |
d95f09ac WS |
862 | /* It's safe to do ip discovery here for Renior, |
863 | * it doesn't support SRIOV. */ | |
c1cf79ca AD |
864 | if (amdgpu_discovery) { |
865 | r = amdgpu_discovery_reg_base_init(adev); | |
2ae78708 DG |
866 | if (r == 0) |
867 | break; | |
868 | DRM_WARN("failed to init reg base from ip discovery table, " | |
869 | "fallback to legacy init method\n"); | |
c1cf79ca | 870 | } |
2ae78708 | 871 | vega10_reg_base_init(adev); |
c1cf79ca | 872 | break; |
8ee273e5 FX |
873 | case CHIP_VEGA20: |
874 | vega20_reg_base_init(adev); | |
875 | break; | |
e78705ec LM |
876 | case CHIP_ARCTURUS: |
877 | arct_reg_base_init(adev); | |
878 | break; | |
42b72608 LM |
879 | case CHIP_ALDEBARAN: |
880 | aldebaran_reg_base_init(adev); | |
881 | break; | |
4522824c | 882 | default: |
d95f09ac WS |
883 | DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); |
884 | break; | |
4522824c | 885 | } |
d95f09ac WS |
886 | } |
887 | ||
888 | void soc15_set_virt_ops(struct amdgpu_device *adev) | |
889 | { | |
890 | adev->virt.ops = &xgpu_ai_virt_ops; | |
891 | ||
892 | /* init soc15 reg base early enough so we can | |
893 | * request request full access for sriov before | |
894 | * set_ip_blocks. */ | |
895 | soc15_reg_base_init(adev); | |
896 | } | |
897 | ||
898 | int soc15_set_ip_blocks(struct amdgpu_device *adev) | |
899 | { | |
900 | /* for bare metal case */ | |
901 | if (!amdgpu_sriov_vf(adev)) | |
902 | soc15_reg_base_init(adev); | |
4522824c | 903 | |
bebc0762 HZ |
904 | if (adev->flags & AMD_IS_APU) { |
905 | adev->nbio.funcs = &nbio_v7_0_funcs; | |
906 | adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; | |
907 | } else if (adev->asic_type == CHIP_VEGA20 || | |
7906af5e LM |
908 | adev->asic_type == CHIP_ARCTURUS || |
909 | adev->asic_type == CHIP_ALDEBARAN) { | |
bebc0762 HZ |
910 | adev->nbio.funcs = &nbio_v7_4_funcs; |
911 | adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; | |
912 | } else { | |
913 | adev->nbio.funcs = &nbio_v6_1_funcs; | |
914 | adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; | |
915 | } | |
455d40c9 | 916 | adev->hdp.funcs = &hdp_v4_0_funcs; |
bf383fb6 | 917 | |
7906af5e LM |
918 | if (adev->asic_type == CHIP_VEGA20 || |
919 | adev->asic_type == CHIP_ARCTURUS || | |
920 | adev->asic_type == CHIP_ALDEBARAN) | |
bdf84a80 | 921 | adev->df.funcs = &df_v3_6_funcs; |
698758bb | 922 | else |
bdf84a80 | 923 | adev->df.funcs = &df_v1_7_funcs; |
4cb0becb | 924 | |
0e961589 HZ |
925 | if (adev->asic_type == CHIP_VEGA20 || |
926 | adev->asic_type == CHIP_ARCTURUS) | |
927 | adev->smuio.funcs = &smuio_v11_0_funcs; | |
7914a0cd HZ |
928 | else if (adev->asic_type == CHIP_ALDEBARAN) |
929 | adev->smuio.funcs = &smuio_v13_0_funcs; | |
0e961589 HZ |
930 | else |
931 | adev->smuio.funcs = &smuio_v9_0_funcs; | |
932 | ||
4cb0becb | 933 | adev->rev_id = soc15_get_rev_id(adev); |
1b922423 | 934 | |
220ab9bd KW |
935 | switch (adev->asic_type) { |
936 | case CHIP_VEGA10: | |
692069a1 | 937 | case CHIP_VEGA12: |
7c7af6c1 | 938 | case CHIP_VEGA20: |
2990a1fc AD |
939 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
940 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
2d11fd3f TH |
941 | |
942 | /* For Vega10 SR-IOV, PSP need to be initialized before IH */ | |
943 | if (amdgpu_sriov_vf(adev)) { | |
944 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { | |
945 | if (adev->asic_type == CHIP_VEGA20) | |
946 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
947 | else | |
948 | amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); | |
949 | } | |
c1059360 | 950 | if (adev->asic_type == CHIP_VEGA20) |
320a2e0c | 951 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
c1059360 AS |
952 | else |
953 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); | |
2d11fd3f | 954 | } else { |
c1059360 | 955 | if (adev->asic_type == CHIP_VEGA20) |
320a2e0c | 956 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
c1059360 AS |
957 | else |
958 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); | |
2d11fd3f TH |
959 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { |
960 | if (adev->asic_type == CHIP_VEGA20) | |
961 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
962 | else | |
963 | amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); | |
964 | } | |
3680b2a5 | 965 | } |
009d9ed6 RZ |
966 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
967 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
c9ffa427 YT |
968 | if (is_support_sw_smu(adev)) { |
969 | if (!amdgpu_sriov_vf(adev)) | |
2da5410b | 970 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
c9ffa427 YT |
971 | } else { |
972 | amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); | |
2da5410b | 973 | } |
f8445307 | 974 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
2990a1fc | 975 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
ab587d4a AD |
976 | #if defined(CONFIG_DRM_AMD_DC) |
977 | else if (amdgpu_device_has_dc_support(adev)) | |
2990a1fc | 978 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
ab587d4a | 979 | #endif |
846311ae FM |
980 | if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { |
981 | amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); | |
982 | amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); | |
983 | } | |
220ab9bd | 984 | break; |
1023b797 | 985 | case CHIP_RAVEN: |
40c2358b HR |
986 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
987 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
2990a1fc | 988 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
3680b2a5 EQ |
989 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
990 | amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); | |
009d9ed6 RZ |
991 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
992 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
b905090d | 993 | amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); |
d67fed16 | 994 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
2990a1fc | 995 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
0bf954c1 AD |
996 | #if defined(CONFIG_DRM_AMD_DC) |
997 | else if (amdgpu_device_has_dc_support(adev)) | |
2990a1fc | 998 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
0bf954c1 | 999 | #endif |
2990a1fc | 1000 | amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); |
1023b797 | 1001 | break; |
0e54df05 LM |
1002 | case CHIP_ARCTURUS: |
1003 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); | |
1004 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
21889cec JZ |
1005 | |
1006 | if (amdgpu_sriov_vf(adev)) { | |
1007 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
1008 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
320a2e0c | 1009 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
21889cec | 1010 | } else { |
320a2e0c | 1011 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
21889cec JZ |
1012 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
1013 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
1014 | } | |
1015 | ||
0e54df05 LM |
1016 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
1017 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
1018 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); | |
1019 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
c2a801af | 1020 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
21889cec | 1021 | |
ab5999de JJ |
1022 | if (amdgpu_sriov_vf(adev)) { |
1023 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
1024 | amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); | |
1025 | } else { | |
e7ddb878 | 1026 | amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); |
ab5999de | 1027 | } |
e416fdb6 JZ |
1028 | if (!amdgpu_sriov_vf(adev)) |
1029 | amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); | |
0e54df05 | 1030 | break; |
05e1f0e0 HR |
1031 | case CHIP_RENOIR: |
1032 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); | |
1033 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
1034 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); | |
6a7a0bdb AL |
1035 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
1036 | amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); | |
9530273e | 1037 | amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); |
97222cfa AL |
1038 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
1039 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
b1326bbc AL |
1040 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
1041 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
e1c14c43 RL |
1042 | #if defined(CONFIG_DRM_AMD_DC) |
1043 | else if (amdgpu_device_has_dc_support(adev)) | |
94ba290d | 1044 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
e1c14c43 | 1045 | #endif |
279ba48e | 1046 | amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); |
5be45a26 | 1047 | amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); |
05e1f0e0 | 1048 | break; |
7906af5e LM |
1049 | case CHIP_ALDEBARAN: |
1050 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); | |
1051 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
9fbd96a1 HZ |
1052 | |
1053 | if (amdgpu_sriov_vf(adev)) { | |
1054 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
1055 | amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); | |
10c71e6c | 1056 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
9fbd96a1 | 1057 | } else { |
10c71e6c | 1058 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
9fbd96a1 HZ |
1059 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
1060 | amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); | |
1061 | } | |
1062 | ||
7906af5e LM |
1063 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
1064 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
9f386fd3 | 1065 | |
bd7228ab | 1066 | amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); |
fdb1fdef JZ |
1067 | amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); |
1068 | amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); | |
7906af5e | 1069 | break; |
220ab9bd KW |
1070 | default: |
1071 | return -EINVAL; | |
1072 | } | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
adbd4f89 AD |
1077 | static bool soc15_need_full_reset(struct amdgpu_device *adev) |
1078 | { | |
1079 | /* change this when we implement soft reset */ | |
1080 | return true; | |
1081 | } | |
4a89ad9b | 1082 | |
b45e18ac KR |
1083 | static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
1084 | uint64_t *count1) | |
1085 | { | |
1086 | uint32_t perfctr = 0; | |
1087 | uint64_t cnt0_of, cnt1_of; | |
1088 | int tmp; | |
1089 | ||
1090 | /* This reports 0 on APUs, so return to avoid writing/reading registers | |
1091 | * that may or may not be different from their GPU counterparts | |
1092 | */ | |
0172591e ES |
1093 | if (adev->flags & AMD_IS_APU) |
1094 | return; | |
b45e18ac KR |
1095 | |
1096 | /* Set the 2 events that we wish to watch, defined above */ | |
9417f703 | 1097 | /* Reg 40 is # received msgs */ |
612e4ed9 | 1098 | /* Reg 104 is # of posted requests sent */ |
b45e18ac | 1099 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); |
612e4ed9 | 1100 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); |
b45e18ac KR |
1101 | |
1102 | /* Write to enable desired perf counters */ | |
1103 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); | |
1104 | /* Zero out and enable the perf counters | |
1105 | * Write 0x5: | |
1106 | * Bit 0 = Start all counters(1) | |
1107 | * Bit 2 = Global counter reset enable(1) | |
1108 | */ | |
1109 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); | |
1110 | ||
1111 | msleep(1000); | |
1112 | ||
1113 | /* Load the shadow and disable the perf counters | |
1114 | * Write 0x2: | |
1115 | * Bit 0 = Stop counters(0) | |
1116 | * Bit 1 = Load the shadow counters(1) | |
1117 | */ | |
1118 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); | |
1119 | ||
1120 | /* Read register values to get any >32bit overflow */ | |
1121 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); | |
1122 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); | |
1123 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); | |
1124 | ||
1125 | /* Get the values and add the overflow */ | |
1126 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); | |
1127 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); | |
1128 | } | |
adbd4f89 | 1129 | |
612e4ed9 KR |
1130 | static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
1131 | uint64_t *count1) | |
1132 | { | |
1133 | uint32_t perfctr = 0; | |
1134 | uint64_t cnt0_of, cnt1_of; | |
1135 | int tmp; | |
1136 | ||
1137 | /* This reports 0 on APUs, so return to avoid writing/reading registers | |
1138 | * that may or may not be different from their GPU counterparts | |
1139 | */ | |
1140 | if (adev->flags & AMD_IS_APU) | |
1141 | return; | |
1142 | ||
1143 | /* Set the 2 events that we wish to watch, defined above */ | |
1144 | /* Reg 40 is # received msgs */ | |
1145 | /* Reg 108 is # of posted requests sent on VG20 */ | |
1146 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, | |
1147 | EVENT0_SEL, 40); | |
1148 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, | |
1149 | EVENT1_SEL, 108); | |
1150 | ||
1151 | /* Write to enable desired perf counters */ | |
1152 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); | |
1153 | /* Zero out and enable the perf counters | |
1154 | * Write 0x5: | |
1155 | * Bit 0 = Start all counters(1) | |
1156 | * Bit 2 = Global counter reset enable(1) | |
1157 | */ | |
1158 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); | |
1159 | ||
1160 | msleep(1000); | |
1161 | ||
1162 | /* Load the shadow and disable the perf counters | |
1163 | * Write 0x2: | |
1164 | * Bit 0 = Stop counters(0) | |
1165 | * Bit 1 = Load the shadow counters(1) | |
1166 | */ | |
1167 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); | |
1168 | ||
1169 | /* Read register values to get any >32bit overflow */ | |
1170 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); | |
1171 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); | |
1172 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); | |
1173 | ||
1174 | /* Get the values and add the overflow */ | |
1175 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); | |
1176 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); | |
1177 | } | |
1178 | ||
9281f12c AD |
1179 | static bool soc15_need_reset_on_init(struct amdgpu_device *adev) |
1180 | { | |
1181 | u32 sol_reg; | |
1182 | ||
d55f33da AD |
1183 | /* Just return false for soc15 GPUs. Reset does not seem to |
1184 | * be necessary. | |
1185 | */ | |
394e9a14 ED |
1186 | if (!amdgpu_passthrough(adev)) |
1187 | return false; | |
d55f33da | 1188 | |
9281f12c AD |
1189 | if (adev->flags & AMD_IS_APU) |
1190 | return false; | |
1191 | ||
1192 | /* Check sOS sign of life register to confirm sys driver and sOS | |
1193 | * are already been loaded. | |
1194 | */ | |
1195 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
1196 | if (sol_reg) | |
1197 | return true; | |
1198 | ||
1199 | return false; | |
1200 | } | |
1201 | ||
dcea6e65 KR |
1202 | static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) |
1203 | { | |
1204 | uint64_t nak_r, nak_g; | |
1205 | ||
1206 | /* Get the number of NAKs received and generated */ | |
1207 | nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); | |
1208 | nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); | |
1209 | ||
1210 | /* Add the total number of NAKs, i.e the number of replays */ | |
1211 | return (nak_r + nak_g); | |
1212 | } | |
1213 | ||
b0a2db9b AD |
1214 | static void soc15_pre_asic_init(struct amdgpu_device *adev) |
1215 | { | |
1216 | gmc_v9_0_restore_registers(adev); | |
1217 | } | |
1218 | ||
220ab9bd KW |
1219 | static const struct amdgpu_asic_funcs soc15_asic_funcs = |
1220 | { | |
1221 | .read_disabled_bios = &soc15_read_disabled_bios, | |
1222 | .read_bios_from_rom = &soc15_read_bios_from_rom, | |
1223 | .read_register = &soc15_read_register, | |
1224 | .reset = &soc15_asic_reset, | |
ee360c0b | 1225 | .reset_method = &soc15_asic_reset_method, |
220ab9bd KW |
1226 | .set_vga_state = &soc15_vga_set_state, |
1227 | .get_xclk = &soc15_get_xclk, | |
1228 | .set_uvd_clocks = &soc15_set_uvd_clocks, | |
1229 | .set_vce_clocks = &soc15_set_vce_clocks, | |
1230 | .get_config_memsize = &soc15_get_config_memsize, | |
adbd4f89 | 1231 | .need_full_reset = &soc15_need_full_reset, |
062f3807 | 1232 | .init_doorbell_index = &vega10_doorbell_index_init, |
b45e18ac | 1233 | .get_pcie_usage = &soc15_get_pcie_usage, |
9281f12c | 1234 | .need_reset_on_init = &soc15_need_reset_on_init, |
dcea6e65 | 1235 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
988eb9ff | 1236 | .supports_baco = &soc15_supports_baco, |
b0a2db9b | 1237 | .pre_asic_init = &soc15_pre_asic_init, |
3b246e8b | 1238 | .query_video_codecs = &soc15_query_video_codecs, |
220ab9bd KW |
1239 | }; |
1240 | ||
c93aa775 OZ |
1241 | static const struct amdgpu_asic_funcs vega20_asic_funcs = |
1242 | { | |
1243 | .read_disabled_bios = &soc15_read_disabled_bios, | |
1244 | .read_bios_from_rom = &soc15_read_bios_from_rom, | |
1245 | .read_register = &soc15_read_register, | |
1246 | .reset = &soc15_asic_reset, | |
761e0923 | 1247 | .reset_method = &soc15_asic_reset_method, |
c93aa775 OZ |
1248 | .set_vga_state = &soc15_vga_set_state, |
1249 | .get_xclk = &soc15_get_xclk, | |
1250 | .set_uvd_clocks = &soc15_set_uvd_clocks, | |
1251 | .set_vce_clocks = &soc15_set_vce_clocks, | |
1252 | .get_config_memsize = &soc15_get_config_memsize, | |
c93aa775 OZ |
1253 | .need_full_reset = &soc15_need_full_reset, |
1254 | .init_doorbell_index = &vega20_doorbell_index_init, | |
612e4ed9 | 1255 | .get_pcie_usage = &vega20_get_pcie_usage, |
9281f12c | 1256 | .need_reset_on_init = &soc15_need_reset_on_init, |
dcea6e65 | 1257 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
988eb9ff | 1258 | .supports_baco = &soc15_supports_baco, |
b0a2db9b | 1259 | .pre_asic_init = &soc15_pre_asic_init, |
3b246e8b | 1260 | .query_video_codecs = &soc15_query_video_codecs, |
220ab9bd KW |
1261 | }; |
1262 | ||
1263 | static int soc15_common_early_init(void *handle) | |
1264 | { | |
88807dc8 | 1265 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) |
220ab9bd KW |
1266 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1267 | ||
88807dc8 OZ |
1268 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; |
1269 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; | |
220ab9bd KW |
1270 | adev->smc_rreg = NULL; |
1271 | adev->smc_wreg = NULL; | |
1272 | adev->pcie_rreg = &soc15_pcie_rreg; | |
1273 | adev->pcie_wreg = &soc15_pcie_wreg; | |
4fa1c6a6 TZ |
1274 | adev->pcie_rreg64 = &soc15_pcie_rreg64; |
1275 | adev->pcie_wreg64 = &soc15_pcie_wreg64; | |
220ab9bd KW |
1276 | adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; |
1277 | adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; | |
1278 | adev->didt_rreg = &soc15_didt_rreg; | |
1279 | adev->didt_wreg = &soc15_didt_wreg; | |
560460f2 EQ |
1280 | adev->gc_cac_rreg = &soc15_gc_cac_rreg; |
1281 | adev->gc_cac_wreg = &soc15_gc_cac_wreg; | |
2f11fb02 EQ |
1282 | adev->se_cac_rreg = &soc15_se_cac_rreg; |
1283 | adev->se_cac_wreg = &soc15_se_cac_wreg; | |
220ab9bd | 1284 | |
220ab9bd | 1285 | |
220ab9bd KW |
1286 | adev->external_rev_id = 0xFF; |
1287 | switch (adev->asic_type) { | |
1288 | case CHIP_VEGA10: | |
c93aa775 | 1289 | adev->asic_funcs = &soc15_asic_funcs; |
220ab9bd KW |
1290 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1291 | AMD_CG_SUPPORT_GFX_MGLS | | |
1292 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1293 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1294 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1295 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1296 | AMD_CG_SUPPORT_GFX_CGCG | | |
1297 | AMD_CG_SUPPORT_GFX_CGLS | | |
1298 | AMD_CG_SUPPORT_BIF_MGCG | | |
1299 | AMD_CG_SUPPORT_BIF_LS | | |
1300 | AMD_CG_SUPPORT_HDP_LS | | |
1301 | AMD_CG_SUPPORT_DRM_MGCG | | |
1302 | AMD_CG_SUPPORT_DRM_LS | | |
1303 | AMD_CG_SUPPORT_ROM_MGCG | | |
1304 | AMD_CG_SUPPORT_DF_MGCG | | |
1305 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1306 | AMD_CG_SUPPORT_SDMA_LS | | |
1307 | AMD_CG_SUPPORT_MC_MGCG | | |
1308 | AMD_CG_SUPPORT_MC_LS; | |
1309 | adev->pg_flags = 0; | |
1310 | adev->external_rev_id = 0x1; | |
1311 | break; | |
692069a1 | 1312 | case CHIP_VEGA12: |
c93aa775 | 1313 | adev->asic_funcs = &soc15_asic_funcs; |
e4a38755 EQ |
1314 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1315 | AMD_CG_SUPPORT_GFX_MGLS | | |
1316 | AMD_CG_SUPPORT_GFX_CGCG | | |
1317 | AMD_CG_SUPPORT_GFX_CGLS | | |
1318 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1319 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1320 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1321 | AMD_CG_SUPPORT_MC_LS | | |
1322 | AMD_CG_SUPPORT_MC_MGCG | | |
1323 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1324 | AMD_CG_SUPPORT_SDMA_LS | | |
1325 | AMD_CG_SUPPORT_BIF_MGCG | | |
1326 | AMD_CG_SUPPORT_BIF_LS | | |
1327 | AMD_CG_SUPPORT_HDP_MGCG | | |
1328 | AMD_CG_SUPPORT_HDP_LS | | |
1329 | AMD_CG_SUPPORT_ROM_MGCG | | |
1330 | AMD_CG_SUPPORT_VCE_MGCG | | |
1331 | AMD_CG_SUPPORT_UVD_MGCG; | |
692069a1 | 1332 | adev->pg_flags = 0; |
f559fe2b | 1333 | adev->external_rev_id = adev->rev_id + 0x14; |
692069a1 | 1334 | break; |
935be7a0 | 1335 | case CHIP_VEGA20: |
c93aa775 | 1336 | adev->asic_funcs = &vega20_asic_funcs; |
3fdbab5f EQ |
1337 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1338 | AMD_CG_SUPPORT_GFX_MGLS | | |
1339 | AMD_CG_SUPPORT_GFX_CGCG | | |
1340 | AMD_CG_SUPPORT_GFX_CGLS | | |
1341 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1342 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1343 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1344 | AMD_CG_SUPPORT_MC_LS | | |
1345 | AMD_CG_SUPPORT_MC_MGCG | | |
1346 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1347 | AMD_CG_SUPPORT_SDMA_LS | | |
1348 | AMD_CG_SUPPORT_BIF_MGCG | | |
1349 | AMD_CG_SUPPORT_BIF_LS | | |
1350 | AMD_CG_SUPPORT_HDP_MGCG | | |
102e4940 | 1351 | AMD_CG_SUPPORT_HDP_LS | |
3fdbab5f EQ |
1352 | AMD_CG_SUPPORT_ROM_MGCG | |
1353 | AMD_CG_SUPPORT_VCE_MGCG | | |
1354 | AMD_CG_SUPPORT_UVD_MGCG; | |
935be7a0 FX |
1355 | adev->pg_flags = 0; |
1356 | adev->external_rev_id = adev->rev_id + 0x28; | |
1357 | break; | |
957c6fe1 | 1358 | case CHIP_RAVEN: |
c93aa775 | 1359 | adev->asic_funcs = &soc15_asic_funcs; |
54f78a76 AD |
1360 | if (adev->pdev->device == 0x15dd) |
1361 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1362 | if (adev->pdev->device == 0x15d8) | |
1363 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
520cbe0f | 1364 | if (adev->rev_id >= 0x8) |
54f78a76 AD |
1365 | adev->apu_flags |= AMD_APU_IS_RAVEN2; |
1366 | ||
1367 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) | |
7e4545d3 | 1368 | adev->external_rev_id = adev->rev_id + 0x79; |
54f78a76 | 1369 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1370 | adev->external_rev_id = adev->rev_id + 0x41; |
7e4545d3 HR |
1371 | else if (adev->rev_id == 1) |
1372 | adev->external_rev_id = adev->rev_id + 0x20; | |
741deade | 1373 | else |
7e4545d3 | 1374 | adev->external_rev_id = adev->rev_id + 0x01; |
741deade | 1375 | |
54f78a76 | 1376 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) { |
520cbe0f HR |
1377 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1378 | AMD_CG_SUPPORT_GFX_MGLS | | |
1379 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1380 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1381 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1382 | AMD_CG_SUPPORT_GFX_CGCG | | |
1383 | AMD_CG_SUPPORT_GFX_CGLS | | |
1384 | AMD_CG_SUPPORT_BIF_LS | | |
1385 | AMD_CG_SUPPORT_HDP_LS | | |
520cbe0f HR |
1386 | AMD_CG_SUPPORT_MC_MGCG | |
1387 | AMD_CG_SUPPORT_MC_LS | | |
1388 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1389 | AMD_CG_SUPPORT_SDMA_LS | | |
1390 | AMD_CG_SUPPORT_VCN_MGCG; | |
741deade | 1391 | |
d5159591 | 1392 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
54f78a76 | 1393 | } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { |
fced5c70 LG |
1394 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1395 | AMD_CG_SUPPORT_GFX_MGLS | | |
741deade | 1396 | AMD_CG_SUPPORT_GFX_CP_LS | |
741deade AD |
1397 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
1398 | AMD_CG_SUPPORT_GFX_CGCG | | |
1399 | AMD_CG_SUPPORT_GFX_CGLS | | |
1400 | AMD_CG_SUPPORT_BIF_LS | | |
1401 | AMD_CG_SUPPORT_HDP_LS | | |
741deade AD |
1402 | AMD_CG_SUPPORT_MC_MGCG | |
1403 | AMD_CG_SUPPORT_MC_LS | | |
1404 | AMD_CG_SUPPORT_SDMA_MGCG | | |
a8f76887 S |
1405 | AMD_CG_SUPPORT_SDMA_LS | |
1406 | AMD_CG_SUPPORT_VCN_MGCG; | |
741deade AD |
1407 | |
1408 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | | |
1409 | AMD_PG_SUPPORT_MMHUB | | |
a10aad13 | 1410 | AMD_PG_SUPPORT_VCN; |
741deade | 1411 | } else { |
520cbe0f HR |
1412 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1413 | AMD_CG_SUPPORT_GFX_MGLS | | |
1414 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1415 | AMD_CG_SUPPORT_GFX_CP_LS | | |
520cbe0f HR |
1416 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
1417 | AMD_CG_SUPPORT_GFX_CGCG | | |
1418 | AMD_CG_SUPPORT_GFX_CGLS | | |
1419 | AMD_CG_SUPPORT_BIF_MGCG | | |
1420 | AMD_CG_SUPPORT_BIF_LS | | |
1421 | AMD_CG_SUPPORT_HDP_MGCG | | |
1422 | AMD_CG_SUPPORT_HDP_LS | | |
1423 | AMD_CG_SUPPORT_DRM_MGCG | | |
1424 | AMD_CG_SUPPORT_DRM_LS | | |
520cbe0f HR |
1425 | AMD_CG_SUPPORT_MC_MGCG | |
1426 | AMD_CG_SUPPORT_MC_LS | | |
1427 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1428 | AMD_CG_SUPPORT_SDMA_LS | | |
1429 | AMD_CG_SUPPORT_VCN_MGCG; | |
61c8e90d | 1430 | |
d5159591 | 1431 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
741deade | 1432 | } |
ad5a67a7 | 1433 | break; |
0e54df05 | 1434 | case CHIP_ARCTURUS: |
7f40581c | 1435 | adev->asic_funcs = &vega20_asic_funcs; |
6b76ce62 LM |
1436 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1437 | AMD_CG_SUPPORT_GFX_MGLS | | |
1438 | AMD_CG_SUPPORT_GFX_CGCG | | |
5d111f5b | 1439 | AMD_CG_SUPPORT_GFX_CGLS | |
f9da7c43 | 1440 | AMD_CG_SUPPORT_GFX_CP_LS | |
5d111f5b | 1441 | AMD_CG_SUPPORT_HDP_MGCG | |
f7ee1995 LM |
1442 | AMD_CG_SUPPORT_HDP_LS | |
1443 | AMD_CG_SUPPORT_SDMA_MGCG | | |
a840159c LM |
1444 | AMD_CG_SUPPORT_SDMA_LS | |
1445 | AMD_CG_SUPPORT_MC_MGCG | | |
227f7d58 | 1446 | AMD_CG_SUPPORT_MC_LS | |
e89e2237 LL |
1447 | AMD_CG_SUPPORT_IH_CG | |
1448 | AMD_CG_SUPPORT_VCN_MGCG | | |
1449 | AMD_CG_SUPPORT_JPEG_MGCG; | |
e520859c | 1450 | adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; |
d57c3d56 | 1451 | adev->external_rev_id = adev->rev_id + 0x32; |
0e54df05 | 1452 | break; |
080deab6 | 1453 | case CHIP_RENOIR: |
e09ce481 | 1454 | adev->asic_funcs = &soc15_asic_funcs; |
278cdb68 | 1455 | if ((adev->pdev->device == 0x1636) || |
1456 | (adev->pdev->device == 0x164c)) | |
5baf4150 PL |
1457 | adev->apu_flags |= AMD_APU_IS_RENOIR; |
1458 | else | |
1459 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1460 | ||
1461 | if (adev->apu_flags & AMD_APU_IS_RENOIR) | |
1462 | adev->external_rev_id = adev->rev_id + 0x91; | |
1463 | else | |
1464 | adev->external_rev_id = adev->rev_id + 0xa1; | |
ec3636a5 PL |
1465 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1466 | AMD_CG_SUPPORT_GFX_MGLS | | |
1467 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1468 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1469 | AMD_CG_SUPPORT_GFX_CGCG | | |
1470 | AMD_CG_SUPPORT_GFX_CGLS | | |
a2d15255 PL |
1471 | AMD_CG_SUPPORT_GFX_CP_LS | |
1472 | AMD_CG_SUPPORT_MC_MGCG | | |
ef0e7d08 PL |
1473 | AMD_CG_SUPPORT_MC_LS | |
1474 | AMD_CG_SUPPORT_SDMA_MGCG | | |
d98930f5 | 1475 | AMD_CG_SUPPORT_SDMA_LS | |
9deac0a4 | 1476 | AMD_CG_SUPPORT_BIF_LS | |
de273070 | 1477 | AMD_CG_SUPPORT_HDP_LS | |
91ec8bbb | 1478 | AMD_CG_SUPPORT_VCN_MGCG | |
099d66e4 | 1479 | AMD_CG_SUPPORT_JPEG_MGCG | |
e2ef3b70 PL |
1480 | AMD_CG_SUPPORT_IH_CG | |
1481 | AMD_CG_SUPPORT_ATHUB_LS | | |
8db63b7c PL |
1482 | AMD_CG_SUPPORT_ATHUB_MGCG | |
1483 | AMD_CG_SUPPORT_DF_MGCG; | |
85400984 TT |
1484 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | |
1485 | AMD_PG_SUPPORT_VCN | | |
099d66e4 | 1486 | AMD_PG_SUPPORT_JPEG | |
85400984 | 1487 | AMD_PG_SUPPORT_VCN_DPG; |
080deab6 | 1488 | break; |
7906af5e LM |
1489 | case CHIP_ALDEBARAN: |
1490 | adev->asic_funcs = &vega20_asic_funcs; | |
48a6379a LL |
1491 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1492 | AMD_CG_SUPPORT_GFX_MGLS | | |
1493 | AMD_CG_SUPPORT_GFX_CGCG | | |
1494 | AMD_CG_SUPPORT_GFX_CGLS | | |
1495 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1496 | AMD_CG_SUPPORT_HDP_LS | | |
1497 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1498 | AMD_CG_SUPPORT_SDMA_LS | | |
50ca2522 LL |
1499 | AMD_CG_SUPPORT_IH_CG | |
1500 | AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; | |
bd937973 | 1501 | adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; |
4f668d3d | 1502 | adev->external_rev_id = adev->rev_id + 0x3c; |
7906af5e | 1503 | break; |
220ab9bd KW |
1504 | default: |
1505 | /* FIXME: not supported yet */ | |
1506 | return -EINVAL; | |
1507 | } | |
1508 | ||
ab276632 XY |
1509 | if (amdgpu_sriov_vf(adev)) { |
1510 | amdgpu_virt_init_setting(adev); | |
1511 | xgpu_ai_mailbox_set_irq_funcs(adev); | |
1512 | } | |
1513 | ||
220ab9bd KW |
1514 | return 0; |
1515 | } | |
1516 | ||
81758c55 ML |
1517 | static int soc15_common_late_init(void *handle) |
1518 | { | |
1519 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
22e1d14f | 1520 | int r = 0; |
81758c55 ML |
1521 | |
1522 | if (amdgpu_sriov_vf(adev)) | |
1523 | xgpu_ai_mailbox_get_irq(adev); | |
1524 | ||
6e36f231 HZ |
1525 | if (adev->nbio.ras_funcs && |
1526 | adev->nbio.ras_funcs->ras_late_init) | |
1527 | r = adev->nbio.ras_funcs->ras_late_init(adev); | |
22e1d14f HZ |
1528 | |
1529 | return r; | |
81758c55 ML |
1530 | } |
1531 | ||
220ab9bd KW |
1532 | static int soc15_common_sw_init(void *handle) |
1533 | { | |
81758c55 ML |
1534 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1535 | ||
1536 | if (amdgpu_sriov_vf(adev)) | |
1537 | xgpu_ai_mailbox_add_irq_id(adev); | |
1538 | ||
bdf84a80 | 1539 | adev->df.funcs->sw_init(adev); |
e4cf4bf5 | 1540 | |
220ab9bd KW |
1541 | return 0; |
1542 | } | |
1543 | ||
1544 | static int soc15_common_sw_fini(void *handle) | |
1545 | { | |
f1d59e00 JZ |
1546 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1547 | ||
6e36f231 HZ |
1548 | if (adev->nbio.ras_funcs && |
1549 | adev->nbio.ras_funcs->ras_fini) | |
1550 | adev->nbio.ras_funcs->ras_fini(adev); | |
bdf84a80 | 1551 | adev->df.funcs->sw_fini(adev); |
220ab9bd KW |
1552 | return 0; |
1553 | } | |
1554 | ||
7c94bc82 OZ |
1555 | static void soc15_doorbell_range_init(struct amdgpu_device *adev) |
1556 | { | |
1557 | int i; | |
1558 | struct amdgpu_ring *ring; | |
1559 | ||
4cd4c5c0 ML |
1560 | /* sdma/ih doorbell range are programed by hypervisor */ |
1561 | if (!amdgpu_sriov_vf(adev)) { | |
98cad2de TH |
1562 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1563 | ring = &adev->sdma.instance[i].ring; | |
bebc0762 | 1564 | adev->nbio.funcs->sdma_doorbell_range(adev, i, |
98cad2de TH |
1565 | ring->use_doorbell, ring->doorbell_index, |
1566 | adev->doorbell_index.sdma_doorbell_range); | |
1567 | } | |
7c94bc82 | 1568 | |
bebc0762 | 1569 | adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, |
7c94bc82 | 1570 | adev->irq.ih.doorbell_index); |
4cd4c5c0 | 1571 | } |
7c94bc82 OZ |
1572 | } |
1573 | ||
220ab9bd KW |
1574 | static int soc15_common_hw_init(void *handle) |
1575 | { | |
1576 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1577 | ||
220ab9bd KW |
1578 | /* enable pcie gen2/3 link */ |
1579 | soc15_pcie_gen3_enable(adev); | |
1580 | /* enable aspm */ | |
1581 | soc15_program_aspm(adev); | |
833fa075 | 1582 | /* setup nbio registers */ |
bebc0762 | 1583 | adev->nbio.funcs->init_registers(adev); |
88807dc8 OZ |
1584 | /* remap HDP registers to a hole in mmio space, |
1585 | * for the purpose of expose those registers | |
1586 | * to process space | |
1587 | */ | |
bebc0762 HZ |
1588 | if (adev->nbio.funcs->remap_hdp_registers) |
1589 | adev->nbio.funcs->remap_hdp_registers(adev); | |
e4cf4bf5 | 1590 | |
220ab9bd KW |
1591 | /* enable the doorbell aperture */ |
1592 | soc15_enable_doorbell_aperture(adev, true); | |
7c94bc82 OZ |
1593 | /* HW doorbell routing policy: doorbell writing not |
1594 | * in SDMA/IH/MM/ACV range will be routed to CP. So | |
1595 | * we need to init SDMA/IH/MM/ACV doorbell range prior | |
1596 | * to CP ip block init and ring test. | |
1597 | */ | |
1598 | soc15_doorbell_range_init(adev); | |
220ab9bd KW |
1599 | |
1600 | return 0; | |
1601 | } | |
1602 | ||
1603 | static int soc15_common_hw_fini(void *handle) | |
1604 | { | |
1605 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1606 | ||
1607 | /* disable the doorbell aperture */ | |
1608 | soc15_enable_doorbell_aperture(adev, false); | |
81758c55 ML |
1609 | if (amdgpu_sriov_vf(adev)) |
1610 | xgpu_ai_mailbox_put_irq(adev); | |
220ab9bd | 1611 | |
cde85ac2 PY |
1612 | if (adev->nbio.ras_if && |
1613 | amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { | |
6e36f231 HZ |
1614 | if (adev->nbio.ras_funcs && |
1615 | adev->nbio.ras_funcs->init_ras_controller_interrupt) | |
22e1d14f | 1616 | amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); |
6e36f231 HZ |
1617 | if (adev->nbio.ras_funcs && |
1618 | adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) | |
22e1d14f HZ |
1619 | amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); |
1620 | } | |
1621 | ||
220ab9bd KW |
1622 | return 0; |
1623 | } | |
1624 | ||
1625 | static int soc15_common_suspend(void *handle) | |
1626 | { | |
1627 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1628 | ||
1629 | return soc15_common_hw_fini(adev); | |
1630 | } | |
1631 | ||
1632 | static int soc15_common_resume(void *handle) | |
1633 | { | |
1634 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1635 | ||
1636 | return soc15_common_hw_init(adev); | |
1637 | } | |
1638 | ||
1639 | static bool soc15_common_is_idle(void *handle) | |
1640 | { | |
1641 | return true; | |
1642 | } | |
1643 | ||
1644 | static int soc15_common_wait_for_idle(void *handle) | |
1645 | { | |
1646 | return 0; | |
1647 | } | |
1648 | ||
1649 | static int soc15_common_soft_reset(void *handle) | |
1650 | { | |
1651 | return 0; | |
1652 | } | |
1653 | ||
220ab9bd KW |
1654 | static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) |
1655 | { | |
1656 | uint32_t def, data; | |
1657 | ||
1658 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); | |
1659 | ||
1660 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) | |
1661 | data &= ~(0x01000000 | | |
1662 | 0x02000000 | | |
1663 | 0x04000000 | | |
1664 | 0x08000000 | | |
1665 | 0x10000000 | | |
1666 | 0x20000000 | | |
1667 | 0x40000000 | | |
1668 | 0x80000000); | |
1669 | else | |
1670 | data |= (0x01000000 | | |
1671 | 0x02000000 | | |
1672 | 0x04000000 | | |
1673 | 0x08000000 | | |
1674 | 0x10000000 | | |
1675 | 0x20000000 | | |
1676 | 0x40000000 | | |
1677 | 0x80000000); | |
1678 | ||
1679 | if (def != data) | |
1680 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); | |
1681 | } | |
1682 | ||
1683 | static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) | |
1684 | { | |
1685 | uint32_t def, data; | |
1686 | ||
1687 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); | |
1688 | ||
1689 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) | |
1690 | data |= 1; | |
1691 | else | |
1692 | data &= ~1; | |
1693 | ||
1694 | if (def != data) | |
1695 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); | |
1696 | } | |
1697 | ||
220ab9bd KW |
1698 | static int soc15_common_set_clockgating_state(void *handle, |
1699 | enum amd_clockgating_state state) | |
1700 | { | |
1701 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1702 | ||
6e9dc861 ML |
1703 | if (amdgpu_sriov_vf(adev)) |
1704 | return 0; | |
1705 | ||
220ab9bd KW |
1706 | switch (adev->asic_type) { |
1707 | case CHIP_VEGA10: | |
692069a1 | 1708 | case CHIP_VEGA12: |
f980d127 | 1709 | case CHIP_VEGA20: |
bebc0762 | 1710 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
a9d4fe2f | 1711 | state == AMD_CG_STATE_GATE); |
bebc0762 | 1712 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
a9d4fe2f | 1713 | state == AMD_CG_STATE_GATE); |
455d40c9 | 1714 | adev->hdp.funcs->update_clock_gating(adev, |
a9d4fe2f | 1715 | state == AMD_CG_STATE_GATE); |
220ab9bd | 1716 | soc15_update_drm_clock_gating(adev, |
a9d4fe2f | 1717 | state == AMD_CG_STATE_GATE); |
220ab9bd | 1718 | soc15_update_drm_light_sleep(adev, |
a9d4fe2f | 1719 | state == AMD_CG_STATE_GATE); |
0e961589 | 1720 | adev->smuio.funcs->update_rom_clock_gating(adev, |
a9d4fe2f | 1721 | state == AMD_CG_STATE_GATE); |
bdf84a80 | 1722 | adev->df.funcs->update_medium_grain_clock_gating(adev, |
a9d4fe2f | 1723 | state == AMD_CG_STATE_GATE); |
220ab9bd | 1724 | break; |
9e5a9eb4 | 1725 | case CHIP_RAVEN: |
f78e007f | 1726 | case CHIP_RENOIR: |
bebc0762 | 1727 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
a9d4fe2f | 1728 | state == AMD_CG_STATE_GATE); |
bebc0762 | 1729 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
a9d4fe2f | 1730 | state == AMD_CG_STATE_GATE); |
455d40c9 | 1731 | adev->hdp.funcs->update_clock_gating(adev, |
a9d4fe2f | 1732 | state == AMD_CG_STATE_GATE); |
9e5a9eb4 | 1733 | soc15_update_drm_clock_gating(adev, |
a9d4fe2f | 1734 | state == AMD_CG_STATE_GATE); |
9e5a9eb4 | 1735 | soc15_update_drm_light_sleep(adev, |
a9d4fe2f | 1736 | state == AMD_CG_STATE_GATE); |
9e5a9eb4 | 1737 | break; |
6acb87ac | 1738 | case CHIP_ARCTURUS: |
48a6379a | 1739 | case CHIP_ALDEBARAN: |
455d40c9 | 1740 | adev->hdp.funcs->update_clock_gating(adev, |
a9d4fe2f | 1741 | state == AMD_CG_STATE_GATE); |
6acb87ac | 1742 | break; |
220ab9bd KW |
1743 | default: |
1744 | break; | |
1745 | } | |
1746 | return 0; | |
1747 | } | |
1748 | ||
f9abe35c HR |
1749 | static void soc15_common_get_clockgating_state(void *handle, u32 *flags) |
1750 | { | |
1751 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1752 | int data; | |
1753 | ||
1754 | if (amdgpu_sriov_vf(adev)) | |
1755 | *flags = 0; | |
1756 | ||
bebc0762 | 1757 | adev->nbio.funcs->get_clockgating_state(adev, flags); |
f9abe35c | 1758 | |
455d40c9 | 1759 | adev->hdp.funcs->get_clock_gating_state(adev, flags); |
f9abe35c | 1760 | |
48a6379a | 1761 | if (adev->asic_type != CHIP_ALDEBARAN) { |
f9abe35c | 1762 | |
48a6379a LL |
1763 | /* AMD_CG_SUPPORT_DRM_MGCG */ |
1764 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); | |
1765 | if (!(data & 0x01000000)) | |
1766 | *flags |= AMD_CG_SUPPORT_DRM_MGCG; | |
1767 | ||
1768 | /* AMD_CG_SUPPORT_DRM_LS */ | |
1769 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); | |
1770 | if (data & 0x1) | |
1771 | *flags |= AMD_CG_SUPPORT_DRM_LS; | |
1772 | } | |
f9abe35c HR |
1773 | |
1774 | /* AMD_CG_SUPPORT_ROM_MGCG */ | |
0e961589 | 1775 | adev->smuio.funcs->get_clock_gating_state(adev, flags); |
f9abe35c | 1776 | |
bdf84a80 | 1777 | adev->df.funcs->get_clockgating_state(adev, flags); |
f9abe35c HR |
1778 | } |
1779 | ||
220ab9bd KW |
1780 | static int soc15_common_set_powergating_state(void *handle, |
1781 | enum amd_powergating_state state) | |
1782 | { | |
1783 | /* todo */ | |
1784 | return 0; | |
1785 | } | |
1786 | ||
1787 | const struct amd_ip_funcs soc15_common_ip_funcs = { | |
1788 | .name = "soc15_common", | |
1789 | .early_init = soc15_common_early_init, | |
81758c55 | 1790 | .late_init = soc15_common_late_init, |
220ab9bd KW |
1791 | .sw_init = soc15_common_sw_init, |
1792 | .sw_fini = soc15_common_sw_fini, | |
1793 | .hw_init = soc15_common_hw_init, | |
1794 | .hw_fini = soc15_common_hw_fini, | |
1795 | .suspend = soc15_common_suspend, | |
1796 | .resume = soc15_common_resume, | |
1797 | .is_idle = soc15_common_is_idle, | |
1798 | .wait_for_idle = soc15_common_wait_for_idle, | |
1799 | .soft_reset = soc15_common_soft_reset, | |
1800 | .set_clockgating_state = soc15_common_set_clockgating_state, | |
1801 | .set_powergating_state = soc15_common_set_powergating_state, | |
f9abe35c | 1802 | .get_clockgating_state= soc15_common_get_clockgating_state, |
220ab9bd | 1803 | }; |