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drm/amd/powerplay: disable raven2 force dpm level support (v2)
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
248a1d6f 26#include <drm/drmP.h>
220ab9bd 27#include "amdgpu.h"
d05da0e2 28#include "amdgpu_atombios.h"
220ab9bd
KW		 29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
5d735f83 37#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 38#include "gc/gc_9_0_offset.h"
39#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 40#include "sdma0/sdma0_4_0_offset.h"
41#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 42#include "hdp/hdp_4_0_offset.h"
43#include "hdp/hdp_4_0_sh_mask.h"
424d9bb4
FX		 44#include "smuio/smuio_9_0_offset.h"
45#include "smuio/smuio_9_0_sh_mask.h"
220ab9bd
KW		 46
47#include "soc15.h"
48#include "soc15_common.h"
49#include "gfx_v9_0.h"
50#include "gmc_v9_0.h"
51#include "gfxhub_v1_0.h"
52#include "mmhub_v1_0.h"
070706c0 53#include "df_v1_7.h"
698758bb 54#include "df_v3_6.h"
220ab9bd
KW		 55#include "vega10_ih.h"
56#include "sdma_v4_0.h"
57#include "uvd_v7_0.h"
58#include "vce_v4_0.h"
f2d7e707 59#include "vcn_v1_0.h"
796b6568 60#include "dce_virtual.h"
f1a34465 61#include "mxgpu_ai.h"
220ab9bd 62
220ab9bd
KW		 63#define mmMP0_MISC_CGTT_CTRL0 0x01b9
64#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
65#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
67
68/*
69 * Indirect registers accessor
70 */
71static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
72{
73 unsigned long flags, address, data;
74 u32 r;
946a4d5b
SL		 75 address = adev->nbio_funcs->get_pcie_index_offset(adev);
76 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 77
78 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
79 WREG32(address, reg);
80 (void)RREG32(address);
81 r = RREG32(data);
82 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
83 return r;
84}
85
86static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
87{
88 unsigned long flags, address, data;
220ab9bd 89
946a4d5b
SL		 90 address = adev->nbio_funcs->get_pcie_index_offset(adev);
91 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 92
93 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
94 WREG32(address, reg);
95 (void)RREG32(address);
96 WREG32(data, v);
97 (void)RREG32(data);
98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
99}
100
101static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
102{
103 unsigned long flags, address, data;
104 u32 r;
105
106 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
107 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
108
109 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
110 WREG32(address, ((reg) & 0x1ff));
111 r = RREG32(data);
112 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
113 return r;
114}
115
116static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
117{
118 unsigned long flags, address, data;
119
120 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
121 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
122
123 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
124 WREG32(address, ((reg) & 0x1ff));
125 WREG32(data, (v));
126 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
127}
128
129static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
130{
131 unsigned long flags, address, data;
132 u32 r;
133
134 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
135 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
136
137 spin_lock_irqsave(&adev->didt_idx_lock, flags);
138 WREG32(address, (reg));
139 r = RREG32(data);
140 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
141 return r;
142}
143
144static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
145{
146 unsigned long flags, address, data;
147
148 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
149 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
150
151 spin_lock_irqsave(&adev->didt_idx_lock, flags);
152 WREG32(address, (reg));
153 WREG32(data, (v));
154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
155}
156
560460f2
EQ		 157static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
158{
159 unsigned long flags;
160 u32 r;
161
162 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
163 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
164 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
165 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
166 return r;
167}
168
169static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
170{
171 unsigned long flags;
172
173 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
174 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
175 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
176 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
177}
178
2f11fb02
EQ		 179static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
180{
181 unsigned long flags;
182 u32 r;
183
184 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
185 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
186 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
187 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
188 return r;
189}
190
191static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
192{
193 unsigned long flags;
194
195 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
196 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
197 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
198 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
199}
200
220ab9bd
KW		 201static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
202{
bf383fb6 203 return adev->nbio_funcs->get_memsize(adev);
220ab9bd
KW		 204}
205
220ab9bd
KW		 206static u32 soc15_get_xclk(struct amdgpu_device *adev)
207{
76d6172b 208 return adev->clock.spll.reference_freq;
220ab9bd
KW		 209}
210
211
212void soc15_grbm_select(struct amdgpu_device *adev,
213 u32 me, u32 pipe, u32 queue, u32 vmid)
214{
215 u32 grbm_gfx_cntl = 0;
216 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
217 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
218 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
219 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
220
221 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
222}
223
224static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
225{
226 /* todo */
227}
228
229static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
230{
231 /* todo */
232 return false;
233}
234
235static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
236 u8 *bios, u32 length_bytes)
237{
238 u32 *dw_ptr;
239 u32 i, length_dw;
240
241 if (bios == NULL)
242 return false;
243 if (length_bytes == 0)
244 return false;
245 /* APU vbios image is part of sbios image */
246 if (adev->flags & AMD_IS_APU)
247 return false;
248
249 dw_ptr = (u32 *)bios;
250 length_dw = ALIGN(length_bytes, 4) / 4;
251
252 /* set rom index to 0 */
253 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
254 /* read out the rom data */
255 for (i = 0; i < length_dw; i++)
256 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
257
258 return true;
259}
260
946a4d5b
SL		 261struct soc15_allowed_register_entry {
262 uint32_t hwip;
263 uint32_t inst;
264 uint32_t seg;
265 uint32_t reg_offset;
266 bool grbm_indexed;
267};
268
269
270static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
271 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
272 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
273 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
274 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
275 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
276 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
277 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
278 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
279 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
280 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
281 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
282 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
283 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
284 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
285 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
286 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
287 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
288 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
5eeae247 289 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
220ab9bd
KW		 290};
291
292static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
293 u32 sh_num, u32 reg_offset)
294{
295 uint32_t val;
296
297 mutex_lock(&adev->grbm_idx_mutex);
298 if (se_num != 0xffffffff || sh_num != 0xffffffff)
299 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
300
301 val = RREG32(reg_offset);
302
303 if (se_num != 0xffffffff || sh_num != 0xffffffff)
304 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
305 mutex_unlock(&adev->grbm_idx_mutex);
306 return val;
307}
308
c013cea2
AD		 309static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
310 bool indexed, u32 se_num,
311 u32 sh_num, u32 reg_offset)
312{
313 if (indexed) {
314 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
315 } else {
cd29253f 316 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 317 return adev->gfx.config.gb_addr_config;
5eeae247
AD		 318 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
319 return adev->gfx.config.db_debug2;
cd29253f 320 return RREG32(reg_offset);
c013cea2
AD		 321 }
322}
323
220ab9bd
KW		 324static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
325 u32 sh_num, u32 reg_offset, u32 *value)
326{
3032f350 327 uint32_t i;
946a4d5b 328 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 329
330 *value = 0;
220ab9bd 331 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 332 en = &soc15_allowed_read_registers[i];
333 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
334 + en->reg_offset))
220ab9bd
KW		 335 continue;
336
97fcc76b
CK		 337 *value = soc15_get_register_value(adev,
338 soc15_allowed_read_registers[i].grbm_indexed,
339 se_num, sh_num, reg_offset);
220ab9bd
KW		 340 return 0;
341 }
342 return -EINVAL;
343}
344
946a4d5b
SL		 345
346/**
347 * soc15_program_register_sequence - program an array of registers.
348 *
349 * @adev: amdgpu_device pointer
350 * @regs: pointer to the register array
351 * @array_size: size of the register array
352 *
353 * Programs an array or registers with and and or masks.
354 * This is a helper for setting golden registers.
355 */
356
357void soc15_program_register_sequence(struct amdgpu_device *adev,
358 const struct soc15_reg_golden *regs,
359 const u32 array_size)
360{
361 const struct soc15_reg_golden *entry;
362 u32 tmp, reg;
363 int i;
364
365 for (i = 0; i < array_size; ++i) {
366 entry = &regs[i];
367 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
368
369 if (entry->and_mask == 0xffffffff) {
370 tmp = entry->or_mask;
371 } else {
372 tmp = RREG32(reg);
373 tmp &= ~(entry->and_mask);
374 tmp |= entry->or_mask;
375 }
376 WREG32(reg, tmp);
377 }
378
379}
380
381
98512bb8 382static int soc15_asic_reset(struct amdgpu_device *adev)
220ab9bd
KW		 383{
384 u32 i;
385
98512bb8
KW		 386 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
387
388 dev_info(adev->dev, "GPU reset\n");
220ab9bd
KW		 389
390 /* disable BM */
391 pci_clear_master(adev->pdev);
220ab9bd 392
98512bb8
KW		 393 pci_save_state(adev->pdev);
394
f75a9a5d 395 psp_gpu_reset(adev);
98512bb8
KW		 396
397 pci_restore_state(adev->pdev);
220ab9bd
KW		 398
399 /* wait for asic to come out of reset */
400 for (i = 0; i < adev->usec_timeout; i++) {
bf383fb6
AD		 401 u32 memsize = adev->nbio_funcs->get_memsize(adev);
402
aecbe64f 403 if (memsize != 0xffffffff)
220ab9bd
KW		 404 break;
405 udelay(1);
406 }
407
d05da0e2 408 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd
KW		 409
410 return 0;
411}
412
413/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
414 u32 cntl_reg, u32 status_reg)
415{
416 return 0;
417}*/
418
419static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
420{
421 /*int r;
422
423 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
424 if (r)
425 return r;
426
427 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
428 */
429 return 0;
430}
431
432static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
433{
434 /* todo */
435
436 return 0;
437}
438
439static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
440{
441 if (pci_is_root_bus(adev->pdev->bus))
442 return;
443
444 if (amdgpu_pcie_gen2 == 0)
445 return;
446
447 if (adev->flags & AMD_IS_APU)
448 return;
449
450 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
451 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
452 return;
453
454 /* todo */
455}
456
457static void soc15_program_aspm(struct amdgpu_device *adev)
458{
459
460 if (amdgpu_aspm == 0)
461 return;
462
463 /* todo */
464}
465
466static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 467 bool enable)
220ab9bd 468{
bf383fb6
AD		 469 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
470 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 471}
472
473static const struct amdgpu_ip_block_version vega10_common_ip_block =
474{
475 .type = AMD_IP_BLOCK_TYPE_COMMON,
476 .major = 2,
477 .minor = 0,
478 .rev = 0,
479 .funcs = &soc15_common_ip_funcs,
480};
481
4cb0becb
HR		 482static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
483{
484 return adev->nbio_funcs->get_rev_id(adev);
485}
486
220ab9bd
KW		 487int soc15_set_ip_blocks(struct amdgpu_device *adev)
488{
4522824c
SL		 489 /* Set IP register base before any HW register access */
490 switch (adev->asic_type) {
491 case CHIP_VEGA10:
3084eb00 492 case CHIP_VEGA12:
4522824c 493 case CHIP_RAVEN:
ad5a67a7 494 case CHIP_PICASSO:
4522824c
SL		 495 vega10_reg_base_init(adev);
496 break;
8ee273e5
FX		 497 case CHIP_VEGA20:
498 vega20_reg_base_init(adev);
499 break;
4522824c
SL		 500 default:
501 return -EINVAL;
502 }
503
bf383fb6
AD		 504 if (adev->flags & AMD_IS_APU)
505 adev->nbio_funcs = &nbio_v7_0_funcs;
fe3c9489
FX		 506 else if (adev->asic_type == CHIP_VEGA20)
507 adev->nbio_funcs = &nbio_v7_4_funcs;
bf383fb6
AD		 508 else
509 adev->nbio_funcs = &nbio_v6_1_funcs;
510
698758bb
FX		 511 if (adev->asic_type == CHIP_VEGA20)
512 adev->df_funcs = &df_v3_6_funcs;
513 else
514 adev->df_funcs = &df_v1_7_funcs;
4cb0becb
HR		 515
516 adev->rev_id = soc15_get_rev_id(adev);
bf383fb6 517 adev->nbio_funcs->detect_hw_virt(adev);
1b922423 518
f1a34465
XY		 519 if (amdgpu_sriov_vf(adev))
520 adev->virt.ops = &xgpu_ai_virt_ops;
521
220ab9bd
KW		 522 switch (adev->asic_type) {
523 case CHIP_VEGA10:
692069a1 524 case CHIP_VEGA12:
7c7af6c1 525 case CHIP_VEGA20:
2990a1fc
AD		 526 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
527 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
528 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
654f761c
FX		 529 if (adev->asic_type == CHIP_VEGA20)
530 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
531 else
602ed6c6 532 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
a6637313
EQ		 533 if (!amdgpu_sriov_vf(adev))
534 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
f8445307 535 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 536 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 537#if defined(CONFIG_DRM_AMD_DC)
538 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 539 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a
AD		 540#else
541# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
542#endif
2990a1fc
AD		 543 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
544 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
705e98d7
JZ		 545 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
546 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
220ab9bd 547 break;
1023b797 548 case CHIP_RAVEN:
2990a1fc
AD		 549 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
550 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
40c2358b
HR		 551 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
552 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
553 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
554 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
555 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
556#if defined(CONFIG_DRM_AMD_DC)
557 else if (amdgpu_device_has_dc_support(adev))
558 amdgpu_device_ip_block_add(adev, &dm_ip_block);
559#else
560# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
561#endif
562 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
563 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
564 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
565 break;
566 case CHIP_PICASSO:
567 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
568 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2990a1fc
AD		 569 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
570 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
b905090d 571 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 572 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 573 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 574#if defined(CONFIG_DRM_AMD_DC)
575 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 576 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1
AD		 577#else
578# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
579#endif
2990a1fc
AD		 580 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
581 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
582 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 583 break;
220ab9bd
KW		 584 default:
585 return -EINVAL;
586 }
587
588 return 0;
589}
590
69882565 591static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 592{
69882565 593 adev->nbio_funcs->hdp_flush(adev, ring);
73c73240
AD		 594}
595
69882565
CK		 596static void soc15_invalidate_hdp(struct amdgpu_device *adev,
597 struct amdgpu_ring *ring)
73c73240 598{
69882565
CK		 599 if (!ring || !ring->funcs->emit_wreg)
600 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
601 else
602 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
603 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 604}
605
adbd4f89
AD		 606static bool soc15_need_full_reset(struct amdgpu_device *adev)
607{
608 /* change this when we implement soft reset */
609 return true;
610}
611
220ab9bd
KW		 612static const struct amdgpu_asic_funcs soc15_asic_funcs =
613{
614 .read_disabled_bios = &soc15_read_disabled_bios,
615 .read_bios_from_rom = &soc15_read_bios_from_rom,
616 .read_register = &soc15_read_register,
617 .reset = &soc15_asic_reset,
618 .set_vga_state = &soc15_vga_set_state,
619 .get_xclk = &soc15_get_xclk,
620 .set_uvd_clocks = &soc15_set_uvd_clocks,
621 .set_vce_clocks = &soc15_set_vce_clocks,
622 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 623 .flush_hdp = &soc15_flush_hdp,
624 .invalidate_hdp = &soc15_invalidate_hdp,
adbd4f89 625 .need_full_reset = &soc15_need_full_reset,
220ab9bd
KW		 626};
627
628static int soc15_common_early_init(void *handle)
629{
220ab9bd
KW		 630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
631
632 adev->smc_rreg = NULL;
633 adev->smc_wreg = NULL;
634 adev->pcie_rreg = &soc15_pcie_rreg;
635 adev->pcie_wreg = &soc15_pcie_wreg;
636 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
637 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
638 adev->didt_rreg = &soc15_didt_rreg;
639 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 640 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
641 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 642 adev->se_cac_rreg = &soc15_se_cac_rreg;
643 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd
KW		 644
645 adev->asic_funcs = &soc15_asic_funcs;
646
220ab9bd
KW		 647 adev->external_rev_id = 0xFF;
648 switch (adev->asic_type) {
649 case CHIP_VEGA10:
650 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
651 AMD_CG_SUPPORT_GFX_MGLS |
652 AMD_CG_SUPPORT_GFX_RLC_LS |
653 AMD_CG_SUPPORT_GFX_CP_LS |
654 AMD_CG_SUPPORT_GFX_3D_CGCG |
655 AMD_CG_SUPPORT_GFX_3D_CGLS |
656 AMD_CG_SUPPORT_GFX_CGCG |
657 AMD_CG_SUPPORT_GFX_CGLS |
658 AMD_CG_SUPPORT_BIF_MGCG |
659 AMD_CG_SUPPORT_BIF_LS |
660 AMD_CG_SUPPORT_HDP_LS |
661 AMD_CG_SUPPORT_DRM_MGCG |
662 AMD_CG_SUPPORT_DRM_LS |
663 AMD_CG_SUPPORT_ROM_MGCG |
664 AMD_CG_SUPPORT_DF_MGCG |
665 AMD_CG_SUPPORT_SDMA_MGCG |
666 AMD_CG_SUPPORT_SDMA_LS |
667 AMD_CG_SUPPORT_MC_MGCG |
668 AMD_CG_SUPPORT_MC_LS;
669 adev->pg_flags = 0;
670 adev->external_rev_id = 0x1;
671 break;
692069a1 672 case CHIP_VEGA12:
e4a38755
EQ		 673 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
674 AMD_CG_SUPPORT_GFX_MGLS |
675 AMD_CG_SUPPORT_GFX_CGCG |
676 AMD_CG_SUPPORT_GFX_CGLS |
677 AMD_CG_SUPPORT_GFX_3D_CGCG |
678 AMD_CG_SUPPORT_GFX_3D_CGLS |
679 AMD_CG_SUPPORT_GFX_CP_LS |
680 AMD_CG_SUPPORT_MC_LS |
681 AMD_CG_SUPPORT_MC_MGCG |
682 AMD_CG_SUPPORT_SDMA_MGCG |
683 AMD_CG_SUPPORT_SDMA_LS |
684 AMD_CG_SUPPORT_BIF_MGCG |
685 AMD_CG_SUPPORT_BIF_LS |
686 AMD_CG_SUPPORT_HDP_MGCG |
687 AMD_CG_SUPPORT_HDP_LS |
688 AMD_CG_SUPPORT_ROM_MGCG |
689 AMD_CG_SUPPORT_VCE_MGCG |
690 AMD_CG_SUPPORT_UVD_MGCG;
692069a1 691 adev->pg_flags = 0;
f559fe2b 692 adev->external_rev_id = adev->rev_id + 0x14;
692069a1 693 break;
935be7a0 694 case CHIP_VEGA20:
3fdbab5f
EQ		 695 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
696 AMD_CG_SUPPORT_GFX_MGLS |
697 AMD_CG_SUPPORT_GFX_CGCG |
698 AMD_CG_SUPPORT_GFX_CGLS |
699 AMD_CG_SUPPORT_GFX_3D_CGCG |
700 AMD_CG_SUPPORT_GFX_3D_CGLS |
701 AMD_CG_SUPPORT_GFX_CP_LS |
702 AMD_CG_SUPPORT_MC_LS |
703 AMD_CG_SUPPORT_MC_MGCG |
704 AMD_CG_SUPPORT_SDMA_MGCG |
705 AMD_CG_SUPPORT_SDMA_LS |
706 AMD_CG_SUPPORT_BIF_MGCG |
707 AMD_CG_SUPPORT_BIF_LS |
708 AMD_CG_SUPPORT_HDP_MGCG |
102e4940 709 AMD_CG_SUPPORT_HDP_LS |
3fdbab5f
EQ		 710 AMD_CG_SUPPORT_ROM_MGCG |
711 AMD_CG_SUPPORT_VCE_MGCG |
712 AMD_CG_SUPPORT_UVD_MGCG;
935be7a0
FX		 713 adev->pg_flags = 0;
714 adev->external_rev_id = adev->rev_id + 0x28;
715 break;
957c6fe1 716 case CHIP_RAVEN:
5c5928a2
HR		 717 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
718 AMD_CG_SUPPORT_GFX_MGLS |
719 AMD_CG_SUPPORT_GFX_RLC_LS |
720 AMD_CG_SUPPORT_GFX_CP_LS |
721 AMD_CG_SUPPORT_GFX_3D_CGCG |
722 AMD_CG_SUPPORT_GFX_3D_CGLS |
723 AMD_CG_SUPPORT_GFX_CGCG |
724 AMD_CG_SUPPORT_GFX_CGLS |
725 AMD_CG_SUPPORT_BIF_MGCG |
726 AMD_CG_SUPPORT_BIF_LS |
727 AMD_CG_SUPPORT_HDP_MGCG |
728 AMD_CG_SUPPORT_HDP_LS |
729 AMD_CG_SUPPORT_DRM_MGCG |
730 AMD_CG_SUPPORT_DRM_LS |
c2cdb0ec
HR		 731 AMD_CG_SUPPORT_ROM_MGCG |
732 AMD_CG_SUPPORT_MC_MGCG |
fe1a3b2e
HR		 733 AMD_CG_SUPPORT_MC_LS |
734 AMD_CG_SUPPORT_SDMA_MGCG |
79953a60
RZ		 735 AMD_CG_SUPPORT_SDMA_LS |
736 AMD_CG_SUPPORT_VCN_MGCG;
61c8e90d
RZ		 737
738 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
400b6afb 739
9ac4b0d9
HR		 740 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
741 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
742 AMD_PG_SUPPORT_CP |
743 AMD_PG_SUPPORT_RLC_SMU_HS;
744
1879e6a7
AD		 745 if (adev->rev_id >= 0x8)
746 adev->external_rev_id = adev->rev_id + 0x81;
747 else
748 adev->external_rev_id = 0x1;
957c6fe1 749 break;
ad5a67a7
LG		 750 case CHIP_PICASSO:
751 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
752 AMD_CG_SUPPORT_GFX_CP_LS |
753 AMD_CG_SUPPORT_GFX_3D_CGCG |
754 AMD_CG_SUPPORT_GFX_3D_CGLS |
755 AMD_CG_SUPPORT_GFX_CGCG |
756 AMD_CG_SUPPORT_GFX_CGLS |
757 AMD_CG_SUPPORT_BIF_LS |
758 AMD_CG_SUPPORT_HDP_LS |
759 AMD_CG_SUPPORT_ROM_MGCG |
760 AMD_CG_SUPPORT_MC_MGCG |
761 AMD_CG_SUPPORT_MC_LS |
762 AMD_CG_SUPPORT_SDMA_MGCG |
763 AMD_CG_SUPPORT_SDMA_LS;
764
1a84d967
KF		 765 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
766 AMD_PG_SUPPORT_MMHUB |
767 AMD_PG_SUPPORT_VCN;
a4494fda 768
8c7bf583
KF		 769 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
770 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
771 AMD_PG_SUPPORT_CP |
772 AMD_PG_SUPPORT_RLC_SMU_HS;
ad5a67a7
LG		 773
774 adev->external_rev_id = adev->rev_id + 0x41;
775 break;
220ab9bd
KW		 776 default:
777 /* FIXME: not supported yet */
778 return -EINVAL;
779 }
780
ab276632
XY		 781 if (amdgpu_sriov_vf(adev)) {
782 amdgpu_virt_init_setting(adev);
783 xgpu_ai_mailbox_set_irq_funcs(adev);
784 }
785
220ab9bd
KW		 786 return 0;
787}
788
81758c55
ML		 789static int soc15_common_late_init(void *handle)
790{
791 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
792
793 if (amdgpu_sriov_vf(adev))
794 xgpu_ai_mailbox_get_irq(adev);
795
796 return 0;
797}
798
220ab9bd
KW		 799static int soc15_common_sw_init(void *handle)
800{
81758c55
ML		 801 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
802
803 if (amdgpu_sriov_vf(adev))
804 xgpu_ai_mailbox_add_irq_id(adev);
805
220ab9bd
KW		 806 return 0;
807}
808
809static int soc15_common_sw_fini(void *handle)
810{
811 return 0;
812}
813
814static int soc15_common_hw_init(void *handle)
815{
816 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
817
220ab9bd
KW		 818 /* enable pcie gen2/3 link */
819 soc15_pcie_gen3_enable(adev);
820 /* enable aspm */
821 soc15_program_aspm(adev);
833fa075 822 /* setup nbio registers */
bf383fb6 823 adev->nbio_funcs->init_registers(adev);
220ab9bd
KW		 824 /* enable the doorbell aperture */
825 soc15_enable_doorbell_aperture(adev, true);
826
827 return 0;
828}
829
830static int soc15_common_hw_fini(void *handle)
831{
832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
833
834 /* disable the doorbell aperture */
835 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 836 if (amdgpu_sriov_vf(adev))
837 xgpu_ai_mailbox_put_irq(adev);
220ab9bd
KW		 838
839 return 0;
840}
841
842static int soc15_common_suspend(void *handle)
843{
844 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
845
846 return soc15_common_hw_fini(adev);
847}
848
849static int soc15_common_resume(void *handle)
850{
851 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
852
853 return soc15_common_hw_init(adev);
854}
855
856static bool soc15_common_is_idle(void *handle)
857{
858 return true;
859}
860
861static int soc15_common_wait_for_idle(void *handle)
862{
863 return 0;
864}
865
866static int soc15_common_soft_reset(void *handle)
867{
868 return 0;
869}
870
871static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
872{
873 uint32_t def, data;
874
875 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
876
877 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
878 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
879 else
880 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
881
882 if (def != data)
883 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
884}
885
886static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
887{
888 uint32_t def, data;
889
890 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
891
892 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
893 data &= ~(0x01000000 |
894 0x02000000 |
895 0x04000000 |
896 0x08000000 |
897 0x10000000 |
898 0x20000000 |
899 0x40000000 |
900 0x80000000);
901 else
902 data |= (0x01000000 |
903 0x02000000 |
904 0x04000000 |
905 0x08000000 |
906 0x10000000 |
907 0x20000000 |
908 0x40000000 |
909 0x80000000);
910
911 if (def != data)
912 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
913}
914
915static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
916{
917 uint32_t def, data;
918
919 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
920
921 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
922 data |= 1;
923 else
924 data &= ~1;
925
926 if (def != data)
927 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
928}
929
930static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
931 bool enable)
932{
933 uint32_t def, data;
934
935 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
936
937 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
938 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
939 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
940 else
941 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
942 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
943
944 if (def != data)
945 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
946}
947
220ab9bd
KW		 948static int soc15_common_set_clockgating_state(void *handle,
949 enum amd_clockgating_state state)
950{
951 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
952
6e9dc861
ML		 953 if (amdgpu_sriov_vf(adev))
954 return 0;
955
220ab9bd
KW		 956 switch (adev->asic_type) {
957 case CHIP_VEGA10:
692069a1 958 case CHIP_VEGA12:
f980d127 959 case CHIP_VEGA20:
bf383fb6 960 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
220ab9bd 961 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 962 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 963 state == AMD_CG_STATE_GATE ? true : false);
964 soc15_update_hdp_light_sleep(adev,
965 state == AMD_CG_STATE_GATE ? true : false);
966 soc15_update_drm_clock_gating(adev,
967 state == AMD_CG_STATE_GATE ? true : false);
968 soc15_update_drm_light_sleep(adev,
969 state == AMD_CG_STATE_GATE ? true : false);
970 soc15_update_rom_medium_grain_clock_gating(adev,
971 state == AMD_CG_STATE_GATE ? true : false);
070706c0 972 adev->df_funcs->update_medium_grain_clock_gating(adev,
220ab9bd
KW		 973 state == AMD_CG_STATE_GATE ? true : false);
974 break;
9e5a9eb4 975 case CHIP_RAVEN:
ad5a67a7 976 case CHIP_PICASSO:
bf383fb6 977 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 978 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 979 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 980 state == AMD_CG_STATE_GATE ? true : false);
981 soc15_update_hdp_light_sleep(adev,
982 state == AMD_CG_STATE_GATE ? true : false);
983 soc15_update_drm_clock_gating(adev,
984 state == AMD_CG_STATE_GATE ? true : false);
985 soc15_update_drm_light_sleep(adev,
986 state == AMD_CG_STATE_GATE ? true : false);
987 soc15_update_rom_medium_grain_clock_gating(adev,
988 state == AMD_CG_STATE_GATE ? true : false);
989 break;
220ab9bd
KW		 990 default:
991 break;
992 }
993 return 0;
994}
995
f9abe35c
HR		 996static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
997{
998 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
999 int data;
1000
1001 if (amdgpu_sriov_vf(adev))
1002 *flags = 0;
1003
bf383fb6 1004 adev->nbio_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1005
1006 /* AMD_CG_SUPPORT_HDP_LS */
1007 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1008 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1009 *flags |= AMD_CG_SUPPORT_HDP_LS;
1010
1011 /* AMD_CG_SUPPORT_DRM_MGCG */
1012 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1013 if (!(data & 0x01000000))
1014 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1015
1016 /* AMD_CG_SUPPORT_DRM_LS */
1017 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1018 if (data & 0x1)
1019 *flags |= AMD_CG_SUPPORT_DRM_LS;
1020
1021 /* AMD_CG_SUPPORT_ROM_MGCG */
1022 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1023 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1024 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1025
070706c0 1026 adev->df_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1027}
1028
220ab9bd
KW		 1029static int soc15_common_set_powergating_state(void *handle,
1030 enum amd_powergating_state state)
1031{
1032 /* todo */
1033 return 0;
1034}
1035
1036const struct amd_ip_funcs soc15_common_ip_funcs = {
1037 .name = "soc15_common",
1038 .early_init = soc15_common_early_init,
81758c55 1039 .late_init = soc15_common_late_init,
220ab9bd
KW		 1040 .sw_init = soc15_common_sw_init,
1041 .sw_fini = soc15_common_sw_fini,
1042 .hw_init = soc15_common_hw_init,
1043 .hw_fini = soc15_common_hw_fini,
1044 .suspend = soc15_common_suspend,
1045 .resume = soc15_common_resume,
1046 .is_idle = soc15_common_is_idle,
1047 .wait_for_idle = soc15_common_wait_for_idle,
1048 .soft_reset = soc15_common_soft_reset,
1049 .set_clockgating_state = soc15_common_set_clockgating_state,
1050 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 1051 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 1052};
Linux 6.x block layer and io_uring tree(s)