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drm/amdgpu/VCN2.5: set JPEG decode ring functions
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
47b757fb
SR		 26#include <linux/pci.h>
27
220ab9bd 28#include "amdgpu.h"
d05da0e2 29#include "amdgpu_atombios.h"
220ab9bd
KW		 30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "atom.h"
36#include "amd_pcie.h"
37
5d735f83 38#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 39#include "gc/gc_9_0_offset.h"
40#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 41#include "sdma0/sdma0_4_0_offset.h"
42#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 43#include "hdp/hdp_4_0_offset.h"
44#include "hdp/hdp_4_0_sh_mask.h"
424d9bb4
FX		 45#include "smuio/smuio_9_0_offset.h"
46#include "smuio/smuio_9_0_sh_mask.h"
b45e18ac 47#include "nbio/nbio_7_0_default.h"
88807dc8 48#include "nbio/nbio_7_0_offset.h"
b45e18ac
KR		 49#include "nbio/nbio_7_0_sh_mask.h"
50#include "nbio/nbio_7_0_smn.h"
9281f12c 51#include "mp/mp_9_0_offset.h"
220ab9bd
KW		 52
53#include "soc15.h"
54#include "soc15_common.h"
55#include "gfx_v9_0.h"
56#include "gmc_v9_0.h"
57#include "gfxhub_v1_0.h"
58#include "mmhub_v1_0.h"
070706c0 59#include "df_v1_7.h"
698758bb 60#include "df_v3_6.h"
220ab9bd
KW		 61#include "vega10_ih.h"
62#include "sdma_v4_0.h"
63#include "uvd_v7_0.h"
64#include "vce_v4_0.h"
f2d7e707 65#include "vcn_v1_0.h"
796b6568 66#include "dce_virtual.h"
f1a34465 67#include "mxgpu_ai.h"
2da5410b 68#include "amdgpu_smu.h"
e74609cb
AD		 69#include "amdgpu_ras.h"
70#include "amdgpu_xgmi.h"
88807dc8 71#include <uapi/linux/kfd_ioctl.h>
220ab9bd 72
220ab9bd
KW		 73#define mmMP0_MISC_CGTT_CTRL0 0x01b9
74#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
75#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
76#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
77
a5d0f456
KF		 78/* for Vega20 register name change */
79#define mmHDP_MEM_POWER_CTRL 0x00d4
80#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
81#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
82#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
83#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
84#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
220ab9bd
KW		 85/*
86 * Indirect registers accessor
87 */
88static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
89{
90 unsigned long flags, address, data;
91 u32 r;
946a4d5b
SL		 92 address = adev->nbio_funcs->get_pcie_index_offset(adev);
93 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 94
95 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
96 WREG32(address, reg);
97 (void)RREG32(address);
98 r = RREG32(data);
99 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
100 return r;
101}
102
103static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
104{
105 unsigned long flags, address, data;
220ab9bd 106
946a4d5b
SL		 107 address = adev->nbio_funcs->get_pcie_index_offset(adev);
108 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 109
110 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
111 WREG32(address, reg);
112 (void)RREG32(address);
113 WREG32(data, v);
114 (void)RREG32(data);
115 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
116}
117
118static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
119{
120 unsigned long flags, address, data;
121 u32 r;
122
123 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
124 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
125
126 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
127 WREG32(address, ((reg) & 0x1ff));
128 r = RREG32(data);
129 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
130 return r;
131}
132
133static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
134{
135 unsigned long flags, address, data;
136
137 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
138 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
139
140 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
141 WREG32(address, ((reg) & 0x1ff));
142 WREG32(data, (v));
143 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
144}
145
146static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
147{
148 unsigned long flags, address, data;
149 u32 r;
150
151 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
152 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
153
154 spin_lock_irqsave(&adev->didt_idx_lock, flags);
155 WREG32(address, (reg));
156 r = RREG32(data);
157 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
158 return r;
159}
160
161static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
162{
163 unsigned long flags, address, data;
164
165 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
166 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
167
168 spin_lock_irqsave(&adev->didt_idx_lock, flags);
169 WREG32(address, (reg));
170 WREG32(data, (v));
171 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
172}
173
560460f2
EQ		 174static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
175{
176 unsigned long flags;
177 u32 r;
178
179 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
180 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
181 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
182 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
183 return r;
184}
185
186static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
187{
188 unsigned long flags;
189
190 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
191 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
192 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
193 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
194}
195
2f11fb02
EQ		 196static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
197{
198 unsigned long flags;
199 u32 r;
200
201 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
202 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
203 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
204 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
205 return r;
206}
207
208static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
209{
210 unsigned long flags;
211
212 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
213 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
214 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
215 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
216}
217
220ab9bd
KW		 218static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
219{
bf383fb6 220 return adev->nbio_funcs->get_memsize(adev);
220ab9bd
KW		 221}
222
220ab9bd
KW		 223static u32 soc15_get_xclk(struct amdgpu_device *adev)
224{
76d6172b 225 return adev->clock.spll.reference_freq;
220ab9bd
KW		 226}
227
228
229void soc15_grbm_select(struct amdgpu_device *adev,
230 u32 me, u32 pipe, u32 queue, u32 vmid)
231{
232 u32 grbm_gfx_cntl = 0;
233 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
234 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
235 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
236 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
237
1bff7f6c 238 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
220ab9bd
KW		 239}
240
241static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
242{
243 /* todo */
244}
245
246static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
247{
248 /* todo */
249 return false;
250}
251
252static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
253 u8 *bios, u32 length_bytes)
254{
255 u32 *dw_ptr;
256 u32 i, length_dw;
257
258 if (bios == NULL)
259 return false;
260 if (length_bytes == 0)
261 return false;
262 /* APU vbios image is part of sbios image */
263 if (adev->flags & AMD_IS_APU)
264 return false;
265
266 dw_ptr = (u32 *)bios;
267 length_dw = ALIGN(length_bytes, 4) / 4;
268
269 /* set rom index to 0 */
270 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
271 /* read out the rom data */
272 for (i = 0; i < length_dw; i++)
273 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
274
275 return true;
276}
277
946a4d5b
SL		 278static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
279 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
280 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
281 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
282 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
283 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
284 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
285 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
286 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
287 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
288 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
289 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
290 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
291 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
292 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
293 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
294 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
295 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
296 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
5eeae247 297 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
220ab9bd
KW		 298};
299
300static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
301 u32 sh_num, u32 reg_offset)
302{
303 uint32_t val;
304
305 mutex_lock(&adev->grbm_idx_mutex);
306 if (se_num != 0xffffffff || sh_num != 0xffffffff)
307 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
308
309 val = RREG32(reg_offset);
310
311 if (se_num != 0xffffffff || sh_num != 0xffffffff)
312 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
313 mutex_unlock(&adev->grbm_idx_mutex);
314 return val;
315}
316
c013cea2
AD		 317static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
318 bool indexed, u32 se_num,
319 u32 sh_num, u32 reg_offset)
320{
321 if (indexed) {
322 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
323 } else {
cd29253f 324 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 325 return adev->gfx.config.gb_addr_config;
5eeae247
AD		 326 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
327 return adev->gfx.config.db_debug2;
cd29253f 328 return RREG32(reg_offset);
c013cea2
AD		 329 }
330}
331
220ab9bd
KW		 332static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
333 u32 sh_num, u32 reg_offset, u32 *value)
334{
3032f350 335 uint32_t i;
946a4d5b 336 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 337
338 *value = 0;
220ab9bd 339 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 340 en = &soc15_allowed_read_registers[i];
341 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
342 + en->reg_offset))
220ab9bd
KW		 343 continue;
344
97fcc76b
CK		 345 *value = soc15_get_register_value(adev,
346 soc15_allowed_read_registers[i].grbm_indexed,
347 se_num, sh_num, reg_offset);
220ab9bd
KW		 348 return 0;
349 }
350 return -EINVAL;
351}
352
946a4d5b
SL		 353
354/**
355 * soc15_program_register_sequence - program an array of registers.
356 *
357 * @adev: amdgpu_device pointer
358 * @regs: pointer to the register array
359 * @array_size: size of the register array
360 *
361 * Programs an array or registers with and and or masks.
362 * This is a helper for setting golden registers.
363 */
364
365void soc15_program_register_sequence(struct amdgpu_device *adev,
366 const struct soc15_reg_golden *regs,
367 const u32 array_size)
368{
369 const struct soc15_reg_golden *entry;
370 u32 tmp, reg;
371 int i;
372
373 for (i = 0; i < array_size; ++i) {
374 entry = &regs[i];
375 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
376
377 if (entry->and_mask == 0xffffffff) {
378 tmp = entry->or_mask;
379 } else {
380 tmp = RREG32(reg);
381 tmp &= ~(entry->and_mask);
e0d07657 382 tmp |= (entry->or_mask & entry->and_mask);
946a4d5b 383 }
1bff7f6c
TH		 384
385 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
386 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
387 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
388 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
389 WREG32_RLC(reg, tmp);
390 else
391 WREG32(reg, tmp);
392
946a4d5b
SL		 393 }
394
395}
396
e2b6d053 397static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
220ab9bd
KW		 398{
399 u32 i;
39fee32b 400 int ret = 0;
220ab9bd 401
98512bb8
KW		 402 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
403
e2b6d053 404 dev_info(adev->dev, "GPU mode1 reset\n");
220ab9bd
KW		 405
406 /* disable BM */
407 pci_clear_master(adev->pdev);
220ab9bd 408
98512bb8
KW		 409 pci_save_state(adev->pdev);
410
39fee32b
EQ		 411 ret = psp_gpu_reset(adev);
412 if (ret)
413 dev_err(adev->dev, "GPU mode1 reset failed\n");
98512bb8
KW		 414
415 pci_restore_state(adev->pdev);
220ab9bd
KW		 416
417 /* wait for asic to come out of reset */
418 for (i = 0; i < adev->usec_timeout; i++) {
bf383fb6
AD		 419 u32 memsize = adev->nbio_funcs->get_memsize(adev);
420
aecbe64f 421 if (memsize != 0xffffffff)
220ab9bd
KW		 422 break;
423 udelay(1);
424 }
425
d05da0e2 426 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd 427
39fee32b 428 return ret;
220ab9bd
KW		 429}
430
e2b6d053
JQ		 431static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
432{
433 void *pp_handle = adev->powerplay.pp_handle;
434 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
435
436 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
437 *cap = false;
1f46df61 438 return -ENOENT;
e2b6d053
JQ		 439 }
440
441 return pp_funcs->get_asic_baco_capability(pp_handle, cap);
442}
443
444static int soc15_asic_baco_reset(struct amdgpu_device *adev)
445{
446 void *pp_handle = adev->powerplay.pp_handle;
447 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
448
449 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
1f46df61 450 return -ENOENT;
e2b6d053
JQ		 451
452 /* enter BACO state */
453 if (pp_funcs->set_asic_baco_state(pp_handle, 1))
1f46df61 454 return -EIO;
e2b6d053
JQ		 455
456 /* exit BACO state */
457 if (pp_funcs->set_asic_baco_state(pp_handle, 0))
1f46df61 458 return -EIO;
e2b6d053
JQ		 459
460 dev_info(adev->dev, "GPU BACO reset\n");
461
0c5ccf14
EQ		 462 adev->in_baco_reset = 1;
463
e2b6d053
JQ		 464 return 0;
465}
466
467static int soc15_asic_reset(struct amdgpu_device *adev)
468{
469 int ret;
470 bool baco_reset;
471
472 switch (adev->asic_type) {
473 case CHIP_VEGA10:
f8b18cf4 474 case CHIP_VEGA12:
e2b6d053
JQ		 475 soc15_asic_get_baco_capability(adev, &baco_reset);
476 break;
017d75f1
EQ		 477 case CHIP_VEGA20:
478 if (adev->psp.sos_fw_version >= 0x80067)
479 soc15_asic_get_baco_capability(adev, &baco_reset);
480 else
481 baco_reset = false;
e74609cb
AD		 482 if (baco_reset) {
483 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
485
486 if (hive || (ras && ras->supported))
487 baco_reset = false;
488 }
017d75f1 489 break;
e2b6d053
JQ		 490 default:
491 baco_reset = false;
492 break;
493 }
494
495 if (baco_reset)
496 ret = soc15_asic_baco_reset(adev);
497 else
498 ret = soc15_asic_mode1_reset(adev);
499
500 return ret;
501}
502
220ab9bd
KW		 503/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
504 u32 cntl_reg, u32 status_reg)
505{
506 return 0;
507}*/
508
509static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
510{
511 /*int r;
512
513 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
514 if (r)
515 return r;
516
517 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
518 */
519 return 0;
520}
521
522static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
523{
524 /* todo */
525
526 return 0;
527}
528
529static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
530{
531 if (pci_is_root_bus(adev->pdev->bus))
532 return;
533
534 if (amdgpu_pcie_gen2 == 0)
535 return;
536
537 if (adev->flags & AMD_IS_APU)
538 return;
539
540 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
541 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
542 return;
543
544 /* todo */
545}
546
547static void soc15_program_aspm(struct amdgpu_device *adev)
548{
549
550 if (amdgpu_aspm == 0)
551 return;
552
553 /* todo */
554}
555
556static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 557 bool enable)
220ab9bd 558{
bf383fb6
AD		 559 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
560 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 561}
562
563static const struct amdgpu_ip_block_version vega10_common_ip_block =
564{
565 .type = AMD_IP_BLOCK_TYPE_COMMON,
566 .major = 2,
567 .minor = 0,
568 .rev = 0,
569 .funcs = &soc15_common_ip_funcs,
570};
571
4cb0becb
HR		 572static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
573{
574 return adev->nbio_funcs->get_rev_id(adev);
575}
576
220ab9bd
KW		 577int soc15_set_ip_blocks(struct amdgpu_device *adev)
578{
4522824c
SL		 579 /* Set IP register base before any HW register access */
580 switch (adev->asic_type) {
581 case CHIP_VEGA10:
3084eb00 582 case CHIP_VEGA12:
4522824c
SL		 583 case CHIP_RAVEN:
584 vega10_reg_base_init(adev);
585 break;
8ee273e5
FX		 586 case CHIP_VEGA20:
587 vega20_reg_base_init(adev);
588 break;
e78705ec
LM		 589 case CHIP_ARCTURUS:
590 arct_reg_base_init(adev);
591 break;
4522824c
SL		 592 default:
593 return -EINVAL;
594 }
595
eb39aff7 596 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
47622ba0
AD		 597 adev->gmc.xgmi.supported = true;
598
bf383fb6
AD		 599 if (adev->flags & AMD_IS_APU)
600 adev->nbio_funcs = &nbio_v7_0_funcs;
0e54df05
LM		 601 else if (adev->asic_type == CHIP_VEGA20 ||
602 adev->asic_type == CHIP_ARCTURUS)
fe3c9489 603 adev->nbio_funcs = &nbio_v7_4_funcs;
bf383fb6
AD		 604 else
605 adev->nbio_funcs = &nbio_v6_1_funcs;
606
0e54df05 607 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
698758bb
FX		 608 adev->df_funcs = &df_v3_6_funcs;
609 else
610 adev->df_funcs = &df_v1_7_funcs;
4cb0becb
HR		 611
612 adev->rev_id = soc15_get_rev_id(adev);
bf383fb6 613 adev->nbio_funcs->detect_hw_virt(adev);
1b922423 614
f1a34465
XY		 615 if (amdgpu_sriov_vf(adev))
616 adev->virt.ops = &xgpu_ai_virt_ops;
617
220ab9bd
KW		 618 switch (adev->asic_type) {
619 case CHIP_VEGA10:
692069a1 620 case CHIP_VEGA12:
7c7af6c1 621 case CHIP_VEGA20:
2990a1fc
AD		 622 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
623 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2d11fd3f
TH		 624
625 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
626 if (amdgpu_sriov_vf(adev)) {
627 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
628 if (adev->asic_type == CHIP_VEGA20)
629 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
630 else
631 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
632 }
633 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
634 } else {
635 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
636 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
637 if (adev->asic_type == CHIP_VEGA20)
638 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
639 else
640 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
641 }
3680b2a5 642 }
009d9ed6
RZ		 643 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
644 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2da5410b 645 if (!amdgpu_sriov_vf(adev)) {
dc8e3a0c 646 if (is_support_sw_smu(adev))
2da5410b
HR		 647 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
648 else
649 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
650 }
f8445307 651 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 652 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 653#if defined(CONFIG_DRM_AMD_DC)
654 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 655 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a 656#endif
846311ae
FM		 657 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
658 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
659 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
660 }
220ab9bd 661 break;
1023b797 662 case CHIP_RAVEN:
40c2358b
HR		 663 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
664 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2990a1fc 665 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
3680b2a5
EQ		 666 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
667 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
009d9ed6
RZ		 668 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
669 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b905090d 670 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 671 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 672 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 673#if defined(CONFIG_DRM_AMD_DC)
674 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 675 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1 676#endif
2990a1fc 677 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 678 break;
0e54df05
LM		 679 case CHIP_ARCTURUS:
680 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
681 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
682 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
683 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
684 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
685 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
686 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
687 break;
220ab9bd
KW		 688 default:
689 return -EINVAL;
690 }
691
692 return 0;
693}
694
69882565 695static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 696{
69882565 697 adev->nbio_funcs->hdp_flush(adev, ring);
73c73240
AD		 698}
699
69882565
CK		 700static void soc15_invalidate_hdp(struct amdgpu_device *adev,
701 struct amdgpu_ring *ring)
73c73240 702{
69882565
CK		 703 if (!ring || !ring->funcs->emit_wreg)
704 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
705 else
706 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
707 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 708}
709
adbd4f89
AD		 710static bool soc15_need_full_reset(struct amdgpu_device *adev)
711{
712 /* change this when we implement soft reset */
713 return true;
714}
b45e18ac
KR		 715static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
716 uint64_t *count1)
717{
718 uint32_t perfctr = 0;
719 uint64_t cnt0_of, cnt1_of;
720 int tmp;
721
722 /* This reports 0 on APUs, so return to avoid writing/reading registers
723 * that may or may not be different from their GPU counterparts
724 */
0172591e
ES		 725 if (adev->flags & AMD_IS_APU)
726 return;
b45e18ac
KR		 727
728 /* Set the 2 events that we wish to watch, defined above */
9417f703 729 /* Reg 40 is # received msgs */
b45e18ac 730 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
9417f703
KR		 731 /* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
732 if (adev->asic_type == CHIP_VEGA20)
733 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
734 EVENT1_SEL, 108);
735 else
736 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
737 EVENT1_SEL, 104);
b45e18ac
KR		 738
739 /* Write to enable desired perf counters */
740 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
741 /* Zero out and enable the perf counters
742 * Write 0x5:
743 * Bit 0 = Start all counters(1)
744 * Bit 2 = Global counter reset enable(1)
745 */
746 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
747
748 msleep(1000);
749
750 /* Load the shadow and disable the perf counters
751 * Write 0x2:
752 * Bit 0 = Stop counters(0)
753 * Bit 1 = Load the shadow counters(1)
754 */
755 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
756
757 /* Read register values to get any >32bit overflow */
758 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
759 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
760 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
761
762 /* Get the values and add the overflow */
763 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
764 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
765}
adbd4f89 766
9281f12c
AD		 767static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
768{
769 u32 sol_reg;
770
d55f33da
AD		 771 /* Just return false for soc15 GPUs. Reset does not seem to
772 * be necessary.
773 */
394e9a14
ED		 774 if (!amdgpu_passthrough(adev))
775 return false;
d55f33da 776
9281f12c
AD		 777 if (adev->flags & AMD_IS_APU)
778 return false;
779
780 /* Check sOS sign of life register to confirm sys driver and sOS
781 * are already been loaded.
782 */
783 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
784 if (sol_reg)
785 return true;
786
787 return false;
788}
789
dcea6e65
KR		 790static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
791{
792 uint64_t nak_r, nak_g;
793
794 /* Get the number of NAKs received and generated */
795 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
796 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
797
798 /* Add the total number of NAKs, i.e the number of replays */
799 return (nak_r + nak_g);
800}
801
220ab9bd
KW		 802static const struct amdgpu_asic_funcs soc15_asic_funcs =
803{
804 .read_disabled_bios = &soc15_read_disabled_bios,
805 .read_bios_from_rom = &soc15_read_bios_from_rom,
806 .read_register = &soc15_read_register,
807 .reset = &soc15_asic_reset,
808 .set_vga_state = &soc15_vga_set_state,
809 .get_xclk = &soc15_get_xclk,
810 .set_uvd_clocks = &soc15_set_uvd_clocks,
811 .set_vce_clocks = &soc15_set_vce_clocks,
812 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 813 .flush_hdp = &soc15_flush_hdp,
814 .invalidate_hdp = &soc15_invalidate_hdp,
adbd4f89 815 .need_full_reset = &soc15_need_full_reset,
062f3807 816 .init_doorbell_index = &vega10_doorbell_index_init,
b45e18ac 817 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 818 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 819 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
220ab9bd
KW		 820};
821
c93aa775
OZ		 822static const struct amdgpu_asic_funcs vega20_asic_funcs =
823{
824 .read_disabled_bios = &soc15_read_disabled_bios,
825 .read_bios_from_rom = &soc15_read_bios_from_rom,
826 .read_register = &soc15_read_register,
827 .reset = &soc15_asic_reset,
828 .set_vga_state = &soc15_vga_set_state,
829 .get_xclk = &soc15_get_xclk,
830 .set_uvd_clocks = &soc15_set_uvd_clocks,
831 .set_vce_clocks = &soc15_set_vce_clocks,
832 .get_config_memsize = &soc15_get_config_memsize,
833 .flush_hdp = &soc15_flush_hdp,
834 .invalidate_hdp = &soc15_invalidate_hdp,
835 .need_full_reset = &soc15_need_full_reset,
836 .init_doorbell_index = &vega20_doorbell_index_init,
b45e18ac 837 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 838 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 839 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
220ab9bd
KW		 840};
841
842static int soc15_common_early_init(void *handle)
843{
88807dc8 844#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
220ab9bd
KW		 845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
846
88807dc8
OZ		 847 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
848 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
220ab9bd
KW		 849 adev->smc_rreg = NULL;
850 adev->smc_wreg = NULL;
851 adev->pcie_rreg = &soc15_pcie_rreg;
852 adev->pcie_wreg = &soc15_pcie_wreg;
853 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
854 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
855 adev->didt_rreg = &soc15_didt_rreg;
856 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 857 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
858 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 859 adev->se_cac_rreg = &soc15_se_cac_rreg;
860 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd 861
220ab9bd 862
220ab9bd
KW		 863 adev->external_rev_id = 0xFF;
864 switch (adev->asic_type) {
865 case CHIP_VEGA10:
c93aa775 866 adev->asic_funcs = &soc15_asic_funcs;
220ab9bd
KW		 867 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
868 AMD_CG_SUPPORT_GFX_MGLS |
869 AMD_CG_SUPPORT_GFX_RLC_LS |
870 AMD_CG_SUPPORT_GFX_CP_LS |
871 AMD_CG_SUPPORT_GFX_3D_CGCG |
872 AMD_CG_SUPPORT_GFX_3D_CGLS |
873 AMD_CG_SUPPORT_GFX_CGCG |
874 AMD_CG_SUPPORT_GFX_CGLS |
875 AMD_CG_SUPPORT_BIF_MGCG |
876 AMD_CG_SUPPORT_BIF_LS |
877 AMD_CG_SUPPORT_HDP_LS |
878 AMD_CG_SUPPORT_DRM_MGCG |
879 AMD_CG_SUPPORT_DRM_LS |
880 AMD_CG_SUPPORT_ROM_MGCG |
881 AMD_CG_SUPPORT_DF_MGCG |
882 AMD_CG_SUPPORT_SDMA_MGCG |
883 AMD_CG_SUPPORT_SDMA_LS |
884 AMD_CG_SUPPORT_MC_MGCG |
885 AMD_CG_SUPPORT_MC_LS;
886 adev->pg_flags = 0;
887 adev->external_rev_id = 0x1;
888 break;
692069a1 889 case CHIP_VEGA12:
c93aa775 890 adev->asic_funcs = &soc15_asic_funcs;
e4a38755
EQ		 891 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
892 AMD_CG_SUPPORT_GFX_MGLS |
893 AMD_CG_SUPPORT_GFX_CGCG |
894 AMD_CG_SUPPORT_GFX_CGLS |
895 AMD_CG_SUPPORT_GFX_3D_CGCG |
896 AMD_CG_SUPPORT_GFX_3D_CGLS |
897 AMD_CG_SUPPORT_GFX_CP_LS |
898 AMD_CG_SUPPORT_MC_LS |
899 AMD_CG_SUPPORT_MC_MGCG |
900 AMD_CG_SUPPORT_SDMA_MGCG |
901 AMD_CG_SUPPORT_SDMA_LS |
902 AMD_CG_SUPPORT_BIF_MGCG |
903 AMD_CG_SUPPORT_BIF_LS |
904 AMD_CG_SUPPORT_HDP_MGCG |
905 AMD_CG_SUPPORT_HDP_LS |
906 AMD_CG_SUPPORT_ROM_MGCG |
907 AMD_CG_SUPPORT_VCE_MGCG |
908 AMD_CG_SUPPORT_UVD_MGCG;
692069a1 909 adev->pg_flags = 0;
f559fe2b 910 adev->external_rev_id = adev->rev_id + 0x14;
692069a1 911 break;
935be7a0 912 case CHIP_VEGA20:
c93aa775 913 adev->asic_funcs = &vega20_asic_funcs;
3fdbab5f
EQ		 914 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
915 AMD_CG_SUPPORT_GFX_MGLS |
916 AMD_CG_SUPPORT_GFX_CGCG |
917 AMD_CG_SUPPORT_GFX_CGLS |
918 AMD_CG_SUPPORT_GFX_3D_CGCG |
919 AMD_CG_SUPPORT_GFX_3D_CGLS |
920 AMD_CG_SUPPORT_GFX_CP_LS |
921 AMD_CG_SUPPORT_MC_LS |
922 AMD_CG_SUPPORT_MC_MGCG |
923 AMD_CG_SUPPORT_SDMA_MGCG |
924 AMD_CG_SUPPORT_SDMA_LS |
925 AMD_CG_SUPPORT_BIF_MGCG |
926 AMD_CG_SUPPORT_BIF_LS |
927 AMD_CG_SUPPORT_HDP_MGCG |
102e4940 928 AMD_CG_SUPPORT_HDP_LS |
3fdbab5f
EQ		 929 AMD_CG_SUPPORT_ROM_MGCG |
930 AMD_CG_SUPPORT_VCE_MGCG |
931 AMD_CG_SUPPORT_UVD_MGCG;
935be7a0
FX		 932 adev->pg_flags = 0;
933 adev->external_rev_id = adev->rev_id + 0x28;
934 break;
957c6fe1 935 case CHIP_RAVEN:
c93aa775 936 adev->asic_funcs = &soc15_asic_funcs;
520cbe0f 937 if (adev->rev_id >= 0x8)
7e4545d3 938 adev->external_rev_id = adev->rev_id + 0x79;
741deade
AD		 939 else if (adev->pdev->device == 0x15d8)
940 adev->external_rev_id = adev->rev_id + 0x41;
7e4545d3
HR		 941 else if (adev->rev_id == 1)
942 adev->external_rev_id = adev->rev_id + 0x20;
741deade 943 else
7e4545d3 944 adev->external_rev_id = adev->rev_id + 0x01;
741deade
AD		 945
946 if (adev->rev_id >= 0x8) {
520cbe0f
HR		 947 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
948 AMD_CG_SUPPORT_GFX_MGLS |
949 AMD_CG_SUPPORT_GFX_CP_LS |
950 AMD_CG_SUPPORT_GFX_3D_CGCG |
951 AMD_CG_SUPPORT_GFX_3D_CGLS |
952 AMD_CG_SUPPORT_GFX_CGCG |
953 AMD_CG_SUPPORT_GFX_CGLS |
954 AMD_CG_SUPPORT_BIF_LS |
955 AMD_CG_SUPPORT_HDP_LS |
956 AMD_CG_SUPPORT_ROM_MGCG |
957 AMD_CG_SUPPORT_MC_MGCG |
958 AMD_CG_SUPPORT_MC_LS |
959 AMD_CG_SUPPORT_SDMA_MGCG |
960 AMD_CG_SUPPORT_SDMA_LS |
961 AMD_CG_SUPPORT_VCN_MGCG;
741deade
AD		 962
963 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
964 } else if (adev->pdev->device == 0x15d8) {
fced5c70
LG		 965 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
966 AMD_CG_SUPPORT_GFX_MGLS |
741deade
AD		 967 AMD_CG_SUPPORT_GFX_CP_LS |
968 AMD_CG_SUPPORT_GFX_3D_CGCG |
969 AMD_CG_SUPPORT_GFX_3D_CGLS |
970 AMD_CG_SUPPORT_GFX_CGCG |
971 AMD_CG_SUPPORT_GFX_CGLS |
972 AMD_CG_SUPPORT_BIF_LS |
973 AMD_CG_SUPPORT_HDP_LS |
974 AMD_CG_SUPPORT_ROM_MGCG |
975 AMD_CG_SUPPORT_MC_MGCG |
976 AMD_CG_SUPPORT_MC_LS |
977 AMD_CG_SUPPORT_SDMA_MGCG |
978 AMD_CG_SUPPORT_SDMA_LS;
979
980 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
981 AMD_PG_SUPPORT_MMHUB |
a3716d3a
JZ		 982 AMD_PG_SUPPORT_VCN |
983 AMD_PG_SUPPORT_VCN_DPG;
741deade 984 } else {
520cbe0f
HR		 985 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
986 AMD_CG_SUPPORT_GFX_MGLS |
987 AMD_CG_SUPPORT_GFX_RLC_LS |
988 AMD_CG_SUPPORT_GFX_CP_LS |
989 AMD_CG_SUPPORT_GFX_3D_CGCG |
990 AMD_CG_SUPPORT_GFX_3D_CGLS |
991 AMD_CG_SUPPORT_GFX_CGCG |
992 AMD_CG_SUPPORT_GFX_CGLS |
993 AMD_CG_SUPPORT_BIF_MGCG |
994 AMD_CG_SUPPORT_BIF_LS |
995 AMD_CG_SUPPORT_HDP_MGCG |
996 AMD_CG_SUPPORT_HDP_LS |
997 AMD_CG_SUPPORT_DRM_MGCG |
998 AMD_CG_SUPPORT_DRM_LS |
999 AMD_CG_SUPPORT_ROM_MGCG |
1000 AMD_CG_SUPPORT_MC_MGCG |
1001 AMD_CG_SUPPORT_MC_LS |
1002 AMD_CG_SUPPORT_SDMA_MGCG |
1003 AMD_CG_SUPPORT_SDMA_LS |
1004 AMD_CG_SUPPORT_VCN_MGCG;
61c8e90d 1005
741deade
AD		 1006 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1007 }
a4494fda 1008
3b94fb10 1009 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
8c7bf583
KF		 1010 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1011 AMD_PG_SUPPORT_CP |
1012 AMD_PG_SUPPORT_RLC_SMU_HS;
ad5a67a7 1013 break;
0e54df05 1014 case CHIP_ARCTURUS:
7f40581c 1015 adev->asic_funcs = &vega20_asic_funcs;
0e54df05
LM		 1016 adev->cg_flags = 0;
1017 adev->pg_flags = 0;
1018 break;
220ab9bd
KW		 1019 default:
1020 /* FIXME: not supported yet */
1021 return -EINVAL;
1022 }
1023
ab276632
XY		 1024 if (amdgpu_sriov_vf(adev)) {
1025 amdgpu_virt_init_setting(adev);
1026 xgpu_ai_mailbox_set_irq_funcs(adev);
1027 }
1028
220ab9bd
KW		 1029 return 0;
1030}
1031
81758c55
ML		 1032static int soc15_common_late_init(void *handle)
1033{
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036 if (amdgpu_sriov_vf(adev))
1037 xgpu_ai_mailbox_get_irq(adev);
1038
1039 return 0;
1040}
1041
220ab9bd
KW		 1042static int soc15_common_sw_init(void *handle)
1043{
81758c55
ML		 1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045
1046 if (amdgpu_sriov_vf(adev))
1047 xgpu_ai_mailbox_add_irq_id(adev);
1048
e4cf4bf5
JK		 1049 adev->df_funcs->sw_init(adev);
1050
220ab9bd
KW		 1051 return 0;
1052}
1053
1054static int soc15_common_sw_fini(void *handle)
1055{
1056 return 0;
1057}
1058
7c94bc82
OZ		 1059static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1060{
1061 int i;
1062 struct amdgpu_ring *ring;
1063
98cad2de
TH		 1064 /* Two reasons to skip
1065 * 1, Host driver already programmed them
1066 * 2, To avoid registers program violations in SR-IOV
1067 */
1068 if (!amdgpu_virt_support_skip_setting(adev)) {
1069 for (i = 0; i < adev->sdma.num_instances; i++) {
1070 ring = &adev->sdma.instance[i].ring;
1071 adev->nbio_funcs->sdma_doorbell_range(adev, i,
1072 ring->use_doorbell, ring->doorbell_index,
1073 adev->doorbell_index.sdma_doorbell_range);
1074 }
7c94bc82
OZ		 1075 }
1076
1077 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1078 adev->irq.ih.doorbell_index);
1079}
1080
220ab9bd
KW		 1081static int soc15_common_hw_init(void *handle)
1082{
1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
220ab9bd
KW		 1085 /* enable pcie gen2/3 link */
1086 soc15_pcie_gen3_enable(adev);
1087 /* enable aspm */
1088 soc15_program_aspm(adev);
833fa075 1089 /* setup nbio registers */
bf383fb6 1090 adev->nbio_funcs->init_registers(adev);
88807dc8
OZ		 1091 /* remap HDP registers to a hole in mmio space,
1092 * for the purpose of expose those registers
1093 * to process space
1094 */
1095 if (adev->nbio_funcs->remap_hdp_registers)
1096 adev->nbio_funcs->remap_hdp_registers(adev);
e4cf4bf5 1097
220ab9bd
KW		 1098 /* enable the doorbell aperture */
1099 soc15_enable_doorbell_aperture(adev, true);
7c94bc82
OZ		 1100 /* HW doorbell routing policy: doorbell writing not
1101 * in SDMA/IH/MM/ACV range will be routed to CP. So
1102 * we need to init SDMA/IH/MM/ACV doorbell range prior
1103 * to CP ip block init and ring test.
1104 */
1105 soc15_doorbell_range_init(adev);
220ab9bd
KW		 1106
1107 return 0;
1108}
1109
1110static int soc15_common_hw_fini(void *handle)
1111{
1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113
1114 /* disable the doorbell aperture */
1115 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 1116 if (amdgpu_sriov_vf(adev))
1117 xgpu_ai_mailbox_put_irq(adev);
220ab9bd
KW		 1118
1119 return 0;
1120}
1121
1122static int soc15_common_suspend(void *handle)
1123{
1124 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1125
1126 return soc15_common_hw_fini(adev);
1127}
1128
1129static int soc15_common_resume(void *handle)
1130{
1131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1132
1133 return soc15_common_hw_init(adev);
1134}
1135
1136static bool soc15_common_is_idle(void *handle)
1137{
1138 return true;
1139}
1140
1141static int soc15_common_wait_for_idle(void *handle)
1142{
1143 return 0;
1144}
1145
1146static int soc15_common_soft_reset(void *handle)
1147{
1148 return 0;
1149}
1150
1151static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1152{
1153 uint32_t def, data;
1154
a5d0f456
KF		 1155 if (adev->asic_type == CHIP_VEGA20) {
1156 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
220ab9bd 1157
a5d0f456
KF		 1158 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1159 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1160 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1161 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1162 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1163 else
1164 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1165 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1166 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1167 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
220ab9bd 1168
a5d0f456
KF		 1169 if (def != data)
1170 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1171 } else {
1172 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1173
1174 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1175 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1176 else
1177 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1178
1179 if (def != data)
1180 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1181 }
220ab9bd
KW		 1182}
1183
1184static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1185{
1186 uint32_t def, data;
1187
1188 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1189
1190 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1191 data &= ~(0x01000000 |
1192 0x02000000 |
1193 0x04000000 |
1194 0x08000000 |
1195 0x10000000 |
1196 0x20000000 |
1197 0x40000000 |
1198 0x80000000);
1199 else
1200 data |= (0x01000000 |
1201 0x02000000 |
1202 0x04000000 |
1203 0x08000000 |
1204 0x10000000 |
1205 0x20000000 |
1206 0x40000000 |
1207 0x80000000);
1208
1209 if (def != data)
1210 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1211}
1212
1213static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1214{
1215 uint32_t def, data;
1216
1217 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1218
1219 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1220 data |= 1;
1221 else
1222 data &= ~1;
1223
1224 if (def != data)
1225 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1226}
1227
1228static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1229 bool enable)
1230{
1231 uint32_t def, data;
1232
1233 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1234
1235 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1236 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1237 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1238 else
1239 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1240 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1241
1242 if (def != data)
1243 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1244}
1245
220ab9bd
KW		 1246static int soc15_common_set_clockgating_state(void *handle,
1247 enum amd_clockgating_state state)
1248{
1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250
6e9dc861
ML		 1251 if (amdgpu_sriov_vf(adev))
1252 return 0;
1253
220ab9bd
KW		 1254 switch (adev->asic_type) {
1255 case CHIP_VEGA10:
692069a1 1256 case CHIP_VEGA12:
f980d127 1257 case CHIP_VEGA20:
bf383fb6 1258 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
220ab9bd 1259 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1260 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 1261 state == AMD_CG_STATE_GATE ? true : false);
1262 soc15_update_hdp_light_sleep(adev,
1263 state == AMD_CG_STATE_GATE ? true : false);
1264 soc15_update_drm_clock_gating(adev,
1265 state == AMD_CG_STATE_GATE ? true : false);
1266 soc15_update_drm_light_sleep(adev,
1267 state == AMD_CG_STATE_GATE ? true : false);
1268 soc15_update_rom_medium_grain_clock_gating(adev,
1269 state == AMD_CG_STATE_GATE ? true : false);
070706c0 1270 adev->df_funcs->update_medium_grain_clock_gating(adev,
220ab9bd
KW		 1271 state == AMD_CG_STATE_GATE ? true : false);
1272 break;
9e5a9eb4 1273 case CHIP_RAVEN:
bf383fb6 1274 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 1275 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1276 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 1277 state == AMD_CG_STATE_GATE ? true : false);
1278 soc15_update_hdp_light_sleep(adev,
1279 state == AMD_CG_STATE_GATE ? true : false);
1280 soc15_update_drm_clock_gating(adev,
1281 state == AMD_CG_STATE_GATE ? true : false);
1282 soc15_update_drm_light_sleep(adev,
1283 state == AMD_CG_STATE_GATE ? true : false);
1284 soc15_update_rom_medium_grain_clock_gating(adev,
1285 state == AMD_CG_STATE_GATE ? true : false);
1286 break;
220ab9bd
KW		 1287 default:
1288 break;
1289 }
1290 return 0;
1291}
1292
f9abe35c
HR		 1293static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1294{
1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296 int data;
1297
1298 if (amdgpu_sriov_vf(adev))
1299 *flags = 0;
1300
bf383fb6 1301 adev->nbio_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1302
1303 /* AMD_CG_SUPPORT_HDP_LS */
1304 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1305 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1306 *flags |= AMD_CG_SUPPORT_HDP_LS;
1307
1308 /* AMD_CG_SUPPORT_DRM_MGCG */
1309 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1310 if (!(data & 0x01000000))
1311 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1312
1313 /* AMD_CG_SUPPORT_DRM_LS */
1314 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1315 if (data & 0x1)
1316 *flags |= AMD_CG_SUPPORT_DRM_LS;
1317
1318 /* AMD_CG_SUPPORT_ROM_MGCG */
1319 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1320 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1321 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1322
070706c0 1323 adev->df_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1324}
1325
220ab9bd
KW		 1326static int soc15_common_set_powergating_state(void *handle,
1327 enum amd_powergating_state state)
1328{
1329 /* todo */
1330 return 0;
1331}
1332
1333const struct amd_ip_funcs soc15_common_ip_funcs = {
1334 .name = "soc15_common",
1335 .early_init = soc15_common_early_init,
81758c55 1336 .late_init = soc15_common_late_init,
220ab9bd
KW		 1337 .sw_init = soc15_common_sw_init,
1338 .sw_fini = soc15_common_sw_fini,
1339 .hw_init = soc15_common_hw_init,
1340 .hw_fini = soc15_common_hw_fini,
1341 .suspend = soc15_common_suspend,
1342 .resume = soc15_common_resume,
1343 .is_idle = soc15_common_is_idle,
1344 .wait_for_idle = soc15_common_wait_for_idle,
1345 .soft_reset = soc15_common_soft_reset,
1346 .set_clockgating_state = soc15_common_set_clockgating_state,
1347 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 1348 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 1349};
Linux 6.x block layer and io_uring tree(s)