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drm/amd/powerplay: retrieve the enabled feature mask from cache
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
47b757fb
SR		 26#include <linux/pci.h>
27
220ab9bd 28#include "amdgpu.h"
d05da0e2 29#include "amdgpu_atombios.h"
220ab9bd
KW		 30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "atom.h"
36#include "amd_pcie.h"
37
5d735f83 38#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 39#include "gc/gc_9_0_offset.h"
40#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 41#include "sdma0/sdma0_4_0_offset.h"
42#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 43#include "hdp/hdp_4_0_offset.h"
44#include "hdp/hdp_4_0_sh_mask.h"
424d9bb4
FX		 45#include "smuio/smuio_9_0_offset.h"
46#include "smuio/smuio_9_0_sh_mask.h"
b45e18ac 47#include "nbio/nbio_7_0_default.h"
88807dc8 48#include "nbio/nbio_7_0_offset.h"
b45e18ac
KR		 49#include "nbio/nbio_7_0_sh_mask.h"
50#include "nbio/nbio_7_0_smn.h"
9281f12c 51#include "mp/mp_9_0_offset.h"
220ab9bd
KW		 52
53#include "soc15.h"
54#include "soc15_common.h"
55#include "gfx_v9_0.h"
56#include "gmc_v9_0.h"
57#include "gfxhub_v1_0.h"
58#include "mmhub_v1_0.h"
070706c0 59#include "df_v1_7.h"
698758bb 60#include "df_v3_6.h"
bebc0762
HZ		 61#include "nbio_v6_1.h"
62#include "nbio_v7_0.h"
63#include "nbio_v7_4.h"
220ab9bd
KW		 64#include "vega10_ih.h"
65#include "sdma_v4_0.h"
66#include "uvd_v7_0.h"
67#include "vce_v4_0.h"
f2d7e707 68#include "vcn_v1_0.h"
279ba48e 69#include "vcn_v2_0.h"
5be45a26 70#include "jpeg_v2_0.h"
08249a3a 71#include "vcn_v2_5.h"
8c74e590 72#include "jpeg_v2_5.h"
796b6568 73#include "dce_virtual.h"
f1a34465 74#include "mxgpu_ai.h"
2da5410b 75#include "amdgpu_smu.h"
e74609cb
AD		 76#include "amdgpu_ras.h"
77#include "amdgpu_xgmi.h"
88807dc8 78#include <uapi/linux/kfd_ioctl.h>
220ab9bd 79
220ab9bd
KW		 80#define mmMP0_MISC_CGTT_CTRL0 0x01b9
81#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
84
a5d0f456
KF		 85/* for Vega20 register name change */
86#define mmHDP_MEM_POWER_CTRL 0x00d4
87#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
220ab9bd
KW		 92/*
93 * Indirect registers accessor
94 */
95static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
96{
97 unsigned long flags, address, data;
98 u32 r;
bebc0762
HZ		 99 address = adev->nbio.funcs->get_pcie_index_offset(adev);
100 data = adev->nbio.funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 101
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
103 WREG32(address, reg);
104 (void)RREG32(address);
105 r = RREG32(data);
106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
107 return r;
108}
109
110static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
111{
112 unsigned long flags, address, data;
220ab9bd 113
bebc0762
HZ		 114 address = adev->nbio.funcs->get_pcie_index_offset(adev);
115 data = adev->nbio.funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 116
117 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
118 WREG32(address, reg);
119 (void)RREG32(address);
120 WREG32(data, v);
121 (void)RREG32(data);
122 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
123}
124
4fa1c6a6
TZ		 125static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
126{
127 unsigned long flags, address, data;
128 u64 r;
bebc0762
HZ		 129 address = adev->nbio.funcs->get_pcie_index_offset(adev);
130 data = adev->nbio.funcs->get_pcie_data_offset(adev);
4fa1c6a6
TZ		 131
132 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
133 /* read low 32 bit */
134 WREG32(address, reg);
135 (void)RREG32(address);
136 r = RREG32(data);
137
138 /* read high 32 bit*/
139 WREG32(address, reg + 4);
140 (void)RREG32(address);
141 r |= ((u64)RREG32(data) << 32);
142 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
143 return r;
144}
145
146static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
147{
148 unsigned long flags, address, data;
149
bebc0762
HZ		 150 address = adev->nbio.funcs->get_pcie_index_offset(adev);
151 data = adev->nbio.funcs->get_pcie_data_offset(adev);
4fa1c6a6
TZ		 152
153 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
154 /* write low 32 bit */
155 WREG32(address, reg);
156 (void)RREG32(address);
157 WREG32(data, (u32)(v & 0xffffffffULL));
158 (void)RREG32(data);
159
160 /* write high 32 bit */
161 WREG32(address, reg + 4);
162 (void)RREG32(address);
163 WREG32(data, (u32)(v >> 32));
164 (void)RREG32(data);
165 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
166}
167
220ab9bd
KW		 168static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
169{
170 unsigned long flags, address, data;
171 u32 r;
172
173 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
174 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
175
176 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
177 WREG32(address, ((reg) & 0x1ff));
178 r = RREG32(data);
179 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
180 return r;
181}
182
183static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
184{
185 unsigned long flags, address, data;
186
187 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
188 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
189
190 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
191 WREG32(address, ((reg) & 0x1ff));
192 WREG32(data, (v));
193 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
194}
195
196static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
197{
198 unsigned long flags, address, data;
199 u32 r;
200
201 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
202 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
203
204 spin_lock_irqsave(&adev->didt_idx_lock, flags);
205 WREG32(address, (reg));
206 r = RREG32(data);
207 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
208 return r;
209}
210
211static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
212{
213 unsigned long flags, address, data;
214
215 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
216 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
217
218 spin_lock_irqsave(&adev->didt_idx_lock, flags);
219 WREG32(address, (reg));
220 WREG32(data, (v));
221 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
222}
223
560460f2
EQ		 224static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
225{
226 unsigned long flags;
227 u32 r;
228
229 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
231 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
232 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
233 return r;
234}
235
236static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
237{
238 unsigned long flags;
239
240 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
241 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
242 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
243 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
244}
245
2f11fb02
EQ		 246static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
247{
248 unsigned long flags;
249 u32 r;
250
251 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
252 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
253 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
254 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
255 return r;
256}
257
258static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
259{
260 unsigned long flags;
261
262 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
263 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
264 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
265 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
266}
267
220ab9bd
KW		 268static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
269{
bebc0762 270 return adev->nbio.funcs->get_memsize(adev);
220ab9bd
KW		 271}
272
220ab9bd
KW		 273static u32 soc15_get_xclk(struct amdgpu_device *adev)
274{
76d6172b 275 return adev->clock.spll.reference_freq;
220ab9bd
KW		 276}
277
278
279void soc15_grbm_select(struct amdgpu_device *adev,
280 u32 me, u32 pipe, u32 queue, u32 vmid)
281{
282 u32 grbm_gfx_cntl = 0;
283 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
284 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
285 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
286 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
287
1bff7f6c 288 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
220ab9bd
KW		 289}
290
291static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
292{
293 /* todo */
294}
295
296static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
297{
298 /* todo */
299 return false;
300}
301
302static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
303 u8 *bios, u32 length_bytes)
304{
305 u32 *dw_ptr;
306 u32 i, length_dw;
307
308 if (bios == NULL)
309 return false;
310 if (length_bytes == 0)
311 return false;
312 /* APU vbios image is part of sbios image */
313 if (adev->flags & AMD_IS_APU)
314 return false;
315
316 dw_ptr = (u32 *)bios;
317 length_dw = ALIGN(length_bytes, 4) / 4;
318
319 /* set rom index to 0 */
320 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
321 /* read out the rom data */
322 for (i = 0; i < length_dw; i++)
323 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
324
325 return true;
326}
327
946a4d5b
SL		 328static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
329 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
330 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
331 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
332 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
333 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
335 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
336 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
337 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
338 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
339 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
340 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
341 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
342 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
343 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
664fe85a 344 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
946a4d5b
SL		 345 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
347 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
5eeae247 348 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
220ab9bd
KW		 349};
350
351static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
352 u32 sh_num, u32 reg_offset)
353{
354 uint32_t val;
355
356 mutex_lock(&adev->grbm_idx_mutex);
357 if (se_num != 0xffffffff || sh_num != 0xffffffff)
358 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
359
360 val = RREG32(reg_offset);
361
362 if (se_num != 0xffffffff || sh_num != 0xffffffff)
363 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
364 mutex_unlock(&adev->grbm_idx_mutex);
365 return val;
366}
367
c013cea2
AD		 368static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
369 bool indexed, u32 se_num,
370 u32 sh_num, u32 reg_offset)
371{
372 if (indexed) {
373 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
374 } else {
cd29253f 375 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 376 return adev->gfx.config.gb_addr_config;
5eeae247
AD		 377 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
378 return adev->gfx.config.db_debug2;
cd29253f 379 return RREG32(reg_offset);
c013cea2
AD		 380 }
381}
382
220ab9bd
KW		 383static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
384 u32 sh_num, u32 reg_offset, u32 *value)
385{
3032f350 386 uint32_t i;
946a4d5b 387 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 388
389 *value = 0;
220ab9bd 390 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 391 en = &soc15_allowed_read_registers[i];
392 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
393 + en->reg_offset))
220ab9bd
KW		 394 continue;
395
97fcc76b
CK		 396 *value = soc15_get_register_value(adev,
397 soc15_allowed_read_registers[i].grbm_indexed,
398 se_num, sh_num, reg_offset);
220ab9bd
KW		 399 return 0;
400 }
401 return -EINVAL;
402}
403
946a4d5b
SL		 404
405/**
406 * soc15_program_register_sequence - program an array of registers.
407 *
408 * @adev: amdgpu_device pointer
409 * @regs: pointer to the register array
410 * @array_size: size of the register array
411 *
412 * Programs an array or registers with and and or masks.
413 * This is a helper for setting golden registers.
414 */
415
416void soc15_program_register_sequence(struct amdgpu_device *adev,
417 const struct soc15_reg_golden *regs,
418 const u32 array_size)
419{
420 const struct soc15_reg_golden *entry;
421 u32 tmp, reg;
422 int i;
423
424 for (i = 0; i < array_size; ++i) {
425 entry = &regs[i];
426 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
427
428 if (entry->and_mask == 0xffffffff) {
429 tmp = entry->or_mask;
430 } else {
431 tmp = RREG32(reg);
432 tmp &= ~(entry->and_mask);
e0d07657 433 tmp |= (entry->or_mask & entry->and_mask);
946a4d5b 434 }
1bff7f6c
TH		 435
436 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
437 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
438 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
439 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
440 WREG32_RLC(reg, tmp);
441 else
442 WREG32(reg, tmp);
443
946a4d5b
SL		 444 }
445
446}
447
e2b6d053 448static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
220ab9bd
KW		 449{
450 u32 i;
39fee32b 451 int ret = 0;
220ab9bd 452
98512bb8
KW		 453 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
454
e2b6d053 455 dev_info(adev->dev, "GPU mode1 reset\n");
220ab9bd
KW		 456
457 /* disable BM */
458 pci_clear_master(adev->pdev);
220ab9bd 459
98512bb8
KW		 460 pci_save_state(adev->pdev);
461
39fee32b
EQ		 462 ret = psp_gpu_reset(adev);
463 if (ret)
464 dev_err(adev->dev, "GPU mode1 reset failed\n");
98512bb8
KW		 465
466 pci_restore_state(adev->pdev);
220ab9bd
KW		 467
468 /* wait for asic to come out of reset */
469 for (i = 0; i < adev->usec_timeout; i++) {
bebc0762 470 u32 memsize = adev->nbio.funcs->get_memsize(adev);
bf383fb6 471
aecbe64f 472 if (memsize != 0xffffffff)
220ab9bd
KW		 473 break;
474 udelay(1);
475 }
476
d05da0e2 477 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd 478
39fee32b 479 return ret;
220ab9bd
KW		 480}
481
e2b6d053
JQ		 482static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
483{
5337aae9
AD		 484 if (is_support_sw_smu(adev)) {
485 struct smu_context *smu = &adev->smu;
e2b6d053 486
5337aae9
AD		 487 *cap = smu_baco_is_support(smu);
488 return 0;
489 } else {
490 void *pp_handle = adev->powerplay.pp_handle;
491 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
492
493 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
494 *cap = false;
495 return -ENOENT;
496 }
e2b6d053 497
5337aae9
AD		 498 return pp_funcs->get_asic_baco_capability(pp_handle, cap);
499 }
e2b6d053
JQ		 500}
501
502static int soc15_asic_baco_reset(struct amdgpu_device *adev)
503{
956f6705 504 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
e2b6d053 505
956f6705
LM		 506 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
507 if (ras && ras->supported)
508 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
509
5337aae9
AD		 510 dev_info(adev->dev, "GPU BACO reset\n");
511
512 if (is_support_sw_smu(adev)) {
513 struct smu_context *smu = &adev->smu;
11520f27 514 int ret;
5337aae9 515
11520f27
AD		 516 ret = smu_baco_enter(smu);
517 if (ret)
518 return ret;
519
520 ret = smu_baco_exit(smu);
521 if (ret)
522 return ret;
5337aae9
AD		 523 } else {
524 void *pp_handle = adev->powerplay.pp_handle;
525 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
526
527 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
528 return -ENOENT;
e2b6d053 529
5337aae9
AD		 530 /* enter BACO state */
531 if (pp_funcs->set_asic_baco_state(pp_handle, 1))
532 return -EIO;
533
534 /* exit BACO state */
535 if (pp_funcs->set_asic_baco_state(pp_handle, 0))
536 return -EIO;
537 }
e2b6d053 538
956f6705
LM		 539 /* re-enable doorbell interrupt after BACO exit */
540 if (ras && ras->supported)
541 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
542
e2b6d053
JQ		 543 return 0;
544}
545
c43b849f
AG		 546static int soc15_mode2_reset(struct amdgpu_device *adev)
547{
90a08351 548 if (is_support_sw_smu(adev))
549 return smu_mode2_reset(&adev->smu);
c43b849f
AG		 550 if (!adev->powerplay.pp_funcs ||
551 !adev->powerplay.pp_funcs->asic_reset_mode_2)
552 return -ENOENT;
553
554 return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
555}
556
ee360c0b
AD		 557static enum amd_reset_method
558soc15_asic_reset_method(struct amdgpu_device *adev)
e2b6d053 559{
feffbaac
LM		 560 bool baco_reset = false;
561 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
e2b6d053
JQ		 562
563 switch (adev->asic_type) {
ee360c0b 564 case CHIP_RAVEN:
90a08351 565 case CHIP_RENOIR:
ee360c0b 566 return AMD_RESET_METHOD_MODE2;
e2b6d053 567 case CHIP_VEGA10:
f8b18cf4 568 case CHIP_VEGA12:
0a650c1d 569 case CHIP_ARCTURUS:
e2b6d053
JQ		 570 soc15_asic_get_baco_capability(adev, &baco_reset);
571 break;
017d75f1
EQ		 572 case CHIP_VEGA20:
573 if (adev->psp.sos_fw_version >= 0x80067)
574 soc15_asic_get_baco_capability(adev, &baco_reset);
e74609cb 575
feffbaac
LM		 576 /*
577 * 1. PMFW version > 0x284300: all cases use baco
578 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
579 */
580 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
581 baco_reset = false;
017d75f1 582 break;
e2b6d053 583 default:
e2b6d053
JQ		 584 break;
585 }
586
587 if (baco_reset)
ee360c0b
AD		 588 return AMD_RESET_METHOD_BACO;
589 else
590 return AMD_RESET_METHOD_MODE1;
591}
592
593static int soc15_asic_reset(struct amdgpu_device *adev)
594{
c43b849f
AG		 595 switch (soc15_asic_reset_method(adev)) {
596 case AMD_RESET_METHOD_BACO:
2c9a0c66
AD		 597 if (!adev->in_suspend)
598 amdgpu_inc_vram_lost(adev);
c43b849f
AG		 599 return soc15_asic_baco_reset(adev);
600 case AMD_RESET_METHOD_MODE2:
601 return soc15_mode2_reset(adev);
602 default:
2c9a0c66
AD		 603 if (!adev->in_suspend)
604 amdgpu_inc_vram_lost(adev);
c43b849f
AG		 605 return soc15_asic_mode1_reset(adev);
606 }
e2b6d053
JQ		 607}
608
988eb9ff
AD		 609static bool soc15_supports_baco(struct amdgpu_device *adev)
610{
611 bool baco_support;
612
613 switch (adev->asic_type) {
614 case CHIP_VEGA10:
615 case CHIP_VEGA12:
b8ab58f3 616 case CHIP_ARCTURUS:
988eb9ff
AD		 617 soc15_asic_get_baco_capability(adev, &baco_support);
618 break;
619 case CHIP_VEGA20:
620 if (adev->psp.sos_fw_version >= 0x80067)
621 soc15_asic_get_baco_capability(adev, &baco_support);
622 else
623 baco_support = false;
624 break;
625 default:
626 return false;
627 }
628
629 return baco_support;
630}
631
220ab9bd
KW		 632/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
633 u32 cntl_reg, u32 status_reg)
634{
635 return 0;
636}*/
637
638static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
639{
640 /*int r;
641
642 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
643 if (r)
644 return r;
645
646 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
647 */
648 return 0;
649}
650
651static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
652{
653 /* todo */
654
655 return 0;
656}
657
658static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
659{
660 if (pci_is_root_bus(adev->pdev->bus))
661 return;
662
663 if (amdgpu_pcie_gen2 == 0)
664 return;
665
666 if (adev->flags & AMD_IS_APU)
667 return;
668
669 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
670 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
671 return;
672
673 /* todo */
674}
675
676static void soc15_program_aspm(struct amdgpu_device *adev)
677{
678
679 if (amdgpu_aspm == 0)
680 return;
681
682 /* todo */
683}
684
685static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 686 bool enable)
220ab9bd 687{
bebc0762
HZ		 688 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
689 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 690}
691
692static const struct amdgpu_ip_block_version vega10_common_ip_block =
693{
694 .type = AMD_IP_BLOCK_TYPE_COMMON,
695 .major = 2,
696 .minor = 0,
697 .rev = 0,
698 .funcs = &soc15_common_ip_funcs,
699};
700
4cb0becb
HR		 701static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
702{
bebc0762 703 return adev->nbio.funcs->get_rev_id(adev);
4cb0becb
HR		 704}
705
220ab9bd
KW		 706int soc15_set_ip_blocks(struct amdgpu_device *adev)
707{
4522824c
SL		 708 /* Set IP register base before any HW register access */
709 switch (adev->asic_type) {
710 case CHIP_VEGA10:
3084eb00 711 case CHIP_VEGA12:
4522824c 712 case CHIP_RAVEN:
080deab6 713 case CHIP_RENOIR:
4522824c
SL		 714 vega10_reg_base_init(adev);
715 break;
8ee273e5
FX		 716 case CHIP_VEGA20:
717 vega20_reg_base_init(adev);
718 break;
e78705ec
LM		 719 case CHIP_ARCTURUS:
720 arct_reg_base_init(adev);
721 break;
4522824c
SL		 722 default:
723 return -EINVAL;
724 }
725
eb39aff7 726 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
47622ba0
AD		 727 adev->gmc.xgmi.supported = true;
728
bebc0762
HZ		 729 if (adev->flags & AMD_IS_APU) {
730 adev->nbio.funcs = &nbio_v7_0_funcs;
731 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
732 } else if (adev->asic_type == CHIP_VEGA20 ||
733 adev->asic_type == CHIP_ARCTURUS) {
734 adev->nbio.funcs = &nbio_v7_4_funcs;
735 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
736 } else {
737 adev->nbio.funcs = &nbio_v6_1_funcs;
738 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
739 }
bf383fb6 740
0e54df05 741 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
698758bb
FX		 742 adev->df_funcs = &df_v3_6_funcs;
743 else
744 adev->df_funcs = &df_v1_7_funcs;
4cb0becb
HR		 745
746 adev->rev_id = soc15_get_rev_id(adev);
bebc0762 747 adev->nbio.funcs->detect_hw_virt(adev);
1b922423 748
f1a34465
XY		 749 if (amdgpu_sriov_vf(adev))
750 adev->virt.ops = &xgpu_ai_virt_ops;
751
220ab9bd
KW		 752 switch (adev->asic_type) {
753 case CHIP_VEGA10:
692069a1 754 case CHIP_VEGA12:
7c7af6c1 755 case CHIP_VEGA20:
2990a1fc
AD		 756 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
757 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2d11fd3f
TH		 758
759 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
760 if (amdgpu_sriov_vf(adev)) {
761 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
762 if (adev->asic_type == CHIP_VEGA20)
763 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
764 else
765 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
766 }
767 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
768 } else {
769 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
770 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
771 if (adev->asic_type == CHIP_VEGA20)
772 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
773 else
774 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
775 }
3680b2a5 776 }
009d9ed6
RZ		 777 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
778 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
c9ffa427
YT		 779 if (is_support_sw_smu(adev)) {
780 if (!amdgpu_sriov_vf(adev))
2da5410b 781 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
c9ffa427
YT		 782 } else {
783 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2da5410b 784 }
f8445307 785 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 786 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 787#if defined(CONFIG_DRM_AMD_DC)
788 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 789 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a 790#endif
846311ae
FM		 791 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
792 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
793 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
794 }
220ab9bd 795 break;
1023b797 796 case CHIP_RAVEN:
40c2358b
HR		 797 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
798 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2990a1fc 799 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
3680b2a5
EQ		 800 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
801 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
009d9ed6
RZ		 802 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
803 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b905090d 804 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 805 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 806 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 807#if defined(CONFIG_DRM_AMD_DC)
808 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 809 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1 810#endif
2990a1fc 811 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 812 break;
0e54df05
LM		 813 case CHIP_ARCTURUS:
814 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
815 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
21889cec
JZ		 816
817 if (amdgpu_sriov_vf(adev)) {
818 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
819 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
820 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
821 } else {
822 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
823 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
824 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
825 }
826
0e54df05
LM		 827 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
828 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
829 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
830 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
21889cec
JZ		 831 if (!amdgpu_sriov_vf(adev))
832 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
833
ab5999de
JJ		 834 if (amdgpu_sriov_vf(adev)) {
835 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
836 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
837 } else {
838 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
839 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
840 }
e416fdb6
JZ		 841 if (!amdgpu_sriov_vf(adev))
842 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
0e54df05 843 break;
05e1f0e0
HR		 844 case CHIP_RENOIR:
845 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
846 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
847 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
6a7a0bdb
AL		 848 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
849 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
5dbbe6a7
AL		 850 if (is_support_sw_smu(adev))
851 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
97222cfa
AL		 852 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
853 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b1326bbc
AL		 854 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
855 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
e1c14c43
RL		 856#if defined(CONFIG_DRM_AMD_DC)
857 else if (amdgpu_device_has_dc_support(adev))
858 amdgpu_device_ip_block_add(adev, &dm_ip_block);
e1c14c43 859#endif
279ba48e 860 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
5be45a26 861 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
05e1f0e0 862 break;
220ab9bd
KW		 863 default:
864 return -EINVAL;
865 }
866
867 return 0;
868}
869
69882565 870static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 871{
bebc0762 872 adev->nbio.funcs->hdp_flush(adev, ring);
73c73240
AD		 873}
874
69882565
CK		 875static void soc15_invalidate_hdp(struct amdgpu_device *adev,
876 struct amdgpu_ring *ring)
73c73240 877{
69882565 878 if (!ring || !ring->funcs->emit_wreg)
5fb7c665 879 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
69882565
CK		 880 else
881 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
882 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 883}
884
adbd4f89
AD		 885static bool soc15_need_full_reset(struct amdgpu_device *adev)
886{
887 /* change this when we implement soft reset */
888 return true;
889}
b45e18ac
KR		 890static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
891 uint64_t *count1)
892{
893 uint32_t perfctr = 0;
894 uint64_t cnt0_of, cnt1_of;
895 int tmp;
896
897 /* This reports 0 on APUs, so return to avoid writing/reading registers
898 * that may or may not be different from their GPU counterparts
899 */
0172591e
ES		 900 if (adev->flags & AMD_IS_APU)
901 return;
b45e18ac
KR		 902
903 /* Set the 2 events that we wish to watch, defined above */
9417f703 904 /* Reg 40 is # received msgs */
612e4ed9 905 /* Reg 104 is # of posted requests sent */
b45e18ac 906 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
612e4ed9 907 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
b45e18ac
KR		 908
909 /* Write to enable desired perf counters */
910 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
911 /* Zero out and enable the perf counters
912 * Write 0x5:
913 * Bit 0 = Start all counters(1)
914 * Bit 2 = Global counter reset enable(1)
915 */
916 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
917
918 msleep(1000);
919
920 /* Load the shadow and disable the perf counters
921 * Write 0x2:
922 * Bit 0 = Stop counters(0)
923 * Bit 1 = Load the shadow counters(1)
924 */
925 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
926
927 /* Read register values to get any >32bit overflow */
928 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
929 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
930 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
931
932 /* Get the values and add the overflow */
933 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
934 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
935}
adbd4f89 936
612e4ed9
KR		 937static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
938 uint64_t *count1)
939{
940 uint32_t perfctr = 0;
941 uint64_t cnt0_of, cnt1_of;
942 int tmp;
943
944 /* This reports 0 on APUs, so return to avoid writing/reading registers
945 * that may or may not be different from their GPU counterparts
946 */
947 if (adev->flags & AMD_IS_APU)
948 return;
949
950 /* Set the 2 events that we wish to watch, defined above */
951 /* Reg 40 is # received msgs */
952 /* Reg 108 is # of posted requests sent on VG20 */
953 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
954 EVENT0_SEL, 40);
955 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
956 EVENT1_SEL, 108);
957
958 /* Write to enable desired perf counters */
959 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
960 /* Zero out and enable the perf counters
961 * Write 0x5:
962 * Bit 0 = Start all counters(1)
963 * Bit 2 = Global counter reset enable(1)
964 */
965 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
966
967 msleep(1000);
968
969 /* Load the shadow and disable the perf counters
970 * Write 0x2:
971 * Bit 0 = Stop counters(0)
972 * Bit 1 = Load the shadow counters(1)
973 */
974 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
975
976 /* Read register values to get any >32bit overflow */
977 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
978 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
979 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
980
981 /* Get the values and add the overflow */
982 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
983 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
984}
985
9281f12c
AD		 986static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
987{
988 u32 sol_reg;
989
d55f33da
AD		 990 /* Just return false for soc15 GPUs. Reset does not seem to
991 * be necessary.
992 */
394e9a14
ED		 993 if (!amdgpu_passthrough(adev))
994 return false;
d55f33da 995
9281f12c
AD		 996 if (adev->flags & AMD_IS_APU)
997 return false;
998
999 /* Check sOS sign of life register to confirm sys driver and sOS
1000 * are already been loaded.
1001 */
1002 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1003 if (sol_reg)
1004 return true;
1005
1006 return false;
1007}
1008
dcea6e65
KR		 1009static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
1010{
1011 uint64_t nak_r, nak_g;
1012
1013 /* Get the number of NAKs received and generated */
1014 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
1015 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
1016
1017 /* Add the total number of NAKs, i.e the number of replays */
1018 return (nak_r + nak_g);
1019}
1020
220ab9bd
KW		 1021static const struct amdgpu_asic_funcs soc15_asic_funcs =
1022{
1023 .read_disabled_bios = &soc15_read_disabled_bios,
1024 .read_bios_from_rom = &soc15_read_bios_from_rom,
1025 .read_register = &soc15_read_register,
1026 .reset = &soc15_asic_reset,
ee360c0b 1027 .reset_method = &soc15_asic_reset_method,
220ab9bd
KW		 1028 .set_vga_state = &soc15_vga_set_state,
1029 .get_xclk = &soc15_get_xclk,
1030 .set_uvd_clocks = &soc15_set_uvd_clocks,
1031 .set_vce_clocks = &soc15_set_vce_clocks,
1032 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 1033 .flush_hdp = &soc15_flush_hdp,
1034 .invalidate_hdp = &soc15_invalidate_hdp,
adbd4f89 1035 .need_full_reset = &soc15_need_full_reset,
062f3807 1036 .init_doorbell_index = &vega10_doorbell_index_init,
b45e18ac 1037 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 1038 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 1039 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
988eb9ff 1040 .supports_baco = &soc15_supports_baco,
220ab9bd
KW		 1041};
1042
c93aa775
OZ		 1043static const struct amdgpu_asic_funcs vega20_asic_funcs =
1044{
1045 .read_disabled_bios = &soc15_read_disabled_bios,
1046 .read_bios_from_rom = &soc15_read_bios_from_rom,
1047 .read_register = &soc15_read_register,
1048 .reset = &soc15_asic_reset,
761e0923 1049 .reset_method = &soc15_asic_reset_method,
c93aa775
OZ		 1050 .set_vga_state = &soc15_vga_set_state,
1051 .get_xclk = &soc15_get_xclk,
1052 .set_uvd_clocks = &soc15_set_uvd_clocks,
1053 .set_vce_clocks = &soc15_set_vce_clocks,
1054 .get_config_memsize = &soc15_get_config_memsize,
1055 .flush_hdp = &soc15_flush_hdp,
1056 .invalidate_hdp = &soc15_invalidate_hdp,
1057 .need_full_reset = &soc15_need_full_reset,
1058 .init_doorbell_index = &vega20_doorbell_index_init,
612e4ed9 1059 .get_pcie_usage = &vega20_get_pcie_usage,
9281f12c 1060 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 1061 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
988eb9ff 1062 .supports_baco = &soc15_supports_baco,
220ab9bd
KW		 1063};
1064
1065static int soc15_common_early_init(void *handle)
1066{
88807dc8 1067#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
220ab9bd
KW		 1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1069
88807dc8
OZ		 1070 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1071 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
220ab9bd
KW		 1072 adev->smc_rreg = NULL;
1073 adev->smc_wreg = NULL;
1074 adev->pcie_rreg = &soc15_pcie_rreg;
1075 adev->pcie_wreg = &soc15_pcie_wreg;
4fa1c6a6
TZ		 1076 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1077 adev->pcie_wreg64 = &soc15_pcie_wreg64;
220ab9bd
KW		 1078 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1079 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1080 adev->didt_rreg = &soc15_didt_rreg;
1081 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 1082 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1083 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 1084 adev->se_cac_rreg = &soc15_se_cac_rreg;
1085 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd 1086
220ab9bd 1087
220ab9bd
KW		 1088 adev->external_rev_id = 0xFF;
1089 switch (adev->asic_type) {
1090 case CHIP_VEGA10:
c93aa775 1091 adev->asic_funcs = &soc15_asic_funcs;
220ab9bd
KW		 1092 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1093 AMD_CG_SUPPORT_GFX_MGLS |
1094 AMD_CG_SUPPORT_GFX_RLC_LS |
1095 AMD_CG_SUPPORT_GFX_CP_LS |
1096 AMD_CG_SUPPORT_GFX_3D_CGCG |
1097 AMD_CG_SUPPORT_GFX_3D_CGLS |
1098 AMD_CG_SUPPORT_GFX_CGCG |
1099 AMD_CG_SUPPORT_GFX_CGLS |
1100 AMD_CG_SUPPORT_BIF_MGCG |
1101 AMD_CG_SUPPORT_BIF_LS |
1102 AMD_CG_SUPPORT_HDP_LS |
1103 AMD_CG_SUPPORT_DRM_MGCG |
1104 AMD_CG_SUPPORT_DRM_LS |
1105 AMD_CG_SUPPORT_ROM_MGCG |
1106 AMD_CG_SUPPORT_DF_MGCG |
1107 AMD_CG_SUPPORT_SDMA_MGCG |
1108 AMD_CG_SUPPORT_SDMA_LS |
1109 AMD_CG_SUPPORT_MC_MGCG |
1110 AMD_CG_SUPPORT_MC_LS;
1111 adev->pg_flags = 0;
1112 adev->external_rev_id = 0x1;
1113 break;
692069a1 1114 case CHIP_VEGA12:
c93aa775 1115 adev->asic_funcs = &soc15_asic_funcs;
e4a38755
EQ		 1116 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1117 AMD_CG_SUPPORT_GFX_MGLS |
1118 AMD_CG_SUPPORT_GFX_CGCG |
1119 AMD_CG_SUPPORT_GFX_CGLS |
1120 AMD_CG_SUPPORT_GFX_3D_CGCG |
1121 AMD_CG_SUPPORT_GFX_3D_CGLS |
1122 AMD_CG_SUPPORT_GFX_CP_LS |
1123 AMD_CG_SUPPORT_MC_LS |
1124 AMD_CG_SUPPORT_MC_MGCG |
1125 AMD_CG_SUPPORT_SDMA_MGCG |
1126 AMD_CG_SUPPORT_SDMA_LS |
1127 AMD_CG_SUPPORT_BIF_MGCG |
1128 AMD_CG_SUPPORT_BIF_LS |
1129 AMD_CG_SUPPORT_HDP_MGCG |
1130 AMD_CG_SUPPORT_HDP_LS |
1131 AMD_CG_SUPPORT_ROM_MGCG |
1132 AMD_CG_SUPPORT_VCE_MGCG |
1133 AMD_CG_SUPPORT_UVD_MGCG;
692069a1 1134 adev->pg_flags = 0;
f559fe2b 1135 adev->external_rev_id = adev->rev_id + 0x14;
692069a1 1136 break;
935be7a0 1137 case CHIP_VEGA20:
c93aa775 1138 adev->asic_funcs = &vega20_asic_funcs;
3fdbab5f
EQ		 1139 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1140 AMD_CG_SUPPORT_GFX_MGLS |
1141 AMD_CG_SUPPORT_GFX_CGCG |
1142 AMD_CG_SUPPORT_GFX_CGLS |
1143 AMD_CG_SUPPORT_GFX_3D_CGCG |
1144 AMD_CG_SUPPORT_GFX_3D_CGLS |
1145 AMD_CG_SUPPORT_GFX_CP_LS |
1146 AMD_CG_SUPPORT_MC_LS |
1147 AMD_CG_SUPPORT_MC_MGCG |
1148 AMD_CG_SUPPORT_SDMA_MGCG |
1149 AMD_CG_SUPPORT_SDMA_LS |
1150 AMD_CG_SUPPORT_BIF_MGCG |
1151 AMD_CG_SUPPORT_BIF_LS |
1152 AMD_CG_SUPPORT_HDP_MGCG |
102e4940 1153 AMD_CG_SUPPORT_HDP_LS |
3fdbab5f
EQ		 1154 AMD_CG_SUPPORT_ROM_MGCG |
1155 AMD_CG_SUPPORT_VCE_MGCG |
1156 AMD_CG_SUPPORT_UVD_MGCG;
935be7a0
FX		 1157 adev->pg_flags = 0;
1158 adev->external_rev_id = adev->rev_id + 0x28;
1159 break;
957c6fe1 1160 case CHIP_RAVEN:
c93aa775 1161 adev->asic_funcs = &soc15_asic_funcs;
520cbe0f 1162 if (adev->rev_id >= 0x8)
7e4545d3 1163 adev->external_rev_id = adev->rev_id + 0x79;
741deade
AD		 1164 else if (adev->pdev->device == 0x15d8)
1165 adev->external_rev_id = adev->rev_id + 0x41;
7e4545d3
HR		 1166 else if (adev->rev_id == 1)
1167 adev->external_rev_id = adev->rev_id + 0x20;
741deade 1168 else
7e4545d3 1169 adev->external_rev_id = adev->rev_id + 0x01;
741deade
AD		 1170
1171 if (adev->rev_id >= 0x8) {
520cbe0f
HR		 1172 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1173 AMD_CG_SUPPORT_GFX_MGLS |
1174 AMD_CG_SUPPORT_GFX_CP_LS |
1175 AMD_CG_SUPPORT_GFX_3D_CGCG |
1176 AMD_CG_SUPPORT_GFX_3D_CGLS |
1177 AMD_CG_SUPPORT_GFX_CGCG |
1178 AMD_CG_SUPPORT_GFX_CGLS |
1179 AMD_CG_SUPPORT_BIF_LS |
1180 AMD_CG_SUPPORT_HDP_LS |
1181 AMD_CG_SUPPORT_ROM_MGCG |
1182 AMD_CG_SUPPORT_MC_MGCG |
1183 AMD_CG_SUPPORT_MC_LS |
1184 AMD_CG_SUPPORT_SDMA_MGCG |
1185 AMD_CG_SUPPORT_SDMA_LS |
1186 AMD_CG_SUPPORT_VCN_MGCG;
741deade 1187
d5159591 1188 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
741deade 1189 } else if (adev->pdev->device == 0x15d8) {
fced5c70
LG		 1190 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1191 AMD_CG_SUPPORT_GFX_MGLS |
741deade
AD		 1192 AMD_CG_SUPPORT_GFX_CP_LS |
1193 AMD_CG_SUPPORT_GFX_3D_CGCG |
1194 AMD_CG_SUPPORT_GFX_3D_CGLS |
1195 AMD_CG_SUPPORT_GFX_CGCG |
1196 AMD_CG_SUPPORT_GFX_CGLS |
1197 AMD_CG_SUPPORT_BIF_LS |
1198 AMD_CG_SUPPORT_HDP_LS |
1199 AMD_CG_SUPPORT_ROM_MGCG |
1200 AMD_CG_SUPPORT_MC_MGCG |
1201 AMD_CG_SUPPORT_MC_LS |
1202 AMD_CG_SUPPORT_SDMA_MGCG |
1203 AMD_CG_SUPPORT_SDMA_LS;
1204
1205 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1206 AMD_PG_SUPPORT_MMHUB |
a3716d3a
JZ		 1207 AMD_PG_SUPPORT_VCN |
1208 AMD_PG_SUPPORT_VCN_DPG;
741deade 1209 } else {
520cbe0f
HR		 1210 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1211 AMD_CG_SUPPORT_GFX_MGLS |
1212 AMD_CG_SUPPORT_GFX_RLC_LS |
1213 AMD_CG_SUPPORT_GFX_CP_LS |
1214 AMD_CG_SUPPORT_GFX_3D_CGCG |
1215 AMD_CG_SUPPORT_GFX_3D_CGLS |
1216 AMD_CG_SUPPORT_GFX_CGCG |
1217 AMD_CG_SUPPORT_GFX_CGLS |
1218 AMD_CG_SUPPORT_BIF_MGCG |
1219 AMD_CG_SUPPORT_BIF_LS |
1220 AMD_CG_SUPPORT_HDP_MGCG |
1221 AMD_CG_SUPPORT_HDP_LS |
1222 AMD_CG_SUPPORT_DRM_MGCG |
1223 AMD_CG_SUPPORT_DRM_LS |
1224 AMD_CG_SUPPORT_ROM_MGCG |
1225 AMD_CG_SUPPORT_MC_MGCG |
1226 AMD_CG_SUPPORT_MC_LS |
1227 AMD_CG_SUPPORT_SDMA_MGCG |
1228 AMD_CG_SUPPORT_SDMA_LS |
1229 AMD_CG_SUPPORT_VCN_MGCG;
61c8e90d 1230
d5159591 1231 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
741deade 1232 }
ad5a67a7 1233 break;
0e54df05 1234 case CHIP_ARCTURUS:
7f40581c 1235 adev->asic_funcs = &vega20_asic_funcs;
6b76ce62
LM		 1236 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1237 AMD_CG_SUPPORT_GFX_MGLS |
1238 AMD_CG_SUPPORT_GFX_CGCG |
5d111f5b 1239 AMD_CG_SUPPORT_GFX_CGLS |
f9da7c43 1240 AMD_CG_SUPPORT_GFX_CP_LS |
5d111f5b 1241 AMD_CG_SUPPORT_HDP_MGCG |
f7ee1995
LM		 1242 AMD_CG_SUPPORT_HDP_LS |
1243 AMD_CG_SUPPORT_SDMA_MGCG |
a840159c
LM		 1244 AMD_CG_SUPPORT_SDMA_LS |
1245 AMD_CG_SUPPORT_MC_MGCG |
227f7d58 1246 AMD_CG_SUPPORT_MC_LS |
e89e2237
LL		 1247 AMD_CG_SUPPORT_IH_CG |
1248 AMD_CG_SUPPORT_VCN_MGCG |
1249 AMD_CG_SUPPORT_JPEG_MGCG;
0e54df05 1250 adev->pg_flags = 0;
d57c3d56 1251 adev->external_rev_id = adev->rev_id + 0x32;
0e54df05 1252 break;
080deab6 1253 case CHIP_RENOIR:
e09ce481 1254 adev->asic_funcs = &soc15_asic_funcs;
ec3636a5
PL		 1255 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1256 AMD_CG_SUPPORT_GFX_MGLS |
1257 AMD_CG_SUPPORT_GFX_3D_CGCG |
1258 AMD_CG_SUPPORT_GFX_3D_CGLS |
1259 AMD_CG_SUPPORT_GFX_CGCG |
1260 AMD_CG_SUPPORT_GFX_CGLS |
a2d15255
PL		 1261 AMD_CG_SUPPORT_GFX_CP_LS |
1262 AMD_CG_SUPPORT_MC_MGCG |
ef0e7d08
PL		 1263 AMD_CG_SUPPORT_MC_LS |
1264 AMD_CG_SUPPORT_SDMA_MGCG |
d98930f5 1265 AMD_CG_SUPPORT_SDMA_LS |
9deac0a4 1266 AMD_CG_SUPPORT_BIF_LS |
de273070 1267 AMD_CG_SUPPORT_HDP_LS |
753c929c 1268 AMD_CG_SUPPORT_ROM_MGCG |
91ec8bbb 1269 AMD_CG_SUPPORT_VCN_MGCG |
099d66e4 1270 AMD_CG_SUPPORT_JPEG_MGCG |
e2ef3b70
PL		 1271 AMD_CG_SUPPORT_IH_CG |
1272 AMD_CG_SUPPORT_ATHUB_LS |
8db63b7c
PL		 1273 AMD_CG_SUPPORT_ATHUB_MGCG |
1274 AMD_CG_SUPPORT_DF_MGCG;
85400984
TT		 1275 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1276 AMD_PG_SUPPORT_VCN |
099d66e4 1277 AMD_PG_SUPPORT_JPEG |
85400984 1278 AMD_PG_SUPPORT_VCN_DPG;
080deab6
HR		 1279 adev->external_rev_id = adev->rev_id + 0x91;
1280 break;
220ab9bd
KW		 1281 default:
1282 /* FIXME: not supported yet */
1283 return -EINVAL;
1284 }
1285
ab276632
XY		 1286 if (amdgpu_sriov_vf(adev)) {
1287 amdgpu_virt_init_setting(adev);
1288 xgpu_ai_mailbox_set_irq_funcs(adev);
1289 }
1290
220ab9bd
KW		 1291 return 0;
1292}
1293
81758c55
ML		 1294static int soc15_common_late_init(void *handle)
1295{
1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
22e1d14f 1297 int r = 0;
81758c55
ML		 1298
1299 if (amdgpu_sriov_vf(adev))
1300 xgpu_ai_mailbox_get_irq(adev);
1301
22e1d14f
HZ		 1302 if (adev->nbio.funcs->ras_late_init)
1303 r = adev->nbio.funcs->ras_late_init(adev);
1304
1305 return r;
81758c55
ML		 1306}
1307
220ab9bd
KW		 1308static int soc15_common_sw_init(void *handle)
1309{
81758c55
ML		 1310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1311
1312 if (amdgpu_sriov_vf(adev))
1313 xgpu_ai_mailbox_add_irq_id(adev);
1314
e4cf4bf5
JK		 1315 adev->df_funcs->sw_init(adev);
1316
220ab9bd
KW		 1317 return 0;
1318}
1319
1320static int soc15_common_sw_fini(void *handle)
1321{
f1d59e00
JZ		 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323
de9bbd52 1324 amdgpu_nbio_ras_fini(adev);
f1d59e00 1325 adev->df_funcs->sw_fini(adev);
220ab9bd
KW		 1326 return 0;
1327}
1328
7c94bc82
OZ		 1329static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1330{
1331 int i;
1332 struct amdgpu_ring *ring;
1333
4cd4c5c0
ML		 1334 /* sdma/ih doorbell range are programed by hypervisor */
1335 if (!amdgpu_sriov_vf(adev)) {
98cad2de
TH		 1336 for (i = 0; i < adev->sdma.num_instances; i++) {
1337 ring = &adev->sdma.instance[i].ring;
bebc0762 1338 adev->nbio.funcs->sdma_doorbell_range(adev, i,
98cad2de
TH		 1339 ring->use_doorbell, ring->doorbell_index,
1340 adev->doorbell_index.sdma_doorbell_range);
1341 }
7c94bc82 1342
bebc0762 1343 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
7c94bc82 1344 adev->irq.ih.doorbell_index);
4cd4c5c0 1345 }
7c94bc82
OZ		 1346}
1347
220ab9bd
KW		 1348static int soc15_common_hw_init(void *handle)
1349{
1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351
220ab9bd
KW		 1352 /* enable pcie gen2/3 link */
1353 soc15_pcie_gen3_enable(adev);
1354 /* enable aspm */
1355 soc15_program_aspm(adev);
833fa075 1356 /* setup nbio registers */
bebc0762 1357 adev->nbio.funcs->init_registers(adev);
88807dc8
OZ		 1358 /* remap HDP registers to a hole in mmio space,
1359 * for the purpose of expose those registers
1360 * to process space
1361 */
bebc0762
HZ		 1362 if (adev->nbio.funcs->remap_hdp_registers)
1363 adev->nbio.funcs->remap_hdp_registers(adev);
e4cf4bf5 1364
220ab9bd
KW		 1365 /* enable the doorbell aperture */
1366 soc15_enable_doorbell_aperture(adev, true);
7c94bc82
OZ		 1367 /* HW doorbell routing policy: doorbell writing not
1368 * in SDMA/IH/MM/ACV range will be routed to CP. So
1369 * we need to init SDMA/IH/MM/ACV doorbell range prior
1370 * to CP ip block init and ring test.
1371 */
1372 soc15_doorbell_range_init(adev);
220ab9bd
KW		 1373
1374 return 0;
1375}
1376
1377static int soc15_common_hw_fini(void *handle)
1378{
1379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1380
1381 /* disable the doorbell aperture */
1382 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 1383 if (amdgpu_sriov_vf(adev))
1384 xgpu_ai_mailbox_put_irq(adev);
220ab9bd 1385
cde85ac2
PY		 1386 if (adev->nbio.ras_if &&
1387 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
22e1d14f
HZ		 1388 if (adev->nbio.funcs->init_ras_controller_interrupt)
1389 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1390 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1391 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1392 }
1393
220ab9bd
KW		 1394 return 0;
1395}
1396
1397static int soc15_common_suspend(void *handle)
1398{
1399 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1400
1401 return soc15_common_hw_fini(adev);
1402}
1403
1404static int soc15_common_resume(void *handle)
1405{
1406 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1407
1408 return soc15_common_hw_init(adev);
1409}
1410
1411static bool soc15_common_is_idle(void *handle)
1412{
1413 return true;
1414}
1415
1416static int soc15_common_wait_for_idle(void *handle)
1417{
1418 return 0;
1419}
1420
1421static int soc15_common_soft_reset(void *handle)
1422{
1423 return 0;
1424}
1425
1426static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1427{
1428 uint32_t def, data;
1429
6acb87ac
LM		 1430 if (adev->asic_type == CHIP_VEGA20 ||
1431 adev->asic_type == CHIP_ARCTURUS) {
a5d0f456 1432 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
220ab9bd 1433
a5d0f456
KF		 1434 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1435 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1436 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1437 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1438 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1439 else
1440 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1441 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1442 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1443 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
220ab9bd 1444
a5d0f456
KF		 1445 if (def != data)
1446 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1447 } else {
1448 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1449
1450 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1451 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1452 else
1453 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1454
1455 if (def != data)
1456 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1457 }
220ab9bd
KW		 1458}
1459
1460static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1461{
1462 uint32_t def, data;
1463
1464 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1465
1466 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1467 data &= ~(0x01000000 |
1468 0x02000000 |
1469 0x04000000 |
1470 0x08000000 |
1471 0x10000000 |
1472 0x20000000 |
1473 0x40000000 |
1474 0x80000000);
1475 else
1476 data |= (0x01000000 |
1477 0x02000000 |
1478 0x04000000 |
1479 0x08000000 |
1480 0x10000000 |
1481 0x20000000 |
1482 0x40000000 |
1483 0x80000000);
1484
1485 if (def != data)
1486 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1487}
1488
1489static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1490{
1491 uint32_t def, data;
1492
1493 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1494
1495 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1496 data |= 1;
1497 else
1498 data &= ~1;
1499
1500 if (def != data)
1501 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1502}
1503
1504static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1505 bool enable)
1506{
1507 uint32_t def, data;
1508
1509 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1510
1511 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1512 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1513 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1514 else
1515 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1516 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1517
1518 if (def != data)
1519 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1520}
1521
220ab9bd
KW		 1522static int soc15_common_set_clockgating_state(void *handle,
1523 enum amd_clockgating_state state)
1524{
1525 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1526
6e9dc861
ML		 1527 if (amdgpu_sriov_vf(adev))
1528 return 0;
1529
220ab9bd
KW		 1530 switch (adev->asic_type) {
1531 case CHIP_VEGA10:
692069a1 1532 case CHIP_VEGA12:
f980d127 1533 case CHIP_VEGA20:
bebc0762 1534 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
220ab9bd 1535 state == AMD_CG_STATE_GATE ? true : false);
bebc0762 1536 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 1537 state == AMD_CG_STATE_GATE ? true : false);
1538 soc15_update_hdp_light_sleep(adev,
1539 state == AMD_CG_STATE_GATE ? true : false);
1540 soc15_update_drm_clock_gating(adev,
1541 state == AMD_CG_STATE_GATE ? true : false);
1542 soc15_update_drm_light_sleep(adev,
1543 state == AMD_CG_STATE_GATE ? true : false);
1544 soc15_update_rom_medium_grain_clock_gating(adev,
1545 state == AMD_CG_STATE_GATE ? true : false);
070706c0 1546 adev->df_funcs->update_medium_grain_clock_gating(adev,
220ab9bd
KW		 1547 state == AMD_CG_STATE_GATE ? true : false);
1548 break;
9e5a9eb4 1549 case CHIP_RAVEN:
f78e007f 1550 case CHIP_RENOIR:
bebc0762 1551 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 1552 state == AMD_CG_STATE_GATE ? true : false);
bebc0762 1553 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 1554 state == AMD_CG_STATE_GATE ? true : false);
1555 soc15_update_hdp_light_sleep(adev,
1556 state == AMD_CG_STATE_GATE ? true : false);
1557 soc15_update_drm_clock_gating(adev,
1558 state == AMD_CG_STATE_GATE ? true : false);
1559 soc15_update_drm_light_sleep(adev,
1560 state == AMD_CG_STATE_GATE ? true : false);
1561 soc15_update_rom_medium_grain_clock_gating(adev,
1562 state == AMD_CG_STATE_GATE ? true : false);
1563 break;
6acb87ac
LM		 1564 case CHIP_ARCTURUS:
1565 soc15_update_hdp_light_sleep(adev,
1566 state == AMD_CG_STATE_GATE ? true : false);
1567 break;
220ab9bd
KW		 1568 default:
1569 break;
1570 }
1571 return 0;
1572}
1573
f9abe35c
HR		 1574static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1575{
1576 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1577 int data;
1578
1579 if (amdgpu_sriov_vf(adev))
1580 *flags = 0;
1581
bebc0762 1582 adev->nbio.funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1583
1584 /* AMD_CG_SUPPORT_HDP_LS */
1585 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1586 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1587 *flags |= AMD_CG_SUPPORT_HDP_LS;
1588
1589 /* AMD_CG_SUPPORT_DRM_MGCG */
1590 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1591 if (!(data & 0x01000000))
1592 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1593
1594 /* AMD_CG_SUPPORT_DRM_LS */
1595 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1596 if (data & 0x1)
1597 *flags |= AMD_CG_SUPPORT_DRM_LS;
1598
1599 /* AMD_CG_SUPPORT_ROM_MGCG */
1600 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1601 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1602 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1603
070706c0 1604 adev->df_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1605}
1606
220ab9bd
KW		 1607static int soc15_common_set_powergating_state(void *handle,
1608 enum amd_powergating_state state)
1609{
1610 /* todo */
1611 return 0;
1612}
1613
1614const struct amd_ip_funcs soc15_common_ip_funcs = {
1615 .name = "soc15_common",
1616 .early_init = soc15_common_early_init,
81758c55 1617 .late_init = soc15_common_late_init,
220ab9bd
KW		 1618 .sw_init = soc15_common_sw_init,
1619 .sw_fini = soc15_common_sw_fini,
1620 .hw_init = soc15_common_hw_init,
1621 .hw_fini = soc15_common_hw_fini,
1622 .suspend = soc15_common_suspend,
1623 .resume = soc15_common_resume,
1624 .is_idle = soc15_common_is_idle,
1625 .wait_for_idle = soc15_common_wait_for_idle,
1626 .soft_reset = soc15_common_soft_reset,
1627 .set_clockgating_state = soc15_common_set_clockgating_state,
1628 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 1629 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 1630};
Linux 6.x block layer and io_uring tree(s)