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drm/amdgpu: disable uvd for sriov
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
37#include "vega10/soc15ip.h"
38#include "vega10/UVD/uvd_7_0_offset.h"
39#include "vega10/GC/gc_9_0_offset.h"
40#include "vega10/GC/gc_9_0_sh_mask.h"
41#include "vega10/SDMA0/sdma0_4_0_offset.h"
42#include "vega10/SDMA1/sdma1_4_0_offset.h"
43#include "vega10/HDP/hdp_4_0_offset.h"
44#include "vega10/HDP/hdp_4_0_sh_mask.h"
45#include "vega10/MP/mp_9_0_offset.h"
46#include "vega10/MP/mp_9_0_sh_mask.h"
47#include "vega10/SMUIO/smuio_9_0_offset.h"
48#include "vega10/SMUIO/smuio_9_0_sh_mask.h"
49
50#include "soc15.h"
51#include "soc15_common.h"
52#include "gfx_v9_0.h"
53#include "gmc_v9_0.h"
54#include "gfxhub_v1_0.h"
55#include "mmhub_v1_0.h"
56#include "vega10_ih.h"
57#include "sdma_v4_0.h"
58#include "uvd_v7_0.h"
59#include "vce_v4_0.h"
60#include "amdgpu_powerplay.h"
796b6568 61#include "dce_virtual.h"
f1a34465 62#include "mxgpu_ai.h"
220ab9bd
KW		 63
64MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
65
66#define mmFabricConfigAccessControl 0x0410
67#define mmFabricConfigAccessControl_BASE_IDX 0
68#define mmFabricConfigAccessControl_DEFAULT 0x00000000
69//FabricConfigAccessControl
70#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
71#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
72#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
73#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
74#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
75#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
76
77
78#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc
79#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0
80//DF_PIE_AON0_DfGlobalClkGater
81#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
82#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
83
84enum {
85 DF_MGCG_DISABLE = 0,
86 DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
87 DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
88 DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
89 DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
90 DF_MGCG_ENABLE_63_CYCLE_DELAY =15
91};
92
93#define mmMP0_MISC_CGTT_CTRL0 0x01b9
94#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
95#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
96#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
97
98/*
99 * Indirect registers accessor
100 */
101static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
102{
103 unsigned long flags, address, data;
104 u32 r;
105 struct nbio_pcie_index_data *nbio_pcie_id;
106
107 if (adev->asic_type == CHIP_VEGA10)
108 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
109
110 address = nbio_pcie_id->index_offset;
111 data = nbio_pcie_id->data_offset;
112
113 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
114 WREG32(address, reg);
115 (void)RREG32(address);
116 r = RREG32(data);
117 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
118 return r;
119}
120
121static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
122{
123 unsigned long flags, address, data;
124 struct nbio_pcie_index_data *nbio_pcie_id;
125
126 if (adev->asic_type == CHIP_VEGA10)
127 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
128
129 address = nbio_pcie_id->index_offset;
130 data = nbio_pcie_id->data_offset;
131
132 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
133 WREG32(address, reg);
134 (void)RREG32(address);
135 WREG32(data, v);
136 (void)RREG32(data);
137 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
138}
139
140static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
141{
142 unsigned long flags, address, data;
143 u32 r;
144
145 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
146 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
147
148 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
149 WREG32(address, ((reg) & 0x1ff));
150 r = RREG32(data);
151 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
152 return r;
153}
154
155static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
156{
157 unsigned long flags, address, data;
158
159 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
160 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
161
162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
163 WREG32(address, ((reg) & 0x1ff));
164 WREG32(data, (v));
165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
166}
167
168static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
169{
170 unsigned long flags, address, data;
171 u32 r;
172
173 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
174 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
175
176 spin_lock_irqsave(&adev->didt_idx_lock, flags);
177 WREG32(address, (reg));
178 r = RREG32(data);
179 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
180 return r;
181}
182
183static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
184{
185 unsigned long flags, address, data;
186
187 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
188 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
189
190 spin_lock_irqsave(&adev->didt_idx_lock, flags);
191 WREG32(address, (reg));
192 WREG32(data, (v));
193 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
194}
195
196static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
197{
198 return nbio_v6_1_get_memsize(adev);
199}
200
201static const u32 vega10_golden_init[] =
202{
203};
204
205static void soc15_init_golden_registers(struct amdgpu_device *adev)
206{
207 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
208 mutex_lock(&adev->grbm_idx_mutex);
209
210 switch (adev->asic_type) {
211 case CHIP_VEGA10:
212 amdgpu_program_register_sequence(adev,
213 vega10_golden_init,
214 (const u32)ARRAY_SIZE(vega10_golden_init));
215 break;
216 default:
217 break;
218 }
219 mutex_unlock(&adev->grbm_idx_mutex);
220}
221static u32 soc15_get_xclk(struct amdgpu_device *adev)
222{
223 if (adev->asic_type == CHIP_VEGA10)
224 return adev->clock.spll.reference_freq/4;
225 else
226 return adev->clock.spll.reference_freq;
227}
228
229
230void soc15_grbm_select(struct amdgpu_device *adev,
231 u32 me, u32 pipe, u32 queue, u32 vmid)
232{
233 u32 grbm_gfx_cntl = 0;
234 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
235 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
236 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
237 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
238
239 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
240}
241
242static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
243{
244 /* todo */
245}
246
247static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
248{
249 /* todo */
250 return false;
251}
252
253static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
254 u8 *bios, u32 length_bytes)
255{
256 u32 *dw_ptr;
257 u32 i, length_dw;
258
259 if (bios == NULL)
260 return false;
261 if (length_bytes == 0)
262 return false;
263 /* APU vbios image is part of sbios image */
264 if (adev->flags & AMD_IS_APU)
265 return false;
266
267 dw_ptr = (u32 *)bios;
268 length_dw = ALIGN(length_bytes, 4) / 4;
269
270 /* set rom index to 0 */
271 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
272 /* read out the rom data */
273 for (i = 0; i < length_dw; i++)
274 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
275
276 return true;
277}
278
279static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = {
280 /* todo */
281};
282
283static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
284 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false},
285 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false},
286 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false},
287 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false},
288 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false},
289 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false},
290 { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false},
291 { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false},
292 { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false},
293 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false},
294 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false},
295 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false},
296 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
297 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
298 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
299 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
300 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
301 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
302 { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
303 { SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true},
304 { SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true},
305 { SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false},
306};
307
308static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
309 u32 sh_num, u32 reg_offset)
310{
311 uint32_t val;
312
313 mutex_lock(&adev->grbm_idx_mutex);
314 if (se_num != 0xffffffff || sh_num != 0xffffffff)
315 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
316
317 val = RREG32(reg_offset);
318
319 if (se_num != 0xffffffff || sh_num != 0xffffffff)
320 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
321 mutex_unlock(&adev->grbm_idx_mutex);
322 return val;
323}
324
325static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
326 u32 sh_num, u32 reg_offset, u32 *value)
327{
328 struct amdgpu_allowed_register_entry *asic_register_table = NULL;
329 struct amdgpu_allowed_register_entry *asic_register_entry;
330 uint32_t size, i;
331
332 *value = 0;
333 switch (adev->asic_type) {
334 case CHIP_VEGA10:
335 asic_register_table = vega10_allowed_read_registers;
336 size = ARRAY_SIZE(vega10_allowed_read_registers);
337 break;
338 default:
339 return -EINVAL;
340 }
341
342 if (asic_register_table) {
343 for (i = 0; i < size; i++) {
344 asic_register_entry = asic_register_table + i;
345 if (reg_offset != asic_register_entry->reg_offset)
346 continue;
347 if (!asic_register_entry->untouched)
348 *value = asic_register_entry->grbm_indexed ?
349 soc15_read_indexed_register(adev, se_num,
350 sh_num, reg_offset) :
351 RREG32(reg_offset);
352 return 0;
353 }
354 }
355
356 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
357 if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
358 continue;
359
360 if (!soc15_allowed_read_registers[i].untouched)
361 *value = soc15_allowed_read_registers[i].grbm_indexed ?
362 soc15_read_indexed_register(adev, se_num,
363 sh_num, reg_offset) :
364 RREG32(reg_offset);
365 return 0;
366 }
367 return -EINVAL;
368}
369
370static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
371{
372 u32 i;
373
374 dev_info(adev->dev, "GPU pci config reset\n");
375
376 /* disable BM */
377 pci_clear_master(adev->pdev);
378 /* reset */
379 amdgpu_pci_config_reset(adev);
380
381 udelay(100);
382
383 /* wait for asic to come out of reset */
384 for (i = 0; i < adev->usec_timeout; i++) {
385 if (nbio_v6_1_get_memsize(adev) != 0xffffffff)
386 break;
387 udelay(1);
388 }
389
390}
391
392static int soc15_asic_reset(struct amdgpu_device *adev)
393{
394 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
395
396 soc15_gpu_pci_config_reset(adev);
397
398 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
399
400 return 0;
401}
402
403/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
404 u32 cntl_reg, u32 status_reg)
405{
406 return 0;
407}*/
408
409static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
410{
411 /*int r;
412
413 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
414 if (r)
415 return r;
416
417 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
418 */
419 return 0;
420}
421
422static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
423{
424 /* todo */
425
426 return 0;
427}
428
429static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
430{
431 if (pci_is_root_bus(adev->pdev->bus))
432 return;
433
434 if (amdgpu_pcie_gen2 == 0)
435 return;
436
437 if (adev->flags & AMD_IS_APU)
438 return;
439
440 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
441 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
442 return;
443
444 /* todo */
445}
446
447static void soc15_program_aspm(struct amdgpu_device *adev)
448{
449
450 if (amdgpu_aspm == 0)
451 return;
452
453 /* todo */
454}
455
456static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
457 bool enable)
458{
459 nbio_v6_1_enable_doorbell_aperture(adev, enable);
460 nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
461}
462
463static const struct amdgpu_ip_block_version vega10_common_ip_block =
464{
465 .type = AMD_IP_BLOCK_TYPE_COMMON,
466 .major = 2,
467 .minor = 0,
468 .rev = 0,
469 .funcs = &soc15_common_ip_funcs,
470};
471
472int soc15_set_ip_blocks(struct amdgpu_device *adev)
473{
1b922423
XY		 474 nbio_v6_1_detect_hw_virt(adev);
475
f1a34465
XY		 476 if (amdgpu_sriov_vf(adev))
477 adev->virt.ops = &xgpu_ai_virt_ops;
478
220ab9bd
KW		 479 switch (adev->asic_type) {
480 case CHIP_VEGA10:
481 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
482 amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
483 amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
484 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
485 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
86d3798a
XY		 486 if (!amdgpu_sriov_vf(adev))
487 amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
220ab9bd 488 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
f8445307 489 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
796b6568 490 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
220ab9bd
KW		 491 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
492 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
468842a5
XY		 493 if (!amdgpu_sriov_vf(adev))
494 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
220ab9bd
KW		 495 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
496 break;
497 default:
498 return -EINVAL;
499 }
500
501 return 0;
502}
503
504static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
505{
506 return nbio_v6_1_get_rev_id(adev);
507}
508
509
510int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev)
511{
512 /* to be implemented in MC IP*/
513 return 0;
514}
515
516static const struct amdgpu_asic_funcs soc15_asic_funcs =
517{
518 .read_disabled_bios = &soc15_read_disabled_bios,
519 .read_bios_from_rom = &soc15_read_bios_from_rom,
520 .read_register = &soc15_read_register,
521 .reset = &soc15_asic_reset,
522 .set_vga_state = &soc15_vga_set_state,
523 .get_xclk = &soc15_get_xclk,
524 .set_uvd_clocks = &soc15_set_uvd_clocks,
525 .set_vce_clocks = &soc15_set_vce_clocks,
526 .get_config_memsize = &soc15_get_config_memsize,
527};
528
529static int soc15_common_early_init(void *handle)
530{
531 bool psp_enabled = false;
532 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
533
534 adev->smc_rreg = NULL;
535 adev->smc_wreg = NULL;
536 adev->pcie_rreg = &soc15_pcie_rreg;
537 adev->pcie_wreg = &soc15_pcie_wreg;
538 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
539 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
540 adev->didt_rreg = &soc15_didt_rreg;
541 adev->didt_wreg = &soc15_didt_wreg;
542
543 adev->asic_funcs = &soc15_asic_funcs;
544
545 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
546 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
547 psp_enabled = true;
548
549 /*
550 * nbio need be used for both sdma and gfx9, but only
551 * initializes once
552 */
553 switch(adev->asic_type) {
554 case CHIP_VEGA10:
555 nbio_v6_1_init(adev);
556 break;
557 default:
558 return -EINVAL;
559 }
560
561 adev->rev_id = soc15_get_rev_id(adev);
562 adev->external_rev_id = 0xFF;
563 switch (adev->asic_type) {
564 case CHIP_VEGA10:
565 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
566 AMD_CG_SUPPORT_GFX_MGLS |
567 AMD_CG_SUPPORT_GFX_RLC_LS |
568 AMD_CG_SUPPORT_GFX_CP_LS |
569 AMD_CG_SUPPORT_GFX_3D_CGCG |
570 AMD_CG_SUPPORT_GFX_3D_CGLS |
571 AMD_CG_SUPPORT_GFX_CGCG |
572 AMD_CG_SUPPORT_GFX_CGLS |
573 AMD_CG_SUPPORT_BIF_MGCG |
574 AMD_CG_SUPPORT_BIF_LS |
575 AMD_CG_SUPPORT_HDP_LS |
576 AMD_CG_SUPPORT_DRM_MGCG |
577 AMD_CG_SUPPORT_DRM_LS |
578 AMD_CG_SUPPORT_ROM_MGCG |
579 AMD_CG_SUPPORT_DF_MGCG |
580 AMD_CG_SUPPORT_SDMA_MGCG |
581 AMD_CG_SUPPORT_SDMA_LS |
582 AMD_CG_SUPPORT_MC_MGCG |
583 AMD_CG_SUPPORT_MC_LS;
584 adev->pg_flags = 0;
585 adev->external_rev_id = 0x1;
586 break;
587 default:
588 /* FIXME: not supported yet */
589 return -EINVAL;
590 }
591
592 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
593
594 amdgpu_get_pcie_info(adev);
595
596 return 0;
597}
598
599static int soc15_common_sw_init(void *handle)
600{
601 return 0;
602}
603
604static int soc15_common_sw_fini(void *handle)
605{
606 return 0;
607}
608
609static int soc15_common_hw_init(void *handle)
610{
611 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
612
613 /* move the golden regs per IP block */
614 soc15_init_golden_registers(adev);
615 /* enable pcie gen2/3 link */
616 soc15_pcie_gen3_enable(adev);
617 /* enable aspm */
618 soc15_program_aspm(adev);
619 /* enable the doorbell aperture */
620 soc15_enable_doorbell_aperture(adev, true);
621
622 return 0;
623}
624
625static int soc15_common_hw_fini(void *handle)
626{
627 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
628
629 /* disable the doorbell aperture */
630 soc15_enable_doorbell_aperture(adev, false);
631
632 return 0;
633}
634
635static int soc15_common_suspend(void *handle)
636{
637 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
638
639 return soc15_common_hw_fini(adev);
640}
641
642static int soc15_common_resume(void *handle)
643{
644 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
645
646 return soc15_common_hw_init(adev);
647}
648
649static bool soc15_common_is_idle(void *handle)
650{
651 return true;
652}
653
654static int soc15_common_wait_for_idle(void *handle)
655{
656 return 0;
657}
658
659static int soc15_common_soft_reset(void *handle)
660{
661 return 0;
662}
663
664static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
665{
666 uint32_t def, data;
667
668 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
669
670 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
671 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
672 else
673 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
674
675 if (def != data)
676 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
677}
678
679static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
680{
681 uint32_t def, data;
682
683 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
684
685 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
686 data &= ~(0x01000000 |
687 0x02000000 |
688 0x04000000 |
689 0x08000000 |
690 0x10000000 |
691 0x20000000 |
692 0x40000000 |
693 0x80000000);
694 else
695 data |= (0x01000000 |
696 0x02000000 |
697 0x04000000 |
698 0x08000000 |
699 0x10000000 |
700 0x20000000 |
701 0x40000000 |
702 0x80000000);
703
704 if (def != data)
705 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
706}
707
708static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
709{
710 uint32_t def, data;
711
712 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
713
714 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
715 data |= 1;
716 else
717 data &= ~1;
718
719 if (def != data)
720 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
721}
722
723static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
724 bool enable)
725{
726 uint32_t def, data;
727
728 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
729
730 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
731 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
732 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
733 else
734 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
735 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
736
737 if (def != data)
738 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
739}
740
741static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
742 bool enable)
743{
744 uint32_t data;
745
746 /* Put DF on broadcast mode */
747 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
748 data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
749 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
750
751 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
752 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
753 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
754 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
755 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
756 } else {
757 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
758 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
759 data |= DF_MGCG_DISABLE;
760 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
761 }
762
763 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
764 mmFabricConfigAccessControl_DEFAULT);
765}
766
767static int soc15_common_set_clockgating_state(void *handle,
768 enum amd_clockgating_state state)
769{
770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
771
772 switch (adev->asic_type) {
773 case CHIP_VEGA10:
774 nbio_v6_1_update_medium_grain_clock_gating(adev,
775 state == AMD_CG_STATE_GATE ? true : false);
776 nbio_v6_1_update_medium_grain_light_sleep(adev,
777 state == AMD_CG_STATE_GATE ? true : false);
778 soc15_update_hdp_light_sleep(adev,
779 state == AMD_CG_STATE_GATE ? true : false);
780 soc15_update_drm_clock_gating(adev,
781 state == AMD_CG_STATE_GATE ? true : false);
782 soc15_update_drm_light_sleep(adev,
783 state == AMD_CG_STATE_GATE ? true : false);
784 soc15_update_rom_medium_grain_clock_gating(adev,
785 state == AMD_CG_STATE_GATE ? true : false);
786 soc15_update_df_medium_grain_clock_gating(adev,
787 state == AMD_CG_STATE_GATE ? true : false);
788 break;
789 default:
790 break;
791 }
792 return 0;
793}
794
795static int soc15_common_set_powergating_state(void *handle,
796 enum amd_powergating_state state)
797{
798 /* todo */
799 return 0;
800}
801
802const struct amd_ip_funcs soc15_common_ip_funcs = {
803 .name = "soc15_common",
804 .early_init = soc15_common_early_init,
805 .late_init = NULL,
806 .sw_init = soc15_common_sw_init,
807 .sw_fini = soc15_common_sw_fini,
808 .hw_init = soc15_common_hw_init,
809 .hw_fini = soc15_common_hw_fini,
810 .suspend = soc15_common_suspend,
811 .resume = soc15_common_resume,
812 .is_idle = soc15_common_is_idle,
813 .wait_for_idle = soc15_common_wait_for_idle,
814 .soft_reset = soc15_common_soft_reset,
815 .set_clockgating_state = soc15_common_set_clockgating_state,
816 .set_powergating_state = soc15_common_set_powergating_state,
817};
Linux 6.x block layer and io_uring tree(s)