Commit | Line | Data |
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220ab9bd KW |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/module.h> | |
47b757fb SR |
26 | #include <linux/pci.h> |
27 | ||
6f786950 AD |
28 | #include <drm/amdgpu_drm.h> |
29 | ||
220ab9bd | 30 | #include "amdgpu.h" |
d05da0e2 | 31 | #include "amdgpu_atombios.h" |
220ab9bd KW |
32 | #include "amdgpu_ih.h" |
33 | #include "amdgpu_uvd.h" | |
34 | #include "amdgpu_vce.h" | |
35 | #include "amdgpu_ucode.h" | |
36 | #include "amdgpu_psp.h" | |
37 | #include "atom.h" | |
38 | #include "amd_pcie.h" | |
39 | ||
5d735f83 | 40 | #include "uvd/uvd_7_0_offset.h" |
cde5c34f FX |
41 | #include "gc/gc_9_0_offset.h" |
42 | #include "gc/gc_9_0_sh_mask.h" | |
812f77b7 FX |
43 | #include "sdma0/sdma0_4_0_offset.h" |
44 | #include "sdma1/sdma1_4_0_offset.h" | |
b45e18ac | 45 | #include "nbio/nbio_7_0_default.h" |
88807dc8 | 46 | #include "nbio/nbio_7_0_offset.h" |
b45e18ac KR |
47 | #include "nbio/nbio_7_0_sh_mask.h" |
48 | #include "nbio/nbio_7_0_smn.h" | |
9281f12c | 49 | #include "mp/mp_9_0_offset.h" |
220ab9bd KW |
50 | |
51 | #include "soc15.h" | |
52 | #include "soc15_common.h" | |
53 | #include "gfx_v9_0.h" | |
54 | #include "gmc_v9_0.h" | |
55 | #include "gfxhub_v1_0.h" | |
56 | #include "mmhub_v1_0.h" | |
070706c0 | 57 | #include "df_v1_7.h" |
698758bb | 58 | #include "df_v3_6.h" |
bebc0762 HZ |
59 | #include "nbio_v6_1.h" |
60 | #include "nbio_v7_0.h" | |
61 | #include "nbio_v7_4.h" | |
455d40c9 | 62 | #include "hdp_v4_0.h" |
220ab9bd | 63 | #include "vega10_ih.h" |
320a2e0c | 64 | #include "vega20_ih.h" |
c1059360 | 65 | #include "navi10_ih.h" |
220ab9bd KW |
66 | #include "sdma_v4_0.h" |
67 | #include "uvd_v7_0.h" | |
68 | #include "vce_v4_0.h" | |
f2d7e707 | 69 | #include "vcn_v1_0.h" |
279ba48e | 70 | #include "vcn_v2_0.h" |
5be45a26 | 71 | #include "jpeg_v2_0.h" |
08249a3a | 72 | #include "vcn_v2_5.h" |
8c74e590 | 73 | #include "jpeg_v2_5.h" |
0e961589 HZ |
74 | #include "smuio_v9_0.h" |
75 | #include "smuio_v11_0.h" | |
7914a0cd | 76 | #include "smuio_v13_0.h" |
796b6568 | 77 | #include "dce_virtual.h" |
f1a34465 | 78 | #include "mxgpu_ai.h" |
e74609cb AD |
79 | #include "amdgpu_ras.h" |
80 | #include "amdgpu_xgmi.h" | |
88807dc8 | 81 | #include <uapi/linux/kfd_ioctl.h> |
220ab9bd | 82 | |
220ab9bd KW |
83 | #define mmMP0_MISC_CGTT_CTRL0 0x01b9 |
84 | #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 | |
85 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba | |
86 | #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 | |
87 | ||
3b246e8b AD |
88 | /* Vega, Raven, Arcturus */ |
89 | static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = | |
90 | { | |
91 | { | |
6f786950 | 92 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
93 | .max_width = 4096, |
94 | .max_height = 2304, | |
95 | .max_pixels_per_frame = 4096 * 2304, | |
96 | .max_level = 0, | |
97 | }, | |
98 | { | |
6f786950 | 99 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
100 | .max_width = 4096, |
101 | .max_height = 2304, | |
102 | .max_pixels_per_frame = 4096 * 2304, | |
103 | .max_level = 0, | |
104 | }, | |
105 | }; | |
106 | ||
107 | static const struct amdgpu_video_codecs vega_video_codecs_encode = | |
108 | { | |
109 | .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), | |
110 | .codec_array = vega_video_codecs_encode_array, | |
111 | }; | |
112 | ||
113 | /* Vega */ | |
114 | static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = | |
115 | { | |
116 | { | |
6f786950 | 117 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
118 | .max_width = 4096, |
119 | .max_height = 4096, | |
120 | .max_pixels_per_frame = 4096 * 4096, | |
121 | .max_level = 3, | |
122 | }, | |
123 | { | |
6f786950 | 124 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
125 | .max_width = 4096, |
126 | .max_height = 4096, | |
127 | .max_pixels_per_frame = 4096 * 4096, | |
128 | .max_level = 5, | |
129 | }, | |
130 | { | |
6f786950 | 131 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
132 | .max_width = 4096, |
133 | .max_height = 4096, | |
134 | .max_pixels_per_frame = 4096 * 4096, | |
135 | .max_level = 52, | |
136 | }, | |
137 | { | |
6f786950 | 138 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
139 | .max_width = 4096, |
140 | .max_height = 4096, | |
141 | .max_pixels_per_frame = 4096 * 4096, | |
142 | .max_level = 4, | |
143 | }, | |
144 | { | |
6f786950 | 145 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
146 | .max_width = 4096, |
147 | .max_height = 4096, | |
148 | .max_pixels_per_frame = 4096 * 4096, | |
149 | .max_level = 186, | |
150 | }, | |
151 | { | |
6f786950 | 152 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
153 | .max_width = 4096, |
154 | .max_height = 4096, | |
155 | .max_pixels_per_frame = 4096 * 4096, | |
156 | .max_level = 0, | |
157 | }, | |
158 | }; | |
159 | ||
160 | static const struct amdgpu_video_codecs vega_video_codecs_decode = | |
161 | { | |
162 | .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), | |
163 | .codec_array = vega_video_codecs_decode_array, | |
164 | }; | |
165 | ||
166 | /* Raven */ | |
167 | static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = | |
168 | { | |
169 | { | |
6f786950 | 170 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
171 | .max_width = 4096, |
172 | .max_height = 4096, | |
173 | .max_pixels_per_frame = 4096 * 4096, | |
174 | .max_level = 3, | |
175 | }, | |
176 | { | |
6f786950 | 177 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
178 | .max_width = 4096, |
179 | .max_height = 4096, | |
180 | .max_pixels_per_frame = 4096 * 4096, | |
181 | .max_level = 5, | |
182 | }, | |
183 | { | |
6f786950 | 184 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
185 | .max_width = 4096, |
186 | .max_height = 4096, | |
187 | .max_pixels_per_frame = 4096 * 4096, | |
188 | .max_level = 52, | |
189 | }, | |
190 | { | |
6f786950 | 191 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
192 | .max_width = 4096, |
193 | .max_height = 4096, | |
194 | .max_pixels_per_frame = 4096 * 4096, | |
195 | .max_level = 4, | |
196 | }, | |
197 | { | |
6f786950 | 198 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
199 | .max_width = 4096, |
200 | .max_height = 4096, | |
201 | .max_pixels_per_frame = 4096 * 4096, | |
202 | .max_level = 186, | |
203 | }, | |
204 | { | |
6f786950 | 205 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
206 | .max_width = 4096, |
207 | .max_height = 4096, | |
208 | .max_pixels_per_frame = 4096 * 4096, | |
209 | .max_level = 0, | |
210 | }, | |
211 | { | |
6f786950 | 212 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, |
3b246e8b AD |
213 | .max_width = 4096, |
214 | .max_height = 4096, | |
215 | .max_pixels_per_frame = 4096 * 4096, | |
216 | .max_level = 0, | |
217 | }, | |
218 | }; | |
219 | ||
220 | static const struct amdgpu_video_codecs rv_video_codecs_decode = | |
221 | { | |
222 | .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), | |
223 | .codec_array = rv_video_codecs_decode_array, | |
224 | }; | |
225 | ||
226 | /* Renoir, Arcturus */ | |
227 | static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = | |
228 | { | |
229 | { | |
6f786950 | 230 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
231 | .max_width = 4096, |
232 | .max_height = 4096, | |
233 | .max_pixels_per_frame = 4096 * 4096, | |
234 | .max_level = 3, | |
235 | }, | |
236 | { | |
6f786950 | 237 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
238 | .max_width = 4096, |
239 | .max_height = 4096, | |
240 | .max_pixels_per_frame = 4096 * 4096, | |
241 | .max_level = 5, | |
242 | }, | |
243 | { | |
6f786950 | 244 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
245 | .max_width = 4096, |
246 | .max_height = 4096, | |
247 | .max_pixels_per_frame = 4096 * 4096, | |
248 | .max_level = 52, | |
249 | }, | |
250 | { | |
6f786950 | 251 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
252 | .max_width = 4096, |
253 | .max_height = 4096, | |
254 | .max_pixels_per_frame = 4096 * 4096, | |
255 | .max_level = 4, | |
256 | }, | |
257 | { | |
6f786950 | 258 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
259 | .max_width = 8192, |
260 | .max_height = 4352, | |
261 | .max_pixels_per_frame = 4096 * 4096, | |
262 | .max_level = 186, | |
263 | }, | |
264 | { | |
6f786950 | 265 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
266 | .max_width = 4096, |
267 | .max_height = 4096, | |
268 | .max_pixels_per_frame = 4096 * 4096, | |
269 | .max_level = 0, | |
270 | }, | |
271 | { | |
6f786950 | 272 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, |
3b246e8b AD |
273 | .max_width = 8192, |
274 | .max_height = 4352, | |
275 | .max_pixels_per_frame = 4096 * 4096, | |
276 | .max_level = 0, | |
277 | }, | |
278 | }; | |
279 | ||
280 | static const struct amdgpu_video_codecs rn_video_codecs_decode = | |
281 | { | |
282 | .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), | |
283 | .codec_array = rn_video_codecs_decode_array, | |
284 | }; | |
285 | ||
286 | static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, | |
287 | const struct amdgpu_video_codecs **codecs) | |
288 | { | |
289 | switch (adev->asic_type) { | |
290 | case CHIP_VEGA20: | |
291 | case CHIP_VEGA10: | |
292 | case CHIP_VEGA12: | |
293 | if (encode) | |
294 | *codecs = &vega_video_codecs_encode; | |
295 | else | |
296 | *codecs = &vega_video_codecs_decode; | |
297 | return 0; | |
298 | case CHIP_RAVEN: | |
299 | if (encode) | |
300 | *codecs = &vega_video_codecs_encode; | |
301 | else | |
302 | *codecs = &rv_video_codecs_decode; | |
303 | return 0; | |
304 | case CHIP_ARCTURUS: | |
305 | case CHIP_RENOIR: | |
306 | if (encode) | |
307 | *codecs = &vega_video_codecs_encode; | |
308 | else | |
309 | *codecs = &rn_video_codecs_decode; | |
310 | return 0; | |
311 | default: | |
312 | return -EINVAL; | |
313 | } | |
314 | } | |
315 | ||
220ab9bd KW |
316 | /* |
317 | * Indirect registers accessor | |
318 | */ | |
319 | static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) | |
320 | { | |
705a2b5b | 321 | unsigned long address, data; |
bebc0762 HZ |
322 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
323 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
220ab9bd | 324 | |
705a2b5b | 325 | return amdgpu_device_indirect_rreg(adev, address, data, reg); |
220ab9bd KW |
326 | } |
327 | ||
328 | static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
329 | { | |
705a2b5b | 330 | unsigned long address, data; |
220ab9bd | 331 | |
bebc0762 HZ |
332 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
333 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
220ab9bd | 334 | |
705a2b5b | 335 | amdgpu_device_indirect_wreg(adev, address, data, reg, v); |
220ab9bd KW |
336 | } |
337 | ||
4fa1c6a6 TZ |
338 | static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) |
339 | { | |
705a2b5b | 340 | unsigned long address, data; |
bebc0762 HZ |
341 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
342 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
4fa1c6a6 | 343 | |
705a2b5b | 344 | return amdgpu_device_indirect_rreg64(adev, address, data, reg); |
4fa1c6a6 TZ |
345 | } |
346 | ||
347 | static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) | |
348 | { | |
705a2b5b | 349 | unsigned long address, data; |
4fa1c6a6 | 350 | |
bebc0762 HZ |
351 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
352 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
4fa1c6a6 | 353 | |
705a2b5b | 354 | amdgpu_device_indirect_wreg64(adev, address, data, reg, v); |
4fa1c6a6 TZ |
355 | } |
356 | ||
220ab9bd KW |
357 | static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) |
358 | { | |
359 | unsigned long flags, address, data; | |
360 | u32 r; | |
361 | ||
362 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); | |
363 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); | |
364 | ||
365 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); | |
366 | WREG32(address, ((reg) & 0x1ff)); | |
367 | r = RREG32(data); | |
368 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); | |
369 | return r; | |
370 | } | |
371 | ||
372 | static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
373 | { | |
374 | unsigned long flags, address, data; | |
375 | ||
376 | address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); | |
377 | data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); | |
378 | ||
379 | spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); | |
380 | WREG32(address, ((reg) & 0x1ff)); | |
381 | WREG32(data, (v)); | |
382 | spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); | |
383 | } | |
384 | ||
385 | static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) | |
386 | { | |
387 | unsigned long flags, address, data; | |
388 | u32 r; | |
389 | ||
390 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); | |
391 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); | |
392 | ||
393 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
394 | WREG32(address, (reg)); | |
395 | r = RREG32(data); | |
396 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
397 | return r; | |
398 | } | |
399 | ||
400 | static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
401 | { | |
402 | unsigned long flags, address, data; | |
403 | ||
404 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); | |
405 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); | |
406 | ||
407 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
408 | WREG32(address, (reg)); | |
409 | WREG32(data, (v)); | |
410 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
411 | } | |
412 | ||
560460f2 EQ |
413 | static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) |
414 | { | |
415 | unsigned long flags; | |
416 | u32 r; | |
417 | ||
418 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); | |
419 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); | |
420 | r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); | |
421 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); | |
422 | return r; | |
423 | } | |
424 | ||
425 | static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
426 | { | |
427 | unsigned long flags; | |
428 | ||
429 | spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); | |
430 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); | |
431 | WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); | |
432 | spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); | |
433 | } | |
434 | ||
2f11fb02 EQ |
435 | static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) |
436 | { | |
437 | unsigned long flags; | |
438 | u32 r; | |
439 | ||
440 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); | |
441 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); | |
442 | r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); | |
443 | spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); | |
444 | return r; | |
445 | } | |
446 | ||
447 | static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
448 | { | |
449 | unsigned long flags; | |
450 | ||
451 | spin_lock_irqsave(&adev->se_cac_idx_lock, flags); | |
452 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); | |
453 | WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); | |
454 | spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); | |
455 | } | |
456 | ||
220ab9bd KW |
457 | static u32 soc15_get_config_memsize(struct amdgpu_device *adev) |
458 | { | |
bebc0762 | 459 | return adev->nbio.funcs->get_memsize(adev); |
220ab9bd KW |
460 | } |
461 | ||
220ab9bd KW |
462 | static u32 soc15_get_xclk(struct amdgpu_device *adev) |
463 | { | |
b90c4d66 AD |
464 | u32 reference_clock = adev->clock.spll.reference_freq; |
465 | ||
6e80fb8a AD |
466 | if (adev->asic_type == CHIP_RENOIR) |
467 | return 10000; | |
b90c4d66 AD |
468 | if (adev->asic_type == CHIP_RAVEN) |
469 | return reference_clock / 4; | |
470 | ||
471 | return reference_clock; | |
220ab9bd KW |
472 | } |
473 | ||
474 | ||
475 | void soc15_grbm_select(struct amdgpu_device *adev, | |
476 | u32 me, u32 pipe, u32 queue, u32 vmid) | |
477 | { | |
478 | u32 grbm_gfx_cntl = 0; | |
479 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); | |
480 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); | |
481 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); | |
482 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); | |
483 | ||
1bff7f6c | 484 | WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); |
220ab9bd KW |
485 | } |
486 | ||
487 | static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) | |
488 | { | |
489 | /* todo */ | |
490 | } | |
491 | ||
492 | static bool soc15_read_disabled_bios(struct amdgpu_device *adev) | |
493 | { | |
494 | /* todo */ | |
495 | return false; | |
496 | } | |
497 | ||
498 | static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, | |
499 | u8 *bios, u32 length_bytes) | |
500 | { | |
501 | u32 *dw_ptr; | |
502 | u32 i, length_dw; | |
1a0dd3d9 HZ |
503 | uint32_t rom_index_offset; |
504 | uint32_t rom_data_offset; | |
220ab9bd KW |
505 | |
506 | if (bios == NULL) | |
507 | return false; | |
508 | if (length_bytes == 0) | |
509 | return false; | |
510 | /* APU vbios image is part of sbios image */ | |
511 | if (adev->flags & AMD_IS_APU) | |
512 | return false; | |
513 | ||
514 | dw_ptr = (u32 *)bios; | |
515 | length_dw = ALIGN(length_bytes, 4) / 4; | |
516 | ||
0e961589 HZ |
517 | rom_index_offset = |
518 | adev->smuio.funcs->get_rom_index_offset(adev); | |
519 | rom_data_offset = | |
520 | adev->smuio.funcs->get_rom_data_offset(adev); | |
1a0dd3d9 | 521 | |
220ab9bd | 522 | /* set rom index to 0 */ |
1a0dd3d9 | 523 | WREG32(rom_index_offset, 0); |
220ab9bd KW |
524 | /* read out the rom data */ |
525 | for (i = 0; i < length_dw; i++) | |
1a0dd3d9 | 526 | dw_ptr[i] = RREG32(rom_data_offset); |
220ab9bd KW |
527 | |
528 | return true; | |
529 | } | |
530 | ||
946a4d5b SL |
531 | static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { |
532 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, | |
533 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, | |
534 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, | |
535 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, | |
536 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, | |
537 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, | |
538 | { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, | |
539 | { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, | |
540 | { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, | |
541 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, | |
542 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, | |
543 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, | |
544 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, | |
545 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, | |
546 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, | |
664fe85a | 547 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, |
946a4d5b SL |
548 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, |
549 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, | |
550 | { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, | |
5eeae247 | 551 | { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, |
220ab9bd KW |
552 | }; |
553 | ||
554 | static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, | |
555 | u32 sh_num, u32 reg_offset) | |
556 | { | |
557 | uint32_t val; | |
558 | ||
559 | mutex_lock(&adev->grbm_idx_mutex); | |
560 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
561 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); | |
562 | ||
563 | val = RREG32(reg_offset); | |
564 | ||
565 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
566 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
567 | mutex_unlock(&adev->grbm_idx_mutex); | |
568 | return val; | |
569 | } | |
570 | ||
c013cea2 AD |
571 | static uint32_t soc15_get_register_value(struct amdgpu_device *adev, |
572 | bool indexed, u32 se_num, | |
573 | u32 sh_num, u32 reg_offset) | |
574 | { | |
575 | if (indexed) { | |
576 | return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); | |
577 | } else { | |
cd29253f | 578 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) |
c013cea2 | 579 | return adev->gfx.config.gb_addr_config; |
5eeae247 AD |
580 | else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) |
581 | return adev->gfx.config.db_debug2; | |
cd29253f | 582 | return RREG32(reg_offset); |
c013cea2 AD |
583 | } |
584 | } | |
585 | ||
220ab9bd KW |
586 | static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, |
587 | u32 sh_num, u32 reg_offset, u32 *value) | |
588 | { | |
3032f350 | 589 | uint32_t i; |
946a4d5b | 590 | struct soc15_allowed_register_entry *en; |
220ab9bd KW |
591 | |
592 | *value = 0; | |
220ab9bd | 593 | for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { |
946a4d5b | 594 | en = &soc15_allowed_read_registers[i]; |
207f0f13 PL |
595 | if (adev->reg_offset[en->hwip][en->inst] && |
596 | reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] | |
946a4d5b | 597 | + en->reg_offset)) |
220ab9bd KW |
598 | continue; |
599 | ||
97fcc76b CK |
600 | *value = soc15_get_register_value(adev, |
601 | soc15_allowed_read_registers[i].grbm_indexed, | |
602 | se_num, sh_num, reg_offset); | |
220ab9bd KW |
603 | return 0; |
604 | } | |
605 | return -EINVAL; | |
606 | } | |
607 | ||
946a4d5b SL |
608 | |
609 | /** | |
610 | * soc15_program_register_sequence - program an array of registers. | |
611 | * | |
612 | * @adev: amdgpu_device pointer | |
613 | * @regs: pointer to the register array | |
614 | * @array_size: size of the register array | |
615 | * | |
616 | * Programs an array or registers with and and or masks. | |
617 | * This is a helper for setting golden registers. | |
618 | */ | |
619 | ||
620 | void soc15_program_register_sequence(struct amdgpu_device *adev, | |
621 | const struct soc15_reg_golden *regs, | |
622 | const u32 array_size) | |
623 | { | |
624 | const struct soc15_reg_golden *entry; | |
625 | u32 tmp, reg; | |
626 | int i; | |
627 | ||
628 | for (i = 0; i < array_size; ++i) { | |
629 | entry = ®s[i]; | |
630 | reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; | |
631 | ||
632 | if (entry->and_mask == 0xffffffff) { | |
633 | tmp = entry->or_mask; | |
634 | } else { | |
635 | tmp = RREG32(reg); | |
636 | tmp &= ~(entry->and_mask); | |
e0d07657 | 637 | tmp |= (entry->or_mask & entry->and_mask); |
946a4d5b | 638 | } |
1bff7f6c TH |
639 | |
640 | if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || | |
641 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || | |
642 | reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || | |
643 | reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) | |
644 | WREG32_RLC(reg, tmp); | |
645 | else | |
646 | WREG32(reg, tmp); | |
647 | ||
946a4d5b SL |
648 | } |
649 | ||
650 | } | |
651 | ||
e2b6d053 JQ |
652 | static int soc15_asic_baco_reset(struct amdgpu_device *adev) |
653 | { | |
956f6705 | 654 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 655 | int ret = 0; |
e2b6d053 | 656 | |
956f6705 | 657 | /* avoid NBIF got stuck when do RAS recovery in BACO reset */ |
8ab0d6f0 | 658 | if (ras && adev->ras_enabled) |
956f6705 LM |
659 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
660 | ||
9530273e EQ |
661 | ret = amdgpu_dpm_baco_reset(adev); |
662 | if (ret) | |
663 | return ret; | |
e2b6d053 | 664 | |
956f6705 | 665 | /* re-enable doorbell interrupt after BACO exit */ |
8ab0d6f0 | 666 | if (ras && adev->ras_enabled) |
956f6705 LM |
667 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
668 | ||
e2b6d053 JQ |
669 | return 0; |
670 | } | |
671 | ||
ee360c0b AD |
672 | static enum amd_reset_method |
673 | soc15_asic_reset_method(struct amdgpu_device *adev) | |
e2b6d053 | 674 | { |
feffbaac | 675 | bool baco_reset = false; |
5c03e584 | 676 | bool connected_to_cpu = false; |
feffbaac | 677 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
e2b6d053 | 678 | |
5c03e584 FX |
679 | if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) |
680 | connected_to_cpu = true; | |
681 | ||
273da6ff WS |
682 | if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || |
683 | amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || | |
1176a1e0 | 684 | amdgpu_reset_method == AMD_RESET_METHOD_BACO || |
5c03e584 FX |
685 | amdgpu_reset_method == AMD_RESET_METHOD_PCI) { |
686 | /* If connected to cpu, driver only support mode2 */ | |
687 | if (connected_to_cpu) | |
688 | return AMD_RESET_METHOD_MODE2; | |
689 | return amdgpu_reset_method; | |
690 | } | |
273da6ff WS |
691 | |
692 | if (amdgpu_reset_method != -1) | |
693 | dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", | |
694 | amdgpu_reset_method); | |
695 | ||
e2b6d053 | 696 | switch (adev->asic_type) { |
ee360c0b | 697 | case CHIP_RAVEN: |
90a08351 | 698 | case CHIP_RENOIR: |
ee360c0b | 699 | return AMD_RESET_METHOD_MODE2; |
e2b6d053 | 700 | case CHIP_VEGA10: |
f8b18cf4 | 701 | case CHIP_VEGA12: |
0a650c1d | 702 | case CHIP_ARCTURUS: |
9530273e | 703 | baco_reset = amdgpu_dpm_is_baco_supported(adev); |
e2b6d053 | 704 | break; |
017d75f1 EQ |
705 | case CHIP_VEGA20: |
706 | if (adev->psp.sos_fw_version >= 0x80067) | |
9530273e | 707 | baco_reset = amdgpu_dpm_is_baco_supported(adev); |
e74609cb | 708 | |
feffbaac LM |
709 | /* |
710 | * 1. PMFW version > 0x284300: all cases use baco | |
711 | * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco | |
712 | */ | |
8ab0d6f0 | 713 | if (ras && adev->ras_enabled && |
acdae216 | 714 | adev->pm.fw_version <= 0x283400) |
feffbaac | 715 | baco_reset = false; |
017d75f1 | 716 | break; |
5c03e584 FX |
717 | case CHIP_ALDEBARAN: |
718 | /* | |
719 | * 1.connected to cpu: driver issue mode2 reset | |
720 | * 2.discret gpu: driver issue mode1 reset | |
721 | */ | |
722 | if (connected_to_cpu) | |
723 | return AMD_RESET_METHOD_MODE2; | |
724 | break; | |
e2b6d053 | 725 | default: |
e2b6d053 JQ |
726 | break; |
727 | } | |
728 | ||
729 | if (baco_reset) | |
ee360c0b AD |
730 | return AMD_RESET_METHOD_BACO; |
731 | else | |
732 | return AMD_RESET_METHOD_MODE1; | |
733 | } | |
734 | ||
735 | static int soc15_asic_reset(struct amdgpu_device *adev) | |
736 | { | |
276cc929 | 737 | /* original raven doesn't have full asic reset */ |
54f78a76 AD |
738 | if ((adev->apu_flags & AMD_APU_IS_RAVEN) && |
739 | !(adev->apu_flags & AMD_APU_IS_RAVEN2)) | |
276cc929 AD |
740 | return 0; |
741 | ||
c43b849f | 742 | switch (soc15_asic_reset_method(adev)) { |
1176a1e0 AD |
743 | case AMD_RESET_METHOD_PCI: |
744 | dev_info(adev->dev, "PCI reset\n"); | |
745 | return amdgpu_device_pci_reset(adev); | |
746 | case AMD_RESET_METHOD_BACO: | |
747 | dev_info(adev->dev, "BACO reset\n"); | |
748 | return soc15_asic_baco_reset(adev); | |
749 | case AMD_RESET_METHOD_MODE2: | |
750 | dev_info(adev->dev, "MODE2 reset\n"); | |
751 | return amdgpu_dpm_mode2_reset(adev); | |
752 | default: | |
753 | dev_info(adev->dev, "MODE1 reset\n"); | |
5c03e584 | 754 | return amdgpu_device_mode1_reset(adev); |
c43b849f | 755 | } |
e2b6d053 JQ |
756 | } |
757 | ||
988eb9ff AD |
758 | static bool soc15_supports_baco(struct amdgpu_device *adev) |
759 | { | |
988eb9ff AD |
760 | switch (adev->asic_type) { |
761 | case CHIP_VEGA10: | |
762 | case CHIP_VEGA12: | |
b8ab58f3 | 763 | case CHIP_ARCTURUS: |
9530273e | 764 | return amdgpu_dpm_is_baco_supported(adev); |
988eb9ff AD |
765 | case CHIP_VEGA20: |
766 | if (adev->psp.sos_fw_version >= 0x80067) | |
9530273e EQ |
767 | return amdgpu_dpm_is_baco_supported(adev); |
768 | return false; | |
988eb9ff AD |
769 | default: |
770 | return false; | |
771 | } | |
988eb9ff AD |
772 | } |
773 | ||
220ab9bd KW |
774 | /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, |
775 | u32 cntl_reg, u32 status_reg) | |
776 | { | |
777 | return 0; | |
778 | }*/ | |
779 | ||
780 | static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) | |
781 | { | |
782 | /*int r; | |
783 | ||
784 | r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); | |
785 | if (r) | |
786 | return r; | |
787 | ||
788 | r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); | |
789 | */ | |
790 | return 0; | |
791 | } | |
792 | ||
793 | static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) | |
794 | { | |
795 | /* todo */ | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) | |
801 | { | |
802 | if (pci_is_root_bus(adev->pdev->bus)) | |
803 | return; | |
804 | ||
805 | if (amdgpu_pcie_gen2 == 0) | |
806 | return; | |
807 | ||
808 | if (adev->flags & AMD_IS_APU) | |
809 | return; | |
810 | ||
811 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
812 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) | |
813 | return; | |
814 | ||
815 | /* todo */ | |
816 | } | |
817 | ||
818 | static void soc15_program_aspm(struct amdgpu_device *adev) | |
819 | { | |
9d015c0d | 820 | if (amdgpu_aspm != 1) |
220ab9bd KW |
821 | return; |
822 | ||
9d015c0d KF |
823 | if (!(adev->flags & AMD_IS_APU) && |
824 | (adev->nbio.funcs->program_aspm)) | |
825 | adev->nbio.funcs->program_aspm(adev); | |
220ab9bd KW |
826 | } |
827 | ||
828 | static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, | |
bf383fb6 | 829 | bool enable) |
220ab9bd | 830 | { |
bebc0762 HZ |
831 | adev->nbio.funcs->enable_doorbell_aperture(adev, enable); |
832 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); | |
220ab9bd KW |
833 | } |
834 | ||
835 | static const struct amdgpu_ip_block_version vega10_common_ip_block = | |
836 | { | |
837 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
838 | .major = 2, | |
839 | .minor = 0, | |
840 | .rev = 0, | |
841 | .funcs = &soc15_common_ip_funcs, | |
842 | }; | |
843 | ||
4cb0becb HR |
844 | static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) |
845 | { | |
bebc0762 | 846 | return adev->nbio.funcs->get_rev_id(adev); |
4cb0becb HR |
847 | } |
848 | ||
d95f09ac | 849 | static void soc15_reg_base_init(struct amdgpu_device *adev) |
220ab9bd | 850 | { |
c1cf79ca AD |
851 | int r; |
852 | ||
4522824c SL |
853 | /* Set IP register base before any HW register access */ |
854 | switch (adev->asic_type) { | |
855 | case CHIP_VEGA10: | |
3084eb00 | 856 | case CHIP_VEGA12: |
4522824c SL |
857 | case CHIP_RAVEN: |
858 | vega10_reg_base_init(adev); | |
859 | break; | |
c1cf79ca | 860 | case CHIP_RENOIR: |
d95f09ac WS |
861 | /* It's safe to do ip discovery here for Renior, |
862 | * it doesn't support SRIOV. */ | |
c1cf79ca AD |
863 | if (amdgpu_discovery) { |
864 | r = amdgpu_discovery_reg_base_init(adev); | |
2ae78708 DG |
865 | if (r == 0) |
866 | break; | |
867 | DRM_WARN("failed to init reg base from ip discovery table, " | |
868 | "fallback to legacy init method\n"); | |
c1cf79ca | 869 | } |
2ae78708 | 870 | vega10_reg_base_init(adev); |
c1cf79ca | 871 | break; |
8ee273e5 FX |
872 | case CHIP_VEGA20: |
873 | vega20_reg_base_init(adev); | |
874 | break; | |
e78705ec LM |
875 | case CHIP_ARCTURUS: |
876 | arct_reg_base_init(adev); | |
877 | break; | |
42b72608 LM |
878 | case CHIP_ALDEBARAN: |
879 | aldebaran_reg_base_init(adev); | |
880 | break; | |
4522824c | 881 | default: |
d95f09ac WS |
882 | DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); |
883 | break; | |
4522824c | 884 | } |
d95f09ac WS |
885 | } |
886 | ||
887 | void soc15_set_virt_ops(struct amdgpu_device *adev) | |
888 | { | |
889 | adev->virt.ops = &xgpu_ai_virt_ops; | |
890 | ||
891 | /* init soc15 reg base early enough so we can | |
892 | * request request full access for sriov before | |
893 | * set_ip_blocks. */ | |
894 | soc15_reg_base_init(adev); | |
895 | } | |
896 | ||
897 | int soc15_set_ip_blocks(struct amdgpu_device *adev) | |
898 | { | |
899 | /* for bare metal case */ | |
900 | if (!amdgpu_sriov_vf(adev)) | |
901 | soc15_reg_base_init(adev); | |
4522824c | 902 | |
bebc0762 HZ |
903 | if (adev->flags & AMD_IS_APU) { |
904 | adev->nbio.funcs = &nbio_v7_0_funcs; | |
905 | adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; | |
906 | } else if (adev->asic_type == CHIP_VEGA20 || | |
7906af5e LM |
907 | adev->asic_type == CHIP_ARCTURUS || |
908 | adev->asic_type == CHIP_ALDEBARAN) { | |
bebc0762 HZ |
909 | adev->nbio.funcs = &nbio_v7_4_funcs; |
910 | adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; | |
911 | } else { | |
912 | adev->nbio.funcs = &nbio_v6_1_funcs; | |
913 | adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; | |
914 | } | |
455d40c9 | 915 | adev->hdp.funcs = &hdp_v4_0_funcs; |
bf383fb6 | 916 | |
7906af5e LM |
917 | if (adev->asic_type == CHIP_VEGA20 || |
918 | adev->asic_type == CHIP_ARCTURUS || | |
919 | adev->asic_type == CHIP_ALDEBARAN) | |
bdf84a80 | 920 | adev->df.funcs = &df_v3_6_funcs; |
698758bb | 921 | else |
bdf84a80 | 922 | adev->df.funcs = &df_v1_7_funcs; |
4cb0becb | 923 | |
0e961589 HZ |
924 | if (adev->asic_type == CHIP_VEGA20 || |
925 | adev->asic_type == CHIP_ARCTURUS) | |
926 | adev->smuio.funcs = &smuio_v11_0_funcs; | |
7914a0cd HZ |
927 | else if (adev->asic_type == CHIP_ALDEBARAN) |
928 | adev->smuio.funcs = &smuio_v13_0_funcs; | |
0e961589 HZ |
929 | else |
930 | adev->smuio.funcs = &smuio_v9_0_funcs; | |
931 | ||
4cb0becb | 932 | adev->rev_id = soc15_get_rev_id(adev); |
1b922423 | 933 | |
220ab9bd KW |
934 | switch (adev->asic_type) { |
935 | case CHIP_VEGA10: | |
692069a1 | 936 | case CHIP_VEGA12: |
7c7af6c1 | 937 | case CHIP_VEGA20: |
2990a1fc AD |
938 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
939 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
2d11fd3f TH |
940 | |
941 | /* For Vega10 SR-IOV, PSP need to be initialized before IH */ | |
942 | if (amdgpu_sriov_vf(adev)) { | |
943 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { | |
944 | if (adev->asic_type == CHIP_VEGA20) | |
945 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
946 | else | |
947 | amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); | |
948 | } | |
c1059360 | 949 | if (adev->asic_type == CHIP_VEGA20) |
320a2e0c | 950 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
c1059360 AS |
951 | else |
952 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); | |
2d11fd3f | 953 | } else { |
c1059360 | 954 | if (adev->asic_type == CHIP_VEGA20) |
320a2e0c | 955 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
c1059360 AS |
956 | else |
957 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); | |
2d11fd3f TH |
958 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { |
959 | if (adev->asic_type == CHIP_VEGA20) | |
960 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
961 | else | |
962 | amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); | |
963 | } | |
3680b2a5 | 964 | } |
009d9ed6 RZ |
965 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
966 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
c9ffa427 YT |
967 | if (is_support_sw_smu(adev)) { |
968 | if (!amdgpu_sriov_vf(adev)) | |
2da5410b | 969 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
c9ffa427 YT |
970 | } else { |
971 | amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); | |
2da5410b | 972 | } |
f8445307 | 973 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
2990a1fc | 974 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
ab587d4a AD |
975 | #if defined(CONFIG_DRM_AMD_DC) |
976 | else if (amdgpu_device_has_dc_support(adev)) | |
2990a1fc | 977 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
ab587d4a | 978 | #endif |
846311ae FM |
979 | if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { |
980 | amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); | |
981 | amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); | |
982 | } | |
220ab9bd | 983 | break; |
1023b797 | 984 | case CHIP_RAVEN: |
40c2358b HR |
985 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); |
986 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
2990a1fc | 987 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); |
3680b2a5 EQ |
988 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
989 | amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); | |
009d9ed6 RZ |
990 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
991 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
b905090d | 992 | amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); |
d67fed16 | 993 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
2990a1fc | 994 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); |
0bf954c1 AD |
995 | #if defined(CONFIG_DRM_AMD_DC) |
996 | else if (amdgpu_device_has_dc_support(adev)) | |
2990a1fc | 997 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
0bf954c1 | 998 | #endif |
2990a1fc | 999 | amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); |
1023b797 | 1000 | break; |
0e54df05 LM |
1001 | case CHIP_ARCTURUS: |
1002 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); | |
1003 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
21889cec JZ |
1004 | |
1005 | if (amdgpu_sriov_vf(adev)) { | |
1006 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
1007 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
320a2e0c | 1008 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
21889cec | 1009 | } else { |
320a2e0c | 1010 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
21889cec JZ |
1011 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
1012 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
1013 | } | |
1014 | ||
0e54df05 LM |
1015 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
1016 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
1017 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); | |
1018 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
c2a801af | 1019 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
21889cec | 1020 | |
ab5999de JJ |
1021 | if (amdgpu_sriov_vf(adev)) { |
1022 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
1023 | amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); | |
1024 | } else { | |
e7ddb878 | 1025 | amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); |
ab5999de | 1026 | } |
e416fdb6 JZ |
1027 | if (!amdgpu_sriov_vf(adev)) |
1028 | amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); | |
0e54df05 | 1029 | break; |
05e1f0e0 HR |
1030 | case CHIP_RENOIR: |
1031 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); | |
1032 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
1033 | amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); | |
6a7a0bdb AL |
1034 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
1035 | amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); | |
9530273e | 1036 | amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); |
97222cfa AL |
1037 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
1038 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
b1326bbc AL |
1039 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
1040 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
e1c14c43 RL |
1041 | #if defined(CONFIG_DRM_AMD_DC) |
1042 | else if (amdgpu_device_has_dc_support(adev)) | |
94ba290d | 1043 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
e1c14c43 | 1044 | #endif |
279ba48e | 1045 | amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); |
5be45a26 | 1046 | amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); |
05e1f0e0 | 1047 | break; |
7906af5e LM |
1048 | case CHIP_ALDEBARAN: |
1049 | amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); | |
1050 | amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); | |
9fbd96a1 HZ |
1051 | |
1052 | if (amdgpu_sriov_vf(adev)) { | |
1053 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
1054 | amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); | |
10c71e6c | 1055 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
9fbd96a1 | 1056 | } else { |
10c71e6c | 1057 | amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); |
9fbd96a1 HZ |
1058 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
1059 | amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); | |
1060 | } | |
1061 | ||
7906af5e LM |
1062 | amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); |
1063 | amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); | |
9f386fd3 | 1064 | |
bd7228ab | 1065 | amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); |
fdb1fdef JZ |
1066 | amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); |
1067 | amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); | |
7906af5e | 1068 | break; |
220ab9bd KW |
1069 | default: |
1070 | return -EINVAL; | |
1071 | } | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
adbd4f89 AD |
1076 | static bool soc15_need_full_reset(struct amdgpu_device *adev) |
1077 | { | |
1078 | /* change this when we implement soft reset */ | |
1079 | return true; | |
1080 | } | |
4a89ad9b | 1081 | |
b45e18ac KR |
1082 | static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
1083 | uint64_t *count1) | |
1084 | { | |
1085 | uint32_t perfctr = 0; | |
1086 | uint64_t cnt0_of, cnt1_of; | |
1087 | int tmp; | |
1088 | ||
1089 | /* This reports 0 on APUs, so return to avoid writing/reading registers | |
1090 | * that may or may not be different from their GPU counterparts | |
1091 | */ | |
0172591e ES |
1092 | if (adev->flags & AMD_IS_APU) |
1093 | return; | |
b45e18ac KR |
1094 | |
1095 | /* Set the 2 events that we wish to watch, defined above */ | |
9417f703 | 1096 | /* Reg 40 is # received msgs */ |
612e4ed9 | 1097 | /* Reg 104 is # of posted requests sent */ |
b45e18ac | 1098 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); |
612e4ed9 | 1099 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); |
b45e18ac KR |
1100 | |
1101 | /* Write to enable desired perf counters */ | |
1102 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); | |
1103 | /* Zero out and enable the perf counters | |
1104 | * Write 0x5: | |
1105 | * Bit 0 = Start all counters(1) | |
1106 | * Bit 2 = Global counter reset enable(1) | |
1107 | */ | |
1108 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); | |
1109 | ||
1110 | msleep(1000); | |
1111 | ||
1112 | /* Load the shadow and disable the perf counters | |
1113 | * Write 0x2: | |
1114 | * Bit 0 = Stop counters(0) | |
1115 | * Bit 1 = Load the shadow counters(1) | |
1116 | */ | |
1117 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); | |
1118 | ||
1119 | /* Read register values to get any >32bit overflow */ | |
1120 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); | |
1121 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); | |
1122 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); | |
1123 | ||
1124 | /* Get the values and add the overflow */ | |
1125 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); | |
1126 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); | |
1127 | } | |
adbd4f89 | 1128 | |
612e4ed9 KR |
1129 | static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, |
1130 | uint64_t *count1) | |
1131 | { | |
1132 | uint32_t perfctr = 0; | |
1133 | uint64_t cnt0_of, cnt1_of; | |
1134 | int tmp; | |
1135 | ||
1136 | /* This reports 0 on APUs, so return to avoid writing/reading registers | |
1137 | * that may or may not be different from their GPU counterparts | |
1138 | */ | |
1139 | if (adev->flags & AMD_IS_APU) | |
1140 | return; | |
1141 | ||
1142 | /* Set the 2 events that we wish to watch, defined above */ | |
1143 | /* Reg 40 is # received msgs */ | |
1144 | /* Reg 108 is # of posted requests sent on VG20 */ | |
1145 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, | |
1146 | EVENT0_SEL, 40); | |
1147 | perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, | |
1148 | EVENT1_SEL, 108); | |
1149 | ||
1150 | /* Write to enable desired perf counters */ | |
1151 | WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); | |
1152 | /* Zero out and enable the perf counters | |
1153 | * Write 0x5: | |
1154 | * Bit 0 = Start all counters(1) | |
1155 | * Bit 2 = Global counter reset enable(1) | |
1156 | */ | |
1157 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); | |
1158 | ||
1159 | msleep(1000); | |
1160 | ||
1161 | /* Load the shadow and disable the perf counters | |
1162 | * Write 0x2: | |
1163 | * Bit 0 = Stop counters(0) | |
1164 | * Bit 1 = Load the shadow counters(1) | |
1165 | */ | |
1166 | WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); | |
1167 | ||
1168 | /* Read register values to get any >32bit overflow */ | |
1169 | tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); | |
1170 | cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); | |
1171 | cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); | |
1172 | ||
1173 | /* Get the values and add the overflow */ | |
1174 | *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); | |
1175 | *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); | |
1176 | } | |
1177 | ||
9281f12c AD |
1178 | static bool soc15_need_reset_on_init(struct amdgpu_device *adev) |
1179 | { | |
1180 | u32 sol_reg; | |
1181 | ||
d55f33da AD |
1182 | /* Just return false for soc15 GPUs. Reset does not seem to |
1183 | * be necessary. | |
1184 | */ | |
394e9a14 ED |
1185 | if (!amdgpu_passthrough(adev)) |
1186 | return false; | |
d55f33da | 1187 | |
9281f12c AD |
1188 | if (adev->flags & AMD_IS_APU) |
1189 | return false; | |
1190 | ||
1191 | /* Check sOS sign of life register to confirm sys driver and sOS | |
1192 | * are already been loaded. | |
1193 | */ | |
1194 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
1195 | if (sol_reg) | |
1196 | return true; | |
1197 | ||
1198 | return false; | |
1199 | } | |
1200 | ||
dcea6e65 KR |
1201 | static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) |
1202 | { | |
1203 | uint64_t nak_r, nak_g; | |
1204 | ||
1205 | /* Get the number of NAKs received and generated */ | |
1206 | nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); | |
1207 | nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); | |
1208 | ||
1209 | /* Add the total number of NAKs, i.e the number of replays */ | |
1210 | return (nak_r + nak_g); | |
1211 | } | |
1212 | ||
b0a2db9b AD |
1213 | static void soc15_pre_asic_init(struct amdgpu_device *adev) |
1214 | { | |
1215 | gmc_v9_0_restore_registers(adev); | |
1216 | } | |
1217 | ||
220ab9bd KW |
1218 | static const struct amdgpu_asic_funcs soc15_asic_funcs = |
1219 | { | |
1220 | .read_disabled_bios = &soc15_read_disabled_bios, | |
1221 | .read_bios_from_rom = &soc15_read_bios_from_rom, | |
1222 | .read_register = &soc15_read_register, | |
1223 | .reset = &soc15_asic_reset, | |
ee360c0b | 1224 | .reset_method = &soc15_asic_reset_method, |
220ab9bd KW |
1225 | .set_vga_state = &soc15_vga_set_state, |
1226 | .get_xclk = &soc15_get_xclk, | |
1227 | .set_uvd_clocks = &soc15_set_uvd_clocks, | |
1228 | .set_vce_clocks = &soc15_set_vce_clocks, | |
1229 | .get_config_memsize = &soc15_get_config_memsize, | |
adbd4f89 | 1230 | .need_full_reset = &soc15_need_full_reset, |
062f3807 | 1231 | .init_doorbell_index = &vega10_doorbell_index_init, |
b45e18ac | 1232 | .get_pcie_usage = &soc15_get_pcie_usage, |
9281f12c | 1233 | .need_reset_on_init = &soc15_need_reset_on_init, |
dcea6e65 | 1234 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
988eb9ff | 1235 | .supports_baco = &soc15_supports_baco, |
b0a2db9b | 1236 | .pre_asic_init = &soc15_pre_asic_init, |
3b246e8b | 1237 | .query_video_codecs = &soc15_query_video_codecs, |
220ab9bd KW |
1238 | }; |
1239 | ||
c93aa775 OZ |
1240 | static const struct amdgpu_asic_funcs vega20_asic_funcs = |
1241 | { | |
1242 | .read_disabled_bios = &soc15_read_disabled_bios, | |
1243 | .read_bios_from_rom = &soc15_read_bios_from_rom, | |
1244 | .read_register = &soc15_read_register, | |
1245 | .reset = &soc15_asic_reset, | |
761e0923 | 1246 | .reset_method = &soc15_asic_reset_method, |
c93aa775 OZ |
1247 | .set_vga_state = &soc15_vga_set_state, |
1248 | .get_xclk = &soc15_get_xclk, | |
1249 | .set_uvd_clocks = &soc15_set_uvd_clocks, | |
1250 | .set_vce_clocks = &soc15_set_vce_clocks, | |
1251 | .get_config_memsize = &soc15_get_config_memsize, | |
c93aa775 OZ |
1252 | .need_full_reset = &soc15_need_full_reset, |
1253 | .init_doorbell_index = &vega20_doorbell_index_init, | |
612e4ed9 | 1254 | .get_pcie_usage = &vega20_get_pcie_usage, |
9281f12c | 1255 | .need_reset_on_init = &soc15_need_reset_on_init, |
dcea6e65 | 1256 | .get_pcie_replay_count = &soc15_get_pcie_replay_count, |
988eb9ff | 1257 | .supports_baco = &soc15_supports_baco, |
b0a2db9b | 1258 | .pre_asic_init = &soc15_pre_asic_init, |
3b246e8b | 1259 | .query_video_codecs = &soc15_query_video_codecs, |
220ab9bd KW |
1260 | }; |
1261 | ||
1262 | static int soc15_common_early_init(void *handle) | |
1263 | { | |
88807dc8 | 1264 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) |
220ab9bd KW |
1265 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1266 | ||
88807dc8 OZ |
1267 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; |
1268 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; | |
220ab9bd KW |
1269 | adev->smc_rreg = NULL; |
1270 | adev->smc_wreg = NULL; | |
1271 | adev->pcie_rreg = &soc15_pcie_rreg; | |
1272 | adev->pcie_wreg = &soc15_pcie_wreg; | |
4fa1c6a6 TZ |
1273 | adev->pcie_rreg64 = &soc15_pcie_rreg64; |
1274 | adev->pcie_wreg64 = &soc15_pcie_wreg64; | |
220ab9bd KW |
1275 | adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; |
1276 | adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; | |
1277 | adev->didt_rreg = &soc15_didt_rreg; | |
1278 | adev->didt_wreg = &soc15_didt_wreg; | |
560460f2 EQ |
1279 | adev->gc_cac_rreg = &soc15_gc_cac_rreg; |
1280 | adev->gc_cac_wreg = &soc15_gc_cac_wreg; | |
2f11fb02 EQ |
1281 | adev->se_cac_rreg = &soc15_se_cac_rreg; |
1282 | adev->se_cac_wreg = &soc15_se_cac_wreg; | |
220ab9bd | 1283 | |
220ab9bd | 1284 | |
220ab9bd KW |
1285 | adev->external_rev_id = 0xFF; |
1286 | switch (adev->asic_type) { | |
1287 | case CHIP_VEGA10: | |
c93aa775 | 1288 | adev->asic_funcs = &soc15_asic_funcs; |
220ab9bd KW |
1289 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1290 | AMD_CG_SUPPORT_GFX_MGLS | | |
1291 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1292 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1293 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1294 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1295 | AMD_CG_SUPPORT_GFX_CGCG | | |
1296 | AMD_CG_SUPPORT_GFX_CGLS | | |
1297 | AMD_CG_SUPPORT_BIF_MGCG | | |
1298 | AMD_CG_SUPPORT_BIF_LS | | |
1299 | AMD_CG_SUPPORT_HDP_LS | | |
1300 | AMD_CG_SUPPORT_DRM_MGCG | | |
1301 | AMD_CG_SUPPORT_DRM_LS | | |
1302 | AMD_CG_SUPPORT_ROM_MGCG | | |
1303 | AMD_CG_SUPPORT_DF_MGCG | | |
1304 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1305 | AMD_CG_SUPPORT_SDMA_LS | | |
1306 | AMD_CG_SUPPORT_MC_MGCG | | |
1307 | AMD_CG_SUPPORT_MC_LS; | |
1308 | adev->pg_flags = 0; | |
1309 | adev->external_rev_id = 0x1; | |
1310 | break; | |
692069a1 | 1311 | case CHIP_VEGA12: |
c93aa775 | 1312 | adev->asic_funcs = &soc15_asic_funcs; |
e4a38755 EQ |
1313 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1314 | AMD_CG_SUPPORT_GFX_MGLS | | |
1315 | AMD_CG_SUPPORT_GFX_CGCG | | |
1316 | AMD_CG_SUPPORT_GFX_CGLS | | |
1317 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1318 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1319 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1320 | AMD_CG_SUPPORT_MC_LS | | |
1321 | AMD_CG_SUPPORT_MC_MGCG | | |
1322 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1323 | AMD_CG_SUPPORT_SDMA_LS | | |
1324 | AMD_CG_SUPPORT_BIF_MGCG | | |
1325 | AMD_CG_SUPPORT_BIF_LS | | |
1326 | AMD_CG_SUPPORT_HDP_MGCG | | |
1327 | AMD_CG_SUPPORT_HDP_LS | | |
1328 | AMD_CG_SUPPORT_ROM_MGCG | | |
1329 | AMD_CG_SUPPORT_VCE_MGCG | | |
1330 | AMD_CG_SUPPORT_UVD_MGCG; | |
692069a1 | 1331 | adev->pg_flags = 0; |
f559fe2b | 1332 | adev->external_rev_id = adev->rev_id + 0x14; |
692069a1 | 1333 | break; |
935be7a0 | 1334 | case CHIP_VEGA20: |
c93aa775 | 1335 | adev->asic_funcs = &vega20_asic_funcs; |
3fdbab5f EQ |
1336 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1337 | AMD_CG_SUPPORT_GFX_MGLS | | |
1338 | AMD_CG_SUPPORT_GFX_CGCG | | |
1339 | AMD_CG_SUPPORT_GFX_CGLS | | |
1340 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1341 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1342 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1343 | AMD_CG_SUPPORT_MC_LS | | |
1344 | AMD_CG_SUPPORT_MC_MGCG | | |
1345 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1346 | AMD_CG_SUPPORT_SDMA_LS | | |
1347 | AMD_CG_SUPPORT_BIF_MGCG | | |
1348 | AMD_CG_SUPPORT_BIF_LS | | |
1349 | AMD_CG_SUPPORT_HDP_MGCG | | |
102e4940 | 1350 | AMD_CG_SUPPORT_HDP_LS | |
3fdbab5f EQ |
1351 | AMD_CG_SUPPORT_ROM_MGCG | |
1352 | AMD_CG_SUPPORT_VCE_MGCG | | |
1353 | AMD_CG_SUPPORT_UVD_MGCG; | |
935be7a0 FX |
1354 | adev->pg_flags = 0; |
1355 | adev->external_rev_id = adev->rev_id + 0x28; | |
1356 | break; | |
957c6fe1 | 1357 | case CHIP_RAVEN: |
c93aa775 | 1358 | adev->asic_funcs = &soc15_asic_funcs; |
54f78a76 AD |
1359 | if (adev->pdev->device == 0x15dd) |
1360 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1361 | if (adev->pdev->device == 0x15d8) | |
1362 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
520cbe0f | 1363 | if (adev->rev_id >= 0x8) |
54f78a76 AD |
1364 | adev->apu_flags |= AMD_APU_IS_RAVEN2; |
1365 | ||
1366 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) | |
7e4545d3 | 1367 | adev->external_rev_id = adev->rev_id + 0x79; |
54f78a76 | 1368 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1369 | adev->external_rev_id = adev->rev_id + 0x41; |
7e4545d3 HR |
1370 | else if (adev->rev_id == 1) |
1371 | adev->external_rev_id = adev->rev_id + 0x20; | |
741deade | 1372 | else |
7e4545d3 | 1373 | adev->external_rev_id = adev->rev_id + 0x01; |
741deade | 1374 | |
54f78a76 | 1375 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) { |
520cbe0f HR |
1376 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1377 | AMD_CG_SUPPORT_GFX_MGLS | | |
1378 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1379 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1380 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1381 | AMD_CG_SUPPORT_GFX_CGCG | | |
1382 | AMD_CG_SUPPORT_GFX_CGLS | | |
1383 | AMD_CG_SUPPORT_BIF_LS | | |
1384 | AMD_CG_SUPPORT_HDP_LS | | |
520cbe0f HR |
1385 | AMD_CG_SUPPORT_MC_MGCG | |
1386 | AMD_CG_SUPPORT_MC_LS | | |
1387 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1388 | AMD_CG_SUPPORT_SDMA_LS | | |
1389 | AMD_CG_SUPPORT_VCN_MGCG; | |
741deade | 1390 | |
d5159591 | 1391 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
54f78a76 | 1392 | } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { |
fced5c70 LG |
1393 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1394 | AMD_CG_SUPPORT_GFX_MGLS | | |
741deade AD |
1395 | AMD_CG_SUPPORT_GFX_CP_LS | |
1396 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1397 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1398 | AMD_CG_SUPPORT_GFX_CGCG | | |
1399 | AMD_CG_SUPPORT_GFX_CGLS | | |
1400 | AMD_CG_SUPPORT_BIF_LS | | |
1401 | AMD_CG_SUPPORT_HDP_LS | | |
741deade AD |
1402 | AMD_CG_SUPPORT_MC_MGCG | |
1403 | AMD_CG_SUPPORT_MC_LS | | |
1404 | AMD_CG_SUPPORT_SDMA_MGCG | | |
a8f76887 S |
1405 | AMD_CG_SUPPORT_SDMA_LS | |
1406 | AMD_CG_SUPPORT_VCN_MGCG; | |
741deade AD |
1407 | |
1408 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | | |
1409 | AMD_PG_SUPPORT_MMHUB | | |
a10aad13 | 1410 | AMD_PG_SUPPORT_VCN; |
741deade | 1411 | } else { |
520cbe0f HR |
1412 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1413 | AMD_CG_SUPPORT_GFX_MGLS | | |
1414 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1415 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1416 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1417 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1418 | AMD_CG_SUPPORT_GFX_CGCG | | |
1419 | AMD_CG_SUPPORT_GFX_CGLS | | |
1420 | AMD_CG_SUPPORT_BIF_MGCG | | |
1421 | AMD_CG_SUPPORT_BIF_LS | | |
1422 | AMD_CG_SUPPORT_HDP_MGCG | | |
1423 | AMD_CG_SUPPORT_HDP_LS | | |
1424 | AMD_CG_SUPPORT_DRM_MGCG | | |
1425 | AMD_CG_SUPPORT_DRM_LS | | |
520cbe0f HR |
1426 | AMD_CG_SUPPORT_MC_MGCG | |
1427 | AMD_CG_SUPPORT_MC_LS | | |
1428 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1429 | AMD_CG_SUPPORT_SDMA_LS | | |
1430 | AMD_CG_SUPPORT_VCN_MGCG; | |
61c8e90d | 1431 | |
d5159591 | 1432 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; |
741deade | 1433 | } |
ad5a67a7 | 1434 | break; |
0e54df05 | 1435 | case CHIP_ARCTURUS: |
7f40581c | 1436 | adev->asic_funcs = &vega20_asic_funcs; |
6b76ce62 LM |
1437 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1438 | AMD_CG_SUPPORT_GFX_MGLS | | |
1439 | AMD_CG_SUPPORT_GFX_CGCG | | |
5d111f5b | 1440 | AMD_CG_SUPPORT_GFX_CGLS | |
f9da7c43 | 1441 | AMD_CG_SUPPORT_GFX_CP_LS | |
5d111f5b | 1442 | AMD_CG_SUPPORT_HDP_MGCG | |
f7ee1995 LM |
1443 | AMD_CG_SUPPORT_HDP_LS | |
1444 | AMD_CG_SUPPORT_SDMA_MGCG | | |
a840159c LM |
1445 | AMD_CG_SUPPORT_SDMA_LS | |
1446 | AMD_CG_SUPPORT_MC_MGCG | | |
227f7d58 | 1447 | AMD_CG_SUPPORT_MC_LS | |
e89e2237 LL |
1448 | AMD_CG_SUPPORT_IH_CG | |
1449 | AMD_CG_SUPPORT_VCN_MGCG | | |
1450 | AMD_CG_SUPPORT_JPEG_MGCG; | |
e520859c | 1451 | adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; |
d57c3d56 | 1452 | adev->external_rev_id = adev->rev_id + 0x32; |
0e54df05 | 1453 | break; |
080deab6 | 1454 | case CHIP_RENOIR: |
e09ce481 | 1455 | adev->asic_funcs = &soc15_asic_funcs; |
278cdb68 | 1456 | if ((adev->pdev->device == 0x1636) || |
1457 | (adev->pdev->device == 0x164c)) | |
5baf4150 PL |
1458 | adev->apu_flags |= AMD_APU_IS_RENOIR; |
1459 | else | |
1460 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1461 | ||
1462 | if (adev->apu_flags & AMD_APU_IS_RENOIR) | |
1463 | adev->external_rev_id = adev->rev_id + 0x91; | |
1464 | else | |
1465 | adev->external_rev_id = adev->rev_id + 0xa1; | |
ec3636a5 PL |
1466 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1467 | AMD_CG_SUPPORT_GFX_MGLS | | |
1468 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1469 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1470 | AMD_CG_SUPPORT_GFX_CGCG | | |
1471 | AMD_CG_SUPPORT_GFX_CGLS | | |
a2d15255 PL |
1472 | AMD_CG_SUPPORT_GFX_CP_LS | |
1473 | AMD_CG_SUPPORT_MC_MGCG | | |
ef0e7d08 PL |
1474 | AMD_CG_SUPPORT_MC_LS | |
1475 | AMD_CG_SUPPORT_SDMA_MGCG | | |
d98930f5 | 1476 | AMD_CG_SUPPORT_SDMA_LS | |
9deac0a4 | 1477 | AMD_CG_SUPPORT_BIF_LS | |
de273070 | 1478 | AMD_CG_SUPPORT_HDP_LS | |
91ec8bbb | 1479 | AMD_CG_SUPPORT_VCN_MGCG | |
099d66e4 | 1480 | AMD_CG_SUPPORT_JPEG_MGCG | |
e2ef3b70 PL |
1481 | AMD_CG_SUPPORT_IH_CG | |
1482 | AMD_CG_SUPPORT_ATHUB_LS | | |
8db63b7c PL |
1483 | AMD_CG_SUPPORT_ATHUB_MGCG | |
1484 | AMD_CG_SUPPORT_DF_MGCG; | |
85400984 TT |
1485 | adev->pg_flags = AMD_PG_SUPPORT_SDMA | |
1486 | AMD_PG_SUPPORT_VCN | | |
099d66e4 | 1487 | AMD_PG_SUPPORT_JPEG | |
85400984 | 1488 | AMD_PG_SUPPORT_VCN_DPG; |
080deab6 | 1489 | break; |
7906af5e LM |
1490 | case CHIP_ALDEBARAN: |
1491 | adev->asic_funcs = &vega20_asic_funcs; | |
48a6379a LL |
1492 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1493 | AMD_CG_SUPPORT_GFX_MGLS | | |
1494 | AMD_CG_SUPPORT_GFX_CGCG | | |
1495 | AMD_CG_SUPPORT_GFX_CGLS | | |
1496 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1497 | AMD_CG_SUPPORT_HDP_LS | | |
1498 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1499 | AMD_CG_SUPPORT_SDMA_LS | | |
50ca2522 LL |
1500 | AMD_CG_SUPPORT_IH_CG | |
1501 | AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; | |
bd937973 | 1502 | adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; |
4f668d3d | 1503 | adev->external_rev_id = adev->rev_id + 0x3c; |
7906af5e | 1504 | break; |
220ab9bd KW |
1505 | default: |
1506 | /* FIXME: not supported yet */ | |
1507 | return -EINVAL; | |
1508 | } | |
1509 | ||
ab276632 XY |
1510 | if (amdgpu_sriov_vf(adev)) { |
1511 | amdgpu_virt_init_setting(adev); | |
1512 | xgpu_ai_mailbox_set_irq_funcs(adev); | |
1513 | } | |
1514 | ||
220ab9bd KW |
1515 | return 0; |
1516 | } | |
1517 | ||
81758c55 ML |
1518 | static int soc15_common_late_init(void *handle) |
1519 | { | |
1520 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
22e1d14f | 1521 | int r = 0; |
81758c55 ML |
1522 | |
1523 | if (amdgpu_sriov_vf(adev)) | |
1524 | xgpu_ai_mailbox_get_irq(adev); | |
1525 | ||
6e36f231 HZ |
1526 | if (adev->nbio.ras_funcs && |
1527 | adev->nbio.ras_funcs->ras_late_init) | |
1528 | r = adev->nbio.ras_funcs->ras_late_init(adev); | |
22e1d14f HZ |
1529 | |
1530 | return r; | |
81758c55 ML |
1531 | } |
1532 | ||
220ab9bd KW |
1533 | static int soc15_common_sw_init(void *handle) |
1534 | { | |
81758c55 ML |
1535 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1536 | ||
1537 | if (amdgpu_sriov_vf(adev)) | |
1538 | xgpu_ai_mailbox_add_irq_id(adev); | |
1539 | ||
bdf84a80 | 1540 | adev->df.funcs->sw_init(adev); |
e4cf4bf5 | 1541 | |
220ab9bd KW |
1542 | return 0; |
1543 | } | |
1544 | ||
1545 | static int soc15_common_sw_fini(void *handle) | |
1546 | { | |
f1d59e00 JZ |
1547 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1548 | ||
6e36f231 HZ |
1549 | if (adev->nbio.ras_funcs && |
1550 | adev->nbio.ras_funcs->ras_fini) | |
1551 | adev->nbio.ras_funcs->ras_fini(adev); | |
bdf84a80 | 1552 | adev->df.funcs->sw_fini(adev); |
220ab9bd KW |
1553 | return 0; |
1554 | } | |
1555 | ||
7c94bc82 OZ |
1556 | static void soc15_doorbell_range_init(struct amdgpu_device *adev) |
1557 | { | |
1558 | int i; | |
1559 | struct amdgpu_ring *ring; | |
1560 | ||
4cd4c5c0 ML |
1561 | /* sdma/ih doorbell range are programed by hypervisor */ |
1562 | if (!amdgpu_sriov_vf(adev)) { | |
98cad2de TH |
1563 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1564 | ring = &adev->sdma.instance[i].ring; | |
bebc0762 | 1565 | adev->nbio.funcs->sdma_doorbell_range(adev, i, |
98cad2de TH |
1566 | ring->use_doorbell, ring->doorbell_index, |
1567 | adev->doorbell_index.sdma_doorbell_range); | |
1568 | } | |
7c94bc82 | 1569 | |
bebc0762 | 1570 | adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, |
7c94bc82 | 1571 | adev->irq.ih.doorbell_index); |
4cd4c5c0 | 1572 | } |
7c94bc82 OZ |
1573 | } |
1574 | ||
220ab9bd KW |
1575 | static int soc15_common_hw_init(void *handle) |
1576 | { | |
1577 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1578 | ||
220ab9bd KW |
1579 | /* enable pcie gen2/3 link */ |
1580 | soc15_pcie_gen3_enable(adev); | |
1581 | /* enable aspm */ | |
1582 | soc15_program_aspm(adev); | |
833fa075 | 1583 | /* setup nbio registers */ |
bebc0762 | 1584 | adev->nbio.funcs->init_registers(adev); |
88807dc8 OZ |
1585 | /* remap HDP registers to a hole in mmio space, |
1586 | * for the purpose of expose those registers | |
1587 | * to process space | |
1588 | */ | |
bebc0762 HZ |
1589 | if (adev->nbio.funcs->remap_hdp_registers) |
1590 | adev->nbio.funcs->remap_hdp_registers(adev); | |
e4cf4bf5 | 1591 | |
220ab9bd KW |
1592 | /* enable the doorbell aperture */ |
1593 | soc15_enable_doorbell_aperture(adev, true); | |
7c94bc82 OZ |
1594 | /* HW doorbell routing policy: doorbell writing not |
1595 | * in SDMA/IH/MM/ACV range will be routed to CP. So | |
1596 | * we need to init SDMA/IH/MM/ACV doorbell range prior | |
1597 | * to CP ip block init and ring test. | |
1598 | */ | |
1599 | soc15_doorbell_range_init(adev); | |
220ab9bd KW |
1600 | |
1601 | return 0; | |
1602 | } | |
1603 | ||
1604 | static int soc15_common_hw_fini(void *handle) | |
1605 | { | |
1606 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1607 | ||
1608 | /* disable the doorbell aperture */ | |
1609 | soc15_enable_doorbell_aperture(adev, false); | |
81758c55 ML |
1610 | if (amdgpu_sriov_vf(adev)) |
1611 | xgpu_ai_mailbox_put_irq(adev); | |
220ab9bd | 1612 | |
cde85ac2 PY |
1613 | if (adev->nbio.ras_if && |
1614 | amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { | |
6e36f231 HZ |
1615 | if (adev->nbio.ras_funcs && |
1616 | adev->nbio.ras_funcs->init_ras_controller_interrupt) | |
22e1d14f | 1617 | amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); |
6e36f231 HZ |
1618 | if (adev->nbio.ras_funcs && |
1619 | adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) | |
22e1d14f HZ |
1620 | amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); |
1621 | } | |
1622 | ||
220ab9bd KW |
1623 | return 0; |
1624 | } | |
1625 | ||
1626 | static int soc15_common_suspend(void *handle) | |
1627 | { | |
1628 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1629 | ||
1630 | return soc15_common_hw_fini(adev); | |
1631 | } | |
1632 | ||
1633 | static int soc15_common_resume(void *handle) | |
1634 | { | |
1635 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1636 | ||
1637 | return soc15_common_hw_init(adev); | |
1638 | } | |
1639 | ||
1640 | static bool soc15_common_is_idle(void *handle) | |
1641 | { | |
1642 | return true; | |
1643 | } | |
1644 | ||
1645 | static int soc15_common_wait_for_idle(void *handle) | |
1646 | { | |
1647 | return 0; | |
1648 | } | |
1649 | ||
1650 | static int soc15_common_soft_reset(void *handle) | |
1651 | { | |
1652 | return 0; | |
1653 | } | |
1654 | ||
220ab9bd KW |
1655 | static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) |
1656 | { | |
1657 | uint32_t def, data; | |
1658 | ||
1659 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); | |
1660 | ||
1661 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) | |
1662 | data &= ~(0x01000000 | | |
1663 | 0x02000000 | | |
1664 | 0x04000000 | | |
1665 | 0x08000000 | | |
1666 | 0x10000000 | | |
1667 | 0x20000000 | | |
1668 | 0x40000000 | | |
1669 | 0x80000000); | |
1670 | else | |
1671 | data |= (0x01000000 | | |
1672 | 0x02000000 | | |
1673 | 0x04000000 | | |
1674 | 0x08000000 | | |
1675 | 0x10000000 | | |
1676 | 0x20000000 | | |
1677 | 0x40000000 | | |
1678 | 0x80000000); | |
1679 | ||
1680 | if (def != data) | |
1681 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); | |
1682 | } | |
1683 | ||
1684 | static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) | |
1685 | { | |
1686 | uint32_t def, data; | |
1687 | ||
1688 | def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); | |
1689 | ||
1690 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) | |
1691 | data |= 1; | |
1692 | else | |
1693 | data &= ~1; | |
1694 | ||
1695 | if (def != data) | |
1696 | WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); | |
1697 | } | |
1698 | ||
220ab9bd KW |
1699 | static int soc15_common_set_clockgating_state(void *handle, |
1700 | enum amd_clockgating_state state) | |
1701 | { | |
1702 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1703 | ||
6e9dc861 ML |
1704 | if (amdgpu_sriov_vf(adev)) |
1705 | return 0; | |
1706 | ||
220ab9bd KW |
1707 | switch (adev->asic_type) { |
1708 | case CHIP_VEGA10: | |
692069a1 | 1709 | case CHIP_VEGA12: |
f980d127 | 1710 | case CHIP_VEGA20: |
bebc0762 | 1711 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
a9d4fe2f | 1712 | state == AMD_CG_STATE_GATE); |
bebc0762 | 1713 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
a9d4fe2f | 1714 | state == AMD_CG_STATE_GATE); |
455d40c9 | 1715 | adev->hdp.funcs->update_clock_gating(adev, |
a9d4fe2f | 1716 | state == AMD_CG_STATE_GATE); |
220ab9bd | 1717 | soc15_update_drm_clock_gating(adev, |
a9d4fe2f | 1718 | state == AMD_CG_STATE_GATE); |
220ab9bd | 1719 | soc15_update_drm_light_sleep(adev, |
a9d4fe2f | 1720 | state == AMD_CG_STATE_GATE); |
0e961589 | 1721 | adev->smuio.funcs->update_rom_clock_gating(adev, |
a9d4fe2f | 1722 | state == AMD_CG_STATE_GATE); |
bdf84a80 | 1723 | adev->df.funcs->update_medium_grain_clock_gating(adev, |
a9d4fe2f | 1724 | state == AMD_CG_STATE_GATE); |
220ab9bd | 1725 | break; |
9e5a9eb4 | 1726 | case CHIP_RAVEN: |
f78e007f | 1727 | case CHIP_RENOIR: |
bebc0762 | 1728 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
a9d4fe2f | 1729 | state == AMD_CG_STATE_GATE); |
bebc0762 | 1730 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
a9d4fe2f | 1731 | state == AMD_CG_STATE_GATE); |
455d40c9 | 1732 | adev->hdp.funcs->update_clock_gating(adev, |
a9d4fe2f | 1733 | state == AMD_CG_STATE_GATE); |
9e5a9eb4 | 1734 | soc15_update_drm_clock_gating(adev, |
a9d4fe2f | 1735 | state == AMD_CG_STATE_GATE); |
9e5a9eb4 | 1736 | soc15_update_drm_light_sleep(adev, |
a9d4fe2f | 1737 | state == AMD_CG_STATE_GATE); |
9e5a9eb4 | 1738 | break; |
6acb87ac | 1739 | case CHIP_ARCTURUS: |
48a6379a | 1740 | case CHIP_ALDEBARAN: |
455d40c9 | 1741 | adev->hdp.funcs->update_clock_gating(adev, |
a9d4fe2f | 1742 | state == AMD_CG_STATE_GATE); |
6acb87ac | 1743 | break; |
220ab9bd KW |
1744 | default: |
1745 | break; | |
1746 | } | |
1747 | return 0; | |
1748 | } | |
1749 | ||
f9abe35c HR |
1750 | static void soc15_common_get_clockgating_state(void *handle, u32 *flags) |
1751 | { | |
1752 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1753 | int data; | |
1754 | ||
1755 | if (amdgpu_sriov_vf(adev)) | |
1756 | *flags = 0; | |
1757 | ||
bebc0762 | 1758 | adev->nbio.funcs->get_clockgating_state(adev, flags); |
f9abe35c | 1759 | |
455d40c9 | 1760 | adev->hdp.funcs->get_clock_gating_state(adev, flags); |
f9abe35c | 1761 | |
48a6379a | 1762 | if (adev->asic_type != CHIP_ALDEBARAN) { |
f9abe35c | 1763 | |
48a6379a LL |
1764 | /* AMD_CG_SUPPORT_DRM_MGCG */ |
1765 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); | |
1766 | if (!(data & 0x01000000)) | |
1767 | *flags |= AMD_CG_SUPPORT_DRM_MGCG; | |
1768 | ||
1769 | /* AMD_CG_SUPPORT_DRM_LS */ | |
1770 | data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); | |
1771 | if (data & 0x1) | |
1772 | *flags |= AMD_CG_SUPPORT_DRM_LS; | |
1773 | } | |
f9abe35c HR |
1774 | |
1775 | /* AMD_CG_SUPPORT_ROM_MGCG */ | |
0e961589 | 1776 | adev->smuio.funcs->get_clock_gating_state(adev, flags); |
f9abe35c | 1777 | |
bdf84a80 | 1778 | adev->df.funcs->get_clockgating_state(adev, flags); |
f9abe35c HR |
1779 | } |
1780 | ||
220ab9bd KW |
1781 | static int soc15_common_set_powergating_state(void *handle, |
1782 | enum amd_powergating_state state) | |
1783 | { | |
1784 | /* todo */ | |
1785 | return 0; | |
1786 | } | |
1787 | ||
1788 | const struct amd_ip_funcs soc15_common_ip_funcs = { | |
1789 | .name = "soc15_common", | |
1790 | .early_init = soc15_common_early_init, | |
81758c55 | 1791 | .late_init = soc15_common_late_init, |
220ab9bd KW |
1792 | .sw_init = soc15_common_sw_init, |
1793 | .sw_fini = soc15_common_sw_fini, | |
1794 | .hw_init = soc15_common_hw_init, | |
1795 | .hw_fini = soc15_common_hw_fini, | |
1796 | .suspend = soc15_common_suspend, | |
1797 | .resume = soc15_common_resume, | |
1798 | .is_idle = soc15_common_is_idle, | |
1799 | .wait_for_idle = soc15_common_wait_for_idle, | |
1800 | .soft_reset = soc15_common_soft_reset, | |
1801 | .set_clockgating_state = soc15_common_set_clockgating_state, | |
1802 | .set_powergating_state = soc15_common_set_powergating_state, | |
f9abe35c | 1803 | .get_clockgating_state= soc15_common_get_clockgating_state, |
220ab9bd | 1804 | }; |