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drm/amdgpu/vcn2.5: fix PSP FW loading for the second instance
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
47b757fb
SR		 26#include <linux/pci.h>
27
220ab9bd 28#include "amdgpu.h"
d05da0e2 29#include "amdgpu_atombios.h"
220ab9bd
KW		 30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "atom.h"
36#include "amd_pcie.h"
37
5d735f83 38#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 39#include "gc/gc_9_0_offset.h"
40#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 41#include "sdma0/sdma0_4_0_offset.h"
42#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 43#include "hdp/hdp_4_0_offset.h"
44#include "hdp/hdp_4_0_sh_mask.h"
424d9bb4
FX		 45#include "smuio/smuio_9_0_offset.h"
46#include "smuio/smuio_9_0_sh_mask.h"
b45e18ac 47#include "nbio/nbio_7_0_default.h"
88807dc8 48#include "nbio/nbio_7_0_offset.h"
b45e18ac
KR		 49#include "nbio/nbio_7_0_sh_mask.h"
50#include "nbio/nbio_7_0_smn.h"
9281f12c 51#include "mp/mp_9_0_offset.h"
220ab9bd
KW		 52
53#include "soc15.h"
54#include "soc15_common.h"
55#include "gfx_v9_0.h"
56#include "gmc_v9_0.h"
57#include "gfxhub_v1_0.h"
58#include "mmhub_v1_0.h"
070706c0 59#include "df_v1_7.h"
698758bb 60#include "df_v3_6.h"
bebc0762
HZ		 61#include "nbio_v6_1.h"
62#include "nbio_v7_0.h"
63#include "nbio_v7_4.h"
220ab9bd
KW		 64#include "vega10_ih.h"
65#include "sdma_v4_0.h"
66#include "uvd_v7_0.h"
67#include "vce_v4_0.h"
f2d7e707 68#include "vcn_v1_0.h"
279ba48e 69#include "vcn_v2_0.h"
5be45a26 70#include "jpeg_v2_0.h"
08249a3a 71#include "vcn_v2_5.h"
8c74e590 72#include "jpeg_v2_5.h"
796b6568 73#include "dce_virtual.h"
f1a34465 74#include "mxgpu_ai.h"
2da5410b 75#include "amdgpu_smu.h"
e74609cb
AD		 76#include "amdgpu_ras.h"
77#include "amdgpu_xgmi.h"
88807dc8 78#include <uapi/linux/kfd_ioctl.h>
220ab9bd 79
220ab9bd
KW		 80#define mmMP0_MISC_CGTT_CTRL0 0x01b9
81#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
84
a5d0f456
KF		 85/* for Vega20 register name change */
86#define mmHDP_MEM_POWER_CTRL 0x00d4
87#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
220ab9bd
KW		 92/*
93 * Indirect registers accessor
94 */
95static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
96{
97 unsigned long flags, address, data;
98 u32 r;
bebc0762
HZ		 99 address = adev->nbio.funcs->get_pcie_index_offset(adev);
100 data = adev->nbio.funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 101
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
103 WREG32(address, reg);
104 (void)RREG32(address);
105 r = RREG32(data);
106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
107 return r;
108}
109
110static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
111{
112 unsigned long flags, address, data;
220ab9bd 113
bebc0762
HZ		 114 address = adev->nbio.funcs->get_pcie_index_offset(adev);
115 data = adev->nbio.funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 116
117 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
118 WREG32(address, reg);
119 (void)RREG32(address);
120 WREG32(data, v);
121 (void)RREG32(data);
122 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
123}
124
4fa1c6a6
TZ		 125static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
126{
127 unsigned long flags, address, data;
128 u64 r;
bebc0762
HZ		 129 address = adev->nbio.funcs->get_pcie_index_offset(adev);
130 data = adev->nbio.funcs->get_pcie_data_offset(adev);
4fa1c6a6
TZ		 131
132 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
133 /* read low 32 bit */
134 WREG32(address, reg);
135 (void)RREG32(address);
136 r = RREG32(data);
137
138 /* read high 32 bit*/
139 WREG32(address, reg + 4);
140 (void)RREG32(address);
141 r |= ((u64)RREG32(data) << 32);
142 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
143 return r;
144}
145
146static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
147{
148 unsigned long flags, address, data;
149
bebc0762
HZ		 150 address = adev->nbio.funcs->get_pcie_index_offset(adev);
151 data = adev->nbio.funcs->get_pcie_data_offset(adev);
4fa1c6a6
TZ		 152
153 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
154 /* write low 32 bit */
155 WREG32(address, reg);
156 (void)RREG32(address);
157 WREG32(data, (u32)(v & 0xffffffffULL));
158 (void)RREG32(data);
159
160 /* write high 32 bit */
161 WREG32(address, reg + 4);
162 (void)RREG32(address);
163 WREG32(data, (u32)(v >> 32));
164 (void)RREG32(data);
165 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
166}
167
220ab9bd
KW		 168static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
169{
170 unsigned long flags, address, data;
171 u32 r;
172
173 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
174 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
175
176 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
177 WREG32(address, ((reg) & 0x1ff));
178 r = RREG32(data);
179 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
180 return r;
181}
182
183static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
184{
185 unsigned long flags, address, data;
186
187 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
188 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
189
190 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
191 WREG32(address, ((reg) & 0x1ff));
192 WREG32(data, (v));
193 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
194}
195
196static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
197{
198 unsigned long flags, address, data;
199 u32 r;
200
201 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
202 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
203
204 spin_lock_irqsave(&adev->didt_idx_lock, flags);
205 WREG32(address, (reg));
206 r = RREG32(data);
207 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
208 return r;
209}
210
211static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
212{
213 unsigned long flags, address, data;
214
215 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
216 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
217
218 spin_lock_irqsave(&adev->didt_idx_lock, flags);
219 WREG32(address, (reg));
220 WREG32(data, (v));
221 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
222}
223
560460f2
EQ		 224static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
225{
226 unsigned long flags;
227 u32 r;
228
229 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
231 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
232 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
233 return r;
234}
235
236static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
237{
238 unsigned long flags;
239
240 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
241 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
242 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
243 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
244}
245
2f11fb02
EQ		 246static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
247{
248 unsigned long flags;
249 u32 r;
250
251 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
252 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
253 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
254 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
255 return r;
256}
257
258static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
259{
260 unsigned long flags;
261
262 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
263 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
264 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
265 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
266}
267
220ab9bd
KW		 268static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
269{
bebc0762 270 return adev->nbio.funcs->get_memsize(adev);
220ab9bd
KW		 271}
272
220ab9bd
KW		 273static u32 soc15_get_xclk(struct amdgpu_device *adev)
274{
76d6172b 275 return adev->clock.spll.reference_freq;
220ab9bd
KW		 276}
277
278
279void soc15_grbm_select(struct amdgpu_device *adev,
280 u32 me, u32 pipe, u32 queue, u32 vmid)
281{
282 u32 grbm_gfx_cntl = 0;
283 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
284 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
285 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
286 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
287
1bff7f6c 288 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
220ab9bd
KW		 289}
290
291static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
292{
293 /* todo */
294}
295
296static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
297{
298 /* todo */
299 return false;
300}
301
302static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
303 u8 *bios, u32 length_bytes)
304{
305 u32 *dw_ptr;
306 u32 i, length_dw;
307
308 if (bios == NULL)
309 return false;
310 if (length_bytes == 0)
311 return false;
312 /* APU vbios image is part of sbios image */
313 if (adev->flags & AMD_IS_APU)
314 return false;
315
316 dw_ptr = (u32 *)bios;
317 length_dw = ALIGN(length_bytes, 4) / 4;
318
319 /* set rom index to 0 */
320 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
321 /* read out the rom data */
322 for (i = 0; i < length_dw; i++)
323 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
324
325 return true;
326}
327
946a4d5b
SL		 328static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
329 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
330 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
331 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
332 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
333 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
335 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
336 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
337 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
338 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
339 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
340 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
341 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
342 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
343 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
664fe85a 344 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
946a4d5b
SL		 345 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
347 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
5eeae247 348 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
220ab9bd
KW		 349};
350
351static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
352 u32 sh_num, u32 reg_offset)
353{
354 uint32_t val;
355
356 mutex_lock(&adev->grbm_idx_mutex);
357 if (se_num != 0xffffffff || sh_num != 0xffffffff)
358 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
359
360 val = RREG32(reg_offset);
361
362 if (se_num != 0xffffffff || sh_num != 0xffffffff)
363 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
364 mutex_unlock(&adev->grbm_idx_mutex);
365 return val;
366}
367
c013cea2
AD		 368static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
369 bool indexed, u32 se_num,
370 u32 sh_num, u32 reg_offset)
371{
372 if (indexed) {
373 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
374 } else {
cd29253f 375 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 376 return adev->gfx.config.gb_addr_config;
5eeae247
AD		 377 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
378 return adev->gfx.config.db_debug2;
cd29253f 379 return RREG32(reg_offset);
c013cea2
AD		 380 }
381}
382
220ab9bd
KW		 383static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
384 u32 sh_num, u32 reg_offset, u32 *value)
385{
3032f350 386 uint32_t i;
946a4d5b 387 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 388
389 *value = 0;
220ab9bd 390 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 391 en = &soc15_allowed_read_registers[i];
392 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
393 + en->reg_offset))
220ab9bd
KW		 394 continue;
395
97fcc76b
CK		 396 *value = soc15_get_register_value(adev,
397 soc15_allowed_read_registers[i].grbm_indexed,
398 se_num, sh_num, reg_offset);
220ab9bd
KW		 399 return 0;
400 }
401 return -EINVAL;
402}
403
946a4d5b
SL		 404
405/**
406 * soc15_program_register_sequence - program an array of registers.
407 *
408 * @adev: amdgpu_device pointer
409 * @regs: pointer to the register array
410 * @array_size: size of the register array
411 *
412 * Programs an array or registers with and and or masks.
413 * This is a helper for setting golden registers.
414 */
415
416void soc15_program_register_sequence(struct amdgpu_device *adev,
417 const struct soc15_reg_golden *regs,
418 const u32 array_size)
419{
420 const struct soc15_reg_golden *entry;
421 u32 tmp, reg;
422 int i;
423
424 for (i = 0; i < array_size; ++i) {
425 entry = &regs[i];
426 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
427
428 if (entry->and_mask == 0xffffffff) {
429 tmp = entry->or_mask;
430 } else {
431 tmp = RREG32(reg);
432 tmp &= ~(entry->and_mask);
e0d07657 433 tmp |= (entry->or_mask & entry->and_mask);
946a4d5b 434 }
1bff7f6c
TH		 435
436 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
437 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
438 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
439 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
440 WREG32_RLC(reg, tmp);
441 else
442 WREG32(reg, tmp);
443
946a4d5b
SL		 444 }
445
446}
447
e2b6d053 448static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
220ab9bd
KW		 449{
450 u32 i;
39fee32b 451 int ret = 0;
220ab9bd 452
98512bb8
KW		 453 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
454
e2b6d053 455 dev_info(adev->dev, "GPU mode1 reset\n");
220ab9bd
KW		 456
457 /* disable BM */
458 pci_clear_master(adev->pdev);
220ab9bd 459
98512bb8
KW		 460 pci_save_state(adev->pdev);
461
39fee32b
EQ		 462 ret = psp_gpu_reset(adev);
463 if (ret)
464 dev_err(adev->dev, "GPU mode1 reset failed\n");
98512bb8
KW		 465
466 pci_restore_state(adev->pdev);
220ab9bd
KW		 467
468 /* wait for asic to come out of reset */
469 for (i = 0; i < adev->usec_timeout; i++) {
bebc0762 470 u32 memsize = adev->nbio.funcs->get_memsize(adev);
bf383fb6 471
aecbe64f 472 if (memsize != 0xffffffff)
220ab9bd
KW		 473 break;
474 udelay(1);
475 }
476
d05da0e2 477 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd 478
39fee32b 479 return ret;
220ab9bd
KW		 480}
481
e2b6d053
JQ		 482static int soc15_asic_baco_reset(struct amdgpu_device *adev)
483{
956f6705 484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
9530273e 485 int ret = 0;
e2b6d053 486
956f6705
LM		 487 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
488 if (ras && ras->supported)
489 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
490
9530273e
EQ		 491 ret = amdgpu_dpm_baco_reset(adev);
492 if (ret)
493 return ret;
e2b6d053 494
956f6705
LM		 495 /* re-enable doorbell interrupt after BACO exit */
496 if (ras && ras->supported)
497 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
498
e2b6d053
JQ		 499 return 0;
500}
501
ee360c0b
AD		 502static enum amd_reset_method
503soc15_asic_reset_method(struct amdgpu_device *adev)
e2b6d053 504{
feffbaac
LM		 505 bool baco_reset = false;
506 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
e2b6d053
JQ		 507
508 switch (adev->asic_type) {
ee360c0b 509 case CHIP_RAVEN:
90a08351 510 case CHIP_RENOIR:
ee360c0b 511 return AMD_RESET_METHOD_MODE2;
e2b6d053 512 case CHIP_VEGA10:
f8b18cf4 513 case CHIP_VEGA12:
0a650c1d 514 case CHIP_ARCTURUS:
9530273e 515 baco_reset = amdgpu_dpm_is_baco_supported(adev);
e2b6d053 516 break;
017d75f1
EQ		 517 case CHIP_VEGA20:
518 if (adev->psp.sos_fw_version >= 0x80067)
9530273e 519 baco_reset = amdgpu_dpm_is_baco_supported(adev);
e74609cb 520
feffbaac
LM		 521 /*
522 * 1. PMFW version > 0x284300: all cases use baco
523 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
524 */
525 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
526 baco_reset = false;
017d75f1 527 break;
e2b6d053 528 default:
e2b6d053
JQ		 529 break;
530 }
531
532 if (baco_reset)
ee360c0b
AD		 533 return AMD_RESET_METHOD_BACO;
534 else
535 return AMD_RESET_METHOD_MODE1;
536}
537
538static int soc15_asic_reset(struct amdgpu_device *adev)
539{
c43b849f
AG		 540 switch (soc15_asic_reset_method(adev)) {
541 case AMD_RESET_METHOD_BACO:
2c9a0c66
AD		 542 if (!adev->in_suspend)
543 amdgpu_inc_vram_lost(adev);
c43b849f
AG		 544 return soc15_asic_baco_reset(adev);
545 case AMD_RESET_METHOD_MODE2:
9530273e 546 return amdgpu_dpm_mode2_reset(adev);
c43b849f 547 default:
2c9a0c66
AD		 548 if (!adev->in_suspend)
549 amdgpu_inc_vram_lost(adev);
c43b849f
AG		 550 return soc15_asic_mode1_reset(adev);
551 }
e2b6d053
JQ		 552}
553
988eb9ff
AD		 554static bool soc15_supports_baco(struct amdgpu_device *adev)
555{
988eb9ff
AD		 556 switch (adev->asic_type) {
557 case CHIP_VEGA10:
558 case CHIP_VEGA12:
b8ab58f3 559 case CHIP_ARCTURUS:
9530273e 560 return amdgpu_dpm_is_baco_supported(adev);
988eb9ff
AD		 561 case CHIP_VEGA20:
562 if (adev->psp.sos_fw_version >= 0x80067)
9530273e
EQ		 563 return amdgpu_dpm_is_baco_supported(adev);
564 return false;
988eb9ff
AD		 565 default:
566 return false;
567 }
988eb9ff
AD		 568}
569
220ab9bd
KW		 570/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
571 u32 cntl_reg, u32 status_reg)
572{
573 return 0;
574}*/
575
576static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
577{
578 /*int r;
579
580 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
581 if (r)
582 return r;
583
584 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
585 */
586 return 0;
587}
588
589static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
590{
591 /* todo */
592
593 return 0;
594}
595
596static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
597{
598 if (pci_is_root_bus(adev->pdev->bus))
599 return;
600
601 if (amdgpu_pcie_gen2 == 0)
602 return;
603
604 if (adev->flags & AMD_IS_APU)
605 return;
606
607 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
608 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
609 return;
610
611 /* todo */
612}
613
614static void soc15_program_aspm(struct amdgpu_device *adev)
615{
616
617 if (amdgpu_aspm == 0)
618 return;
619
620 /* todo */
621}
622
623static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 624 bool enable)
220ab9bd 625{
bebc0762
HZ		 626 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
627 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 628}
629
630static const struct amdgpu_ip_block_version vega10_common_ip_block =
631{
632 .type = AMD_IP_BLOCK_TYPE_COMMON,
633 .major = 2,
634 .minor = 0,
635 .rev = 0,
636 .funcs = &soc15_common_ip_funcs,
637};
638
4cb0becb
HR		 639static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
640{
bebc0762 641 return adev->nbio.funcs->get_rev_id(adev);
4cb0becb
HR		 642}
643
220ab9bd
KW		 644int soc15_set_ip_blocks(struct amdgpu_device *adev)
645{
4522824c
SL		 646 /* Set IP register base before any HW register access */
647 switch (adev->asic_type) {
648 case CHIP_VEGA10:
3084eb00 649 case CHIP_VEGA12:
4522824c 650 case CHIP_RAVEN:
080deab6 651 case CHIP_RENOIR:
4522824c
SL		 652 vega10_reg_base_init(adev);
653 break;
8ee273e5
FX		 654 case CHIP_VEGA20:
655 vega20_reg_base_init(adev);
656 break;
e78705ec
LM		 657 case CHIP_ARCTURUS:
658 arct_reg_base_init(adev);
659 break;
4522824c
SL		 660 default:
661 return -EINVAL;
662 }
663
eb39aff7 664 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
47622ba0
AD		 665 adev->gmc.xgmi.supported = true;
666
bebc0762
HZ		 667 if (adev->flags & AMD_IS_APU) {
668 adev->nbio.funcs = &nbio_v7_0_funcs;
669 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
670 } else if (adev->asic_type == CHIP_VEGA20 ||
671 adev->asic_type == CHIP_ARCTURUS) {
672 adev->nbio.funcs = &nbio_v7_4_funcs;
673 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
674 } else {
675 adev->nbio.funcs = &nbio_v6_1_funcs;
676 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
677 }
bf383fb6 678
0e54df05 679 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
698758bb
FX		 680 adev->df_funcs = &df_v3_6_funcs;
681 else
682 adev->df_funcs = &df_v1_7_funcs;
4cb0becb
HR		 683
684 adev->rev_id = soc15_get_rev_id(adev);
bebc0762 685 adev->nbio.funcs->detect_hw_virt(adev);
1b922423 686
f1a34465
XY		 687 if (amdgpu_sriov_vf(adev))
688 adev->virt.ops = &xgpu_ai_virt_ops;
689
220ab9bd
KW		 690 switch (adev->asic_type) {
691 case CHIP_VEGA10:
692069a1 692 case CHIP_VEGA12:
7c7af6c1 693 case CHIP_VEGA20:
2990a1fc
AD		 694 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
695 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2d11fd3f
TH		 696
697 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
698 if (amdgpu_sriov_vf(adev)) {
699 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
700 if (adev->asic_type == CHIP_VEGA20)
701 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
702 else
703 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
704 }
705 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
706 } else {
707 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
708 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
709 if (adev->asic_type == CHIP_VEGA20)
710 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
711 else
712 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
713 }
3680b2a5 714 }
009d9ed6
RZ		 715 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
716 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
c9ffa427
YT		 717 if (is_support_sw_smu(adev)) {
718 if (!amdgpu_sriov_vf(adev))
2da5410b 719 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
c9ffa427
YT		 720 } else {
721 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2da5410b 722 }
f8445307 723 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 724 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 725#if defined(CONFIG_DRM_AMD_DC)
726 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 727 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a 728#endif
846311ae
FM		 729 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
730 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
731 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
732 }
220ab9bd 733 break;
1023b797 734 case CHIP_RAVEN:
40c2358b
HR		 735 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
736 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2990a1fc 737 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
3680b2a5
EQ		 738 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
739 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
009d9ed6
RZ		 740 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
741 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b905090d 742 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 743 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 744 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 745#if defined(CONFIG_DRM_AMD_DC)
746 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 747 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1 748#endif
2990a1fc 749 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 750 break;
0e54df05
LM		 751 case CHIP_ARCTURUS:
752 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
753 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
21889cec
JZ		 754
755 if (amdgpu_sriov_vf(adev)) {
756 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
757 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
758 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
759 } else {
760 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
761 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
762 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
763 }
764
0e54df05
LM		 765 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
766 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
767 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
768 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
c2a801af 769 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
21889cec 770
ab5999de
JJ		 771 if (amdgpu_sriov_vf(adev)) {
772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
773 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
774 } else {
775 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
776 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
777 }
e416fdb6
JZ		 778 if (!amdgpu_sriov_vf(adev))
779 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
0e54df05 780 break;
05e1f0e0
HR		 781 case CHIP_RENOIR:
782 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
783 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
784 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
6a7a0bdb
AL		 785 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
786 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
9530273e 787 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
97222cfa
AL		 788 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
789 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b1326bbc
AL		 790 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
791 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
e1c14c43
RL		 792#if defined(CONFIG_DRM_AMD_DC)
793 else if (amdgpu_device_has_dc_support(adev))
794 amdgpu_device_ip_block_add(adev, &dm_ip_block);
e1c14c43 795#endif
279ba48e 796 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
5be45a26 797 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
05e1f0e0 798 break;
220ab9bd
KW		 799 default:
800 return -EINVAL;
801 }
802
803 return 0;
804}
805
69882565 806static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 807{
bebc0762 808 adev->nbio.funcs->hdp_flush(adev, ring);
73c73240
AD		 809}
810
69882565
CK		 811static void soc15_invalidate_hdp(struct amdgpu_device *adev,
812 struct amdgpu_ring *ring)
73c73240 813{
69882565 814 if (!ring || !ring->funcs->emit_wreg)
5fb7c665 815 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
69882565
CK		 816 else
817 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
818 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 819}
820
adbd4f89
AD		 821static bool soc15_need_full_reset(struct amdgpu_device *adev)
822{
823 /* change this when we implement soft reset */
824 return true;
825}
b45e18ac
KR		 826static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
827 uint64_t *count1)
828{
829 uint32_t perfctr = 0;
830 uint64_t cnt0_of, cnt1_of;
831 int tmp;
832
833 /* This reports 0 on APUs, so return to avoid writing/reading registers
834 * that may or may not be different from their GPU counterparts
835 */
0172591e
ES		 836 if (adev->flags & AMD_IS_APU)
837 return;
b45e18ac
KR		 838
839 /* Set the 2 events that we wish to watch, defined above */
9417f703 840 /* Reg 40 is # received msgs */
612e4ed9 841 /* Reg 104 is # of posted requests sent */
b45e18ac 842 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
612e4ed9 843 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
b45e18ac
KR		 844
845 /* Write to enable desired perf counters */
846 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
847 /* Zero out and enable the perf counters
848 * Write 0x5:
849 * Bit 0 = Start all counters(1)
850 * Bit 2 = Global counter reset enable(1)
851 */
852 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
853
854 msleep(1000);
855
856 /* Load the shadow and disable the perf counters
857 * Write 0x2:
858 * Bit 0 = Stop counters(0)
859 * Bit 1 = Load the shadow counters(1)
860 */
861 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
862
863 /* Read register values to get any >32bit overflow */
864 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
865 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
866 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
867
868 /* Get the values and add the overflow */
869 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
870 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
871}
adbd4f89 872
612e4ed9
KR		 873static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
874 uint64_t *count1)
875{
876 uint32_t perfctr = 0;
877 uint64_t cnt0_of, cnt1_of;
878 int tmp;
879
880 /* This reports 0 on APUs, so return to avoid writing/reading registers
881 * that may or may not be different from their GPU counterparts
882 */
883 if (adev->flags & AMD_IS_APU)
884 return;
885
886 /* Set the 2 events that we wish to watch, defined above */
887 /* Reg 40 is # received msgs */
888 /* Reg 108 is # of posted requests sent on VG20 */
889 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
890 EVENT0_SEL, 40);
891 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
892 EVENT1_SEL, 108);
893
894 /* Write to enable desired perf counters */
895 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
896 /* Zero out and enable the perf counters
897 * Write 0x5:
898 * Bit 0 = Start all counters(1)
899 * Bit 2 = Global counter reset enable(1)
900 */
901 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
902
903 msleep(1000);
904
905 /* Load the shadow and disable the perf counters
906 * Write 0x2:
907 * Bit 0 = Stop counters(0)
908 * Bit 1 = Load the shadow counters(1)
909 */
910 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
911
912 /* Read register values to get any >32bit overflow */
913 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
914 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
915 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
916
917 /* Get the values and add the overflow */
918 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
919 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
920}
921
9281f12c
AD		 922static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
923{
924 u32 sol_reg;
925
d55f33da
AD		 926 /* Just return false for soc15 GPUs. Reset does not seem to
927 * be necessary.
928 */
394e9a14
ED		 929 if (!amdgpu_passthrough(adev))
930 return false;
d55f33da 931
9281f12c
AD		 932 if (adev->flags & AMD_IS_APU)
933 return false;
934
935 /* Check sOS sign of life register to confirm sys driver and sOS
936 * are already been loaded.
937 */
938 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
939 if (sol_reg)
940 return true;
941
942 return false;
943}
944
dcea6e65
KR		 945static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
946{
947 uint64_t nak_r, nak_g;
948
949 /* Get the number of NAKs received and generated */
950 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
951 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
952
953 /* Add the total number of NAKs, i.e the number of replays */
954 return (nak_r + nak_g);
955}
956
220ab9bd
KW		 957static const struct amdgpu_asic_funcs soc15_asic_funcs =
958{
959 .read_disabled_bios = &soc15_read_disabled_bios,
960 .read_bios_from_rom = &soc15_read_bios_from_rom,
961 .read_register = &soc15_read_register,
962 .reset = &soc15_asic_reset,
ee360c0b 963 .reset_method = &soc15_asic_reset_method,
220ab9bd
KW		 964 .set_vga_state = &soc15_vga_set_state,
965 .get_xclk = &soc15_get_xclk,
966 .set_uvd_clocks = &soc15_set_uvd_clocks,
967 .set_vce_clocks = &soc15_set_vce_clocks,
968 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 969 .flush_hdp = &soc15_flush_hdp,
970 .invalidate_hdp = &soc15_invalidate_hdp,
adbd4f89 971 .need_full_reset = &soc15_need_full_reset,
062f3807 972 .init_doorbell_index = &vega10_doorbell_index_init,
b45e18ac 973 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 974 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 975 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
988eb9ff 976 .supports_baco = &soc15_supports_baco,
220ab9bd
KW		 977};
978
c93aa775
OZ		 979static const struct amdgpu_asic_funcs vega20_asic_funcs =
980{
981 .read_disabled_bios = &soc15_read_disabled_bios,
982 .read_bios_from_rom = &soc15_read_bios_from_rom,
983 .read_register = &soc15_read_register,
984 .reset = &soc15_asic_reset,
761e0923 985 .reset_method = &soc15_asic_reset_method,
c93aa775
OZ		 986 .set_vga_state = &soc15_vga_set_state,
987 .get_xclk = &soc15_get_xclk,
988 .set_uvd_clocks = &soc15_set_uvd_clocks,
989 .set_vce_clocks = &soc15_set_vce_clocks,
990 .get_config_memsize = &soc15_get_config_memsize,
991 .flush_hdp = &soc15_flush_hdp,
992 .invalidate_hdp = &soc15_invalidate_hdp,
993 .need_full_reset = &soc15_need_full_reset,
994 .init_doorbell_index = &vega20_doorbell_index_init,
612e4ed9 995 .get_pcie_usage = &vega20_get_pcie_usage,
9281f12c 996 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 997 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
988eb9ff 998 .supports_baco = &soc15_supports_baco,
220ab9bd
KW		 999};
1000
1001static int soc15_common_early_init(void *handle)
1002{
88807dc8 1003#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
220ab9bd
KW		 1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1005
88807dc8
OZ		 1006 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1007 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
220ab9bd
KW		 1008 adev->smc_rreg = NULL;
1009 adev->smc_wreg = NULL;
1010 adev->pcie_rreg = &soc15_pcie_rreg;
1011 adev->pcie_wreg = &soc15_pcie_wreg;
4fa1c6a6
TZ		 1012 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1013 adev->pcie_wreg64 = &soc15_pcie_wreg64;
220ab9bd
KW		 1014 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1015 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1016 adev->didt_rreg = &soc15_didt_rreg;
1017 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 1018 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1019 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 1020 adev->se_cac_rreg = &soc15_se_cac_rreg;
1021 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd 1022
220ab9bd 1023
220ab9bd
KW		 1024 adev->external_rev_id = 0xFF;
1025 switch (adev->asic_type) {
1026 case CHIP_VEGA10:
c93aa775 1027 adev->asic_funcs = &soc15_asic_funcs;
220ab9bd
KW		 1028 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1029 AMD_CG_SUPPORT_GFX_MGLS |
1030 AMD_CG_SUPPORT_GFX_RLC_LS |
1031 AMD_CG_SUPPORT_GFX_CP_LS |
1032 AMD_CG_SUPPORT_GFX_3D_CGCG |
1033 AMD_CG_SUPPORT_GFX_3D_CGLS |
1034 AMD_CG_SUPPORT_GFX_CGCG |
1035 AMD_CG_SUPPORT_GFX_CGLS |
1036 AMD_CG_SUPPORT_BIF_MGCG |
1037 AMD_CG_SUPPORT_BIF_LS |
1038 AMD_CG_SUPPORT_HDP_LS |
1039 AMD_CG_SUPPORT_DRM_MGCG |
1040 AMD_CG_SUPPORT_DRM_LS |
1041 AMD_CG_SUPPORT_ROM_MGCG |
1042 AMD_CG_SUPPORT_DF_MGCG |
1043 AMD_CG_SUPPORT_SDMA_MGCG |
1044 AMD_CG_SUPPORT_SDMA_LS |
1045 AMD_CG_SUPPORT_MC_MGCG |
1046 AMD_CG_SUPPORT_MC_LS;
1047 adev->pg_flags = 0;
1048 adev->external_rev_id = 0x1;
1049 break;
692069a1 1050 case CHIP_VEGA12:
c93aa775 1051 adev->asic_funcs = &soc15_asic_funcs;
e4a38755
EQ		 1052 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1053 AMD_CG_SUPPORT_GFX_MGLS |
1054 AMD_CG_SUPPORT_GFX_CGCG |
1055 AMD_CG_SUPPORT_GFX_CGLS |
1056 AMD_CG_SUPPORT_GFX_3D_CGCG |
1057 AMD_CG_SUPPORT_GFX_3D_CGLS |
1058 AMD_CG_SUPPORT_GFX_CP_LS |
1059 AMD_CG_SUPPORT_MC_LS |
1060 AMD_CG_SUPPORT_MC_MGCG |
1061 AMD_CG_SUPPORT_SDMA_MGCG |
1062 AMD_CG_SUPPORT_SDMA_LS |
1063 AMD_CG_SUPPORT_BIF_MGCG |
1064 AMD_CG_SUPPORT_BIF_LS |
1065 AMD_CG_SUPPORT_HDP_MGCG |
1066 AMD_CG_SUPPORT_HDP_LS |
1067 AMD_CG_SUPPORT_ROM_MGCG |
1068 AMD_CG_SUPPORT_VCE_MGCG |
1069 AMD_CG_SUPPORT_UVD_MGCG;
692069a1 1070 adev->pg_flags = 0;
f559fe2b 1071 adev->external_rev_id = adev->rev_id + 0x14;
692069a1 1072 break;
935be7a0 1073 case CHIP_VEGA20:
c93aa775 1074 adev->asic_funcs = &vega20_asic_funcs;
3fdbab5f
EQ		 1075 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1076 AMD_CG_SUPPORT_GFX_MGLS |
1077 AMD_CG_SUPPORT_GFX_CGCG |
1078 AMD_CG_SUPPORT_GFX_CGLS |
1079 AMD_CG_SUPPORT_GFX_3D_CGCG |
1080 AMD_CG_SUPPORT_GFX_3D_CGLS |
1081 AMD_CG_SUPPORT_GFX_CP_LS |
1082 AMD_CG_SUPPORT_MC_LS |
1083 AMD_CG_SUPPORT_MC_MGCG |
1084 AMD_CG_SUPPORT_SDMA_MGCG |
1085 AMD_CG_SUPPORT_SDMA_LS |
1086 AMD_CG_SUPPORT_BIF_MGCG |
1087 AMD_CG_SUPPORT_BIF_LS |
1088 AMD_CG_SUPPORT_HDP_MGCG |
102e4940 1089 AMD_CG_SUPPORT_HDP_LS |
3fdbab5f
EQ		 1090 AMD_CG_SUPPORT_ROM_MGCG |
1091 AMD_CG_SUPPORT_VCE_MGCG |
1092 AMD_CG_SUPPORT_UVD_MGCG;
935be7a0
FX		 1093 adev->pg_flags = 0;
1094 adev->external_rev_id = adev->rev_id + 0x28;
1095 break;
957c6fe1 1096 case CHIP_RAVEN:
c93aa775 1097 adev->asic_funcs = &soc15_asic_funcs;
520cbe0f 1098 if (adev->rev_id >= 0x8)
7e4545d3 1099 adev->external_rev_id = adev->rev_id + 0x79;
741deade
AD		 1100 else if (adev->pdev->device == 0x15d8)
1101 adev->external_rev_id = adev->rev_id + 0x41;
7e4545d3
HR		 1102 else if (adev->rev_id == 1)
1103 adev->external_rev_id = adev->rev_id + 0x20;
741deade 1104 else
7e4545d3 1105 adev->external_rev_id = adev->rev_id + 0x01;
741deade
AD		 1106
1107 if (adev->rev_id >= 0x8) {
520cbe0f
HR		 1108 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1109 AMD_CG_SUPPORT_GFX_MGLS |
1110 AMD_CG_SUPPORT_GFX_CP_LS |
1111 AMD_CG_SUPPORT_GFX_3D_CGCG |
1112 AMD_CG_SUPPORT_GFX_3D_CGLS |
1113 AMD_CG_SUPPORT_GFX_CGCG |
1114 AMD_CG_SUPPORT_GFX_CGLS |
1115 AMD_CG_SUPPORT_BIF_LS |
1116 AMD_CG_SUPPORT_HDP_LS |
1117 AMD_CG_SUPPORT_ROM_MGCG |
1118 AMD_CG_SUPPORT_MC_MGCG |
1119 AMD_CG_SUPPORT_MC_LS |
1120 AMD_CG_SUPPORT_SDMA_MGCG |
1121 AMD_CG_SUPPORT_SDMA_LS |
1122 AMD_CG_SUPPORT_VCN_MGCG;
741deade 1123
d5159591 1124 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
741deade 1125 } else if (adev->pdev->device == 0x15d8) {
fced5c70
LG		 1126 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1127 AMD_CG_SUPPORT_GFX_MGLS |
741deade
AD		 1128 AMD_CG_SUPPORT_GFX_CP_LS |
1129 AMD_CG_SUPPORT_GFX_3D_CGCG |
1130 AMD_CG_SUPPORT_GFX_3D_CGLS |
1131 AMD_CG_SUPPORT_GFX_CGCG |
1132 AMD_CG_SUPPORT_GFX_CGLS |
1133 AMD_CG_SUPPORT_BIF_LS |
1134 AMD_CG_SUPPORT_HDP_LS |
1135 AMD_CG_SUPPORT_ROM_MGCG |
1136 AMD_CG_SUPPORT_MC_MGCG |
1137 AMD_CG_SUPPORT_MC_LS |
1138 AMD_CG_SUPPORT_SDMA_MGCG |
1139 AMD_CG_SUPPORT_SDMA_LS;
1140
1141 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1142 AMD_PG_SUPPORT_MMHUB |
a3716d3a
JZ		 1143 AMD_PG_SUPPORT_VCN |
1144 AMD_PG_SUPPORT_VCN_DPG;
741deade 1145 } else {
520cbe0f
HR		 1146 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1147 AMD_CG_SUPPORT_GFX_MGLS |
1148 AMD_CG_SUPPORT_GFX_RLC_LS |
1149 AMD_CG_SUPPORT_GFX_CP_LS |
1150 AMD_CG_SUPPORT_GFX_3D_CGCG |
1151 AMD_CG_SUPPORT_GFX_3D_CGLS |
1152 AMD_CG_SUPPORT_GFX_CGCG |
1153 AMD_CG_SUPPORT_GFX_CGLS |
1154 AMD_CG_SUPPORT_BIF_MGCG |
1155 AMD_CG_SUPPORT_BIF_LS |
1156 AMD_CG_SUPPORT_HDP_MGCG |
1157 AMD_CG_SUPPORT_HDP_LS |
1158 AMD_CG_SUPPORT_DRM_MGCG |
1159 AMD_CG_SUPPORT_DRM_LS |
1160 AMD_CG_SUPPORT_ROM_MGCG |
1161 AMD_CG_SUPPORT_MC_MGCG |
1162 AMD_CG_SUPPORT_MC_LS |
1163 AMD_CG_SUPPORT_SDMA_MGCG |
1164 AMD_CG_SUPPORT_SDMA_LS |
1165 AMD_CG_SUPPORT_VCN_MGCG;
61c8e90d 1166
d5159591 1167 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
741deade 1168 }
ad5a67a7 1169 break;
0e54df05 1170 case CHIP_ARCTURUS:
7f40581c 1171 adev->asic_funcs = &vega20_asic_funcs;
6b76ce62
LM		 1172 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1173 AMD_CG_SUPPORT_GFX_MGLS |
1174 AMD_CG_SUPPORT_GFX_CGCG |
5d111f5b 1175 AMD_CG_SUPPORT_GFX_CGLS |
f9da7c43 1176 AMD_CG_SUPPORT_GFX_CP_LS |
5d111f5b 1177 AMD_CG_SUPPORT_HDP_MGCG |
f7ee1995
LM		 1178 AMD_CG_SUPPORT_HDP_LS |
1179 AMD_CG_SUPPORT_SDMA_MGCG |
a840159c
LM		 1180 AMD_CG_SUPPORT_SDMA_LS |
1181 AMD_CG_SUPPORT_MC_MGCG |
227f7d58 1182 AMD_CG_SUPPORT_MC_LS |
e89e2237
LL		 1183 AMD_CG_SUPPORT_IH_CG |
1184 AMD_CG_SUPPORT_VCN_MGCG |
1185 AMD_CG_SUPPORT_JPEG_MGCG;
0e54df05 1186 adev->pg_flags = 0;
d57c3d56 1187 adev->external_rev_id = adev->rev_id + 0x32;
0e54df05 1188 break;
080deab6 1189 case CHIP_RENOIR:
e09ce481 1190 adev->asic_funcs = &soc15_asic_funcs;
ec3636a5
PL		 1191 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1192 AMD_CG_SUPPORT_GFX_MGLS |
1193 AMD_CG_SUPPORT_GFX_3D_CGCG |
1194 AMD_CG_SUPPORT_GFX_3D_CGLS |
1195 AMD_CG_SUPPORT_GFX_CGCG |
1196 AMD_CG_SUPPORT_GFX_CGLS |
a2d15255
PL		 1197 AMD_CG_SUPPORT_GFX_CP_LS |
1198 AMD_CG_SUPPORT_MC_MGCG |
ef0e7d08
PL		 1199 AMD_CG_SUPPORT_MC_LS |
1200 AMD_CG_SUPPORT_SDMA_MGCG |
d98930f5 1201 AMD_CG_SUPPORT_SDMA_LS |
9deac0a4 1202 AMD_CG_SUPPORT_BIF_LS |
de273070 1203 AMD_CG_SUPPORT_HDP_LS |
753c929c 1204 AMD_CG_SUPPORT_ROM_MGCG |
91ec8bbb 1205 AMD_CG_SUPPORT_VCN_MGCG |
099d66e4 1206 AMD_CG_SUPPORT_JPEG_MGCG |
e2ef3b70
PL		 1207 AMD_CG_SUPPORT_IH_CG |
1208 AMD_CG_SUPPORT_ATHUB_LS |
8db63b7c
PL		 1209 AMD_CG_SUPPORT_ATHUB_MGCG |
1210 AMD_CG_SUPPORT_DF_MGCG;
85400984
TT		 1211 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1212 AMD_PG_SUPPORT_VCN |
099d66e4 1213 AMD_PG_SUPPORT_JPEG |
85400984 1214 AMD_PG_SUPPORT_VCN_DPG;
080deab6
HR		 1215 adev->external_rev_id = adev->rev_id + 0x91;
1216 break;
220ab9bd
KW		 1217 default:
1218 /* FIXME: not supported yet */
1219 return -EINVAL;
1220 }
1221
ab276632
XY		 1222 if (amdgpu_sriov_vf(adev)) {
1223 amdgpu_virt_init_setting(adev);
1224 xgpu_ai_mailbox_set_irq_funcs(adev);
1225 }
1226
220ab9bd
KW		 1227 return 0;
1228}
1229
81758c55
ML		 1230static int soc15_common_late_init(void *handle)
1231{
1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
22e1d14f 1233 int r = 0;
81758c55
ML		 1234
1235 if (amdgpu_sriov_vf(adev))
1236 xgpu_ai_mailbox_get_irq(adev);
1237
22e1d14f
HZ		 1238 if (adev->nbio.funcs->ras_late_init)
1239 r = adev->nbio.funcs->ras_late_init(adev);
1240
1241 return r;
81758c55
ML		 1242}
1243
220ab9bd
KW		 1244static int soc15_common_sw_init(void *handle)
1245{
81758c55
ML		 1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1247
1248 if (amdgpu_sriov_vf(adev))
1249 xgpu_ai_mailbox_add_irq_id(adev);
1250
e4cf4bf5
JK		 1251 adev->df_funcs->sw_init(adev);
1252
220ab9bd
KW		 1253 return 0;
1254}
1255
1256static int soc15_common_sw_fini(void *handle)
1257{
f1d59e00
JZ		 1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1259
de9bbd52 1260 amdgpu_nbio_ras_fini(adev);
f1d59e00 1261 adev->df_funcs->sw_fini(adev);
220ab9bd
KW		 1262 return 0;
1263}
1264
7c94bc82
OZ		 1265static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1266{
1267 int i;
1268 struct amdgpu_ring *ring;
1269
4cd4c5c0
ML		 1270 /* sdma/ih doorbell range are programed by hypervisor */
1271 if (!amdgpu_sriov_vf(adev)) {
98cad2de
TH		 1272 for (i = 0; i < adev->sdma.num_instances; i++) {
1273 ring = &adev->sdma.instance[i].ring;
bebc0762 1274 adev->nbio.funcs->sdma_doorbell_range(adev, i,
98cad2de
TH		 1275 ring->use_doorbell, ring->doorbell_index,
1276 adev->doorbell_index.sdma_doorbell_range);
1277 }
7c94bc82 1278
bebc0762 1279 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
7c94bc82 1280 adev->irq.ih.doorbell_index);
4cd4c5c0 1281 }
7c94bc82
OZ		 1282}
1283
220ab9bd
KW		 1284static int soc15_common_hw_init(void *handle)
1285{
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287
220ab9bd
KW		 1288 /* enable pcie gen2/3 link */
1289 soc15_pcie_gen3_enable(adev);
1290 /* enable aspm */
1291 soc15_program_aspm(adev);
833fa075 1292 /* setup nbio registers */
bebc0762 1293 adev->nbio.funcs->init_registers(adev);
88807dc8
OZ		 1294 /* remap HDP registers to a hole in mmio space,
1295 * for the purpose of expose those registers
1296 * to process space
1297 */
bebc0762
HZ		 1298 if (adev->nbio.funcs->remap_hdp_registers)
1299 adev->nbio.funcs->remap_hdp_registers(adev);
e4cf4bf5 1300
220ab9bd
KW		 1301 /* enable the doorbell aperture */
1302 soc15_enable_doorbell_aperture(adev, true);
7c94bc82
OZ		 1303 /* HW doorbell routing policy: doorbell writing not
1304 * in SDMA/IH/MM/ACV range will be routed to CP. So
1305 * we need to init SDMA/IH/MM/ACV doorbell range prior
1306 * to CP ip block init and ring test.
1307 */
1308 soc15_doorbell_range_init(adev);
220ab9bd
KW		 1309
1310 return 0;
1311}
1312
1313static int soc15_common_hw_fini(void *handle)
1314{
1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317 /* disable the doorbell aperture */
1318 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 1319 if (amdgpu_sriov_vf(adev))
1320 xgpu_ai_mailbox_put_irq(adev);
220ab9bd 1321
cde85ac2
PY		 1322 if (adev->nbio.ras_if &&
1323 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
22e1d14f
HZ		 1324 if (adev->nbio.funcs->init_ras_controller_interrupt)
1325 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1326 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1327 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1328 }
1329
220ab9bd
KW		 1330 return 0;
1331}
1332
1333static int soc15_common_suspend(void *handle)
1334{
1335 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1336
1337 return soc15_common_hw_fini(adev);
1338}
1339
1340static int soc15_common_resume(void *handle)
1341{
1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1343
1344 return soc15_common_hw_init(adev);
1345}
1346
1347static bool soc15_common_is_idle(void *handle)
1348{
1349 return true;
1350}
1351
1352static int soc15_common_wait_for_idle(void *handle)
1353{
1354 return 0;
1355}
1356
1357static int soc15_common_soft_reset(void *handle)
1358{
1359 return 0;
1360}
1361
1362static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1363{
1364 uint32_t def, data;
1365
6acb87ac
LM		 1366 if (adev->asic_type == CHIP_VEGA20 ||
1367 adev->asic_type == CHIP_ARCTURUS) {
a5d0f456 1368 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
220ab9bd 1369
a5d0f456
KF		 1370 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1371 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1372 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1373 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1374 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1375 else
1376 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1377 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1378 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1379 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
220ab9bd 1380
a5d0f456
KF		 1381 if (def != data)
1382 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1383 } else {
1384 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1385
1386 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1387 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1388 else
1389 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1390
1391 if (def != data)
1392 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1393 }
220ab9bd
KW		 1394}
1395
1396static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1397{
1398 uint32_t def, data;
1399
1400 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1401
1402 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1403 data &= ~(0x01000000 |
1404 0x02000000 |
1405 0x04000000 |
1406 0x08000000 |
1407 0x10000000 |
1408 0x20000000 |
1409 0x40000000 |
1410 0x80000000);
1411 else
1412 data |= (0x01000000 |
1413 0x02000000 |
1414 0x04000000 |
1415 0x08000000 |
1416 0x10000000 |
1417 0x20000000 |
1418 0x40000000 |
1419 0x80000000);
1420
1421 if (def != data)
1422 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1423}
1424
1425static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1426{
1427 uint32_t def, data;
1428
1429 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1430
1431 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1432 data |= 1;
1433 else
1434 data &= ~1;
1435
1436 if (def != data)
1437 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1438}
1439
1440static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1441 bool enable)
1442{
1443 uint32_t def, data;
1444
1445 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1446
1447 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1448 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1449 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1450 else
1451 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1452 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1453
1454 if (def != data)
1455 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1456}
1457
220ab9bd
KW		 1458static int soc15_common_set_clockgating_state(void *handle,
1459 enum amd_clockgating_state state)
1460{
1461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1462
6e9dc861
ML		 1463 if (amdgpu_sriov_vf(adev))
1464 return 0;
1465
220ab9bd
KW		 1466 switch (adev->asic_type) {
1467 case CHIP_VEGA10:
692069a1 1468 case CHIP_VEGA12:
f980d127 1469 case CHIP_VEGA20:
bebc0762 1470 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
220ab9bd 1471 state == AMD_CG_STATE_GATE ? true : false);
bebc0762 1472 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 1473 state == AMD_CG_STATE_GATE ? true : false);
1474 soc15_update_hdp_light_sleep(adev,
1475 state == AMD_CG_STATE_GATE ? true : false);
1476 soc15_update_drm_clock_gating(adev,
1477 state == AMD_CG_STATE_GATE ? true : false);
1478 soc15_update_drm_light_sleep(adev,
1479 state == AMD_CG_STATE_GATE ? true : false);
1480 soc15_update_rom_medium_grain_clock_gating(adev,
1481 state == AMD_CG_STATE_GATE ? true : false);
070706c0 1482 adev->df_funcs->update_medium_grain_clock_gating(adev,
220ab9bd
KW		 1483 state == AMD_CG_STATE_GATE ? true : false);
1484 break;
9e5a9eb4 1485 case CHIP_RAVEN:
f78e007f 1486 case CHIP_RENOIR:
bebc0762 1487 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 1488 state == AMD_CG_STATE_GATE ? true : false);
bebc0762 1489 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 1490 state == AMD_CG_STATE_GATE ? true : false);
1491 soc15_update_hdp_light_sleep(adev,
1492 state == AMD_CG_STATE_GATE ? true : false);
1493 soc15_update_drm_clock_gating(adev,
1494 state == AMD_CG_STATE_GATE ? true : false);
1495 soc15_update_drm_light_sleep(adev,
1496 state == AMD_CG_STATE_GATE ? true : false);
1497 soc15_update_rom_medium_grain_clock_gating(adev,
1498 state == AMD_CG_STATE_GATE ? true : false);
1499 break;
6acb87ac
LM		 1500 case CHIP_ARCTURUS:
1501 soc15_update_hdp_light_sleep(adev,
1502 state == AMD_CG_STATE_GATE ? true : false);
1503 break;
220ab9bd
KW		 1504 default:
1505 break;
1506 }
1507 return 0;
1508}
1509
f9abe35c
HR		 1510static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1511{
1512 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1513 int data;
1514
1515 if (amdgpu_sriov_vf(adev))
1516 *flags = 0;
1517
bebc0762 1518 adev->nbio.funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1519
1520 /* AMD_CG_SUPPORT_HDP_LS */
1521 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1522 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1523 *flags |= AMD_CG_SUPPORT_HDP_LS;
1524
1525 /* AMD_CG_SUPPORT_DRM_MGCG */
1526 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1527 if (!(data & 0x01000000))
1528 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1529
1530 /* AMD_CG_SUPPORT_DRM_LS */
1531 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1532 if (data & 0x1)
1533 *flags |= AMD_CG_SUPPORT_DRM_LS;
1534
1535 /* AMD_CG_SUPPORT_ROM_MGCG */
1536 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1537 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1538 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1539
070706c0 1540 adev->df_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1541}
1542
220ab9bd
KW		 1543static int soc15_common_set_powergating_state(void *handle,
1544 enum amd_powergating_state state)
1545{
1546 /* todo */
1547 return 0;
1548}
1549
1550const struct amd_ip_funcs soc15_common_ip_funcs = {
1551 .name = "soc15_common",
1552 .early_init = soc15_common_early_init,
81758c55 1553 .late_init = soc15_common_late_init,
220ab9bd
KW		 1554 .sw_init = soc15_common_sw_init,
1555 .sw_fini = soc15_common_sw_fini,
1556 .hw_init = soc15_common_hw_init,
1557 .hw_fini = soc15_common_hw_fini,
1558 .suspend = soc15_common_suspend,
1559 .resume = soc15_common_resume,
1560 .is_idle = soc15_common_is_idle,
1561 .wait_for_idle = soc15_common_wait_for_idle,
1562 .soft_reset = soc15_common_soft_reset,
1563 .set_clockgating_state = soc15_common_set_clockgating_state,
1564 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 1565 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 1566};
Linux 6.x block layer and io_uring tree(s)