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drm/amd/display: 3.2.31
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / soc15.c
CommitLineData
220ab9bd
KW		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
248a1d6f 26#include <drm/drmP.h>
220ab9bd 27#include "amdgpu.h"
d05da0e2 28#include "amdgpu_atombios.h"
220ab9bd
KW		 29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "amdgpu_psp.h"
34#include "atom.h"
35#include "amd_pcie.h"
36
5d735f83 37#include "uvd/uvd_7_0_offset.h"
cde5c34f
FX		 38#include "gc/gc_9_0_offset.h"
39#include "gc/gc_9_0_sh_mask.h"
812f77b7
FX		 40#include "sdma0/sdma0_4_0_offset.h"
41#include "sdma1/sdma1_4_0_offset.h"
75199b8c
FX		 42#include "hdp/hdp_4_0_offset.h"
43#include "hdp/hdp_4_0_sh_mask.h"
424d9bb4
FX		 44#include "smuio/smuio_9_0_offset.h"
45#include "smuio/smuio_9_0_sh_mask.h"
b45e18ac 46#include "nbio/nbio_7_0_default.h"
88807dc8 47#include "nbio/nbio_7_0_offset.h"
b45e18ac
KR		 48#include "nbio/nbio_7_0_sh_mask.h"
49#include "nbio/nbio_7_0_smn.h"
9281f12c 50#include "mp/mp_9_0_offset.h"
220ab9bd
KW		 51
52#include "soc15.h"
53#include "soc15_common.h"
54#include "gfx_v9_0.h"
55#include "gmc_v9_0.h"
56#include "gfxhub_v1_0.h"
57#include "mmhub_v1_0.h"
070706c0 58#include "df_v1_7.h"
698758bb 59#include "df_v3_6.h"
220ab9bd
KW		 60#include "vega10_ih.h"
61#include "sdma_v4_0.h"
62#include "uvd_v7_0.h"
63#include "vce_v4_0.h"
f2d7e707 64#include "vcn_v1_0.h"
796b6568 65#include "dce_virtual.h"
f1a34465 66#include "mxgpu_ai.h"
2da5410b 67#include "amdgpu_smu.h"
88807dc8 68#include <uapi/linux/kfd_ioctl.h>
220ab9bd 69
220ab9bd
KW		 70#define mmMP0_MISC_CGTT_CTRL0 0x01b9
71#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
72#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
73#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
74
a5d0f456
KF		 75/* for Vega20 register name change */
76#define mmHDP_MEM_POWER_CTRL 0x00d4
77#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
78#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
79#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
80#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
81#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
220ab9bd
KW		 82/*
83 * Indirect registers accessor
84 */
85static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
86{
87 unsigned long flags, address, data;
88 u32 r;
946a4d5b
SL		 89 address = adev->nbio_funcs->get_pcie_index_offset(adev);
90 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 91
92 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
93 WREG32(address, reg);
94 (void)RREG32(address);
95 r = RREG32(data);
96 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
97 return r;
98}
99
100static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
101{
102 unsigned long flags, address, data;
220ab9bd 103
946a4d5b
SL		 104 address = adev->nbio_funcs->get_pcie_index_offset(adev);
105 data = adev->nbio_funcs->get_pcie_data_offset(adev);
220ab9bd
KW		 106
107 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
108 WREG32(address, reg);
109 (void)RREG32(address);
110 WREG32(data, v);
111 (void)RREG32(data);
112 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
113}
114
115static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
116{
117 unsigned long flags, address, data;
118 u32 r;
119
120 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
121 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
122
123 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
124 WREG32(address, ((reg) & 0x1ff));
125 r = RREG32(data);
126 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
127 return r;
128}
129
130static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
131{
132 unsigned long flags, address, data;
133
134 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
135 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
136
137 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
138 WREG32(address, ((reg) & 0x1ff));
139 WREG32(data, (v));
140 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
141}
142
143static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
144{
145 unsigned long flags, address, data;
146 u32 r;
147
148 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
149 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
150
151 spin_lock_irqsave(&adev->didt_idx_lock, flags);
152 WREG32(address, (reg));
153 r = RREG32(data);
154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
155 return r;
156}
157
158static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
159{
160 unsigned long flags, address, data;
161
162 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
163 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
164
165 spin_lock_irqsave(&adev->didt_idx_lock, flags);
166 WREG32(address, (reg));
167 WREG32(data, (v));
168 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
169}
170
560460f2
EQ		 171static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
172{
173 unsigned long flags;
174 u32 r;
175
176 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
177 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
178 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
179 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
180 return r;
181}
182
183static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
184{
185 unsigned long flags;
186
187 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
188 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
189 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
190 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
191}
192
2f11fb02
EQ		 193static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
194{
195 unsigned long flags;
196 u32 r;
197
198 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
199 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
200 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
201 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
202 return r;
203}
204
205static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
206{
207 unsigned long flags;
208
209 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
210 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
211 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
212 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
213}
214
220ab9bd
KW		 215static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
216{
bf383fb6 217 return adev->nbio_funcs->get_memsize(adev);
220ab9bd
KW		 218}
219
220ab9bd
KW		 220static u32 soc15_get_xclk(struct amdgpu_device *adev)
221{
76d6172b 222 return adev->clock.spll.reference_freq;
220ab9bd
KW		 223}
224
225
226void soc15_grbm_select(struct amdgpu_device *adev,
227 u32 me, u32 pipe, u32 queue, u32 vmid)
228{
229 u32 grbm_gfx_cntl = 0;
230 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
231 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
232 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
233 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
234
1bff7f6c 235 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
220ab9bd
KW		 236}
237
238static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
239{
240 /* todo */
241}
242
243static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
244{
245 /* todo */
246 return false;
247}
248
249static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
250 u8 *bios, u32 length_bytes)
251{
252 u32 *dw_ptr;
253 u32 i, length_dw;
254
255 if (bios == NULL)
256 return false;
257 if (length_bytes == 0)
258 return false;
259 /* APU vbios image is part of sbios image */
260 if (adev->flags & AMD_IS_APU)
261 return false;
262
263 dw_ptr = (u32 *)bios;
264 length_dw = ALIGN(length_bytes, 4) / 4;
265
266 /* set rom index to 0 */
267 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
268 /* read out the rom data */
269 for (i = 0; i < length_dw; i++)
270 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
271
272 return true;
273}
274
946a4d5b
SL		 275struct soc15_allowed_register_entry {
276 uint32_t hwip;
277 uint32_t inst;
278 uint32_t seg;
279 uint32_t reg_offset;
280 bool grbm_indexed;
281};
282
283
284static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
285 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
286 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
287 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
288 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
289 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
290 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
291 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
292 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
293 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
294 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
295 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
296 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
297 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
298 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
299 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
300 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
301 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
302 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
5eeae247 303 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
220ab9bd
KW		 304};
305
306static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
307 u32 sh_num, u32 reg_offset)
308{
309 uint32_t val;
310
311 mutex_lock(&adev->grbm_idx_mutex);
312 if (se_num != 0xffffffff || sh_num != 0xffffffff)
313 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
314
315 val = RREG32(reg_offset);
316
317 if (se_num != 0xffffffff || sh_num != 0xffffffff)
318 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
319 mutex_unlock(&adev->grbm_idx_mutex);
320 return val;
321}
322
c013cea2
AD		 323static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
324 bool indexed, u32 se_num,
325 u32 sh_num, u32 reg_offset)
326{
327 if (indexed) {
328 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
329 } else {
cd29253f 330 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
c013cea2 331 return adev->gfx.config.gb_addr_config;
5eeae247
AD		 332 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
333 return adev->gfx.config.db_debug2;
cd29253f 334 return RREG32(reg_offset);
c013cea2
AD		 335 }
336}
337
220ab9bd
KW		 338static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
339 u32 sh_num, u32 reg_offset, u32 *value)
340{
3032f350 341 uint32_t i;
946a4d5b 342 struct soc15_allowed_register_entry *en;
220ab9bd
KW		 343
344 *value = 0;
220ab9bd 345 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
946a4d5b
SL		 346 en = &soc15_allowed_read_registers[i];
347 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
348 + en->reg_offset))
220ab9bd
KW		 349 continue;
350
97fcc76b
CK		 351 *value = soc15_get_register_value(adev,
352 soc15_allowed_read_registers[i].grbm_indexed,
353 se_num, sh_num, reg_offset);
220ab9bd
KW		 354 return 0;
355 }
356 return -EINVAL;
357}
358
946a4d5b
SL		 359
360/**
361 * soc15_program_register_sequence - program an array of registers.
362 *
363 * @adev: amdgpu_device pointer
364 * @regs: pointer to the register array
365 * @array_size: size of the register array
366 *
367 * Programs an array or registers with and and or masks.
368 * This is a helper for setting golden registers.
369 */
370
371void soc15_program_register_sequence(struct amdgpu_device *adev,
372 const struct soc15_reg_golden *regs,
373 const u32 array_size)
374{
375 const struct soc15_reg_golden *entry;
376 u32 tmp, reg;
377 int i;
378
379 for (i = 0; i < array_size; ++i) {
380 entry = &regs[i];
381 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
382
383 if (entry->and_mask == 0xffffffff) {
384 tmp = entry->or_mask;
385 } else {
386 tmp = RREG32(reg);
387 tmp &= ~(entry->and_mask);
388 tmp |= entry->or_mask;
389 }
1bff7f6c
TH		 390
391 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
392 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
393 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
394 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
395 WREG32_RLC(reg, tmp);
396 else
397 WREG32(reg, tmp);
398
946a4d5b
SL		 399 }
400
401}
402
e2b6d053 403static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
220ab9bd
KW		 404{
405 u32 i;
39fee32b 406 int ret = 0;
220ab9bd 407
98512bb8
KW		 408 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
409
e2b6d053 410 dev_info(adev->dev, "GPU mode1 reset\n");
220ab9bd
KW		 411
412 /* disable BM */
413 pci_clear_master(adev->pdev);
220ab9bd 414
98512bb8
KW		 415 pci_save_state(adev->pdev);
416
39fee32b
EQ		 417 ret = psp_gpu_reset(adev);
418 if (ret)
419 dev_err(adev->dev, "GPU mode1 reset failed\n");
98512bb8
KW		 420
421 pci_restore_state(adev->pdev);
220ab9bd
KW		 422
423 /* wait for asic to come out of reset */
424 for (i = 0; i < adev->usec_timeout; i++) {
bf383fb6
AD		 425 u32 memsize = adev->nbio_funcs->get_memsize(adev);
426
aecbe64f 427 if (memsize != 0xffffffff)
220ab9bd
KW		 428 break;
429 udelay(1);
430 }
431
d05da0e2 432 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
220ab9bd 433
39fee32b 434 return ret;
220ab9bd
KW		 435}
436
e2b6d053
JQ		 437static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
438{
439 void *pp_handle = adev->powerplay.pp_handle;
440 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
441
442 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
443 *cap = false;
1f46df61 444 return -ENOENT;
e2b6d053
JQ		 445 }
446
447 return pp_funcs->get_asic_baco_capability(pp_handle, cap);
448}
449
450static int soc15_asic_baco_reset(struct amdgpu_device *adev)
451{
452 void *pp_handle = adev->powerplay.pp_handle;
453 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
454
455 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
1f46df61 456 return -ENOENT;
e2b6d053
JQ		 457
458 /* enter BACO state */
459 if (pp_funcs->set_asic_baco_state(pp_handle, 1))
1f46df61 460 return -EIO;
e2b6d053
JQ		 461
462 /* exit BACO state */
463 if (pp_funcs->set_asic_baco_state(pp_handle, 0))
1f46df61 464 return -EIO;
e2b6d053
JQ		 465
466 dev_info(adev->dev, "GPU BACO reset\n");
467
0c5ccf14
EQ		 468 adev->in_baco_reset = 1;
469
e2b6d053
JQ		 470 return 0;
471}
472
473static int soc15_asic_reset(struct amdgpu_device *adev)
474{
475 int ret;
476 bool baco_reset;
477
478 switch (adev->asic_type) {
479 case CHIP_VEGA10:
f8b18cf4 480 case CHIP_VEGA12:
e2b6d053
JQ		 481 soc15_asic_get_baco_capability(adev, &baco_reset);
482 break;
017d75f1
EQ		 483 case CHIP_VEGA20:
484 if (adev->psp.sos_fw_version >= 0x80067)
485 soc15_asic_get_baco_capability(adev, &baco_reset);
486 else
487 baco_reset = false;
488 break;
e2b6d053
JQ		 489 default:
490 baco_reset = false;
491 break;
492 }
493
494 if (baco_reset)
495 ret = soc15_asic_baco_reset(adev);
496 else
497 ret = soc15_asic_mode1_reset(adev);
498
499 return ret;
500}
501
220ab9bd
KW		 502/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
503 u32 cntl_reg, u32 status_reg)
504{
505 return 0;
506}*/
507
508static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
509{
510 /*int r;
511
512 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
513 if (r)
514 return r;
515
516 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
517 */
518 return 0;
519}
520
521static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
522{
523 /* todo */
524
525 return 0;
526}
527
528static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
529{
530 if (pci_is_root_bus(adev->pdev->bus))
531 return;
532
533 if (amdgpu_pcie_gen2 == 0)
534 return;
535
536 if (adev->flags & AMD_IS_APU)
537 return;
538
539 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
540 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
541 return;
542
543 /* todo */
544}
545
546static void soc15_program_aspm(struct amdgpu_device *adev)
547{
548
549 if (amdgpu_aspm == 0)
550 return;
551
552 /* todo */
553}
554
555static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 556 bool enable)
220ab9bd 557{
bf383fb6
AD		 558 adev->nbio_funcs->enable_doorbell_aperture(adev, enable);
559 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable);
220ab9bd
KW		 560}
561
562static const struct amdgpu_ip_block_version vega10_common_ip_block =
563{
564 .type = AMD_IP_BLOCK_TYPE_COMMON,
565 .major = 2,
566 .minor = 0,
567 .rev = 0,
568 .funcs = &soc15_common_ip_funcs,
569};
570
4cb0becb
HR		 571static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
572{
573 return adev->nbio_funcs->get_rev_id(adev);
574}
575
220ab9bd
KW		 576int soc15_set_ip_blocks(struct amdgpu_device *adev)
577{
4522824c
SL		 578 /* Set IP register base before any HW register access */
579 switch (adev->asic_type) {
580 case CHIP_VEGA10:
3084eb00 581 case CHIP_VEGA12:
4522824c
SL		 582 case CHIP_RAVEN:
583 vega10_reg_base_init(adev);
584 break;
8ee273e5
FX		 585 case CHIP_VEGA20:
586 vega20_reg_base_init(adev);
587 break;
4522824c
SL		 588 default:
589 return -EINVAL;
590 }
591
47622ba0
AD		 592 if (adev->asic_type == CHIP_VEGA20)
593 adev->gmc.xgmi.supported = true;
594
bf383fb6
AD		 595 if (adev->flags & AMD_IS_APU)
596 adev->nbio_funcs = &nbio_v7_0_funcs;
fe3c9489
FX		 597 else if (adev->asic_type == CHIP_VEGA20)
598 adev->nbio_funcs = &nbio_v7_4_funcs;
bf383fb6
AD		 599 else
600 adev->nbio_funcs = &nbio_v6_1_funcs;
601
698758bb
FX		 602 if (adev->asic_type == CHIP_VEGA20)
603 adev->df_funcs = &df_v3_6_funcs;
604 else
605 adev->df_funcs = &df_v1_7_funcs;
4cb0becb
HR		 606
607 adev->rev_id = soc15_get_rev_id(adev);
bf383fb6 608 adev->nbio_funcs->detect_hw_virt(adev);
1b922423 609
f1a34465
XY		 610 if (amdgpu_sriov_vf(adev))
611 adev->virt.ops = &xgpu_ai_virt_ops;
612
220ab9bd
KW		 613 switch (adev->asic_type) {
614 case CHIP_VEGA10:
692069a1 615 case CHIP_VEGA12:
7c7af6c1 616 case CHIP_VEGA20:
2990a1fc
AD		 617 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
618 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2d11fd3f
TH		 619
620 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
621 if (amdgpu_sriov_vf(adev)) {
622 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
623 if (adev->asic_type == CHIP_VEGA20)
624 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
625 else
626 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
627 }
628 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
629 } else {
630 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
631 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
632 if (adev->asic_type == CHIP_VEGA20)
633 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
634 else
635 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
636 }
3680b2a5 637 }
009d9ed6
RZ		 638 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
639 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2da5410b 640 if (!amdgpu_sriov_vf(adev)) {
dc8e3a0c 641 if (is_support_sw_smu(adev))
2da5410b
HR		 642 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
643 else
644 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
645 }
f8445307 646 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 647 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
ab587d4a
AD		 648#if defined(CONFIG_DRM_AMD_DC)
649 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 650 amdgpu_device_ip_block_add(adev, &dm_ip_block);
ab587d4a
AD		 651#else
652# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
653#endif
846311ae
FM		 654 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
655 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
656 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
657 }
220ab9bd 658 break;
1023b797 659 case CHIP_RAVEN:
40c2358b
HR		 660 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
661 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
2990a1fc 662 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
3680b2a5
EQ		 663 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
664 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
009d9ed6
RZ		 665 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
666 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
b905090d 667 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
d67fed16 668 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
2990a1fc 669 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
0bf954c1
AD		 670#if defined(CONFIG_DRM_AMD_DC)
671 else if (amdgpu_device_has_dc_support(adev))
2990a1fc 672 amdgpu_device_ip_block_add(adev, &dm_ip_block);
0bf954c1
AD		 673#else
674# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
675#endif
2990a1fc 676 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1023b797 677 break;
220ab9bd
KW		 678 default:
679 return -EINVAL;
680 }
681
682 return 0;
683}
684
69882565 685static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
73c73240 686{
69882565 687 adev->nbio_funcs->hdp_flush(adev, ring);
73c73240
AD		 688}
689
69882565
CK		 690static void soc15_invalidate_hdp(struct amdgpu_device *adev,
691 struct amdgpu_ring *ring)
73c73240 692{
69882565
CK		 693 if (!ring || !ring->funcs->emit_wreg)
694 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
695 else
696 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
697 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
73c73240
AD		 698}
699
adbd4f89
AD		 700static bool soc15_need_full_reset(struct amdgpu_device *adev)
701{
702 /* change this when we implement soft reset */
703 return true;
704}
b45e18ac
KR		 705static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
706 uint64_t *count1)
707{
708 uint32_t perfctr = 0;
709 uint64_t cnt0_of, cnt1_of;
710 int tmp;
711
712 /* This reports 0 on APUs, so return to avoid writing/reading registers
713 * that may or may not be different from their GPU counterparts
714 */
715 if (adev->flags & AMD_IS_APU)
716 return;
717
718 /* Set the 2 events that we wish to watch, defined above */
719 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
720 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
721 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
722
723 /* Write to enable desired perf counters */
724 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
725 /* Zero out and enable the perf counters
726 * Write 0x5:
727 * Bit 0 = Start all counters(1)
728 * Bit 2 = Global counter reset enable(1)
729 */
730 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
731
732 msleep(1000);
733
734 /* Load the shadow and disable the perf counters
735 * Write 0x2:
736 * Bit 0 = Stop counters(0)
737 * Bit 1 = Load the shadow counters(1)
738 */
739 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
740
741 /* Read register values to get any >32bit overflow */
742 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
743 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
744 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
745
746 /* Get the values and add the overflow */
747 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
748 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
749}
adbd4f89 750
9281f12c
AD		 751static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
752{
753 u32 sol_reg;
754
755 if (adev->flags & AMD_IS_APU)
756 return false;
757
758 /* Check sOS sign of life register to confirm sys driver and sOS
759 * are already been loaded.
760 */
761 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
762 if (sol_reg)
763 return true;
764
765 return false;
766}
767
dcea6e65
KR		 768static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
769{
770 uint64_t nak_r, nak_g;
771
772 /* Get the number of NAKs received and generated */
773 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
774 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
775
776 /* Add the total number of NAKs, i.e the number of replays */
777 return (nak_r + nak_g);
778}
779
220ab9bd
KW		 780static const struct amdgpu_asic_funcs soc15_asic_funcs =
781{
782 .read_disabled_bios = &soc15_read_disabled_bios,
783 .read_bios_from_rom = &soc15_read_bios_from_rom,
784 .read_register = &soc15_read_register,
785 .reset = &soc15_asic_reset,
786 .set_vga_state = &soc15_vga_set_state,
787 .get_xclk = &soc15_get_xclk,
788 .set_uvd_clocks = &soc15_set_uvd_clocks,
789 .set_vce_clocks = &soc15_set_vce_clocks,
790 .get_config_memsize = &soc15_get_config_memsize,
73c73240
AD		 791 .flush_hdp = &soc15_flush_hdp,
792 .invalidate_hdp = &soc15_invalidate_hdp,
adbd4f89 793 .need_full_reset = &soc15_need_full_reset,
062f3807 794 .init_doorbell_index = &vega10_doorbell_index_init,
b45e18ac 795 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 796 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 797 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
220ab9bd
KW		 798};
799
c93aa775
OZ		 800static const struct amdgpu_asic_funcs vega20_asic_funcs =
801{
802 .read_disabled_bios = &soc15_read_disabled_bios,
803 .read_bios_from_rom = &soc15_read_bios_from_rom,
804 .read_register = &soc15_read_register,
805 .reset = &soc15_asic_reset,
806 .set_vga_state = &soc15_vga_set_state,
807 .get_xclk = &soc15_get_xclk,
808 .set_uvd_clocks = &soc15_set_uvd_clocks,
809 .set_vce_clocks = &soc15_set_vce_clocks,
810 .get_config_memsize = &soc15_get_config_memsize,
811 .flush_hdp = &soc15_flush_hdp,
812 .invalidate_hdp = &soc15_invalidate_hdp,
813 .need_full_reset = &soc15_need_full_reset,
814 .init_doorbell_index = &vega20_doorbell_index_init,
b45e18ac 815 .get_pcie_usage = &soc15_get_pcie_usage,
9281f12c 816 .need_reset_on_init = &soc15_need_reset_on_init,
dcea6e65 817 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
220ab9bd
KW		 818};
819
820static int soc15_common_early_init(void *handle)
821{
88807dc8 822#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
220ab9bd
KW		 823 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
824
88807dc8
OZ		 825 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
826 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
220ab9bd
KW		 827 adev->smc_rreg = NULL;
828 adev->smc_wreg = NULL;
829 adev->pcie_rreg = &soc15_pcie_rreg;
830 adev->pcie_wreg = &soc15_pcie_wreg;
831 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
832 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
833 adev->didt_rreg = &soc15_didt_rreg;
834 adev->didt_wreg = &soc15_didt_wreg;
560460f2
EQ		 835 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
836 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
2f11fb02
EQ		 837 adev->se_cac_rreg = &soc15_se_cac_rreg;
838 adev->se_cac_wreg = &soc15_se_cac_wreg;
220ab9bd 839
220ab9bd 840
220ab9bd
KW		 841 adev->external_rev_id = 0xFF;
842 switch (adev->asic_type) {
843 case CHIP_VEGA10:
c93aa775 844 adev->asic_funcs = &soc15_asic_funcs;
220ab9bd
KW		 845 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
846 AMD_CG_SUPPORT_GFX_MGLS |
847 AMD_CG_SUPPORT_GFX_RLC_LS |
848 AMD_CG_SUPPORT_GFX_CP_LS |
849 AMD_CG_SUPPORT_GFX_3D_CGCG |
850 AMD_CG_SUPPORT_GFX_3D_CGLS |
851 AMD_CG_SUPPORT_GFX_CGCG |
852 AMD_CG_SUPPORT_GFX_CGLS |
853 AMD_CG_SUPPORT_BIF_MGCG |
854 AMD_CG_SUPPORT_BIF_LS |
855 AMD_CG_SUPPORT_HDP_LS |
856 AMD_CG_SUPPORT_DRM_MGCG |
857 AMD_CG_SUPPORT_DRM_LS |
858 AMD_CG_SUPPORT_ROM_MGCG |
859 AMD_CG_SUPPORT_DF_MGCG |
860 AMD_CG_SUPPORT_SDMA_MGCG |
861 AMD_CG_SUPPORT_SDMA_LS |
862 AMD_CG_SUPPORT_MC_MGCG |
863 AMD_CG_SUPPORT_MC_LS;
864 adev->pg_flags = 0;
865 adev->external_rev_id = 0x1;
866 break;
692069a1 867 case CHIP_VEGA12:
c93aa775 868 adev->asic_funcs = &soc15_asic_funcs;
e4a38755
EQ		 869 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
870 AMD_CG_SUPPORT_GFX_MGLS |
871 AMD_CG_SUPPORT_GFX_CGCG |
872 AMD_CG_SUPPORT_GFX_CGLS |
873 AMD_CG_SUPPORT_GFX_3D_CGCG |
874 AMD_CG_SUPPORT_GFX_3D_CGLS |
875 AMD_CG_SUPPORT_GFX_CP_LS |
876 AMD_CG_SUPPORT_MC_LS |
877 AMD_CG_SUPPORT_MC_MGCG |
878 AMD_CG_SUPPORT_SDMA_MGCG |
879 AMD_CG_SUPPORT_SDMA_LS |
880 AMD_CG_SUPPORT_BIF_MGCG |
881 AMD_CG_SUPPORT_BIF_LS |
882 AMD_CG_SUPPORT_HDP_MGCG |
883 AMD_CG_SUPPORT_HDP_LS |
884 AMD_CG_SUPPORT_ROM_MGCG |
885 AMD_CG_SUPPORT_VCE_MGCG |
886 AMD_CG_SUPPORT_UVD_MGCG;
692069a1 887 adev->pg_flags = 0;
f559fe2b 888 adev->external_rev_id = adev->rev_id + 0x14;
692069a1 889 break;
935be7a0 890 case CHIP_VEGA20:
c93aa775 891 adev->asic_funcs = &vega20_asic_funcs;
3fdbab5f
EQ		 892 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
893 AMD_CG_SUPPORT_GFX_MGLS |
894 AMD_CG_SUPPORT_GFX_CGCG |
895 AMD_CG_SUPPORT_GFX_CGLS |
896 AMD_CG_SUPPORT_GFX_3D_CGCG |
897 AMD_CG_SUPPORT_GFX_3D_CGLS |
898 AMD_CG_SUPPORT_GFX_CP_LS |
899 AMD_CG_SUPPORT_MC_LS |
900 AMD_CG_SUPPORT_MC_MGCG |
901 AMD_CG_SUPPORT_SDMA_MGCG |
902 AMD_CG_SUPPORT_SDMA_LS |
903 AMD_CG_SUPPORT_BIF_MGCG |
904 AMD_CG_SUPPORT_BIF_LS |
905 AMD_CG_SUPPORT_HDP_MGCG |
102e4940 906 AMD_CG_SUPPORT_HDP_LS |
3fdbab5f
EQ		 907 AMD_CG_SUPPORT_ROM_MGCG |
908 AMD_CG_SUPPORT_VCE_MGCG |
909 AMD_CG_SUPPORT_UVD_MGCG;
935be7a0
FX		 910 adev->pg_flags = 0;
911 adev->external_rev_id = adev->rev_id + 0x28;
912 break;
957c6fe1 913 case CHIP_RAVEN:
c93aa775 914 adev->asic_funcs = &soc15_asic_funcs;
520cbe0f 915 if (adev->rev_id >= 0x8)
7e4545d3 916 adev->external_rev_id = adev->rev_id + 0x79;
741deade
AD		 917 else if (adev->pdev->device == 0x15d8)
918 adev->external_rev_id = adev->rev_id + 0x41;
7e4545d3
HR		 919 else if (adev->rev_id == 1)
920 adev->external_rev_id = adev->rev_id + 0x20;
741deade 921 else
7e4545d3 922 adev->external_rev_id = adev->rev_id + 0x01;
741deade
AD		 923
924 if (adev->rev_id >= 0x8) {
520cbe0f
HR		 925 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
926 AMD_CG_SUPPORT_GFX_MGLS |
927 AMD_CG_SUPPORT_GFX_CP_LS |
928 AMD_CG_SUPPORT_GFX_3D_CGCG |
929 AMD_CG_SUPPORT_GFX_3D_CGLS |
930 AMD_CG_SUPPORT_GFX_CGCG |
931 AMD_CG_SUPPORT_GFX_CGLS |
932 AMD_CG_SUPPORT_BIF_LS |
933 AMD_CG_SUPPORT_HDP_LS |
934 AMD_CG_SUPPORT_ROM_MGCG |
935 AMD_CG_SUPPORT_MC_MGCG |
936 AMD_CG_SUPPORT_MC_LS |
937 AMD_CG_SUPPORT_SDMA_MGCG |
938 AMD_CG_SUPPORT_SDMA_LS |
939 AMD_CG_SUPPORT_VCN_MGCG;
741deade
AD		 940
941 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
942 } else if (adev->pdev->device == 0x15d8) {
fced5c70
LG		 943 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
944 AMD_CG_SUPPORT_GFX_MGLS |
741deade
AD		 945 AMD_CG_SUPPORT_GFX_CP_LS |
946 AMD_CG_SUPPORT_GFX_3D_CGCG |
947 AMD_CG_SUPPORT_GFX_3D_CGLS |
948 AMD_CG_SUPPORT_GFX_CGCG |
949 AMD_CG_SUPPORT_GFX_CGLS |
950 AMD_CG_SUPPORT_BIF_LS |
951 AMD_CG_SUPPORT_HDP_LS |
952 AMD_CG_SUPPORT_ROM_MGCG |
953 AMD_CG_SUPPORT_MC_MGCG |
954 AMD_CG_SUPPORT_MC_LS |
955 AMD_CG_SUPPORT_SDMA_MGCG |
956 AMD_CG_SUPPORT_SDMA_LS;
957
958 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
959 AMD_PG_SUPPORT_MMHUB |
a3716d3a
JZ		 960 AMD_PG_SUPPORT_VCN |
961 AMD_PG_SUPPORT_VCN_DPG;
741deade 962 } else {
520cbe0f
HR		 963 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
964 AMD_CG_SUPPORT_GFX_MGLS |
965 AMD_CG_SUPPORT_GFX_RLC_LS |
966 AMD_CG_SUPPORT_GFX_CP_LS |
967 AMD_CG_SUPPORT_GFX_3D_CGCG |
968 AMD_CG_SUPPORT_GFX_3D_CGLS |
969 AMD_CG_SUPPORT_GFX_CGCG |
970 AMD_CG_SUPPORT_GFX_CGLS |
971 AMD_CG_SUPPORT_BIF_MGCG |
972 AMD_CG_SUPPORT_BIF_LS |
973 AMD_CG_SUPPORT_HDP_MGCG |
974 AMD_CG_SUPPORT_HDP_LS |
975 AMD_CG_SUPPORT_DRM_MGCG |
976 AMD_CG_SUPPORT_DRM_LS |
977 AMD_CG_SUPPORT_ROM_MGCG |
978 AMD_CG_SUPPORT_MC_MGCG |
979 AMD_CG_SUPPORT_MC_LS |
980 AMD_CG_SUPPORT_SDMA_MGCG |
981 AMD_CG_SUPPORT_SDMA_LS |
982 AMD_CG_SUPPORT_VCN_MGCG;
61c8e90d 983
741deade
AD		 984 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
985 }
a4494fda 986
3b94fb10 987 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
8c7bf583
KF		 988 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
989 AMD_PG_SUPPORT_CP |
990 AMD_PG_SUPPORT_RLC_SMU_HS;
ad5a67a7 991 break;
220ab9bd
KW		 992 default:
993 /* FIXME: not supported yet */
994 return -EINVAL;
995 }
996
ab276632
XY		 997 if (amdgpu_sriov_vf(adev)) {
998 amdgpu_virt_init_setting(adev);
999 xgpu_ai_mailbox_set_irq_funcs(adev);
1000 }
1001
220ab9bd
KW		 1002 return 0;
1003}
1004
81758c55
ML		 1005static int soc15_common_late_init(void *handle)
1006{
1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008
1009 if (amdgpu_sriov_vf(adev))
1010 xgpu_ai_mailbox_get_irq(adev);
1011
1012 return 0;
1013}
1014
220ab9bd
KW		 1015static int soc15_common_sw_init(void *handle)
1016{
81758c55
ML		 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019 if (amdgpu_sriov_vf(adev))
1020 xgpu_ai_mailbox_add_irq_id(adev);
1021
220ab9bd
KW		 1022 return 0;
1023}
1024
1025static int soc15_common_sw_fini(void *handle)
1026{
1027 return 0;
1028}
1029
7c94bc82
OZ		 1030static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1031{
1032 int i;
1033 struct amdgpu_ring *ring;
1034
98cad2de
TH		 1035 /* Two reasons to skip
1036 * 1, Host driver already programmed them
1037 * 2, To avoid registers program violations in SR-IOV
1038 */
1039 if (!amdgpu_virt_support_skip_setting(adev)) {
1040 for (i = 0; i < adev->sdma.num_instances; i++) {
1041 ring = &adev->sdma.instance[i].ring;
1042 adev->nbio_funcs->sdma_doorbell_range(adev, i,
1043 ring->use_doorbell, ring->doorbell_index,
1044 adev->doorbell_index.sdma_doorbell_range);
1045 }
7c94bc82
OZ		 1046 }
1047
1048 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1049 adev->irq.ih.doorbell_index);
1050}
1051
220ab9bd
KW		 1052static int soc15_common_hw_init(void *handle)
1053{
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
220ab9bd
KW		 1056 /* enable pcie gen2/3 link */
1057 soc15_pcie_gen3_enable(adev);
1058 /* enable aspm */
1059 soc15_program_aspm(adev);
833fa075 1060 /* setup nbio registers */
bf383fb6 1061 adev->nbio_funcs->init_registers(adev);
88807dc8
OZ		 1062 /* remap HDP registers to a hole in mmio space,
1063 * for the purpose of expose those registers
1064 * to process space
1065 */
1066 if (adev->nbio_funcs->remap_hdp_registers)
1067 adev->nbio_funcs->remap_hdp_registers(adev);
220ab9bd
KW		 1068 /* enable the doorbell aperture */
1069 soc15_enable_doorbell_aperture(adev, true);
7c94bc82
OZ		 1070 /* HW doorbell routing policy: doorbell writing not
1071 * in SDMA/IH/MM/ACV range will be routed to CP. So
1072 * we need to init SDMA/IH/MM/ACV doorbell range prior
1073 * to CP ip block init and ring test.
1074 */
1075 soc15_doorbell_range_init(adev);
220ab9bd
KW		 1076
1077 return 0;
1078}
1079
1080static int soc15_common_hw_fini(void *handle)
1081{
1082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083
1084 /* disable the doorbell aperture */
1085 soc15_enable_doorbell_aperture(adev, false);
81758c55
ML		 1086 if (amdgpu_sriov_vf(adev))
1087 xgpu_ai_mailbox_put_irq(adev);
220ab9bd
KW		 1088
1089 return 0;
1090}
1091
1092static int soc15_common_suspend(void *handle)
1093{
1094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1095
1096 return soc15_common_hw_fini(adev);
1097}
1098
1099static int soc15_common_resume(void *handle)
1100{
1101 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1102
1103 return soc15_common_hw_init(adev);
1104}
1105
1106static bool soc15_common_is_idle(void *handle)
1107{
1108 return true;
1109}
1110
1111static int soc15_common_wait_for_idle(void *handle)
1112{
1113 return 0;
1114}
1115
1116static int soc15_common_soft_reset(void *handle)
1117{
1118 return 0;
1119}
1120
1121static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1122{
1123 uint32_t def, data;
1124
a5d0f456
KF		 1125 if (adev->asic_type == CHIP_VEGA20) {
1126 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
220ab9bd 1127
a5d0f456
KF		 1128 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1129 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1130 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1131 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1132 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1133 else
1134 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1135 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1136 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1137 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
220ab9bd 1138
a5d0f456
KF		 1139 if (def != data)
1140 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1141 } else {
1142 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1143
1144 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1145 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1146 else
1147 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1148
1149 if (def != data)
1150 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1151 }
220ab9bd
KW		 1152}
1153
1154static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1155{
1156 uint32_t def, data;
1157
1158 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1159
1160 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1161 data &= ~(0x01000000 |
1162 0x02000000 |
1163 0x04000000 |
1164 0x08000000 |
1165 0x10000000 |
1166 0x20000000 |
1167 0x40000000 |
1168 0x80000000);
1169 else
1170 data |= (0x01000000 |
1171 0x02000000 |
1172 0x04000000 |
1173 0x08000000 |
1174 0x10000000 |
1175 0x20000000 |
1176 0x40000000 |
1177 0x80000000);
1178
1179 if (def != data)
1180 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1181}
1182
1183static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1184{
1185 uint32_t def, data;
1186
1187 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1188
1189 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1190 data |= 1;
1191 else
1192 data &= ~1;
1193
1194 if (def != data)
1195 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1196}
1197
1198static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1199 bool enable)
1200{
1201 uint32_t def, data;
1202
1203 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1204
1205 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1206 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1207 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1208 else
1209 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1210 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1211
1212 if (def != data)
1213 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1214}
1215
220ab9bd
KW		 1216static int soc15_common_set_clockgating_state(void *handle,
1217 enum amd_clockgating_state state)
1218{
1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
6e9dc861
ML		 1221 if (amdgpu_sriov_vf(adev))
1222 return 0;
1223
220ab9bd
KW		 1224 switch (adev->asic_type) {
1225 case CHIP_VEGA10:
692069a1 1226 case CHIP_VEGA12:
f980d127 1227 case CHIP_VEGA20:
bf383fb6 1228 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
220ab9bd 1229 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1230 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
220ab9bd
KW		 1231 state == AMD_CG_STATE_GATE ? true : false);
1232 soc15_update_hdp_light_sleep(adev,
1233 state == AMD_CG_STATE_GATE ? true : false);
1234 soc15_update_drm_clock_gating(adev,
1235 state == AMD_CG_STATE_GATE ? true : false);
1236 soc15_update_drm_light_sleep(adev,
1237 state == AMD_CG_STATE_GATE ? true : false);
1238 soc15_update_rom_medium_grain_clock_gating(adev,
1239 state == AMD_CG_STATE_GATE ? true : false);
070706c0 1240 adev->df_funcs->update_medium_grain_clock_gating(adev,
220ab9bd
KW		 1241 state == AMD_CG_STATE_GATE ? true : false);
1242 break;
9e5a9eb4 1243 case CHIP_RAVEN:
bf383fb6 1244 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
9e5a9eb4 1245 state == AMD_CG_STATE_GATE ? true : false);
bf383fb6 1246 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
9e5a9eb4
HR		 1247 state == AMD_CG_STATE_GATE ? true : false);
1248 soc15_update_hdp_light_sleep(adev,
1249 state == AMD_CG_STATE_GATE ? true : false);
1250 soc15_update_drm_clock_gating(adev,
1251 state == AMD_CG_STATE_GATE ? true : false);
1252 soc15_update_drm_light_sleep(adev,
1253 state == AMD_CG_STATE_GATE ? true : false);
1254 soc15_update_rom_medium_grain_clock_gating(adev,
1255 state == AMD_CG_STATE_GATE ? true : false);
1256 break;
220ab9bd
KW		 1257 default:
1258 break;
1259 }
1260 return 0;
1261}
1262
f9abe35c
HR		 1263static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1264{
1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266 int data;
1267
1268 if (amdgpu_sriov_vf(adev))
1269 *flags = 0;
1270
bf383fb6 1271 adev->nbio_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1272
1273 /* AMD_CG_SUPPORT_HDP_LS */
1274 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1275 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1276 *flags |= AMD_CG_SUPPORT_HDP_LS;
1277
1278 /* AMD_CG_SUPPORT_DRM_MGCG */
1279 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1280 if (!(data & 0x01000000))
1281 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1282
1283 /* AMD_CG_SUPPORT_DRM_LS */
1284 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1285 if (data & 0x1)
1286 *flags |= AMD_CG_SUPPORT_DRM_LS;
1287
1288 /* AMD_CG_SUPPORT_ROM_MGCG */
1289 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1290 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1291 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1292
070706c0 1293 adev->df_funcs->get_clockgating_state(adev, flags);
f9abe35c
HR		 1294}
1295
220ab9bd
KW		 1296static int soc15_common_set_powergating_state(void *handle,
1297 enum amd_powergating_state state)
1298{
1299 /* todo */
1300 return 0;
1301}
1302
1303const struct amd_ip_funcs soc15_common_ip_funcs = {
1304 .name = "soc15_common",
1305 .early_init = soc15_common_early_init,
81758c55 1306 .late_init = soc15_common_late_init,
220ab9bd
KW		 1307 .sw_init = soc15_common_sw_init,
1308 .sw_fini = soc15_common_sw_fini,
1309 .hw_init = soc15_common_hw_init,
1310 .hw_fini = soc15_common_hw_fini,
1311 .suspend = soc15_common_suspend,
1312 .resume = soc15_common_resume,
1313 .is_idle = soc15_common_is_idle,
1314 .wait_for_idle = soc15_common_wait_for_idle,
1315 .soft_reset = soc15_common_soft_reset,
1316 .set_clockgating_state = soc15_common_set_clockgating_state,
1317 .set_powergating_state = soc15_common_set_powergating_state,
f9abe35c 1318 .get_clockgating_state= soc15_common_get_clockgating_state,
220ab9bd 1319};
Linux 6.x block layer and io_uring tree(s)