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841686df MB |
1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
248a1d6f | 24 | #include <drm/drmP.h> |
841686df MB |
25 | #include "amdgpu.h" |
26 | #include "amdgpu_pm.h" | |
27 | #include "amdgpu_dpm.h" | |
28 | #include "amdgpu_atombios.h" | |
0bf67185 | 29 | #include "amd_pcie.h" |
689957b1 | 30 | #include "sid.h" |
841686df MB |
31 | #include "r600_dpm.h" |
32 | #include "si_dpm.h" | |
33 | #include "atom.h" | |
34 | #include "../include/pptable.h" | |
35 | #include <linux/math64.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/firmware.h> | |
38 | ||
39 | #define MC_CG_ARB_FREQ_F0 0x0a | |
40 | #define MC_CG_ARB_FREQ_F1 0x0b | |
41 | #define MC_CG_ARB_FREQ_F2 0x0c | |
42 | #define MC_CG_ARB_FREQ_F3 0x0d | |
43 | ||
44 | #define SMC_RAM_END 0x20000 | |
45 | ||
46 | #define SCLK_MIN_DEEPSLEEP_FREQ 1350 | |
47 | ||
48 | ||
49 | /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ | |
50 | #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 | |
51 | #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 | |
52 | #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 | |
53 | #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 | |
54 | #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 | |
55 | #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 | |
56 | ||
57 | #define BIOS_SCRATCH_4 0x5cd | |
58 | ||
8eaf2b1f AD |
59 | MODULE_FIRMWARE("amdgpu/tahiti_smc.bin"); |
60 | MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin"); | |
61 | MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin"); | |
62 | MODULE_FIRMWARE("amdgpu/verde_smc.bin"); | |
63 | MODULE_FIRMWARE("amdgpu/verde_k_smc.bin"); | |
64 | MODULE_FIRMWARE("amdgpu/oland_smc.bin"); | |
65 | MODULE_FIRMWARE("amdgpu/oland_k_smc.bin"); | |
66 | MODULE_FIRMWARE("amdgpu/hainan_smc.bin"); | |
67 | MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin"); | |
68 | MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin"); | |
841686df | 69 | |
b905090d RZ |
70 | static const struct amd_pm_funcs si_dpm_funcs; |
71 | ||
841686df MB |
72 | union power_info { |
73 | struct _ATOM_POWERPLAY_INFO info; | |
74 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
75 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
76 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; | |
77 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; | |
78 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; | |
79 | struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; | |
80 | struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; | |
81 | }; | |
82 | ||
83 | union fan_info { | |
84 | struct _ATOM_PPLIB_FANTABLE fan; | |
85 | struct _ATOM_PPLIB_FANTABLE2 fan2; | |
86 | struct _ATOM_PPLIB_FANTABLE3 fan3; | |
87 | }; | |
88 | ||
89 | union pplib_clock_info { | |
77d318a6 TSD |
90 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; |
91 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; | |
92 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; | |
93 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; | |
94 | struct _ATOM_PPLIB_SI_CLOCK_INFO si; | |
841686df MB |
95 | }; |
96 | ||
a1047777 | 97 | static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = |
841686df MB |
98 | { |
99 | R600_UTC_DFLT_00, | |
100 | R600_UTC_DFLT_01, | |
101 | R600_UTC_DFLT_02, | |
102 | R600_UTC_DFLT_03, | |
103 | R600_UTC_DFLT_04, | |
104 | R600_UTC_DFLT_05, | |
105 | R600_UTC_DFLT_06, | |
106 | R600_UTC_DFLT_07, | |
107 | R600_UTC_DFLT_08, | |
108 | R600_UTC_DFLT_09, | |
109 | R600_UTC_DFLT_10, | |
110 | R600_UTC_DFLT_11, | |
111 | R600_UTC_DFLT_12, | |
112 | R600_UTC_DFLT_13, | |
113 | R600_UTC_DFLT_14, | |
114 | }; | |
115 | ||
a1047777 | 116 | static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = |
841686df MB |
117 | { |
118 | R600_DTC_DFLT_00, | |
119 | R600_DTC_DFLT_01, | |
120 | R600_DTC_DFLT_02, | |
121 | R600_DTC_DFLT_03, | |
122 | R600_DTC_DFLT_04, | |
123 | R600_DTC_DFLT_05, | |
124 | R600_DTC_DFLT_06, | |
125 | R600_DTC_DFLT_07, | |
126 | R600_DTC_DFLT_08, | |
127 | R600_DTC_DFLT_09, | |
128 | R600_DTC_DFLT_10, | |
129 | R600_DTC_DFLT_11, | |
130 | R600_DTC_DFLT_12, | |
131 | R600_DTC_DFLT_13, | |
132 | R600_DTC_DFLT_14, | |
133 | }; | |
134 | ||
135 | static const struct si_cac_config_reg cac_weights_tahiti[] = | |
136 | { | |
137 | { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, | |
138 | { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
139 | { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, | |
140 | { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, | |
141 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
142 | { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
143 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
144 | { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
145 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
146 | { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, | |
147 | { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
148 | { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, | |
149 | { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, | |
150 | { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, | |
151 | { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, | |
152 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
153 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
154 | { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, | |
155 | { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
156 | { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, | |
157 | { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, | |
158 | { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, | |
159 | { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
160 | { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
161 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
162 | { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
163 | { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
164 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
165 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
166 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
167 | { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, | |
168 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
169 | { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
170 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
171 | { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
172 | { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
173 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
174 | { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
175 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
176 | { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, | |
177 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
178 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
179 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
180 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
181 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
182 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
183 | { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
184 | { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
185 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
186 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
187 | { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
188 | { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
189 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
190 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
191 | { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
192 | { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
193 | { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
194 | { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
195 | { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
196 | { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, | |
197 | { 0xFFFFFFFF } | |
198 | }; | |
199 | ||
200 | static const struct si_cac_config_reg lcac_tahiti[] = | |
201 | { | |
202 | { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
203 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
204 | { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
205 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
206 | { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
207 | { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
208 | { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
209 | { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
210 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
211 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
212 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
213 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
214 | { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
215 | { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
216 | { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
217 | { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
218 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
219 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
220 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
221 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
222 | { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
223 | { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
224 | { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
225 | { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
226 | { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
227 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
228 | { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
229 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
230 | { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
231 | { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
232 | { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
233 | { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
234 | { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
235 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
236 | { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
237 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
238 | { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
239 | { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
240 | { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
241 | { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
242 | { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
243 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
244 | { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
245 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
246 | { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
247 | { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
248 | { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, | |
249 | { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
250 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
251 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
252 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
253 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
254 | { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
255 | { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
256 | { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
257 | { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
258 | { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
259 | { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
260 | { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
261 | { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
262 | { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
263 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
264 | { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
265 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
266 | { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
267 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
268 | { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
269 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
270 | { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
271 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
272 | { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
273 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
274 | { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
275 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
276 | { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
277 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
278 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
279 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
280 | { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
281 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
282 | { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
283 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
284 | { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
285 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
286 | { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
287 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
288 | { 0xFFFFFFFF } | |
289 | ||
290 | }; | |
291 | ||
292 | static const struct si_cac_config_reg cac_override_tahiti[] = | |
293 | { | |
294 | { 0xFFFFFFFF } | |
295 | }; | |
296 | ||
297 | static const struct si_powertune_data powertune_data_tahiti = | |
298 | { | |
299 | ((1 << 16) | 27027), | |
300 | 6, | |
301 | 0, | |
302 | 4, | |
303 | 95, | |
304 | { | |
305 | 0UL, | |
306 | 0UL, | |
307 | 4521550UL, | |
308 | 309631529UL, | |
309 | -1270850L, | |
310 | 4513710L, | |
311 | 40 | |
312 | }, | |
313 | 595000000UL, | |
314 | 12, | |
315 | { | |
316 | 0, | |
317 | 0, | |
318 | 0, | |
319 | 0, | |
320 | 0, | |
321 | 0, | |
322 | 0, | |
323 | 0 | |
324 | }, | |
325 | true | |
326 | }; | |
327 | ||
328 | static const struct si_dte_data dte_data_tahiti = | |
329 | { | |
330 | { 1159409, 0, 0, 0, 0 }, | |
331 | { 777, 0, 0, 0, 0 }, | |
332 | 2, | |
333 | 54000, | |
334 | 127000, | |
335 | 25, | |
336 | 2, | |
337 | 10, | |
338 | 13, | |
339 | { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, | |
340 | { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, | |
341 | { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, | |
342 | 85, | |
343 | false | |
344 | }; | |
345 | ||
e5c5304f | 346 | #if 0 |
841686df MB |
347 | static const struct si_dte_data dte_data_tahiti_le = |
348 | { | |
349 | { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, | |
350 | { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, | |
351 | 0x5, | |
352 | 0xAFC8, | |
353 | 0x64, | |
354 | 0x32, | |
355 | 1, | |
356 | 0, | |
357 | 0x10, | |
358 | { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, | |
359 | { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, | |
360 | { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, | |
361 | 85, | |
362 | true | |
363 | }; | |
e5c5304f | 364 | #endif |
841686df MB |
365 | |
366 | static const struct si_dte_data dte_data_tahiti_pro = | |
367 | { | |
368 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
369 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
370 | 5, | |
371 | 45000, | |
372 | 100, | |
373 | 0xA, | |
374 | 1, | |
375 | 0, | |
376 | 0x10, | |
377 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
378 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
379 | { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
380 | 90, | |
381 | true | |
382 | }; | |
383 | ||
384 | static const struct si_dte_data dte_data_new_zealand = | |
385 | { | |
386 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, | |
387 | { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, | |
388 | 0x5, | |
389 | 0xAFC8, | |
390 | 0x69, | |
391 | 0x32, | |
392 | 1, | |
393 | 0, | |
394 | 0x10, | |
395 | { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, | |
396 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
397 | { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, | |
398 | 85, | |
399 | true | |
400 | }; | |
401 | ||
402 | static const struct si_dte_data dte_data_aruba_pro = | |
403 | { | |
404 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
405 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
406 | 5, | |
407 | 45000, | |
408 | 100, | |
409 | 0xA, | |
410 | 1, | |
411 | 0, | |
412 | 0x10, | |
413 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
414 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
415 | { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
416 | 90, | |
417 | true | |
418 | }; | |
419 | ||
420 | static const struct si_dte_data dte_data_malta = | |
421 | { | |
422 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
423 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
424 | 5, | |
425 | 45000, | |
426 | 100, | |
427 | 0xA, | |
428 | 1, | |
429 | 0, | |
430 | 0x10, | |
431 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
432 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
433 | { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
434 | 90, | |
435 | true | |
436 | }; | |
437 | ||
a1047777 | 438 | static const struct si_cac_config_reg cac_weights_pitcairn[] = |
841686df MB |
439 | { |
440 | { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, | |
441 | { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
442 | { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
443 | { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, | |
444 | { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, | |
445 | { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
446 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
447 | { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
448 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
449 | { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, | |
450 | { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, | |
451 | { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, | |
452 | { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, | |
453 | { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, | |
454 | { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
455 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
456 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
457 | { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, | |
458 | { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, | |
459 | { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, | |
460 | { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, | |
461 | { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, | |
462 | { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, | |
463 | { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
464 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
465 | { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, | |
466 | { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, | |
467 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
468 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
469 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
470 | { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, | |
471 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
472 | { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, | |
473 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
474 | { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, | |
475 | { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, | |
476 | { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, | |
477 | { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
478 | { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, | |
479 | { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
480 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
481 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
482 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
483 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
484 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
485 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
486 | { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
487 | { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
488 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
489 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
490 | { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
491 | { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
492 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
493 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
494 | { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
495 | { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
496 | { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
497 | { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
498 | { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
499 | { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, | |
500 | { 0xFFFFFFFF } | |
501 | }; | |
502 | ||
503 | static const struct si_cac_config_reg lcac_pitcairn[] = | |
504 | { | |
505 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
506 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
507 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
508 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
509 | { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
510 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
511 | { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
512 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
513 | { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
514 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
515 | { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
516 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
517 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
518 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
519 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
520 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
521 | { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
522 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
523 | { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
524 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
525 | { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
526 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
527 | { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
528 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
529 | { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
530 | { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
531 | { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
532 | { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
533 | { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
534 | { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
535 | { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
536 | { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
537 | { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
538 | { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
539 | { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
540 | { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
541 | { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
542 | { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
543 | { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
544 | { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
545 | { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
546 | { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
547 | { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
548 | { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
549 | { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
550 | { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
551 | { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
552 | { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
553 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
554 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
555 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
556 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
557 | { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
558 | { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
559 | { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
560 | { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
561 | { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
562 | { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
563 | { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
564 | { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
565 | { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
566 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
567 | { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
568 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
569 | { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
570 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
571 | { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
572 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
573 | { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
574 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
575 | { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
576 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
577 | { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
578 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
579 | { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
580 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
581 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
582 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
583 | { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
584 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
585 | { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
586 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
587 | { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
588 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
589 | { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
590 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
591 | { 0xFFFFFFFF } | |
592 | }; | |
593 | ||
594 | static const struct si_cac_config_reg cac_override_pitcairn[] = | |
595 | { | |
596 | { 0xFFFFFFFF } | |
597 | }; | |
598 | ||
599 | static const struct si_powertune_data powertune_data_pitcairn = | |
600 | { | |
601 | ((1 << 16) | 27027), | |
602 | 5, | |
603 | 0, | |
604 | 6, | |
605 | 100, | |
606 | { | |
607 | 51600000UL, | |
608 | 1800000UL, | |
609 | 7194395UL, | |
610 | 309631529UL, | |
611 | -1270850L, | |
612 | 4513710L, | |
613 | 100 | |
614 | }, | |
615 | 117830498UL, | |
616 | 12, | |
617 | { | |
618 | 0, | |
619 | 0, | |
620 | 0, | |
621 | 0, | |
622 | 0, | |
623 | 0, | |
624 | 0, | |
625 | 0 | |
626 | }, | |
627 | true | |
628 | }; | |
629 | ||
630 | static const struct si_dte_data dte_data_pitcairn = | |
631 | { | |
632 | { 0, 0, 0, 0, 0 }, | |
633 | { 0, 0, 0, 0, 0 }, | |
634 | 0, | |
635 | 0, | |
636 | 0, | |
637 | 0, | |
638 | 0, | |
639 | 0, | |
640 | 0, | |
641 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
642 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
643 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
644 | 0, | |
645 | false | |
646 | }; | |
647 | ||
648 | static const struct si_dte_data dte_data_curacao_xt = | |
649 | { | |
650 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
651 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
652 | 5, | |
653 | 45000, | |
654 | 100, | |
655 | 0xA, | |
656 | 1, | |
657 | 0, | |
658 | 0x10, | |
659 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
660 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
661 | { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
662 | 90, | |
663 | true | |
664 | }; | |
665 | ||
666 | static const struct si_dte_data dte_data_curacao_pro = | |
667 | { | |
668 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
669 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
670 | 5, | |
671 | 45000, | |
672 | 100, | |
673 | 0xA, | |
674 | 1, | |
675 | 0, | |
676 | 0x10, | |
677 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
678 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
679 | { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
680 | 90, | |
681 | true | |
682 | }; | |
683 | ||
684 | static const struct si_dte_data dte_data_neptune_xt = | |
685 | { | |
686 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
687 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
688 | 5, | |
689 | 45000, | |
690 | 100, | |
691 | 0xA, | |
692 | 1, | |
693 | 0, | |
694 | 0x10, | |
695 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
696 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
697 | { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
698 | 90, | |
699 | true | |
700 | }; | |
701 | ||
702 | static const struct si_cac_config_reg cac_weights_chelsea_pro[] = | |
703 | { | |
704 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
705 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
706 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
707 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
708 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
709 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
710 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
711 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
712 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
713 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
714 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
715 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
716 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
717 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
718 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
719 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
720 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
721 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
722 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
723 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
724 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
725 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
726 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
727 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
728 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
729 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
730 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
731 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
732 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
733 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
734 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
735 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
736 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
737 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
738 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
739 | { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, | |
740 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
741 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
742 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
743 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
744 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
745 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
746 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
747 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
748 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
749 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
750 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
751 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
752 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
753 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
754 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
755 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
756 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
757 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
758 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
759 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
760 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
761 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
762 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
763 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
764 | { 0xFFFFFFFF } | |
765 | }; | |
766 | ||
767 | static const struct si_cac_config_reg cac_weights_chelsea_xt[] = | |
768 | { | |
769 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
770 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
771 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
772 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
773 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
774 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
775 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
776 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
777 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
778 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
779 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
780 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
781 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
782 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
783 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
784 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
785 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
786 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
787 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
788 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
789 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
790 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
791 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
792 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
793 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
794 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
795 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
796 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
797 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
798 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
799 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
800 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
801 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
802 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
803 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
804 | { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, | |
805 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
806 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
807 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
808 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
809 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
810 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
811 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
812 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
813 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
814 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
815 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
816 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
817 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
818 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
819 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
820 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
821 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
822 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
823 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
824 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
825 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
826 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
827 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
828 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
829 | { 0xFFFFFFFF } | |
830 | }; | |
831 | ||
832 | static const struct si_cac_config_reg cac_weights_heathrow[] = | |
833 | { | |
834 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
835 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
836 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
837 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
838 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
839 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
840 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
841 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
842 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
843 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
844 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
845 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
846 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
847 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
848 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
849 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
850 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
851 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
852 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
853 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
854 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
855 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
856 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
857 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
858 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
859 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
860 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
861 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
862 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
863 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
864 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
865 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
866 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
867 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
868 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
869 | { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, | |
870 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
871 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
872 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
873 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
874 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
875 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
876 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
877 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
878 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
879 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
880 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
881 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
882 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
883 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
884 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
885 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
886 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
887 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
888 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
889 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
890 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
891 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
892 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
893 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
894 | { 0xFFFFFFFF } | |
895 | }; | |
896 | ||
897 | static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = | |
898 | { | |
899 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
900 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
901 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
902 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
903 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
904 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
905 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
906 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
907 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
908 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
909 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
910 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
911 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
912 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
913 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
914 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
915 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
916 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
917 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
918 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
919 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
920 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
921 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
922 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
923 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
924 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
925 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
926 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
927 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
928 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
929 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
930 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
931 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
932 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
933 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
934 | { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, | |
935 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
936 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
937 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
938 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
939 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
940 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
941 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
942 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
943 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
944 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
945 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
946 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
947 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
948 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
949 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
950 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
951 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
952 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
953 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
954 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
955 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
956 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
957 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
958 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
959 | { 0xFFFFFFFF } | |
960 | }; | |
961 | ||
962 | static const struct si_cac_config_reg cac_weights_cape_verde[] = | |
963 | { | |
964 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
965 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
966 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
967 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
968 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
969 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
970 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
971 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
972 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
973 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
974 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
975 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
976 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
977 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
978 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
979 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
980 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
981 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
982 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
983 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
984 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
985 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
986 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
987 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
988 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
989 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
990 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
991 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
992 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
993 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
994 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
995 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
996 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
997 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
998 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
999 | { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, | |
1000 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1001 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1002 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1003 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
1004 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
1005 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1006 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1007 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1008 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1009 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1010 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1011 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1012 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1013 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1014 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1015 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1016 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1017 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1018 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1019 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1020 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1021 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1022 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1023 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
1024 | { 0xFFFFFFFF } | |
1025 | }; | |
1026 | ||
1027 | static const struct si_cac_config_reg lcac_cape_verde[] = | |
1028 | { | |
1029 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1030 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1031 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1032 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1033 | { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1034 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1035 | { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1036 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1037 | { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1038 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1039 | { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1040 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1041 | { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1042 | { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1043 | { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1044 | { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1045 | { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1046 | { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1047 | { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1048 | { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1049 | { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1050 | { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1051 | { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1052 | { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1053 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1054 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1055 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1056 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1057 | { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1058 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1059 | { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1060 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1061 | { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1062 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1063 | { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1064 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1065 | { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1066 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1067 | { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1068 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1069 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1070 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1071 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1072 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1073 | { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1074 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1075 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1076 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1077 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1078 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1079 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1080 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1081 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1082 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1083 | { 0xFFFFFFFF } | |
1084 | }; | |
1085 | ||
1086 | static const struct si_cac_config_reg cac_override_cape_verde[] = | |
1087 | { | |
1088 | { 0xFFFFFFFF } | |
1089 | }; | |
1090 | ||
1091 | static const struct si_powertune_data powertune_data_cape_verde = | |
1092 | { | |
1093 | ((1 << 16) | 0x6993), | |
1094 | 5, | |
1095 | 0, | |
1096 | 7, | |
1097 | 105, | |
1098 | { | |
1099 | 0UL, | |
1100 | 0UL, | |
1101 | 7194395UL, | |
1102 | 309631529UL, | |
1103 | -1270850L, | |
1104 | 4513710L, | |
1105 | 100 | |
1106 | }, | |
1107 | 117830498UL, | |
1108 | 12, | |
1109 | { | |
1110 | 0, | |
1111 | 0, | |
1112 | 0, | |
1113 | 0, | |
1114 | 0, | |
1115 | 0, | |
1116 | 0, | |
1117 | 0 | |
1118 | }, | |
1119 | true | |
1120 | }; | |
1121 | ||
1122 | static const struct si_dte_data dte_data_cape_verde = | |
1123 | { | |
1124 | { 0, 0, 0, 0, 0 }, | |
1125 | { 0, 0, 0, 0, 0 }, | |
1126 | 0, | |
1127 | 0, | |
1128 | 0, | |
1129 | 0, | |
1130 | 0, | |
1131 | 0, | |
1132 | 0, | |
1133 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1134 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1135 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1136 | 0, | |
1137 | false | |
1138 | }; | |
1139 | ||
1140 | static const struct si_dte_data dte_data_venus_xtx = | |
1141 | { | |
1142 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1143 | { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, | |
1144 | 5, | |
1145 | 55000, | |
1146 | 0x69, | |
1147 | 0xA, | |
1148 | 1, | |
1149 | 0, | |
1150 | 0x3, | |
1151 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1152 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1153 | { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1154 | 90, | |
1155 | true | |
1156 | }; | |
1157 | ||
1158 | static const struct si_dte_data dte_data_venus_xt = | |
1159 | { | |
1160 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1161 | { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, | |
1162 | 5, | |
1163 | 55000, | |
1164 | 0x69, | |
1165 | 0xA, | |
1166 | 1, | |
1167 | 0, | |
1168 | 0x3, | |
1169 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1170 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1171 | { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1172 | 90, | |
1173 | true | |
1174 | }; | |
1175 | ||
1176 | static const struct si_dte_data dte_data_venus_pro = | |
1177 | { | |
1178 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1179 | { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, | |
1180 | 5, | |
1181 | 55000, | |
1182 | 0x69, | |
1183 | 0xA, | |
1184 | 1, | |
1185 | 0, | |
1186 | 0x3, | |
1187 | { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1188 | { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1189 | { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1190 | 90, | |
1191 | true | |
1192 | }; | |
1193 | ||
a1047777 | 1194 | static const struct si_cac_config_reg cac_weights_oland[] = |
841686df MB |
1195 | { |
1196 | { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, | |
1197 | { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
1198 | { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, | |
1199 | { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, | |
1200 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1201 | { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
1202 | { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, | |
1203 | { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, | |
1204 | { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, | |
1205 | { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, | |
1206 | { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, | |
1207 | { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, | |
1208 | { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, | |
1209 | { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
1210 | { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, | |
1211 | { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, | |
1212 | { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, | |
1213 | { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, | |
1214 | { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, | |
1215 | { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, | |
1216 | { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, | |
1217 | { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, | |
1218 | { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, | |
1219 | { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
1220 | { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, | |
1221 | { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1222 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1223 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1224 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1225 | { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1226 | { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1227 | { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1228 | { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, | |
1229 | { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1230 | { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1231 | { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, | |
1232 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1233 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1234 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1235 | { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, | |
1236 | { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, | |
1237 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1238 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1239 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1240 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1241 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1242 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1243 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1244 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1245 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1246 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1247 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1248 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1249 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1250 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1251 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1252 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1253 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1254 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1255 | { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, | |
1256 | { 0xFFFFFFFF } | |
1257 | }; | |
1258 | ||
1259 | static const struct si_cac_config_reg cac_weights_mars_pro[] = | |
1260 | { | |
1261 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1262 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1263 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1264 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1265 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1266 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1267 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1268 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1269 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1270 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1271 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1272 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1273 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1274 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1275 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1276 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1277 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1278 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1279 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1280 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1281 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1282 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1283 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1284 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1285 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1286 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1287 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1288 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1289 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1290 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1291 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1292 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1293 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1294 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1295 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1296 | { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1297 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1298 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1299 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1300 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1301 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1302 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1303 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1304 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1305 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1306 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1307 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1308 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1309 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1310 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1311 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1312 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1313 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1314 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1315 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1316 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1317 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1318 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1319 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1320 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1321 | { 0xFFFFFFFF } | |
1322 | }; | |
1323 | ||
1324 | static const struct si_cac_config_reg cac_weights_mars_xt[] = | |
1325 | { | |
1326 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1327 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1328 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1329 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1330 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1331 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1332 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1333 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1334 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1335 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1336 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1337 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1338 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1339 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1340 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1341 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1342 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1343 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1344 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1345 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1346 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1347 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1348 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1349 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1350 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1351 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1352 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1353 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1354 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1355 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1356 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1357 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1358 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1359 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1360 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1361 | { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, | |
1362 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1363 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1364 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1365 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1366 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1367 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1368 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1369 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1370 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1371 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1372 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1373 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1374 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1375 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1376 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1377 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1378 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1379 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1380 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1381 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1382 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1383 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1384 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1385 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1386 | { 0xFFFFFFFF } | |
1387 | }; | |
1388 | ||
1389 | static const struct si_cac_config_reg cac_weights_oland_pro[] = | |
1390 | { | |
1391 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1392 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1393 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1394 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1395 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1396 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1397 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1398 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1399 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1400 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1401 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1402 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1403 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1404 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1405 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1406 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1407 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1408 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1409 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1410 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1411 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1412 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1413 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1414 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1415 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1416 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1417 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1418 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1419 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1420 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1421 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1422 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1423 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1424 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1425 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1426 | { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, | |
1427 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1428 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1429 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1430 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1431 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1432 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1433 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1434 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1435 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1436 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1437 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1438 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1439 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1440 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1441 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1442 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1443 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1444 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1445 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1446 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1447 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1448 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1449 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1450 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1451 | { 0xFFFFFFFF } | |
1452 | }; | |
1453 | ||
1454 | static const struct si_cac_config_reg cac_weights_oland_xt[] = | |
1455 | { | |
1456 | { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, | |
1457 | { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1458 | { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, | |
1459 | { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, | |
1460 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1461 | { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1462 | { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, | |
1463 | { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, | |
1464 | { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, | |
1465 | { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, | |
1466 | { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, | |
1467 | { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, | |
1468 | { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, | |
1469 | { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, | |
1470 | { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, | |
1471 | { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, | |
1472 | { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, | |
1473 | { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1474 | { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, | |
1475 | { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, | |
1476 | { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, | |
1477 | { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, | |
1478 | { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, | |
1479 | { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1480 | { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, | |
1481 | { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, | |
1482 | { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, | |
1483 | { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1484 | { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1485 | { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1486 | { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, | |
1487 | { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1488 | { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, | |
1489 | { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1490 | { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, | |
1491 | { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, | |
1492 | { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1493 | { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1494 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1495 | { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, | |
1496 | { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, | |
1497 | { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1498 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1499 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1500 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1501 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1502 | { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, | |
1503 | { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, | |
1504 | { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1505 | { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1506 | { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, | |
1507 | { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, | |
1508 | { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1509 | { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1510 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1511 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1512 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1513 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1514 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1515 | { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, | |
1516 | { 0xFFFFFFFF } | |
1517 | }; | |
1518 | ||
1519 | static const struct si_cac_config_reg lcac_oland[] = | |
1520 | { | |
1521 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1522 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1523 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1524 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1525 | { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1526 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1527 | { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1528 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1529 | { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1530 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1531 | { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, | |
1532 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1533 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1534 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1535 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1536 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1537 | { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1538 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1539 | { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1540 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1541 | { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1542 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1543 | { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1544 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1545 | { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1546 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1547 | { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1548 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1549 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1550 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1551 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1552 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1553 | { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1554 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1555 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1556 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1557 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1558 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1559 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1560 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1561 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1562 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1563 | { 0xFFFFFFFF } | |
1564 | }; | |
1565 | ||
1566 | static const struct si_cac_config_reg lcac_mars_pro[] = | |
1567 | { | |
1568 | { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1569 | { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1570 | { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1571 | { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1572 | { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1573 | { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1574 | { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1575 | { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1576 | { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, | |
1577 | { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1578 | { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1579 | { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1580 | { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1581 | { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1582 | { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1583 | { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1584 | { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1585 | { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1586 | { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1587 | { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1588 | { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1589 | { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1590 | { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1591 | { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1592 | { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1593 | { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1594 | { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1595 | { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1596 | { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, | |
1597 | { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1598 | { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1599 | { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1600 | { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1601 | { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1602 | { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1603 | { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1604 | { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1605 | { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1606 | { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1607 | { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1608 | { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1609 | { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, | |
1610 | { 0xFFFFFFFF } | |
1611 | }; | |
1612 | ||
1613 | static const struct si_cac_config_reg cac_override_oland[] = | |
1614 | { | |
1615 | { 0xFFFFFFFF } | |
1616 | }; | |
1617 | ||
1618 | static const struct si_powertune_data powertune_data_oland = | |
1619 | { | |
1620 | ((1 << 16) | 0x6993), | |
1621 | 5, | |
1622 | 0, | |
1623 | 7, | |
1624 | 105, | |
1625 | { | |
1626 | 0UL, | |
1627 | 0UL, | |
1628 | 7194395UL, | |
1629 | 309631529UL, | |
1630 | -1270850L, | |
1631 | 4513710L, | |
1632 | 100 | |
1633 | }, | |
1634 | 117830498UL, | |
1635 | 12, | |
1636 | { | |
1637 | 0, | |
1638 | 0, | |
1639 | 0, | |
1640 | 0, | |
1641 | 0, | |
1642 | 0, | |
1643 | 0, | |
1644 | 0 | |
1645 | }, | |
1646 | true | |
1647 | }; | |
1648 | ||
1649 | static const struct si_powertune_data powertune_data_mars_pro = | |
1650 | { | |
1651 | ((1 << 16) | 0x6993), | |
1652 | 5, | |
1653 | 0, | |
1654 | 7, | |
1655 | 105, | |
1656 | { | |
1657 | 0UL, | |
1658 | 0UL, | |
1659 | 7194395UL, | |
1660 | 309631529UL, | |
1661 | -1270850L, | |
1662 | 4513710L, | |
1663 | 100 | |
1664 | }, | |
1665 | 117830498UL, | |
1666 | 12, | |
1667 | { | |
1668 | 0, | |
1669 | 0, | |
1670 | 0, | |
1671 | 0, | |
1672 | 0, | |
1673 | 0, | |
1674 | 0, | |
1675 | 0 | |
1676 | }, | |
1677 | true | |
1678 | }; | |
1679 | ||
1680 | static const struct si_dte_data dte_data_oland = | |
1681 | { | |
1682 | { 0, 0, 0, 0, 0 }, | |
1683 | { 0, 0, 0, 0, 0 }, | |
1684 | 0, | |
1685 | 0, | |
1686 | 0, | |
1687 | 0, | |
1688 | 0, | |
1689 | 0, | |
1690 | 0, | |
1691 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1692 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1693 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, | |
1694 | 0, | |
1695 | false | |
1696 | }; | |
1697 | ||
1698 | static const struct si_dte_data dte_data_mars_pro = | |
1699 | { | |
1700 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1701 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1702 | 5, | |
1703 | 55000, | |
1704 | 105, | |
1705 | 0xA, | |
1706 | 1, | |
1707 | 0, | |
1708 | 0x10, | |
1709 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
1710 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
1711 | { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1712 | 90, | |
1713 | true | |
1714 | }; | |
1715 | ||
1716 | static const struct si_dte_data dte_data_sun_xt = | |
1717 | { | |
1718 | { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, | |
1719 | { 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1720 | 5, | |
1721 | 55000, | |
1722 | 105, | |
1723 | 0xA, | |
1724 | 1, | |
1725 | 0, | |
1726 | 0x10, | |
1727 | { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, | |
1728 | { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, | |
1729 | { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, | |
1730 | 90, | |
1731 | true | |
1732 | }; | |
1733 | ||
1734 | ||
1735 | static const struct si_cac_config_reg cac_weights_hainan[] = | |
1736 | { | |
1737 | { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, | |
1738 | { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, | |
1739 | { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, | |
1740 | { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, | |
1741 | { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1742 | { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, | |
1743 | { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1744 | { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1745 | { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1746 | { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, | |
1747 | { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, | |
1748 | { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, | |
1749 | { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, | |
1750 | { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1751 | { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, | |
1752 | { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1753 | { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1754 | { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, | |
1755 | { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, | |
1756 | { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, | |
1757 | { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, | |
1758 | { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, | |
1759 | { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, | |
1760 | { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, | |
1761 | { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1762 | { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, | |
1763 | { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, | |
1764 | { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1765 | { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1766 | { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1767 | { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, | |
1768 | { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1769 | { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1770 | { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1771 | { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, | |
1772 | { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, | |
1773 | { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, | |
1774 | { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1775 | { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1776 | { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, | |
1777 | { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1778 | { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, | |
1779 | { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1780 | { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1781 | { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1782 | { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, | |
1783 | { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1784 | { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1785 | { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1786 | { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1787 | { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1788 | { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1789 | { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1790 | { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1791 | { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1792 | { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1793 | { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1794 | { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, | |
1795 | { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, | |
1796 | { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, | |
1797 | { 0xFFFFFFFF } | |
1798 | }; | |
1799 | ||
1800 | static const struct si_powertune_data powertune_data_hainan = | |
1801 | { | |
1802 | ((1 << 16) | 0x6993), | |
1803 | 5, | |
1804 | 0, | |
1805 | 9, | |
1806 | 105, | |
1807 | { | |
1808 | 0UL, | |
1809 | 0UL, | |
1810 | 7194395UL, | |
1811 | 309631529UL, | |
1812 | -1270850L, | |
1813 | 4513710L, | |
1814 | 100 | |
1815 | }, | |
1816 | 117830498UL, | |
1817 | 12, | |
1818 | { | |
1819 | 0, | |
1820 | 0, | |
1821 | 0, | |
1822 | 0, | |
1823 | 0, | |
1824 | 0, | |
1825 | 0, | |
1826 | 0 | |
1827 | }, | |
1828 | true | |
1829 | }; | |
1830 | ||
a1047777 AD |
1831 | static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); |
1832 | static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); | |
1833 | static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); | |
1834 | static struct si_ps *si_get_ps(struct amdgpu_ps *rps); | |
841686df MB |
1835 | |
1836 | static int si_populate_voltage_value(struct amdgpu_device *adev, | |
1837 | const struct atom_voltage_table *table, | |
1838 | u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); | |
1839 | static int si_get_std_voltage_value(struct amdgpu_device *adev, | |
1840 | SISLANDS_SMC_VOLTAGE_VALUE *voltage, | |
1841 | u16 *std_voltage); | |
1842 | static int si_write_smc_soft_register(struct amdgpu_device *adev, | |
1843 | u16 reg_offset, u32 value); | |
1844 | static int si_convert_power_level_to_smc(struct amdgpu_device *adev, | |
1845 | struct rv7xx_pl *pl, | |
1846 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); | |
1847 | static int si_calculate_sclk_params(struct amdgpu_device *adev, | |
1848 | u32 engine_clock, | |
1849 | SISLANDS_SMC_SCLK_VALUE *sclk); | |
1850 | ||
1851 | static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); | |
1852 | static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); | |
841686df MB |
1853 | static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); |
1854 | ||
841686df MB |
1855 | static struct si_power_info *si_get_pi(struct amdgpu_device *adev) |
1856 | { | |
77d318a6 TSD |
1857 | struct si_power_info *pi = adev->pm.dpm.priv; |
1858 | return pi; | |
841686df MB |
1859 | } |
1860 | ||
1861 | static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, | |
1862 | u16 v, s32 t, u32 ileakage, u32 *leakage) | |
1863 | { | |
1864 | s64 kt, kv, leakage_w, i_leakage, vddc; | |
1865 | s64 temperature, t_slope, t_intercept, av, bv, t_ref; | |
1866 | s64 tmp; | |
1867 | ||
1868 | i_leakage = div64_s64(drm_int2fixp(ileakage), 100); | |
1869 | vddc = div64_s64(drm_int2fixp(v), 1000); | |
1870 | temperature = div64_s64(drm_int2fixp(t), 1000); | |
1871 | ||
1872 | t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); | |
1873 | t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); | |
1874 | av = div64_s64(drm_int2fixp(coeff->av), 100000000); | |
1875 | bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); | |
1876 | t_ref = drm_int2fixp(coeff->t_ref); | |
1877 | ||
1878 | tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; | |
1879 | kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); | |
1880 | kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); | |
1881 | kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); | |
1882 | ||
1883 | leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); | |
1884 | ||
1885 | *leakage = drm_fixp2int(leakage_w * 1000); | |
1886 | } | |
1887 | ||
1888 | static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, | |
1889 | const struct ni_leakage_coeffients *coeff, | |
1890 | u16 v, | |
1891 | s32 t, | |
1892 | u32 i_leakage, | |
1893 | u32 *leakage) | |
1894 | { | |
1895 | si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); | |
1896 | } | |
1897 | ||
1898 | static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, | |
1899 | const u32 fixed_kt, u16 v, | |
1900 | u32 ileakage, u32 *leakage) | |
1901 | { | |
1902 | s64 kt, kv, leakage_w, i_leakage, vddc; | |
1903 | ||
1904 | i_leakage = div64_s64(drm_int2fixp(ileakage), 100); | |
1905 | vddc = div64_s64(drm_int2fixp(v), 1000); | |
1906 | ||
1907 | kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); | |
1908 | kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), | |
1909 | drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); | |
1910 | ||
1911 | leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); | |
1912 | ||
1913 | *leakage = drm_fixp2int(leakage_w * 1000); | |
1914 | } | |
1915 | ||
1916 | static void si_calculate_leakage_for_v(struct amdgpu_device *adev, | |
1917 | const struct ni_leakage_coeffients *coeff, | |
1918 | const u32 fixed_kt, | |
1919 | u16 v, | |
1920 | u32 i_leakage, | |
1921 | u32 *leakage) | |
1922 | { | |
1923 | si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); | |
1924 | } | |
1925 | ||
1926 | ||
1927 | static void si_update_dte_from_pl2(struct amdgpu_device *adev, | |
1928 | struct si_dte_data *dte_data) | |
1929 | { | |
1930 | u32 p_limit1 = adev->pm.dpm.tdp_limit; | |
1931 | u32 p_limit2 = adev->pm.dpm.near_tdp_limit; | |
1932 | u32 k = dte_data->k; | |
1933 | u32 t_max = dte_data->max_t; | |
1934 | u32 t_split[5] = { 10, 15, 20, 25, 30 }; | |
1935 | u32 t_0 = dte_data->t0; | |
1936 | u32 i; | |
1937 | ||
1938 | if (p_limit2 != 0 && p_limit2 <= p_limit1) { | |
1939 | dte_data->tdep_count = 3; | |
1940 | ||
1941 | for (i = 0; i < k; i++) { | |
1942 | dte_data->r[i] = | |
1943 | (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / | |
1944 | (p_limit2 * (u32)100); | |
1945 | } | |
1946 | ||
1947 | dte_data->tdep_r[1] = dte_data->r[4] * 2; | |
1948 | ||
1949 | for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { | |
1950 | dte_data->tdep_r[i] = dte_data->r[4]; | |
1951 | } | |
1952 | } else { | |
1953 | DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); | |
1954 | } | |
1955 | } | |
1956 | ||
a1047777 | 1957 | static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) |
841686df | 1958 | { |
77d318a6 | 1959 | struct rv7xx_power_info *pi = adev->pm.dpm.priv; |
841686df | 1960 | |
77d318a6 | 1961 | return pi; |
841686df MB |
1962 | } |
1963 | ||
a1047777 | 1964 | static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) |
841686df | 1965 | { |
77d318a6 | 1966 | struct ni_power_info *pi = adev->pm.dpm.priv; |
841686df | 1967 | |
77d318a6 | 1968 | return pi; |
841686df MB |
1969 | } |
1970 | ||
a1047777 | 1971 | static struct si_ps *si_get_ps(struct amdgpu_ps *aps) |
841686df | 1972 | { |
77d318a6 | 1973 | struct si_ps *ps = aps->ps_priv; |
841686df | 1974 | |
77d318a6 | 1975 | return ps; |
841686df MB |
1976 | } |
1977 | ||
1978 | static void si_initialize_powertune_defaults(struct amdgpu_device *adev) | |
1979 | { | |
1980 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
1981 | struct si_power_info *si_pi = si_get_pi(adev); | |
1982 | bool update_dte_from_pl2 = false; | |
1983 | ||
1984 | if (adev->asic_type == CHIP_TAHITI) { | |
1985 | si_pi->cac_weights = cac_weights_tahiti; | |
1986 | si_pi->lcac_config = lcac_tahiti; | |
1987 | si_pi->cac_override = cac_override_tahiti; | |
1988 | si_pi->powertune_data = &powertune_data_tahiti; | |
1989 | si_pi->dte_data = dte_data_tahiti; | |
1990 | ||
1991 | switch (adev->pdev->device) { | |
1992 | case 0x6798: | |
1993 | si_pi->dte_data.enable_dte_by_default = true; | |
1994 | break; | |
1995 | case 0x6799: | |
1996 | si_pi->dte_data = dte_data_new_zealand; | |
1997 | break; | |
1998 | case 0x6790: | |
1999 | case 0x6791: | |
2000 | case 0x6792: | |
2001 | case 0x679E: | |
2002 | si_pi->dte_data = dte_data_aruba_pro; | |
2003 | update_dte_from_pl2 = true; | |
2004 | break; | |
2005 | case 0x679B: | |
2006 | si_pi->dte_data = dte_data_malta; | |
2007 | update_dte_from_pl2 = true; | |
2008 | break; | |
2009 | case 0x679A: | |
2010 | si_pi->dte_data = dte_data_tahiti_pro; | |
2011 | update_dte_from_pl2 = true; | |
2012 | break; | |
2013 | default: | |
2014 | if (si_pi->dte_data.enable_dte_by_default == true) | |
2015 | DRM_ERROR("DTE is not enabled!\n"); | |
2016 | break; | |
2017 | } | |
2018 | } else if (adev->asic_type == CHIP_PITCAIRN) { | |
c3d98645 TSD |
2019 | si_pi->cac_weights = cac_weights_pitcairn; |
2020 | si_pi->lcac_config = lcac_pitcairn; | |
2021 | si_pi->cac_override = cac_override_pitcairn; | |
2022 | si_pi->powertune_data = &powertune_data_pitcairn; | |
2023 | ||
841686df MB |
2024 | switch (adev->pdev->device) { |
2025 | case 0x6810: | |
2026 | case 0x6818: | |
841686df MB |
2027 | si_pi->dte_data = dte_data_curacao_xt; |
2028 | update_dte_from_pl2 = true; | |
2029 | break; | |
2030 | case 0x6819: | |
2031 | case 0x6811: | |
841686df MB |
2032 | si_pi->dte_data = dte_data_curacao_pro; |
2033 | update_dte_from_pl2 = true; | |
2034 | break; | |
2035 | case 0x6800: | |
2036 | case 0x6806: | |
841686df MB |
2037 | si_pi->dte_data = dte_data_neptune_xt; |
2038 | update_dte_from_pl2 = true; | |
2039 | break; | |
2040 | default: | |
841686df MB |
2041 | si_pi->dte_data = dte_data_pitcairn; |
2042 | break; | |
2043 | } | |
2044 | } else if (adev->asic_type == CHIP_VERDE) { | |
2045 | si_pi->lcac_config = lcac_cape_verde; | |
2046 | si_pi->cac_override = cac_override_cape_verde; | |
2047 | si_pi->powertune_data = &powertune_data_cape_verde; | |
2048 | ||
2049 | switch (adev->pdev->device) { | |
2050 | case 0x683B: | |
2051 | case 0x683F: | |
2052 | case 0x6829: | |
2053 | case 0x6835: | |
2054 | si_pi->cac_weights = cac_weights_cape_verde_pro; | |
2055 | si_pi->dte_data = dte_data_cape_verde; | |
2056 | break; | |
2057 | case 0x682C: | |
2058 | si_pi->cac_weights = cac_weights_cape_verde_pro; | |
2059 | si_pi->dte_data = dte_data_sun_xt; | |
5cb818b8 | 2060 | update_dte_from_pl2 = true; |
841686df MB |
2061 | break; |
2062 | case 0x6825: | |
2063 | case 0x6827: | |
2064 | si_pi->cac_weights = cac_weights_heathrow; | |
2065 | si_pi->dte_data = dte_data_cape_verde; | |
2066 | break; | |
2067 | case 0x6824: | |
2068 | case 0x682D: | |
2069 | si_pi->cac_weights = cac_weights_chelsea_xt; | |
2070 | si_pi->dte_data = dte_data_cape_verde; | |
2071 | break; | |
2072 | case 0x682F: | |
2073 | si_pi->cac_weights = cac_weights_chelsea_pro; | |
2074 | si_pi->dte_data = dte_data_cape_verde; | |
2075 | break; | |
2076 | case 0x6820: | |
2077 | si_pi->cac_weights = cac_weights_heathrow; | |
2078 | si_pi->dte_data = dte_data_venus_xtx; | |
2079 | break; | |
2080 | case 0x6821: | |
2081 | si_pi->cac_weights = cac_weights_heathrow; | |
2082 | si_pi->dte_data = dte_data_venus_xt; | |
2083 | break; | |
2084 | case 0x6823: | |
2085 | case 0x682B: | |
2086 | case 0x6822: | |
2087 | case 0x682A: | |
2088 | si_pi->cac_weights = cac_weights_chelsea_pro; | |
2089 | si_pi->dte_data = dte_data_venus_pro; | |
2090 | break; | |
2091 | default: | |
2092 | si_pi->cac_weights = cac_weights_cape_verde; | |
2093 | si_pi->dte_data = dte_data_cape_verde; | |
2094 | break; | |
2095 | } | |
2096 | } else if (adev->asic_type == CHIP_OLAND) { | |
c3d98645 TSD |
2097 | si_pi->lcac_config = lcac_mars_pro; |
2098 | si_pi->cac_override = cac_override_oland; | |
2099 | si_pi->powertune_data = &powertune_data_mars_pro; | |
2100 | si_pi->dte_data = dte_data_mars_pro; | |
2101 | ||
841686df MB |
2102 | switch (adev->pdev->device) { |
2103 | case 0x6601: | |
2104 | case 0x6621: | |
2105 | case 0x6603: | |
2106 | case 0x6605: | |
2107 | si_pi->cac_weights = cac_weights_mars_pro; | |
841686df MB |
2108 | update_dte_from_pl2 = true; |
2109 | break; | |
2110 | case 0x6600: | |
2111 | case 0x6606: | |
2112 | case 0x6620: | |
2113 | case 0x6604: | |
2114 | si_pi->cac_weights = cac_weights_mars_xt; | |
841686df MB |
2115 | update_dte_from_pl2 = true; |
2116 | break; | |
2117 | case 0x6611: | |
2118 | case 0x6613: | |
2119 | case 0x6608: | |
2120 | si_pi->cac_weights = cac_weights_oland_pro; | |
841686df MB |
2121 | update_dte_from_pl2 = true; |
2122 | break; | |
2123 | case 0x6610: | |
2124 | si_pi->cac_weights = cac_weights_oland_xt; | |
841686df MB |
2125 | update_dte_from_pl2 = true; |
2126 | break; | |
2127 | default: | |
2128 | si_pi->cac_weights = cac_weights_oland; | |
2129 | si_pi->lcac_config = lcac_oland; | |
2130 | si_pi->cac_override = cac_override_oland; | |
2131 | si_pi->powertune_data = &powertune_data_oland; | |
2132 | si_pi->dte_data = dte_data_oland; | |
2133 | break; | |
2134 | } | |
2135 | } else if (adev->asic_type == CHIP_HAINAN) { | |
2136 | si_pi->cac_weights = cac_weights_hainan; | |
2137 | si_pi->lcac_config = lcac_oland; | |
2138 | si_pi->cac_override = cac_override_oland; | |
2139 | si_pi->powertune_data = &powertune_data_hainan; | |
2140 | si_pi->dte_data = dte_data_sun_xt; | |
2141 | update_dte_from_pl2 = true; | |
2142 | } else { | |
2143 | DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); | |
2144 | return; | |
2145 | } | |
2146 | ||
2147 | ni_pi->enable_power_containment = false; | |
2148 | ni_pi->enable_cac = false; | |
2149 | ni_pi->enable_sq_ramping = false; | |
2150 | si_pi->enable_dte = false; | |
2151 | ||
2152 | if (si_pi->powertune_data->enable_powertune_by_default) { | |
77d318a6 | 2153 | ni_pi->enable_power_containment = true; |
841686df MB |
2154 | ni_pi->enable_cac = true; |
2155 | if (si_pi->dte_data.enable_dte_by_default) { | |
2156 | si_pi->enable_dte = true; | |
2157 | if (update_dte_from_pl2) | |
2158 | si_update_dte_from_pl2(adev, &si_pi->dte_data); | |
2159 | ||
2160 | } | |
2161 | ni_pi->enable_sq_ramping = true; | |
2162 | } | |
2163 | ||
2164 | ni_pi->driver_calculate_cac_leakage = true; | |
2165 | ni_pi->cac_configuration_required = true; | |
2166 | ||
2167 | if (ni_pi->cac_configuration_required) { | |
2168 | ni_pi->support_cac_long_term_average = true; | |
2169 | si_pi->dyn_powertune_data.l2_lta_window_size = | |
2170 | si_pi->powertune_data->l2_lta_window_size_default; | |
2171 | si_pi->dyn_powertune_data.lts_truncate = | |
2172 | si_pi->powertune_data->lts_truncate_default; | |
2173 | } else { | |
2174 | ni_pi->support_cac_long_term_average = false; | |
2175 | si_pi->dyn_powertune_data.l2_lta_window_size = 0; | |
2176 | si_pi->dyn_powertune_data.lts_truncate = 0; | |
2177 | } | |
2178 | ||
2179 | si_pi->dyn_powertune_data.disable_uvd_powertune = false; | |
2180 | } | |
2181 | ||
2182 | static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) | |
2183 | { | |
2184 | return 1; | |
2185 | } | |
2186 | ||
2187 | static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) | |
2188 | { | |
2189 | u32 xclk; | |
2190 | u32 wintime; | |
2191 | u32 cac_window; | |
2192 | u32 cac_window_size; | |
2193 | ||
2194 | xclk = amdgpu_asic_get_xclk(adev); | |
2195 | ||
2196 | if (xclk == 0) | |
2197 | return 0; | |
2198 | ||
2199 | cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; | |
2200 | cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); | |
2201 | ||
2202 | wintime = (cac_window_size * 100) / xclk; | |
2203 | ||
2204 | return wintime; | |
2205 | } | |
2206 | ||
2207 | static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) | |
2208 | { | |
2209 | return power_in_watts; | |
2210 | } | |
2211 | ||
2212 | static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, | |
2213 | bool adjust_polarity, | |
2214 | u32 tdp_adjustment, | |
2215 | u32 *tdp_limit, | |
2216 | u32 *near_tdp_limit) | |
2217 | { | |
2218 | u32 adjustment_delta, max_tdp_limit; | |
2219 | ||
2220 | if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) | |
2221 | return -EINVAL; | |
2222 | ||
2223 | max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; | |
2224 | ||
2225 | if (adjust_polarity) { | |
2226 | *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; | |
2227 | *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); | |
2228 | } else { | |
2229 | *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; | |
2230 | adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; | |
2231 | if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) | |
2232 | *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; | |
2233 | else | |
2234 | *near_tdp_limit = 0; | |
2235 | } | |
2236 | ||
2237 | if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) | |
2238 | return -EINVAL; | |
2239 | if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) | |
2240 | return -EINVAL; | |
2241 | ||
2242 | return 0; | |
2243 | } | |
2244 | ||
2245 | static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, | |
2246 | struct amdgpu_ps *amdgpu_state) | |
2247 | { | |
2248 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2249 | struct si_power_info *si_pi = si_get_pi(adev); | |
2250 | ||
2251 | if (ni_pi->enable_power_containment) { | |
2252 | SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; | |
2253 | PP_SIslands_PAPMParameters *papm_parm; | |
2254 | struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; | |
2255 | u32 scaling_factor = si_get_smc_power_scaling_factor(adev); | |
2256 | u32 tdp_limit; | |
2257 | u32 near_tdp_limit; | |
2258 | int ret; | |
2259 | ||
2260 | if (scaling_factor == 0) | |
2261 | return -EINVAL; | |
2262 | ||
2263 | memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); | |
2264 | ||
2265 | ret = si_calculate_adjusted_tdp_limits(adev, | |
2266 | false, /* ??? */ | |
2267 | adev->pm.dpm.tdp_adjustment, | |
2268 | &tdp_limit, | |
2269 | &near_tdp_limit); | |
2270 | if (ret) | |
2271 | return ret; | |
2272 | ||
2273 | smc_table->dpm2Params.TDPLimit = | |
2274 | cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); | |
2275 | smc_table->dpm2Params.NearTDPLimit = | |
2276 | cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); | |
2277 | smc_table->dpm2Params.SafePowerLimit = | |
2278 | cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); | |
2279 | ||
6861c837 AD |
2280 | ret = amdgpu_si_copy_bytes_to_smc(adev, |
2281 | (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + | |
2282 | offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), | |
2283 | (u8 *)(&(smc_table->dpm2Params.TDPLimit)), | |
2284 | sizeof(u32) * 3, | |
2285 | si_pi->sram_end); | |
841686df MB |
2286 | if (ret) |
2287 | return ret; | |
2288 | ||
2289 | if (si_pi->enable_ppm) { | |
2290 | papm_parm = &si_pi->papm_parm; | |
2291 | memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); | |
2292 | papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); | |
2293 | papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); | |
2294 | papm_parm->dGPU_T_Warning = cpu_to_be32(95); | |
2295 | papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); | |
2296 | papm_parm->PlatformPowerLimit = 0xffffffff; | |
2297 | papm_parm->NearTDPLimitPAPM = 0xffffffff; | |
2298 | ||
6861c837 AD |
2299 | ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, |
2300 | (u8 *)papm_parm, | |
2301 | sizeof(PP_SIslands_PAPMParameters), | |
2302 | si_pi->sram_end); | |
841686df MB |
2303 | if (ret) |
2304 | return ret; | |
2305 | } | |
2306 | } | |
2307 | return 0; | |
2308 | } | |
2309 | ||
2310 | static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, | |
2311 | struct amdgpu_ps *amdgpu_state) | |
2312 | { | |
2313 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2314 | struct si_power_info *si_pi = si_get_pi(adev); | |
2315 | ||
2316 | if (ni_pi->enable_power_containment) { | |
2317 | SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; | |
2318 | u32 scaling_factor = si_get_smc_power_scaling_factor(adev); | |
2319 | int ret; | |
2320 | ||
2321 | memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); | |
2322 | ||
2323 | smc_table->dpm2Params.NearTDPLimit = | |
2324 | cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); | |
2325 | smc_table->dpm2Params.SafePowerLimit = | |
2326 | cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); | |
2327 | ||
6861c837 AD |
2328 | ret = amdgpu_si_copy_bytes_to_smc(adev, |
2329 | (si_pi->state_table_start + | |
2330 | offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + | |
2331 | offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), | |
2332 | (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), | |
2333 | sizeof(u32) * 2, | |
2334 | si_pi->sram_end); | |
841686df MB |
2335 | if (ret) |
2336 | return ret; | |
2337 | } | |
2338 | ||
2339 | return 0; | |
2340 | } | |
2341 | ||
2342 | static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, | |
2343 | const u16 prev_std_vddc, | |
2344 | const u16 curr_std_vddc) | |
2345 | { | |
2346 | u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; | |
2347 | u64 prev_vddc = (u64)prev_std_vddc; | |
2348 | u64 curr_vddc = (u64)curr_std_vddc; | |
2349 | u64 pwr_efficiency_ratio, n, d; | |
2350 | ||
2351 | if ((prev_vddc == 0) || (curr_vddc == 0)) | |
2352 | return 0; | |
2353 | ||
2354 | n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); | |
2355 | d = prev_vddc * prev_vddc; | |
2356 | pwr_efficiency_ratio = div64_u64(n, d); | |
2357 | ||
2358 | if (pwr_efficiency_ratio > (u64)0xFFFF) | |
2359 | return 0; | |
2360 | ||
2361 | return (u16)pwr_efficiency_ratio; | |
2362 | } | |
2363 | ||
2364 | static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, | |
2365 | struct amdgpu_ps *amdgpu_state) | |
2366 | { | |
2367 | struct si_power_info *si_pi = si_get_pi(adev); | |
2368 | ||
2369 | if (si_pi->dyn_powertune_data.disable_uvd_powertune && | |
2370 | amdgpu_state->vclk && amdgpu_state->dclk) | |
2371 | return true; | |
2372 | ||
2373 | return false; | |
2374 | } | |
2375 | ||
2376 | struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) | |
2377 | { | |
2378 | struct evergreen_power_info *pi = adev->pm.dpm.priv; | |
2379 | ||
2380 | return pi; | |
2381 | } | |
2382 | ||
2383 | static int si_populate_power_containment_values(struct amdgpu_device *adev, | |
2384 | struct amdgpu_ps *amdgpu_state, | |
2385 | SISLANDS_SMC_SWSTATE *smc_state) | |
2386 | { | |
2387 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
2388 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2389 | struct si_ps *state = si_get_ps(amdgpu_state); | |
2390 | SISLANDS_SMC_VOLTAGE_VALUE vddc; | |
2391 | u32 prev_sclk; | |
2392 | u32 max_sclk; | |
2393 | u32 min_sclk; | |
2394 | u16 prev_std_vddc; | |
2395 | u16 curr_std_vddc; | |
2396 | int i; | |
2397 | u16 pwr_efficiency_ratio; | |
2398 | u8 max_ps_percent; | |
2399 | bool disable_uvd_power_tune; | |
2400 | int ret; | |
2401 | ||
2402 | if (ni_pi->enable_power_containment == false) | |
2403 | return 0; | |
2404 | ||
2405 | if (state->performance_level_count == 0) | |
2406 | return -EINVAL; | |
2407 | ||
2408 | if (smc_state->levelCount != state->performance_level_count) | |
2409 | return -EINVAL; | |
2410 | ||
2411 | disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); | |
2412 | ||
2413 | smc_state->levels[0].dpm2.MaxPS = 0; | |
2414 | smc_state->levels[0].dpm2.NearTDPDec = 0; | |
2415 | smc_state->levels[0].dpm2.AboveSafeInc = 0; | |
2416 | smc_state->levels[0].dpm2.BelowSafeInc = 0; | |
2417 | smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; | |
2418 | ||
2419 | for (i = 1; i < state->performance_level_count; i++) { | |
2420 | prev_sclk = state->performance_levels[i-1].sclk; | |
2421 | max_sclk = state->performance_levels[i].sclk; | |
2422 | if (i == 1) | |
2423 | max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; | |
2424 | else | |
2425 | max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; | |
2426 | ||
2427 | if (prev_sclk > max_sclk) | |
2428 | return -EINVAL; | |
2429 | ||
2430 | if ((max_ps_percent == 0) || | |
2431 | (prev_sclk == max_sclk) || | |
77d318a6 | 2432 | disable_uvd_power_tune) |
841686df | 2433 | min_sclk = max_sclk; |
77d318a6 | 2434 | else if (i == 1) |
841686df | 2435 | min_sclk = prev_sclk; |
77d318a6 | 2436 | else |
841686df | 2437 | min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; |
841686df MB |
2438 | |
2439 | if (min_sclk < state->performance_levels[0].sclk) | |
2440 | min_sclk = state->performance_levels[0].sclk; | |
2441 | ||
2442 | if (min_sclk == 0) | |
2443 | return -EINVAL; | |
2444 | ||
2445 | ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, | |
2446 | state->performance_levels[i-1].vddc, &vddc); | |
2447 | if (ret) | |
2448 | return ret; | |
2449 | ||
2450 | ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); | |
2451 | if (ret) | |
2452 | return ret; | |
2453 | ||
2454 | ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, | |
2455 | state->performance_levels[i].vddc, &vddc); | |
2456 | if (ret) | |
2457 | return ret; | |
2458 | ||
2459 | ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); | |
2460 | if (ret) | |
2461 | return ret; | |
2462 | ||
2463 | pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev, | |
2464 | prev_std_vddc, curr_std_vddc); | |
2465 | ||
2466 | smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); | |
2467 | smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; | |
2468 | smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; | |
2469 | smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; | |
2470 | smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); | |
2471 | } | |
2472 | ||
2473 | return 0; | |
2474 | } | |
2475 | ||
2476 | static int si_populate_sq_ramping_values(struct amdgpu_device *adev, | |
2477 | struct amdgpu_ps *amdgpu_state, | |
2478 | SISLANDS_SMC_SWSTATE *smc_state) | |
2479 | { | |
2480 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2481 | struct si_ps *state = si_get_ps(amdgpu_state); | |
2482 | u32 sq_power_throttle, sq_power_throttle2; | |
2483 | bool enable_sq_ramping = ni_pi->enable_sq_ramping; | |
2484 | int i; | |
2485 | ||
2486 | if (state->performance_level_count == 0) | |
2487 | return -EINVAL; | |
2488 | ||
2489 | if (smc_state->levelCount != state->performance_level_count) | |
2490 | return -EINVAL; | |
2491 | ||
2492 | if (adev->pm.dpm.sq_ramping_threshold == 0) | |
2493 | return -EINVAL; | |
2494 | ||
2495 | if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) | |
2496 | enable_sq_ramping = false; | |
2497 | ||
2498 | if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) | |
2499 | enable_sq_ramping = false; | |
2500 | ||
2501 | if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) | |
2502 | enable_sq_ramping = false; | |
2503 | ||
2504 | if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) | |
2505 | enable_sq_ramping = false; | |
2506 | ||
2507 | if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) | |
2508 | enable_sq_ramping = false; | |
2509 | ||
2510 | for (i = 0; i < state->performance_level_count; i++) { | |
2511 | sq_power_throttle = 0; | |
2512 | sq_power_throttle2 = 0; | |
2513 | ||
2514 | if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && | |
2515 | enable_sq_ramping) { | |
2516 | sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); | |
2517 | sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); | |
2518 | sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); | |
2519 | sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); | |
2520 | sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); | |
2521 | } else { | |
2522 | sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; | |
2523 | sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; | |
2524 | } | |
2525 | ||
2526 | smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); | |
2527 | smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); | |
2528 | } | |
2529 | ||
2530 | return 0; | |
2531 | } | |
2532 | ||
2533 | static int si_enable_power_containment(struct amdgpu_device *adev, | |
2534 | struct amdgpu_ps *amdgpu_new_state, | |
2535 | bool enable) | |
2536 | { | |
2537 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2538 | PPSMC_Result smc_result; | |
2539 | int ret = 0; | |
2540 | ||
2541 | if (ni_pi->enable_power_containment) { | |
2542 | if (enable) { | |
2543 | if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { | |
6861c837 | 2544 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); |
841686df MB |
2545 | if (smc_result != PPSMC_Result_OK) { |
2546 | ret = -EINVAL; | |
2547 | ni_pi->pc_enabled = false; | |
2548 | } else { | |
2549 | ni_pi->pc_enabled = true; | |
2550 | } | |
2551 | } | |
2552 | } else { | |
6861c837 | 2553 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); |
841686df MB |
2554 | if (smc_result != PPSMC_Result_OK) |
2555 | ret = -EINVAL; | |
2556 | ni_pi->pc_enabled = false; | |
2557 | } | |
2558 | } | |
2559 | ||
2560 | return ret; | |
2561 | } | |
2562 | ||
2563 | static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) | |
2564 | { | |
2565 | struct si_power_info *si_pi = si_get_pi(adev); | |
2566 | int ret = 0; | |
2567 | struct si_dte_data *dte_data = &si_pi->dte_data; | |
2568 | Smc_SIslands_DTE_Configuration *dte_tables = NULL; | |
2569 | u32 table_size; | |
2570 | u8 tdep_count; | |
2571 | u32 i; | |
2572 | ||
2573 | if (dte_data == NULL) | |
2574 | si_pi->enable_dte = false; | |
2575 | ||
2576 | if (si_pi->enable_dte == false) | |
2577 | return 0; | |
2578 | ||
2579 | if (dte_data->k <= 0) | |
2580 | return -EINVAL; | |
2581 | ||
2582 | dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); | |
2583 | if (dte_tables == NULL) { | |
2584 | si_pi->enable_dte = false; | |
2585 | return -ENOMEM; | |
2586 | } | |
2587 | ||
2588 | table_size = dte_data->k; | |
2589 | ||
2590 | if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) | |
2591 | table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; | |
2592 | ||
2593 | tdep_count = dte_data->tdep_count; | |
2594 | if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) | |
2595 | tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; | |
2596 | ||
2597 | dte_tables->K = cpu_to_be32(table_size); | |
2598 | dte_tables->T0 = cpu_to_be32(dte_data->t0); | |
2599 | dte_tables->MaxT = cpu_to_be32(dte_data->max_t); | |
2600 | dte_tables->WindowSize = dte_data->window_size; | |
2601 | dte_tables->temp_select = dte_data->temp_select; | |
2602 | dte_tables->DTE_mode = dte_data->dte_mode; | |
2603 | dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); | |
2604 | ||
2605 | if (tdep_count > 0) | |
2606 | table_size--; | |
2607 | ||
2608 | for (i = 0; i < table_size; i++) { | |
2609 | dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); | |
2610 | dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); | |
2611 | } | |
2612 | ||
2613 | dte_tables->Tdep_count = tdep_count; | |
2614 | ||
2615 | for (i = 0; i < (u32)tdep_count; i++) { | |
2616 | dte_tables->T_limits[i] = dte_data->t_limits[i]; | |
2617 | dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); | |
2618 | dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); | |
2619 | } | |
2620 | ||
6861c837 AD |
2621 | ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, |
2622 | (u8 *)dte_tables, | |
2623 | sizeof(Smc_SIslands_DTE_Configuration), | |
2624 | si_pi->sram_end); | |
841686df MB |
2625 | kfree(dte_tables); |
2626 | ||
2627 | return ret; | |
2628 | } | |
2629 | ||
2630 | static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, | |
2631 | u16 *max, u16 *min) | |
2632 | { | |
2633 | struct si_power_info *si_pi = si_get_pi(adev); | |
2634 | struct amdgpu_cac_leakage_table *table = | |
2635 | &adev->pm.dpm.dyn_state.cac_leakage_table; | |
2636 | u32 i; | |
2637 | u32 v0_loadline; | |
2638 | ||
841686df MB |
2639 | if (table == NULL) |
2640 | return -EINVAL; | |
2641 | ||
2642 | *max = 0; | |
2643 | *min = 0xFFFF; | |
2644 | ||
2645 | for (i = 0; i < table->count; i++) { | |
2646 | if (table->entries[i].vddc > *max) | |
2647 | *max = table->entries[i].vddc; | |
2648 | if (table->entries[i].vddc < *min) | |
2649 | *min = table->entries[i].vddc; | |
2650 | } | |
2651 | ||
2652 | if (si_pi->powertune_data->lkge_lut_v0_percent > 100) | |
2653 | return -EINVAL; | |
2654 | ||
2655 | v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; | |
2656 | ||
2657 | if (v0_loadline > 0xFFFFUL) | |
2658 | return -EINVAL; | |
2659 | ||
2660 | *min = (u16)v0_loadline; | |
2661 | ||
2662 | if ((*min > *max) || (*max == 0) || (*min == 0)) | |
2663 | return -EINVAL; | |
2664 | ||
2665 | return 0; | |
2666 | } | |
2667 | ||
2668 | static u16 si_get_cac_std_voltage_step(u16 max, u16 min) | |
2669 | { | |
2670 | return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / | |
2671 | SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; | |
2672 | } | |
2673 | ||
2674 | static int si_init_dte_leakage_table(struct amdgpu_device *adev, | |
2675 | PP_SIslands_CacConfig *cac_tables, | |
2676 | u16 vddc_max, u16 vddc_min, u16 vddc_step, | |
2677 | u16 t0, u16 t_step) | |
2678 | { | |
2679 | struct si_power_info *si_pi = si_get_pi(adev); | |
2680 | u32 leakage; | |
2681 | unsigned int i, j; | |
2682 | s32 t; | |
2683 | u32 smc_leakage; | |
2684 | u32 scaling_factor; | |
2685 | u16 voltage; | |
2686 | ||
2687 | scaling_factor = si_get_smc_power_scaling_factor(adev); | |
2688 | ||
2689 | for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { | |
2690 | t = (1000 * (i * t_step + t0)); | |
2691 | ||
2692 | for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { | |
2693 | voltage = vddc_max - (vddc_step * j); | |
2694 | ||
2695 | si_calculate_leakage_for_v_and_t(adev, | |
2696 | &si_pi->powertune_data->leakage_coefficients, | |
2697 | voltage, | |
2698 | t, | |
2699 | si_pi->dyn_powertune_data.cac_leakage, | |
2700 | &leakage); | |
2701 | ||
2702 | smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; | |
2703 | ||
2704 | if (smc_leakage > 0xFFFF) | |
2705 | smc_leakage = 0xFFFF; | |
2706 | ||
2707 | cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = | |
2708 | cpu_to_be16((u16)smc_leakage); | |
2709 | } | |
2710 | } | |
2711 | return 0; | |
2712 | } | |
2713 | ||
2714 | static int si_init_simplified_leakage_table(struct amdgpu_device *adev, | |
2715 | PP_SIslands_CacConfig *cac_tables, | |
2716 | u16 vddc_max, u16 vddc_min, u16 vddc_step) | |
2717 | { | |
2718 | struct si_power_info *si_pi = si_get_pi(adev); | |
2719 | u32 leakage; | |
2720 | unsigned int i, j; | |
2721 | u32 smc_leakage; | |
2722 | u32 scaling_factor; | |
2723 | u16 voltage; | |
2724 | ||
2725 | scaling_factor = si_get_smc_power_scaling_factor(adev); | |
2726 | ||
2727 | for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { | |
2728 | voltage = vddc_max - (vddc_step * j); | |
2729 | ||
2730 | si_calculate_leakage_for_v(adev, | |
2731 | &si_pi->powertune_data->leakage_coefficients, | |
2732 | si_pi->powertune_data->fixed_kt, | |
2733 | voltage, | |
2734 | si_pi->dyn_powertune_data.cac_leakage, | |
2735 | &leakage); | |
2736 | ||
2737 | smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; | |
2738 | ||
2739 | if (smc_leakage > 0xFFFF) | |
2740 | smc_leakage = 0xFFFF; | |
2741 | ||
2742 | for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) | |
2743 | cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = | |
2744 | cpu_to_be16((u16)smc_leakage); | |
2745 | } | |
2746 | return 0; | |
2747 | } | |
2748 | ||
2749 | static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) | |
2750 | { | |
2751 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2752 | struct si_power_info *si_pi = si_get_pi(adev); | |
2753 | PP_SIslands_CacConfig *cac_tables = NULL; | |
2754 | u16 vddc_max, vddc_min, vddc_step; | |
2755 | u16 t0, t_step; | |
2756 | u32 load_line_slope, reg; | |
2757 | int ret = 0; | |
2758 | u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100; | |
2759 | ||
2760 | if (ni_pi->enable_cac == false) | |
2761 | return 0; | |
2762 | ||
2763 | cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); | |
2764 | if (!cac_tables) | |
2765 | return -ENOMEM; | |
2766 | ||
2767 | reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; | |
2768 | reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); | |
2769 | WREG32(CG_CAC_CTRL, reg); | |
2770 | ||
2771 | si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; | |
2772 | si_pi->dyn_powertune_data.dc_pwr_value = | |
2773 | si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; | |
2774 | si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); | |
2775 | si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; | |
2776 | ||
2777 | si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; | |
2778 | ||
2779 | ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min); | |
2780 | if (ret) | |
2781 | goto done_free; | |
2782 | ||
2783 | vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); | |
2784 | vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); | |
2785 | t_step = 4; | |
2786 | t0 = 60; | |
2787 | ||
2788 | if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) | |
2789 | ret = si_init_dte_leakage_table(adev, cac_tables, | |
2790 | vddc_max, vddc_min, vddc_step, | |
2791 | t0, t_step); | |
2792 | else | |
2793 | ret = si_init_simplified_leakage_table(adev, cac_tables, | |
2794 | vddc_max, vddc_min, vddc_step); | |
2795 | if (ret) | |
2796 | goto done_free; | |
2797 | ||
2798 | load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; | |
2799 | ||
2800 | cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); | |
2801 | cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; | |
2802 | cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; | |
2803 | cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); | |
2804 | cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); | |
2805 | cac_tables->R_LL = cpu_to_be32(load_line_slope); | |
2806 | cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); | |
2807 | cac_tables->calculation_repeats = cpu_to_be32(2); | |
2808 | cac_tables->dc_cac = cpu_to_be32(0); | |
2809 | cac_tables->log2_PG_LKG_SCALE = 12; | |
2810 | cac_tables->cac_temp = si_pi->powertune_data->operating_temp; | |
2811 | cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); | |
2812 | cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); | |
2813 | ||
6861c837 AD |
2814 | ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, |
2815 | (u8 *)cac_tables, | |
2816 | sizeof(PP_SIslands_CacConfig), | |
2817 | si_pi->sram_end); | |
841686df MB |
2818 | |
2819 | if (ret) | |
2820 | goto done_free; | |
2821 | ||
2822 | ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); | |
2823 | ||
2824 | done_free: | |
2825 | if (ret) { | |
2826 | ni_pi->enable_cac = false; | |
2827 | ni_pi->enable_power_containment = false; | |
2828 | } | |
2829 | ||
2830 | kfree(cac_tables); | |
2831 | ||
ad2473af | 2832 | return ret; |
841686df MB |
2833 | } |
2834 | ||
2835 | static int si_program_cac_config_registers(struct amdgpu_device *adev, | |
2836 | const struct si_cac_config_reg *cac_config_regs) | |
2837 | { | |
2838 | const struct si_cac_config_reg *config_regs = cac_config_regs; | |
2839 | u32 data = 0, offset; | |
2840 | ||
2841 | if (!config_regs) | |
2842 | return -EINVAL; | |
2843 | ||
2844 | while (config_regs->offset != 0xFFFFFFFF) { | |
2845 | switch (config_regs->type) { | |
2846 | case SISLANDS_CACCONFIG_CGIND: | |
2847 | offset = SMC_CG_IND_START + config_regs->offset; | |
2848 | if (offset < SMC_CG_IND_END) | |
2849 | data = RREG32_SMC(offset); | |
2850 | break; | |
2851 | default: | |
2852 | data = RREG32(config_regs->offset); | |
2853 | break; | |
2854 | } | |
2855 | ||
2856 | data &= ~config_regs->mask; | |
2857 | data |= ((config_regs->value << config_regs->shift) & config_regs->mask); | |
2858 | ||
2859 | switch (config_regs->type) { | |
2860 | case SISLANDS_CACCONFIG_CGIND: | |
2861 | offset = SMC_CG_IND_START + config_regs->offset; | |
2862 | if (offset < SMC_CG_IND_END) | |
2863 | WREG32_SMC(offset, data); | |
2864 | break; | |
2865 | default: | |
2866 | WREG32(config_regs->offset, data); | |
2867 | break; | |
2868 | } | |
2869 | config_regs++; | |
2870 | } | |
2871 | return 0; | |
2872 | } | |
2873 | ||
2874 | static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) | |
2875 | { | |
2876 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2877 | struct si_power_info *si_pi = si_get_pi(adev); | |
2878 | int ret; | |
2879 | ||
2880 | if ((ni_pi->enable_cac == false) || | |
2881 | (ni_pi->cac_configuration_required == false)) | |
2882 | return 0; | |
2883 | ||
2884 | ret = si_program_cac_config_registers(adev, si_pi->lcac_config); | |
2885 | if (ret) | |
2886 | return ret; | |
2887 | ret = si_program_cac_config_registers(adev, si_pi->cac_override); | |
2888 | if (ret) | |
2889 | return ret; | |
2890 | ret = si_program_cac_config_registers(adev, si_pi->cac_weights); | |
2891 | if (ret) | |
2892 | return ret; | |
2893 | ||
2894 | return 0; | |
2895 | } | |
2896 | ||
2897 | static int si_enable_smc_cac(struct amdgpu_device *adev, | |
2898 | struct amdgpu_ps *amdgpu_new_state, | |
2899 | bool enable) | |
2900 | { | |
2901 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2902 | struct si_power_info *si_pi = si_get_pi(adev); | |
2903 | PPSMC_Result smc_result; | |
2904 | int ret = 0; | |
2905 | ||
2906 | if (ni_pi->enable_cac) { | |
2907 | if (enable) { | |
2908 | if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { | |
2909 | if (ni_pi->support_cac_long_term_average) { | |
6861c837 | 2910 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); |
841686df MB |
2911 | if (smc_result != PPSMC_Result_OK) |
2912 | ni_pi->support_cac_long_term_average = false; | |
2913 | } | |
2914 | ||
6861c837 | 2915 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); |
841686df MB |
2916 | if (smc_result != PPSMC_Result_OK) { |
2917 | ret = -EINVAL; | |
2918 | ni_pi->cac_enabled = false; | |
2919 | } else { | |
2920 | ni_pi->cac_enabled = true; | |
2921 | } | |
2922 | ||
2923 | if (si_pi->enable_dte) { | |
6861c837 | 2924 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); |
841686df MB |
2925 | if (smc_result != PPSMC_Result_OK) |
2926 | ret = -EINVAL; | |
2927 | } | |
2928 | } | |
2929 | } else if (ni_pi->cac_enabled) { | |
2930 | if (si_pi->enable_dte) | |
6861c837 | 2931 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); |
841686df | 2932 | |
6861c837 | 2933 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); |
841686df MB |
2934 | |
2935 | ni_pi->cac_enabled = false; | |
2936 | ||
2937 | if (ni_pi->support_cac_long_term_average) | |
6861c837 | 2938 | smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); |
841686df MB |
2939 | } |
2940 | } | |
2941 | return ret; | |
2942 | } | |
2943 | ||
2944 | static int si_init_smc_spll_table(struct amdgpu_device *adev) | |
2945 | { | |
2946 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
2947 | struct si_power_info *si_pi = si_get_pi(adev); | |
2948 | SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; | |
2949 | SISLANDS_SMC_SCLK_VALUE sclk_params; | |
2950 | u32 fb_div, p_div; | |
2951 | u32 clk_s, clk_v; | |
2952 | u32 sclk = 0; | |
2953 | int ret = 0; | |
2954 | u32 tmp; | |
2955 | int i; | |
2956 | ||
2957 | if (si_pi->spll_table_start == 0) | |
2958 | return -EINVAL; | |
2959 | ||
2960 | spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); | |
2961 | if (spll_table == NULL) | |
2962 | return -ENOMEM; | |
2963 | ||
2964 | for (i = 0; i < 256; i++) { | |
2965 | ret = si_calculate_sclk_params(adev, sclk, &sclk_params); | |
2966 | if (ret) | |
2967 | break; | |
2968 | p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; | |
2969 | fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; | |
2970 | clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; | |
2971 | clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; | |
2972 | ||
2973 | fb_div &= ~0x00001FFF; | |
2974 | fb_div >>= 1; | |
2975 | clk_v >>= 6; | |
2976 | ||
2977 | if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) | |
2978 | ret = -EINVAL; | |
2979 | if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) | |
2980 | ret = -EINVAL; | |
2981 | if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) | |
2982 | ret = -EINVAL; | |
2983 | if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) | |
2984 | ret = -EINVAL; | |
2985 | ||
2986 | if (ret) | |
2987 | break; | |
2988 | ||
2989 | tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | | |
2990 | ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); | |
2991 | spll_table->freq[i] = cpu_to_be32(tmp); | |
2992 | ||
2993 | tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | | |
2994 | ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); | |
2995 | spll_table->ss[i] = cpu_to_be32(tmp); | |
2996 | ||
2997 | sclk += 512; | |
2998 | } | |
2999 | ||
3000 | ||
3001 | if (!ret) | |
6861c837 AD |
3002 | ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, |
3003 | (u8 *)spll_table, | |
3004 | sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), | |
3005 | si_pi->sram_end); | |
841686df MB |
3006 | |
3007 | if (ret) | |
3008 | ni_pi->enable_power_containment = false; | |
3009 | ||
3010 | kfree(spll_table); | |
3011 | ||
3012 | return ret; | |
3013 | } | |
3014 | ||
841686df MB |
3015 | static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, |
3016 | u16 vce_voltage) | |
3017 | { | |
3018 | u16 highest_leakage = 0; | |
3019 | struct si_power_info *si_pi = si_get_pi(adev); | |
3020 | int i; | |
3021 | ||
3022 | for (i = 0; i < si_pi->leakage_voltage.count; i++){ | |
3023 | if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) | |
3024 | highest_leakage = si_pi->leakage_voltage.entries[i].voltage; | |
3025 | } | |
3026 | ||
3027 | if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) | |
3028 | return highest_leakage; | |
3029 | ||
3030 | return vce_voltage; | |
3031 | } | |
3032 | ||
3033 | static int si_get_vce_clock_voltage(struct amdgpu_device *adev, | |
3034 | u32 evclk, u32 ecclk, u16 *voltage) | |
3035 | { | |
3036 | u32 i; | |
3037 | int ret = -EINVAL; | |
3038 | struct amdgpu_vce_clock_voltage_dependency_table *table = | |
3039 | &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; | |
3040 | ||
3041 | if (((evclk == 0) && (ecclk == 0)) || | |
3042 | (table && (table->count == 0))) { | |
3043 | *voltage = 0; | |
3044 | return 0; | |
3045 | } | |
3046 | ||
3047 | for (i = 0; i < table->count; i++) { | |
3048 | if ((evclk <= table->entries[i].evclk) && | |
3049 | (ecclk <= table->entries[i].ecclk)) { | |
3050 | *voltage = table->entries[i].v; | |
3051 | ret = 0; | |
3052 | break; | |
3053 | } | |
3054 | } | |
3055 | ||
3056 | /* if no match return the highest voltage */ | |
3057 | if (ret) | |
3058 | *voltage = table->entries[table->count - 1].v; | |
3059 | ||
3060 | *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage); | |
3061 | ||
3062 | return ret; | |
3063 | } | |
3064 | ||
cfa289fd | 3065 | static bool si_dpm_vblank_too_short(void *handle) |
841686df | 3066 | { |
cfa289fd | 3067 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
77d318a6 TSD |
3068 | u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); |
3069 | /* we never hit the non-gddr5 limit so disable it */ | |
770d13b1 | 3070 | u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; |
841686df | 3071 | |
77d318a6 TSD |
3072 | if (vblank_time < switch_limit) |
3073 | return true; | |
3074 | else | |
3075 | return false; | |
841686df MB |
3076 | |
3077 | } | |
3078 | ||
3079 | static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, | |
3080 | u32 arb_freq_src, u32 arb_freq_dest) | |
3081 | { | |
3082 | u32 mc_arb_dram_timing; | |
3083 | u32 mc_arb_dram_timing2; | |
3084 | u32 burst_time; | |
3085 | u32 mc_cg_config; | |
3086 | ||
3087 | switch (arb_freq_src) { | |
77d318a6 | 3088 | case MC_CG_ARB_FREQ_F0: |
841686df MB |
3089 | mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
3090 | mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); | |
3091 | burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; | |
3092 | break; | |
77d318a6 | 3093 | case MC_CG_ARB_FREQ_F1: |
841686df MB |
3094 | mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); |
3095 | mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); | |
3096 | burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; | |
3097 | break; | |
77d318a6 | 3098 | case MC_CG_ARB_FREQ_F2: |
841686df MB |
3099 | mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); |
3100 | mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); | |
3101 | burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; | |
3102 | break; | |
77d318a6 | 3103 | case MC_CG_ARB_FREQ_F3: |
841686df MB |
3104 | mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); |
3105 | mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); | |
3106 | burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; | |
3107 | break; | |
77d318a6 | 3108 | default: |
841686df MB |
3109 | return -EINVAL; |
3110 | } | |
3111 | ||
3112 | switch (arb_freq_dest) { | |
77d318a6 | 3113 | case MC_CG_ARB_FREQ_F0: |
841686df MB |
3114 | WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); |
3115 | WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); | |
3116 | WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); | |
3117 | break; | |
77d318a6 | 3118 | case MC_CG_ARB_FREQ_F1: |
841686df MB |
3119 | WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); |
3120 | WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); | |
3121 | WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); | |
3122 | break; | |
77d318a6 | 3123 | case MC_CG_ARB_FREQ_F2: |
841686df MB |
3124 | WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); |
3125 | WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); | |
3126 | WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); | |
3127 | break; | |
77d318a6 | 3128 | case MC_CG_ARB_FREQ_F3: |
841686df MB |
3129 | WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); |
3130 | WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); | |
3131 | WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); | |
3132 | break; | |
3133 | default: | |
3134 | return -EINVAL; | |
3135 | } | |
3136 | ||
3137 | mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; | |
3138 | WREG32(MC_CG_CONFIG, mc_cg_config); | |
3139 | WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); | |
3140 | ||
3141 | return 0; | |
3142 | } | |
3143 | ||
3144 | static void ni_update_current_ps(struct amdgpu_device *adev, | |
3145 | struct amdgpu_ps *rps) | |
3146 | { | |
77d318a6 | 3147 | struct si_ps *new_ps = si_get_ps(rps); |
841686df | 3148 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
77d318a6 | 3149 | struct ni_power_info *ni_pi = ni_get_pi(adev); |
841686df MB |
3150 | |
3151 | eg_pi->current_rps = *rps; | |
3152 | ni_pi->current_ps = *new_ps; | |
3153 | eg_pi->current_rps.ps_priv = &ni_pi->current_ps; | |
8c8e2c30 | 3154 | adev->pm.dpm.current_ps = &eg_pi->current_rps; |
841686df MB |
3155 | } |
3156 | ||
3157 | static void ni_update_requested_ps(struct amdgpu_device *adev, | |
3158 | struct amdgpu_ps *rps) | |
3159 | { | |
77d318a6 | 3160 | struct si_ps *new_ps = si_get_ps(rps); |
841686df | 3161 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
77d318a6 | 3162 | struct ni_power_info *ni_pi = ni_get_pi(adev); |
841686df MB |
3163 | |
3164 | eg_pi->requested_rps = *rps; | |
3165 | ni_pi->requested_ps = *new_ps; | |
3166 | eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; | |
8c8e2c30 | 3167 | adev->pm.dpm.requested_ps = &eg_pi->requested_rps; |
841686df MB |
3168 | } |
3169 | ||
3170 | static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, | |
3171 | struct amdgpu_ps *new_ps, | |
3172 | struct amdgpu_ps *old_ps) | |
3173 | { | |
77d318a6 TSD |
3174 | struct si_ps *new_state = si_get_ps(new_ps); |
3175 | struct si_ps *current_state = si_get_ps(old_ps); | |
841686df MB |
3176 | |
3177 | if ((new_ps->vclk == old_ps->vclk) && | |
3178 | (new_ps->dclk == old_ps->dclk)) | |
3179 | return; | |
3180 | ||
3181 | if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= | |
3182 | current_state->performance_levels[current_state->performance_level_count - 1].sclk) | |
3183 | return; | |
3184 | ||
3185 | amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); | |
3186 | } | |
3187 | ||
3188 | static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, | |
3189 | struct amdgpu_ps *new_ps, | |
3190 | struct amdgpu_ps *old_ps) | |
3191 | { | |
77d318a6 TSD |
3192 | struct si_ps *new_state = si_get_ps(new_ps); |
3193 | struct si_ps *current_state = si_get_ps(old_ps); | |
841686df MB |
3194 | |
3195 | if ((new_ps->vclk == old_ps->vclk) && | |
3196 | (new_ps->dclk == old_ps->dclk)) | |
3197 | return; | |
3198 | ||
3199 | if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < | |
3200 | current_state->performance_levels[current_state->performance_level_count - 1].sclk) | |
3201 | return; | |
3202 | ||
3203 | amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); | |
3204 | } | |
3205 | ||
3206 | static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) | |
3207 | { | |
77d318a6 | 3208 | unsigned int i; |
841686df | 3209 | |
77d318a6 TSD |
3210 | for (i = 0; i < table->count; i++) |
3211 | if (voltage <= table->entries[i].value) | |
3212 | return table->entries[i].value; | |
841686df | 3213 | |
77d318a6 | 3214 | return table->entries[table->count - 1].value; |
841686df MB |
3215 | } |
3216 | ||
3217 | static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, | |
77d318a6 | 3218 | u32 max_clock, u32 requested_clock) |
841686df | 3219 | { |
77d318a6 | 3220 | unsigned int i; |
841686df | 3221 | |
77d318a6 TSD |
3222 | if ((clocks == NULL) || (clocks->count == 0)) |
3223 | return (requested_clock < max_clock) ? requested_clock : max_clock; | |
841686df | 3224 | |
77d318a6 TSD |
3225 | for (i = 0; i < clocks->count; i++) { |
3226 | if (clocks->values[i] >= requested_clock) | |
3227 | return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; | |
3228 | } | |
841686df | 3229 | |
77d318a6 TSD |
3230 | return (clocks->values[clocks->count - 1] < max_clock) ? |
3231 | clocks->values[clocks->count - 1] : max_clock; | |
841686df MB |
3232 | } |
3233 | ||
3234 | static u32 btc_get_valid_mclk(struct amdgpu_device *adev, | |
77d318a6 | 3235 | u32 max_mclk, u32 requested_mclk) |
841686df | 3236 | { |
77d318a6 TSD |
3237 | return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, |
3238 | max_mclk, requested_mclk); | |
841686df MB |
3239 | } |
3240 | ||
3241 | static u32 btc_get_valid_sclk(struct amdgpu_device *adev, | |
77d318a6 | 3242 | u32 max_sclk, u32 requested_sclk) |
841686df | 3243 | { |
77d318a6 TSD |
3244 | return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, |
3245 | max_sclk, requested_sclk); | |
841686df MB |
3246 | } |
3247 | ||
a1047777 AD |
3248 | static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, |
3249 | u32 *max_clock) | |
841686df | 3250 | { |
77d318a6 | 3251 | u32 i, clock = 0; |
841686df | 3252 | |
77d318a6 TSD |
3253 | if ((table == NULL) || (table->count == 0)) { |
3254 | *max_clock = clock; | |
3255 | return; | |
3256 | } | |
841686df | 3257 | |
77d318a6 TSD |
3258 | for (i = 0; i < table->count; i++) { |
3259 | if (clock < table->entries[i].clk) | |
3260 | clock = table->entries[i].clk; | |
3261 | } | |
3262 | *max_clock = clock; | |
841686df MB |
3263 | } |
3264 | ||
3265 | static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, | |
77d318a6 | 3266 | u32 clock, u16 max_voltage, u16 *voltage) |
841686df | 3267 | { |
77d318a6 | 3268 | u32 i; |
841686df | 3269 | |
77d318a6 TSD |
3270 | if ((table == NULL) || (table->count == 0)) |
3271 | return; | |
841686df | 3272 | |
77d318a6 TSD |
3273 | for (i= 0; i < table->count; i++) { |
3274 | if (clock <= table->entries[i].clk) { | |
3275 | if (*voltage < table->entries[i].v) | |
3276 | *voltage = (u16)((table->entries[i].v < max_voltage) ? | |
3277 | table->entries[i].v : max_voltage); | |
3278 | return; | |
3279 | } | |
3280 | } | |
841686df | 3281 | |
77d318a6 | 3282 | *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; |
841686df MB |
3283 | } |
3284 | ||
3285 | static void btc_adjust_clock_combinations(struct amdgpu_device *adev, | |
77d318a6 TSD |
3286 | const struct amdgpu_clock_and_voltage_limits *max_limits, |
3287 | struct rv7xx_pl *pl) | |
841686df MB |
3288 | { |
3289 | ||
77d318a6 TSD |
3290 | if ((pl->mclk == 0) || (pl->sclk == 0)) |
3291 | return; | |
841686df | 3292 | |
77d318a6 TSD |
3293 | if (pl->mclk == pl->sclk) |
3294 | return; | |
841686df | 3295 | |
77d318a6 TSD |
3296 | if (pl->mclk > pl->sclk) { |
3297 | if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) | |
3298 | pl->sclk = btc_get_valid_sclk(adev, | |
3299 | max_limits->sclk, | |
3300 | (pl->mclk + | |
3301 | (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / | |
3302 | adev->pm.dpm.dyn_state.mclk_sclk_ratio); | |
3303 | } else { | |
3304 | if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) | |
3305 | pl->mclk = btc_get_valid_mclk(adev, | |
3306 | max_limits->mclk, | |
3307 | pl->sclk - | |
3308 | adev->pm.dpm.dyn_state.sclk_mclk_delta); | |
3309 | } | |
841686df MB |
3310 | } |
3311 | ||
3312 | static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, | |
77d318a6 TSD |
3313 | u16 max_vddc, u16 max_vddci, |
3314 | u16 *vddc, u16 *vddci) | |
3315 | { | |
3316 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
3317 | u16 new_voltage; | |
3318 | ||
3319 | if ((0 == *vddc) || (0 == *vddci)) | |
3320 | return; | |
3321 | ||
3322 | if (*vddc > *vddci) { | |
3323 | if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { | |
3324 | new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, | |
3325 | (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); | |
3326 | *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; | |
3327 | } | |
3328 | } else { | |
3329 | if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { | |
3330 | new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, | |
3331 | (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); | |
3332 | *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; | |
3333 | } | |
3334 | } | |
841686df MB |
3335 | } |
3336 | ||
841686df MB |
3337 | static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, |
3338 | u32 *p, u32 *u) | |
3339 | { | |
3340 | u32 b_c = 0; | |
3341 | u32 i_c; | |
3342 | u32 tmp; | |
3343 | ||
3344 | i_c = (i * r_c) / 100; | |
3345 | tmp = i_c >> p_b; | |
3346 | ||
3347 | while (tmp) { | |
3348 | b_c++; | |
3349 | tmp >>= 1; | |
3350 | } | |
3351 | ||
3352 | *u = (b_c + 1) / 2; | |
3353 | *p = i_c / (1 << (2 * (*u))); | |
3354 | } | |
3355 | ||
3356 | static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) | |
3357 | { | |
3358 | u32 k, a, ah, al; | |
3359 | u32 t1; | |
3360 | ||
3361 | if ((fl == 0) || (fh == 0) || (fl > fh)) | |
3362 | return -EINVAL; | |
3363 | ||
3364 | k = (100 * fh) / fl; | |
3365 | t1 = (t * (k - 100)); | |
3366 | a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); | |
3367 | a = (a + 5) / 10; | |
3368 | ah = ((a * t) + 5000) / 10000; | |
3369 | al = a - ah; | |
3370 | ||
3371 | *th = t - ah; | |
3372 | *tl = t + al; | |
3373 | ||
3374 | return 0; | |
3375 | } | |
3376 | ||
3377 | static bool r600_is_uvd_state(u32 class, u32 class2) | |
3378 | { | |
3379 | if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | |
3380 | return true; | |
3381 | if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) | |
3382 | return true; | |
3383 | if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) | |
3384 | return true; | |
3385 | if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) | |
3386 | return true; | |
3387 | if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) | |
3388 | return true; | |
3389 | return false; | |
3390 | } | |
3391 | ||
3392 | static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) | |
3393 | { | |
3394 | return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); | |
3395 | } | |
3396 | ||
3397 | static void rv770_get_max_vddc(struct amdgpu_device *adev) | |
3398 | { | |
3399 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
3400 | u16 vddc; | |
3401 | ||
3402 | if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) | |
3403 | pi->max_vddc = 0; | |
3404 | else | |
3405 | pi->max_vddc = vddc; | |
3406 | } | |
3407 | ||
3408 | static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) | |
3409 | { | |
3410 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
3411 | struct amdgpu_atom_ss ss; | |
3412 | ||
3413 | pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, | |
3414 | ASIC_INTERNAL_ENGINE_SS, 0); | |
3415 | pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, | |
3416 | ASIC_INTERNAL_MEMORY_SS, 0); | |
3417 | ||
3418 | if (pi->sclk_ss || pi->mclk_ss) | |
3419 | pi->dynamic_ss = true; | |
3420 | else | |
3421 | pi->dynamic_ss = false; | |
3422 | } | |
3423 | ||
3424 | ||
3425 | static void si_apply_state_adjust_rules(struct amdgpu_device *adev, | |
3426 | struct amdgpu_ps *rps) | |
3427 | { | |
3428 | struct si_ps *ps = si_get_ps(rps); | |
3429 | struct amdgpu_clock_and_voltage_limits *max_limits; | |
3430 | bool disable_mclk_switching = false; | |
3431 | bool disable_sclk_switching = false; | |
3432 | u32 mclk, sclk; | |
3433 | u16 vddc, vddci, min_vce_voltage = 0; | |
3434 | u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; | |
3435 | u32 max_sclk = 0, max_mclk = 0; | |
3436 | int i; | |
841686df | 3437 | |
85d2fce6 | 3438 | if (adev->asic_type == CHIP_HAINAN) { |
71451bdf AD |
3439 | if ((adev->pdev->revision == 0x81) || |
3440 | (adev->pdev->revision == 0x83) || | |
3441 | (adev->pdev->revision == 0xC3) || | |
3442 | (adev->pdev->device == 0x6664) || | |
3443 | (adev->pdev->device == 0x6665) || | |
3444 | (adev->pdev->device == 0x6667)) { | |
3445 | max_sclk = 75000; | |
71451bdf | 3446 | } |
f2e5262f AD |
3447 | if ((adev->pdev->revision == 0xC3) || |
3448 | (adev->pdev->device == 0x6665)) { | |
3449 | max_sclk = 60000; | |
3450 | max_mclk = 80000; | |
3451 | } | |
18a8de1b | 3452 | } else if (adev->asic_type == CHIP_OLAND) { |
e11ddff6 AD |
3453 | if ((adev->pdev->revision == 0xC7) || |
3454 | (adev->pdev->revision == 0x80) || | |
3455 | (adev->pdev->revision == 0x81) || | |
3456 | (adev->pdev->revision == 0x83) || | |
3457 | (adev->pdev->revision == 0x87) || | |
3458 | (adev->pdev->device == 0x6604) || | |
3459 | (adev->pdev->device == 0x6605)) { | |
18a8de1b AD |
3460 | max_sclk = 75000; |
3461 | } | |
71451bdf | 3462 | } |
841686df MB |
3463 | |
3464 | if (rps->vce_active) { | |
3465 | rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; | |
3466 | rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; | |
3467 | si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, | |
3468 | &min_vce_voltage); | |
3469 | } else { | |
3470 | rps->evclk = 0; | |
3471 | rps->ecclk = 0; | |
3472 | } | |
3473 | ||
3474 | if ((adev->pm.dpm.new_active_crtc_count > 1) || | |
3475 | si_dpm_vblank_too_short(adev)) | |
3476 | disable_mclk_switching = true; | |
3477 | ||
3478 | if (rps->vclk || rps->dclk) { | |
3479 | disable_mclk_switching = true; | |
3480 | disable_sclk_switching = true; | |
3481 | } | |
3482 | ||
600ae890 | 3483 | if (adev->pm.ac_power) |
841686df MB |
3484 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; |
3485 | else | |
3486 | max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; | |
3487 | ||
3488 | for (i = ps->performance_level_count - 2; i >= 0; i--) { | |
3489 | if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) | |
3490 | ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; | |
3491 | } | |
600ae890 | 3492 | if (adev->pm.ac_power == false) { |
841686df MB |
3493 | for (i = 0; i < ps->performance_level_count; i++) { |
3494 | if (ps->performance_levels[i].mclk > max_limits->mclk) | |
3495 | ps->performance_levels[i].mclk = max_limits->mclk; | |
3496 | if (ps->performance_levels[i].sclk > max_limits->sclk) | |
3497 | ps->performance_levels[i].sclk = max_limits->sclk; | |
3498 | if (ps->performance_levels[i].vddc > max_limits->vddc) | |
3499 | ps->performance_levels[i].vddc = max_limits->vddc; | |
3500 | if (ps->performance_levels[i].vddci > max_limits->vddci) | |
3501 | ps->performance_levels[i].vddci = max_limits->vddci; | |
3502 | } | |
3503 | } | |
3504 | ||
3505 | /* limit clocks to max supported clocks based on voltage dependency tables */ | |
3506 | btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, | |
3507 | &max_sclk_vddc); | |
3508 | btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, | |
3509 | &max_mclk_vddci); | |
3510 | btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, | |
3511 | &max_mclk_vddc); | |
3512 | ||
3513 | for (i = 0; i < ps->performance_level_count; i++) { | |
3514 | if (max_sclk_vddc) { | |
3515 | if (ps->performance_levels[i].sclk > max_sclk_vddc) | |
3516 | ps->performance_levels[i].sclk = max_sclk_vddc; | |
3517 | } | |
3518 | if (max_mclk_vddci) { | |
3519 | if (ps->performance_levels[i].mclk > max_mclk_vddci) | |
3520 | ps->performance_levels[i].mclk = max_mclk_vddci; | |
3521 | } | |
3522 | if (max_mclk_vddc) { | |
3523 | if (ps->performance_levels[i].mclk > max_mclk_vddc) | |
3524 | ps->performance_levels[i].mclk = max_mclk_vddc; | |
3525 | } | |
3526 | if (max_mclk) { | |
3527 | if (ps->performance_levels[i].mclk > max_mclk) | |
3528 | ps->performance_levels[i].mclk = max_mclk; | |
3529 | } | |
3530 | if (max_sclk) { | |
3531 | if (ps->performance_levels[i].sclk > max_sclk) | |
3532 | ps->performance_levels[i].sclk = max_sclk; | |
3533 | } | |
3534 | } | |
3535 | ||
3536 | /* XXX validate the min clocks required for display */ | |
3537 | ||
3538 | if (disable_mclk_switching) { | |
3539 | mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; | |
3540 | vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; | |
3541 | } else { | |
3542 | mclk = ps->performance_levels[0].mclk; | |
3543 | vddci = ps->performance_levels[0].vddci; | |
3544 | } | |
3545 | ||
3546 | if (disable_sclk_switching) { | |
3547 | sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; | |
3548 | vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; | |
3549 | } else { | |
3550 | sclk = ps->performance_levels[0].sclk; | |
3551 | vddc = ps->performance_levels[0].vddc; | |
3552 | } | |
3553 | ||
3554 | if (rps->vce_active) { | |
3555 | if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) | |
3556 | sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; | |
3557 | if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) | |
3558 | mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; | |
3559 | } | |
3560 | ||
3561 | /* adjusted low state */ | |
3562 | ps->performance_levels[0].sclk = sclk; | |
3563 | ps->performance_levels[0].mclk = mclk; | |
3564 | ps->performance_levels[0].vddc = vddc; | |
3565 | ps->performance_levels[0].vddci = vddci; | |
3566 | ||
3567 | if (disable_sclk_switching) { | |
3568 | sclk = ps->performance_levels[0].sclk; | |
3569 | for (i = 1; i < ps->performance_level_count; i++) { | |
3570 | if (sclk < ps->performance_levels[i].sclk) | |
3571 | sclk = ps->performance_levels[i].sclk; | |
3572 | } | |
3573 | for (i = 0; i < ps->performance_level_count; i++) { | |
3574 | ps->performance_levels[i].sclk = sclk; | |
3575 | ps->performance_levels[i].vddc = vddc; | |
3576 | } | |
3577 | } else { | |
3578 | for (i = 1; i < ps->performance_level_count; i++) { | |
3579 | if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) | |
3580 | ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; | |
3581 | if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) | |
3582 | ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; | |
3583 | } | |
3584 | } | |
3585 | ||
3586 | if (disable_mclk_switching) { | |
3587 | mclk = ps->performance_levels[0].mclk; | |
3588 | for (i = 1; i < ps->performance_level_count; i++) { | |
3589 | if (mclk < ps->performance_levels[i].mclk) | |
3590 | mclk = ps->performance_levels[i].mclk; | |
3591 | } | |
3592 | for (i = 0; i < ps->performance_level_count; i++) { | |
3593 | ps->performance_levels[i].mclk = mclk; | |
3594 | ps->performance_levels[i].vddci = vddci; | |
3595 | } | |
3596 | } else { | |
3597 | for (i = 1; i < ps->performance_level_count; i++) { | |
3598 | if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) | |
3599 | ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; | |
3600 | if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) | |
3601 | ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; | |
3602 | } | |
3603 | } | |
3604 | ||
77d318a6 TSD |
3605 | for (i = 0; i < ps->performance_level_count; i++) |
3606 | btc_adjust_clock_combinations(adev, max_limits, | |
3607 | &ps->performance_levels[i]); | |
841686df MB |
3608 | |
3609 | for (i = 0; i < ps->performance_level_count; i++) { | |
3610 | if (ps->performance_levels[i].vddc < min_vce_voltage) | |
3611 | ps->performance_levels[i].vddc = min_vce_voltage; | |
3612 | btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, | |
3613 | ps->performance_levels[i].sclk, | |
3614 | max_limits->vddc, &ps->performance_levels[i].vddc); | |
3615 | btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, | |
3616 | ps->performance_levels[i].mclk, | |
3617 | max_limits->vddci, &ps->performance_levels[i].vddci); | |
3618 | btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, | |
3619 | ps->performance_levels[i].mclk, | |
3620 | max_limits->vddc, &ps->performance_levels[i].vddc); | |
3621 | btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, | |
3622 | adev->clock.current_dispclk, | |
3623 | max_limits->vddc, &ps->performance_levels[i].vddc); | |
3624 | } | |
3625 | ||
3626 | for (i = 0; i < ps->performance_level_count; i++) { | |
3627 | btc_apply_voltage_delta_rules(adev, | |
3628 | max_limits->vddc, max_limits->vddci, | |
3629 | &ps->performance_levels[i].vddc, | |
3630 | &ps->performance_levels[i].vddci); | |
3631 | } | |
3632 | ||
3633 | ps->dc_compatible = true; | |
3634 | for (i = 0; i < ps->performance_level_count; i++) { | |
3635 | if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) | |
3636 | ps->dc_compatible = false; | |
3637 | } | |
3638 | } | |
3639 | ||
3640 | #if 0 | |
3641 | static int si_read_smc_soft_register(struct amdgpu_device *adev, | |
3642 | u16 reg_offset, u32 *value) | |
3643 | { | |
3644 | struct si_power_info *si_pi = si_get_pi(adev); | |
3645 | ||
6861c837 AD |
3646 | return amdgpu_si_read_smc_sram_dword(adev, |
3647 | si_pi->soft_regs_start + reg_offset, value, | |
3648 | si_pi->sram_end); | |
841686df MB |
3649 | } |
3650 | #endif | |
3651 | ||
3652 | static int si_write_smc_soft_register(struct amdgpu_device *adev, | |
3653 | u16 reg_offset, u32 value) | |
3654 | { | |
3655 | struct si_power_info *si_pi = si_get_pi(adev); | |
3656 | ||
6861c837 AD |
3657 | return amdgpu_si_write_smc_sram_dword(adev, |
3658 | si_pi->soft_regs_start + reg_offset, | |
3659 | value, si_pi->sram_end); | |
841686df MB |
3660 | } |
3661 | ||
3662 | static bool si_is_special_1gb_platform(struct amdgpu_device *adev) | |
3663 | { | |
3664 | bool ret = false; | |
3665 | u32 tmp, width, row, column, bank, density; | |
3666 | bool is_memory_gddr5, is_special; | |
3667 | ||
3668 | tmp = RREG32(MC_SEQ_MISC0); | |
3669 | is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); | |
3670 | is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) | |
3671 | & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); | |
3672 | ||
3673 | WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); | |
3674 | width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; | |
3675 | ||
3676 | tmp = RREG32(MC_ARB_RAMCFG); | |
3677 | row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; | |
3678 | column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; | |
3679 | bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; | |
3680 | ||
3681 | density = (1 << (row + column - 20 + bank)) * width; | |
3682 | ||
3683 | if ((adev->pdev->device == 0x6819) && | |
3684 | is_memory_gddr5 && is_special && (density == 0x400)) | |
3685 | ret = true; | |
3686 | ||
3687 | return ret; | |
3688 | } | |
3689 | ||
3690 | static void si_get_leakage_vddc(struct amdgpu_device *adev) | |
3691 | { | |
3692 | struct si_power_info *si_pi = si_get_pi(adev); | |
3693 | u16 vddc, count = 0; | |
3694 | int i, ret; | |
3695 | ||
3696 | for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { | |
3697 | ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); | |
3698 | ||
3699 | if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { | |
3700 | si_pi->leakage_voltage.entries[count].voltage = vddc; | |
3701 | si_pi->leakage_voltage.entries[count].leakage_index = | |
3702 | SISLANDS_LEAKAGE_INDEX0 + i; | |
3703 | count++; | |
3704 | } | |
3705 | } | |
3706 | si_pi->leakage_voltage.count = count; | |
3707 | } | |
3708 | ||
3709 | static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, | |
3710 | u32 index, u16 *leakage_voltage) | |
3711 | { | |
3712 | struct si_power_info *si_pi = si_get_pi(adev); | |
3713 | int i; | |
3714 | ||
3715 | if (leakage_voltage == NULL) | |
3716 | return -EINVAL; | |
3717 | ||
3718 | if ((index & 0xff00) != 0xff00) | |
3719 | return -EINVAL; | |
3720 | ||
3721 | if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) | |
3722 | return -EINVAL; | |
3723 | ||
3724 | if (index < SISLANDS_LEAKAGE_INDEX0) | |
3725 | return -EINVAL; | |
3726 | ||
3727 | for (i = 0; i < si_pi->leakage_voltage.count; i++) { | |
3728 | if (si_pi->leakage_voltage.entries[i].leakage_index == index) { | |
3729 | *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; | |
3730 | return 0; | |
3731 | } | |
3732 | } | |
3733 | return -EAGAIN; | |
3734 | } | |
3735 | ||
3736 | static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) | |
3737 | { | |
3738 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
3739 | bool want_thermal_protection; | |
3740 | enum amdgpu_dpm_event_src dpm_event_src; | |
3741 | ||
3742 | switch (sources) { | |
3743 | case 0: | |
3744 | default: | |
3745 | want_thermal_protection = false; | |
77d318a6 | 3746 | break; |
841686df MB |
3747 | case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL): |
3748 | want_thermal_protection = true; | |
3749 | dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL; | |
3750 | break; | |
3751 | case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL): | |
3752 | want_thermal_protection = true; | |
3753 | dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL; | |
3754 | break; | |
3755 | case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | | |
3756 | (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)): | |
3757 | want_thermal_protection = true; | |
3758 | dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; | |
3759 | break; | |
3760 | } | |
3761 | ||
3762 | if (want_thermal_protection) { | |
3763 | WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); | |
3764 | if (pi->thermal_protection) | |
3765 | WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); | |
3766 | } else { | |
3767 | WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); | |
3768 | } | |
3769 | } | |
3770 | ||
3771 | static void si_enable_auto_throttle_source(struct amdgpu_device *adev, | |
3772 | enum amdgpu_dpm_auto_throttle_src source, | |
3773 | bool enable) | |
3774 | { | |
3775 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
3776 | ||
3777 | if (enable) { | |
3778 | if (!(pi->active_auto_throttle_sources & (1 << source))) { | |
3779 | pi->active_auto_throttle_sources |= 1 << source; | |
3780 | si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); | |
3781 | } | |
3782 | } else { | |
3783 | if (pi->active_auto_throttle_sources & (1 << source)) { | |
3784 | pi->active_auto_throttle_sources &= ~(1 << source); | |
3785 | si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); | |
3786 | } | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | static void si_start_dpm(struct amdgpu_device *adev) | |
3791 | { | |
3792 | WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); | |
3793 | } | |
3794 | ||
3795 | static void si_stop_dpm(struct amdgpu_device *adev) | |
3796 | { | |
3797 | WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); | |
3798 | } | |
3799 | ||
3800 | static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) | |
3801 | { | |
3802 | if (enable) | |
3803 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); | |
3804 | else | |
3805 | WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); | |
3806 | ||
3807 | } | |
3808 | ||
3809 | #if 0 | |
3810 | static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, | |
3811 | u32 thermal_level) | |
3812 | { | |
3813 | PPSMC_Result ret; | |
3814 | ||
3815 | if (thermal_level == 0) { | |
6861c837 | 3816 | ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); |
841686df MB |
3817 | if (ret == PPSMC_Result_OK) |
3818 | return 0; | |
3819 | else | |
3820 | return -EINVAL; | |
3821 | } | |
3822 | return 0; | |
3823 | } | |
3824 | ||
3825 | static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) | |
3826 | { | |
3827 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); | |
3828 | } | |
3829 | #endif | |
3830 | ||
3831 | #if 0 | |
3832 | static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) | |
3833 | { | |
3834 | if (ac_power) | |
6861c837 | 3835 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? |
841686df MB |
3836 | 0 : -EINVAL; |
3837 | ||
3838 | return 0; | |
3839 | } | |
3840 | #endif | |
3841 | ||
3842 | static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, | |
3843 | PPSMC_Msg msg, u32 parameter) | |
3844 | { | |
3845 | WREG32(SMC_SCRATCH0, parameter); | |
6861c837 | 3846 | return amdgpu_si_send_msg_to_smc(adev, msg); |
841686df MB |
3847 | } |
3848 | ||
3849 | static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) | |
3850 | { | |
6861c837 | 3851 | if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) |
841686df MB |
3852 | return -EINVAL; |
3853 | ||
3854 | return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? | |
3855 | 0 : -EINVAL; | |
3856 | } | |
3857 | ||
cfa289fd | 3858 | static int si_dpm_force_performance_level(void *handle, |
e5d03ac2 | 3859 | enum amd_dpm_forced_level level) |
841686df | 3860 | { |
cfa289fd | 3861 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
3862 | struct amdgpu_ps *rps = adev->pm.dpm.current_ps; |
3863 | struct si_ps *ps = si_get_ps(rps); | |
3864 | u32 levels = ps->performance_level_count; | |
3865 | ||
e5d03ac2 | 3866 | if (level == AMD_DPM_FORCED_LEVEL_HIGH) { |
841686df MB |
3867 | if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) |
3868 | return -EINVAL; | |
3869 | ||
3870 | if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) | |
3871 | return -EINVAL; | |
e5d03ac2 | 3872 | } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { |
841686df MB |
3873 | if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) |
3874 | return -EINVAL; | |
3875 | ||
3876 | if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) | |
3877 | return -EINVAL; | |
e5d03ac2 | 3878 | } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { |
841686df MB |
3879 | if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) |
3880 | return -EINVAL; | |
3881 | ||
3882 | if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) | |
3883 | return -EINVAL; | |
3884 | } | |
3885 | ||
3886 | adev->pm.dpm.forced_level = level; | |
3887 | ||
3888 | return 0; | |
3889 | } | |
3890 | ||
3891 | #if 0 | |
3892 | static int si_set_boot_state(struct amdgpu_device *adev) | |
3893 | { | |
6861c837 | 3894 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? |
841686df MB |
3895 | 0 : -EINVAL; |
3896 | } | |
3897 | #endif | |
3898 | ||
3899 | static int si_set_sw_state(struct amdgpu_device *adev) | |
3900 | { | |
6861c837 | 3901 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? |
841686df MB |
3902 | 0 : -EINVAL; |
3903 | } | |
3904 | ||
3905 | static int si_halt_smc(struct amdgpu_device *adev) | |
3906 | { | |
6861c837 | 3907 | if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) |
841686df MB |
3908 | return -EINVAL; |
3909 | ||
6861c837 | 3910 | return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? |
841686df MB |
3911 | 0 : -EINVAL; |
3912 | } | |
3913 | ||
3914 | static int si_resume_smc(struct amdgpu_device *adev) | |
3915 | { | |
6861c837 | 3916 | if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) |
841686df MB |
3917 | return -EINVAL; |
3918 | ||
6861c837 | 3919 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? |
841686df MB |
3920 | 0 : -EINVAL; |
3921 | } | |
3922 | ||
3923 | static void si_dpm_start_smc(struct amdgpu_device *adev) | |
3924 | { | |
6861c837 AD |
3925 | amdgpu_si_program_jump_on_start(adev); |
3926 | amdgpu_si_start_smc(adev); | |
3927 | amdgpu_si_smc_clock(adev, true); | |
841686df MB |
3928 | } |
3929 | ||
3930 | static void si_dpm_stop_smc(struct amdgpu_device *adev) | |
3931 | { | |
6861c837 AD |
3932 | amdgpu_si_reset_smc(adev); |
3933 | amdgpu_si_smc_clock(adev, false); | |
841686df MB |
3934 | } |
3935 | ||
3936 | static int si_process_firmware_header(struct amdgpu_device *adev) | |
3937 | { | |
3938 | struct si_power_info *si_pi = si_get_pi(adev); | |
3939 | u32 tmp; | |
3940 | int ret; | |
3941 | ||
6861c837 AD |
3942 | ret = amdgpu_si_read_smc_sram_dword(adev, |
3943 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3944 | SISLANDS_SMC_FIRMWARE_HEADER_stateTable, | |
3945 | &tmp, si_pi->sram_end); | |
841686df MB |
3946 | if (ret) |
3947 | return ret; | |
3948 | ||
77d318a6 | 3949 | si_pi->state_table_start = tmp; |
841686df | 3950 | |
6861c837 AD |
3951 | ret = amdgpu_si_read_smc_sram_dword(adev, |
3952 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3953 | SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, | |
3954 | &tmp, si_pi->sram_end); | |
841686df MB |
3955 | if (ret) |
3956 | return ret; | |
3957 | ||
3958 | si_pi->soft_regs_start = tmp; | |
3959 | ||
6861c837 AD |
3960 | ret = amdgpu_si_read_smc_sram_dword(adev, |
3961 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3962 | SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, | |
3963 | &tmp, si_pi->sram_end); | |
841686df MB |
3964 | if (ret) |
3965 | return ret; | |
3966 | ||
3967 | si_pi->mc_reg_table_start = tmp; | |
3968 | ||
6861c837 AD |
3969 | ret = amdgpu_si_read_smc_sram_dword(adev, |
3970 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3971 | SISLANDS_SMC_FIRMWARE_HEADER_fanTable, | |
3972 | &tmp, si_pi->sram_end); | |
841686df MB |
3973 | if (ret) |
3974 | return ret; | |
3975 | ||
3976 | si_pi->fan_table_start = tmp; | |
3977 | ||
6861c837 AD |
3978 | ret = amdgpu_si_read_smc_sram_dword(adev, |
3979 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3980 | SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, | |
3981 | &tmp, si_pi->sram_end); | |
841686df MB |
3982 | if (ret) |
3983 | return ret; | |
3984 | ||
3985 | si_pi->arb_table_start = tmp; | |
3986 | ||
6861c837 AD |
3987 | ret = amdgpu_si_read_smc_sram_dword(adev, |
3988 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3989 | SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, | |
3990 | &tmp, si_pi->sram_end); | |
841686df MB |
3991 | if (ret) |
3992 | return ret; | |
3993 | ||
3994 | si_pi->cac_table_start = tmp; | |
3995 | ||
6861c837 AD |
3996 | ret = amdgpu_si_read_smc_sram_dword(adev, |
3997 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
3998 | SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, | |
3999 | &tmp, si_pi->sram_end); | |
841686df MB |
4000 | if (ret) |
4001 | return ret; | |
4002 | ||
4003 | si_pi->dte_table_start = tmp; | |
4004 | ||
6861c837 AD |
4005 | ret = amdgpu_si_read_smc_sram_dword(adev, |
4006 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
4007 | SISLANDS_SMC_FIRMWARE_HEADER_spllTable, | |
4008 | &tmp, si_pi->sram_end); | |
841686df MB |
4009 | if (ret) |
4010 | return ret; | |
4011 | ||
4012 | si_pi->spll_table_start = tmp; | |
4013 | ||
6861c837 AD |
4014 | ret = amdgpu_si_read_smc_sram_dword(adev, |
4015 | SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + | |
4016 | SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, | |
4017 | &tmp, si_pi->sram_end); | |
841686df MB |
4018 | if (ret) |
4019 | return ret; | |
4020 | ||
4021 | si_pi->papm_cfg_table_start = tmp; | |
4022 | ||
4023 | return ret; | |
4024 | } | |
4025 | ||
4026 | static void si_read_clock_registers(struct amdgpu_device *adev) | |
4027 | { | |
4028 | struct si_power_info *si_pi = si_get_pi(adev); | |
4029 | ||
4030 | si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); | |
4031 | si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); | |
4032 | si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); | |
4033 | si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); | |
4034 | si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); | |
4035 | si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); | |
4036 | si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); | |
4037 | si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); | |
4038 | si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); | |
4039 | si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); | |
4040 | si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); | |
4041 | si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); | |
4042 | si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); | |
4043 | si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); | |
4044 | si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); | |
4045 | } | |
4046 | ||
4047 | static void si_enable_thermal_protection(struct amdgpu_device *adev, | |
4048 | bool enable) | |
4049 | { | |
4050 | if (enable) | |
4051 | WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); | |
4052 | else | |
4053 | WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); | |
4054 | } | |
4055 | ||
4056 | static void si_enable_acpi_power_management(struct amdgpu_device *adev) | |
4057 | { | |
4058 | WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); | |
4059 | } | |
4060 | ||
4061 | #if 0 | |
4062 | static int si_enter_ulp_state(struct amdgpu_device *adev) | |
4063 | { | |
4064 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); | |
4065 | ||
4066 | udelay(25000); | |
4067 | ||
4068 | return 0; | |
4069 | } | |
4070 | ||
4071 | static int si_exit_ulp_state(struct amdgpu_device *adev) | |
4072 | { | |
4073 | int i; | |
4074 | ||
4075 | WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); | |
4076 | ||
4077 | udelay(7000); | |
4078 | ||
4079 | for (i = 0; i < adev->usec_timeout; i++) { | |
4080 | if (RREG32(SMC_RESP_0) == 1) | |
4081 | break; | |
4082 | udelay(1000); | |
4083 | } | |
4084 | ||
4085 | return 0; | |
4086 | } | |
4087 | #endif | |
4088 | ||
4089 | static int si_notify_smc_display_change(struct amdgpu_device *adev, | |
4090 | bool has_display) | |
4091 | { | |
4092 | PPSMC_Msg msg = has_display ? | |
4093 | PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; | |
4094 | ||
6861c837 | 4095 | return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? |
841686df MB |
4096 | 0 : -EINVAL; |
4097 | } | |
4098 | ||
4099 | static void si_program_response_times(struct amdgpu_device *adev) | |
4100 | { | |
4101 | u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; | |
4102 | u32 vddc_dly, acpi_dly, vbi_dly; | |
4103 | u32 reference_clock; | |
4104 | ||
4105 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); | |
4106 | ||
4107 | voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; | |
77d318a6 | 4108 | backbias_response_time = (u32)adev->pm.dpm.backbias_response_time; |
841686df MB |
4109 | |
4110 | if (voltage_response_time == 0) | |
4111 | voltage_response_time = 1000; | |
4112 | ||
4113 | acpi_delay_time = 15000; | |
4114 | vbi_time_out = 100000; | |
4115 | ||
4116 | reference_clock = amdgpu_asic_get_xclk(adev); | |
4117 | ||
4118 | vddc_dly = (voltage_response_time * reference_clock) / 100; | |
4119 | acpi_dly = (acpi_delay_time * reference_clock) / 100; | |
4120 | vbi_dly = (vbi_time_out * reference_clock) / 100; | |
4121 | ||
4122 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); | |
4123 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); | |
4124 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); | |
4125 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); | |
4126 | } | |
4127 | ||
4128 | static void si_program_ds_registers(struct amdgpu_device *adev) | |
4129 | { | |
4130 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
4131 | u32 tmp; | |
4132 | ||
4133 | /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */ | |
4134 | if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) | |
4135 | tmp = 0x10; | |
4136 | else | |
4137 | tmp = 0x1; | |
4138 | ||
4139 | if (eg_pi->sclk_deep_sleep) { | |
4140 | WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); | |
4141 | WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, | |
4142 | ~AUTOSCALE_ON_SS_CLEAR); | |
4143 | } | |
4144 | } | |
4145 | ||
4146 | static void si_program_display_gap(struct amdgpu_device *adev) | |
4147 | { | |
4148 | u32 tmp, pipe; | |
4149 | int i; | |
4150 | ||
4151 | tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); | |
4152 | if (adev->pm.dpm.new_active_crtc_count > 0) | |
4153 | tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); | |
4154 | else | |
4155 | tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); | |
4156 | ||
4157 | if (adev->pm.dpm.new_active_crtc_count > 1) | |
4158 | tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); | |
4159 | else | |
4160 | tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); | |
4161 | ||
4162 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); | |
4163 | ||
4164 | tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); | |
4165 | pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; | |
4166 | ||
4167 | if ((adev->pm.dpm.new_active_crtc_count > 0) && | |
4168 | (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { | |
4169 | /* find the first active crtc */ | |
4170 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
4171 | if (adev->pm.dpm.new_active_crtcs & (1 << i)) | |
4172 | break; | |
4173 | } | |
4174 | if (i == adev->mode_info.num_crtc) | |
4175 | pipe = 0; | |
4176 | else | |
4177 | pipe = i; | |
4178 | ||
4179 | tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; | |
4180 | tmp |= DCCG_DISP1_SLOW_SELECT(pipe); | |
4181 | WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); | |
4182 | } | |
4183 | ||
4184 | /* Setting this to false forces the performance state to low if the crtcs are disabled. | |
4185 | * This can be a problem on PowerXpress systems or if you want to use the card | |
4186 | * for offscreen rendering or compute if there are no crtcs enabled. | |
4187 | */ | |
4188 | si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); | |
4189 | } | |
4190 | ||
4191 | static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) | |
4192 | { | |
4193 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4194 | ||
4195 | if (enable) { | |
4196 | if (pi->sclk_ss) | |
4197 | WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); | |
4198 | } else { | |
4199 | WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); | |
4200 | WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); | |
4201 | } | |
4202 | } | |
4203 | ||
4204 | static void si_setup_bsp(struct amdgpu_device *adev) | |
4205 | { | |
4206 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4207 | u32 xclk = amdgpu_asic_get_xclk(adev); | |
4208 | ||
4209 | r600_calculate_u_and_p(pi->asi, | |
4210 | xclk, | |
4211 | 16, | |
4212 | &pi->bsp, | |
4213 | &pi->bsu); | |
4214 | ||
4215 | r600_calculate_u_and_p(pi->pasi, | |
4216 | xclk, | |
4217 | 16, | |
4218 | &pi->pbsp, | |
4219 | &pi->pbsu); | |
4220 | ||
4221 | ||
4222 | pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); | |
4223 | pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); | |
4224 | ||
4225 | WREG32(CG_BSP, pi->dsp); | |
4226 | } | |
4227 | ||
4228 | static void si_program_git(struct amdgpu_device *adev) | |
4229 | { | |
4230 | WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); | |
4231 | } | |
4232 | ||
4233 | static void si_program_tp(struct amdgpu_device *adev) | |
4234 | { | |
4235 | int i; | |
4236 | enum r600_td td = R600_TD_DFLT; | |
4237 | ||
4238 | for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) | |
4239 | WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); | |
4240 | ||
4241 | if (td == R600_TD_AUTO) | |
4242 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); | |
4243 | else | |
4244 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); | |
4245 | ||
4246 | if (td == R600_TD_UP) | |
4247 | WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); | |
4248 | ||
4249 | if (td == R600_TD_DOWN) | |
4250 | WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); | |
4251 | } | |
4252 | ||
4253 | static void si_program_tpp(struct amdgpu_device *adev) | |
4254 | { | |
4255 | WREG32(CG_TPC, R600_TPC_DFLT); | |
4256 | } | |
4257 | ||
4258 | static void si_program_sstp(struct amdgpu_device *adev) | |
4259 | { | |
4260 | WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); | |
4261 | } | |
4262 | ||
4263 | static void si_enable_display_gap(struct amdgpu_device *adev) | |
4264 | { | |
4265 | u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); | |
4266 | ||
4267 | tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); | |
4268 | tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | | |
4269 | DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); | |
4270 | ||
4271 | tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); | |
4272 | tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | | |
4273 | DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); | |
4274 | WREG32(CG_DISPLAY_GAP_CNTL, tmp); | |
4275 | } | |
4276 | ||
4277 | static void si_program_vc(struct amdgpu_device *adev) | |
4278 | { | |
4279 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4280 | ||
4281 | WREG32(CG_FTV, pi->vrc); | |
4282 | } | |
4283 | ||
4284 | static void si_clear_vc(struct amdgpu_device *adev) | |
4285 | { | |
4286 | WREG32(CG_FTV, 0); | |
4287 | } | |
4288 | ||
a1047777 | 4289 | static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) |
841686df MB |
4290 | { |
4291 | u8 mc_para_index; | |
4292 | ||
4293 | if (memory_clock < 10000) | |
4294 | mc_para_index = 0; | |
4295 | else if (memory_clock >= 80000) | |
4296 | mc_para_index = 0x0f; | |
4297 | else | |
4298 | mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); | |
4299 | return mc_para_index; | |
4300 | } | |
4301 | ||
a1047777 | 4302 | static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) |
841686df MB |
4303 | { |
4304 | u8 mc_para_index; | |
4305 | ||
4306 | if (strobe_mode) { | |
4307 | if (memory_clock < 12500) | |
4308 | mc_para_index = 0x00; | |
4309 | else if (memory_clock > 47500) | |
4310 | mc_para_index = 0x0f; | |
4311 | else | |
4312 | mc_para_index = (u8)((memory_clock - 10000) / 2500); | |
4313 | } else { | |
4314 | if (memory_clock < 65000) | |
4315 | mc_para_index = 0x00; | |
4316 | else if (memory_clock > 135000) | |
4317 | mc_para_index = 0x0f; | |
4318 | else | |
4319 | mc_para_index = (u8)((memory_clock - 60000) / 5000); | |
4320 | } | |
4321 | return mc_para_index; | |
4322 | } | |
4323 | ||
4324 | static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) | |
4325 | { | |
4326 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4327 | bool strobe_mode = false; | |
4328 | u8 result = 0; | |
4329 | ||
4330 | if (mclk <= pi->mclk_strobe_mode_threshold) | |
4331 | strobe_mode = true; | |
4332 | ||
770d13b1 | 4333 | if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) |
841686df MB |
4334 | result = si_get_mclk_frequency_ratio(mclk, strobe_mode); |
4335 | else | |
4336 | result = si_get_ddr3_mclk_frequency_ratio(mclk); | |
4337 | ||
4338 | if (strobe_mode) | |
4339 | result |= SISLANDS_SMC_STROBE_ENABLE; | |
4340 | ||
4341 | return result; | |
4342 | } | |
4343 | ||
4344 | static int si_upload_firmware(struct amdgpu_device *adev) | |
4345 | { | |
4346 | struct si_power_info *si_pi = si_get_pi(adev); | |
841686df | 4347 | |
6861c837 AD |
4348 | amdgpu_si_reset_smc(adev); |
4349 | amdgpu_si_smc_clock(adev, false); | |
841686df | 4350 | |
6861c837 | 4351 | return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); |
841686df MB |
4352 | } |
4353 | ||
4354 | static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, | |
4355 | const struct atom_voltage_table *table, | |
4356 | const struct amdgpu_phase_shedding_limits_table *limits) | |
4357 | { | |
4358 | u32 data, num_bits, num_levels; | |
4359 | ||
4360 | if ((table == NULL) || (limits == NULL)) | |
4361 | return false; | |
4362 | ||
4363 | data = table->mask_low; | |
4364 | ||
4365 | num_bits = hweight32(data); | |
4366 | ||
4367 | if (num_bits == 0) | |
4368 | return false; | |
4369 | ||
4370 | num_levels = (1 << num_bits); | |
4371 | ||
4372 | if (table->count != num_levels) | |
4373 | return false; | |
4374 | ||
4375 | if (limits->count != (num_levels - 1)) | |
4376 | return false; | |
4377 | ||
4378 | return true; | |
4379 | } | |
4380 | ||
4381 | static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, | |
4382 | u32 max_voltage_steps, | |
4383 | struct atom_voltage_table *voltage_table) | |
4384 | { | |
4385 | unsigned int i, diff; | |
4386 | ||
4387 | if (voltage_table->count <= max_voltage_steps) | |
4388 | return; | |
4389 | ||
4390 | diff = voltage_table->count - max_voltage_steps; | |
4391 | ||
4392 | for (i= 0; i < max_voltage_steps; i++) | |
4393 | voltage_table->entries[i] = voltage_table->entries[i + diff]; | |
4394 | ||
4395 | voltage_table->count = max_voltage_steps; | |
4396 | } | |
4397 | ||
4398 | static int si_get_svi2_voltage_table(struct amdgpu_device *adev, | |
4399 | struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, | |
4400 | struct atom_voltage_table *voltage_table) | |
4401 | { | |
4402 | u32 i; | |
4403 | ||
4404 | if (voltage_dependency_table == NULL) | |
4405 | return -EINVAL; | |
4406 | ||
4407 | voltage_table->mask_low = 0; | |
4408 | voltage_table->phase_delay = 0; | |
4409 | ||
4410 | voltage_table->count = voltage_dependency_table->count; | |
4411 | for (i = 0; i < voltage_table->count; i++) { | |
4412 | voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; | |
4413 | voltage_table->entries[i].smio_low = 0; | |
4414 | } | |
4415 | ||
4416 | return 0; | |
4417 | } | |
4418 | ||
4419 | static int si_construct_voltage_tables(struct amdgpu_device *adev) | |
4420 | { | |
4421 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4422 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
4423 | struct si_power_info *si_pi = si_get_pi(adev); | |
4424 | int ret; | |
4425 | ||
4426 | if (pi->voltage_control) { | |
4427 | ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, | |
4428 | VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); | |
4429 | if (ret) | |
4430 | return ret; | |
4431 | ||
4432 | if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) | |
4433 | si_trim_voltage_table_to_fit_state_table(adev, | |
4434 | SISLANDS_MAX_NO_VREG_STEPS, | |
4435 | &eg_pi->vddc_voltage_table); | |
4436 | } else if (si_pi->voltage_control_svi2) { | |
4437 | ret = si_get_svi2_voltage_table(adev, | |
4438 | &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, | |
4439 | &eg_pi->vddc_voltage_table); | |
4440 | if (ret) | |
4441 | return ret; | |
4442 | } else { | |
4443 | return -EINVAL; | |
4444 | } | |
4445 | ||
4446 | if (eg_pi->vddci_control) { | |
4447 | ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, | |
4448 | VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); | |
4449 | if (ret) | |
4450 | return ret; | |
4451 | ||
4452 | if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) | |
4453 | si_trim_voltage_table_to_fit_state_table(adev, | |
4454 | SISLANDS_MAX_NO_VREG_STEPS, | |
4455 | &eg_pi->vddci_voltage_table); | |
4456 | } | |
4457 | if (si_pi->vddci_control_svi2) { | |
4458 | ret = si_get_svi2_voltage_table(adev, | |
4459 | &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, | |
4460 | &eg_pi->vddci_voltage_table); | |
4461 | if (ret) | |
4462 | return ret; | |
4463 | } | |
4464 | ||
4465 | if (pi->mvdd_control) { | |
4466 | ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, | |
4467 | VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); | |
4468 | ||
4469 | if (ret) { | |
4470 | pi->mvdd_control = false; | |
4471 | return ret; | |
4472 | } | |
4473 | ||
4474 | if (si_pi->mvdd_voltage_table.count == 0) { | |
4475 | pi->mvdd_control = false; | |
4476 | return -EINVAL; | |
4477 | } | |
4478 | ||
4479 | if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) | |
4480 | si_trim_voltage_table_to_fit_state_table(adev, | |
4481 | SISLANDS_MAX_NO_VREG_STEPS, | |
4482 | &si_pi->mvdd_voltage_table); | |
4483 | } | |
4484 | ||
4485 | if (si_pi->vddc_phase_shed_control) { | |
4486 | ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, | |
4487 | VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); | |
4488 | if (ret) | |
4489 | si_pi->vddc_phase_shed_control = false; | |
4490 | ||
4491 | if ((si_pi->vddc_phase_shed_table.count == 0) || | |
4492 | (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) | |
4493 | si_pi->vddc_phase_shed_control = false; | |
4494 | } | |
4495 | ||
4496 | return 0; | |
4497 | } | |
4498 | ||
4499 | static void si_populate_smc_voltage_table(struct amdgpu_device *adev, | |
4500 | const struct atom_voltage_table *voltage_table, | |
4501 | SISLANDS_SMC_STATETABLE *table) | |
4502 | { | |
4503 | unsigned int i; | |
4504 | ||
4505 | for (i = 0; i < voltage_table->count; i++) | |
4506 | table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); | |
4507 | } | |
4508 | ||
4509 | static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, | |
4510 | SISLANDS_SMC_STATETABLE *table) | |
4511 | { | |
4512 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4513 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
4514 | struct si_power_info *si_pi = si_get_pi(adev); | |
4515 | u8 i; | |
4516 | ||
4517 | if (si_pi->voltage_control_svi2) { | |
4518 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, | |
4519 | si_pi->svc_gpio_id); | |
4520 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, | |
4521 | si_pi->svd_gpio_id); | |
4522 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, | |
4523 | 2); | |
4524 | } else { | |
4525 | if (eg_pi->vddc_voltage_table.count) { | |
4526 | si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); | |
4527 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = | |
4528 | cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); | |
4529 | ||
4530 | for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { | |
4531 | if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { | |
4532 | table->maxVDDCIndexInPPTable = i; | |
4533 | break; | |
4534 | } | |
4535 | } | |
4536 | } | |
4537 | ||
4538 | if (eg_pi->vddci_voltage_table.count) { | |
4539 | si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); | |
4540 | ||
4541 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = | |
4542 | cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); | |
4543 | } | |
4544 | ||
4545 | ||
4546 | if (si_pi->mvdd_voltage_table.count) { | |
4547 | si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); | |
4548 | ||
4549 | table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = | |
4550 | cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); | |
4551 | } | |
4552 | ||
4553 | if (si_pi->vddc_phase_shed_control) { | |
4554 | if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, | |
4555 | &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { | |
4556 | si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); | |
4557 | ||
bdbdb571 | 4558 | table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = |
841686df MB |
4559 | cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); |
4560 | ||
4561 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, | |
4562 | (u32)si_pi->vddc_phase_shed_table.phase_delay); | |
4563 | } else { | |
4564 | si_pi->vddc_phase_shed_control = false; | |
4565 | } | |
4566 | } | |
4567 | } | |
4568 | ||
4569 | return 0; | |
4570 | } | |
4571 | ||
4572 | static int si_populate_voltage_value(struct amdgpu_device *adev, | |
4573 | const struct atom_voltage_table *table, | |
4574 | u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4575 | { | |
4576 | unsigned int i; | |
4577 | ||
4578 | for (i = 0; i < table->count; i++) { | |
4579 | if (value <= table->entries[i].value) { | |
4580 | voltage->index = (u8)i; | |
4581 | voltage->value = cpu_to_be16(table->entries[i].value); | |
4582 | break; | |
4583 | } | |
4584 | } | |
4585 | ||
4586 | if (i >= table->count) | |
4587 | return -EINVAL; | |
4588 | ||
4589 | return 0; | |
4590 | } | |
4591 | ||
4592 | static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, | |
4593 | SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4594 | { | |
4595 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4596 | struct si_power_info *si_pi = si_get_pi(adev); | |
4597 | ||
4598 | if (pi->mvdd_control) { | |
4599 | if (mclk <= pi->mvdd_split_frequency) | |
4600 | voltage->index = 0; | |
4601 | else | |
4602 | voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; | |
4603 | ||
4604 | voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); | |
4605 | } | |
4606 | return 0; | |
4607 | } | |
4608 | ||
4609 | static int si_get_std_voltage_value(struct amdgpu_device *adev, | |
4610 | SISLANDS_SMC_VOLTAGE_VALUE *voltage, | |
4611 | u16 *std_voltage) | |
4612 | { | |
4613 | u16 v_index; | |
4614 | bool voltage_found = false; | |
4615 | *std_voltage = be16_to_cpu(voltage->value); | |
4616 | ||
4617 | if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { | |
4618 | if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { | |
4619 | if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) | |
4620 | return -EINVAL; | |
4621 | ||
4622 | for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { | |
4623 | if (be16_to_cpu(voltage->value) == | |
4624 | (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { | |
4625 | voltage_found = true; | |
4626 | if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) | |
4627 | *std_voltage = | |
4628 | adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; | |
4629 | else | |
4630 | *std_voltage = | |
4631 | adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; | |
4632 | break; | |
4633 | } | |
4634 | } | |
4635 | ||
4636 | if (!voltage_found) { | |
4637 | for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { | |
4638 | if (be16_to_cpu(voltage->value) <= | |
4639 | (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { | |
4640 | voltage_found = true; | |
4641 | if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) | |
4642 | *std_voltage = | |
4643 | adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; | |
4644 | else | |
4645 | *std_voltage = | |
4646 | adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; | |
4647 | break; | |
4648 | } | |
4649 | } | |
4650 | } | |
4651 | } else { | |
4652 | if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) | |
4653 | *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; | |
4654 | } | |
4655 | } | |
4656 | ||
4657 | return 0; | |
4658 | } | |
4659 | ||
4660 | static int si_populate_std_voltage_value(struct amdgpu_device *adev, | |
4661 | u16 value, u8 index, | |
4662 | SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4663 | { | |
4664 | voltage->index = index; | |
4665 | voltage->value = cpu_to_be16(value); | |
4666 | ||
4667 | return 0; | |
4668 | } | |
4669 | ||
4670 | static int si_populate_phase_shedding_value(struct amdgpu_device *adev, | |
4671 | const struct amdgpu_phase_shedding_limits_table *limits, | |
4672 | u16 voltage, u32 sclk, u32 mclk, | |
4673 | SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) | |
4674 | { | |
4675 | unsigned int i; | |
4676 | ||
4677 | for (i = 0; i < limits->count; i++) { | |
4678 | if ((voltage <= limits->entries[i].voltage) && | |
4679 | (sclk <= limits->entries[i].sclk) && | |
4680 | (mclk <= limits->entries[i].mclk)) | |
4681 | break; | |
4682 | } | |
4683 | ||
4684 | smc_voltage->phase_settings = (u8)i; | |
4685 | ||
4686 | return 0; | |
4687 | } | |
4688 | ||
4689 | static int si_init_arb_table_index(struct amdgpu_device *adev) | |
4690 | { | |
4691 | struct si_power_info *si_pi = si_get_pi(adev); | |
4692 | u32 tmp; | |
4693 | int ret; | |
4694 | ||
6861c837 AD |
4695 | ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, |
4696 | &tmp, si_pi->sram_end); | |
841686df MB |
4697 | if (ret) |
4698 | return ret; | |
4699 | ||
4700 | tmp &= 0x00FFFFFF; | |
4701 | tmp |= MC_CG_ARB_FREQ_F1 << 24; | |
4702 | ||
6861c837 AD |
4703 | return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, |
4704 | tmp, si_pi->sram_end); | |
841686df MB |
4705 | } |
4706 | ||
4707 | static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) | |
4708 | { | |
4709 | return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); | |
4710 | } | |
4711 | ||
4712 | static int si_reset_to_default(struct amdgpu_device *adev) | |
4713 | { | |
6861c837 | 4714 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? |
841686df MB |
4715 | 0 : -EINVAL; |
4716 | } | |
4717 | ||
4718 | static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) | |
4719 | { | |
4720 | struct si_power_info *si_pi = si_get_pi(adev); | |
4721 | u32 tmp; | |
4722 | int ret; | |
4723 | ||
6861c837 AD |
4724 | ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, |
4725 | &tmp, si_pi->sram_end); | |
841686df MB |
4726 | if (ret) |
4727 | return ret; | |
4728 | ||
4729 | tmp = (tmp >> 24) & 0xff; | |
4730 | ||
4731 | if (tmp == MC_CG_ARB_FREQ_F0) | |
4732 | return 0; | |
4733 | ||
4734 | return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); | |
4735 | } | |
4736 | ||
4737 | static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, | |
4738 | u32 engine_clock) | |
4739 | { | |
4740 | u32 dram_rows; | |
4741 | u32 dram_refresh_rate; | |
4742 | u32 mc_arb_rfsh_rate; | |
4743 | u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; | |
4744 | ||
4745 | if (tmp >= 4) | |
4746 | dram_rows = 16384; | |
4747 | else | |
4748 | dram_rows = 1 << (tmp + 10); | |
4749 | ||
4750 | dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); | |
4751 | mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; | |
4752 | ||
4753 | return mc_arb_rfsh_rate; | |
4754 | } | |
4755 | ||
4756 | static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, | |
4757 | struct rv7xx_pl *pl, | |
4758 | SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) | |
4759 | { | |
4760 | u32 dram_timing; | |
4761 | u32 dram_timing2; | |
4762 | u32 burst_time; | |
4763 | ||
4764 | arb_regs->mc_arb_rfsh_rate = | |
4765 | (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); | |
4766 | ||
4767 | amdgpu_atombios_set_engine_dram_timings(adev, | |
4768 | pl->sclk, | |
77d318a6 | 4769 | pl->mclk); |
841686df MB |
4770 | |
4771 | dram_timing = RREG32(MC_ARB_DRAM_TIMING); | |
4772 | dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); | |
4773 | burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; | |
4774 | ||
4775 | arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); | |
4776 | arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); | |
4777 | arb_regs->mc_arb_burst_time = (u8)burst_time; | |
4778 | ||
4779 | return 0; | |
4780 | } | |
4781 | ||
4782 | static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, | |
4783 | struct amdgpu_ps *amdgpu_state, | |
4784 | unsigned int first_arb_set) | |
4785 | { | |
4786 | struct si_power_info *si_pi = si_get_pi(adev); | |
4787 | struct si_ps *state = si_get_ps(amdgpu_state); | |
4788 | SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; | |
4789 | int i, ret = 0; | |
4790 | ||
4791 | for (i = 0; i < state->performance_level_count; i++) { | |
4792 | ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); | |
4793 | if (ret) | |
4794 | break; | |
6861c837 AD |
4795 | ret = amdgpu_si_copy_bytes_to_smc(adev, |
4796 | si_pi->arb_table_start + | |
4797 | offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + | |
4798 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), | |
4799 | (u8 *)&arb_regs, | |
4800 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), | |
4801 | si_pi->sram_end); | |
841686df MB |
4802 | if (ret) |
4803 | break; | |
77d318a6 | 4804 | } |
841686df MB |
4805 | |
4806 | return ret; | |
4807 | } | |
4808 | ||
4809 | static int si_program_memory_timing_parameters(struct amdgpu_device *adev, | |
4810 | struct amdgpu_ps *amdgpu_new_state) | |
4811 | { | |
4812 | return si_do_program_memory_timing_parameters(adev, amdgpu_new_state, | |
4813 | SISLANDS_DRIVER_STATE_ARB_INDEX); | |
4814 | } | |
4815 | ||
4816 | static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, | |
4817 | struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) | |
4818 | { | |
4819 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4820 | struct si_power_info *si_pi = si_get_pi(adev); | |
4821 | ||
4822 | if (pi->mvdd_control) | |
4823 | return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, | |
4824 | si_pi->mvdd_bootup_value, voltage); | |
4825 | ||
4826 | return 0; | |
4827 | } | |
4828 | ||
4829 | static int si_populate_smc_initial_state(struct amdgpu_device *adev, | |
4830 | struct amdgpu_ps *amdgpu_initial_state, | |
4831 | SISLANDS_SMC_STATETABLE *table) | |
4832 | { | |
4833 | struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); | |
4834 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4835 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
4836 | struct si_power_info *si_pi = si_get_pi(adev); | |
4837 | u32 reg; | |
4838 | int ret; | |
4839 | ||
4840 | table->initialState.levels[0].mclk.vDLL_CNTL = | |
4841 | cpu_to_be32(si_pi->clock_registers.dll_cntl); | |
4842 | table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = | |
4843 | cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); | |
4844 | table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = | |
4845 | cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); | |
4846 | table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = | |
4847 | cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); | |
4848 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = | |
4849 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); | |
4850 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = | |
4851 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); | |
4852 | table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = | |
4853 | cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); | |
4854 | table->initialState.levels[0].mclk.vMPLL_SS = | |
4855 | cpu_to_be32(si_pi->clock_registers.mpll_ss1); | |
4856 | table->initialState.levels[0].mclk.vMPLL_SS2 = | |
4857 | cpu_to_be32(si_pi->clock_registers.mpll_ss2); | |
4858 | ||
4859 | table->initialState.levels[0].mclk.mclk_value = | |
4860 | cpu_to_be32(initial_state->performance_levels[0].mclk); | |
4861 | ||
4862 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = | |
4863 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); | |
4864 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = | |
4865 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); | |
4866 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = | |
4867 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); | |
4868 | table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = | |
4869 | cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); | |
4870 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = | |
4871 | cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); | |
4872 | table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = | |
4873 | cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); | |
4874 | ||
4875 | table->initialState.levels[0].sclk.sclk_value = | |
4876 | cpu_to_be32(initial_state->performance_levels[0].sclk); | |
4877 | ||
4878 | table->initialState.levels[0].arbRefreshState = | |
4879 | SISLANDS_INITIAL_STATE_ARB_INDEX; | |
4880 | ||
4881 | table->initialState.levels[0].ACIndex = 0; | |
4882 | ||
4883 | ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, | |
4884 | initial_state->performance_levels[0].vddc, | |
4885 | &table->initialState.levels[0].vddc); | |
4886 | ||
4887 | if (!ret) { | |
4888 | u16 std_vddc; | |
4889 | ||
4890 | ret = si_get_std_voltage_value(adev, | |
4891 | &table->initialState.levels[0].vddc, | |
4892 | &std_vddc); | |
4893 | if (!ret) | |
4894 | si_populate_std_voltage_value(adev, std_vddc, | |
4895 | table->initialState.levels[0].vddc.index, | |
4896 | &table->initialState.levels[0].std_vddc); | |
4897 | } | |
4898 | ||
4899 | if (eg_pi->vddci_control) | |
4900 | si_populate_voltage_value(adev, | |
4901 | &eg_pi->vddci_voltage_table, | |
4902 | initial_state->performance_levels[0].vddci, | |
4903 | &table->initialState.levels[0].vddci); | |
4904 | ||
4905 | if (si_pi->vddc_phase_shed_control) | |
4906 | si_populate_phase_shedding_value(adev, | |
4907 | &adev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
4908 | initial_state->performance_levels[0].vddc, | |
4909 | initial_state->performance_levels[0].sclk, | |
4910 | initial_state->performance_levels[0].mclk, | |
4911 | &table->initialState.levels[0].vddc); | |
4912 | ||
4913 | si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd); | |
4914 | ||
4915 | reg = CG_R(0xffff) | CG_L(0); | |
4916 | table->initialState.levels[0].aT = cpu_to_be32(reg); | |
841686df | 4917 | table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); |
841686df MB |
4918 | table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; |
4919 | ||
770d13b1 | 4920 | if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { |
841686df MB |
4921 | table->initialState.levels[0].strobeMode = |
4922 | si_get_strobe_mode_settings(adev, | |
4923 | initial_state->performance_levels[0].mclk); | |
4924 | ||
4925 | if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) | |
4926 | table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; | |
4927 | else | |
4928 | table->initialState.levels[0].mcFlags = 0; | |
4929 | } | |
4930 | ||
4931 | table->initialState.levelCount = 1; | |
4932 | ||
4933 | table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; | |
4934 | ||
4935 | table->initialState.levels[0].dpm2.MaxPS = 0; | |
4936 | table->initialState.levels[0].dpm2.NearTDPDec = 0; | |
4937 | table->initialState.levels[0].dpm2.AboveSafeInc = 0; | |
4938 | table->initialState.levels[0].dpm2.BelowSafeInc = 0; | |
4939 | table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; | |
4940 | ||
4941 | reg = MIN_POWER_MASK | MAX_POWER_MASK; | |
4942 | table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); | |
4943 | ||
4944 | reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; | |
4945 | table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); | |
4946 | ||
4947 | return 0; | |
4948 | } | |
4949 | ||
4950 | static int si_populate_smc_acpi_state(struct amdgpu_device *adev, | |
4951 | SISLANDS_SMC_STATETABLE *table) | |
4952 | { | |
4953 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
4954 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
4955 | struct si_power_info *si_pi = si_get_pi(adev); | |
4956 | u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; | |
4957 | u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; | |
4958 | u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; | |
4959 | u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; | |
4960 | u32 dll_cntl = si_pi->clock_registers.dll_cntl; | |
4961 | u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; | |
4962 | u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; | |
4963 | u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; | |
4964 | u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; | |
4965 | u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; | |
4966 | u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; | |
4967 | u32 reg; | |
4968 | int ret; | |
4969 | ||
4970 | table->ACPIState = table->initialState; | |
4971 | ||
4972 | table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; | |
4973 | ||
4974 | if (pi->acpi_vddc) { | |
4975 | ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, | |
4976 | pi->acpi_vddc, &table->ACPIState.levels[0].vddc); | |
4977 | if (!ret) { | |
4978 | u16 std_vddc; | |
4979 | ||
4980 | ret = si_get_std_voltage_value(adev, | |
4981 | &table->ACPIState.levels[0].vddc, &std_vddc); | |
4982 | if (!ret) | |
4983 | si_populate_std_voltage_value(adev, std_vddc, | |
4984 | table->ACPIState.levels[0].vddc.index, | |
4985 | &table->ACPIState.levels[0].std_vddc); | |
4986 | } | |
4987 | table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; | |
4988 | ||
4989 | if (si_pi->vddc_phase_shed_control) { | |
4990 | si_populate_phase_shedding_value(adev, | |
4991 | &adev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
4992 | pi->acpi_vddc, | |
4993 | 0, | |
4994 | 0, | |
4995 | &table->ACPIState.levels[0].vddc); | |
4996 | } | |
4997 | } else { | |
4998 | ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, | |
4999 | pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); | |
5000 | if (!ret) { | |
5001 | u16 std_vddc; | |
5002 | ||
5003 | ret = si_get_std_voltage_value(adev, | |
5004 | &table->ACPIState.levels[0].vddc, &std_vddc); | |
5005 | ||
5006 | if (!ret) | |
5007 | si_populate_std_voltage_value(adev, std_vddc, | |
5008 | table->ACPIState.levels[0].vddc.index, | |
5009 | &table->ACPIState.levels[0].std_vddc); | |
5010 | } | |
0bf67185 AD |
5011 | table->ACPIState.levels[0].gen2PCIE = |
5012 | (u8)amdgpu_get_pcie_gen_support(adev, | |
5013 | si_pi->sys_pcie_mask, | |
5014 | si_pi->boot_pcie_gen, | |
5015 | AMDGPU_PCIE_GEN1); | |
841686df MB |
5016 | |
5017 | if (si_pi->vddc_phase_shed_control) | |
5018 | si_populate_phase_shedding_value(adev, | |
5019 | &adev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
5020 | pi->min_vddc_in_table, | |
5021 | 0, | |
5022 | 0, | |
5023 | &table->ACPIState.levels[0].vddc); | |
5024 | } | |
5025 | ||
5026 | if (pi->acpi_vddc) { | |
5027 | if (eg_pi->acpi_vddci) | |
5028 | si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, | |
5029 | eg_pi->acpi_vddci, | |
5030 | &table->ACPIState.levels[0].vddci); | |
5031 | } | |
5032 | ||
5033 | mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; | |
5034 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); | |
5035 | ||
5036 | dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); | |
5037 | ||
5038 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; | |
5039 | spll_func_cntl_2 |= SCLK_MUX_SEL(4); | |
5040 | ||
5041 | table->ACPIState.levels[0].mclk.vDLL_CNTL = | |
5042 | cpu_to_be32(dll_cntl); | |
5043 | table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = | |
5044 | cpu_to_be32(mclk_pwrmgt_cntl); | |
5045 | table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = | |
5046 | cpu_to_be32(mpll_ad_func_cntl); | |
5047 | table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = | |
5048 | cpu_to_be32(mpll_dq_func_cntl); | |
5049 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = | |
5050 | cpu_to_be32(mpll_func_cntl); | |
5051 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = | |
5052 | cpu_to_be32(mpll_func_cntl_1); | |
5053 | table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = | |
5054 | cpu_to_be32(mpll_func_cntl_2); | |
5055 | table->ACPIState.levels[0].mclk.vMPLL_SS = | |
5056 | cpu_to_be32(si_pi->clock_registers.mpll_ss1); | |
5057 | table->ACPIState.levels[0].mclk.vMPLL_SS2 = | |
5058 | cpu_to_be32(si_pi->clock_registers.mpll_ss2); | |
5059 | ||
5060 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = | |
5061 | cpu_to_be32(spll_func_cntl); | |
5062 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = | |
5063 | cpu_to_be32(spll_func_cntl_2); | |
5064 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = | |
5065 | cpu_to_be32(spll_func_cntl_3); | |
5066 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = | |
5067 | cpu_to_be32(spll_func_cntl_4); | |
5068 | ||
5069 | table->ACPIState.levels[0].mclk.mclk_value = 0; | |
5070 | table->ACPIState.levels[0].sclk.sclk_value = 0; | |
5071 | ||
5072 | si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd); | |
5073 | ||
5074 | if (eg_pi->dynamic_ac_timing) | |
5075 | table->ACPIState.levels[0].ACIndex = 0; | |
5076 | ||
5077 | table->ACPIState.levels[0].dpm2.MaxPS = 0; | |
5078 | table->ACPIState.levels[0].dpm2.NearTDPDec = 0; | |
5079 | table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; | |
5080 | table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; | |
5081 | table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; | |
5082 | ||
5083 | reg = MIN_POWER_MASK | MAX_POWER_MASK; | |
5084 | table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); | |
5085 | ||
5086 | reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; | |
5087 | table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); | |
5088 | ||
5089 | return 0; | |
5090 | } | |
5091 | ||
5092 | static int si_populate_ulv_state(struct amdgpu_device *adev, | |
5093 | SISLANDS_SMC_SWSTATE *state) | |
5094 | { | |
5095 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
5096 | struct si_power_info *si_pi = si_get_pi(adev); | |
5097 | struct si_ulv_param *ulv = &si_pi->ulv; | |
5098 | u32 sclk_in_sr = 1350; /* ??? */ | |
5099 | int ret; | |
5100 | ||
5101 | ret = si_convert_power_level_to_smc(adev, &ulv->pl, | |
5102 | &state->levels[0]); | |
5103 | if (!ret) { | |
5104 | if (eg_pi->sclk_deep_sleep) { | |
5105 | if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) | |
5106 | state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; | |
5107 | else | |
5108 | state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; | |
5109 | } | |
5110 | if (ulv->one_pcie_lane_in_ulv) | |
5111 | state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; | |
5112 | state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); | |
5113 | state->levels[0].ACIndex = 1; | |
5114 | state->levels[0].std_vddc = state->levels[0].vddc; | |
5115 | state->levelCount = 1; | |
5116 | ||
5117 | state->flags |= PPSMC_SWSTATE_FLAG_DC; | |
5118 | } | |
5119 | ||
5120 | return ret; | |
5121 | } | |
5122 | ||
5123 | static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) | |
5124 | { | |
5125 | struct si_power_info *si_pi = si_get_pi(adev); | |
5126 | struct si_ulv_param *ulv = &si_pi->ulv; | |
5127 | SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; | |
5128 | int ret; | |
5129 | ||
5130 | ret = si_populate_memory_timing_parameters(adev, &ulv->pl, | |
5131 | &arb_regs); | |
5132 | if (ret) | |
5133 | return ret; | |
5134 | ||
5135 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, | |
5136 | ulv->volt_change_delay); | |
5137 | ||
6861c837 AD |
5138 | ret = amdgpu_si_copy_bytes_to_smc(adev, |
5139 | si_pi->arb_table_start + | |
5140 | offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + | |
5141 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, | |
5142 | (u8 *)&arb_regs, | |
5143 | sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), | |
5144 | si_pi->sram_end); | |
841686df MB |
5145 | |
5146 | return ret; | |
5147 | } | |
5148 | ||
5149 | static void si_get_mvdd_configuration(struct amdgpu_device *adev) | |
5150 | { | |
5151 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
5152 | ||
5153 | pi->mvdd_split_frequency = 30000; | |
5154 | } | |
5155 | ||
5156 | static int si_init_smc_table(struct amdgpu_device *adev) | |
5157 | { | |
5158 | struct si_power_info *si_pi = si_get_pi(adev); | |
5159 | struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; | |
5160 | const struct si_ulv_param *ulv = &si_pi->ulv; | |
5161 | SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; | |
5162 | int ret; | |
5163 | u32 lane_width; | |
5164 | u32 vr_hot_gpio; | |
5165 | ||
5166 | si_populate_smc_voltage_tables(adev, table); | |
5167 | ||
5168 | switch (adev->pm.int_thermal_type) { | |
5169 | case THERMAL_TYPE_SI: | |
5170 | case THERMAL_TYPE_EMC2103_WITH_INTERNAL: | |
5171 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; | |
5172 | break; | |
5173 | case THERMAL_TYPE_NONE: | |
5174 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; | |
5175 | break; | |
5176 | default: | |
5177 | table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; | |
5178 | break; | |
5179 | } | |
5180 | ||
5181 | if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) | |
5182 | table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; | |
5183 | ||
5184 | if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { | |
5185 | if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) | |
5186 | table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; | |
5187 | } | |
5188 | ||
5189 | if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) | |
5190 | table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; | |
5191 | ||
770d13b1 | 5192 | if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) |
841686df MB |
5193 | table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; |
5194 | ||
5195 | if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) | |
5196 | table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; | |
5197 | ||
5198 | if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { | |
5199 | table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; | |
5200 | vr_hot_gpio = adev->pm.dpm.backbias_response_time; | |
5201 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, | |
5202 | vr_hot_gpio); | |
5203 | } | |
5204 | ||
5205 | ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table); | |
5206 | if (ret) | |
5207 | return ret; | |
5208 | ||
5209 | ret = si_populate_smc_acpi_state(adev, table); | |
5210 | if (ret) | |
5211 | return ret; | |
5212 | ||
5213 | table->driverState = table->initialState; | |
5214 | ||
5215 | ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state, | |
5216 | SISLANDS_INITIAL_STATE_ARB_INDEX); | |
5217 | if (ret) | |
5218 | return ret; | |
5219 | ||
5220 | if (ulv->supported && ulv->pl.vddc) { | |
5221 | ret = si_populate_ulv_state(adev, &table->ULVState); | |
5222 | if (ret) | |
5223 | return ret; | |
5224 | ||
5225 | ret = si_program_ulv_memory_timing_parameters(adev); | |
5226 | if (ret) | |
5227 | return ret; | |
5228 | ||
5229 | WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); | |
5230 | WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); | |
5231 | ||
5232 | lane_width = amdgpu_get_pcie_lanes(adev); | |
5233 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); | |
5234 | } else { | |
5235 | table->ULVState = table->initialState; | |
5236 | } | |
5237 | ||
6861c837 AD |
5238 | return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, |
5239 | (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), | |
5240 | si_pi->sram_end); | |
841686df MB |
5241 | } |
5242 | ||
5243 | static int si_calculate_sclk_params(struct amdgpu_device *adev, | |
5244 | u32 engine_clock, | |
5245 | SISLANDS_SMC_SCLK_VALUE *sclk) | |
5246 | { | |
5247 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
5248 | struct si_power_info *si_pi = si_get_pi(adev); | |
5249 | struct atom_clock_dividers dividers; | |
5250 | u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; | |
5251 | u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; | |
5252 | u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; | |
5253 | u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; | |
5254 | u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; | |
5255 | u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; | |
5256 | u64 tmp; | |
5257 | u32 reference_clock = adev->clock.spll.reference_freq; | |
5258 | u32 reference_divider; | |
5259 | u32 fbdiv; | |
5260 | int ret; | |
5261 | ||
5262 | ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, | |
5263 | engine_clock, false, ÷rs); | |
5264 | if (ret) | |
5265 | return ret; | |
5266 | ||
5267 | reference_divider = 1 + dividers.ref_div; | |
5268 | ||
5269 | tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; | |
5270 | do_div(tmp, reference_clock); | |
5271 | fbdiv = (u32) tmp; | |
5272 | ||
5273 | spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); | |
5274 | spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); | |
5275 | spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); | |
5276 | ||
5277 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; | |
5278 | spll_func_cntl_2 |= SCLK_MUX_SEL(2); | |
5279 | ||
77d318a6 TSD |
5280 | spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; |
5281 | spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); | |
5282 | spll_func_cntl_3 |= SPLL_DITHEN; | |
841686df MB |
5283 | |
5284 | if (pi->sclk_ss) { | |
5285 | struct amdgpu_atom_ss ss; | |
5286 | u32 vco_freq = engine_clock * dividers.post_div; | |
5287 | ||
5288 | if (amdgpu_atombios_get_asic_ss_info(adev, &ss, | |
5289 | ASIC_INTERNAL_ENGINE_SS, vco_freq)) { | |
5290 | u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); | |
5291 | u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); | |
5292 | ||
5293 | cg_spll_spread_spectrum &= ~CLK_S_MASK; | |
5294 | cg_spll_spread_spectrum |= CLK_S(clk_s); | |
5295 | cg_spll_spread_spectrum |= SSEN; | |
5296 | ||
5297 | cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; | |
5298 | cg_spll_spread_spectrum_2 |= CLK_V(clk_v); | |
5299 | } | |
5300 | } | |
5301 | ||
5302 | sclk->sclk_value = engine_clock; | |
5303 | sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; | |
5304 | sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; | |
5305 | sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; | |
5306 | sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; | |
5307 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; | |
5308 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; | |
5309 | ||
5310 | return 0; | |
5311 | } | |
5312 | ||
5313 | static int si_populate_sclk_value(struct amdgpu_device *adev, | |
5314 | u32 engine_clock, | |
5315 | SISLANDS_SMC_SCLK_VALUE *sclk) | |
5316 | { | |
5317 | SISLANDS_SMC_SCLK_VALUE sclk_tmp; | |
5318 | int ret; | |
5319 | ||
5320 | ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); | |
5321 | if (!ret) { | |
5322 | sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); | |
5323 | sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); | |
5324 | sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); | |
5325 | sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); | |
5326 | sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); | |
5327 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); | |
5328 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); | |
5329 | } | |
5330 | ||
5331 | return ret; | |
5332 | } | |
5333 | ||
5334 | static int si_populate_mclk_value(struct amdgpu_device *adev, | |
5335 | u32 engine_clock, | |
5336 | u32 memory_clock, | |
5337 | SISLANDS_SMC_MCLK_VALUE *mclk, | |
5338 | bool strobe_mode, | |
5339 | bool dll_state_on) | |
5340 | { | |
5341 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
5342 | struct si_power_info *si_pi = si_get_pi(adev); | |
5343 | u32 dll_cntl = si_pi->clock_registers.dll_cntl; | |
5344 | u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; | |
5345 | u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; | |
5346 | u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; | |
5347 | u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; | |
5348 | u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; | |
5349 | u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; | |
5350 | u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; | |
5351 | u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; | |
5352 | struct atom_mpll_param mpll_param; | |
5353 | int ret; | |
5354 | ||
5355 | ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); | |
5356 | if (ret) | |
5357 | return ret; | |
5358 | ||
5359 | mpll_func_cntl &= ~BWCTRL_MASK; | |
5360 | mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); | |
5361 | ||
5362 | mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); | |
5363 | mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | | |
5364 | CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); | |
5365 | ||
5366 | mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; | |
5367 | mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); | |
5368 | ||
770d13b1 | 5369 | if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { |
841686df MB |
5370 | mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); |
5371 | mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | | |
5372 | YCLK_POST_DIV(mpll_param.post_div); | |
5373 | } | |
5374 | ||
5375 | if (pi->mclk_ss) { | |
5376 | struct amdgpu_atom_ss ss; | |
5377 | u32 freq_nom; | |
5378 | u32 tmp; | |
5379 | u32 reference_clock = adev->clock.mpll.reference_freq; | |
5380 | ||
770d13b1 | 5381 | if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) |
841686df MB |
5382 | freq_nom = memory_clock * 4; |
5383 | else | |
5384 | freq_nom = memory_clock * 2; | |
5385 | ||
5386 | tmp = freq_nom / reference_clock; | |
5387 | tmp = tmp * tmp; | |
5388 | if (amdgpu_atombios_get_asic_ss_info(adev, &ss, | |
77d318a6 | 5389 | ASIC_INTERNAL_MEMORY_SS, freq_nom)) { |
841686df MB |
5390 | u32 clks = reference_clock * 5 / ss.rate; |
5391 | u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); | |
5392 | ||
77d318a6 TSD |
5393 | mpll_ss1 &= ~CLKV_MASK; |
5394 | mpll_ss1 |= CLKV(clkv); | |
841686df | 5395 | |
77d318a6 TSD |
5396 | mpll_ss2 &= ~CLKS_MASK; |
5397 | mpll_ss2 |= CLKS(clks); | |
841686df MB |
5398 | } |
5399 | } | |
5400 | ||
5401 | mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; | |
5402 | mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); | |
5403 | ||
5404 | if (dll_state_on) | |
5405 | mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; | |
5406 | else | |
5407 | mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); | |
5408 | ||
5409 | mclk->mclk_value = cpu_to_be32(memory_clock); | |
5410 | mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); | |
5411 | mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); | |
5412 | mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); | |
5413 | mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); | |
5414 | mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); | |
5415 | mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); | |
5416 | mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); | |
5417 | mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); | |
5418 | mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); | |
5419 | ||
5420 | return 0; | |
5421 | } | |
5422 | ||
5423 | static void si_populate_smc_sp(struct amdgpu_device *adev, | |
5424 | struct amdgpu_ps *amdgpu_state, | |
5425 | SISLANDS_SMC_SWSTATE *smc_state) | |
5426 | { | |
5427 | struct si_ps *ps = si_get_ps(amdgpu_state); | |
5428 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
5429 | int i; | |
5430 | ||
5431 | for (i = 0; i < ps->performance_level_count - 1; i++) | |
5432 | smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); | |
5433 | ||
5434 | smc_state->levels[ps->performance_level_count - 1].bSP = | |
5435 | cpu_to_be32(pi->psp); | |
5436 | } | |
5437 | ||
5438 | static int si_convert_power_level_to_smc(struct amdgpu_device *adev, | |
5439 | struct rv7xx_pl *pl, | |
5440 | SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) | |
5441 | { | |
5442 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
5443 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
5444 | struct si_power_info *si_pi = si_get_pi(adev); | |
5445 | int ret; | |
5446 | bool dll_state_on; | |
5447 | u16 std_vddc; | |
5448 | bool gmc_pg = false; | |
5449 | ||
5450 | if (eg_pi->pcie_performance_request && | |
5451 | (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID)) | |
5452 | level->gen2PCIE = (u8)si_pi->force_pcie_gen; | |
5453 | else | |
5454 | level->gen2PCIE = (u8)pl->pcie_gen; | |
5455 | ||
5456 | ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); | |
5457 | if (ret) | |
5458 | return ret; | |
5459 | ||
5460 | level->mcFlags = 0; | |
5461 | ||
5462 | if (pi->mclk_stutter_mode_threshold && | |
5463 | (pl->mclk <= pi->mclk_stutter_mode_threshold) && | |
5464 | !eg_pi->uvd_enabled && | |
5465 | (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && | |
5466 | (adev->pm.dpm.new_active_crtc_count <= 2)) { | |
5467 | level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; | |
5468 | ||
5469 | if (gmc_pg) | |
5470 | level->mcFlags |= SISLANDS_SMC_MC_PG_EN; | |
5471 | } | |
5472 | ||
770d13b1 | 5473 | if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { |
841686df MB |
5474 | if (pl->mclk > pi->mclk_edc_enable_threshold) |
5475 | level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; | |
5476 | ||
5477 | if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) | |
5478 | level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; | |
5479 | ||
5480 | level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); | |
5481 | ||
5482 | if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { | |
5483 | if (si_get_mclk_frequency_ratio(pl->mclk, true) >= | |
5484 | ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) | |
5485 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; | |
5486 | else | |
5487 | dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; | |
5488 | } else { | |
5489 | dll_state_on = false; | |
5490 | } | |
5491 | } else { | |
5492 | level->strobeMode = si_get_strobe_mode_settings(adev, | |
5493 | pl->mclk); | |
5494 | ||
5495 | dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; | |
5496 | } | |
5497 | ||
5498 | ret = si_populate_mclk_value(adev, | |
5499 | pl->sclk, | |
5500 | pl->mclk, | |
5501 | &level->mclk, | |
5502 | (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); | |
5503 | if (ret) | |
5504 | return ret; | |
5505 | ||
5506 | ret = si_populate_voltage_value(adev, | |
5507 | &eg_pi->vddc_voltage_table, | |
5508 | pl->vddc, &level->vddc); | |
5509 | if (ret) | |
5510 | return ret; | |
5511 | ||
5512 | ||
5513 | ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); | |
5514 | if (ret) | |
5515 | return ret; | |
5516 | ||
5517 | ret = si_populate_std_voltage_value(adev, std_vddc, | |
5518 | level->vddc.index, &level->std_vddc); | |
5519 | if (ret) | |
5520 | return ret; | |
5521 | ||
5522 | if (eg_pi->vddci_control) { | |
5523 | ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, | |
5524 | pl->vddci, &level->vddci); | |
5525 | if (ret) | |
5526 | return ret; | |
5527 | } | |
5528 | ||
5529 | if (si_pi->vddc_phase_shed_control) { | |
5530 | ret = si_populate_phase_shedding_value(adev, | |
5531 | &adev->pm.dpm.dyn_state.phase_shedding_limits_table, | |
5532 | pl->vddc, | |
5533 | pl->sclk, | |
5534 | pl->mclk, | |
5535 | &level->vddc); | |
5536 | if (ret) | |
5537 | return ret; | |
5538 | } | |
5539 | ||
5540 | level->MaxPoweredUpCU = si_pi->max_cu; | |
5541 | ||
5542 | ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); | |
5543 | ||
5544 | return ret; | |
5545 | } | |
5546 | ||
5547 | static int si_populate_smc_t(struct amdgpu_device *adev, | |
5548 | struct amdgpu_ps *amdgpu_state, | |
5549 | SISLANDS_SMC_SWSTATE *smc_state) | |
5550 | { | |
5551 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
5552 | struct si_ps *state = si_get_ps(amdgpu_state); | |
5553 | u32 a_t; | |
5554 | u32 t_l, t_h; | |
5555 | u32 high_bsp; | |
5556 | int i, ret; | |
5557 | ||
5558 | if (state->performance_level_count >= 9) | |
5559 | return -EINVAL; | |
5560 | ||
5561 | if (state->performance_level_count < 2) { | |
5562 | a_t = CG_R(0xffff) | CG_L(0); | |
5563 | smc_state->levels[0].aT = cpu_to_be32(a_t); | |
5564 | return 0; | |
5565 | } | |
5566 | ||
5567 | smc_state->levels[0].aT = cpu_to_be32(0); | |
5568 | ||
5569 | for (i = 0; i <= state->performance_level_count - 2; i++) { | |
5570 | ret = r600_calculate_at( | |
5571 | (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), | |
5572 | 100 * R600_AH_DFLT, | |
5573 | state->performance_levels[i + 1].sclk, | |
5574 | state->performance_levels[i].sclk, | |
5575 | &t_l, | |
5576 | &t_h); | |
5577 | ||
5578 | if (ret) { | |
5579 | t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; | |
5580 | t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; | |
5581 | } | |
5582 | ||
5583 | a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; | |
5584 | a_t |= CG_R(t_l * pi->bsp / 20000); | |
5585 | smc_state->levels[i].aT = cpu_to_be32(a_t); | |
5586 | ||
5587 | high_bsp = (i == state->performance_level_count - 2) ? | |
5588 | pi->pbsp : pi->bsp; | |
5589 | a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); | |
5590 | smc_state->levels[i + 1].aT = cpu_to_be32(a_t); | |
5591 | } | |
5592 | ||
5593 | return 0; | |
5594 | } | |
5595 | ||
5596 | static int si_disable_ulv(struct amdgpu_device *adev) | |
5597 | { | |
5598 | struct si_power_info *si_pi = si_get_pi(adev); | |
5599 | struct si_ulv_param *ulv = &si_pi->ulv; | |
5600 | ||
5601 | if (ulv->supported) | |
6861c837 | 5602 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? |
841686df MB |
5603 | 0 : -EINVAL; |
5604 | ||
5605 | return 0; | |
5606 | } | |
5607 | ||
5608 | static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, | |
5609 | struct amdgpu_ps *amdgpu_state) | |
5610 | { | |
5611 | const struct si_power_info *si_pi = si_get_pi(adev); | |
5612 | const struct si_ulv_param *ulv = &si_pi->ulv; | |
5613 | const struct si_ps *state = si_get_ps(amdgpu_state); | |
5614 | int i; | |
5615 | ||
5616 | if (state->performance_levels[0].mclk != ulv->pl.mclk) | |
5617 | return false; | |
5618 | ||
5619 | /* XXX validate against display requirements! */ | |
5620 | ||
5621 | for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { | |
5622 | if (adev->clock.current_dispclk <= | |
5623 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { | |
5624 | if (ulv->pl.vddc < | |
5625 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) | |
5626 | return false; | |
5627 | } | |
5628 | } | |
5629 | ||
5630 | if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) | |
5631 | return false; | |
5632 | ||
5633 | return true; | |
5634 | } | |
5635 | ||
5636 | static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, | |
5637 | struct amdgpu_ps *amdgpu_new_state) | |
5638 | { | |
5639 | const struct si_power_info *si_pi = si_get_pi(adev); | |
5640 | const struct si_ulv_param *ulv = &si_pi->ulv; | |
5641 | ||
5642 | if (ulv->supported) { | |
5643 | if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) | |
6861c837 | 5644 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? |
841686df MB |
5645 | 0 : -EINVAL; |
5646 | } | |
5647 | return 0; | |
5648 | } | |
5649 | ||
5650 | static int si_convert_power_state_to_smc(struct amdgpu_device *adev, | |
5651 | struct amdgpu_ps *amdgpu_state, | |
5652 | SISLANDS_SMC_SWSTATE *smc_state) | |
5653 | { | |
5654 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
5655 | struct ni_power_info *ni_pi = ni_get_pi(adev); | |
5656 | struct si_power_info *si_pi = si_get_pi(adev); | |
5657 | struct si_ps *state = si_get_ps(amdgpu_state); | |
5658 | int i, ret; | |
5659 | u32 threshold; | |
5660 | u32 sclk_in_sr = 1350; /* ??? */ | |
5661 | ||
5662 | if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) | |
5663 | return -EINVAL; | |
5664 | ||
5665 | threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; | |
5666 | ||
5667 | if (amdgpu_state->vclk && amdgpu_state->dclk) { | |
5668 | eg_pi->uvd_enabled = true; | |
5669 | if (eg_pi->smu_uvd_hs) | |
5670 | smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; | |
5671 | } else { | |
5672 | eg_pi->uvd_enabled = false; | |
5673 | } | |
5674 | ||
5675 | if (state->dc_compatible) | |
5676 | smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; | |
5677 | ||
5678 | smc_state->levelCount = 0; | |
5679 | for (i = 0; i < state->performance_level_count; i++) { | |
5680 | if (eg_pi->sclk_deep_sleep) { | |
5681 | if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { | |
5682 | if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) | |
5683 | smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; | |
5684 | else | |
5685 | smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; | |
5686 | } | |
5687 | } | |
5688 | ||
5689 | ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], | |
5690 | &smc_state->levels[i]); | |
5691 | smc_state->levels[i].arbRefreshState = | |
5692 | (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); | |
5693 | ||
5694 | if (ret) | |
5695 | return ret; | |
5696 | ||
5697 | if (ni_pi->enable_power_containment) | |
5698 | smc_state->levels[i].displayWatermark = | |
5699 | (state->performance_levels[i].sclk < threshold) ? | |
5700 | PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; | |
5701 | else | |
5702 | smc_state->levels[i].displayWatermark = (i < 2) ? | |
5703 | PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; | |
5704 | ||
5705 | if (eg_pi->dynamic_ac_timing) | |
5706 | smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; | |
5707 | else | |
5708 | smc_state->levels[i].ACIndex = 0; | |
5709 | ||
5710 | smc_state->levelCount++; | |
5711 | } | |
5712 | ||
5713 | si_write_smc_soft_register(adev, | |
5714 | SI_SMC_SOFT_REGISTER_watermark_threshold, | |
5715 | threshold / 512); | |
5716 | ||
5717 | si_populate_smc_sp(adev, amdgpu_state, smc_state); | |
5718 | ||
5719 | ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); | |
5720 | if (ret) | |
5721 | ni_pi->enable_power_containment = false; | |
5722 | ||
5723 | ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); | |
77d318a6 | 5724 | if (ret) |
841686df MB |
5725 | ni_pi->enable_sq_ramping = false; |
5726 | ||
5727 | return si_populate_smc_t(adev, amdgpu_state, smc_state); | |
5728 | } | |
5729 | ||
5730 | static int si_upload_sw_state(struct amdgpu_device *adev, | |
5731 | struct amdgpu_ps *amdgpu_new_state) | |
5732 | { | |
5733 | struct si_power_info *si_pi = si_get_pi(adev); | |
5734 | struct si_ps *new_state = si_get_ps(amdgpu_new_state); | |
5735 | int ret; | |
5736 | u32 address = si_pi->state_table_start + | |
5737 | offsetof(SISLANDS_SMC_STATETABLE, driverState); | |
5738 | u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + | |
5739 | ((new_state->performance_level_count - 1) * | |
5740 | sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); | |
5741 | SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; | |
5742 | ||
5743 | memset(smc_state, 0, state_size); | |
5744 | ||
5745 | ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); | |
5746 | if (ret) | |
5747 | return ret; | |
5748 | ||
6861c837 AD |
5749 | return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, |
5750 | state_size, si_pi->sram_end); | |
841686df MB |
5751 | } |
5752 | ||
5753 | static int si_upload_ulv_state(struct amdgpu_device *adev) | |
5754 | { | |
5755 | struct si_power_info *si_pi = si_get_pi(adev); | |
5756 | struct si_ulv_param *ulv = &si_pi->ulv; | |
5757 | int ret = 0; | |
5758 | ||
5759 | if (ulv->supported && ulv->pl.vddc) { | |
5760 | u32 address = si_pi->state_table_start + | |
5761 | offsetof(SISLANDS_SMC_STATETABLE, ULVState); | |
5762 | SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; | |
5763 | u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); | |
5764 | ||
5765 | memset(smc_state, 0, state_size); | |
5766 | ||
5767 | ret = si_populate_ulv_state(adev, smc_state); | |
5768 | if (!ret) | |
6861c837 AD |
5769 | ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, |
5770 | state_size, si_pi->sram_end); | |
841686df MB |
5771 | } |
5772 | ||
5773 | return ret; | |
5774 | } | |
5775 | ||
5776 | static int si_upload_smc_data(struct amdgpu_device *adev) | |
5777 | { | |
5778 | struct amdgpu_crtc *amdgpu_crtc = NULL; | |
5779 | int i; | |
5780 | ||
5781 | if (adev->pm.dpm.new_active_crtc_count == 0) | |
5782 | return 0; | |
5783 | ||
5784 | for (i = 0; i < adev->mode_info.num_crtc; i++) { | |
5785 | if (adev->pm.dpm.new_active_crtcs & (1 << i)) { | |
5786 | amdgpu_crtc = adev->mode_info.crtcs[i]; | |
5787 | break; | |
5788 | } | |
5789 | } | |
5790 | ||
5791 | if (amdgpu_crtc == NULL) | |
5792 | return 0; | |
5793 | ||
5794 | if (amdgpu_crtc->line_time <= 0) | |
5795 | return 0; | |
5796 | ||
5797 | if (si_write_smc_soft_register(adev, | |
5798 | SI_SMC_SOFT_REGISTER_crtc_index, | |
5799 | amdgpu_crtc->crtc_id) != PPSMC_Result_OK) | |
5800 | return 0; | |
5801 | ||
5802 | if (si_write_smc_soft_register(adev, | |
5803 | SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, | |
5804 | amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK) | |
5805 | return 0; | |
5806 | ||
5807 | if (si_write_smc_soft_register(adev, | |
5808 | SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, | |
5809 | amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK) | |
5810 | return 0; | |
5811 | ||
5812 | return 0; | |
5813 | } | |
5814 | ||
5815 | static int si_set_mc_special_registers(struct amdgpu_device *adev, | |
5816 | struct si_mc_reg_table *table) | |
5817 | { | |
5818 | u8 i, j, k; | |
5819 | u32 temp_reg; | |
5820 | ||
5821 | for (i = 0, j = table->last; i < table->last; i++) { | |
5822 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) | |
5823 | return -EINVAL; | |
5824 | switch (table->mc_reg_address[i].s1) { | |
5825 | case MC_SEQ_MISC1: | |
5826 | temp_reg = RREG32(MC_PMG_CMD_EMRS); | |
5827 | table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; | |
5828 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; | |
5829 | for (k = 0; k < table->num_entries; k++) | |
5830 | table->mc_reg_table_entry[k].mc_data[j] = | |
5831 | ((temp_reg & 0xffff0000)) | | |
5832 | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); | |
5833 | j++; | |
8cdbad98 | 5834 | |
841686df MB |
5835 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
5836 | return -EINVAL; | |
841686df MB |
5837 | temp_reg = RREG32(MC_PMG_CMD_MRS); |
5838 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; | |
5839 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; | |
5840 | for (k = 0; k < table->num_entries; k++) { | |
5841 | table->mc_reg_table_entry[k].mc_data[j] = | |
5842 | (temp_reg & 0xffff0000) | | |
5843 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
770d13b1 | 5844 | if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) |
841686df MB |
5845 | table->mc_reg_table_entry[k].mc_data[j] |= 0x100; |
5846 | } | |
5847 | j++; | |
841686df | 5848 | |
770d13b1 | 5849 | if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { |
8cdbad98 ES |
5850 | if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) |
5851 | return -EINVAL; | |
841686df MB |
5852 | table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; |
5853 | table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; | |
5854 | for (k = 0; k < table->num_entries; k++) | |
5855 | table->mc_reg_table_entry[k].mc_data[j] = | |
5856 | (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; | |
5857 | j++; | |
841686df MB |
5858 | } |
5859 | break; | |
5860 | case MC_SEQ_RESERVE_M: | |
5861 | temp_reg = RREG32(MC_PMG_CMD_MRS1); | |
5862 | table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; | |
5863 | table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; | |
5864 | for(k = 0; k < table->num_entries; k++) | |
5865 | table->mc_reg_table_entry[k].mc_data[j] = | |
5866 | (temp_reg & 0xffff0000) | | |
5867 | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); | |
5868 | j++; | |
841686df MB |
5869 | break; |
5870 | default: | |
5871 | break; | |
5872 | } | |
5873 | } | |
5874 | ||
5875 | table->last = j; | |
5876 | ||
5877 | return 0; | |
5878 | } | |
5879 | ||
5880 | static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) | |
5881 | { | |
5882 | bool result = true; | |
5883 | switch (in_reg) { | |
5884 | case MC_SEQ_RAS_TIMING: | |
5885 | *out_reg = MC_SEQ_RAS_TIMING_LP; | |
5886 | break; | |
77d318a6 | 5887 | case MC_SEQ_CAS_TIMING: |
841686df MB |
5888 | *out_reg = MC_SEQ_CAS_TIMING_LP; |
5889 | break; | |
77d318a6 | 5890 | case MC_SEQ_MISC_TIMING: |
841686df MB |
5891 | *out_reg = MC_SEQ_MISC_TIMING_LP; |
5892 | break; | |
77d318a6 | 5893 | case MC_SEQ_MISC_TIMING2: |
841686df MB |
5894 | *out_reg = MC_SEQ_MISC_TIMING2_LP; |
5895 | break; | |
77d318a6 | 5896 | case MC_SEQ_RD_CTL_D0: |
841686df MB |
5897 | *out_reg = MC_SEQ_RD_CTL_D0_LP; |
5898 | break; | |
77d318a6 | 5899 | case MC_SEQ_RD_CTL_D1: |
841686df MB |
5900 | *out_reg = MC_SEQ_RD_CTL_D1_LP; |
5901 | break; | |
77d318a6 | 5902 | case MC_SEQ_WR_CTL_D0: |
841686df MB |
5903 | *out_reg = MC_SEQ_WR_CTL_D0_LP; |
5904 | break; | |
77d318a6 | 5905 | case MC_SEQ_WR_CTL_D1: |
841686df MB |
5906 | *out_reg = MC_SEQ_WR_CTL_D1_LP; |
5907 | break; | |
77d318a6 | 5908 | case MC_PMG_CMD_EMRS: |
841686df MB |
5909 | *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; |
5910 | break; | |
77d318a6 | 5911 | case MC_PMG_CMD_MRS: |
841686df MB |
5912 | *out_reg = MC_SEQ_PMG_CMD_MRS_LP; |
5913 | break; | |
77d318a6 | 5914 | case MC_PMG_CMD_MRS1: |
841686df MB |
5915 | *out_reg = MC_SEQ_PMG_CMD_MRS1_LP; |
5916 | break; | |
77d318a6 | 5917 | case MC_SEQ_PMG_TIMING: |
841686df MB |
5918 | *out_reg = MC_SEQ_PMG_TIMING_LP; |
5919 | break; | |
77d318a6 | 5920 | case MC_PMG_CMD_MRS2: |
841686df MB |
5921 | *out_reg = MC_SEQ_PMG_CMD_MRS2_LP; |
5922 | break; | |
77d318a6 | 5923 | case MC_SEQ_WR_CTL_2: |
841686df MB |
5924 | *out_reg = MC_SEQ_WR_CTL_2_LP; |
5925 | break; | |
77d318a6 | 5926 | default: |
841686df MB |
5927 | result = false; |
5928 | break; | |
5929 | } | |
5930 | ||
5931 | return result; | |
5932 | } | |
5933 | ||
5934 | static void si_set_valid_flag(struct si_mc_reg_table *table) | |
5935 | { | |
5936 | u8 i, j; | |
5937 | ||
5938 | for (i = 0; i < table->last; i++) { | |
5939 | for (j = 1; j < table->num_entries; j++) { | |
5940 | if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { | |
5941 | table->valid_flag |= 1 << i; | |
5942 | break; | |
5943 | } | |
5944 | } | |
5945 | } | |
5946 | } | |
5947 | ||
5948 | static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) | |
5949 | { | |
5950 | u32 i; | |
5951 | u16 address; | |
5952 | ||
5953 | for (i = 0; i < table->last; i++) | |
5954 | table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? | |
5955 | address : table->mc_reg_address[i].s1; | |
5956 | ||
5957 | } | |
5958 | ||
5959 | static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, | |
5960 | struct si_mc_reg_table *si_table) | |
5961 | { | |
5962 | u8 i, j; | |
5963 | ||
5964 | if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) | |
5965 | return -EINVAL; | |
5966 | if (table->num_entries > MAX_AC_TIMING_ENTRIES) | |
5967 | return -EINVAL; | |
5968 | ||
5969 | for (i = 0; i < table->last; i++) | |
5970 | si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; | |
5971 | si_table->last = table->last; | |
5972 | ||
5973 | for (i = 0; i < table->num_entries; i++) { | |
5974 | si_table->mc_reg_table_entry[i].mclk_max = | |
5975 | table->mc_reg_table_entry[i].mclk_max; | |
5976 | for (j = 0; j < table->last; j++) { | |
5977 | si_table->mc_reg_table_entry[i].mc_data[j] = | |
5978 | table->mc_reg_table_entry[i].mc_data[j]; | |
5979 | } | |
5980 | } | |
5981 | si_table->num_entries = table->num_entries; | |
5982 | ||
5983 | return 0; | |
5984 | } | |
5985 | ||
5986 | static int si_initialize_mc_reg_table(struct amdgpu_device *adev) | |
5987 | { | |
5988 | struct si_power_info *si_pi = si_get_pi(adev); | |
5989 | struct atom_mc_reg_table *table; | |
5990 | struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; | |
5991 | u8 module_index = rv770_get_memory_module_index(adev); | |
5992 | int ret; | |
5993 | ||
5994 | table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); | |
5995 | if (!table) | |
5996 | return -ENOMEM; | |
5997 | ||
5998 | WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); | |
5999 | WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); | |
6000 | WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); | |
6001 | WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); | |
6002 | WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); | |
6003 | WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); | |
6004 | WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); | |
6005 | WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); | |
6006 | WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); | |
6007 | WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); | |
6008 | WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); | |
6009 | WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); | |
6010 | WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); | |
6011 | WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); | |
6012 | ||
77d318a6 TSD |
6013 | ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); |
6014 | if (ret) | |
6015 | goto init_mc_done; | |
841686df | 6016 | |
77d318a6 TSD |
6017 | ret = si_copy_vbios_mc_reg_table(table, si_table); |
6018 | if (ret) | |
6019 | goto init_mc_done; | |
841686df MB |
6020 | |
6021 | si_set_s0_mc_reg_index(si_table); | |
6022 | ||
6023 | ret = si_set_mc_special_registers(adev, si_table); | |
77d318a6 TSD |
6024 | if (ret) |
6025 | goto init_mc_done; | |
841686df MB |
6026 | |
6027 | si_set_valid_flag(si_table); | |
6028 | ||
6029 | init_mc_done: | |
6030 | kfree(table); | |
6031 | ||
6032 | return ret; | |
6033 | ||
6034 | } | |
6035 | ||
6036 | static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, | |
6037 | SMC_SIslands_MCRegisters *mc_reg_table) | |
6038 | { | |
6039 | struct si_power_info *si_pi = si_get_pi(adev); | |
6040 | u32 i, j; | |
6041 | ||
6042 | for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { | |
6043 | if (si_pi->mc_reg_table.valid_flag & (1 << j)) { | |
6044 | if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) | |
6045 | break; | |
6046 | mc_reg_table->address[i].s0 = | |
6047 | cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); | |
6048 | mc_reg_table->address[i].s1 = | |
6049 | cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); | |
6050 | i++; | |
6051 | } | |
6052 | } | |
6053 | mc_reg_table->last = (u8)i; | |
6054 | } | |
6055 | ||
6056 | static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, | |
6057 | SMC_SIslands_MCRegisterSet *data, | |
6058 | u32 num_entries, u32 valid_flag) | |
6059 | { | |
6060 | u32 i, j; | |
6061 | ||
6062 | for(i = 0, j = 0; j < num_entries; j++) { | |
6063 | if (valid_flag & (1 << j)) { | |
6064 | data->value[i] = cpu_to_be32(entry->mc_data[j]); | |
6065 | i++; | |
6066 | } | |
6067 | } | |
6068 | } | |
6069 | ||
6070 | static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, | |
6071 | struct rv7xx_pl *pl, | |
6072 | SMC_SIslands_MCRegisterSet *mc_reg_table_data) | |
6073 | { | |
6074 | struct si_power_info *si_pi = si_get_pi(adev); | |
6075 | u32 i = 0; | |
6076 | ||
6077 | for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { | |
6078 | if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) | |
6079 | break; | |
6080 | } | |
6081 | ||
6082 | if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) | |
6083 | --i; | |
6084 | ||
6085 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], | |
6086 | mc_reg_table_data, si_pi->mc_reg_table.last, | |
6087 | si_pi->mc_reg_table.valid_flag); | |
6088 | } | |
6089 | ||
6090 | static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, | |
6091 | struct amdgpu_ps *amdgpu_state, | |
6092 | SMC_SIslands_MCRegisters *mc_reg_table) | |
6093 | { | |
77d318a6 | 6094 | struct si_ps *state = si_get_ps(amdgpu_state); |
841686df MB |
6095 | int i; |
6096 | ||
6097 | for (i = 0; i < state->performance_level_count; i++) { | |
6098 | si_convert_mc_reg_table_entry_to_smc(adev, | |
6099 | &state->performance_levels[i], | |
6100 | &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); | |
6101 | } | |
6102 | } | |
6103 | ||
6104 | static int si_populate_mc_reg_table(struct amdgpu_device *adev, | |
6105 | struct amdgpu_ps *amdgpu_boot_state) | |
6106 | { | |
6107 | struct si_ps *boot_state = si_get_ps(amdgpu_boot_state); | |
6108 | struct si_power_info *si_pi = si_get_pi(adev); | |
6109 | struct si_ulv_param *ulv = &si_pi->ulv; | |
6110 | SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; | |
6111 | ||
6112 | memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); | |
6113 | ||
6114 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1); | |
6115 | ||
6116 | si_populate_mc_reg_addresses(adev, smc_mc_reg_table); | |
6117 | ||
6118 | si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], | |
6119 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); | |
6120 | ||
6121 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], | |
6122 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], | |
6123 | si_pi->mc_reg_table.last, | |
6124 | si_pi->mc_reg_table.valid_flag); | |
6125 | ||
6126 | if (ulv->supported && ulv->pl.vddc != 0) | |
6127 | si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, | |
6128 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); | |
6129 | else | |
6130 | si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], | |
6131 | &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], | |
6132 | si_pi->mc_reg_table.last, | |
6133 | si_pi->mc_reg_table.valid_flag); | |
6134 | ||
6135 | si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); | |
6136 | ||
6861c837 AD |
6137 | return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, |
6138 | (u8 *)smc_mc_reg_table, | |
6139 | sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); | |
841686df MB |
6140 | } |
6141 | ||
6142 | static int si_upload_mc_reg_table(struct amdgpu_device *adev, | |
6143 | struct amdgpu_ps *amdgpu_new_state) | |
6144 | { | |
77d318a6 | 6145 | struct si_ps *new_state = si_get_ps(amdgpu_new_state); |
841686df MB |
6146 | struct si_power_info *si_pi = si_get_pi(adev); |
6147 | u32 address = si_pi->mc_reg_table_start + | |
6148 | offsetof(SMC_SIslands_MCRegisters, | |
6149 | data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); | |
6150 | SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; | |
6151 | ||
6152 | memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); | |
6153 | ||
6154 | si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); | |
6155 | ||
6861c837 AD |
6156 | return amdgpu_si_copy_bytes_to_smc(adev, address, |
6157 | (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], | |
6158 | sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, | |
6159 | si_pi->sram_end); | |
841686df MB |
6160 | } |
6161 | ||
6162 | static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) | |
6163 | { | |
77d318a6 TSD |
6164 | if (enable) |
6165 | WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); | |
6166 | else | |
6167 | WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); | |
841686df MB |
6168 | } |
6169 | ||
6170 | static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, | |
6171 | struct amdgpu_ps *amdgpu_state) | |
6172 | { | |
77d318a6 | 6173 | struct si_ps *state = si_get_ps(amdgpu_state); |
841686df MB |
6174 | int i; |
6175 | u16 pcie_speed, max_speed = 0; | |
6176 | ||
6177 | for (i = 0; i < state->performance_level_count; i++) { | |
6178 | pcie_speed = state->performance_levels[i].pcie_gen; | |
6179 | if (max_speed < pcie_speed) | |
6180 | max_speed = pcie_speed; | |
6181 | } | |
6182 | return max_speed; | |
6183 | } | |
6184 | ||
6185 | static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) | |
6186 | { | |
6187 | u32 speed_cntl; | |
6188 | ||
6189 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; | |
6190 | speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; | |
6191 | ||
6192 | return (u16)speed_cntl; | |
6193 | } | |
6194 | ||
6195 | static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, | |
6196 | struct amdgpu_ps *amdgpu_new_state, | |
6197 | struct amdgpu_ps *amdgpu_current_state) | |
6198 | { | |
6199 | struct si_power_info *si_pi = si_get_pi(adev); | |
6200 | enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); | |
6201 | enum amdgpu_pcie_gen current_link_speed; | |
6202 | ||
6203 | if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID) | |
6204 | current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state); | |
6205 | else | |
6206 | current_link_speed = si_pi->force_pcie_gen; | |
6207 | ||
6208 | si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; | |
6209 | si_pi->pspp_notify_required = false; | |
6210 | if (target_link_speed > current_link_speed) { | |
6211 | switch (target_link_speed) { | |
6212 | #if defined(CONFIG_ACPI) | |
6213 | case AMDGPU_PCIE_GEN3: | |
6214 | if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) | |
6215 | break; | |
6216 | si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2; | |
6217 | if (current_link_speed == AMDGPU_PCIE_GEN2) | |
6218 | break; | |
6219 | case AMDGPU_PCIE_GEN2: | |
6220 | if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) | |
6221 | break; | |
6222 | #endif | |
6223 | default: | |
6224 | si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); | |
6225 | break; | |
6226 | } | |
6227 | } else { | |
6228 | if (target_link_speed < current_link_speed) | |
6229 | si_pi->pspp_notify_required = true; | |
6230 | } | |
6231 | } | |
6232 | ||
6233 | static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, | |
6234 | struct amdgpu_ps *amdgpu_new_state, | |
6235 | struct amdgpu_ps *amdgpu_current_state) | |
6236 | { | |
6237 | struct si_power_info *si_pi = si_get_pi(adev); | |
6238 | enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); | |
6239 | u8 request; | |
6240 | ||
6241 | if (si_pi->pspp_notify_required) { | |
6242 | if (target_link_speed == AMDGPU_PCIE_GEN3) | |
6243 | request = PCIE_PERF_REQ_PECI_GEN3; | |
6244 | else if (target_link_speed == AMDGPU_PCIE_GEN2) | |
6245 | request = PCIE_PERF_REQ_PECI_GEN2; | |
6246 | else | |
6247 | request = PCIE_PERF_REQ_PECI_GEN1; | |
6248 | ||
6249 | if ((request == PCIE_PERF_REQ_PECI_GEN1) && | |
6250 | (si_get_current_pcie_speed(adev) > 0)) | |
6251 | return; | |
6252 | ||
6253 | #if defined(CONFIG_ACPI) | |
6254 | amdgpu_acpi_pcie_performance_request(adev, request, false); | |
6255 | #endif | |
6256 | } | |
6257 | } | |
6258 | ||
6259 | #if 0 | |
6260 | static int si_ds_request(struct amdgpu_device *adev, | |
6261 | bool ds_status_on, u32 count_write) | |
6262 | { | |
6263 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
6264 | ||
6265 | if (eg_pi->sclk_deep_sleep) { | |
6266 | if (ds_status_on) | |
6861c837 | 6267 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == |
841686df MB |
6268 | PPSMC_Result_OK) ? |
6269 | 0 : -EINVAL; | |
6270 | else | |
6861c837 | 6271 | return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == |
841686df MB |
6272 | PPSMC_Result_OK) ? 0 : -EINVAL; |
6273 | } | |
6274 | return 0; | |
6275 | } | |
6276 | #endif | |
6277 | ||
6278 | static void si_set_max_cu_value(struct amdgpu_device *adev) | |
6279 | { | |
6280 | struct si_power_info *si_pi = si_get_pi(adev); | |
6281 | ||
6282 | if (adev->asic_type == CHIP_VERDE) { | |
6283 | switch (adev->pdev->device) { | |
6284 | case 0x6820: | |
6285 | case 0x6825: | |
6286 | case 0x6821: | |
6287 | case 0x6823: | |
6288 | case 0x6827: | |
6289 | si_pi->max_cu = 10; | |
6290 | break; | |
6291 | case 0x682D: | |
6292 | case 0x6824: | |
6293 | case 0x682F: | |
6294 | case 0x6826: | |
6295 | si_pi->max_cu = 8; | |
6296 | break; | |
6297 | case 0x6828: | |
6298 | case 0x6830: | |
6299 | case 0x6831: | |
6300 | case 0x6838: | |
6301 | case 0x6839: | |
6302 | case 0x683D: | |
6303 | si_pi->max_cu = 10; | |
6304 | break; | |
6305 | case 0x683B: | |
6306 | case 0x683F: | |
6307 | case 0x6829: | |
6308 | si_pi->max_cu = 8; | |
6309 | break; | |
6310 | default: | |
6311 | si_pi->max_cu = 0; | |
6312 | break; | |
6313 | } | |
6314 | } else { | |
6315 | si_pi->max_cu = 0; | |
6316 | } | |
6317 | } | |
6318 | ||
6319 | static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, | |
6320 | struct amdgpu_clock_voltage_dependency_table *table) | |
6321 | { | |
6322 | u32 i; | |
6323 | int j; | |
6324 | u16 leakage_voltage; | |
6325 | ||
6326 | if (table) { | |
6327 | for (i = 0; i < table->count; i++) { | |
6328 | switch (si_get_leakage_voltage_from_leakage_index(adev, | |
6329 | table->entries[i].v, | |
6330 | &leakage_voltage)) { | |
6331 | case 0: | |
6332 | table->entries[i].v = leakage_voltage; | |
6333 | break; | |
6334 | case -EAGAIN: | |
6335 | return -EINVAL; | |
6336 | case -EINVAL: | |
6337 | default: | |
6338 | break; | |
6339 | } | |
6340 | } | |
6341 | ||
6342 | for (j = (table->count - 2); j >= 0; j--) { | |
6343 | table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? | |
6344 | table->entries[j].v : table->entries[j + 1].v; | |
6345 | } | |
6346 | } | |
6347 | return 0; | |
6348 | } | |
6349 | ||
6350 | static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) | |
6351 | { | |
6352 | int ret = 0; | |
6353 | ||
6354 | ret = si_patch_single_dependency_table_based_on_leakage(adev, | |
6355 | &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); | |
ad2473af TSD |
6356 | if (ret) |
6357 | DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); | |
841686df MB |
6358 | ret = si_patch_single_dependency_table_based_on_leakage(adev, |
6359 | &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); | |
ad2473af TSD |
6360 | if (ret) |
6361 | DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); | |
841686df MB |
6362 | ret = si_patch_single_dependency_table_based_on_leakage(adev, |
6363 | &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); | |
ad2473af TSD |
6364 | if (ret) |
6365 | DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); | |
841686df MB |
6366 | return ret; |
6367 | } | |
6368 | ||
6369 | static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, | |
6370 | struct amdgpu_ps *amdgpu_new_state, | |
6371 | struct amdgpu_ps *amdgpu_current_state) | |
6372 | { | |
6373 | u32 lane_width; | |
6374 | u32 new_lane_width = | |
41212e2f | 6375 | ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
841686df | 6376 | u32 current_lane_width = |
41212e2f | 6377 | ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
841686df MB |
6378 | |
6379 | if (new_lane_width != current_lane_width) { | |
6380 | amdgpu_set_pcie_lanes(adev, new_lane_width); | |
6381 | lane_width = amdgpu_get_pcie_lanes(adev); | |
6382 | si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); | |
6383 | } | |
6384 | } | |
6385 | ||
6386 | static void si_dpm_setup_asic(struct amdgpu_device *adev) | |
6387 | { | |
6388 | si_read_clock_registers(adev); | |
6389 | si_enable_acpi_power_management(adev); | |
6390 | } | |
6391 | ||
6392 | static int si_thermal_enable_alert(struct amdgpu_device *adev, | |
6393 | bool enable) | |
6394 | { | |
6395 | u32 thermal_int = RREG32(CG_THERMAL_INT); | |
6396 | ||
6397 | if (enable) { | |
6398 | PPSMC_Result result; | |
6399 | ||
6400 | thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); | |
6401 | WREG32(CG_THERMAL_INT, thermal_int); | |
6861c837 | 6402 | result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); |
841686df MB |
6403 | if (result != PPSMC_Result_OK) { |
6404 | DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); | |
6405 | return -EINVAL; | |
6406 | } | |
6407 | } else { | |
6408 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; | |
6409 | WREG32(CG_THERMAL_INT, thermal_int); | |
6410 | } | |
6411 | ||
6412 | return 0; | |
6413 | } | |
6414 | ||
6415 | static int si_thermal_set_temperature_range(struct amdgpu_device *adev, | |
6416 | int min_temp, int max_temp) | |
6417 | { | |
6418 | int low_temp = 0 * 1000; | |
6419 | int high_temp = 255 * 1000; | |
6420 | ||
6421 | if (low_temp < min_temp) | |
6422 | low_temp = min_temp; | |
6423 | if (high_temp > max_temp) | |
6424 | high_temp = max_temp; | |
6425 | if (high_temp < low_temp) { | |
6426 | DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); | |
6427 | return -EINVAL; | |
6428 | } | |
6429 | ||
6430 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); | |
6431 | WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); | |
6432 | WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); | |
6433 | ||
6434 | adev->pm.dpm.thermal.min_temp = low_temp; | |
6435 | adev->pm.dpm.thermal.max_temp = high_temp; | |
6436 | ||
6437 | return 0; | |
6438 | } | |
6439 | ||
6440 | static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) | |
6441 | { | |
6442 | struct si_power_info *si_pi = si_get_pi(adev); | |
6443 | u32 tmp; | |
6444 | ||
6445 | if (si_pi->fan_ctrl_is_in_default_mode) { | |
6446 | tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; | |
6447 | si_pi->fan_ctrl_default_mode = tmp; | |
6448 | tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; | |
6449 | si_pi->t_min = tmp; | |
6450 | si_pi->fan_ctrl_is_in_default_mode = false; | |
6451 | } | |
6452 | ||
6453 | tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; | |
6454 | tmp |= TMIN(0); | |
6455 | WREG32(CG_FDO_CTRL2, tmp); | |
6456 | ||
6457 | tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; | |
6458 | tmp |= FDO_PWM_MODE(mode); | |
6459 | WREG32(CG_FDO_CTRL2, tmp); | |
6460 | } | |
6461 | ||
6462 | static int si_thermal_setup_fan_table(struct amdgpu_device *adev) | |
6463 | { | |
6464 | struct si_power_info *si_pi = si_get_pi(adev); | |
6465 | PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; | |
6466 | u32 duty100; | |
6467 | u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; | |
6468 | u16 fdo_min, slope1, slope2; | |
6469 | u32 reference_clock, tmp; | |
6470 | int ret; | |
6471 | u64 tmp64; | |
6472 | ||
6473 | if (!si_pi->fan_table_start) { | |
6474 | adev->pm.dpm.fan.ucode_fan_control = false; | |
6475 | return 0; | |
6476 | } | |
6477 | ||
6478 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; | |
6479 | ||
6480 | if (duty100 == 0) { | |
6481 | adev->pm.dpm.fan.ucode_fan_control = false; | |
6482 | return 0; | |
6483 | } | |
6484 | ||
6485 | tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; | |
6486 | do_div(tmp64, 10000); | |
6487 | fdo_min = (u16)tmp64; | |
6488 | ||
6489 | t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; | |
6490 | t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; | |
6491 | ||
6492 | pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; | |
6493 | pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; | |
6494 | ||
6495 | slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); | |
6496 | slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); | |
6497 | ||
6498 | fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); | |
6499 | fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); | |
6500 | fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); | |
841686df MB |
6501 | fan_table.slope1 = cpu_to_be16(slope1); |
6502 | fan_table.slope2 = cpu_to_be16(slope2); | |
841686df | 6503 | fan_table.fdo_min = cpu_to_be16(fdo_min); |
841686df | 6504 | fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); |
841686df | 6505 | fan_table.hys_up = cpu_to_be16(1); |
841686df | 6506 | fan_table.hys_slope = cpu_to_be16(1); |
841686df | 6507 | fan_table.temp_resp_lim = cpu_to_be16(5); |
841686df MB |
6508 | reference_clock = amdgpu_asic_get_xclk(adev); |
6509 | ||
6510 | fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * | |
6511 | reference_clock) / 1600); | |
841686df MB |
6512 | fan_table.fdo_max = cpu_to_be16((u16)duty100); |
6513 | ||
6514 | tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; | |
6515 | fan_table.temp_src = (uint8_t)tmp; | |
6516 | ||
6861c837 AD |
6517 | ret = amdgpu_si_copy_bytes_to_smc(adev, |
6518 | si_pi->fan_table_start, | |
6519 | (u8 *)(&fan_table), | |
6520 | sizeof(fan_table), | |
6521 | si_pi->sram_end); | |
841686df MB |
6522 | |
6523 | if (ret) { | |
6524 | DRM_ERROR("Failed to load fan table to the SMC."); | |
6525 | adev->pm.dpm.fan.ucode_fan_control = false; | |
6526 | } | |
6527 | ||
ad2473af | 6528 | return ret; |
841686df MB |
6529 | } |
6530 | ||
6531 | static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) | |
6532 | { | |
6533 | struct si_power_info *si_pi = si_get_pi(adev); | |
6534 | PPSMC_Result ret; | |
6535 | ||
6861c837 | 6536 | ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); |
841686df MB |
6537 | if (ret == PPSMC_Result_OK) { |
6538 | si_pi->fan_is_controlled_by_smc = true; | |
6539 | return 0; | |
6540 | } else { | |
6541 | return -EINVAL; | |
6542 | } | |
6543 | } | |
6544 | ||
6545 | static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) | |
6546 | { | |
6547 | struct si_power_info *si_pi = si_get_pi(adev); | |
6548 | PPSMC_Result ret; | |
6549 | ||
6861c837 | 6550 | ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); |
841686df MB |
6551 | |
6552 | if (ret == PPSMC_Result_OK) { | |
6553 | si_pi->fan_is_controlled_by_smc = false; | |
6554 | return 0; | |
6555 | } else { | |
6556 | return -EINVAL; | |
6557 | } | |
6558 | } | |
6559 | ||
cfa289fd | 6560 | static int si_dpm_get_fan_speed_percent(void *handle, |
841686df MB |
6561 | u32 *speed) |
6562 | { | |
6563 | u32 duty, duty100; | |
6564 | u64 tmp64; | |
cfa289fd | 6565 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
6566 | |
6567 | if (adev->pm.no_fan) | |
6568 | return -ENOENT; | |
6569 | ||
6570 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; | |
6571 | duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; | |
6572 | ||
6573 | if (duty100 == 0) | |
6574 | return -EINVAL; | |
6575 | ||
6576 | tmp64 = (u64)duty * 100; | |
6577 | do_div(tmp64, duty100); | |
6578 | *speed = (u32)tmp64; | |
6579 | ||
6580 | if (*speed > 100) | |
6581 | *speed = 100; | |
6582 | ||
6583 | return 0; | |
6584 | } | |
6585 | ||
cfa289fd | 6586 | static int si_dpm_set_fan_speed_percent(void *handle, |
841686df MB |
6587 | u32 speed) |
6588 | { | |
cfa289fd | 6589 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
6590 | struct si_power_info *si_pi = si_get_pi(adev); |
6591 | u32 tmp; | |
6592 | u32 duty, duty100; | |
6593 | u64 tmp64; | |
6594 | ||
6595 | if (adev->pm.no_fan) | |
6596 | return -ENOENT; | |
6597 | ||
6598 | if (si_pi->fan_is_controlled_by_smc) | |
6599 | return -EINVAL; | |
6600 | ||
6601 | if (speed > 100) | |
6602 | return -EINVAL; | |
6603 | ||
6604 | duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; | |
6605 | ||
6606 | if (duty100 == 0) | |
6607 | return -EINVAL; | |
6608 | ||
6609 | tmp64 = (u64)speed * duty100; | |
6610 | do_div(tmp64, 100); | |
6611 | duty = (u32)tmp64; | |
6612 | ||
6613 | tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; | |
6614 | tmp |= FDO_STATIC_DUTY(duty); | |
6615 | WREG32(CG_FDO_CTRL0, tmp); | |
6616 | ||
6617 | return 0; | |
6618 | } | |
6619 | ||
cfa289fd | 6620 | static void si_dpm_set_fan_control_mode(void *handle, u32 mode) |
841686df | 6621 | { |
cfa289fd RZ |
6622 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
6623 | ||
841686df MB |
6624 | if (mode) { |
6625 | /* stop auto-manage */ | |
6626 | if (adev->pm.dpm.fan.ucode_fan_control) | |
6627 | si_fan_ctrl_stop_smc_fan_control(adev); | |
6628 | si_fan_ctrl_set_static_mode(adev, mode); | |
6629 | } else { | |
6630 | /* restart auto-manage */ | |
6631 | if (adev->pm.dpm.fan.ucode_fan_control) | |
6632 | si_thermal_start_smc_fan_control(adev); | |
6633 | else | |
6634 | si_fan_ctrl_set_default_mode(adev); | |
6635 | } | |
6636 | } | |
6637 | ||
cfa289fd | 6638 | static u32 si_dpm_get_fan_control_mode(void *handle) |
841686df | 6639 | { |
cfa289fd | 6640 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
6641 | struct si_power_info *si_pi = si_get_pi(adev); |
6642 | u32 tmp; | |
6643 | ||
6644 | if (si_pi->fan_is_controlled_by_smc) | |
6645 | return 0; | |
6646 | ||
6647 | tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; | |
6648 | return (tmp >> FDO_PWM_MODE_SHIFT); | |
6649 | } | |
6650 | ||
6651 | #if 0 | |
6652 | static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, | |
6653 | u32 *speed) | |
6654 | { | |
6655 | u32 tach_period; | |
6656 | u32 xclk = amdgpu_asic_get_xclk(adev); | |
6657 | ||
6658 | if (adev->pm.no_fan) | |
6659 | return -ENOENT; | |
6660 | ||
6661 | if (adev->pm.fan_pulses_per_revolution == 0) | |
6662 | return -ENOENT; | |
6663 | ||
6664 | tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; | |
6665 | if (tach_period == 0) | |
6666 | return -ENOENT; | |
6667 | ||
6668 | *speed = 60 * xclk * 10000 / tach_period; | |
6669 | ||
6670 | return 0; | |
6671 | } | |
6672 | ||
6673 | static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, | |
6674 | u32 speed) | |
6675 | { | |
6676 | u32 tach_period, tmp; | |
6677 | u32 xclk = amdgpu_asic_get_xclk(adev); | |
6678 | ||
6679 | if (adev->pm.no_fan) | |
6680 | return -ENOENT; | |
6681 | ||
6682 | if (adev->pm.fan_pulses_per_revolution == 0) | |
6683 | return -ENOENT; | |
6684 | ||
6685 | if ((speed < adev->pm.fan_min_rpm) || | |
6686 | (speed > adev->pm.fan_max_rpm)) | |
6687 | return -EINVAL; | |
6688 | ||
6689 | if (adev->pm.dpm.fan.ucode_fan_control) | |
6690 | si_fan_ctrl_stop_smc_fan_control(adev); | |
6691 | ||
6692 | tach_period = 60 * xclk * 10000 / (8 * speed); | |
6693 | tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; | |
6694 | tmp |= TARGET_PERIOD(tach_period); | |
6695 | WREG32(CG_TACH_CTRL, tmp); | |
6696 | ||
6697 | si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); | |
6698 | ||
6699 | return 0; | |
6700 | } | |
6701 | #endif | |
6702 | ||
6703 | static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) | |
6704 | { | |
6705 | struct si_power_info *si_pi = si_get_pi(adev); | |
6706 | u32 tmp; | |
6707 | ||
6708 | if (!si_pi->fan_ctrl_is_in_default_mode) { | |
6709 | tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; | |
6710 | tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); | |
6711 | WREG32(CG_FDO_CTRL2, tmp); | |
6712 | ||
6713 | tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; | |
6714 | tmp |= TMIN(si_pi->t_min); | |
6715 | WREG32(CG_FDO_CTRL2, tmp); | |
6716 | si_pi->fan_ctrl_is_in_default_mode = true; | |
6717 | } | |
6718 | } | |
6719 | ||
6720 | static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) | |
6721 | { | |
6722 | if (adev->pm.dpm.fan.ucode_fan_control) { | |
6723 | si_fan_ctrl_start_smc_fan_control(adev); | |
6724 | si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); | |
6725 | } | |
6726 | } | |
6727 | ||
6728 | static void si_thermal_initialize(struct amdgpu_device *adev) | |
6729 | { | |
6730 | u32 tmp; | |
6731 | ||
6732 | if (adev->pm.fan_pulses_per_revolution) { | |
6733 | tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; | |
6734 | tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1); | |
6735 | WREG32(CG_TACH_CTRL, tmp); | |
6736 | } | |
6737 | ||
6738 | tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; | |
6739 | tmp |= TACH_PWM_RESP_RATE(0x28); | |
6740 | WREG32(CG_FDO_CTRL2, tmp); | |
6741 | } | |
6742 | ||
6743 | static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) | |
6744 | { | |
6745 | int ret; | |
6746 | ||
6747 | si_thermal_initialize(adev); | |
6748 | ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); | |
6749 | if (ret) | |
6750 | return ret; | |
6751 | ret = si_thermal_enable_alert(adev, true); | |
6752 | if (ret) | |
6753 | return ret; | |
6754 | if (adev->pm.dpm.fan.ucode_fan_control) { | |
6755 | ret = si_halt_smc(adev); | |
6756 | if (ret) | |
6757 | return ret; | |
6758 | ret = si_thermal_setup_fan_table(adev); | |
6759 | if (ret) | |
6760 | return ret; | |
6761 | ret = si_resume_smc(adev); | |
6762 | if (ret) | |
6763 | return ret; | |
6764 | si_thermal_start_smc_fan_control(adev); | |
6765 | } | |
6766 | ||
6767 | return 0; | |
6768 | } | |
6769 | ||
6770 | static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) | |
6771 | { | |
6772 | if (!adev->pm.no_fan) { | |
6773 | si_fan_ctrl_set_default_mode(adev); | |
6774 | si_fan_ctrl_stop_smc_fan_control(adev); | |
6775 | } | |
6776 | } | |
6777 | ||
6778 | static int si_dpm_enable(struct amdgpu_device *adev) | |
6779 | { | |
6780 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
6781 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
6782 | struct si_power_info *si_pi = si_get_pi(adev); | |
6783 | struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; | |
6784 | int ret; | |
6785 | ||
6861c837 | 6786 | if (amdgpu_si_is_smc_running(adev)) |
841686df MB |
6787 | return -EINVAL; |
6788 | if (pi->voltage_control || si_pi->voltage_control_svi2) | |
6789 | si_enable_voltage_control(adev, true); | |
6790 | if (pi->mvdd_control) | |
6791 | si_get_mvdd_configuration(adev); | |
6792 | if (pi->voltage_control || si_pi->voltage_control_svi2) { | |
6793 | ret = si_construct_voltage_tables(adev); | |
6794 | if (ret) { | |
6795 | DRM_ERROR("si_construct_voltage_tables failed\n"); | |
6796 | return ret; | |
6797 | } | |
6798 | } | |
6799 | if (eg_pi->dynamic_ac_timing) { | |
6800 | ret = si_initialize_mc_reg_table(adev); | |
6801 | if (ret) | |
6802 | eg_pi->dynamic_ac_timing = false; | |
6803 | } | |
6804 | if (pi->dynamic_ss) | |
6805 | si_enable_spread_spectrum(adev, true); | |
6806 | if (pi->thermal_protection) | |
6807 | si_enable_thermal_protection(adev, true); | |
6808 | si_setup_bsp(adev); | |
6809 | si_program_git(adev); | |
6810 | si_program_tp(adev); | |
6811 | si_program_tpp(adev); | |
6812 | si_program_sstp(adev); | |
6813 | si_enable_display_gap(adev); | |
6814 | si_program_vc(adev); | |
6815 | ret = si_upload_firmware(adev); | |
6816 | if (ret) { | |
6817 | DRM_ERROR("si_upload_firmware failed\n"); | |
6818 | return ret; | |
6819 | } | |
6820 | ret = si_process_firmware_header(adev); | |
6821 | if (ret) { | |
6822 | DRM_ERROR("si_process_firmware_header failed\n"); | |
6823 | return ret; | |
6824 | } | |
6825 | ret = si_initial_switch_from_arb_f0_to_f1(adev); | |
6826 | if (ret) { | |
6827 | DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); | |
6828 | return ret; | |
6829 | } | |
6830 | ret = si_init_smc_table(adev); | |
6831 | if (ret) { | |
6832 | DRM_ERROR("si_init_smc_table failed\n"); | |
6833 | return ret; | |
6834 | } | |
6835 | ret = si_init_smc_spll_table(adev); | |
6836 | if (ret) { | |
6837 | DRM_ERROR("si_init_smc_spll_table failed\n"); | |
6838 | return ret; | |
6839 | } | |
6840 | ret = si_init_arb_table_index(adev); | |
6841 | if (ret) { | |
6842 | DRM_ERROR("si_init_arb_table_index failed\n"); | |
6843 | return ret; | |
6844 | } | |
6845 | if (eg_pi->dynamic_ac_timing) { | |
6846 | ret = si_populate_mc_reg_table(adev, boot_ps); | |
6847 | if (ret) { | |
6848 | DRM_ERROR("si_populate_mc_reg_table failed\n"); | |
6849 | return ret; | |
6850 | } | |
6851 | } | |
6852 | ret = si_initialize_smc_cac_tables(adev); | |
6853 | if (ret) { | |
6854 | DRM_ERROR("si_initialize_smc_cac_tables failed\n"); | |
6855 | return ret; | |
6856 | } | |
6857 | ret = si_initialize_hardware_cac_manager(adev); | |
6858 | if (ret) { | |
6859 | DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); | |
6860 | return ret; | |
6861 | } | |
6862 | ret = si_initialize_smc_dte_tables(adev); | |
6863 | if (ret) { | |
6864 | DRM_ERROR("si_initialize_smc_dte_tables failed\n"); | |
6865 | return ret; | |
6866 | } | |
6867 | ret = si_populate_smc_tdp_limits(adev, boot_ps); | |
6868 | if (ret) { | |
6869 | DRM_ERROR("si_populate_smc_tdp_limits failed\n"); | |
6870 | return ret; | |
6871 | } | |
6872 | ret = si_populate_smc_tdp_limits_2(adev, boot_ps); | |
6873 | if (ret) { | |
6874 | DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); | |
6875 | return ret; | |
6876 | } | |
6877 | si_program_response_times(adev); | |
6878 | si_program_ds_registers(adev); | |
6879 | si_dpm_start_smc(adev); | |
6880 | ret = si_notify_smc_display_change(adev, false); | |
6881 | if (ret) { | |
6882 | DRM_ERROR("si_notify_smc_display_change failed\n"); | |
6883 | return ret; | |
6884 | } | |
6885 | si_enable_sclk_control(adev, true); | |
6886 | si_start_dpm(adev); | |
6887 | ||
6888 | si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true); | |
841686df | 6889 | si_thermal_start_thermal_controller(adev); |
841686df MB |
6890 | |
6891 | return 0; | |
6892 | } | |
6893 | ||
6894 | static int si_set_temperature_range(struct amdgpu_device *adev) | |
6895 | { | |
6896 | int ret; | |
6897 | ||
6898 | ret = si_thermal_enable_alert(adev, false); | |
6899 | if (ret) | |
6900 | return ret; | |
6901 | ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); | |
6902 | if (ret) | |
6903 | return ret; | |
6904 | ret = si_thermal_enable_alert(adev, true); | |
6905 | if (ret) | |
6906 | return ret; | |
6907 | ||
6908 | return ret; | |
6909 | } | |
6910 | ||
6911 | static void si_dpm_disable(struct amdgpu_device *adev) | |
6912 | { | |
6913 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
6914 | struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; | |
6915 | ||
6861c837 | 6916 | if (!amdgpu_si_is_smc_running(adev)) |
841686df MB |
6917 | return; |
6918 | si_thermal_stop_thermal_controller(adev); | |
6919 | si_disable_ulv(adev); | |
6920 | si_clear_vc(adev); | |
6921 | if (pi->thermal_protection) | |
6922 | si_enable_thermal_protection(adev, false); | |
6923 | si_enable_power_containment(adev, boot_ps, false); | |
6924 | si_enable_smc_cac(adev, boot_ps, false); | |
6925 | si_enable_spread_spectrum(adev, false); | |
6926 | si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false); | |
6927 | si_stop_dpm(adev); | |
6928 | si_reset_to_default(adev); | |
6929 | si_dpm_stop_smc(adev); | |
6930 | si_force_switch_to_arb_f0(adev); | |
6931 | ||
6932 | ni_update_current_ps(adev, boot_ps); | |
6933 | } | |
6934 | ||
cfa289fd | 6935 | static int si_dpm_pre_set_power_state(void *handle) |
841686df | 6936 | { |
cfa289fd | 6937 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
6938 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
6939 | struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; | |
6940 | struct amdgpu_ps *new_ps = &requested_ps; | |
6941 | ||
6942 | ni_update_requested_ps(adev, new_ps); | |
841686df MB |
6943 | si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); |
6944 | ||
6945 | return 0; | |
6946 | } | |
6947 | ||
6948 | static int si_power_control_set_level(struct amdgpu_device *adev) | |
6949 | { | |
6950 | struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; | |
6951 | int ret; | |
6952 | ||
6953 | ret = si_restrict_performance_levels_before_switch(adev); | |
6954 | if (ret) | |
6955 | return ret; | |
6956 | ret = si_halt_smc(adev); | |
6957 | if (ret) | |
6958 | return ret; | |
6959 | ret = si_populate_smc_tdp_limits(adev, new_ps); | |
6960 | if (ret) | |
6961 | return ret; | |
6962 | ret = si_populate_smc_tdp_limits_2(adev, new_ps); | |
6963 | if (ret) | |
6964 | return ret; | |
6965 | ret = si_resume_smc(adev); | |
6966 | if (ret) | |
6967 | return ret; | |
6968 | ret = si_set_sw_state(adev); | |
6969 | if (ret) | |
6970 | return ret; | |
6971 | return 0; | |
6972 | } | |
6973 | ||
cfa289fd | 6974 | static int si_dpm_set_power_state(void *handle) |
841686df | 6975 | { |
cfa289fd | 6976 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
6977 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
6978 | struct amdgpu_ps *new_ps = &eg_pi->requested_rps; | |
6979 | struct amdgpu_ps *old_ps = &eg_pi->current_rps; | |
6980 | int ret; | |
6981 | ||
6982 | ret = si_disable_ulv(adev); | |
6983 | if (ret) { | |
6984 | DRM_ERROR("si_disable_ulv failed\n"); | |
6985 | return ret; | |
6986 | } | |
6987 | ret = si_restrict_performance_levels_before_switch(adev); | |
6988 | if (ret) { | |
6989 | DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); | |
6990 | return ret; | |
6991 | } | |
6992 | if (eg_pi->pcie_performance_request) | |
6993 | si_request_link_speed_change_before_state_change(adev, new_ps, old_ps); | |
6994 | ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps); | |
6995 | ret = si_enable_power_containment(adev, new_ps, false); | |
6996 | if (ret) { | |
6997 | DRM_ERROR("si_enable_power_containment failed\n"); | |
6998 | return ret; | |
6999 | } | |
7000 | ret = si_enable_smc_cac(adev, new_ps, false); | |
7001 | if (ret) { | |
7002 | DRM_ERROR("si_enable_smc_cac failed\n"); | |
7003 | return ret; | |
7004 | } | |
7005 | ret = si_halt_smc(adev); | |
7006 | if (ret) { | |
7007 | DRM_ERROR("si_halt_smc failed\n"); | |
7008 | return ret; | |
7009 | } | |
7010 | ret = si_upload_sw_state(adev, new_ps); | |
7011 | if (ret) { | |
7012 | DRM_ERROR("si_upload_sw_state failed\n"); | |
7013 | return ret; | |
7014 | } | |
7015 | ret = si_upload_smc_data(adev); | |
7016 | if (ret) { | |
7017 | DRM_ERROR("si_upload_smc_data failed\n"); | |
7018 | return ret; | |
7019 | } | |
7020 | ret = si_upload_ulv_state(adev); | |
7021 | if (ret) { | |
7022 | DRM_ERROR("si_upload_ulv_state failed\n"); | |
7023 | return ret; | |
7024 | } | |
7025 | if (eg_pi->dynamic_ac_timing) { | |
7026 | ret = si_upload_mc_reg_table(adev, new_ps); | |
7027 | if (ret) { | |
7028 | DRM_ERROR("si_upload_mc_reg_table failed\n"); | |
7029 | return ret; | |
7030 | } | |
7031 | } | |
7032 | ret = si_program_memory_timing_parameters(adev, new_ps); | |
7033 | if (ret) { | |
7034 | DRM_ERROR("si_program_memory_timing_parameters failed\n"); | |
7035 | return ret; | |
7036 | } | |
7037 | si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps); | |
7038 | ||
7039 | ret = si_resume_smc(adev); | |
7040 | if (ret) { | |
7041 | DRM_ERROR("si_resume_smc failed\n"); | |
7042 | return ret; | |
7043 | } | |
7044 | ret = si_set_sw_state(adev); | |
7045 | if (ret) { | |
7046 | DRM_ERROR("si_set_sw_state failed\n"); | |
7047 | return ret; | |
7048 | } | |
7049 | ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); | |
7050 | if (eg_pi->pcie_performance_request) | |
7051 | si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); | |
7052 | ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps); | |
7053 | if (ret) { | |
7054 | DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); | |
7055 | return ret; | |
7056 | } | |
7057 | ret = si_enable_smc_cac(adev, new_ps, true); | |
7058 | if (ret) { | |
7059 | DRM_ERROR("si_enable_smc_cac failed\n"); | |
7060 | return ret; | |
7061 | } | |
7062 | ret = si_enable_power_containment(adev, new_ps, true); | |
7063 | if (ret) { | |
7064 | DRM_ERROR("si_enable_power_containment failed\n"); | |
7065 | return ret; | |
7066 | } | |
7067 | ||
7068 | ret = si_power_control_set_level(adev); | |
7069 | if (ret) { | |
7070 | DRM_ERROR("si_power_control_set_level failed\n"); | |
7071 | return ret; | |
7072 | } | |
7073 | ||
7074 | return 0; | |
7075 | } | |
7076 | ||
cfa289fd | 7077 | static void si_dpm_post_set_power_state(void *handle) |
841686df | 7078 | { |
cfa289fd | 7079 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
7080 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
7081 | struct amdgpu_ps *new_ps = &eg_pi->requested_rps; | |
7082 | ||
7083 | ni_update_current_ps(adev, new_ps); | |
7084 | } | |
7085 | ||
7086 | #if 0 | |
7087 | void si_dpm_reset_asic(struct amdgpu_device *adev) | |
7088 | { | |
7089 | si_restrict_performance_levels_before_switch(adev); | |
7090 | si_disable_ulv(adev); | |
7091 | si_set_boot_state(adev); | |
7092 | } | |
7093 | #endif | |
7094 | ||
cfa289fd | 7095 | static void si_dpm_display_configuration_changed(void *handle) |
841686df | 7096 | { |
cfa289fd RZ |
7097 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7098 | ||
841686df MB |
7099 | si_program_display_gap(adev); |
7100 | } | |
7101 | ||
7102 | ||
7103 | static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, | |
7104 | struct amdgpu_ps *rps, | |
7105 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, | |
7106 | u8 table_rev) | |
7107 | { | |
7108 | rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); | |
7109 | rps->class = le16_to_cpu(non_clock_info->usClassification); | |
7110 | rps->class2 = le16_to_cpu(non_clock_info->usClassification2); | |
7111 | ||
7112 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { | |
7113 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); | |
7114 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); | |
7115 | } else if (r600_is_uvd_state(rps->class, rps->class2)) { | |
7116 | rps->vclk = RV770_DEFAULT_VCLK_FREQ; | |
7117 | rps->dclk = RV770_DEFAULT_DCLK_FREQ; | |
7118 | } else { | |
7119 | rps->vclk = 0; | |
7120 | rps->dclk = 0; | |
7121 | } | |
7122 | ||
7123 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) | |
7124 | adev->pm.dpm.boot_ps = rps; | |
7125 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | |
7126 | adev->pm.dpm.uvd_ps = rps; | |
7127 | } | |
7128 | ||
7129 | static void si_parse_pplib_clock_info(struct amdgpu_device *adev, | |
7130 | struct amdgpu_ps *rps, int index, | |
7131 | union pplib_clock_info *clock_info) | |
7132 | { | |
7133 | struct rv7xx_power_info *pi = rv770_get_pi(adev); | |
7134 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); | |
7135 | struct si_power_info *si_pi = si_get_pi(adev); | |
7136 | struct si_ps *ps = si_get_ps(rps); | |
7137 | u16 leakage_voltage; | |
7138 | struct rv7xx_pl *pl = &ps->performance_levels[index]; | |
7139 | int ret; | |
7140 | ||
7141 | ps->performance_level_count = index + 1; | |
7142 | ||
7143 | pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); | |
7144 | pl->sclk |= clock_info->si.ucEngineClockHigh << 16; | |
7145 | pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); | |
7146 | pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; | |
7147 | ||
7148 | pl->vddc = le16_to_cpu(clock_info->si.usVDDC); | |
7149 | pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); | |
7150 | pl->flags = le32_to_cpu(clock_info->si.ulFlags); | |
0bf67185 AD |
7151 | pl->pcie_gen = amdgpu_get_pcie_gen_support(adev, |
7152 | si_pi->sys_pcie_mask, | |
7153 | si_pi->boot_pcie_gen, | |
7154 | clock_info->si.ucPCIEGen); | |
841686df MB |
7155 | |
7156 | /* patch up vddc if necessary */ | |
7157 | ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, | |
7158 | &leakage_voltage); | |
7159 | if (ret == 0) | |
7160 | pl->vddc = leakage_voltage; | |
7161 | ||
7162 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { | |
7163 | pi->acpi_vddc = pl->vddc; | |
7164 | eg_pi->acpi_vddci = pl->vddci; | |
7165 | si_pi->acpi_pcie_gen = pl->pcie_gen; | |
7166 | } | |
7167 | ||
7168 | if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && | |
7169 | index == 0) { | |
7170 | /* XXX disable for A0 tahiti */ | |
7171 | si_pi->ulv.supported = false; | |
7172 | si_pi->ulv.pl = *pl; | |
7173 | si_pi->ulv.one_pcie_lane_in_ulv = false; | |
7174 | si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; | |
7175 | si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; | |
7176 | si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; | |
7177 | } | |
7178 | ||
7179 | if (pi->min_vddc_in_table > pl->vddc) | |
7180 | pi->min_vddc_in_table = pl->vddc; | |
7181 | ||
7182 | if (pi->max_vddc_in_table < pl->vddc) | |
7183 | pi->max_vddc_in_table = pl->vddc; | |
7184 | ||
7185 | /* patch up boot state */ | |
7186 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { | |
7187 | u16 vddc, vddci, mvdd; | |
7188 | amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); | |
7189 | pl->mclk = adev->clock.default_mclk; | |
7190 | pl->sclk = adev->clock.default_sclk; | |
7191 | pl->vddc = vddc; | |
7192 | pl->vddci = vddci; | |
7193 | si_pi->mvdd_bootup_value = mvdd; | |
7194 | } | |
7195 | ||
7196 | if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == | |
7197 | ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { | |
7198 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; | |
7199 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; | |
7200 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; | |
7201 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; | |
7202 | } | |
7203 | } | |
7204 | ||
7205 | union pplib_power_state { | |
77d318a6 TSD |
7206 | struct _ATOM_PPLIB_STATE v1; |
7207 | struct _ATOM_PPLIB_STATE_V2 v2; | |
841686df MB |
7208 | }; |
7209 | ||
7210 | static int si_parse_power_table(struct amdgpu_device *adev) | |
7211 | { | |
7212 | struct amdgpu_mode_info *mode_info = &adev->mode_info; | |
7213 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
7214 | union pplib_power_state *power_state; | |
7215 | int i, j, k, non_clock_array_index, clock_array_index; | |
7216 | union pplib_clock_info *clock_info; | |
7217 | struct _StateArray *state_array; | |
7218 | struct _ClockInfoArray *clock_info_array; | |
7219 | struct _NonClockInfoArray *non_clock_info_array; | |
7220 | union power_info *power_info; | |
7221 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
77d318a6 | 7222 | u16 data_offset; |
841686df MB |
7223 | u8 frev, crev; |
7224 | u8 *power_state_offset; | |
7225 | struct si_ps *ps; | |
7226 | ||
7227 | if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, | |
7228 | &frev, &crev, &data_offset)) | |
7229 | return -EINVAL; | |
7230 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
7231 | ||
7232 | amdgpu_add_thermal_controller(adev); | |
7233 | ||
7234 | state_array = (struct _StateArray *) | |
7235 | (mode_info->atom_context->bios + data_offset + | |
7236 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); | |
7237 | clock_info_array = (struct _ClockInfoArray *) | |
7238 | (mode_info->atom_context->bios + data_offset + | |
7239 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); | |
7240 | non_clock_info_array = (struct _NonClockInfoArray *) | |
7241 | (mode_info->atom_context->bios + data_offset + | |
7242 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); | |
7243 | ||
6396bb22 KC |
7244 | adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, |
7245 | sizeof(struct amdgpu_ps), | |
7246 | GFP_KERNEL); | |
841686df MB |
7247 | if (!adev->pm.dpm.ps) |
7248 | return -ENOMEM; | |
7249 | power_state_offset = (u8 *)state_array->states; | |
7250 | for (i = 0; i < state_array->ucNumEntries; i++) { | |
7251 | u8 *idx; | |
7252 | power_state = (union pplib_power_state *)power_state_offset; | |
7253 | non_clock_array_index = power_state->v2.nonClockInfoIndex; | |
7254 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
7255 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; | |
7256 | ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL); | |
7257 | if (ps == NULL) { | |
7258 | kfree(adev->pm.dpm.ps); | |
7259 | return -ENOMEM; | |
7260 | } | |
7261 | adev->pm.dpm.ps[i].ps_priv = ps; | |
7262 | si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], | |
7263 | non_clock_info, | |
7264 | non_clock_info_array->ucEntrySize); | |
7265 | k = 0; | |
7266 | idx = (u8 *)&power_state->v2.clockInfoIndex[0]; | |
7267 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { | |
7268 | clock_array_index = idx[j]; | |
7269 | if (clock_array_index >= clock_info_array->ucNumEntries) | |
7270 | continue; | |
7271 | if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) | |
7272 | break; | |
7273 | clock_info = (union pplib_clock_info *) | |
7274 | ((u8 *)&clock_info_array->clockInfo[0] + | |
7275 | (clock_array_index * clock_info_array->ucEntrySize)); | |
7276 | si_parse_pplib_clock_info(adev, | |
7277 | &adev->pm.dpm.ps[i], k, | |
7278 | clock_info); | |
7279 | k++; | |
7280 | } | |
7281 | power_state_offset += 2 + power_state->v2.ucNumDPMLevels; | |
7282 | } | |
7283 | adev->pm.dpm.num_ps = state_array->ucNumEntries; | |
7284 | ||
7285 | /* fill in the vce power states */ | |
66ba1afd | 7286 | for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { |
841686df MB |
7287 | u32 sclk, mclk; |
7288 | clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; | |
7289 | clock_info = (union pplib_clock_info *) | |
7290 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; | |
7291 | sclk = le16_to_cpu(clock_info->si.usEngineClockLow); | |
7292 | sclk |= clock_info->si.ucEngineClockHigh << 16; | |
7293 | mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); | |
7294 | mclk |= clock_info->si.ucMemoryClockHigh << 16; | |
7295 | adev->pm.dpm.vce_states[i].sclk = sclk; | |
7296 | adev->pm.dpm.vce_states[i].mclk = mclk; | |
7297 | } | |
7298 | ||
7299 | return 0; | |
7300 | } | |
7301 | ||
7302 | static int si_dpm_init(struct amdgpu_device *adev) | |
7303 | { | |
7304 | struct rv7xx_power_info *pi; | |
7305 | struct evergreen_power_info *eg_pi; | |
7306 | struct ni_power_info *ni_pi; | |
7307 | struct si_power_info *si_pi; | |
7308 | struct atom_clock_dividers dividers; | |
7309 | int ret; | |
841686df MB |
7310 | |
7311 | si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); | |
7312 | if (si_pi == NULL) | |
7313 | return -ENOMEM; | |
7314 | adev->pm.dpm.priv = si_pi; | |
7315 | ni_pi = &si_pi->ni; | |
7316 | eg_pi = &ni_pi->eg; | |
7317 | pi = &eg_pi->rv7xx; | |
7318 | ||
0bf67185 | 7319 | si_pi->sys_pcie_mask = |
5d9a6330 | 7320 | adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; |
841686df MB |
7321 | si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; |
7322 | si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); | |
7323 | ||
7324 | si_set_max_cu_value(adev); | |
7325 | ||
7326 | rv770_get_max_vddc(adev); | |
7327 | si_get_leakage_vddc(adev); | |
7328 | si_patch_dependency_tables_based_on_leakage(adev); | |
7329 | ||
7330 | pi->acpi_vddc = 0; | |
7331 | eg_pi->acpi_vddci = 0; | |
7332 | pi->min_vddc_in_table = 0; | |
7333 | pi->max_vddc_in_table = 0; | |
7334 | ||
7335 | ret = amdgpu_get_platform_caps(adev); | |
7336 | if (ret) | |
7337 | return ret; | |
7338 | ||
7339 | ret = amdgpu_parse_extended_power_table(adev); | |
7340 | if (ret) | |
7341 | return ret; | |
7342 | ||
7343 | ret = si_parse_power_table(adev); | |
7344 | if (ret) | |
7345 | return ret; | |
7346 | ||
7347 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = | |
6396bb22 KC |
7348 | kcalloc(4, |
7349 | sizeof(struct amdgpu_clock_voltage_dependency_entry), | |
7350 | GFP_KERNEL); | |
841686df MB |
7351 | if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { |
7352 | amdgpu_free_extended_power_table(adev); | |
7353 | return -ENOMEM; | |
7354 | } | |
7355 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; | |
7356 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; | |
7357 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; | |
7358 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; | |
7359 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; | |
7360 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; | |
7361 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; | |
7362 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; | |
7363 | adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; | |
7364 | ||
7365 | if (adev->pm.dpm.voltage_response_time == 0) | |
7366 | adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; | |
7367 | if (adev->pm.dpm.backbias_response_time == 0) | |
7368 | adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; | |
7369 | ||
7370 | ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, | |
7371 | 0, false, ÷rs); | |
7372 | if (ret) | |
7373 | pi->ref_div = dividers.ref_div + 1; | |
7374 | else | |
7375 | pi->ref_div = R600_REFERENCEDIVIDER_DFLT; | |
7376 | ||
7377 | eg_pi->smu_uvd_hs = false; | |
7378 | ||
7379 | pi->mclk_strobe_mode_threshold = 40000; | |
7380 | if (si_is_special_1gb_platform(adev)) | |
7381 | pi->mclk_stutter_mode_threshold = 0; | |
7382 | else | |
7383 | pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; | |
7384 | pi->mclk_edc_enable_threshold = 40000; | |
7385 | eg_pi->mclk_edc_wr_enable_threshold = 40000; | |
7386 | ||
7387 | ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; | |
7388 | ||
7389 | pi->voltage_control = | |
7390 | amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
7391 | VOLTAGE_OBJ_GPIO_LUT); | |
7392 | if (!pi->voltage_control) { | |
7393 | si_pi->voltage_control_svi2 = | |
7394 | amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
7395 | VOLTAGE_OBJ_SVID2); | |
7396 | if (si_pi->voltage_control_svi2) | |
7397 | amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
7398 | &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); | |
7399 | } | |
7400 | ||
7401 | pi->mvdd_control = | |
7402 | amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC, | |
7403 | VOLTAGE_OBJ_GPIO_LUT); | |
7404 | ||
7405 | eg_pi->vddci_control = | |
7406 | amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, | |
7407 | VOLTAGE_OBJ_GPIO_LUT); | |
7408 | if (!eg_pi->vddci_control) | |
7409 | si_pi->vddci_control_svi2 = | |
7410 | amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, | |
7411 | VOLTAGE_OBJ_SVID2); | |
7412 | ||
7413 | si_pi->vddc_phase_shed_control = | |
7414 | amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, | |
7415 | VOLTAGE_OBJ_PHASE_LUT); | |
7416 | ||
7417 | rv770_get_engine_memory_ss(adev); | |
7418 | ||
7419 | pi->asi = RV770_ASI_DFLT; | |
7420 | pi->pasi = CYPRESS_HASI_DFLT; | |
7421 | pi->vrc = SISLANDS_VRC_DFLT; | |
7422 | ||
7423 | pi->gfx_clock_gating = true; | |
7424 | ||
7425 | eg_pi->sclk_deep_sleep = true; | |
7426 | si_pi->sclk_deep_sleep_above_low = false; | |
7427 | ||
7428 | if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) | |
7429 | pi->thermal_protection = true; | |
7430 | else | |
7431 | pi->thermal_protection = false; | |
7432 | ||
7433 | eg_pi->dynamic_ac_timing = true; | |
7434 | ||
7435 | eg_pi->light_sleep = true; | |
7436 | #if defined(CONFIG_ACPI) | |
7437 | eg_pi->pcie_performance_request = | |
7438 | amdgpu_acpi_is_pcie_performance_request_supported(adev); | |
7439 | #else | |
7440 | eg_pi->pcie_performance_request = false; | |
7441 | #endif | |
7442 | ||
7443 | si_pi->sram_end = SMC_RAM_END; | |
7444 | ||
7445 | adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; | |
7446 | adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; | |
7447 | adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; | |
7448 | adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; | |
7449 | adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; | |
7450 | adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; | |
7451 | adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; | |
7452 | ||
7453 | si_initialize_powertune_defaults(adev); | |
7454 | ||
7455 | /* make sure dc limits are valid */ | |
7456 | if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || | |
7457 | (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) | |
7458 | adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = | |
7459 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; | |
7460 | ||
7461 | si_pi->fan_ctrl_is_in_default_mode = true; | |
7462 | ||
7463 | return 0; | |
7464 | } | |
7465 | ||
7466 | static void si_dpm_fini(struct amdgpu_device *adev) | |
7467 | { | |
7468 | int i; | |
7469 | ||
9623e4bf TSD |
7470 | if (adev->pm.dpm.ps) |
7471 | for (i = 0; i < adev->pm.dpm.num_ps; i++) | |
7472 | kfree(adev->pm.dpm.ps[i].ps_priv); | |
841686df MB |
7473 | kfree(adev->pm.dpm.ps); |
7474 | kfree(adev->pm.dpm.priv); | |
7475 | kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); | |
7476 | amdgpu_free_extended_power_table(adev); | |
7477 | } | |
7478 | ||
cfa289fd | 7479 | static void si_dpm_debugfs_print_current_performance_level(void *handle, |
841686df MB |
7480 | struct seq_file *m) |
7481 | { | |
cfa289fd | 7482 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
7483 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
7484 | struct amdgpu_ps *rps = &eg_pi->current_rps; | |
7485 | struct si_ps *ps = si_get_ps(rps); | |
7486 | struct rv7xx_pl *pl; | |
7487 | u32 current_index = | |
7488 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> | |
7489 | CURRENT_STATE_INDEX_SHIFT; | |
7490 | ||
7491 | if (current_index >= ps->performance_level_count) { | |
7492 | seq_printf(m, "invalid dpm profile %d\n", current_index); | |
7493 | } else { | |
7494 | pl = &ps->performance_levels[current_index]; | |
7495 | seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); | |
7496 | seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", | |
7497 | current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); | |
7498 | } | |
7499 | } | |
7500 | ||
7501 | static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, | |
7502 | struct amdgpu_irq_src *source, | |
7503 | unsigned type, | |
7504 | enum amdgpu_interrupt_state state) | |
7505 | { | |
7506 | u32 cg_thermal_int; | |
7507 | ||
7508 | switch (type) { | |
7509 | case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: | |
7510 | switch (state) { | |
7511 | case AMDGPU_IRQ_STATE_DISABLE: | |
7512 | cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); | |
7513 | cg_thermal_int |= THERM_INT_MASK_HIGH; | |
7514 | WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); | |
7515 | break; | |
7516 | case AMDGPU_IRQ_STATE_ENABLE: | |
7517 | cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); | |
7518 | cg_thermal_int &= ~THERM_INT_MASK_HIGH; | |
7519 | WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); | |
7520 | break; | |
7521 | default: | |
7522 | break; | |
7523 | } | |
7524 | break; | |
7525 | ||
7526 | case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: | |
7527 | switch (state) { | |
7528 | case AMDGPU_IRQ_STATE_DISABLE: | |
7529 | cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); | |
7530 | cg_thermal_int |= THERM_INT_MASK_LOW; | |
7531 | WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); | |
7532 | break; | |
7533 | case AMDGPU_IRQ_STATE_ENABLE: | |
7534 | cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); | |
7535 | cg_thermal_int &= ~THERM_INT_MASK_LOW; | |
7536 | WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); | |
7537 | break; | |
7538 | default: | |
7539 | break; | |
7540 | } | |
7541 | break; | |
7542 | ||
7543 | default: | |
7544 | break; | |
7545 | } | |
7546 | return 0; | |
7547 | } | |
7548 | ||
7549 | static int si_dpm_process_interrupt(struct amdgpu_device *adev, | |
a1047777 | 7550 | struct amdgpu_irq_src *source, |
841686df MB |
7551 | struct amdgpu_iv_entry *entry) |
7552 | { | |
7553 | bool queue_thermal = false; | |
7554 | ||
7555 | if (entry == NULL) | |
7556 | return -EINVAL; | |
7557 | ||
7558 | switch (entry->src_id) { | |
7559 | case 230: /* thermal low to high */ | |
7560 | DRM_DEBUG("IH: thermal low to high\n"); | |
7561 | adev->pm.dpm.thermal.high_to_low = false; | |
7562 | queue_thermal = true; | |
7563 | break; | |
7564 | case 231: /* thermal high to low */ | |
7565 | DRM_DEBUG("IH: thermal high to low\n"); | |
7566 | adev->pm.dpm.thermal.high_to_low = true; | |
7567 | queue_thermal = true; | |
7568 | break; | |
7569 | default: | |
7570 | break; | |
7571 | } | |
7572 | ||
7573 | if (queue_thermal) | |
7574 | schedule_work(&adev->pm.dpm.thermal.work); | |
7575 | ||
7576 | return 0; | |
7577 | } | |
7578 | ||
7579 | static int si_dpm_late_init(void *handle) | |
7580 | { | |
7581 | int ret; | |
7582 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7583 | ||
b13aa109 | 7584 | if (!adev->pm.dpm_enabled) |
841686df MB |
7585 | return 0; |
7586 | ||
841686df MB |
7587 | ret = si_set_temperature_range(adev); |
7588 | if (ret) | |
7589 | return ret; | |
7590 | #if 0 //TODO ? | |
7591 | si_dpm_powergate_uvd(adev, true); | |
7592 | #endif | |
7593 | return 0; | |
7594 | } | |
7595 | ||
7596 | /** | |
7597 | * si_dpm_init_microcode - load ucode images from disk | |
7598 | * | |
7599 | * @adev: amdgpu_device pointer | |
7600 | * | |
7601 | * Use the firmware interface to load the ucode images into | |
7602 | * the driver (not loaded into hw). | |
7603 | * Returns 0 on success, error on failure. | |
7604 | */ | |
7605 | static int si_dpm_init_microcode(struct amdgpu_device *adev) | |
7606 | { | |
7607 | const char *chip_name; | |
7608 | char fw_name[30]; | |
7609 | int err; | |
7610 | ||
7611 | DRM_DEBUG("\n"); | |
7612 | switch (adev->asic_type) { | |
7613 | case CHIP_TAHITI: | |
7614 | chip_name = "tahiti"; | |
7615 | break; | |
7616 | case CHIP_PITCAIRN: | |
5165484b FC |
7617 | if ((adev->pdev->revision == 0x81) && |
7618 | ((adev->pdev->device == 0x6810) || | |
7619 | (adev->pdev->device == 0x6811))) | |
a8c65c13 AD |
7620 | chip_name = "pitcairn_k"; |
7621 | else | |
7622 | chip_name = "pitcairn"; | |
841686df MB |
7623 | break; |
7624 | case CHIP_VERDE: | |
5165484b FC |
7625 | if (((adev->pdev->device == 0x6820) && |
7626 | ((adev->pdev->revision == 0x81) || | |
7627 | (adev->pdev->revision == 0x83))) || | |
7628 | ((adev->pdev->device == 0x6821) && | |
7629 | ((adev->pdev->revision == 0x83) || | |
7630 | (adev->pdev->revision == 0x87))) || | |
7631 | ((adev->pdev->revision == 0x87) && | |
7632 | ((adev->pdev->device == 0x6823) || | |
7633 | (adev->pdev->device == 0x682b)))) | |
a8c65c13 AD |
7634 | chip_name = "verde_k"; |
7635 | else | |
7636 | chip_name = "verde"; | |
841686df MB |
7637 | break; |
7638 | case CHIP_OLAND: | |
5165484b FC |
7639 | if (((adev->pdev->revision == 0x81) && |
7640 | ((adev->pdev->device == 0x6600) || | |
7641 | (adev->pdev->device == 0x6604) || | |
7642 | (adev->pdev->device == 0x6605) || | |
7643 | (adev->pdev->device == 0x6610))) || | |
7644 | ((adev->pdev->revision == 0x83) && | |
7645 | (adev->pdev->device == 0x6610))) | |
a8c65c13 AD |
7646 | chip_name = "oland_k"; |
7647 | else | |
7648 | chip_name = "oland"; | |
841686df MB |
7649 | break; |
7650 | case CHIP_HAINAN: | |
5165484b FC |
7651 | if (((adev->pdev->revision == 0x81) && |
7652 | (adev->pdev->device == 0x6660)) || | |
7653 | ((adev->pdev->revision == 0x83) && | |
7654 | ((adev->pdev->device == 0x6660) || | |
7655 | (adev->pdev->device == 0x6663) || | |
7656 | (adev->pdev->device == 0x6665) || | |
17324b6a | 7657 | (adev->pdev->device == 0x6667)))) |
a8c65c13 | 7658 | chip_name = "hainan_k"; |
17324b6a AD |
7659 | else if ((adev->pdev->revision == 0xc3) && |
7660 | (adev->pdev->device == 0x6665)) | |
7661 | chip_name = "banks_k_2"; | |
a8c65c13 AD |
7662 | else |
7663 | chip_name = "hainan"; | |
841686df MB |
7664 | break; |
7665 | default: BUG(); | |
7666 | } | |
7667 | ||
8eaf2b1f | 7668 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); |
841686df MB |
7669 | err = request_firmware(&adev->pm.fw, fw_name, adev->dev); |
7670 | if (err) | |
7671 | goto out; | |
7672 | err = amdgpu_ucode_validate(adev->pm.fw); | |
7673 | ||
7674 | out: | |
7675 | if (err) { | |
84b77336 HR |
7676 | DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n", |
7677 | err, fw_name); | |
841686df MB |
7678 | release_firmware(adev->pm.fw); |
7679 | adev->pm.fw = NULL; | |
7680 | } | |
7681 | return err; | |
7682 | ||
7683 | } | |
7684 | ||
7685 | static int si_dpm_sw_init(void *handle) | |
7686 | { | |
7687 | int ret; | |
7688 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7689 | ||
d766e6a3 | 7690 | ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); |
841686df MB |
7691 | if (ret) |
7692 | return ret; | |
7693 | ||
d766e6a3 | 7694 | ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); |
841686df MB |
7695 | if (ret) |
7696 | return ret; | |
7697 | ||
7698 | /* default to balanced state */ | |
7699 | adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; | |
7700 | adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; | |
e5d03ac2 | 7701 | adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; |
841686df MB |
7702 | adev->pm.default_sclk = adev->clock.default_sclk; |
7703 | adev->pm.default_mclk = adev->clock.default_mclk; | |
7704 | adev->pm.current_sclk = adev->clock.default_sclk; | |
7705 | adev->pm.current_mclk = adev->clock.default_mclk; | |
7706 | adev->pm.int_thermal_type = THERMAL_TYPE_NONE; | |
7707 | ||
7708 | if (amdgpu_dpm == 0) | |
7709 | return 0; | |
7710 | ||
7711 | ret = si_dpm_init_microcode(adev); | |
7712 | if (ret) | |
7713 | return ret; | |
7714 | ||
7715 | INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); | |
7716 | mutex_lock(&adev->pm.mutex); | |
7717 | ret = si_dpm_init(adev); | |
7718 | if (ret) | |
7719 | goto dpm_failed; | |
7720 | adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; | |
7721 | if (amdgpu_dpm == 1) | |
7722 | amdgpu_pm_print_power_states(adev); | |
7723 | mutex_unlock(&adev->pm.mutex); | |
7724 | DRM_INFO("amdgpu: dpm initialized\n"); | |
7725 | ||
7726 | return 0; | |
7727 | ||
7728 | dpm_failed: | |
7729 | si_dpm_fini(adev); | |
7730 | mutex_unlock(&adev->pm.mutex); | |
7731 | DRM_ERROR("amdgpu: dpm initialization failed\n"); | |
7732 | return ret; | |
7733 | } | |
7734 | ||
7735 | static int si_dpm_sw_fini(void *handle) | |
7736 | { | |
7737 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7738 | ||
4560738a AD |
7739 | flush_work(&adev->pm.dpm.thermal.work); |
7740 | ||
841686df | 7741 | mutex_lock(&adev->pm.mutex); |
841686df MB |
7742 | si_dpm_fini(adev); |
7743 | mutex_unlock(&adev->pm.mutex); | |
7744 | ||
7745 | return 0; | |
7746 | } | |
7747 | ||
7748 | static int si_dpm_hw_init(void *handle) | |
7749 | { | |
7750 | int ret; | |
7751 | ||
7752 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7753 | ||
7754 | if (!amdgpu_dpm) | |
7755 | return 0; | |
7756 | ||
7757 | mutex_lock(&adev->pm.mutex); | |
7758 | si_dpm_setup_asic(adev); | |
7759 | ret = si_dpm_enable(adev); | |
7760 | if (ret) | |
7761 | adev->pm.dpm_enabled = false; | |
7762 | else | |
7763 | adev->pm.dpm_enabled = true; | |
7764 | mutex_unlock(&adev->pm.mutex); | |
2ab4d0e7 | 7765 | amdgpu_pm_compute_clocks(adev); |
841686df MB |
7766 | return ret; |
7767 | } | |
7768 | ||
7769 | static int si_dpm_hw_fini(void *handle) | |
7770 | { | |
7771 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7772 | ||
7773 | if (adev->pm.dpm_enabled) { | |
7774 | mutex_lock(&adev->pm.mutex); | |
7775 | si_dpm_disable(adev); | |
7776 | mutex_unlock(&adev->pm.mutex); | |
7777 | } | |
7778 | ||
7779 | return 0; | |
7780 | } | |
7781 | ||
7782 | static int si_dpm_suspend(void *handle) | |
7783 | { | |
7784 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7785 | ||
7786 | if (adev->pm.dpm_enabled) { | |
7787 | mutex_lock(&adev->pm.mutex); | |
7788 | /* disable dpm */ | |
7789 | si_dpm_disable(adev); | |
7790 | /* reset the power state */ | |
7791 | adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; | |
7792 | mutex_unlock(&adev->pm.mutex); | |
7793 | } | |
7794 | return 0; | |
7795 | } | |
7796 | ||
7797 | static int si_dpm_resume(void *handle) | |
7798 | { | |
7799 | int ret; | |
7800 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7801 | ||
7802 | if (adev->pm.dpm_enabled) { | |
7803 | /* asic init will reset to the boot state */ | |
7804 | mutex_lock(&adev->pm.mutex); | |
7805 | si_dpm_setup_asic(adev); | |
7806 | ret = si_dpm_enable(adev); | |
7807 | if (ret) | |
7808 | adev->pm.dpm_enabled = false; | |
7809 | else | |
7810 | adev->pm.dpm_enabled = true; | |
7811 | mutex_unlock(&adev->pm.mutex); | |
7812 | if (adev->pm.dpm_enabled) | |
7813 | amdgpu_pm_compute_clocks(adev); | |
7814 | } | |
7815 | return 0; | |
7816 | } | |
7817 | ||
7818 | static bool si_dpm_is_idle(void *handle) | |
7819 | { | |
7820 | /* XXX */ | |
7821 | return true; | |
7822 | } | |
7823 | ||
7824 | static int si_dpm_wait_for_idle(void *handle) | |
7825 | { | |
7826 | /* XXX */ | |
7827 | return 0; | |
7828 | } | |
7829 | ||
7830 | static int si_dpm_soft_reset(void *handle) | |
7831 | { | |
7832 | return 0; | |
7833 | } | |
7834 | ||
7835 | static int si_dpm_set_clockgating_state(void *handle, | |
7836 | enum amd_clockgating_state state) | |
7837 | { | |
7838 | return 0; | |
7839 | } | |
7840 | ||
7841 | static int si_dpm_set_powergating_state(void *handle, | |
7842 | enum amd_powergating_state state) | |
7843 | { | |
7844 | return 0; | |
7845 | } | |
7846 | ||
7847 | /* get temperature in millidegrees */ | |
cfa289fd | 7848 | static int si_dpm_get_temp(void *handle) |
841686df MB |
7849 | { |
7850 | u32 temp; | |
7851 | int actual_temp = 0; | |
cfa289fd | 7852 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
841686df MB |
7853 | |
7854 | temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> | |
7855 | CTF_TEMP_SHIFT; | |
7856 | ||
7857 | if (temp & 0x200) | |
7858 | actual_temp = 255; | |
7859 | else | |
7860 | actual_temp = temp & 0x1ff; | |
7861 | ||
7862 | actual_temp = (actual_temp * 1000); | |
7863 | ||
7864 | return actual_temp; | |
7865 | } | |
7866 | ||
cfa289fd | 7867 | static u32 si_dpm_get_sclk(void *handle, bool low) |
841686df | 7868 | { |
cfa289fd | 7869 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
77d318a6 TSD |
7870 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
7871 | struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); | |
841686df | 7872 | |
77d318a6 TSD |
7873 | if (low) |
7874 | return requested_state->performance_levels[0].sclk; | |
7875 | else | |
7876 | return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; | |
841686df MB |
7877 | } |
7878 | ||
cfa289fd | 7879 | static u32 si_dpm_get_mclk(void *handle, bool low) |
841686df | 7880 | { |
cfa289fd | 7881 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
77d318a6 TSD |
7882 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
7883 | struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); | |
841686df | 7884 | |
77d318a6 TSD |
7885 | if (low) |
7886 | return requested_state->performance_levels[0].mclk; | |
7887 | else | |
7888 | return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; | |
841686df MB |
7889 | } |
7890 | ||
cfa289fd RZ |
7891 | static void si_dpm_print_power_state(void *handle, |
7892 | void *current_ps) | |
77d318a6 | 7893 | { |
cfa289fd RZ |
7894 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
7895 | struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; | |
77d318a6 TSD |
7896 | struct si_ps *ps = si_get_ps(rps); |
7897 | struct rv7xx_pl *pl; | |
7898 | int i; | |
7899 | ||
7900 | amdgpu_dpm_print_class_info(rps->class, rps->class2); | |
7901 | amdgpu_dpm_print_cap_info(rps->caps); | |
7902 | DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); | |
7903 | for (i = 0; i < ps->performance_level_count; i++) { | |
7904 | pl = &ps->performance_levels[i]; | |
7905 | if (adev->asic_type >= CHIP_TAHITI) | |
7906 | DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", | |
84b77336 | 7907 | i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); |
77d318a6 TSD |
7908 | else |
7909 | DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", | |
84b77336 | 7910 | i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); |
77d318a6 TSD |
7911 | } |
7912 | amdgpu_dpm_print_ps_status(adev, rps); | |
841686df MB |
7913 | } |
7914 | ||
7915 | static int si_dpm_early_init(void *handle) | |
7916 | { | |
7917 | ||
7918 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
7919 | ||
b905090d | 7920 | adev->powerplay.pp_funcs = &si_dpm_funcs; |
eb4900aa | 7921 | adev->powerplay.pp_handle = adev; |
841686df MB |
7922 | si_dpm_set_irq_funcs(adev); |
7923 | return 0; | |
7924 | } | |
7925 | ||
34117175 RZ |
7926 | static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, |
7927 | const struct rv7xx_pl *si_cpl2) | |
7928 | { | |
7929 | return ((si_cpl1->mclk == si_cpl2->mclk) && | |
7930 | (si_cpl1->sclk == si_cpl2->sclk) && | |
7931 | (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && | |
7932 | (si_cpl1->vddc == si_cpl2->vddc) && | |
7933 | (si_cpl1->vddci == si_cpl2->vddci)); | |
7934 | } | |
7935 | ||
cfa289fd RZ |
7936 | static int si_check_state_equal(void *handle, |
7937 | void *current_ps, | |
7938 | void *request_ps, | |
34117175 RZ |
7939 | bool *equal) |
7940 | { | |
7941 | struct si_ps *si_cps; | |
7942 | struct si_ps *si_rps; | |
7943 | int i; | |
cfa289fd RZ |
7944 | struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; |
7945 | struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; | |
7946 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
34117175 RZ |
7947 | |
7948 | if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) | |
7949 | return -EINVAL; | |
7950 | ||
cfa289fd RZ |
7951 | si_cps = si_get_ps((struct amdgpu_ps *)cps); |
7952 | si_rps = si_get_ps((struct amdgpu_ps *)rps); | |
34117175 RZ |
7953 | |
7954 | if (si_cps == NULL) { | |
7955 | printk("si_cps is NULL\n"); | |
7956 | *equal = false; | |
7957 | return 0; | |
7958 | } | |
7959 | ||
7960 | if (si_cps->performance_level_count != si_rps->performance_level_count) { | |
7961 | *equal = false; | |
7962 | return 0; | |
7963 | } | |
7964 | ||
7965 | for (i = 0; i < si_cps->performance_level_count; i++) { | |
7966 | if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), | |
7967 | &(si_rps->performance_levels[i]))) { | |
7968 | *equal = false; | |
7969 | return 0; | |
7970 | } | |
7971 | } | |
7972 | ||
7973 | /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ | |
7974 | *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); | |
7975 | *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); | |
7976 | ||
7977 | return 0; | |
7978 | } | |
7979 | ||
cfa289fd | 7980 | static int si_dpm_read_sensor(void *handle, int idx, |
d6c29695 SP |
7981 | void *value, int *size) |
7982 | { | |
cfa289fd | 7983 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
d6c29695 SP |
7984 | struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); |
7985 | struct amdgpu_ps *rps = &eg_pi->current_rps; | |
7986 | struct si_ps *ps = si_get_ps(rps); | |
7987 | uint32_t sclk, mclk; | |
7988 | u32 pl_index = | |
7989 | (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> | |
7990 | CURRENT_STATE_INDEX_SHIFT; | |
7991 | ||
7992 | /* size must be at least 4 bytes for all sensors */ | |
7993 | if (*size < 4) | |
7994 | return -EINVAL; | |
7995 | ||
7996 | switch (idx) { | |
7997 | case AMDGPU_PP_SENSOR_GFX_SCLK: | |
7998 | if (pl_index < ps->performance_level_count) { | |
7999 | sclk = ps->performance_levels[pl_index].sclk; | |
8000 | *((uint32_t *)value) = sclk; | |
8001 | *size = 4; | |
8002 | return 0; | |
8003 | } | |
8004 | return -EINVAL; | |
8005 | case AMDGPU_PP_SENSOR_GFX_MCLK: | |
8006 | if (pl_index < ps->performance_level_count) { | |
8007 | mclk = ps->performance_levels[pl_index].mclk; | |
8008 | *((uint32_t *)value) = mclk; | |
8009 | *size = 4; | |
8010 | return 0; | |
8011 | } | |
8012 | return -EINVAL; | |
8013 | case AMDGPU_PP_SENSOR_GPU_TEMP: | |
8014 | *((uint32_t *)value) = si_dpm_get_temp(adev); | |
8015 | *size = 4; | |
8016 | return 0; | |
8017 | default: | |
8018 | return -EINVAL; | |
8019 | } | |
8020 | } | |
841686df | 8021 | |
b905090d | 8022 | static const struct amd_ip_funcs si_dpm_ip_funcs = { |
841686df MB |
8023 | .name = "si_dpm", |
8024 | .early_init = si_dpm_early_init, | |
8025 | .late_init = si_dpm_late_init, | |
8026 | .sw_init = si_dpm_sw_init, | |
8027 | .sw_fini = si_dpm_sw_fini, | |
8028 | .hw_init = si_dpm_hw_init, | |
8029 | .hw_fini = si_dpm_hw_fini, | |
8030 | .suspend = si_dpm_suspend, | |
8031 | .resume = si_dpm_resume, | |
8032 | .is_idle = si_dpm_is_idle, | |
8033 | .wait_for_idle = si_dpm_wait_for_idle, | |
8034 | .soft_reset = si_dpm_soft_reset, | |
8035 | .set_clockgating_state = si_dpm_set_clockgating_state, | |
8036 | .set_powergating_state = si_dpm_set_powergating_state, | |
8037 | }; | |
8038 | ||
b905090d RZ |
8039 | const struct amdgpu_ip_block_version si_smu_ip_block = |
8040 | { | |
8041 | .type = AMD_IP_BLOCK_TYPE_SMC, | |
8042 | .major = 6, | |
8043 | .minor = 0, | |
8044 | .rev = 0, | |
8045 | .funcs = &si_dpm_ip_funcs, | |
8046 | }; | |
8047 | ||
8048 | static const struct amd_pm_funcs si_dpm_funcs = { | |
841686df MB |
8049 | .pre_set_power_state = &si_dpm_pre_set_power_state, |
8050 | .set_power_state = &si_dpm_set_power_state, | |
8051 | .post_set_power_state = &si_dpm_post_set_power_state, | |
8052 | .display_configuration_changed = &si_dpm_display_configuration_changed, | |
8053 | .get_sclk = &si_dpm_get_sclk, | |
8054 | .get_mclk = &si_dpm_get_mclk, | |
8055 | .print_power_state = &si_dpm_print_power_state, | |
8056 | .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, | |
8057 | .force_performance_level = &si_dpm_force_performance_level, | |
8058 | .vblank_too_short = &si_dpm_vblank_too_short, | |
8059 | .set_fan_control_mode = &si_dpm_set_fan_control_mode, | |
8060 | .get_fan_control_mode = &si_dpm_get_fan_control_mode, | |
8061 | .set_fan_speed_percent = &si_dpm_set_fan_speed_percent, | |
8062 | .get_fan_speed_percent = &si_dpm_get_fan_speed_percent, | |
34117175 | 8063 | .check_state_equal = &si_check_state_equal, |
825cc997 | 8064 | .get_vce_clock_state = amdgpu_get_vce_clock_state, |
d6c29695 | 8065 | .read_sensor = &si_dpm_read_sensor, |
841686df MB |
8066 | }; |
8067 | ||
841686df MB |
8068 | static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { |
8069 | .set = si_dpm_set_interrupt_state, | |
8070 | .process = si_dpm_process_interrupt, | |
8071 | }; | |
8072 | ||
8073 | static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) | |
8074 | { | |
8075 | adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; | |
8076 | adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; | |
8077 | } | |
8078 |