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drm/amdgpu: add insert_nop ring func and default implementation
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "vi.h"
30#include "vid.h"
31
32#include "oss/oss_3_0_d.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "gca/gfx_8_0_d.h"
74a5d165 39#include "gca/gfx_8_0_enum.h"
aaa36a97
AD		 40#include "gca/gfx_8_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "tonga_sdma_pkt_open.h"
46
47static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
c65444fe
JZ		 52MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
1a5bbb66
DZ		 56MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
aaa36a97
AD		 58
59static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
60{
61 SDMA0_REGISTER_OFFSET,
62 SDMA1_REGISTER_OFFSET
63};
64
65static const u32 golden_settings_tonga_a11[] =
66{
67 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
68 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
69 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
70 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
71 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
72 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
73 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
74 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
75 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
76 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
77};
78
79static const u32 tonga_mgcg_cgcg_init[] =
80{
81 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
82 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
83};
84
1a5bbb66
DZ		 85static const u32 golden_settings_fiji_a10[] =
86{
87 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
88 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
89 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
90 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
91 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
92 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
93 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
94 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
95};
96
97static const u32 fiji_mgcg_cgcg_init[] =
98{
99 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
100 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
101};
102
aaa36a97
AD		 103static const u32 cz_golden_settings_a11[] =
104{
105 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
106 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
107 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
108 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
109 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
110 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
111 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
112 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
113 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
114 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
115 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
116 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
117};
118
119static const u32 cz_mgcg_cgcg_init[] =
120{
121 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
122 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
123};
124
125/*
126 * sDMA - System DMA
127 * Starting with CIK, the GPU has new asynchronous
128 * DMA engines. These engines are used for compute
129 * and gfx. There are two DMA engines (SDMA0, SDMA1)
130 * and each one supports 1 ring buffer used for gfx
131 * and 2 queues used for compute.
132 *
133 * The programming model is very similar to the CP
134 * (ring buffer, IBs, etc.), but sDMA has it's own
135 * packet format that is different from the PM4 format
136 * used by the CP. sDMA supports copying data, writing
137 * embedded data, solid fills, and a number of other
138 * things. It also has support for tiling/detiling of
139 * buffers.
140 */
141
142static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
143{
144 switch (adev->asic_type) {
1a5bbb66
DZ		 145 case CHIP_FIJI:
146 amdgpu_program_register_sequence(adev,
147 fiji_mgcg_cgcg_init,
148 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
149 amdgpu_program_register_sequence(adev,
150 golden_settings_fiji_a10,
151 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
152 break;
aaa36a97
AD		 153 case CHIP_TONGA:
154 amdgpu_program_register_sequence(adev,
155 tonga_mgcg_cgcg_init,
156 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
157 amdgpu_program_register_sequence(adev,
158 golden_settings_tonga_a11,
159 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
160 break;
161 case CHIP_CARRIZO:
162 amdgpu_program_register_sequence(adev,
163 cz_mgcg_cgcg_init,
164 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
165 amdgpu_program_register_sequence(adev,
166 cz_golden_settings_a11,
167 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
168 break;
169 default:
170 break;
171 }
172}
173
174/**
175 * sdma_v3_0_init_microcode - load ucode images from disk
176 *
177 * @adev: amdgpu_device pointer
178 *
179 * Use the firmware interface to load the ucode images into
180 * the driver (not loaded into hw).
181 * Returns 0 on success, error on failure.
182 */
183static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
184{
185 const char *chip_name;
186 char fw_name[30];
187 int err, i;
188 struct amdgpu_firmware_info *info = NULL;
189 const struct common_firmware_header *header = NULL;
595fd013 190 const struct sdma_firmware_header_v1_0 *hdr;
aaa36a97
AD		 191
192 DRM_DEBUG("\n");
193
194 switch (adev->asic_type) {
195 case CHIP_TONGA:
196 chip_name = "tonga";
197 break;
1a5bbb66
DZ		 198 case CHIP_FIJI:
199 chip_name = "fiji";
200 break;
aaa36a97
AD		 201 case CHIP_CARRIZO:
202 chip_name = "carrizo";
203 break;
204 default: BUG();
205 }
206
207 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
208 if (i == 0)
c65444fe 209 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
aaa36a97 210 else
c65444fe 211 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
aaa36a97
AD		 212 err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
213 if (err)
214 goto out;
215 err = amdgpu_ucode_validate(adev->sdma[i].fw);
216 if (err)
217 goto out;
595fd013
JZ		 218 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
219 adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
220 adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
18111de0
JZ		 221 if (adev->sdma[i].feature_version >= 20)
222 adev->sdma[i].burst_nop = true;
aaa36a97
AD		 223
224 if (adev->firmware.smu_load) {
225 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
226 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
227 info->fw = adev->sdma[i].fw;
228 header = (const struct common_firmware_header *)info->fw->data;
229 adev->firmware.fw_size +=
230 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
231 }
232 }
233out:
234 if (err) {
235 printk(KERN_ERR
236 "sdma_v3_0: Failed to load firmware \"%s\"\n",
237 fw_name);
238 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
239 release_firmware(adev->sdma[i].fw);
240 adev->sdma[i].fw = NULL;
241 }
242 }
243 return err;
244}
245
246/**
247 * sdma_v3_0_ring_get_rptr - get the current read pointer
248 *
249 * @ring: amdgpu ring pointer
250 *
251 * Get the current rptr from the hardware (VI+).
252 */
253static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
254{
255 u32 rptr;
256
257 /* XXX check if swapping is necessary on BE */
258 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
259
260 return rptr;
261}
262
263/**
264 * sdma_v3_0_ring_get_wptr - get the current write pointer
265 *
266 * @ring: amdgpu ring pointer
267 *
268 * Get the current wptr from the hardware (VI+).
269 */
270static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
271{
272 struct amdgpu_device *adev = ring->adev;
273 u32 wptr;
274
275 if (ring->use_doorbell) {
276 /* XXX check if swapping is necessary on BE */
277 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
278 } else {
279 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
280
281 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
282 }
283
284 return wptr;
285}
286
287/**
288 * sdma_v3_0_ring_set_wptr - commit the write pointer
289 *
290 * @ring: amdgpu ring pointer
291 *
292 * Write the wptr back to the hardware (VI+).
293 */
294static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
295{
296 struct amdgpu_device *adev = ring->adev;
297
298 if (ring->use_doorbell) {
299 /* XXX check if swapping is necessary on BE */
300 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
301 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
302 } else {
303 int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
304
305 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
306 }
307}
308
aaa36a97
AD		 309/**
310 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
311 *
312 * @ring: amdgpu ring pointer
313 * @ib: IB object to schedule
314 *
315 * Schedule an IB in the DMA ring (VI).
316 */
317static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
318 struct amdgpu_ib *ib)
319{
320 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
321 u32 next_rptr = ring->wptr + 5;
322
aaa36a97
AD		 323 while ((next_rptr & 7) != 2)
324 next_rptr++;
325 next_rptr += 6;
326
327 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
328 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
329 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
330 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
331 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
332 amdgpu_ring_write(ring, next_rptr);
333
aaa36a97
AD		 334 /* IB packet must end on a 8 DW boundary */
335 while ((ring->wptr & 7) != 2)
336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_NOP));
337
338 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
339 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
340 /* base must be 32 byte aligned */
341 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
342 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
343 amdgpu_ring_write(ring, ib->length_dw);
344 amdgpu_ring_write(ring, 0);
345 amdgpu_ring_write(ring, 0);
346
347}
348
349/**
d2edb07b 350 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
aaa36a97
AD		 351 *
352 * @ring: amdgpu ring pointer
353 *
354 * Emit an hdp flush packet on the requested DMA ring.
355 */
d2edb07b 356static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 357{
358 u32 ref_and_mask = 0;
359
360 if (ring == &ring->adev->sdma[0].ring)
361 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
362 else
363 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
364
365 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
366 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
367 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
368 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
369 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
370 amdgpu_ring_write(ring, ref_and_mask); /* reference */
371 amdgpu_ring_write(ring, ref_and_mask); /* mask */
372 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
373 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
374}
375
376/**
377 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
378 *
379 * @ring: amdgpu ring pointer
380 * @fence: amdgpu fence object
381 *
382 * Add a DMA fence packet to the ring to write
383 * the fence seq number and DMA trap packet to generate
384 * an interrupt if needed (VI).
385 */
386static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 387 unsigned flags)
aaa36a97 388{
890ee23f 389 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
aaa36a97
AD		 390 /* write the fence */
391 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
392 amdgpu_ring_write(ring, lower_32_bits(addr));
393 amdgpu_ring_write(ring, upper_32_bits(addr));
394 amdgpu_ring_write(ring, lower_32_bits(seq));
395
396 /* optionally write high bits as well */
890ee23f 397 if (write64bit) {
aaa36a97
AD		 398 addr += 4;
399 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
400 amdgpu_ring_write(ring, lower_32_bits(addr));
401 amdgpu_ring_write(ring, upper_32_bits(addr));
402 amdgpu_ring_write(ring, upper_32_bits(seq));
403 }
404
405 /* generate an interrupt */
406 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
407 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
408}
409
410
411/**
412 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
413 *
414 * @ring: amdgpu_ring structure holding ring information
415 * @semaphore: amdgpu semaphore object
416 * @emit_wait: wait or signal semaphore
417 *
418 * Add a DMA semaphore packet to the ring wait on or signal
419 * other rings (VI).
420 */
421static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
422 struct amdgpu_semaphore *semaphore,
423 bool emit_wait)
424{
425 u64 addr = semaphore->gpu_addr;
426 u32 sig = emit_wait ? 0 : 1;
427
428 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
429 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
430 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
431 amdgpu_ring_write(ring, upper_32_bits(addr));
432
433 return true;
434}
435
436/**
437 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
438 *
439 * @adev: amdgpu_device pointer
440 *
441 * Stop the gfx async dma ring buffers (VI).
442 */
443static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
444{
445 struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
446 struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
447 u32 rb_cntl, ib_cntl;
448 int i;
449
450 if ((adev->mman.buffer_funcs_ring == sdma0) ||
451 (adev->mman.buffer_funcs_ring == sdma1))
452 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
453
454 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
455 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
456 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
457 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
458 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
459 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
460 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
461 }
462 sdma0->ready = false;
463 sdma1->ready = false;
464}
465
466/**
467 * sdma_v3_0_rlc_stop - stop the compute async dma engines
468 *
469 * @adev: amdgpu_device pointer
470 *
471 * Stop the compute async dma queues (VI).
472 */
473static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
474{
475 /* XXX todo */
476}
477
cd06bf68
BG		 478/**
479 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
480 *
481 * @adev: amdgpu_device pointer
482 * @enable: enable/disable the DMA MEs context switch.
483 *
484 * Halt or unhalt the async dma engines context switch (VI).
485 */
486static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
487{
488 u32 f32_cntl;
489 int i;
490
491 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
492 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
493 if (enable)
494 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
495 AUTO_CTXSW_ENABLE, 1);
496 else
497 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
498 AUTO_CTXSW_ENABLE, 0);
499 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
500 }
501}
502
aaa36a97
AD		 503/**
504 * sdma_v3_0_enable - stop the async dma engines
505 *
506 * @adev: amdgpu_device pointer
507 * @enable: enable/disable the DMA MEs.
508 *
509 * Halt or unhalt the async dma engines (VI).
510 */
511static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
512{
513 u32 f32_cntl;
514 int i;
515
516 if (enable == false) {
517 sdma_v3_0_gfx_stop(adev);
518 sdma_v3_0_rlc_stop(adev);
519 }
520
521 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
522 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
523 if (enable)
524 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
525 else
526 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
527 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
528 }
529}
530
531/**
532 * sdma_v3_0_gfx_resume - setup and start the async dma engines
533 *
534 * @adev: amdgpu_device pointer
535 *
536 * Set up the gfx DMA ring buffers and enable them (VI).
537 * Returns 0 for success, error for failure.
538 */
539static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
540{
541 struct amdgpu_ring *ring;
542 u32 rb_cntl, ib_cntl;
543 u32 rb_bufsz;
544 u32 wb_offset;
545 u32 doorbell;
546 int i, j, r;
547
548 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
549 ring = &adev->sdma[i].ring;
550 wb_offset = (ring->rptr_offs * 4);
551
552 mutex_lock(&adev->srbm_mutex);
553 for (j = 0; j < 16; j++) {
554 vi_srbm_select(adev, 0, 0, 0, j);
555 /* SDMA GFX */
556 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
557 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
558 }
559 vi_srbm_select(adev, 0, 0, 0, 0);
560 mutex_unlock(&adev->srbm_mutex);
561
562 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
563
564 /* Set ring buffer size in dwords */
565 rb_bufsz = order_base_2(ring->ring_size / 4);
566 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
567 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
568#ifdef __BIG_ENDIAN
569 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
570 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
571 RPTR_WRITEBACK_SWAP_ENABLE, 1);
572#endif
573 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
574
575 /* Initialize the ring buffer's read and write pointers */
576 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
577 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
578
579 /* set the wb address whether it's enabled or not */
580 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
581 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
582 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
583 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
584
585 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
586
587 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
588 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
589
590 ring->wptr = 0;
591 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
592
593 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
594
595 if (ring->use_doorbell) {
596 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
597 OFFSET, ring->doorbell_index);
598 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
599 } else {
600 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
601 }
602 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
603
604 /* enable DMA RB */
605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
606 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
607
608 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
609 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
610#ifdef __BIG_ENDIAN
611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
612#endif
613 /* enable DMA IBs */
614 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
615
616 ring->ready = true;
617
618 r = amdgpu_ring_test_ring(ring);
619 if (r) {
620 ring->ready = false;
621 return r;
622 }
623
624 if (adev->mman.buffer_funcs_ring == ring)
625 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
626 }
627
628 return 0;
629}
630
631/**
632 * sdma_v3_0_rlc_resume - setup and start the async dma engines
633 *
634 * @adev: amdgpu_device pointer
635 *
636 * Set up the compute DMA queues and enable them (VI).
637 * Returns 0 for success, error for failure.
638 */
639static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
640{
641 /* XXX todo */
642 return 0;
643}
644
645/**
646 * sdma_v3_0_load_microcode - load the sDMA ME ucode
647 *
648 * @adev: amdgpu_device pointer
649 *
650 * Loads the sDMA0/1 ucode.
651 * Returns 0 for success, -EINVAL if the ucode is not available.
652 */
653static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
654{
655 const struct sdma_firmware_header_v1_0 *hdr;
656 const __le32 *fw_data;
657 u32 fw_size;
658 int i, j;
659
660 if (!adev->sdma[0].fw || !adev->sdma[1].fw)
661 return -EINVAL;
662
663 /* halt the MEs */
664 sdma_v3_0_enable(adev, false);
665
666 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
667 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
668 amdgpu_ucode_print_sdma_hdr(&hdr->header);
669 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
aaa36a97
AD		 670 fw_data = (const __le32 *)
671 (adev->sdma[i].fw->data +
672 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
673 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
674 for (j = 0; j < fw_size; j++)
675 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
676 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
677 }
678
679 return 0;
680}
681
682/**
683 * sdma_v3_0_start - setup and start the async dma engines
684 *
685 * @adev: amdgpu_device pointer
686 *
687 * Set up the DMA engines and enable them (VI).
688 * Returns 0 for success, error for failure.
689 */
690static int sdma_v3_0_start(struct amdgpu_device *adev)
691{
692 int r;
693
694 if (!adev->firmware.smu_load) {
695 r = sdma_v3_0_load_microcode(adev);
696 if (r)
697 return r;
698 } else {
699 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
700 AMDGPU_UCODE_ID_SDMA0);
701 if (r)
702 return -EINVAL;
703 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
704 AMDGPU_UCODE_ID_SDMA1);
705 if (r)
706 return -EINVAL;
707 }
708
709 /* unhalt the MEs */
710 sdma_v3_0_enable(adev, true);
cd06bf68
BG		 711 /* enable sdma ring preemption */
712 sdma_v3_0_ctx_switch_enable(adev, true);
aaa36a97
AD		 713
714 /* start the gfx rings and rlc compute queues */
715 r = sdma_v3_0_gfx_resume(adev);
716 if (r)
717 return r;
718 r = sdma_v3_0_rlc_resume(adev);
719 if (r)
720 return r;
721
722 return 0;
723}
724
725/**
726 * sdma_v3_0_ring_test_ring - simple async dma engine test
727 *
728 * @ring: amdgpu_ring structure holding ring information
729 *
730 * Test the DMA engine by writing using it to write an
731 * value to memory. (VI).
732 * Returns 0 for success, error for failure.
733 */
734static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
735{
736 struct amdgpu_device *adev = ring->adev;
737 unsigned i;
738 unsigned index;
739 int r;
740 u32 tmp;
741 u64 gpu_addr;
742
743 r = amdgpu_wb_get(adev, &index);
744 if (r) {
745 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
746 return r;
747 }
748
749 gpu_addr = adev->wb.gpu_addr + (index * 4);
750 tmp = 0xCAFEDEAD;
751 adev->wb.wb[index] = cpu_to_le32(tmp);
752
753 r = amdgpu_ring_lock(ring, 5);
754 if (r) {
755 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
756 amdgpu_wb_free(adev, index);
757 return r;
758 }
759
760 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
761 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
762 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
763 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
764 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
765 amdgpu_ring_write(ring, 0xDEADBEEF);
766 amdgpu_ring_unlock_commit(ring);
767
768 for (i = 0; i < adev->usec_timeout; i++) {
769 tmp = le32_to_cpu(adev->wb.wb[index]);
770 if (tmp == 0xDEADBEEF)
771 break;
772 DRM_UDELAY(1);
773 }
774
775 if (i < adev->usec_timeout) {
776 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
777 } else {
778 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
779 ring->idx, tmp);
780 r = -EINVAL;
781 }
782 amdgpu_wb_free(adev, index);
783
784 return r;
785}
786
787/**
788 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
789 *
790 * @ring: amdgpu_ring structure holding ring information
791 *
792 * Test a simple IB in the DMA ring (VI).
793 * Returns 0 on success, error on failure.
794 */
795static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
796{
797 struct amdgpu_device *adev = ring->adev;
798 struct amdgpu_ib ib;
1763552e 799 struct fence *f = NULL;
aaa36a97
AD		 800 unsigned i;
801 unsigned index;
802 int r;
803 u32 tmp = 0;
804 u64 gpu_addr;
805
806 r = amdgpu_wb_get(adev, &index);
807 if (r) {
808 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
809 return r;
810 }
811
812 gpu_addr = adev->wb.gpu_addr + (index * 4);
813 tmp = 0xCAFEDEAD;
814 adev->wb.wb[index] = cpu_to_le32(tmp);
b203dd95 815 memset(&ib, 0, sizeof(ib));
aaa36a97
AD		 816 r = amdgpu_ib_get(ring, NULL, 256, &ib);
817 if (r) {
aaa36a97 818 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
0011fdaa 819 goto err0;
aaa36a97
AD		 820 }
821
822 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
823 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
824 ib.ptr[1] = lower_32_bits(gpu_addr);
825 ib.ptr[2] = upper_32_bits(gpu_addr);
826 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
827 ib.ptr[4] = 0xDEADBEEF;
828 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
829 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
830 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
831 ib.length_dw = 8;
832
0011fdaa 833 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
1763552e
CZ		 834 AMDGPU_FENCE_OWNER_UNDEFINED,
835 &f);
0011fdaa
CZ		 836 if (r)
837 goto err1;
838
1763552e 839 r = fence_wait(f, false);
aaa36a97 840 if (r) {
aaa36a97 841 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
0011fdaa 842 goto err1;
aaa36a97
AD		 843 }
844 for (i = 0; i < adev->usec_timeout; i++) {
845 tmp = le32_to_cpu(adev->wb.wb[index]);
846 if (tmp == 0xDEADBEEF)
847 break;
848 DRM_UDELAY(1);
849 }
850 if (i < adev->usec_timeout) {
851 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
0011fdaa
CZ		 852 ring->idx, i);
853 goto err1;
aaa36a97
AD		 854 } else {
855 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
856 r = -EINVAL;
857 }
0011fdaa 858err1:
281b4223 859 fence_put(f);
aaa36a97 860 amdgpu_ib_free(adev, &ib);
0011fdaa 861err0:
aaa36a97
AD		 862 amdgpu_wb_free(adev, index);
863 return r;
864}
865
866/**
867 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
868 *
869 * @ib: indirect buffer to fill with commands
870 * @pe: addr of the page entry
871 * @src: src addr to copy from
872 * @count: number of page entries to update
873 *
874 * Update PTEs by copying them from the GART using sDMA (CIK).
875 */
876static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
877 uint64_t pe, uint64_t src,
878 unsigned count)
879{
880 while (count) {
881 unsigned bytes = count * 8;
882 if (bytes > 0x1FFFF8)
883 bytes = 0x1FFFF8;
884
885 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
886 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
887 ib->ptr[ib->length_dw++] = bytes;
888 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
889 ib->ptr[ib->length_dw++] = lower_32_bits(src);
890 ib->ptr[ib->length_dw++] = upper_32_bits(src);
891 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
892 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
893
894 pe += bytes;
895 src += bytes;
896 count -= bytes / 8;
897 }
898}
899
900/**
901 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
902 *
903 * @ib: indirect buffer to fill with commands
904 * @pe: addr of the page entry
905 * @addr: dst addr to write into pe
906 * @count: number of page entries to update
907 * @incr: increase next addr by incr bytes
908 * @flags: access flags
909 *
910 * Update PTEs by writing them manually using sDMA (CIK).
911 */
912static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
913 uint64_t pe,
914 uint64_t addr, unsigned count,
915 uint32_t incr, uint32_t flags)
916{
917 uint64_t value;
918 unsigned ndw;
919
920 while (count) {
921 ndw = count * 2;
922 if (ndw > 0xFFFFE)
923 ndw = 0xFFFFE;
924
925 /* for non-physically contiguous pages (system) */
926 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
927 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
928 ib->ptr[ib->length_dw++] = pe;
929 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
930 ib->ptr[ib->length_dw++] = ndw;
931 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
932 if (flags & AMDGPU_PTE_SYSTEM) {
933 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
934 value &= 0xFFFFFFFFFFFFF000ULL;
935 } else if (flags & AMDGPU_PTE_VALID) {
936 value = addr;
937 } else {
938 value = 0;
939 }
940 addr += incr;
941 value |= flags;
942 ib->ptr[ib->length_dw++] = value;
943 ib->ptr[ib->length_dw++] = upper_32_bits(value);
944 }
945 }
946}
947
948/**
949 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
950 *
951 * @ib: indirect buffer to fill with commands
952 * @pe: addr of the page entry
953 * @addr: dst addr to write into pe
954 * @count: number of page entries to update
955 * @incr: increase next addr by incr bytes
956 * @flags: access flags
957 *
958 * Update the page tables using sDMA (CIK).
959 */
960static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
961 uint64_t pe,
962 uint64_t addr, unsigned count,
963 uint32_t incr, uint32_t flags)
964{
965 uint64_t value;
966 unsigned ndw;
967
968 while (count) {
969 ndw = count;
970 if (ndw > 0x7FFFF)
971 ndw = 0x7FFFF;
972
973 if (flags & AMDGPU_PTE_VALID)
974 value = addr;
975 else
976 value = 0;
977
978 /* for physically contiguous pages (vram) */
979 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
980 ib->ptr[ib->length_dw++] = pe; /* dst addr */
981 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
982 ib->ptr[ib->length_dw++] = flags; /* mask */
983 ib->ptr[ib->length_dw++] = 0;
984 ib->ptr[ib->length_dw++] = value; /* value */
985 ib->ptr[ib->length_dw++] = upper_32_bits(value);
986 ib->ptr[ib->length_dw++] = incr; /* increment size */
987 ib->ptr[ib->length_dw++] = 0;
988 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
989
990 pe += ndw * 8;
991 addr += ndw * incr;
992 count -= ndw;
993 }
994}
995
996/**
997 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
998 *
999 * @ib: indirect buffer to fill with padding
1000 *
1001 */
1002static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
1003{
1004 while (ib->length_dw & 0x7)
1005 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1006}
1007
1008/**
1009 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1010 *
1011 * @ring: amdgpu_ring pointer
1012 * @vm: amdgpu_vm pointer
1013 *
1014 * Update the page table base and flush the VM TLB
1015 * using sDMA (VI).
1016 */
1017static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1018 unsigned vm_id, uint64_t pd_addr)
1019{
aaa36a97
AD		 1020 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1021 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1022 if (vm_id < 8) {
1023 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1024 } else {
1025 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1026 }
1027 amdgpu_ring_write(ring, pd_addr >> 12);
1028
aaa36a97
AD		 1029 /* flush TLB */
1030 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1031 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1032 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1033 amdgpu_ring_write(ring, 1 << vm_id);
1034
1035 /* wait for flush */
1036 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1037 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1038 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1039 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1040 amdgpu_ring_write(ring, 0);
1041 amdgpu_ring_write(ring, 0); /* reference */
1042 amdgpu_ring_write(ring, 0); /* mask */
1043 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1044 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1045}
1046
5fc3aeeb 1047static int sdma_v3_0_early_init(void *handle)
aaa36a97 1048{
5fc3aeeb 1049 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050
aaa36a97
AD		 1051 sdma_v3_0_set_ring_funcs(adev);
1052 sdma_v3_0_set_buffer_funcs(adev);
1053 sdma_v3_0_set_vm_pte_funcs(adev);
1054 sdma_v3_0_set_irq_funcs(adev);
1055
1056 return 0;
1057}
1058
5fc3aeeb 1059static int sdma_v3_0_sw_init(void *handle)
aaa36a97
AD		 1060{
1061 struct amdgpu_ring *ring;
1062 int r;
5fc3aeeb 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1064
1065 /* SDMA trap event */
1066 r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
1067 if (r)
1068 return r;
1069
1070 /* SDMA Privileged inst */
1071 r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
1072 if (r)
1073 return r;
1074
1075 /* SDMA Privileged inst */
1076 r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
1077 if (r)
1078 return r;
1079
1080 r = sdma_v3_0_init_microcode(adev);
1081 if (r) {
1082 DRM_ERROR("Failed to load sdma firmware!\n");
1083 return r;
1084 }
1085
1086 ring = &adev->sdma[0].ring;
1087 ring->ring_obj = NULL;
1088 ring->use_doorbell = true;
1089 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0;
1090
1091 ring = &adev->sdma[1].ring;
1092 ring->ring_obj = NULL;
1093 ring->use_doorbell = true;
1094 ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1;
1095
1096 ring = &adev->sdma[0].ring;
1097 sprintf(ring->name, "sdma0");
1098 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1099 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1100 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
1101 AMDGPU_RING_TYPE_SDMA);
1102 if (r)
1103 return r;
1104
1105 ring = &adev->sdma[1].ring;
1106 sprintf(ring->name, "sdma1");
1107 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1108 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1109 &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
1110 AMDGPU_RING_TYPE_SDMA);
1111 if (r)
1112 return r;
1113
1114 return r;
1115}
1116
5fc3aeeb 1117static int sdma_v3_0_sw_fini(void *handle)
aaa36a97 1118{
5fc3aeeb 1119 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120
aaa36a97
AD		 1121 amdgpu_ring_fini(&adev->sdma[0].ring);
1122 amdgpu_ring_fini(&adev->sdma[1].ring);
1123
1124 return 0;
1125}
1126
5fc3aeeb 1127static int sdma_v3_0_hw_init(void *handle)
aaa36a97
AD		 1128{
1129 int r;
5fc3aeeb 1130 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1131
1132 sdma_v3_0_init_golden_registers(adev);
1133
1134 r = sdma_v3_0_start(adev);
1135 if (r)
1136 return r;
1137
1138 return r;
1139}
1140
5fc3aeeb 1141static int sdma_v3_0_hw_fini(void *handle)
aaa36a97 1142{
5fc3aeeb 1143 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1144
cd06bf68 1145 sdma_v3_0_ctx_switch_enable(adev, false);
aaa36a97
AD		 1146 sdma_v3_0_enable(adev, false);
1147
1148 return 0;
1149}
1150
5fc3aeeb 1151static int sdma_v3_0_suspend(void *handle)
aaa36a97 1152{
5fc3aeeb 1153 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1154
1155 return sdma_v3_0_hw_fini(adev);
1156}
1157
5fc3aeeb 1158static int sdma_v3_0_resume(void *handle)
aaa36a97 1159{
5fc3aeeb 1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1161
1162 return sdma_v3_0_hw_init(adev);
1163}
1164
5fc3aeeb 1165static bool sdma_v3_0_is_idle(void *handle)
aaa36a97 1166{
5fc3aeeb 1167 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1168 u32 tmp = RREG32(mmSRBM_STATUS2);
1169
1170 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1171 SRBM_STATUS2__SDMA1_BUSY_MASK))
1172 return false;
1173
1174 return true;
1175}
1176
5fc3aeeb 1177static int sdma_v3_0_wait_for_idle(void *handle)
aaa36a97
AD		 1178{
1179 unsigned i;
1180 u32 tmp;
5fc3aeeb 1181 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1182
1183 for (i = 0; i < adev->usec_timeout; i++) {
1184 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1185 SRBM_STATUS2__SDMA1_BUSY_MASK);
1186
1187 if (!tmp)
1188 return 0;
1189 udelay(1);
1190 }
1191 return -ETIMEDOUT;
1192}
1193
5fc3aeeb 1194static void sdma_v3_0_print_status(void *handle)
aaa36a97
AD		 1195{
1196 int i, j;
5fc3aeeb 1197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1198
1199 dev_info(adev->dev, "VI SDMA registers\n");
1200 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1201 RREG32(mmSRBM_STATUS2));
1202 for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
1203 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1204 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1205 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1206 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1207 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1208 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1209 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1210 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1211 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1212 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1213 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1214 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1215 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1216 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1217 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1218 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1219 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1220 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1221 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1222 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1223 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1224 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1225 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1226 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1227 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
1228 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1229 mutex_lock(&adev->srbm_mutex);
1230 for (j = 0; j < 16; j++) {
1231 vi_srbm_select(adev, 0, 0, 0, j);
1232 dev_info(adev->dev, " VM %d:\n", j);
1233 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1234 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1235 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1236 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1237 }
1238 vi_srbm_select(adev, 0, 0, 0, 0);
1239 mutex_unlock(&adev->srbm_mutex);
1240 }
1241}
1242
5fc3aeeb 1243static int sdma_v3_0_soft_reset(void *handle)
aaa36a97
AD		 1244{
1245 u32 srbm_soft_reset = 0;
5fc3aeeb 1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1247 u32 tmp = RREG32(mmSRBM_STATUS2);
1248
1249 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1250 /* sdma0 */
1251 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1252 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1253 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1254 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1255 }
1256 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1257 /* sdma1 */
1258 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1259 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1260 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1261 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1262 }
1263
1264 if (srbm_soft_reset) {
5fc3aeeb 1265 sdma_v3_0_print_status((void *)adev);
aaa36a97
AD		 1266
1267 tmp = RREG32(mmSRBM_SOFT_RESET);
1268 tmp |= srbm_soft_reset;
1269 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1270 WREG32(mmSRBM_SOFT_RESET, tmp);
1271 tmp = RREG32(mmSRBM_SOFT_RESET);
1272
1273 udelay(50);
1274
1275 tmp &= ~srbm_soft_reset;
1276 WREG32(mmSRBM_SOFT_RESET, tmp);
1277 tmp = RREG32(mmSRBM_SOFT_RESET);
1278
1279 /* Wait a little for things to settle down */
1280 udelay(50);
1281
5fc3aeeb 1282 sdma_v3_0_print_status((void *)adev);
aaa36a97
AD		 1283 }
1284
1285 return 0;
1286}
1287
1288static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1289 struct amdgpu_irq_src *source,
1290 unsigned type,
1291 enum amdgpu_interrupt_state state)
1292{
1293 u32 sdma_cntl;
1294
1295 switch (type) {
1296 case AMDGPU_SDMA_IRQ_TRAP0:
1297 switch (state) {
1298 case AMDGPU_IRQ_STATE_DISABLE:
1299 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1300 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1301 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1302 break;
1303 case AMDGPU_IRQ_STATE_ENABLE:
1304 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1305 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1306 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1307 break;
1308 default:
1309 break;
1310 }
1311 break;
1312 case AMDGPU_SDMA_IRQ_TRAP1:
1313 switch (state) {
1314 case AMDGPU_IRQ_STATE_DISABLE:
1315 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1316 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1317 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1318 break;
1319 case AMDGPU_IRQ_STATE_ENABLE:
1320 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1321 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1322 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1323 break;
1324 default:
1325 break;
1326 }
1327 break;
1328 default:
1329 break;
1330 }
1331 return 0;
1332}
1333
1334static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1335 struct amdgpu_irq_src *source,
1336 struct amdgpu_iv_entry *entry)
1337{
1338 u8 instance_id, queue_id;
1339
1340 instance_id = (entry->ring_id & 0x3) >> 0;
1341 queue_id = (entry->ring_id & 0xc) >> 2;
1342 DRM_DEBUG("IH: SDMA trap\n");
1343 switch (instance_id) {
1344 case 0:
1345 switch (queue_id) {
1346 case 0:
1347 amdgpu_fence_process(&adev->sdma[0].ring);
1348 break;
1349 case 1:
1350 /* XXX compute */
1351 break;
1352 case 2:
1353 /* XXX compute */
1354 break;
1355 }
1356 break;
1357 case 1:
1358 switch (queue_id) {
1359 case 0:
1360 amdgpu_fence_process(&adev->sdma[1].ring);
1361 break;
1362 case 1:
1363 /* XXX compute */
1364 break;
1365 case 2:
1366 /* XXX compute */
1367 break;
1368 }
1369 break;
1370 }
1371 return 0;
1372}
1373
1374static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1375 struct amdgpu_irq_src *source,
1376 struct amdgpu_iv_entry *entry)
1377{
1378 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1379 schedule_work(&adev->reset_work);
1380 return 0;
1381}
1382
5fc3aeeb 1383static int sdma_v3_0_set_clockgating_state(void *handle,
1384 enum amd_clockgating_state state)
aaa36a97 1385{
aaa36a97
AD		 1386 return 0;
1387}
1388
5fc3aeeb 1389static int sdma_v3_0_set_powergating_state(void *handle,
1390 enum amd_powergating_state state)
aaa36a97
AD		 1391{
1392 return 0;
1393}
1394
5fc3aeeb 1395const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
aaa36a97
AD		 1396 .early_init = sdma_v3_0_early_init,
1397 .late_init = NULL,
1398 .sw_init = sdma_v3_0_sw_init,
1399 .sw_fini = sdma_v3_0_sw_fini,
1400 .hw_init = sdma_v3_0_hw_init,
1401 .hw_fini = sdma_v3_0_hw_fini,
1402 .suspend = sdma_v3_0_suspend,
1403 .resume = sdma_v3_0_resume,
1404 .is_idle = sdma_v3_0_is_idle,
1405 .wait_for_idle = sdma_v3_0_wait_for_idle,
1406 .soft_reset = sdma_v3_0_soft_reset,
1407 .print_status = sdma_v3_0_print_status,
1408 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1409 .set_powergating_state = sdma_v3_0_set_powergating_state,
1410};
1411
1412/**
1413 * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
1414 *
1415 * @ring: amdgpu_ring structure holding ring information
1416 *
1417 * Check if the async DMA engine is locked up (VI).
1418 * Returns true if the engine appears to be locked up, false if not.
1419 */
1420static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
1421{
1422
1423 if (sdma_v3_0_is_idle(ring->adev)) {
1424 amdgpu_ring_lockup_update(ring);
1425 return false;
1426 }
1427 return amdgpu_ring_test_lockup(ring);
1428}
1429
1430static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1431 .get_rptr = sdma_v3_0_ring_get_rptr,
1432 .get_wptr = sdma_v3_0_ring_get_wptr,
1433 .set_wptr = sdma_v3_0_ring_set_wptr,
1434 .parse_cs = NULL,
1435 .emit_ib = sdma_v3_0_ring_emit_ib,
1436 .emit_fence = sdma_v3_0_ring_emit_fence,
1437 .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
1438 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
d2edb07b 1439 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
aaa36a97
AD		 1440 .test_ring = sdma_v3_0_ring_test_ring,
1441 .test_ib = sdma_v3_0_ring_test_ib,
1442 .is_lockup = sdma_v3_0_ring_is_lockup,
edff0e28 1443 .insert_nop = amdgpu_ring_insert_nop,
aaa36a97
AD		 1444};
1445
1446static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1447{
1448 adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs;
1449 adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs;
1450}
1451
1452static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1453 .set = sdma_v3_0_set_trap_irq_state,
1454 .process = sdma_v3_0_process_trap_irq,
1455};
1456
1457static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1458 .process = sdma_v3_0_process_illegal_inst_irq,
1459};
1460
1461static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1462{
1463 adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1464 adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1465 adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1466}
1467
1468/**
1469 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1470 *
1471 * @ring: amdgpu_ring structure holding ring information
1472 * @src_offset: src GPU address
1473 * @dst_offset: dst GPU address
1474 * @byte_count: number of bytes to xfer
1475 *
1476 * Copy GPU buffers using the DMA engine (VI).
1477 * Used by the amdgpu ttm implementation to move pages if
1478 * registered as the asic copy callback.
1479 */
c7ae72c0 1480static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
aaa36a97
AD		 1481 uint64_t src_offset,
1482 uint64_t dst_offset,
1483 uint32_t byte_count)
1484{
c7ae72c0
CZ		 1485 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1486 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1487 ib->ptr[ib->length_dw++] = byte_count;
1488 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1489 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1490 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1491 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1492 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
aaa36a97
AD		 1493}
1494
1495/**
1496 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1497 *
1498 * @ring: amdgpu_ring structure holding ring information
1499 * @src_data: value to write to buffer
1500 * @dst_offset: dst GPU address
1501 * @byte_count: number of bytes to xfer
1502 *
1503 * Fill GPU buffers using the DMA engine (VI).
1504 */
6e7a3840 1505static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
aaa36a97
AD		 1506 uint32_t src_data,
1507 uint64_t dst_offset,
1508 uint32_t byte_count)
1509{
6e7a3840
CZ		 1510 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1511 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1512 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1513 ib->ptr[ib->length_dw++] = src_data;
1514 ib->ptr[ib->length_dw++] = byte_count;
aaa36a97
AD		 1515}
1516
1517static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1518 .copy_max_bytes = 0x1fffff,
1519 .copy_num_dw = 7,
1520 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1521
1522 .fill_max_bytes = 0x1fffff,
1523 .fill_num_dw = 5,
1524 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1525};
1526
1527static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1528{
1529 if (adev->mman.buffer_funcs == NULL) {
1530 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1531 adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
1532 }
1533}
1534
1535static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1536 .copy_pte = sdma_v3_0_vm_copy_pte,
1537 .write_pte = sdma_v3_0_vm_write_pte,
1538 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1539 .pad_ib = sdma_v3_0_vm_pad_ib,
1540};
1541
1542static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1543{
1544 if (adev->vm_manager.vm_pte_funcs == NULL) {
1545 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1546 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
4274f5d4 1547 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
aaa36a97
AD		 1548 }
1549}
Linux 6.x block layer and io_uring tree(s)