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aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_ucode.h" | |
28 | #include "amdgpu_trace.h" | |
29 | #include "vi.h" | |
30 | #include "vid.h" | |
31 | ||
32 | #include "oss/oss_3_0_d.h" | |
33 | #include "oss/oss_3_0_sh_mask.h" | |
34 | ||
35 | #include "gmc/gmc_8_1_d.h" | |
36 | #include "gmc/gmc_8_1_sh_mask.h" | |
37 | ||
38 | #include "gca/gfx_8_0_d.h" | |
74a5d165 | 39 | #include "gca/gfx_8_0_enum.h" |
aaa36a97 AD |
40 | #include "gca/gfx_8_0_sh_mask.h" |
41 | ||
42 | #include "bif/bif_5_0_d.h" | |
43 | #include "bif/bif_5_0_sh_mask.h" | |
44 | ||
45 | #include "tonga_sdma_pkt_open.h" | |
46 | ||
47 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); | |
48 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); | |
49 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); | |
50 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); | |
51 | ||
c65444fe JZ |
52 | MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); |
53 | MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); | |
54 | MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); | |
55 | MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); | |
1a5bbb66 DZ |
56 | MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); |
57 | MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); | |
bb16e3b6 | 58 | MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); |
2cc0c0b5 FC |
59 | MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); |
60 | MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); | |
61 | MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); | |
62 | MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); | |
c4642a47 JZ |
63 | MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); |
64 | MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); | |
2cea03de | 65 | |
aaa36a97 AD |
66 | |
67 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
68 | { | |
69 | SDMA0_REGISTER_OFFSET, | |
70 | SDMA1_REGISTER_OFFSET | |
71 | }; | |
72 | ||
73 | static const u32 golden_settings_tonga_a11[] = | |
74 | { | |
75 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
76 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
77 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
78 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
79 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
80 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
81 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
82 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
83 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
84 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
85 | }; | |
86 | ||
87 | static const u32 tonga_mgcg_cgcg_init[] = | |
88 | { | |
89 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
90 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
91 | }; | |
92 | ||
1a5bbb66 DZ |
93 | static const u32 golden_settings_fiji_a10[] = |
94 | { | |
95 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
96 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
97 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
98 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
99 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
100 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
101 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
102 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
103 | }; | |
104 | ||
105 | static const u32 fiji_mgcg_cgcg_init[] = | |
106 | { | |
107 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
108 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
109 | }; | |
110 | ||
2cc0c0b5 | 111 | static const u32 golden_settings_polaris11_a11[] = |
2cea03de FC |
112 | { |
113 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
b9934878 | 114 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, |
2cea03de FC |
115 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, |
116 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
117 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
118 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
b9934878 | 119 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, |
2cea03de FC |
120 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, |
121 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
122 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
123 | }; | |
124 | ||
2cc0c0b5 | 125 | static const u32 golden_settings_polaris10_a11[] = |
2cea03de FC |
126 | { |
127 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
128 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
129 | mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
130 | mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
131 | mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
132 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
133 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
134 | mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, | |
135 | mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, | |
136 | mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, | |
137 | }; | |
138 | ||
aaa36a97 AD |
139 | static const u32 cz_golden_settings_a11[] = |
140 | { | |
141 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
142 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
143 | mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
144 | mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, | |
145 | mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
146 | mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
147 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
148 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
149 | mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
150 | mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800, | |
151 | mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
152 | mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
153 | }; | |
154 | ||
155 | static const u32 cz_mgcg_cgcg_init[] = | |
156 | { | |
157 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
158 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
159 | }; | |
160 | ||
bb16e3b6 SL |
161 | static const u32 stoney_golden_settings_a11[] = |
162 | { | |
163 | mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, | |
164 | mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, | |
165 | mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, | |
166 | mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, | |
167 | }; | |
168 | ||
169 | static const u32 stoney_mgcg_cgcg_init[] = | |
170 | { | |
171 | mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, | |
172 | }; | |
173 | ||
aaa36a97 AD |
174 | /* |
175 | * sDMA - System DMA | |
176 | * Starting with CIK, the GPU has new asynchronous | |
177 | * DMA engines. These engines are used for compute | |
178 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
179 | * and each one supports 1 ring buffer used for gfx | |
180 | * and 2 queues used for compute. | |
181 | * | |
182 | * The programming model is very similar to the CP | |
183 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
184 | * packet format that is different from the PM4 format | |
185 | * used by the CP. sDMA supports copying data, writing | |
186 | * embedded data, solid fills, and a number of other | |
187 | * things. It also has support for tiling/detiling of | |
188 | * buffers. | |
189 | */ | |
190 | ||
191 | static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) | |
192 | { | |
193 | switch (adev->asic_type) { | |
1a5bbb66 | 194 | case CHIP_FIJI: |
9c3f2b54 AD |
195 | amdgpu_device_program_register_sequence(adev, |
196 | fiji_mgcg_cgcg_init, | |
197 | ARRAY_SIZE(fiji_mgcg_cgcg_init)); | |
198 | amdgpu_device_program_register_sequence(adev, | |
199 | golden_settings_fiji_a10, | |
200 | ARRAY_SIZE(golden_settings_fiji_a10)); | |
1a5bbb66 | 201 | break; |
aaa36a97 | 202 | case CHIP_TONGA: |
9c3f2b54 AD |
203 | amdgpu_device_program_register_sequence(adev, |
204 | tonga_mgcg_cgcg_init, | |
205 | ARRAY_SIZE(tonga_mgcg_cgcg_init)); | |
206 | amdgpu_device_program_register_sequence(adev, | |
207 | golden_settings_tonga_a11, | |
208 | ARRAY_SIZE(golden_settings_tonga_a11)); | |
aaa36a97 | 209 | break; |
2cc0c0b5 | 210 | case CHIP_POLARIS11: |
c4642a47 | 211 | case CHIP_POLARIS12: |
9c3f2b54 AD |
212 | amdgpu_device_program_register_sequence(adev, |
213 | golden_settings_polaris11_a11, | |
214 | ARRAY_SIZE(golden_settings_polaris11_a11)); | |
2cea03de | 215 | break; |
2cc0c0b5 | 216 | case CHIP_POLARIS10: |
9c3f2b54 AD |
217 | amdgpu_device_program_register_sequence(adev, |
218 | golden_settings_polaris10_a11, | |
219 | ARRAY_SIZE(golden_settings_polaris10_a11)); | |
2cea03de | 220 | break; |
aaa36a97 | 221 | case CHIP_CARRIZO: |
9c3f2b54 AD |
222 | amdgpu_device_program_register_sequence(adev, |
223 | cz_mgcg_cgcg_init, | |
224 | ARRAY_SIZE(cz_mgcg_cgcg_init)); | |
225 | amdgpu_device_program_register_sequence(adev, | |
226 | cz_golden_settings_a11, | |
227 | ARRAY_SIZE(cz_golden_settings_a11)); | |
aaa36a97 | 228 | break; |
bb16e3b6 | 229 | case CHIP_STONEY: |
9c3f2b54 AD |
230 | amdgpu_device_program_register_sequence(adev, |
231 | stoney_mgcg_cgcg_init, | |
232 | ARRAY_SIZE(stoney_mgcg_cgcg_init)); | |
233 | amdgpu_device_program_register_sequence(adev, | |
234 | stoney_golden_settings_a11, | |
235 | ARRAY_SIZE(stoney_golden_settings_a11)); | |
bb16e3b6 | 236 | break; |
aaa36a97 AD |
237 | default: |
238 | break; | |
239 | } | |
240 | } | |
241 | ||
14d83e78 ML |
242 | static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) |
243 | { | |
244 | int i; | |
245 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
246 | release_firmware(adev->sdma.instance[i].fw); | |
247 | adev->sdma.instance[i].fw = NULL; | |
248 | } | |
249 | } | |
250 | ||
aaa36a97 AD |
251 | /** |
252 | * sdma_v3_0_init_microcode - load ucode images from disk | |
253 | * | |
254 | * @adev: amdgpu_device pointer | |
255 | * | |
256 | * Use the firmware interface to load the ucode images into | |
257 | * the driver (not loaded into hw). | |
258 | * Returns 0 on success, error on failure. | |
259 | */ | |
260 | static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) | |
261 | { | |
262 | const char *chip_name; | |
263 | char fw_name[30]; | |
c113ea1c | 264 | int err = 0, i; |
aaa36a97 AD |
265 | struct amdgpu_firmware_info *info = NULL; |
266 | const struct common_firmware_header *header = NULL; | |
595fd013 | 267 | const struct sdma_firmware_header_v1_0 *hdr; |
aaa36a97 AD |
268 | |
269 | DRM_DEBUG("\n"); | |
270 | ||
271 | switch (adev->asic_type) { | |
272 | case CHIP_TONGA: | |
273 | chip_name = "tonga"; | |
274 | break; | |
1a5bbb66 DZ |
275 | case CHIP_FIJI: |
276 | chip_name = "fiji"; | |
277 | break; | |
2cc0c0b5 FC |
278 | case CHIP_POLARIS11: |
279 | chip_name = "polaris11"; | |
2cea03de | 280 | break; |
2cc0c0b5 FC |
281 | case CHIP_POLARIS10: |
282 | chip_name = "polaris10"; | |
2cea03de | 283 | break; |
c4642a47 JZ |
284 | case CHIP_POLARIS12: |
285 | chip_name = "polaris12"; | |
286 | break; | |
aaa36a97 AD |
287 | case CHIP_CARRIZO: |
288 | chip_name = "carrizo"; | |
289 | break; | |
bb16e3b6 SL |
290 | case CHIP_STONEY: |
291 | chip_name = "stoney"; | |
292 | break; | |
aaa36a97 AD |
293 | default: BUG(); |
294 | } | |
295 | ||
c113ea1c | 296 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 | 297 | if (i == 0) |
c65444fe | 298 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); |
aaa36a97 | 299 | else |
c65444fe | 300 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); |
c113ea1c | 301 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
aaa36a97 AD |
302 | if (err) |
303 | goto out; | |
c113ea1c | 304 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
aaa36a97 AD |
305 | if (err) |
306 | goto out; | |
c113ea1c AD |
307 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; |
308 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); | |
309 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
310 | if (adev->sdma.instance[i].feature_version >= 20) | |
311 | adev->sdma.instance[i].burst_nop = true; | |
aaa36a97 | 312 | |
e635ee07 | 313 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { |
aaa36a97 AD |
314 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; |
315 | info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
c113ea1c | 316 | info->fw = adev->sdma.instance[i].fw; |
aaa36a97 AD |
317 | header = (const struct common_firmware_header *)info->fw->data; |
318 | adev->firmware.fw_size += | |
319 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
320 | } | |
321 | } | |
322 | out: | |
323 | if (err) { | |
7ca85295 | 324 | pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); |
c113ea1c AD |
325 | for (i = 0; i < adev->sdma.num_instances; i++) { |
326 | release_firmware(adev->sdma.instance[i].fw); | |
327 | adev->sdma.instance[i].fw = NULL; | |
aaa36a97 AD |
328 | } |
329 | } | |
330 | return err; | |
331 | } | |
332 | ||
333 | /** | |
334 | * sdma_v3_0_ring_get_rptr - get the current read pointer | |
335 | * | |
336 | * @ring: amdgpu ring pointer | |
337 | * | |
338 | * Get the current rptr from the hardware (VI+). | |
339 | */ | |
536fbf94 | 340 | static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) |
aaa36a97 | 341 | { |
aaa36a97 | 342 | /* XXX check if swapping is necessary on BE */ |
d912adef | 343 | return ring->adev->wb.wb[ring->rptr_offs] >> 2; |
aaa36a97 AD |
344 | } |
345 | ||
346 | /** | |
347 | * sdma_v3_0_ring_get_wptr - get the current write pointer | |
348 | * | |
349 | * @ring: amdgpu ring pointer | |
350 | * | |
351 | * Get the current wptr from the hardware (VI+). | |
352 | */ | |
536fbf94 | 353 | static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) |
aaa36a97 AD |
354 | { |
355 | struct amdgpu_device *adev = ring->adev; | |
356 | u32 wptr; | |
357 | ||
2ffe31de | 358 | if (ring->use_doorbell || ring->use_pollmem) { |
aaa36a97 AD |
359 | /* XXX check if swapping is necessary on BE */ |
360 | wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; | |
361 | } else { | |
c113ea1c | 362 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 AD |
363 | |
364 | wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; | |
365 | } | |
366 | ||
367 | return wptr; | |
368 | } | |
369 | ||
370 | /** | |
371 | * sdma_v3_0_ring_set_wptr - commit the write pointer | |
372 | * | |
373 | * @ring: amdgpu ring pointer | |
374 | * | |
375 | * Write the wptr back to the hardware (VI+). | |
376 | */ | |
377 | static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) | |
378 | { | |
379 | struct amdgpu_device *adev = ring->adev; | |
380 | ||
381 | if (ring->use_doorbell) { | |
3e4b0bd9 | 382 | u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; |
aaa36a97 | 383 | /* XXX check if swapping is necessary on BE */ |
3e4b0bd9 | 384 | WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); |
536fbf94 | 385 | WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); |
2ffe31de PD |
386 | } else if (ring->use_pollmem) { |
387 | u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; | |
388 | ||
389 | WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); | |
aaa36a97 | 390 | } else { |
c113ea1c | 391 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 | 392 | |
536fbf94 | 393 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2); |
aaa36a97 AD |
394 | } |
395 | } | |
396 | ||
ac01db3d JZ |
397 | static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
398 | { | |
c113ea1c | 399 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
400 | int i; |
401 | ||
402 | for (i = 0; i < count; i++) | |
403 | if (sdma && sdma->burst_nop && (i == 0)) | |
79887142 | 404 | amdgpu_ring_write(ring, ring->funcs->nop | |
ac01db3d JZ |
405 | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); |
406 | else | |
79887142 | 407 | amdgpu_ring_write(ring, ring->funcs->nop); |
ac01db3d JZ |
408 | } |
409 | ||
aaa36a97 AD |
410 | /** |
411 | * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine | |
412 | * | |
413 | * @ring: amdgpu ring pointer | |
414 | * @ib: IB object to schedule | |
415 | * | |
416 | * Schedule an IB in the DMA ring (VI). | |
417 | */ | |
418 | static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, | |
d88bf583 | 419 | struct amdgpu_ib *ib, |
c4f46f22 | 420 | unsigned vmid, bool ctx_switch) |
aaa36a97 | 421 | { |
aaa36a97 | 422 | /* IB packet must end on a 8 DW boundary */ |
536fbf94 | 423 | sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); |
aaa36a97 AD |
424 | |
425 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | | |
c4f46f22 | 426 | SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); |
aaa36a97 AD |
427 | /* base must be 32 byte aligned */ |
428 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); | |
429 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
430 | amdgpu_ring_write(ring, ib->length_dw); | |
431 | amdgpu_ring_write(ring, 0); | |
432 | amdgpu_ring_write(ring, 0); | |
433 | ||
434 | } | |
435 | ||
436 | /** | |
d2edb07b | 437 | * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
aaa36a97 AD |
438 | * |
439 | * @ring: amdgpu ring pointer | |
440 | * | |
441 | * Emit an hdp flush packet on the requested DMA ring. | |
442 | */ | |
d2edb07b | 443 | static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
aaa36a97 AD |
444 | { |
445 | u32 ref_and_mask = 0; | |
446 | ||
c113ea1c | 447 | if (ring == &ring->adev->sdma.instance[0].ring) |
aaa36a97 AD |
448 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); |
449 | else | |
450 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); | |
451 | ||
452 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
453 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | | |
454 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ | |
455 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
456 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
457 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
458 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
459 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
460 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
461 | } | |
462 | ||
463 | /** | |
464 | * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring | |
465 | * | |
466 | * @ring: amdgpu ring pointer | |
467 | * @fence: amdgpu fence object | |
468 | * | |
469 | * Add a DMA fence packet to the ring to write | |
470 | * the fence seq number and DMA trap packet to generate | |
471 | * an interrupt if needed (VI). | |
472 | */ | |
473 | static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 474 | unsigned flags) |
aaa36a97 | 475 | { |
890ee23f | 476 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
aaa36a97 AD |
477 | /* write the fence */ |
478 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
479 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
480 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
481 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
482 | ||
483 | /* optionally write high bits as well */ | |
890ee23f | 484 | if (write64bit) { |
aaa36a97 AD |
485 | addr += 4; |
486 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
487 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
488 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
489 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
490 | } | |
491 | ||
492 | /* generate an interrupt */ | |
493 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); | |
494 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); | |
495 | } | |
496 | ||
aaa36a97 AD |
497 | /** |
498 | * sdma_v3_0_gfx_stop - stop the gfx async dma engines | |
499 | * | |
500 | * @adev: amdgpu_device pointer | |
501 | * | |
502 | * Stop the gfx async dma ring buffers (VI). | |
503 | */ | |
504 | static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) | |
505 | { | |
c113ea1c AD |
506 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
507 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | |
aaa36a97 AD |
508 | u32 rb_cntl, ib_cntl; |
509 | int i; | |
510 | ||
511 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
512 | (adev->mman.buffer_funcs_ring == sdma1)) | |
770d13b1 | 513 | amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); |
aaa36a97 | 514 | |
c113ea1c | 515 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
516 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
517 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); | |
518 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
519 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
520 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); | |
521 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
522 | } | |
523 | sdma0->ready = false; | |
524 | sdma1->ready = false; | |
525 | } | |
526 | ||
527 | /** | |
528 | * sdma_v3_0_rlc_stop - stop the compute async dma engines | |
529 | * | |
530 | * @adev: amdgpu_device pointer | |
531 | * | |
532 | * Stop the compute async dma queues (VI). | |
533 | */ | |
534 | static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) | |
535 | { | |
536 | /* XXX todo */ | |
537 | } | |
538 | ||
cd06bf68 BG |
539 | /** |
540 | * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch | |
541 | * | |
542 | * @adev: amdgpu_device pointer | |
543 | * @enable: enable/disable the DMA MEs context switch. | |
544 | * | |
545 | * Halt or unhalt the async dma engines context switch (VI). | |
546 | */ | |
547 | static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) | |
548 | { | |
a667386c | 549 | u32 f32_cntl, phase_quantum = 0; |
cd06bf68 BG |
550 | int i; |
551 | ||
a667386c FK |
552 | if (amdgpu_sdma_phase_quantum) { |
553 | unsigned value = amdgpu_sdma_phase_quantum; | |
554 | unsigned unit = 0; | |
555 | ||
556 | while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> | |
557 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { | |
558 | value = (value + 1) >> 1; | |
559 | unit++; | |
560 | } | |
561 | if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> | |
562 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { | |
563 | value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> | |
564 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); | |
565 | unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> | |
566 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); | |
567 | WARN_ONCE(1, | |
568 | "clamping sdma_phase_quantum to %uK clock cycles\n", | |
569 | value << unit); | |
570 | } | |
571 | phase_quantum = | |
572 | value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | | |
573 | unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; | |
574 | } | |
575 | ||
c113ea1c | 576 | for (i = 0; i < adev->sdma.num_instances; i++) { |
cd06bf68 | 577 | f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); |
4048f0f0 | 578 | if (enable) { |
cd06bf68 BG |
579 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, |
580 | AUTO_CTXSW_ENABLE, 1); | |
4048f0f0 | 581 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, |
582 | ATC_L1_ENABLE, 1); | |
a667386c FK |
583 | if (amdgpu_sdma_phase_quantum) { |
584 | WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], | |
585 | phase_quantum); | |
586 | WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], | |
587 | phase_quantum); | |
588 | } | |
4048f0f0 | 589 | } else { |
cd06bf68 BG |
590 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, |
591 | AUTO_CTXSW_ENABLE, 0); | |
4048f0f0 | 592 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, |
593 | ATC_L1_ENABLE, 1); | |
594 | } | |
595 | ||
cd06bf68 BG |
596 | WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); |
597 | } | |
598 | } | |
599 | ||
aaa36a97 AD |
600 | /** |
601 | * sdma_v3_0_enable - stop the async dma engines | |
602 | * | |
603 | * @adev: amdgpu_device pointer | |
604 | * @enable: enable/disable the DMA MEs. | |
605 | * | |
606 | * Halt or unhalt the async dma engines (VI). | |
607 | */ | |
608 | static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) | |
609 | { | |
610 | u32 f32_cntl; | |
611 | int i; | |
612 | ||
004e29cc | 613 | if (!enable) { |
aaa36a97 AD |
614 | sdma_v3_0_gfx_stop(adev); |
615 | sdma_v3_0_rlc_stop(adev); | |
616 | } | |
617 | ||
c113ea1c | 618 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
619 | f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
620 | if (enable) | |
621 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); | |
622 | else | |
623 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); | |
624 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); | |
625 | } | |
626 | } | |
627 | ||
628 | /** | |
629 | * sdma_v3_0_gfx_resume - setup and start the async dma engines | |
630 | * | |
631 | * @adev: amdgpu_device pointer | |
632 | * | |
633 | * Set up the gfx DMA ring buffers and enable them (VI). | |
634 | * Returns 0 for success, error for failure. | |
635 | */ | |
636 | static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) | |
637 | { | |
638 | struct amdgpu_ring *ring; | |
e33dac39 | 639 | u32 rb_cntl, ib_cntl, wptr_poll_cntl; |
aaa36a97 AD |
640 | u32 rb_bufsz; |
641 | u32 wb_offset; | |
642 | u32 doorbell; | |
e33dac39 | 643 | u64 wptr_gpu_addr; |
aaa36a97 AD |
644 | int i, j, r; |
645 | ||
c113ea1c AD |
646 | for (i = 0; i < adev->sdma.num_instances; i++) { |
647 | ring = &adev->sdma.instance[i].ring; | |
f6bd7942 | 648 | amdgpu_ring_clear_ring(ring); |
aaa36a97 AD |
649 | wb_offset = (ring->rptr_offs * 4); |
650 | ||
651 | mutex_lock(&adev->srbm_mutex); | |
652 | for (j = 0; j < 16; j++) { | |
653 | vi_srbm_select(adev, 0, 0, 0, j); | |
654 | /* SDMA GFX */ | |
655 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
656 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
657 | } | |
658 | vi_srbm_select(adev, 0, 0, 0, 0); | |
659 | mutex_unlock(&adev->srbm_mutex); | |
660 | ||
c458fe94 AD |
661 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
662 | adev->gfx.config.gb_addr_config & 0x70); | |
663 | ||
aaa36a97 AD |
664 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); |
665 | ||
666 | /* Set ring buffer size in dwords */ | |
667 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
668 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); | |
669 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); | |
670 | #ifdef __BIG_ENDIAN | |
671 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); | |
672 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, | |
673 | RPTR_WRITEBACK_SWAP_ENABLE, 1); | |
674 | #endif | |
675 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
676 | ||
677 | /* Initialize the ring buffer's read and write pointers */ | |
78cb9083 | 678 | ring->wptr = 0; |
aaa36a97 | 679 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); |
78cb9083 | 680 | sdma_v3_0_ring_set_wptr(ring); |
d72f7c06 ML |
681 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); |
682 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); | |
aaa36a97 AD |
683 | |
684 | /* set the wb address whether it's enabled or not */ | |
685 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
686 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
687 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
688 | lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); | |
689 | ||
690 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); | |
691 | ||
692 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
693 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
694 | ||
aaa36a97 AD |
695 | doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); |
696 | ||
697 | if (ring->use_doorbell) { | |
698 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, | |
699 | OFFSET, ring->doorbell_index); | |
700 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); | |
701 | } else { | |
702 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); | |
703 | } | |
704 | WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); | |
705 | ||
e33dac39 XY |
706 | /* setup the wptr shadow polling */ |
707 | wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); | |
708 | ||
709 | WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], | |
710 | lower_32_bits(wptr_gpu_addr)); | |
711 | WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], | |
712 | upper_32_bits(wptr_gpu_addr)); | |
713 | wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); | |
2ffe31de PD |
714 | if (ring->use_pollmem) |
715 | wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, | |
716 | SDMA0_GFX_RB_WPTR_POLL_CNTL, | |
717 | ENABLE, 1); | |
e33dac39 | 718 | else |
2ffe31de PD |
719 | wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, |
720 | SDMA0_GFX_RB_WPTR_POLL_CNTL, | |
721 | ENABLE, 0); | |
e33dac39 XY |
722 | WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); |
723 | ||
aaa36a97 AD |
724 | /* enable DMA RB */ |
725 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); | |
726 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
727 | ||
728 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
729 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); | |
730 | #ifdef __BIG_ENDIAN | |
731 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); | |
732 | #endif | |
733 | /* enable DMA IBs */ | |
734 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
735 | ||
736 | ring->ready = true; | |
505dfe76 | 737 | } |
aaa36a97 | 738 | |
505dfe76 ML |
739 | /* unhalt the MEs */ |
740 | sdma_v3_0_enable(adev, true); | |
741 | /* enable sdma ring preemption */ | |
742 | sdma_v3_0_ctx_switch_enable(adev, true); | |
743 | ||
744 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
745 | ring = &adev->sdma.instance[i].ring; | |
aaa36a97 AD |
746 | r = amdgpu_ring_test_ring(ring); |
747 | if (r) { | |
748 | ring->ready = false; | |
749 | return r; | |
750 | } | |
751 | ||
752 | if (adev->mman.buffer_funcs_ring == ring) | |
770d13b1 | 753 | amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); |
aaa36a97 AD |
754 | } |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
759 | /** | |
760 | * sdma_v3_0_rlc_resume - setup and start the async dma engines | |
761 | * | |
762 | * @adev: amdgpu_device pointer | |
763 | * | |
764 | * Set up the compute DMA queues and enable them (VI). | |
765 | * Returns 0 for success, error for failure. | |
766 | */ | |
767 | static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) | |
768 | { | |
769 | /* XXX todo */ | |
770 | return 0; | |
771 | } | |
772 | ||
773 | /** | |
774 | * sdma_v3_0_load_microcode - load the sDMA ME ucode | |
775 | * | |
776 | * @adev: amdgpu_device pointer | |
777 | * | |
778 | * Loads the sDMA0/1 ucode. | |
779 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
780 | */ | |
781 | static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) | |
782 | { | |
783 | const struct sdma_firmware_header_v1_0 *hdr; | |
784 | const __le32 *fw_data; | |
785 | u32 fw_size; | |
786 | int i, j; | |
787 | ||
aaa36a97 AD |
788 | /* halt the MEs */ |
789 | sdma_v3_0_enable(adev, false); | |
790 | ||
c113ea1c AD |
791 | for (i = 0; i < adev->sdma.num_instances; i++) { |
792 | if (!adev->sdma.instance[i].fw) | |
793 | return -EINVAL; | |
794 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
aaa36a97 AD |
795 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
796 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
aaa36a97 | 797 | fw_data = (const __le32 *) |
c113ea1c | 798 | (adev->sdma.instance[i].fw->data + |
aaa36a97 AD |
799 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
800 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); | |
801 | for (j = 0; j < fw_size; j++) | |
802 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
c113ea1c | 803 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); |
aaa36a97 AD |
804 | } |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | /** | |
810 | * sdma_v3_0_start - setup and start the async dma engines | |
811 | * | |
812 | * @adev: amdgpu_device pointer | |
813 | * | |
814 | * Set up the DMA engines and enable them (VI). | |
815 | * Returns 0 for success, error for failure. | |
816 | */ | |
817 | static int sdma_v3_0_start(struct amdgpu_device *adev) | |
818 | { | |
790d84fd | 819 | int r; |
aaa36a97 | 820 | |
790d84fd RZ |
821 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
822 | r = sdma_v3_0_load_microcode(adev); | |
823 | if (r) | |
824 | return r; | |
aaa36a97 AD |
825 | } |
826 | ||
8a1115ff | 827 | /* disable sdma engine before programing it */ |
505dfe76 ML |
828 | sdma_v3_0_ctx_switch_enable(adev, false); |
829 | sdma_v3_0_enable(adev, false); | |
aaa36a97 AD |
830 | |
831 | /* start the gfx rings and rlc compute queues */ | |
832 | r = sdma_v3_0_gfx_resume(adev); | |
833 | if (r) | |
834 | return r; | |
835 | r = sdma_v3_0_rlc_resume(adev); | |
836 | if (r) | |
837 | return r; | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
842 | /** | |
843 | * sdma_v3_0_ring_test_ring - simple async dma engine test | |
844 | * | |
845 | * @ring: amdgpu_ring structure holding ring information | |
846 | * | |
847 | * Test the DMA engine by writing using it to write an | |
848 | * value to memory. (VI). | |
849 | * Returns 0 for success, error for failure. | |
850 | */ | |
851 | static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) | |
852 | { | |
853 | struct amdgpu_device *adev = ring->adev; | |
854 | unsigned i; | |
855 | unsigned index; | |
856 | int r; | |
857 | u32 tmp; | |
858 | u64 gpu_addr; | |
859 | ||
131b4b36 | 860 | r = amdgpu_device_wb_get(adev, &index); |
aaa36a97 AD |
861 | if (r) { |
862 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
863 | return r; | |
864 | } | |
865 | ||
866 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
867 | tmp = 0xCAFEDEAD; | |
868 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
869 | ||
a27de35c | 870 | r = amdgpu_ring_alloc(ring, 5); |
aaa36a97 AD |
871 | if (r) { |
872 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
131b4b36 | 873 | amdgpu_device_wb_free(adev, index); |
aaa36a97 AD |
874 | return r; |
875 | } | |
876 | ||
877 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
878 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | |
879 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
880 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
881 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | |
882 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 883 | amdgpu_ring_commit(ring); |
aaa36a97 AD |
884 | |
885 | for (i = 0; i < adev->usec_timeout; i++) { | |
886 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
887 | if (tmp == 0xDEADBEEF) | |
888 | break; | |
889 | DRM_UDELAY(1); | |
890 | } | |
891 | ||
892 | if (i < adev->usec_timeout) { | |
9953b72f | 893 | DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
aaa36a97 AD |
894 | } else { |
895 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
896 | ring->idx, tmp); | |
897 | r = -EINVAL; | |
898 | } | |
131b4b36 | 899 | amdgpu_device_wb_free(adev, index); |
aaa36a97 AD |
900 | |
901 | return r; | |
902 | } | |
903 | ||
904 | /** | |
905 | * sdma_v3_0_ring_test_ib - test an IB on the DMA engine | |
906 | * | |
907 | * @ring: amdgpu_ring structure holding ring information | |
908 | * | |
909 | * Test a simple IB in the DMA ring (VI). | |
910 | * Returns 0 on success, error on failure. | |
911 | */ | |
bbec97aa | 912 | static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
aaa36a97 AD |
913 | { |
914 | struct amdgpu_device *adev = ring->adev; | |
915 | struct amdgpu_ib ib; | |
f54d1867 | 916 | struct dma_fence *f = NULL; |
aaa36a97 | 917 | unsigned index; |
aaa36a97 AD |
918 | u32 tmp = 0; |
919 | u64 gpu_addr; | |
bbec97aa | 920 | long r; |
aaa36a97 | 921 | |
131b4b36 | 922 | r = amdgpu_device_wb_get(adev, &index); |
aaa36a97 | 923 | if (r) { |
bbec97aa | 924 | dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); |
aaa36a97 AD |
925 | return r; |
926 | } | |
927 | ||
928 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
929 | tmp = 0xCAFEDEAD; | |
930 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
b203dd95 | 931 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 932 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
aaa36a97 | 933 | if (r) { |
bbec97aa | 934 | DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); |
0011fdaa | 935 | goto err0; |
aaa36a97 AD |
936 | } |
937 | ||
938 | ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
939 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); | |
940 | ib.ptr[1] = lower_32_bits(gpu_addr); | |
941 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
942 | ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); | |
943 | ib.ptr[4] = 0xDEADBEEF; | |
944 | ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
945 | ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
946 | ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); | |
947 | ib.length_dw = 8; | |
948 | ||
50ddc75e | 949 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); |
0011fdaa CZ |
950 | if (r) |
951 | goto err1; | |
952 | ||
f54d1867 | 953 | r = dma_fence_wait_timeout(f, false, timeout); |
bbec97aa CK |
954 | if (r == 0) { |
955 | DRM_ERROR("amdgpu: IB test timed out\n"); | |
956 | r = -ETIMEDOUT; | |
957 | goto err1; | |
958 | } else if (r < 0) { | |
959 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); | |
0011fdaa | 960 | goto err1; |
aaa36a97 | 961 | } |
6d44565d CK |
962 | tmp = le32_to_cpu(adev->wb.wb[index]); |
963 | if (tmp == 0xDEADBEEF) { | |
9953b72f | 964 | DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); |
bbec97aa | 965 | r = 0; |
aaa36a97 AD |
966 | } else { |
967 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
968 | r = -EINVAL; | |
969 | } | |
0011fdaa | 970 | err1: |
cc55c45d | 971 | amdgpu_ib_free(adev, &ib, NULL); |
f54d1867 | 972 | dma_fence_put(f); |
0011fdaa | 973 | err0: |
131b4b36 | 974 | amdgpu_device_wb_free(adev, index); |
aaa36a97 AD |
975 | return r; |
976 | } | |
977 | ||
978 | /** | |
979 | * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART | |
980 | * | |
981 | * @ib: indirect buffer to fill with commands | |
982 | * @pe: addr of the page entry | |
983 | * @src: src addr to copy from | |
984 | * @count: number of page entries to update | |
985 | * | |
986 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
987 | */ | |
988 | static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, | |
989 | uint64_t pe, uint64_t src, | |
990 | unsigned count) | |
991 | { | |
96105e53 CK |
992 | unsigned bytes = count * 8; |
993 | ||
994 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | | |
995 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
996 | ib->ptr[ib->length_dw++] = bytes; | |
997 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
998 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
999 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
1000 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
1001 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
aaa36a97 AD |
1002 | } |
1003 | ||
1004 | /** | |
1005 | * sdma_v3_0_vm_write_pte - update PTEs by writing them manually | |
1006 | * | |
1007 | * @ib: indirect buffer to fill with commands | |
1008 | * @pe: addr of the page entry | |
de9ea7bd | 1009 | * @value: dst addr to write into pe |
aaa36a97 AD |
1010 | * @count: number of page entries to update |
1011 | * @incr: increase next addr by incr bytes | |
aaa36a97 AD |
1012 | * |
1013 | * Update PTEs by writing them manually using sDMA (CIK). | |
1014 | */ | |
de9ea7bd CK |
1015 | static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, |
1016 | uint64_t value, unsigned count, | |
1017 | uint32_t incr) | |
aaa36a97 | 1018 | { |
de9ea7bd CK |
1019 | unsigned ndw = count * 2; |
1020 | ||
1021 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
6bf3f9c3 | 1022 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); |
de9ea7bd CK |
1023 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
1024 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
1025 | ib->ptr[ib->length_dw++] = ndw; | |
4bc07289 | 1026 | for (; ndw > 0; ndw -= 2) { |
de9ea7bd CK |
1027 | ib->ptr[ib->length_dw++] = lower_32_bits(value); |
1028 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
1029 | value += incr; | |
aaa36a97 AD |
1030 | } |
1031 | } | |
1032 | ||
1033 | /** | |
1034 | * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA | |
1035 | * | |
1036 | * @ib: indirect buffer to fill with commands | |
1037 | * @pe: addr of the page entry | |
1038 | * @addr: dst addr to write into pe | |
1039 | * @count: number of page entries to update | |
1040 | * @incr: increase next addr by incr bytes | |
1041 | * @flags: access flags | |
1042 | * | |
1043 | * Update the page tables using sDMA (CIK). | |
1044 | */ | |
96105e53 | 1045 | static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, |
aaa36a97 | 1046 | uint64_t addr, unsigned count, |
6b777607 | 1047 | uint32_t incr, uint64_t flags) |
aaa36a97 | 1048 | { |
96105e53 CK |
1049 | /* for physically contiguous pages (vram) */ |
1050 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); | |
1051 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ | |
1052 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
b9be700e JZ |
1053 | ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ |
1054 | ib->ptr[ib->length_dw++] = upper_32_bits(flags); | |
96105e53 CK |
1055 | ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ |
1056 | ib->ptr[ib->length_dw++] = upper_32_bits(addr); | |
1057 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
1058 | ib->ptr[ib->length_dw++] = 0; | |
1059 | ib->ptr[ib->length_dw++] = count; /* number of entries */ | |
aaa36a97 AD |
1060 | } |
1061 | ||
1062 | /** | |
9e5d5309 | 1063 | * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw |
aaa36a97 AD |
1064 | * |
1065 | * @ib: indirect buffer to fill with padding | |
1066 | * | |
1067 | */ | |
9e5d5309 | 1068 | static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
aaa36a97 | 1069 | { |
9e5d5309 | 1070 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
1071 | u32 pad_count; |
1072 | int i; | |
1073 | ||
1074 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; | |
1075 | for (i = 0; i < pad_count; i++) | |
1076 | if (sdma && sdma->burst_nop && (i == 0)) | |
1077 | ib->ptr[ib->length_dw++] = | |
1078 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | | |
1079 | SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); | |
1080 | else | |
1081 | ib->ptr[ib->length_dw++] = | |
1082 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP); | |
aaa36a97 AD |
1083 | } |
1084 | ||
1085 | /** | |
00b7c4ff | 1086 | * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline |
aaa36a97 AD |
1087 | * |
1088 | * @ring: amdgpu_ring pointer | |
aaa36a97 | 1089 | * |
00b7c4ff | 1090 | * Make sure all previous operations are completed (CIK). |
aaa36a97 | 1091 | */ |
00b7c4ff | 1092 | static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
aaa36a97 | 1093 | { |
5c55db83 CZ |
1094 | uint32_t seq = ring->fence_drv.sync_seq; |
1095 | uint64_t addr = ring->fence_drv.gpu_addr; | |
1096 | ||
1097 | /* wait for idle */ | |
1098 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
1099 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
1100 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ | |
1101 | SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); | |
1102 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
1103 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
1104 | amdgpu_ring_write(ring, seq); /* reference */ | |
1105 | amdgpu_ring_write(ring, 0xfffffff); /* mask */ | |
1106 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
1107 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ | |
00b7c4ff | 1108 | } |
5c55db83 | 1109 | |
00b7c4ff CK |
1110 | /** |
1111 | * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA | |
1112 | * | |
1113 | * @ring: amdgpu_ring pointer | |
1114 | * @vm: amdgpu_vm pointer | |
1115 | * | |
1116 | * Update the page table base and flush the VM TLB | |
1117 | * using sDMA (VI). | |
1118 | */ | |
1119 | static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
c633c00b | 1120 | unsigned vmid, uint64_t pd_addr) |
00b7c4ff | 1121 | { |
c633c00b | 1122 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
aaa36a97 AD |
1123 | |
1124 | /* wait for flush */ | |
1125 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
1126 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
1127 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ | |
1128 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
1129 | amdgpu_ring_write(ring, 0); | |
1130 | amdgpu_ring_write(ring, 0); /* reference */ | |
1131 | amdgpu_ring_write(ring, 0); /* mask */ | |
1132 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
1133 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
1134 | } | |
1135 | ||
3d31d4cb CK |
1136 | static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, |
1137 | uint32_t reg, uint32_t val) | |
1138 | { | |
1139 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | | |
1140 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
1141 | amdgpu_ring_write(ring, reg); | |
1142 | amdgpu_ring_write(ring, val); | |
1143 | } | |
1144 | ||
5fc3aeeb | 1145 | static int sdma_v3_0_early_init(void *handle) |
aaa36a97 | 1146 | { |
5fc3aeeb | 1147 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1148 | ||
c113ea1c | 1149 | switch (adev->asic_type) { |
bb16e3b6 SL |
1150 | case CHIP_STONEY: |
1151 | adev->sdma.num_instances = 1; | |
1152 | break; | |
c113ea1c AD |
1153 | default: |
1154 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; | |
1155 | break; | |
1156 | } | |
1157 | ||
aaa36a97 AD |
1158 | sdma_v3_0_set_ring_funcs(adev); |
1159 | sdma_v3_0_set_buffer_funcs(adev); | |
1160 | sdma_v3_0_set_vm_pte_funcs(adev); | |
1161 | sdma_v3_0_set_irq_funcs(adev); | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
5fc3aeeb | 1166 | static int sdma_v3_0_sw_init(void *handle) |
aaa36a97 AD |
1167 | { |
1168 | struct amdgpu_ring *ring; | |
c113ea1c | 1169 | int r, i; |
5fc3aeeb | 1170 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1171 | |
1172 | /* SDMA trap event */ | |
d766e6a3 AD |
1173 | r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, |
1174 | &adev->sdma.trap_irq); | |
aaa36a97 AD |
1175 | if (r) |
1176 | return r; | |
1177 | ||
1178 | /* SDMA Privileged inst */ | |
d766e6a3 AD |
1179 | r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, |
1180 | &adev->sdma.illegal_inst_irq); | |
aaa36a97 AD |
1181 | if (r) |
1182 | return r; | |
1183 | ||
1184 | /* SDMA Privileged inst */ | |
d766e6a3 AD |
1185 | r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, |
1186 | &adev->sdma.illegal_inst_irq); | |
aaa36a97 AD |
1187 | if (r) |
1188 | return r; | |
1189 | ||
1190 | r = sdma_v3_0_init_microcode(adev); | |
1191 | if (r) { | |
1192 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
1193 | return r; | |
1194 | } | |
1195 | ||
c113ea1c AD |
1196 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1197 | ring = &adev->sdma.instance[i].ring; | |
1198 | ring->ring_obj = NULL; | |
2ffe31de PD |
1199 | if (!amdgpu_sriov_vf(adev)) { |
1200 | ring->use_doorbell = true; | |
1201 | ring->doorbell_index = (i == 0) ? | |
1202 | AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; | |
1203 | } else { | |
1204 | ring->use_pollmem = true; | |
1205 | } | |
c113ea1c AD |
1206 | |
1207 | sprintf(ring->name, "sdma%d", i); | |
b38d99c4 | 1208 | r = amdgpu_ring_init(adev, ring, 1024, |
c113ea1c AD |
1209 | &adev->sdma.trap_irq, |
1210 | (i == 0) ? | |
21cd942e CK |
1211 | AMDGPU_SDMA_IRQ_TRAP0 : |
1212 | AMDGPU_SDMA_IRQ_TRAP1); | |
c113ea1c AD |
1213 | if (r) |
1214 | return r; | |
1215 | } | |
aaa36a97 AD |
1216 | |
1217 | return r; | |
1218 | } | |
1219 | ||
5fc3aeeb | 1220 | static int sdma_v3_0_sw_fini(void *handle) |
aaa36a97 | 1221 | { |
5fc3aeeb | 1222 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 1223 | int i; |
5fc3aeeb | 1224 | |
c113ea1c AD |
1225 | for (i = 0; i < adev->sdma.num_instances; i++) |
1226 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
aaa36a97 | 1227 | |
14d83e78 | 1228 | sdma_v3_0_free_microcode(adev); |
aaa36a97 AD |
1229 | return 0; |
1230 | } | |
1231 | ||
5fc3aeeb | 1232 | static int sdma_v3_0_hw_init(void *handle) |
aaa36a97 AD |
1233 | { |
1234 | int r; | |
5fc3aeeb | 1235 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1236 | |
1237 | sdma_v3_0_init_golden_registers(adev); | |
1238 | ||
1239 | r = sdma_v3_0_start(adev); | |
1240 | if (r) | |
1241 | return r; | |
1242 | ||
1243 | return r; | |
1244 | } | |
1245 | ||
5fc3aeeb | 1246 | static int sdma_v3_0_hw_fini(void *handle) |
aaa36a97 | 1247 | { |
5fc3aeeb | 1248 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1249 | ||
cd06bf68 | 1250 | sdma_v3_0_ctx_switch_enable(adev, false); |
aaa36a97 AD |
1251 | sdma_v3_0_enable(adev, false); |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
5fc3aeeb | 1256 | static int sdma_v3_0_suspend(void *handle) |
aaa36a97 | 1257 | { |
5fc3aeeb | 1258 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1259 | |
1260 | return sdma_v3_0_hw_fini(adev); | |
1261 | } | |
1262 | ||
5fc3aeeb | 1263 | static int sdma_v3_0_resume(void *handle) |
aaa36a97 | 1264 | { |
5fc3aeeb | 1265 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1266 | |
1267 | return sdma_v3_0_hw_init(adev); | |
1268 | } | |
1269 | ||
5fc3aeeb | 1270 | static bool sdma_v3_0_is_idle(void *handle) |
aaa36a97 | 1271 | { |
5fc3aeeb | 1272 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1273 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1274 | ||
1275 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1276 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1277 | return false; | |
1278 | ||
1279 | return true; | |
1280 | } | |
1281 | ||
5fc3aeeb | 1282 | static int sdma_v3_0_wait_for_idle(void *handle) |
aaa36a97 AD |
1283 | { |
1284 | unsigned i; | |
1285 | u32 tmp; | |
5fc3aeeb | 1286 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1287 | |
1288 | for (i = 0; i < adev->usec_timeout; i++) { | |
1289 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1290 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1291 | ||
1292 | if (!tmp) | |
1293 | return 0; | |
1294 | udelay(1); | |
1295 | } | |
1296 | return -ETIMEDOUT; | |
1297 | } | |
1298 | ||
da146d3b | 1299 | static bool sdma_v3_0_check_soft_reset(void *handle) |
aaa36a97 | 1300 | { |
5fc3aeeb | 1301 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
e702a680 | 1302 | u32 srbm_soft_reset = 0; |
aaa36a97 AD |
1303 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1304 | ||
e702a680 CZ |
1305 | if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) || |
1306 | (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) { | |
aaa36a97 | 1307 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; |
aaa36a97 AD |
1308 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; |
1309 | } | |
1310 | ||
e702a680 | 1311 | if (srbm_soft_reset) { |
e702a680 | 1312 | adev->sdma.srbm_soft_reset = srbm_soft_reset; |
da146d3b | 1313 | return true; |
e702a680 | 1314 | } else { |
e702a680 | 1315 | adev->sdma.srbm_soft_reset = 0; |
da146d3b | 1316 | return false; |
e702a680 | 1317 | } |
e702a680 CZ |
1318 | } |
1319 | ||
1320 | static int sdma_v3_0_pre_soft_reset(void *handle) | |
1321 | { | |
1322 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1323 | u32 srbm_soft_reset = 0; | |
1324 | ||
da146d3b | 1325 | if (!adev->sdma.srbm_soft_reset) |
e702a680 CZ |
1326 | return 0; |
1327 | ||
1328 | srbm_soft_reset = adev->sdma.srbm_soft_reset; | |
1329 | ||
1330 | if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || | |
1331 | REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { | |
1332 | sdma_v3_0_ctx_switch_enable(adev, false); | |
1333 | sdma_v3_0_enable(adev, false); | |
1334 | } | |
1335 | ||
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | static int sdma_v3_0_post_soft_reset(void *handle) | |
1340 | { | |
1341 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1342 | u32 srbm_soft_reset = 0; | |
1343 | ||
da146d3b | 1344 | if (!adev->sdma.srbm_soft_reset) |
e702a680 CZ |
1345 | return 0; |
1346 | ||
1347 | srbm_soft_reset = adev->sdma.srbm_soft_reset; | |
1348 | ||
1349 | if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) || | |
1350 | REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) { | |
1351 | sdma_v3_0_gfx_resume(adev); | |
1352 | sdma_v3_0_rlc_resume(adev); | |
1353 | } | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int sdma_v3_0_soft_reset(void *handle) | |
1359 | { | |
1360 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1361 | u32 srbm_soft_reset = 0; | |
1362 | u32 tmp; | |
1363 | ||
da146d3b | 1364 | if (!adev->sdma.srbm_soft_reset) |
e702a680 CZ |
1365 | return 0; |
1366 | ||
1367 | srbm_soft_reset = adev->sdma.srbm_soft_reset; | |
1368 | ||
aaa36a97 | 1369 | if (srbm_soft_reset) { |
aaa36a97 AD |
1370 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1371 | tmp |= srbm_soft_reset; | |
1372 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1373 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1374 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1375 | ||
1376 | udelay(50); | |
1377 | ||
1378 | tmp &= ~srbm_soft_reset; | |
1379 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1380 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1381 | ||
1382 | /* Wait a little for things to settle down */ | |
1383 | udelay(50); | |
aaa36a97 AD |
1384 | } |
1385 | ||
1386 | return 0; | |
1387 | } | |
1388 | ||
1389 | static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, | |
1390 | struct amdgpu_irq_src *source, | |
1391 | unsigned type, | |
1392 | enum amdgpu_interrupt_state state) | |
1393 | { | |
1394 | u32 sdma_cntl; | |
1395 | ||
1396 | switch (type) { | |
1397 | case AMDGPU_SDMA_IRQ_TRAP0: | |
1398 | switch (state) { | |
1399 | case AMDGPU_IRQ_STATE_DISABLE: | |
1400 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1401 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1402 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1403 | break; | |
1404 | case AMDGPU_IRQ_STATE_ENABLE: | |
1405 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1406 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1407 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1408 | break; | |
1409 | default: | |
1410 | break; | |
1411 | } | |
1412 | break; | |
1413 | case AMDGPU_SDMA_IRQ_TRAP1: | |
1414 | switch (state) { | |
1415 | case AMDGPU_IRQ_STATE_DISABLE: | |
1416 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1417 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1418 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1419 | break; | |
1420 | case AMDGPU_IRQ_STATE_ENABLE: | |
1421 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1422 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1423 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1424 | break; | |
1425 | default: | |
1426 | break; | |
1427 | } | |
1428 | break; | |
1429 | default: | |
1430 | break; | |
1431 | } | |
1432 | return 0; | |
1433 | } | |
1434 | ||
1435 | static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, | |
1436 | struct amdgpu_irq_src *source, | |
1437 | struct amdgpu_iv_entry *entry) | |
1438 | { | |
1439 | u8 instance_id, queue_id; | |
1440 | ||
1441 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1442 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1443 | DRM_DEBUG("IH: SDMA trap\n"); | |
1444 | switch (instance_id) { | |
1445 | case 0: | |
1446 | switch (queue_id) { | |
1447 | case 0: | |
c113ea1c | 1448 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
aaa36a97 AD |
1449 | break; |
1450 | case 1: | |
1451 | /* XXX compute */ | |
1452 | break; | |
1453 | case 2: | |
1454 | /* XXX compute */ | |
1455 | break; | |
1456 | } | |
1457 | break; | |
1458 | case 1: | |
1459 | switch (queue_id) { | |
1460 | case 0: | |
c113ea1c | 1461 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
aaa36a97 AD |
1462 | break; |
1463 | case 1: | |
1464 | /* XXX compute */ | |
1465 | break; | |
1466 | case 2: | |
1467 | /* XXX compute */ | |
1468 | break; | |
1469 | } | |
1470 | break; | |
1471 | } | |
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1476 | struct amdgpu_irq_src *source, | |
1477 | struct amdgpu_iv_entry *entry) | |
1478 | { | |
1479 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
1480 | schedule_work(&adev->reset_work); | |
1481 | return 0; | |
1482 | } | |
1483 | ||
ce22362b | 1484 | static void sdma_v3_0_update_sdma_medium_grain_clock_gating( |
3c997d24 EH |
1485 | struct amdgpu_device *adev, |
1486 | bool enable) | |
1487 | { | |
1488 | uint32_t temp, data; | |
ce22362b | 1489 | int i; |
3c997d24 | 1490 | |
e08d53cb | 1491 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { |
ce22362b AD |
1492 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1493 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); | |
1494 | data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | | |
1495 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | | |
1496 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | | |
1497 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | | |
1498 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | | |
1499 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | | |
1500 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | | |
1501 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); | |
1502 | if (data != temp) | |
1503 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); | |
1504 | } | |
3c997d24 | 1505 | } else { |
ce22362b AD |
1506 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1507 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); | |
1508 | data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | | |
3c997d24 EH |
1509 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | |
1510 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | | |
1511 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | | |
1512 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | | |
1513 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | | |
1514 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | | |
1515 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; | |
1516 | ||
ce22362b AD |
1517 | if (data != temp) |
1518 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); | |
1519 | } | |
3c997d24 EH |
1520 | } |
1521 | } | |
1522 | ||
ce22362b | 1523 | static void sdma_v3_0_update_sdma_medium_grain_light_sleep( |
3c997d24 EH |
1524 | struct amdgpu_device *adev, |
1525 | bool enable) | |
1526 | { | |
1527 | uint32_t temp, data; | |
ce22362b | 1528 | int i; |
3c997d24 | 1529 | |
e08d53cb | 1530 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { |
ce22362b AD |
1531 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1532 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); | |
1533 | data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; | |
3c997d24 | 1534 | |
ce22362b AD |
1535 | if (temp != data) |
1536 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); | |
1537 | } | |
3c997d24 | 1538 | } else { |
ce22362b AD |
1539 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1540 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); | |
1541 | data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; | |
3c997d24 | 1542 | |
ce22362b AD |
1543 | if (temp != data) |
1544 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); | |
1545 | } | |
3c997d24 EH |
1546 | } |
1547 | } | |
1548 | ||
5fc3aeeb | 1549 | static int sdma_v3_0_set_clockgating_state(void *handle, |
1550 | enum amd_clockgating_state state) | |
aaa36a97 | 1551 | { |
3c997d24 EH |
1552 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1553 | ||
ce137c04 ML |
1554 | if (amdgpu_sriov_vf(adev)) |
1555 | return 0; | |
1556 | ||
3c997d24 EH |
1557 | switch (adev->asic_type) { |
1558 | case CHIP_FIJI: | |
ce22362b AD |
1559 | case CHIP_CARRIZO: |
1560 | case CHIP_STONEY: | |
1561 | sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, | |
7e913664 | 1562 | state == AMD_CG_STATE_GATE); |
ce22362b | 1563 | sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, |
7e913664 | 1564 | state == AMD_CG_STATE_GATE); |
3c997d24 EH |
1565 | break; |
1566 | default: | |
1567 | break; | |
1568 | } | |
aaa36a97 AD |
1569 | return 0; |
1570 | } | |
1571 | ||
5fc3aeeb | 1572 | static int sdma_v3_0_set_powergating_state(void *handle, |
1573 | enum amd_powergating_state state) | |
aaa36a97 AD |
1574 | { |
1575 | return 0; | |
1576 | } | |
1577 | ||
41c360f6 HR |
1578 | static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) |
1579 | { | |
1580 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1581 | int data; | |
1582 | ||
ce137c04 ML |
1583 | if (amdgpu_sriov_vf(adev)) |
1584 | *flags = 0; | |
1585 | ||
41c360f6 HR |
1586 | /* AMD_CG_SUPPORT_SDMA_MGCG */ |
1587 | data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); | |
1588 | if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK)) | |
1589 | *flags |= AMD_CG_SUPPORT_SDMA_MGCG; | |
1590 | ||
1591 | /* AMD_CG_SUPPORT_SDMA_LS */ | |
1592 | data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); | |
1593 | if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) | |
1594 | *flags |= AMD_CG_SUPPORT_SDMA_LS; | |
1595 | } | |
1596 | ||
a1255107 | 1597 | static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { |
88a907d6 | 1598 | .name = "sdma_v3_0", |
aaa36a97 AD |
1599 | .early_init = sdma_v3_0_early_init, |
1600 | .late_init = NULL, | |
1601 | .sw_init = sdma_v3_0_sw_init, | |
1602 | .sw_fini = sdma_v3_0_sw_fini, | |
1603 | .hw_init = sdma_v3_0_hw_init, | |
1604 | .hw_fini = sdma_v3_0_hw_fini, | |
1605 | .suspend = sdma_v3_0_suspend, | |
1606 | .resume = sdma_v3_0_resume, | |
1607 | .is_idle = sdma_v3_0_is_idle, | |
1608 | .wait_for_idle = sdma_v3_0_wait_for_idle, | |
e702a680 CZ |
1609 | .check_soft_reset = sdma_v3_0_check_soft_reset, |
1610 | .pre_soft_reset = sdma_v3_0_pre_soft_reset, | |
1611 | .post_soft_reset = sdma_v3_0_post_soft_reset, | |
aaa36a97 | 1612 | .soft_reset = sdma_v3_0_soft_reset, |
aaa36a97 AD |
1613 | .set_clockgating_state = sdma_v3_0_set_clockgating_state, |
1614 | .set_powergating_state = sdma_v3_0_set_powergating_state, | |
41c360f6 | 1615 | .get_clockgating_state = sdma_v3_0_get_clockgating_state, |
aaa36a97 AD |
1616 | }; |
1617 | ||
aaa36a97 | 1618 | static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { |
21cd942e | 1619 | .type = AMDGPU_RING_TYPE_SDMA, |
79887142 CK |
1620 | .align_mask = 0xf, |
1621 | .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), | |
536fbf94 | 1622 | .support_64bit_ptrs = false, |
aaa36a97 AD |
1623 | .get_rptr = sdma_v3_0_ring_get_rptr, |
1624 | .get_wptr = sdma_v3_0_ring_get_wptr, | |
1625 | .set_wptr = sdma_v3_0_ring_set_wptr, | |
e12f3d7a CK |
1626 | .emit_frame_size = |
1627 | 6 + /* sdma_v3_0_ring_emit_hdp_flush */ | |
2ee150cd | 1628 | 3 + /* hdp invalidate */ |
e12f3d7a | 1629 | 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ |
49135593 | 1630 | VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ |
e12f3d7a CK |
1631 | 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ |
1632 | .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ | |
aaa36a97 AD |
1633 | .emit_ib = sdma_v3_0_ring_emit_ib, |
1634 | .emit_fence = sdma_v3_0_ring_emit_fence, | |
00b7c4ff | 1635 | .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, |
aaa36a97 | 1636 | .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, |
d2edb07b | 1637 | .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, |
aaa36a97 AD |
1638 | .test_ring = sdma_v3_0_ring_test_ring, |
1639 | .test_ib = sdma_v3_0_ring_test_ib, | |
ac01db3d | 1640 | .insert_nop = sdma_v3_0_ring_insert_nop, |
9e5d5309 | 1641 | .pad_ib = sdma_v3_0_ring_pad_ib, |
3d31d4cb | 1642 | .emit_wreg = sdma_v3_0_ring_emit_wreg, |
aaa36a97 AD |
1643 | }; |
1644 | ||
1645 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) | |
1646 | { | |
c113ea1c AD |
1647 | int i; |
1648 | ||
1649 | for (i = 0; i < adev->sdma.num_instances; i++) | |
1650 | adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; | |
aaa36a97 AD |
1651 | } |
1652 | ||
1653 | static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { | |
1654 | .set = sdma_v3_0_set_trap_irq_state, | |
1655 | .process = sdma_v3_0_process_trap_irq, | |
1656 | }; | |
1657 | ||
1658 | static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { | |
1659 | .process = sdma_v3_0_process_illegal_inst_irq, | |
1660 | }; | |
1661 | ||
1662 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) | |
1663 | { | |
c113ea1c AD |
1664 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1665 | adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; | |
1666 | adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; | |
aaa36a97 AD |
1667 | } |
1668 | ||
1669 | /** | |
1670 | * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine | |
1671 | * | |
1672 | * @ring: amdgpu_ring structure holding ring information | |
1673 | * @src_offset: src GPU address | |
1674 | * @dst_offset: dst GPU address | |
1675 | * @byte_count: number of bytes to xfer | |
1676 | * | |
1677 | * Copy GPU buffers using the DMA engine (VI). | |
1678 | * Used by the amdgpu ttm implementation to move pages if | |
1679 | * registered as the asic copy callback. | |
1680 | */ | |
c7ae72c0 | 1681 | static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1682 | uint64_t src_offset, |
1683 | uint64_t dst_offset, | |
1684 | uint32_t byte_count) | |
1685 | { | |
c7ae72c0 CZ |
1686 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | |
1687 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
1688 | ib->ptr[ib->length_dw++] = byte_count; | |
1689 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
1690 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
1691 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); | |
1692 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1693 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
aaa36a97 AD |
1694 | } |
1695 | ||
1696 | /** | |
1697 | * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine | |
1698 | * | |
1699 | * @ring: amdgpu_ring structure holding ring information | |
1700 | * @src_data: value to write to buffer | |
1701 | * @dst_offset: dst GPU address | |
1702 | * @byte_count: number of bytes to xfer | |
1703 | * | |
1704 | * Fill GPU buffers using the DMA engine (VI). | |
1705 | */ | |
6e7a3840 | 1706 | static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1707 | uint32_t src_data, |
1708 | uint64_t dst_offset, | |
1709 | uint32_t byte_count) | |
1710 | { | |
6e7a3840 CZ |
1711 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); |
1712 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1713 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
1714 | ib->ptr[ib->length_dw++] = src_data; | |
1715 | ib->ptr[ib->length_dw++] = byte_count; | |
aaa36a97 AD |
1716 | } |
1717 | ||
1718 | static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { | |
dfe5c2b7 | 1719 | .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ |
aaa36a97 AD |
1720 | .copy_num_dw = 7, |
1721 | .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, | |
1722 | ||
dfe5c2b7 | 1723 | .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ |
aaa36a97 AD |
1724 | .fill_num_dw = 5, |
1725 | .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, | |
1726 | }; | |
1727 | ||
1728 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) | |
1729 | { | |
1730 | if (adev->mman.buffer_funcs == NULL) { | |
1731 | adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; | |
c113ea1c | 1732 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
aaa36a97 AD |
1733 | } |
1734 | } | |
1735 | ||
1736 | static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { | |
e6d92197 | 1737 | .copy_pte_num_dw = 7, |
aaa36a97 | 1738 | .copy_pte = sdma_v3_0_vm_copy_pte, |
e6d92197 | 1739 | |
aaa36a97 AD |
1740 | .write_pte = sdma_v3_0_vm_write_pte, |
1741 | .set_pte_pde = sdma_v3_0_vm_set_pte_pde, | |
aaa36a97 AD |
1742 | }; |
1743 | ||
1744 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1745 | { | |
2d55e45a CK |
1746 | unsigned i; |
1747 | ||
aaa36a97 AD |
1748 | if (adev->vm_manager.vm_pte_funcs == NULL) { |
1749 | adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; | |
2d55e45a CK |
1750 | for (i = 0; i < adev->sdma.num_instances; i++) |
1751 | adev->vm_manager.vm_pte_rings[i] = | |
1752 | &adev->sdma.instance[i].ring; | |
1753 | ||
1754 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; | |
aaa36a97 AD |
1755 | } |
1756 | } | |
a1255107 AD |
1757 | |
1758 | const struct amdgpu_ip_block_version sdma_v3_0_ip_block = | |
1759 | { | |
1760 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1761 | .major = 3, | |
1762 | .minor = 0, | |
1763 | .rev = 0, | |
1764 | .funcs = &sdma_v3_0_ip_funcs, | |
1765 | }; | |
1766 | ||
1767 | const struct amdgpu_ip_block_version sdma_v3_1_ip_block = | |
1768 | { | |
1769 | .type = AMD_IP_BLOCK_TYPE_SDMA, | |
1770 | .major = 3, | |
1771 | .minor = 1, | |
1772 | .rev = 0, | |
1773 | .funcs = &sdma_v3_0_ip_funcs, | |
1774 | }; |