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Merge remote-tracking branches 'asoc/topic/fsl-spdif', 'asoc/topic/hdmi', 'asoc/topic...
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / sdma_v3_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "vi.h"
30#include "vid.h"
31
32#include "oss/oss_3_0_d.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "gca/gfx_8_0_d.h"
74a5d165 39#include "gca/gfx_8_0_enum.h"
aaa36a97
AD		 40#include "gca/gfx_8_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "tonga_sdma_pkt_open.h"
46
47static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
51
c65444fe
JZ		 52MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
53MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
54MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
55MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
1a5bbb66
DZ		 56MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
57MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
bb16e3b6 58MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
2cc0c0b5
FC		 59MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
60MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
61MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
62MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
2cea03de 63
aaa36a97
AD		 64
65static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
66{
67 SDMA0_REGISTER_OFFSET,
68 SDMA1_REGISTER_OFFSET
69};
70
71static const u32 golden_settings_tonga_a11[] =
72{
73 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
74 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
75 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
76 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
77 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
78 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
79 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
80 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
81 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
82 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
83};
84
85static const u32 tonga_mgcg_cgcg_init[] =
86{
87 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
88 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
89};
90
1a5bbb66
DZ		 91static const u32 golden_settings_fiji_a10[] =
92{
93 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
94 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
95 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
96 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
97 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
98 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
99 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
100 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
101};
102
103static const u32 fiji_mgcg_cgcg_init[] =
104{
105 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
106 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
107};
108
2cc0c0b5 109static const u32 golden_settings_polaris11_a11[] =
2cea03de
FC		 110{
111 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
b9934878 112 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
2cea03de
FC		 113 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
114 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
115 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
116 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
b9934878 117 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
2cea03de
FC		 118 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
119 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
120 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
121};
122
2cc0c0b5 123static const u32 golden_settings_polaris10_a11[] =
2cea03de
FC		 124{
125 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
126 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
127 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
129 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
130 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
131 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
132 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
133 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
134 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
135};
136
aaa36a97
AD		 137static const u32 cz_golden_settings_a11[] =
138{
139 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
140 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
141 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
142 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
143 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
144 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
145 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
146 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
147 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
148 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
149 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
150 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
151};
152
153static const u32 cz_mgcg_cgcg_init[] =
154{
155 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
156 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
157};
158
bb16e3b6
SL		 159static const u32 stoney_golden_settings_a11[] =
160{
161 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
162 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
163 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
164 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
165};
166
167static const u32 stoney_mgcg_cgcg_init[] =
168{
169 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
170};
171
aaa36a97
AD		 172/*
173 * sDMA - System DMA
174 * Starting with CIK, the GPU has new asynchronous
175 * DMA engines. These engines are used for compute
176 * and gfx. There are two DMA engines (SDMA0, SDMA1)
177 * and each one supports 1 ring buffer used for gfx
178 * and 2 queues used for compute.
179 *
180 * The programming model is very similar to the CP
181 * (ring buffer, IBs, etc.), but sDMA has it's own
182 * packet format that is different from the PM4 format
183 * used by the CP. sDMA supports copying data, writing
184 * embedded data, solid fills, and a number of other
185 * things. It also has support for tiling/detiling of
186 * buffers.
187 */
188
189static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
190{
191 switch (adev->asic_type) {
1a5bbb66
DZ		 192 case CHIP_FIJI:
193 amdgpu_program_register_sequence(adev,
194 fiji_mgcg_cgcg_init,
195 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
196 amdgpu_program_register_sequence(adev,
197 golden_settings_fiji_a10,
198 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
199 break;
aaa36a97
AD		 200 case CHIP_TONGA:
201 amdgpu_program_register_sequence(adev,
202 tonga_mgcg_cgcg_init,
203 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
204 amdgpu_program_register_sequence(adev,
205 golden_settings_tonga_a11,
206 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
207 break;
2cc0c0b5 208 case CHIP_POLARIS11:
2cea03de 209 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 210 golden_settings_polaris11_a11,
211 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
2cea03de 212 break;
2cc0c0b5 213 case CHIP_POLARIS10:
2cea03de 214 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 215 golden_settings_polaris10_a11,
216 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
2cea03de 217 break;
aaa36a97
AD		 218 case CHIP_CARRIZO:
219 amdgpu_program_register_sequence(adev,
220 cz_mgcg_cgcg_init,
221 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
222 amdgpu_program_register_sequence(adev,
223 cz_golden_settings_a11,
224 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
225 break;
bb16e3b6
SL		 226 case CHIP_STONEY:
227 amdgpu_program_register_sequence(adev,
228 stoney_mgcg_cgcg_init,
229 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
230 amdgpu_program_register_sequence(adev,
231 stoney_golden_settings_a11,
232 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
233 break;
aaa36a97
AD		 234 default:
235 break;
236 }
237}
238
14d83e78
ML		 239static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
240{
241 int i;
242 for (i = 0; i < adev->sdma.num_instances; i++) {
243 release_firmware(adev->sdma.instance[i].fw);
244 adev->sdma.instance[i].fw = NULL;
245 }
246}
247
aaa36a97
AD		 248/**
249 * sdma_v3_0_init_microcode - load ucode images from disk
250 *
251 * @adev: amdgpu_device pointer
252 *
253 * Use the firmware interface to load the ucode images into
254 * the driver (not loaded into hw).
255 * Returns 0 on success, error on failure.
256 */
257static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
258{
259 const char *chip_name;
260 char fw_name[30];
c113ea1c 261 int err = 0, i;
aaa36a97
AD		 262 struct amdgpu_firmware_info *info = NULL;
263 const struct common_firmware_header *header = NULL;
595fd013 264 const struct sdma_firmware_header_v1_0 *hdr;
aaa36a97
AD		 265
266 DRM_DEBUG("\n");
267
268 switch (adev->asic_type) {
269 case CHIP_TONGA:
270 chip_name = "tonga";
271 break;
1a5bbb66
DZ		 272 case CHIP_FIJI:
273 chip_name = "fiji";
274 break;
2cc0c0b5
FC		 275 case CHIP_POLARIS11:
276 chip_name = "polaris11";
2cea03de 277 break;
2cc0c0b5
FC		 278 case CHIP_POLARIS10:
279 chip_name = "polaris10";
2cea03de 280 break;
aaa36a97
AD		 281 case CHIP_CARRIZO:
282 chip_name = "carrizo";
283 break;
bb16e3b6
SL		 284 case CHIP_STONEY:
285 chip_name = "stoney";
286 break;
aaa36a97
AD		 287 default: BUG();
288 }
289
c113ea1c 290 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97 291 if (i == 0)
c65444fe 292 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
aaa36a97 293 else
c65444fe 294 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
c113ea1c 295 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
aaa36a97
AD		 296 if (err)
297 goto out;
c113ea1c 298 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
aaa36a97
AD		 299 if (err)
300 goto out;
c113ea1c
AD		 301 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
302 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
303 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
304 if (adev->sdma.instance[i].feature_version >= 20)
305 adev->sdma.instance[i].burst_nop = true;
aaa36a97
AD		 306
307 if (adev->firmware.smu_load) {
308 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
309 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
c113ea1c 310 info->fw = adev->sdma.instance[i].fw;
aaa36a97
AD		 311 header = (const struct common_firmware_header *)info->fw->data;
312 adev->firmware.fw_size +=
313 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
314 }
315 }
316out:
317 if (err) {
318 printk(KERN_ERR
319 "sdma_v3_0: Failed to load firmware \"%s\"\n",
320 fw_name);
c113ea1c
AD		 321 for (i = 0; i < adev->sdma.num_instances; i++) {
322 release_firmware(adev->sdma.instance[i].fw);
323 adev->sdma.instance[i].fw = NULL;
aaa36a97
AD		 324 }
325 }
326 return err;
327}
328
329/**
330 * sdma_v3_0_ring_get_rptr - get the current read pointer
331 *
332 * @ring: amdgpu ring pointer
333 *
334 * Get the current rptr from the hardware (VI+).
335 */
336static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
337{
338 u32 rptr;
339
340 /* XXX check if swapping is necessary on BE */
341 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
342
343 return rptr;
344}
345
346/**
347 * sdma_v3_0_ring_get_wptr - get the current write pointer
348 *
349 * @ring: amdgpu ring pointer
350 *
351 * Get the current wptr from the hardware (VI+).
352 */
353static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
354{
355 struct amdgpu_device *adev = ring->adev;
356 u32 wptr;
357
358 if (ring->use_doorbell) {
359 /* XXX check if swapping is necessary on BE */
360 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
361 } else {
c113ea1c 362 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
aaa36a97
AD		 363
364 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
365 }
366
367 return wptr;
368}
369
370/**
371 * sdma_v3_0_ring_set_wptr - commit the write pointer
372 *
373 * @ring: amdgpu ring pointer
374 *
375 * Write the wptr back to the hardware (VI+).
376 */
377static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
378{
379 struct amdgpu_device *adev = ring->adev;
380
381 if (ring->use_doorbell) {
382 /* XXX check if swapping is necessary on BE */
383 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
384 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
385 } else {
c113ea1c 386 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
aaa36a97
AD		 387
388 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
389 }
390}
391
ac01db3d
JZ		 392static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
393{
c113ea1c 394 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ		 395 int i;
396
397 for (i = 0; i < count; i++)
398 if (sdma && sdma->burst_nop && (i == 0))
399 amdgpu_ring_write(ring, ring->nop |
400 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
401 else
402 amdgpu_ring_write(ring, ring->nop);
403}
404
aaa36a97
AD		 405/**
406 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
407 *
408 * @ring: amdgpu ring pointer
409 * @ib: IB object to schedule
410 *
411 * Schedule an IB in the DMA ring (VI).
412 */
413static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
d88bf583
CK		 414 struct amdgpu_ib *ib,
415 unsigned vm_id, bool ctx_switch)
aaa36a97 416{
d88bf583 417 u32 vmid = vm_id & 0xf;
aaa36a97
AD		 418 u32 next_rptr = ring->wptr + 5;
419
aaa36a97
AD		 420 while ((next_rptr & 7) != 2)
421 next_rptr++;
422 next_rptr += 6;
423
424 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
425 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
426 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
427 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
428 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
429 amdgpu_ring_write(ring, next_rptr);
430
aaa36a97 431 /* IB packet must end on a 8 DW boundary */
ac01db3d 432 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
aaa36a97
AD		 433
434 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
435 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
436 /* base must be 32 byte aligned */
437 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
438 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
439 amdgpu_ring_write(ring, ib->length_dw);
440 amdgpu_ring_write(ring, 0);
441 amdgpu_ring_write(ring, 0);
442
443}
444
445/**
d2edb07b 446 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
aaa36a97
AD		 447 *
448 * @ring: amdgpu ring pointer
449 *
450 * Emit an hdp flush packet on the requested DMA ring.
451 */
d2edb07b 452static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 453{
454 u32 ref_and_mask = 0;
455
c113ea1c 456 if (ring == &ring->adev->sdma.instance[0].ring)
aaa36a97
AD		 457 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
458 else
459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
460
461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
462 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
463 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
464 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
465 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
466 amdgpu_ring_write(ring, ref_and_mask); /* reference */
467 amdgpu_ring_write(ring, ref_and_mask); /* mask */
468 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
469 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
470}
471
cc958e67
CZ		 472static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
473{
474 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
475 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
476 amdgpu_ring_write(ring, mmHDP_DEBUG0);
477 amdgpu_ring_write(ring, 1);
478}
479
aaa36a97
AD		 480/**
481 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
482 *
483 * @ring: amdgpu ring pointer
484 * @fence: amdgpu fence object
485 *
486 * Add a DMA fence packet to the ring to write
487 * the fence seq number and DMA trap packet to generate
488 * an interrupt if needed (VI).
489 */
490static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
890ee23f 491 unsigned flags)
aaa36a97 492{
890ee23f 493 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
aaa36a97
AD		 494 /* write the fence */
495 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
496 amdgpu_ring_write(ring, lower_32_bits(addr));
497 amdgpu_ring_write(ring, upper_32_bits(addr));
498 amdgpu_ring_write(ring, lower_32_bits(seq));
499
500 /* optionally write high bits as well */
890ee23f 501 if (write64bit) {
aaa36a97
AD		 502 addr += 4;
503 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
504 amdgpu_ring_write(ring, lower_32_bits(addr));
505 amdgpu_ring_write(ring, upper_32_bits(addr));
506 amdgpu_ring_write(ring, upper_32_bits(seq));
507 }
508
509 /* generate an interrupt */
510 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
511 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
512}
513
03ccf481
ML		 514unsigned init_cond_exec(struct amdgpu_ring *ring)
515{
516 unsigned ret;
517 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
518 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
519 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
520 amdgpu_ring_write(ring, 1);
521 ret = ring->wptr;/* this is the offset we need patch later */
522 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
523 return ret;
524}
525
526void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
527{
528 unsigned cur;
529 BUG_ON(ring->ring[offset] != 0x55aa55aa);
530
531 cur = ring->wptr - 1;
532 if (likely(cur > offset))
533 ring->ring[offset] = cur - offset;
534 else
535 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
536}
537
538
aaa36a97
AD		 539/**
540 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
541 *
542 * @adev: amdgpu_device pointer
543 *
544 * Stop the gfx async dma ring buffers (VI).
545 */
546static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
547{
c113ea1c
AD		 548 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
549 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
aaa36a97
AD		 550 u32 rb_cntl, ib_cntl;
551 int i;
552
553 if ((adev->mman.buffer_funcs_ring == sdma0) ||
554 (adev->mman.buffer_funcs_ring == sdma1))
555 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
556
c113ea1c 557 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97
AD		 558 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
559 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
560 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
561 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
562 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
563 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
564 }
565 sdma0->ready = false;
566 sdma1->ready = false;
567}
568
569/**
570 * sdma_v3_0_rlc_stop - stop the compute async dma engines
571 *
572 * @adev: amdgpu_device pointer
573 *
574 * Stop the compute async dma queues (VI).
575 */
576static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
577{
578 /* XXX todo */
579}
580
cd06bf68
BG		 581/**
582 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
583 *
584 * @adev: amdgpu_device pointer
585 * @enable: enable/disable the DMA MEs context switch.
586 *
587 * Halt or unhalt the async dma engines context switch (VI).
588 */
589static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
590{
591 u32 f32_cntl;
592 int i;
593
c113ea1c 594 for (i = 0; i < adev->sdma.num_instances; i++) {
cd06bf68
BG		 595 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
596 if (enable)
597 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
598 AUTO_CTXSW_ENABLE, 1);
599 else
600 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
601 AUTO_CTXSW_ENABLE, 0);
602 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
603 }
604}
605
aaa36a97
AD		 606/**
607 * sdma_v3_0_enable - stop the async dma engines
608 *
609 * @adev: amdgpu_device pointer
610 * @enable: enable/disable the DMA MEs.
611 *
612 * Halt or unhalt the async dma engines (VI).
613 */
614static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
615{
616 u32 f32_cntl;
617 int i;
618
619 if (enable == false) {
620 sdma_v3_0_gfx_stop(adev);
621 sdma_v3_0_rlc_stop(adev);
622 }
623
c113ea1c 624 for (i = 0; i < adev->sdma.num_instances; i++) {
aaa36a97
AD		 625 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
626 if (enable)
627 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
628 else
629 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
630 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
631 }
632}
633
634/**
635 * sdma_v3_0_gfx_resume - setup and start the async dma engines
636 *
637 * @adev: amdgpu_device pointer
638 *
639 * Set up the gfx DMA ring buffers and enable them (VI).
640 * Returns 0 for success, error for failure.
641 */
642static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
643{
644 struct amdgpu_ring *ring;
645 u32 rb_cntl, ib_cntl;
646 u32 rb_bufsz;
647 u32 wb_offset;
648 u32 doorbell;
649 int i, j, r;
650
c113ea1c
AD		 651 for (i = 0; i < adev->sdma.num_instances; i++) {
652 ring = &adev->sdma.instance[i].ring;
aaa36a97
AD		 653 wb_offset = (ring->rptr_offs * 4);
654
655 mutex_lock(&adev->srbm_mutex);
656 for (j = 0; j < 16; j++) {
657 vi_srbm_select(adev, 0, 0, 0, j);
658 /* SDMA GFX */
659 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
660 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
661 }
662 vi_srbm_select(adev, 0, 0, 0, 0);
663 mutex_unlock(&adev->srbm_mutex);
664
c458fe94
AD		 665 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
666 adev->gfx.config.gb_addr_config & 0x70);
667
aaa36a97
AD		 668 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
669
670 /* Set ring buffer size in dwords */
671 rb_bufsz = order_base_2(ring->ring_size / 4);
672 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
673 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
674#ifdef __BIG_ENDIAN
675 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
676 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
677 RPTR_WRITEBACK_SWAP_ENABLE, 1);
678#endif
679 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
680
681 /* Initialize the ring buffer's read and write pointers */
682 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
683 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
d72f7c06
ML		 684 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
685 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
aaa36a97
AD		 686
687 /* set the wb address whether it's enabled or not */
688 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
689 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
690 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
691 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
692
693 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
694
695 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
696 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
697
698 ring->wptr = 0;
699 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
700
701 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
702
703 if (ring->use_doorbell) {
704 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
705 OFFSET, ring->doorbell_index);
706 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
707 } else {
708 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
709 }
710 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
711
712 /* enable DMA RB */
713 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
714 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
715
716 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
717 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
718#ifdef __BIG_ENDIAN
719 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
720#endif
721 /* enable DMA IBs */
722 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
723
724 ring->ready = true;
505dfe76 725 }
aaa36a97 726
505dfe76
ML		 727 /* unhalt the MEs */
728 sdma_v3_0_enable(adev, true);
729 /* enable sdma ring preemption */
730 sdma_v3_0_ctx_switch_enable(adev, true);
731
732 for (i = 0; i < adev->sdma.num_instances; i++) {
733 ring = &adev->sdma.instance[i].ring;
aaa36a97
AD		 734 r = amdgpu_ring_test_ring(ring);
735 if (r) {
736 ring->ready = false;
737 return r;
738 }
739
740 if (adev->mman.buffer_funcs_ring == ring)
741 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
742 }
743
744 return 0;
745}
746
747/**
748 * sdma_v3_0_rlc_resume - setup and start the async dma engines
749 *
750 * @adev: amdgpu_device pointer
751 *
752 * Set up the compute DMA queues and enable them (VI).
753 * Returns 0 for success, error for failure.
754 */
755static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
756{
757 /* XXX todo */
758 return 0;
759}
760
761/**
762 * sdma_v3_0_load_microcode - load the sDMA ME ucode
763 *
764 * @adev: amdgpu_device pointer
765 *
766 * Loads the sDMA0/1 ucode.
767 * Returns 0 for success, -EINVAL if the ucode is not available.
768 */
769static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
770{
771 const struct sdma_firmware_header_v1_0 *hdr;
772 const __le32 *fw_data;
773 u32 fw_size;
774 int i, j;
775
aaa36a97
AD		 776 /* halt the MEs */
777 sdma_v3_0_enable(adev, false);
778
c113ea1c
AD		 779 for (i = 0; i < adev->sdma.num_instances; i++) {
780 if (!adev->sdma.instance[i].fw)
781 return -EINVAL;
782 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
aaa36a97
AD		 783 amdgpu_ucode_print_sdma_hdr(&hdr->header);
784 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
aaa36a97 785 fw_data = (const __le32 *)
c113ea1c 786 (adev->sdma.instance[i].fw->data +
aaa36a97
AD		 787 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
788 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
789 for (j = 0; j < fw_size; j++)
790 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
c113ea1c 791 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
aaa36a97
AD		 792 }
793
794 return 0;
795}
796
797/**
798 * sdma_v3_0_start - setup and start the async dma engines
799 *
800 * @adev: amdgpu_device pointer
801 *
802 * Set up the DMA engines and enable them (VI).
803 * Returns 0 for success, error for failure.
804 */
805static int sdma_v3_0_start(struct amdgpu_device *adev)
806{
c113ea1c 807 int r, i;
aaa36a97 808
e61710c5 809 if (!adev->pp_enabled) {
ba5c2a87
RZ		 810 if (!adev->firmware.smu_load) {
811 r = sdma_v3_0_load_microcode(adev);
c113ea1c 812 if (r)
ba5c2a87
RZ		 813 return r;
814 } else {
815 for (i = 0; i < adev->sdma.num_instances; i++) {
816 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
817 (i == 0) ?
818 AMDGPU_UCODE_ID_SDMA0 :
819 AMDGPU_UCODE_ID_SDMA1);
820 if (r)
821 return -EINVAL;
822 }
c113ea1c 823 }
aaa36a97
AD		 824 }
825
505dfe76
ML		 826 /* disble sdma engine before programing it */
827 sdma_v3_0_ctx_switch_enable(adev, false);
828 sdma_v3_0_enable(adev, false);
aaa36a97
AD		 829
830 /* start the gfx rings and rlc compute queues */
831 r = sdma_v3_0_gfx_resume(adev);
832 if (r)
833 return r;
834 r = sdma_v3_0_rlc_resume(adev);
835 if (r)
836 return r;
837
838 return 0;
839}
840
841/**
842 * sdma_v3_0_ring_test_ring - simple async dma engine test
843 *
844 * @ring: amdgpu_ring structure holding ring information
845 *
846 * Test the DMA engine by writing using it to write an
847 * value to memory. (VI).
848 * Returns 0 for success, error for failure.
849 */
850static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
851{
852 struct amdgpu_device *adev = ring->adev;
853 unsigned i;
854 unsigned index;
855 int r;
856 u32 tmp;
857 u64 gpu_addr;
858
859 r = amdgpu_wb_get(adev, &index);
860 if (r) {
861 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
862 return r;
863 }
864
865 gpu_addr = adev->wb.gpu_addr + (index * 4);
866 tmp = 0xCAFEDEAD;
867 adev->wb.wb[index] = cpu_to_le32(tmp);
868
a27de35c 869 r = amdgpu_ring_alloc(ring, 5);
aaa36a97
AD		 870 if (r) {
871 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
872 amdgpu_wb_free(adev, index);
873 return r;
874 }
875
876 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
877 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
878 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
879 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
880 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
881 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 882 amdgpu_ring_commit(ring);
aaa36a97
AD		 883
884 for (i = 0; i < adev->usec_timeout; i++) {
885 tmp = le32_to_cpu(adev->wb.wb[index]);
886 if (tmp == 0xDEADBEEF)
887 break;
888 DRM_UDELAY(1);
889 }
890
891 if (i < adev->usec_timeout) {
892 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
893 } else {
894 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
895 ring->idx, tmp);
896 r = -EINVAL;
897 }
898 amdgpu_wb_free(adev, index);
899
900 return r;
901}
902
903/**
904 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
905 *
906 * @ring: amdgpu_ring structure holding ring information
907 *
908 * Test a simple IB in the DMA ring (VI).
909 * Returns 0 on success, error on failure.
910 */
911static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
912{
913 struct amdgpu_device *adev = ring->adev;
914 struct amdgpu_ib ib;
1763552e 915 struct fence *f = NULL;
aaa36a97
AD		 916 unsigned i;
917 unsigned index;
918 int r;
919 u32 tmp = 0;
920 u64 gpu_addr;
921
922 r = amdgpu_wb_get(adev, &index);
923 if (r) {
924 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
925 return r;
926 }
927
928 gpu_addr = adev->wb.gpu_addr + (index * 4);
929 tmp = 0xCAFEDEAD;
930 adev->wb.wb[index] = cpu_to_le32(tmp);
b203dd95 931 memset(&ib, 0, sizeof(ib));
b07c60c0 932 r = amdgpu_ib_get(adev, NULL, 256, &ib);
aaa36a97 933 if (r) {
aaa36a97 934 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
0011fdaa 935 goto err0;
aaa36a97
AD		 936 }
937
938 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
939 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
940 ib.ptr[1] = lower_32_bits(gpu_addr);
941 ib.ptr[2] = upper_32_bits(gpu_addr);
942 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
943 ib.ptr[4] = 0xDEADBEEF;
944 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
945 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
946 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
947 ib.length_dw = 8;
948
c5637837 949 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
0011fdaa
CZ		 950 if (r)
951 goto err1;
952
1763552e 953 r = fence_wait(f, false);
aaa36a97 954 if (r) {
aaa36a97 955 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
0011fdaa 956 goto err1;
aaa36a97
AD		 957 }
958 for (i = 0; i < adev->usec_timeout; i++) {
959 tmp = le32_to_cpu(adev->wb.wb[index]);
960 if (tmp == 0xDEADBEEF)
961 break;
962 DRM_UDELAY(1);
963 }
964 if (i < adev->usec_timeout) {
965 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
0011fdaa
CZ		 966 ring->idx, i);
967 goto err1;
aaa36a97
AD		 968 } else {
969 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
970 r = -EINVAL;
971 }
0011fdaa 972err1:
281b4223 973 fence_put(f);
cc55c45d 974 amdgpu_ib_free(adev, &ib, NULL);
73cfa5f5 975 fence_put(f);
0011fdaa 976err0:
aaa36a97
AD		 977 amdgpu_wb_free(adev, index);
978 return r;
979}
980
981/**
982 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
983 *
984 * @ib: indirect buffer to fill with commands
985 * @pe: addr of the page entry
986 * @src: src addr to copy from
987 * @count: number of page entries to update
988 *
989 * Update PTEs by copying them from the GART using sDMA (CIK).
990 */
991static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
992 uint64_t pe, uint64_t src,
993 unsigned count)
994{
995 while (count) {
996 unsigned bytes = count * 8;
997 if (bytes > 0x1FFFF8)
998 bytes = 0x1FFFF8;
999
1000 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1001 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1002 ib->ptr[ib->length_dw++] = bytes;
1003 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1004 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1005 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1006 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1007 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1008
1009 pe += bytes;
1010 src += bytes;
1011 count -= bytes / 8;
1012 }
1013}
1014
1015/**
1016 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1017 *
1018 * @ib: indirect buffer to fill with commands
1019 * @pe: addr of the page entry
1020 * @addr: dst addr to write into pe
1021 * @count: number of page entries to update
1022 * @incr: increase next addr by incr bytes
1023 * @flags: access flags
1024 *
1025 * Update PTEs by writing them manually using sDMA (CIK).
1026 */
1027static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
b07c9d2a 1028 const dma_addr_t *pages_addr, uint64_t pe,
aaa36a97
AD		 1029 uint64_t addr, unsigned count,
1030 uint32_t incr, uint32_t flags)
1031{
1032 uint64_t value;
1033 unsigned ndw;
1034
1035 while (count) {
1036 ndw = count * 2;
1037 if (ndw > 0xFFFFE)
1038 ndw = 0xFFFFE;
1039
1040 /* for non-physically contiguous pages (system) */
1041 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1042 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1043 ib->ptr[ib->length_dw++] = pe;
1044 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1045 ib->ptr[ib->length_dw++] = ndw;
1046 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
b07c9d2a 1047 value = amdgpu_vm_map_gart(pages_addr, addr);
aaa36a97
AD		 1048 addr += incr;
1049 value |= flags;
1050 ib->ptr[ib->length_dw++] = value;
1051 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1052 }
1053 }
1054}
1055
1056/**
1057 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1058 *
1059 * @ib: indirect buffer to fill with commands
1060 * @pe: addr of the page entry
1061 * @addr: dst addr to write into pe
1062 * @count: number of page entries to update
1063 * @incr: increase next addr by incr bytes
1064 * @flags: access flags
1065 *
1066 * Update the page tables using sDMA (CIK).
1067 */
1068static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1069 uint64_t pe,
1070 uint64_t addr, unsigned count,
1071 uint32_t incr, uint32_t flags)
1072{
1073 uint64_t value;
1074 unsigned ndw;
1075
1076 while (count) {
1077 ndw = count;
1078 if (ndw > 0x7FFFF)
1079 ndw = 0x7FFFF;
1080
1081 if (flags & AMDGPU_PTE_VALID)
1082 value = addr;
1083 else
1084 value = 0;
1085
1086 /* for physically contiguous pages (vram) */
1087 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1088 ib->ptr[ib->length_dw++] = pe; /* dst addr */
1089 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1090 ib->ptr[ib->length_dw++] = flags; /* mask */
1091 ib->ptr[ib->length_dw++] = 0;
1092 ib->ptr[ib->length_dw++] = value; /* value */
1093 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1094 ib->ptr[ib->length_dw++] = incr; /* increment size */
1095 ib->ptr[ib->length_dw++] = 0;
1096 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1097
1098 pe += ndw * 8;
1099 addr += ndw * incr;
1100 count -= ndw;
1101 }
1102}
1103
1104/**
9e5d5309 1105 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
aaa36a97
AD		 1106 *
1107 * @ib: indirect buffer to fill with padding
1108 *
1109 */
9e5d5309 1110static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
aaa36a97 1111{
9e5d5309 1112 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
ac01db3d
JZ		 1113 u32 pad_count;
1114 int i;
1115
1116 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1117 for (i = 0; i < pad_count; i++)
1118 if (sdma && sdma->burst_nop && (i == 0))
1119 ib->ptr[ib->length_dw++] =
1120 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1121 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1122 else
1123 ib->ptr[ib->length_dw++] =
1124 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
aaa36a97
AD		 1125}
1126
1127/**
00b7c4ff 1128 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
aaa36a97
AD		 1129 *
1130 * @ring: amdgpu_ring pointer
aaa36a97 1131 *
00b7c4ff 1132 * Make sure all previous operations are completed (CIK).
aaa36a97 1133 */
00b7c4ff 1134static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
aaa36a97 1135{
5c55db83
CZ		 1136 uint32_t seq = ring->fence_drv.sync_seq;
1137 uint64_t addr = ring->fence_drv.gpu_addr;
1138
1139 /* wait for idle */
1140 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1141 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1142 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1143 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1144 amdgpu_ring_write(ring, addr & 0xfffffffc);
1145 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1146 amdgpu_ring_write(ring, seq); /* reference */
1147 amdgpu_ring_write(ring, 0xfffffff); /* mask */
1148 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1149 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
00b7c4ff 1150}
5c55db83 1151
00b7c4ff
CK		 1152/**
1153 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1154 *
1155 * @ring: amdgpu_ring pointer
1156 * @vm: amdgpu_vm pointer
1157 *
1158 * Update the page table base and flush the VM TLB
1159 * using sDMA (VI).
1160 */
1161static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1162 unsigned vm_id, uint64_t pd_addr)
1163{
aaa36a97
AD		 1164 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1165 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1166 if (vm_id < 8) {
1167 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1168 } else {
1169 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1170 }
1171 amdgpu_ring_write(ring, pd_addr >> 12);
1172
aaa36a97
AD		 1173 /* flush TLB */
1174 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1175 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1176 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1177 amdgpu_ring_write(ring, 1 << vm_id);
1178
1179 /* wait for flush */
1180 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1181 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1182 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1183 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1184 amdgpu_ring_write(ring, 0);
1185 amdgpu_ring_write(ring, 0); /* reference */
1186 amdgpu_ring_write(ring, 0); /* mask */
1187 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1188 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1189}
1190
5fc3aeeb 1191static int sdma_v3_0_early_init(void *handle)
aaa36a97 1192{
5fc3aeeb 1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194
c113ea1c 1195 switch (adev->asic_type) {
bb16e3b6
SL		 1196 case CHIP_STONEY:
1197 adev->sdma.num_instances = 1;
1198 break;
c113ea1c
AD		 1199 default:
1200 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1201 break;
1202 }
1203
aaa36a97
AD		 1204 sdma_v3_0_set_ring_funcs(adev);
1205 sdma_v3_0_set_buffer_funcs(adev);
1206 sdma_v3_0_set_vm_pte_funcs(adev);
1207 sdma_v3_0_set_irq_funcs(adev);
1208
1209 return 0;
1210}
1211
5fc3aeeb 1212static int sdma_v3_0_sw_init(void *handle)
aaa36a97
AD		 1213{
1214 struct amdgpu_ring *ring;
c113ea1c 1215 int r, i;
5fc3aeeb 1216 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1217
1218 /* SDMA trap event */
c113ea1c 1219 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
aaa36a97
AD		 1220 if (r)
1221 return r;
1222
1223 /* SDMA Privileged inst */
c113ea1c 1224 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
aaa36a97
AD		 1225 if (r)
1226 return r;
1227
1228 /* SDMA Privileged inst */
c113ea1c 1229 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
aaa36a97
AD		 1230 if (r)
1231 return r;
1232
1233 r = sdma_v3_0_init_microcode(adev);
1234 if (r) {
1235 DRM_ERROR("Failed to load sdma firmware!\n");
1236 return r;
1237 }
1238
c113ea1c
AD		 1239 for (i = 0; i < adev->sdma.num_instances; i++) {
1240 ring = &adev->sdma.instance[i].ring;
1241 ring->ring_obj = NULL;
1242 ring->use_doorbell = true;
1243 ring->doorbell_index = (i == 0) ?
1244 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1245
1246 sprintf(ring->name, "sdma%d", i);
b38d99c4 1247 r = amdgpu_ring_init(adev, ring, 1024,
c113ea1c
AD		 1248 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1249 &adev->sdma.trap_irq,
1250 (i == 0) ?
1251 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1252 AMDGPU_RING_TYPE_SDMA);
1253 if (r)
1254 return r;
1255 }
aaa36a97
AD		 1256
1257 return r;
1258}
1259
5fc3aeeb 1260static int sdma_v3_0_sw_fini(void *handle)
aaa36a97 1261{
5fc3aeeb 1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
c113ea1c 1263 int i;
5fc3aeeb 1264
c113ea1c
AD		 1265 for (i = 0; i < adev->sdma.num_instances; i++)
1266 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
aaa36a97 1267
14d83e78 1268 sdma_v3_0_free_microcode(adev);
aaa36a97
AD		 1269 return 0;
1270}
1271
5fc3aeeb 1272static int sdma_v3_0_hw_init(void *handle)
aaa36a97
AD		 1273{
1274 int r;
5fc3aeeb 1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1276
1277 sdma_v3_0_init_golden_registers(adev);
1278
1279 r = sdma_v3_0_start(adev);
1280 if (r)
1281 return r;
1282
1283 return r;
1284}
1285
5fc3aeeb 1286static int sdma_v3_0_hw_fini(void *handle)
aaa36a97 1287{
5fc3aeeb 1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289
cd06bf68 1290 sdma_v3_0_ctx_switch_enable(adev, false);
aaa36a97
AD		 1291 sdma_v3_0_enable(adev, false);
1292
1293 return 0;
1294}
1295
5fc3aeeb 1296static int sdma_v3_0_suspend(void *handle)
aaa36a97 1297{
5fc3aeeb 1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1299
1300 return sdma_v3_0_hw_fini(adev);
1301}
1302
5fc3aeeb 1303static int sdma_v3_0_resume(void *handle)
aaa36a97 1304{
5fc3aeeb 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1306
1307 return sdma_v3_0_hw_init(adev);
1308}
1309
5fc3aeeb 1310static bool sdma_v3_0_is_idle(void *handle)
aaa36a97 1311{
5fc3aeeb 1312 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1313 u32 tmp = RREG32(mmSRBM_STATUS2);
1314
1315 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1316 SRBM_STATUS2__SDMA1_BUSY_MASK))
1317 return false;
1318
1319 return true;
1320}
1321
5fc3aeeb 1322static int sdma_v3_0_wait_for_idle(void *handle)
aaa36a97
AD		 1323{
1324 unsigned i;
1325 u32 tmp;
5fc3aeeb 1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1327
1328 for (i = 0; i < adev->usec_timeout; i++) {
1329 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1330 SRBM_STATUS2__SDMA1_BUSY_MASK);
1331
1332 if (!tmp)
1333 return 0;
1334 udelay(1);
1335 }
1336 return -ETIMEDOUT;
1337}
1338
5fc3aeeb 1339static int sdma_v3_0_soft_reset(void *handle)
aaa36a97
AD		 1340{
1341 u32 srbm_soft_reset = 0;
5fc3aeeb 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1343 u32 tmp = RREG32(mmSRBM_STATUS2);
1344
1345 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1346 /* sdma0 */
1347 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1348 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1349 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1350 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1351 }
1352 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1353 /* sdma1 */
1354 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1355 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1356 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1357 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1358 }
1359
1360 if (srbm_soft_reset) {
aaa36a97
AD		 1361 tmp = RREG32(mmSRBM_SOFT_RESET);
1362 tmp |= srbm_soft_reset;
1363 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1364 WREG32(mmSRBM_SOFT_RESET, tmp);
1365 tmp = RREG32(mmSRBM_SOFT_RESET);
1366
1367 udelay(50);
1368
1369 tmp &= ~srbm_soft_reset;
1370 WREG32(mmSRBM_SOFT_RESET, tmp);
1371 tmp = RREG32(mmSRBM_SOFT_RESET);
1372
1373 /* Wait a little for things to settle down */
1374 udelay(50);
aaa36a97
AD		 1375 }
1376
1377 return 0;
1378}
1379
1380static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1381 struct amdgpu_irq_src *source,
1382 unsigned type,
1383 enum amdgpu_interrupt_state state)
1384{
1385 u32 sdma_cntl;
1386
1387 switch (type) {
1388 case AMDGPU_SDMA_IRQ_TRAP0:
1389 switch (state) {
1390 case AMDGPU_IRQ_STATE_DISABLE:
1391 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1392 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1393 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1394 break;
1395 case AMDGPU_IRQ_STATE_ENABLE:
1396 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1397 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1398 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1399 break;
1400 default:
1401 break;
1402 }
1403 break;
1404 case AMDGPU_SDMA_IRQ_TRAP1:
1405 switch (state) {
1406 case AMDGPU_IRQ_STATE_DISABLE:
1407 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1408 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1409 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1410 break;
1411 case AMDGPU_IRQ_STATE_ENABLE:
1412 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1413 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1414 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1415 break;
1416 default:
1417 break;
1418 }
1419 break;
1420 default:
1421 break;
1422 }
1423 return 0;
1424}
1425
1426static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1427 struct amdgpu_irq_src *source,
1428 struct amdgpu_iv_entry *entry)
1429{
1430 u8 instance_id, queue_id;
1431
1432 instance_id = (entry->ring_id & 0x3) >> 0;
1433 queue_id = (entry->ring_id & 0xc) >> 2;
1434 DRM_DEBUG("IH: SDMA trap\n");
1435 switch (instance_id) {
1436 case 0:
1437 switch (queue_id) {
1438 case 0:
c113ea1c 1439 amdgpu_fence_process(&adev->sdma.instance[0].ring);
aaa36a97
AD		 1440 break;
1441 case 1:
1442 /* XXX compute */
1443 break;
1444 case 2:
1445 /* XXX compute */
1446 break;
1447 }
1448 break;
1449 case 1:
1450 switch (queue_id) {
1451 case 0:
c113ea1c 1452 amdgpu_fence_process(&adev->sdma.instance[1].ring);
aaa36a97
AD		 1453 break;
1454 case 1:
1455 /* XXX compute */
1456 break;
1457 case 2:
1458 /* XXX compute */
1459 break;
1460 }
1461 break;
1462 }
1463 return 0;
1464}
1465
1466static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1467 struct amdgpu_irq_src *source,
1468 struct amdgpu_iv_entry *entry)
1469{
1470 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1471 schedule_work(&adev->reset_work);
1472 return 0;
1473}
1474
ce22362b 1475static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
3c997d24
EH		 1476 struct amdgpu_device *adev,
1477 bool enable)
1478{
1479 uint32_t temp, data;
ce22362b 1480 int i;
3c997d24 1481
e08d53cb 1482 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
ce22362b
AD		 1483 for (i = 0; i < adev->sdma.num_instances; i++) {
1484 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1485 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1486 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1488 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1489 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1490 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1491 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1492 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1493 if (data != temp)
1494 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1495 }
3c997d24 1496 } else {
ce22362b
AD		 1497 for (i = 0; i < adev->sdma.num_instances; i++) {
1498 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1499 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
3c997d24
EH		 1500 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1501 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1502 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1503 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1504 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1505 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1506 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1507
ce22362b
AD		 1508 if (data != temp)
1509 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1510 }
3c997d24
EH		 1511 }
1512}
1513
ce22362b 1514static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
3c997d24
EH		 1515 struct amdgpu_device *adev,
1516 bool enable)
1517{
1518 uint32_t temp, data;
ce22362b 1519 int i;
3c997d24 1520
e08d53cb 1521 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
ce22362b
AD		 1522 for (i = 0; i < adev->sdma.num_instances; i++) {
1523 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1524 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
3c997d24 1525
ce22362b
AD		 1526 if (temp != data)
1527 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1528 }
3c997d24 1529 } else {
ce22362b
AD		 1530 for (i = 0; i < adev->sdma.num_instances; i++) {
1531 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1532 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
3c997d24 1533
ce22362b
AD		 1534 if (temp != data)
1535 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1536 }
3c997d24
EH		 1537 }
1538}
1539
5fc3aeeb 1540static int sdma_v3_0_set_clockgating_state(void *handle,
1541 enum amd_clockgating_state state)
aaa36a97 1542{
3c997d24
EH		 1543 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1544
1545 switch (adev->asic_type) {
1546 case CHIP_FIJI:
ce22362b
AD		 1547 case CHIP_CARRIZO:
1548 case CHIP_STONEY:
1549 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
3c997d24 1550 state == AMD_CG_STATE_GATE ? true : false);
ce22362b 1551 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
3c997d24
EH		 1552 state == AMD_CG_STATE_GATE ? true : false);
1553 break;
1554 default:
1555 break;
1556 }
aaa36a97
AD		 1557 return 0;
1558}
1559
5fc3aeeb 1560static int sdma_v3_0_set_powergating_state(void *handle,
1561 enum amd_powergating_state state)
aaa36a97
AD		 1562{
1563 return 0;
1564}
1565
5fc3aeeb 1566const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
88a907d6 1567 .name = "sdma_v3_0",
aaa36a97
AD		 1568 .early_init = sdma_v3_0_early_init,
1569 .late_init = NULL,
1570 .sw_init = sdma_v3_0_sw_init,
1571 .sw_fini = sdma_v3_0_sw_fini,
1572 .hw_init = sdma_v3_0_hw_init,
1573 .hw_fini = sdma_v3_0_hw_fini,
1574 .suspend = sdma_v3_0_suspend,
1575 .resume = sdma_v3_0_resume,
1576 .is_idle = sdma_v3_0_is_idle,
1577 .wait_for_idle = sdma_v3_0_wait_for_idle,
1578 .soft_reset = sdma_v3_0_soft_reset,
aaa36a97
AD		 1579 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1580 .set_powergating_state = sdma_v3_0_set_powergating_state,
1581};
1582
aaa36a97
AD		 1583static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1584 .get_rptr = sdma_v3_0_ring_get_rptr,
1585 .get_wptr = sdma_v3_0_ring_get_wptr,
1586 .set_wptr = sdma_v3_0_ring_set_wptr,
1587 .parse_cs = NULL,
1588 .emit_ib = sdma_v3_0_ring_emit_ib,
1589 .emit_fence = sdma_v3_0_ring_emit_fence,
00b7c4ff 1590 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
aaa36a97 1591 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
d2edb07b 1592 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
cc958e67 1593 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
aaa36a97
AD		 1594 .test_ring = sdma_v3_0_ring_test_ring,
1595 .test_ib = sdma_v3_0_ring_test_ib,
ac01db3d 1596 .insert_nop = sdma_v3_0_ring_insert_nop,
9e5d5309 1597 .pad_ib = sdma_v3_0_ring_pad_ib,
aaa36a97
AD		 1598};
1599
1600static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1601{
c113ea1c
AD		 1602 int i;
1603
1604 for (i = 0; i < adev->sdma.num_instances; i++)
1605 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
aaa36a97
AD		 1606}
1607
1608static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1609 .set = sdma_v3_0_set_trap_irq_state,
1610 .process = sdma_v3_0_process_trap_irq,
1611};
1612
1613static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1614 .process = sdma_v3_0_process_illegal_inst_irq,
1615};
1616
1617static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1618{
c113ea1c
AD		 1619 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1620 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1621 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
aaa36a97
AD		 1622}
1623
1624/**
1625 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1626 *
1627 * @ring: amdgpu_ring structure holding ring information
1628 * @src_offset: src GPU address
1629 * @dst_offset: dst GPU address
1630 * @byte_count: number of bytes to xfer
1631 *
1632 * Copy GPU buffers using the DMA engine (VI).
1633 * Used by the amdgpu ttm implementation to move pages if
1634 * registered as the asic copy callback.
1635 */
c7ae72c0 1636static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
aaa36a97
AD		 1637 uint64_t src_offset,
1638 uint64_t dst_offset,
1639 uint32_t byte_count)
1640{
c7ae72c0
CZ		 1641 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1642 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1643 ib->ptr[ib->length_dw++] = byte_count;
1644 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1645 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1646 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1647 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1648 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
aaa36a97
AD		 1649}
1650
1651/**
1652 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1653 *
1654 * @ring: amdgpu_ring structure holding ring information
1655 * @src_data: value to write to buffer
1656 * @dst_offset: dst GPU address
1657 * @byte_count: number of bytes to xfer
1658 *
1659 * Fill GPU buffers using the DMA engine (VI).
1660 */
6e7a3840 1661static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
aaa36a97
AD		 1662 uint32_t src_data,
1663 uint64_t dst_offset,
1664 uint32_t byte_count)
1665{
6e7a3840
CZ		 1666 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1667 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1668 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1669 ib->ptr[ib->length_dw++] = src_data;
1670 ib->ptr[ib->length_dw++] = byte_count;
aaa36a97
AD		 1671}
1672
1673static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1674 .copy_max_bytes = 0x1fffff,
1675 .copy_num_dw = 7,
1676 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1677
1678 .fill_max_bytes = 0x1fffff,
1679 .fill_num_dw = 5,
1680 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1681};
1682
1683static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1684{
1685 if (adev->mman.buffer_funcs == NULL) {
1686 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
c113ea1c 1687 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
aaa36a97
AD		 1688 }
1689}
1690
1691static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1692 .copy_pte = sdma_v3_0_vm_copy_pte,
1693 .write_pte = sdma_v3_0_vm_write_pte,
1694 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
aaa36a97
AD		 1695};
1696
1697static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1698{
2d55e45a
CK		 1699 unsigned i;
1700
aaa36a97
AD		 1701 if (adev->vm_manager.vm_pte_funcs == NULL) {
1702 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
2d55e45a
CK		 1703 for (i = 0; i < adev->sdma.num_instances; i++)
1704 adev->vm_manager.vm_pte_rings[i] =
1705 &adev->sdma.instance[i].ring;
1706
1707 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
aaa36a97
AD		 1708 }
1709}
Linux 6.x block layer and io_uring tree(s)