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654f761c FX |
1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include <linux/firmware.h> | |
24 | #include "amdgpu.h" | |
25 | #include "amdgpu_psp.h" | |
26 | #include "amdgpu_ucode.h" | |
27 | #include "soc15_common.h" | |
28 | #include "psp_v11_0.h" | |
29 | ||
30 | #include "mp/mp_11_0_offset.h" | |
31 | #include "mp/mp_11_0_sh_mask.h" | |
32 | #include "gc/gc_9_0_offset.h" | |
33 | #include "sdma0/sdma0_4_0_offset.h" | |
34 | #include "nbio/nbio_7_4_offset.h" | |
35 | ||
36 | MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); | |
51e7177f | 37 | MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); |
654f761c FX |
38 | |
39 | /* address block */ | |
40 | #define smnMP1_FIRMWARE_FLAGS 0x3010024 | |
41 | ||
42 | static int | |
43 | psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) | |
44 | { | |
45 | switch (ucode->ucode_id) { | |
46 | case AMDGPU_UCODE_ID_SDMA0: | |
47 | *type = GFX_FW_TYPE_SDMA0; | |
48 | break; | |
49 | case AMDGPU_UCODE_ID_SDMA1: | |
50 | *type = GFX_FW_TYPE_SDMA1; | |
51 | break; | |
52 | case AMDGPU_UCODE_ID_CP_CE: | |
53 | *type = GFX_FW_TYPE_CP_CE; | |
54 | break; | |
55 | case AMDGPU_UCODE_ID_CP_PFP: | |
56 | *type = GFX_FW_TYPE_CP_PFP; | |
57 | break; | |
58 | case AMDGPU_UCODE_ID_CP_ME: | |
59 | *type = GFX_FW_TYPE_CP_ME; | |
60 | break; | |
61 | case AMDGPU_UCODE_ID_CP_MEC1: | |
62 | *type = GFX_FW_TYPE_CP_MEC; | |
63 | break; | |
64 | case AMDGPU_UCODE_ID_CP_MEC1_JT: | |
65 | *type = GFX_FW_TYPE_CP_MEC_ME1; | |
66 | break; | |
67 | case AMDGPU_UCODE_ID_CP_MEC2: | |
68 | *type = GFX_FW_TYPE_CP_MEC; | |
69 | break; | |
70 | case AMDGPU_UCODE_ID_CP_MEC2_JT: | |
71 | *type = GFX_FW_TYPE_CP_MEC_ME2; | |
72 | break; | |
73 | case AMDGPU_UCODE_ID_RLC_G: | |
74 | *type = GFX_FW_TYPE_RLC_G; | |
75 | break; | |
76 | case AMDGPU_UCODE_ID_SMC: | |
77 | *type = GFX_FW_TYPE_SMU; | |
78 | break; | |
79 | case AMDGPU_UCODE_ID_UVD: | |
80 | *type = GFX_FW_TYPE_UVD; | |
81 | break; | |
82 | case AMDGPU_UCODE_ID_VCE: | |
83 | *type = GFX_FW_TYPE_VCE; | |
84 | break; | |
d4e83843 EQ |
85 | case AMDGPU_UCODE_ID_UVD1: |
86 | *type = GFX_FW_TYPE_UVD1; | |
87 | break; | |
654f761c FX |
88 | case AMDGPU_UCODE_ID_MAXIMUM: |
89 | default: | |
90 | return -EINVAL; | |
91 | } | |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
96 | static int psp_v11_0_init_microcode(struct psp_context *psp) | |
97 | { | |
98 | struct amdgpu_device *adev = psp->adev; | |
99 | const char *chip_name; | |
100 | char fw_name[30]; | |
101 | int err = 0; | |
51e7177f HZ |
102 | const struct psp_firmware_header_v1_0 *sos_hdr; |
103 | const struct ta_firmware_header_v1_0 *ta_hdr; | |
654f761c FX |
104 | |
105 | DRM_DEBUG("\n"); | |
106 | ||
107 | switch (adev->asic_type) { | |
108 | case CHIP_VEGA20: | |
109 | chip_name = "vega20"; | |
110 | break; | |
111 | default: | |
112 | BUG(); | |
113 | } | |
114 | ||
115 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); | |
116 | err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); | |
117 | if (err) | |
118 | goto out; | |
119 | ||
120 | err = amdgpu_ucode_validate(adev->psp.sos_fw); | |
121 | if (err) | |
122 | goto out; | |
123 | ||
51e7177f HZ |
124 | sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; |
125 | adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); | |
126 | adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); | |
127 | adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); | |
128 | adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) - | |
129 | le32_to_cpu(sos_hdr->sos_size_bytes); | |
130 | adev->psp.sys_start_addr = (uint8_t *)sos_hdr + | |
131 | le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); | |
654f761c | 132 | adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + |
51e7177f HZ |
133 | le32_to_cpu(sos_hdr->sos_offset_bytes); |
134 | ||
135 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); | |
136 | err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); | |
137 | if (err) | |
138 | goto out; | |
139 | ||
140 | err = amdgpu_ucode_validate(adev->psp.ta_fw); | |
141 | if (err) | |
142 | goto out; | |
143 | ||
144 | ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; | |
145 | adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); | |
146 | adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); | |
147 | adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + | |
148 | le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); | |
149 | ||
654f761c FX |
150 | return 0; |
151 | out: | |
152 | if (err) { | |
153 | dev_err(adev->dev, | |
154 | "psp v11.0: Failed to load firmware \"%s\"\n", | |
155 | fw_name); | |
156 | release_firmware(adev->psp.sos_fw); | |
157 | adev->psp.sos_fw = NULL; | |
158 | } | |
159 | ||
160 | return err; | |
161 | } | |
162 | ||
163 | static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) | |
164 | { | |
165 | int ret; | |
166 | uint32_t psp_gfxdrv_command_reg = 0; | |
167 | struct amdgpu_device *adev = psp->adev; | |
168 | uint32_t sol_reg; | |
169 | ||
170 | /* Check sOS sign of life register to confirm sys driver and sOS | |
171 | * are already been loaded. | |
172 | */ | |
173 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
d63cda5b XY |
174 | if (sol_reg) { |
175 | psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); | |
654f761c | 176 | return 0; |
d63cda5b | 177 | } |
654f761c FX |
178 | |
179 | /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ | |
180 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
181 | 0x80000000, 0x80000000, false); | |
182 | if (ret) | |
183 | return ret; | |
184 | ||
185 | memset(psp->fw_pri_buf, 0, PSP_1_MEG); | |
186 | ||
187 | /* Copy PSP System Driver binary to memory */ | |
188 | memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); | |
189 | ||
548f2ecc | 190 | /* Provide the sys driver to bootloader */ |
654f761c FX |
191 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, |
192 | (uint32_t)(psp->fw_pri_mc_addr >> 20)); | |
193 | psp_gfxdrv_command_reg = 1 << 16; | |
194 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, | |
195 | psp_gfxdrv_command_reg); | |
196 | ||
197 | /* there might be handshake issue with hardware which needs delay */ | |
198 | mdelay(20); | |
199 | ||
200 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
201 | 0x80000000, 0x80000000, false); | |
202 | ||
203 | return ret; | |
204 | } | |
205 | ||
206 | static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) | |
207 | { | |
208 | int ret; | |
209 | unsigned int psp_gfxdrv_command_reg = 0; | |
210 | struct amdgpu_device *adev = psp->adev; | |
211 | uint32_t sol_reg; | |
212 | ||
213 | /* Check sOS sign of life register to confirm sys driver and sOS | |
214 | * are already been loaded. | |
215 | */ | |
216 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
217 | if (sol_reg) | |
218 | return 0; | |
219 | ||
220 | /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ | |
221 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
222 | 0x80000000, 0x80000000, false); | |
223 | if (ret) | |
224 | return ret; | |
225 | ||
226 | memset(psp->fw_pri_buf, 0, PSP_1_MEG); | |
227 | ||
228 | /* Copy Secure OS binary to PSP memory */ | |
229 | memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); | |
230 | ||
548f2ecc | 231 | /* Provide the PSP secure OS to bootloader */ |
654f761c FX |
232 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, |
233 | (uint32_t)(psp->fw_pri_mc_addr >> 20)); | |
234 | psp_gfxdrv_command_reg = 2 << 16; | |
235 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, | |
236 | psp_gfxdrv_command_reg); | |
237 | ||
238 | /* there might be handshake issue with hardware which needs delay */ | |
239 | mdelay(20); | |
240 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), | |
241 | RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), | |
242 | 0, true); | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, | |
248 | struct psp_gfx_cmd_resp *cmd) | |
249 | { | |
250 | int ret; | |
251 | uint64_t fw_mem_mc_addr = ucode->mc_addr; | |
252 | ||
253 | memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); | |
254 | ||
255 | cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; | |
256 | cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); | |
257 | cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); | |
258 | cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; | |
259 | ||
260 | ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); | |
261 | if (ret) | |
262 | DRM_ERROR("Unknown firmware type\n"); | |
263 | ||
264 | return ret; | |
265 | } | |
266 | ||
267 | static int psp_v11_0_ring_init(struct psp_context *psp, | |
268 | enum psp_ring_type ring_type) | |
269 | { | |
270 | int ret = 0; | |
271 | struct psp_ring *ring; | |
272 | struct amdgpu_device *adev = psp->adev; | |
273 | ||
274 | ring = &psp->km_ring; | |
275 | ||
276 | ring->ring_type = ring_type; | |
277 | ||
278 | /* allocate 4k Page of Local Frame Buffer memory for ring */ | |
279 | ring->ring_size = 0x1000; | |
280 | ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, | |
281 | AMDGPU_GEM_DOMAIN_VRAM, | |
282 | &adev->firmware.rbuf, | |
283 | &ring->ring_mem_mc_addr, | |
284 | (void **)&ring->ring_mem); | |
285 | if (ret) { | |
286 | ring->ring_size = 0; | |
287 | return ret; | |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
293 | static int psp_v11_0_ring_create(struct psp_context *psp, | |
294 | enum psp_ring_type ring_type) | |
295 | { | |
296 | int ret = 0; | |
297 | unsigned int psp_ring_reg = 0; | |
298 | struct psp_ring *ring = &psp->km_ring; | |
299 | struct amdgpu_device *adev = psp->adev; | |
300 | ||
301 | /* Write low address of the ring to C2PMSG_69 */ | |
302 | psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); | |
303 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); | |
304 | /* Write high address of the ring to C2PMSG_70 */ | |
305 | psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); | |
306 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); | |
307 | /* Write size of ring to C2PMSG_71 */ | |
308 | psp_ring_reg = ring->ring_size; | |
309 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); | |
310 | /* Write the ring initialization command to C2PMSG_64 */ | |
311 | psp_ring_reg = ring_type; | |
312 | psp_ring_reg = psp_ring_reg << 16; | |
313 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); | |
314 | ||
315 | /* there might be handshake issue with hardware which needs delay */ | |
316 | mdelay(20); | |
317 | ||
318 | /* Wait for response flag (bit 31) in C2PMSG_64 */ | |
319 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), | |
320 | 0x80000000, 0x8000FFFF, false); | |
321 | ||
322 | return ret; | |
323 | } | |
324 | ||
325 | static int psp_v11_0_ring_stop(struct psp_context *psp, | |
326 | enum psp_ring_type ring_type) | |
327 | { | |
328 | int ret = 0; | |
654f761c FX |
329 | struct amdgpu_device *adev = psp->adev; |
330 | ||
654f761c FX |
331 | /* Write the ring destroy command to C2PMSG_64 */ |
332 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS); | |
333 | ||
334 | /* there might be handshake issue with hardware which needs delay */ | |
335 | mdelay(20); | |
336 | ||
337 | /* Wait for response flag (bit 31) in C2PMSG_64 */ | |
338 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), | |
339 | 0x80000000, 0x80000000, false); | |
340 | ||
341 | return ret; | |
342 | } | |
343 | ||
344 | static int psp_v11_0_ring_destroy(struct psp_context *psp, | |
345 | enum psp_ring_type ring_type) | |
346 | { | |
347 | int ret = 0; | |
348 | struct psp_ring *ring = &psp->km_ring; | |
349 | struct amdgpu_device *adev = psp->adev; | |
350 | ||
351 | ret = psp_v11_0_ring_stop(psp, ring_type); | |
352 | if (ret) | |
353 | DRM_ERROR("Fail to stop psp ring\n"); | |
354 | ||
355 | amdgpu_bo_free_kernel(&adev->firmware.rbuf, | |
356 | &ring->ring_mem_mc_addr, | |
357 | (void **)&ring->ring_mem); | |
358 | ||
359 | return ret; | |
360 | } | |
361 | ||
362 | static int psp_v11_0_cmd_submit(struct psp_context *psp, | |
363 | struct amdgpu_firmware_info *ucode, | |
364 | uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, | |
365 | int index) | |
366 | { | |
367 | unsigned int psp_write_ptr_reg = 0; | |
368 | struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; | |
369 | struct psp_ring *ring = &psp->km_ring; | |
370 | struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; | |
371 | struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + | |
372 | ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; | |
373 | struct amdgpu_device *adev = psp->adev; | |
374 | uint32_t ring_size_dw = ring->ring_size / 4; | |
375 | uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; | |
376 | ||
377 | /* KM (GPCOM) prepare write pointer */ | |
378 | psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); | |
379 | ||
380 | /* Update KM RB frame pointer to new frame */ | |
381 | /* write_frame ptr increments by size of rb_frame in bytes */ | |
382 | /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ | |
383 | if ((psp_write_ptr_reg % ring_size_dw) == 0) | |
384 | write_frame = ring_buffer_start; | |
385 | else | |
386 | write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); | |
387 | /* Check invalid write_frame ptr address */ | |
388 | if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { | |
389 | DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", | |
390 | ring_buffer_start, ring_buffer_end, write_frame); | |
391 | DRM_ERROR("write_frame is pointing to address out of bounds\n"); | |
392 | return -EINVAL; | |
393 | } | |
394 | ||
395 | /* Initialize KM RB frame */ | |
396 | memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); | |
397 | ||
398 | /* Update KM RB frame */ | |
399 | write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); | |
400 | write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); | |
401 | write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); | |
402 | write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); | |
403 | write_frame->fence_value = index; | |
404 | ||
405 | /* Update the write Pointer in DWORDs */ | |
406 | psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; | |
407 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
412 | static int | |
413 | psp_v11_0_sram_map(struct amdgpu_device *adev, | |
414 | unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, | |
415 | unsigned int *sram_data_reg_offset, | |
416 | enum AMDGPU_UCODE_ID ucode_id) | |
417 | { | |
418 | int ret = 0; | |
419 | ||
420 | switch (ucode_id) { | |
421 | /* TODO: needs to confirm */ | |
422 | #if 0 | |
423 | case AMDGPU_UCODE_ID_SMC: | |
424 | *sram_offset = 0; | |
425 | *sram_addr_reg_offset = 0; | |
426 | *sram_data_reg_offset = 0; | |
427 | break; | |
428 | #endif | |
429 | ||
430 | case AMDGPU_UCODE_ID_CP_CE: | |
431 | *sram_offset = 0x0; | |
432 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); | |
433 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); | |
434 | break; | |
435 | ||
436 | case AMDGPU_UCODE_ID_CP_PFP: | |
437 | *sram_offset = 0x0; | |
438 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); | |
439 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); | |
440 | break; | |
441 | ||
442 | case AMDGPU_UCODE_ID_CP_ME: | |
443 | *sram_offset = 0x0; | |
444 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); | |
445 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); | |
446 | break; | |
447 | ||
448 | case AMDGPU_UCODE_ID_CP_MEC1: | |
449 | *sram_offset = 0x10000; | |
450 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); | |
451 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); | |
452 | break; | |
453 | ||
454 | case AMDGPU_UCODE_ID_CP_MEC2: | |
455 | *sram_offset = 0x10000; | |
456 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); | |
457 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); | |
458 | break; | |
459 | ||
460 | case AMDGPU_UCODE_ID_RLC_G: | |
461 | *sram_offset = 0x2000; | |
462 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); | |
463 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); | |
464 | break; | |
465 | ||
466 | case AMDGPU_UCODE_ID_SDMA0: | |
467 | *sram_offset = 0x0; | |
468 | *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); | |
469 | *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); | |
470 | break; | |
471 | ||
472 | /* TODO: needs to confirm */ | |
473 | #if 0 | |
474 | case AMDGPU_UCODE_ID_SDMA1: | |
475 | *sram_offset = ; | |
476 | *sram_addr_reg_offset = ; | |
477 | break; | |
478 | ||
479 | case AMDGPU_UCODE_ID_UVD: | |
480 | *sram_offset = ; | |
481 | *sram_addr_reg_offset = ; | |
482 | break; | |
483 | ||
484 | case AMDGPU_UCODE_ID_VCE: | |
485 | *sram_offset = ; | |
486 | *sram_addr_reg_offset = ; | |
487 | break; | |
488 | #endif | |
489 | ||
490 | case AMDGPU_UCODE_ID_MAXIMUM: | |
491 | default: | |
492 | ret = -EINVAL; | |
493 | break; | |
494 | } | |
495 | ||
496 | return ret; | |
497 | } | |
498 | ||
499 | static bool psp_v11_0_compare_sram_data(struct psp_context *psp, | |
500 | struct amdgpu_firmware_info *ucode, | |
501 | enum AMDGPU_UCODE_ID ucode_type) | |
502 | { | |
503 | int err = 0; | |
504 | unsigned int fw_sram_reg_val = 0; | |
505 | unsigned int fw_sram_addr_reg_offset = 0; | |
506 | unsigned int fw_sram_data_reg_offset = 0; | |
507 | unsigned int ucode_size; | |
508 | uint32_t *ucode_mem = NULL; | |
509 | struct amdgpu_device *adev = psp->adev; | |
510 | ||
511 | err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, | |
512 | &fw_sram_data_reg_offset, ucode_type); | |
513 | if (err) | |
514 | return false; | |
515 | ||
516 | WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); | |
517 | ||
518 | ucode_size = ucode->ucode_size; | |
519 | ucode_mem = (uint32_t *)ucode->kaddr; | |
520 | while (ucode_size) { | |
521 | fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); | |
522 | ||
523 | if (*ucode_mem != fw_sram_reg_val) | |
524 | return false; | |
525 | ||
526 | ucode_mem++; | |
527 | /* 4 bytes */ | |
528 | ucode_size -= 4; | |
529 | } | |
530 | ||
531 | return true; | |
532 | } | |
533 | ||
534 | static int psp_v11_0_mode1_reset(struct psp_context *psp) | |
535 | { | |
536 | int ret; | |
537 | uint32_t offset; | |
538 | struct amdgpu_device *adev = psp->adev; | |
539 | ||
540 | offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); | |
541 | ||
542 | ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); | |
543 | ||
544 | if (ret) { | |
545 | DRM_INFO("psp is not working correctly before mode1 reset!\n"); | |
546 | return -EINVAL; | |
547 | } | |
548 | ||
549 | /*send the mode 1 reset command*/ | |
550 | WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); | |
551 | ||
38cd8a28 | 552 | msleep(500); |
654f761c FX |
553 | |
554 | offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); | |
555 | ||
556 | ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); | |
557 | ||
558 | if (ret) { | |
559 | DRM_INFO("psp mode 1 reset failed!\n"); | |
560 | return -EINVAL; | |
561 | } | |
562 | ||
563 | DRM_INFO("psp mode1 reset succeed \n"); | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
78122127 SL |
568 | /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. |
569 | * For now, return success and hack the hive_id so high level code can | |
570 | * start testing | |
571 | */ | |
572 | static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, | |
573 | int number_devices, struct psp_xgmi_topology_info *topology) | |
574 | { | |
ec1a975e HZ |
575 | struct ta_xgmi_shared_memory *xgmi_cmd; |
576 | struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; | |
577 | struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; | |
578 | int i; | |
579 | int ret; | |
580 | ||
581 | if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) | |
582 | return -EINVAL; | |
583 | ||
584 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
585 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
586 | ||
587 | /* Fill in the shared memory with topology information as input */ | |
588 | topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; | |
589 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; | |
590 | topology_info_input->num_nodes = number_devices; | |
591 | ||
592 | for (i = 0; i < topology_info_input->num_nodes; i++) { | |
593 | topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; | |
594 | topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; | |
595 | topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; | |
596 | topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; | |
597 | } | |
598 | ||
599 | /* Invoke xgmi ta to get the topology information */ | |
600 | ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); | |
601 | if (ret) | |
602 | return ret; | |
603 | ||
604 | /* Read the output topology information from the shared memory */ | |
605 | topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; | |
606 | topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; | |
607 | for (i = 0; i < topology->num_nodes; i++) { | |
608 | topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; | |
609 | topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; | |
610 | topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; | |
611 | topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; | |
612 | } | |
613 | ||
78122127 SL |
614 | return 0; |
615 | } | |
616 | ||
617 | static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, | |
618 | int number_devices, struct psp_xgmi_topology_info *topology) | |
619 | { | |
bb8310cc HZ |
620 | struct ta_xgmi_shared_memory *xgmi_cmd; |
621 | struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; | |
622 | int i; | |
623 | ||
624 | if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) | |
625 | return -EINVAL; | |
626 | ||
627 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
628 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
629 | ||
630 | topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; | |
631 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; | |
632 | topology_info_input->num_nodes = number_devices; | |
633 | ||
634 | for (i = 0; i < topology_info_input->num_nodes; i++) { | |
635 | topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; | |
636 | topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; | |
637 | topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; | |
638 | topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; | |
639 | } | |
640 | ||
641 | /* Invoke xgmi ta to set topology information */ | |
642 | return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); | |
78122127 SL |
643 | } |
644 | ||
645 | static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context *psp) | |
646 | { | |
4b93151f HZ |
647 | struct ta_xgmi_shared_memory *xgmi_cmd; |
648 | int ret; | |
649 | ||
650 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
651 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
78122127 | 652 | |
4b93151f | 653 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; |
78122127 | 654 | |
4b93151f HZ |
655 | /* Invoke xgmi ta to get hive id */ |
656 | ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); | |
657 | if (ret) | |
658 | return 0; | |
659 | else | |
660 | return xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; | |
78122127 SL |
661 | } |
662 | ||
dd3c45d3 HZ |
663 | static u64 psp_v11_0_xgmi_get_node_id(struct psp_context *psp) |
664 | { | |
665 | struct ta_xgmi_shared_memory *xgmi_cmd; | |
666 | int ret; | |
667 | ||
668 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
669 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
670 | ||
671 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; | |
672 | ||
673 | /* Invoke xgmi ta to get the node id */ | |
674 | ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); | |
675 | if (ret) | |
676 | return 0; | |
677 | else | |
678 | return xgmi_cmd->xgmi_out_message.get_node_id.node_id; | |
679 | } | |
680 | ||
654f761c FX |
681 | static const struct psp_funcs psp_v11_0_funcs = { |
682 | .init_microcode = psp_v11_0_init_microcode, | |
683 | .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, | |
684 | .bootloader_load_sos = psp_v11_0_bootloader_load_sos, | |
685 | .prep_cmd_buf = psp_v11_0_prep_cmd_buf, | |
686 | .ring_init = psp_v11_0_ring_init, | |
687 | .ring_create = psp_v11_0_ring_create, | |
688 | .ring_stop = psp_v11_0_ring_stop, | |
689 | .ring_destroy = psp_v11_0_ring_destroy, | |
690 | .cmd_submit = psp_v11_0_cmd_submit, | |
691 | .compare_sram_data = psp_v11_0_compare_sram_data, | |
692 | .mode1_reset = psp_v11_0_mode1_reset, | |
78122127 SL |
693 | .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, |
694 | .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, | |
695 | .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, | |
dd3c45d3 | 696 | .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, |
654f761c FX |
697 | }; |
698 | ||
699 | void psp_v11_0_set_psp_funcs(struct psp_context *psp) | |
700 | { | |
701 | psp->funcs = &psp_v11_0_funcs; | |
702 | } |