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drm/amd/display: Fix MST dp_blank REG_WAIT timeout
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / psp_v11_0.c
CommitLineData
654f761c
FX		 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_psp.h"
26#include "amdgpu_ucode.h"
27#include "soc15_common.h"
28#include "psp_v11_0.h"
29
30#include "mp/mp_11_0_offset.h"
31#include "mp/mp_11_0_sh_mask.h"
32#include "gc/gc_9_0_offset.h"
33#include "sdma0/sdma0_4_0_offset.h"
34#include "nbio/nbio_7_4_offset.h"
35
36MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
51e7177f 37MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
654f761c
FX		 38
39/* address block */
40#define smnMP1_FIRMWARE_FLAGS 0x3010024
41
42static int
43psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
44{
45 switch (ucode->ucode_id) {
46 case AMDGPU_UCODE_ID_SDMA0:
47 *type = GFX_FW_TYPE_SDMA0;
48 break;
49 case AMDGPU_UCODE_ID_SDMA1:
50 *type = GFX_FW_TYPE_SDMA1;
51 break;
52 case AMDGPU_UCODE_ID_CP_CE:
53 *type = GFX_FW_TYPE_CP_CE;
54 break;
55 case AMDGPU_UCODE_ID_CP_PFP:
56 *type = GFX_FW_TYPE_CP_PFP;
57 break;
58 case AMDGPU_UCODE_ID_CP_ME:
59 *type = GFX_FW_TYPE_CP_ME;
60 break;
61 case AMDGPU_UCODE_ID_CP_MEC1:
62 *type = GFX_FW_TYPE_CP_MEC;
63 break;
64 case AMDGPU_UCODE_ID_CP_MEC1_JT:
65 *type = GFX_FW_TYPE_CP_MEC_ME1;
66 break;
67 case AMDGPU_UCODE_ID_CP_MEC2:
68 *type = GFX_FW_TYPE_CP_MEC;
69 break;
70 case AMDGPU_UCODE_ID_CP_MEC2_JT:
71 *type = GFX_FW_TYPE_CP_MEC_ME2;
72 break;
73 case AMDGPU_UCODE_ID_RLC_G:
74 *type = GFX_FW_TYPE_RLC_G;
75 break;
76 case AMDGPU_UCODE_ID_SMC:
77 *type = GFX_FW_TYPE_SMU;
78 break;
79 case AMDGPU_UCODE_ID_UVD:
80 *type = GFX_FW_TYPE_UVD;
81 break;
82 case AMDGPU_UCODE_ID_VCE:
83 *type = GFX_FW_TYPE_VCE;
84 break;
d4e83843
EQ		 85 case AMDGPU_UCODE_ID_UVD1:
86 *type = GFX_FW_TYPE_UVD1;
87 break;
654f761c
FX		 88 case AMDGPU_UCODE_ID_MAXIMUM:
89 default:
90 return -EINVAL;
91 }
92
93 return 0;
94}
95
96static int psp_v11_0_init_microcode(struct psp_context *psp)
97{
98 struct amdgpu_device *adev = psp->adev;
99 const char *chip_name;
100 char fw_name[30];
101 int err = 0;
51e7177f
HZ		 102 const struct psp_firmware_header_v1_0 *sos_hdr;
103 const struct ta_firmware_header_v1_0 *ta_hdr;
654f761c
FX		 104
105 DRM_DEBUG("\n");
106
107 switch (adev->asic_type) {
108 case CHIP_VEGA20:
109 chip_name = "vega20";
110 break;
111 default:
112 BUG();
113 }
114
115 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
116 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
117 if (err)
118 goto out;
119
120 err = amdgpu_ucode_validate(adev->psp.sos_fw);
121 if (err)
122 goto out;
123
51e7177f
HZ		 124 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
125 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
126 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
127 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
128 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) -
129 le32_to_cpu(sos_hdr->sos_size_bytes);
130 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
131 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
654f761c 132 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
51e7177f
HZ		 133 le32_to_cpu(sos_hdr->sos_offset_bytes);
134
135 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
136 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
137 if (err)
138 goto out;
139
140 err = amdgpu_ucode_validate(adev->psp.ta_fw);
141 if (err)
142 goto out;
143
144 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
145 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
146 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
147 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
148 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
149
654f761c
FX		 150 return 0;
151out:
152 if (err) {
153 dev_err(adev->dev,
154 "psp v11.0: Failed to load firmware \"%s\"\n",
155 fw_name);
156 release_firmware(adev->psp.sos_fw);
157 adev->psp.sos_fw = NULL;
158 }
159
160 return err;
161}
162
163static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
164{
165 int ret;
166 uint32_t psp_gfxdrv_command_reg = 0;
167 struct amdgpu_device *adev = psp->adev;
168 uint32_t sol_reg;
169
170 /* Check sOS sign of life register to confirm sys driver and sOS
171 * are already been loaded.
172 */
173 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
d63cda5b
XY		 174 if (sol_reg) {
175 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
5ec996df 176 printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
654f761c 177 return 0;
d63cda5b 178 }
654f761c
FX		 179
180 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
181 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
182 0x80000000, 0x80000000, false);
183 if (ret)
184 return ret;
185
186 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
187
188 /* Copy PSP System Driver binary to memory */
189 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
190
548f2ecc 191 /* Provide the sys driver to bootloader */
654f761c
FX		 192 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
193 (uint32_t)(psp->fw_pri_mc_addr >> 20));
194 psp_gfxdrv_command_reg = 1 << 16;
195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
196 psp_gfxdrv_command_reg);
197
198 /* there might be handshake issue with hardware which needs delay */
199 mdelay(20);
200
201 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
202 0x80000000, 0x80000000, false);
203
204 return ret;
205}
206
207static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
208{
209 int ret;
210 unsigned int psp_gfxdrv_command_reg = 0;
211 struct amdgpu_device *adev = psp->adev;
212 uint32_t sol_reg;
213
214 /* Check sOS sign of life register to confirm sys driver and sOS
215 * are already been loaded.
216 */
217 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
218 if (sol_reg)
219 return 0;
220
221 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
222 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
223 0x80000000, 0x80000000, false);
224 if (ret)
225 return ret;
226
227 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
228
229 /* Copy Secure OS binary to PSP memory */
230 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
231
548f2ecc 232 /* Provide the PSP secure OS to bootloader */
654f761c
FX		 233 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
234 (uint32_t)(psp->fw_pri_mc_addr >> 20));
235 psp_gfxdrv_command_reg = 2 << 16;
236 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
237 psp_gfxdrv_command_reg);
238
239 /* there might be handshake issue with hardware which needs delay */
240 mdelay(20);
241 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
242 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
243 0, true);
244
245 return ret;
246}
247
248static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
249 struct psp_gfx_cmd_resp *cmd)
250{
251 int ret;
252 uint64_t fw_mem_mc_addr = ucode->mc_addr;
253
254 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
255
256 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
257 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
258 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
259 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
260
261 ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
262 if (ret)
263 DRM_ERROR("Unknown firmware type\n");
264
265 return ret;
266}
267
268static int psp_v11_0_ring_init(struct psp_context *psp,
269 enum psp_ring_type ring_type)
270{
271 int ret = 0;
272 struct psp_ring *ring;
273 struct amdgpu_device *adev = psp->adev;
274
275 ring = &psp->km_ring;
276
277 ring->ring_type = ring_type;
278
279 /* allocate 4k Page of Local Frame Buffer memory for ring */
280 ring->ring_size = 0x1000;
281 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
282 AMDGPU_GEM_DOMAIN_VRAM,
283 &adev->firmware.rbuf,
284 &ring->ring_mem_mc_addr,
285 (void **)&ring->ring_mem);
286 if (ret) {
287 ring->ring_size = 0;
288 return ret;
289 }
290
291 return 0;
292}
293
e27a73d1
ED		 294static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
295{
296 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
297 return true;
298 return false;
299}
300
654f761c
FX		 301static int psp_v11_0_ring_create(struct psp_context *psp,
302 enum psp_ring_type ring_type)
303{
304 int ret = 0;
305 unsigned int psp_ring_reg = 0;
306 struct psp_ring *ring = &psp->km_ring;
307 struct amdgpu_device *adev = psp->adev;
308
e27a73d1 309 if (psp_v11_0_support_vmr_ring(psp)) {
5ec996df
XY		 310 /* Write low address of the ring to C2PMSG_102 */
311 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
312 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
313 /* Write high address of the ring to C2PMSG_103 */
314 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
315 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
316
317 /* Write the ring initialization command to C2PMSG_101 */
318 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
319 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
320
321 /* there might be handshake issue with hardware which needs delay */
322 mdelay(20);
323
324 /* Wait for response flag (bit 31) in C2PMSG_101 */
325 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
326 0x80000000, 0x8000FFFF, false);
327
328 } else {
329 /* Write low address of the ring to C2PMSG_69 */
330 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
331 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
332 /* Write high address of the ring to C2PMSG_70 */
333 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
334 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
335 /* Write size of ring to C2PMSG_71 */
336 psp_ring_reg = ring->ring_size;
337 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
338 /* Write the ring initialization command to C2PMSG_64 */
339 psp_ring_reg = ring_type;
340 psp_ring_reg = psp_ring_reg << 16;
341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
342
343 /* there might be handshake issue with hardware which needs delay */
344 mdelay(20);
345
346 /* Wait for response flag (bit 31) in C2PMSG_64 */
347 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
348 0x80000000, 0x8000FFFF, false);
349 }
654f761c
FX		 350
351 return ret;
352}
353
354static int psp_v11_0_ring_stop(struct psp_context *psp,
355 enum psp_ring_type ring_type)
356{
357 int ret = 0;
654f761c
FX		 358 struct amdgpu_device *adev = psp->adev;
359
5ec996df 360 /* Write the ring destroy command*/
e27a73d1 361 if (psp_v11_0_support_vmr_ring(psp))
5ec996df
XY		 362 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
363 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
364 else
365 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
366 GFX_CTRL_CMD_ID_DESTROY_RINGS);
654f761c
FX		 367
368 /* there might be handshake issue with hardware which needs delay */
369 mdelay(20);
370
5ec996df 371 /* Wait for response flag (bit 31) */
e27a73d1 372 if (psp_v11_0_support_vmr_ring(psp))
5ec996df
XY		 373 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
374 0x80000000, 0x80000000, false);
375 else
376 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
377 0x80000000, 0x80000000, false);
654f761c
FX		 378
379 return ret;
380}
381
382static int psp_v11_0_ring_destroy(struct psp_context *psp,
383 enum psp_ring_type ring_type)
384{
385 int ret = 0;
386 struct psp_ring *ring = &psp->km_ring;
387 struct amdgpu_device *adev = psp->adev;
388
389 ret = psp_v11_0_ring_stop(psp, ring_type);
390 if (ret)
391 DRM_ERROR("Fail to stop psp ring\n");
392
393 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
394 &ring->ring_mem_mc_addr,
395 (void **)&ring->ring_mem);
396
397 return ret;
398}
399
400static int psp_v11_0_cmd_submit(struct psp_context *psp,
401 struct amdgpu_firmware_info *ucode,
402 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
403 int index)
404{
405 unsigned int psp_write_ptr_reg = 0;
406 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
407 struct psp_ring *ring = &psp->km_ring;
408 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
409 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
410 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
411 struct amdgpu_device *adev = psp->adev;
412 uint32_t ring_size_dw = ring->ring_size / 4;
413 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
414
415 /* KM (GPCOM) prepare write pointer */
e27a73d1 416 if (psp_v11_0_support_vmr_ring(psp))
5ec996df
XY		 417 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
418 else
419 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
654f761c
FX		 420
421 /* Update KM RB frame pointer to new frame */
422 /* write_frame ptr increments by size of rb_frame in bytes */
423 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
424 if ((psp_write_ptr_reg % ring_size_dw) == 0)
425 write_frame = ring_buffer_start;
426 else
427 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
428 /* Check invalid write_frame ptr address */
429 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
430 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
431 ring_buffer_start, ring_buffer_end, write_frame);
432 DRM_ERROR("write_frame is pointing to address out of bounds\n");
433 return -EINVAL;
434 }
435
436 /* Initialize KM RB frame */
437 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
438
439 /* Update KM RB frame */
440 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
441 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
442 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
443 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
444 write_frame->fence_value = index;
445
446 /* Update the write Pointer in DWORDs */
447 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
e27a73d1 448 if (psp_v11_0_support_vmr_ring(psp)) {
5ec996df
XY		 449 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
450 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
451 } else
452 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
654f761c
FX		 453
454 return 0;
455}
456
457static int
458psp_v11_0_sram_map(struct amdgpu_device *adev,
459 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
460 unsigned int *sram_data_reg_offset,
461 enum AMDGPU_UCODE_ID ucode_id)
462{
463 int ret = 0;
464
465 switch (ucode_id) {
466/* TODO: needs to confirm */
467#if 0
468 case AMDGPU_UCODE_ID_SMC:
469 *sram_offset = 0;
470 *sram_addr_reg_offset = 0;
471 *sram_data_reg_offset = 0;
472 break;
473#endif
474
475 case AMDGPU_UCODE_ID_CP_CE:
476 *sram_offset = 0x0;
477 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
478 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
479 break;
480
481 case AMDGPU_UCODE_ID_CP_PFP:
482 *sram_offset = 0x0;
483 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
484 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
485 break;
486
487 case AMDGPU_UCODE_ID_CP_ME:
488 *sram_offset = 0x0;
489 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
490 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
491 break;
492
493 case AMDGPU_UCODE_ID_CP_MEC1:
494 *sram_offset = 0x10000;
495 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
496 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
497 break;
498
499 case AMDGPU_UCODE_ID_CP_MEC2:
500 *sram_offset = 0x10000;
501 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
502 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
503 break;
504
505 case AMDGPU_UCODE_ID_RLC_G:
506 *sram_offset = 0x2000;
507 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
508 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
509 break;
510
511 case AMDGPU_UCODE_ID_SDMA0:
512 *sram_offset = 0x0;
513 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
514 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
515 break;
516
517/* TODO: needs to confirm */
518#if 0
519 case AMDGPU_UCODE_ID_SDMA1:
520 *sram_offset = ;
521 *sram_addr_reg_offset = ;
522 break;
523
524 case AMDGPU_UCODE_ID_UVD:
525 *sram_offset = ;
526 *sram_addr_reg_offset = ;
527 break;
528
529 case AMDGPU_UCODE_ID_VCE:
530 *sram_offset = ;
531 *sram_addr_reg_offset = ;
532 break;
533#endif
534
535 case AMDGPU_UCODE_ID_MAXIMUM:
536 default:
537 ret = -EINVAL;
538 break;
539 }
540
541 return ret;
542}
543
544static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
545 struct amdgpu_firmware_info *ucode,
546 enum AMDGPU_UCODE_ID ucode_type)
547{
548 int err = 0;
549 unsigned int fw_sram_reg_val = 0;
550 unsigned int fw_sram_addr_reg_offset = 0;
551 unsigned int fw_sram_data_reg_offset = 0;
552 unsigned int ucode_size;
553 uint32_t *ucode_mem = NULL;
554 struct amdgpu_device *adev = psp->adev;
555
556 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
557 &fw_sram_data_reg_offset, ucode_type);
558 if (err)
559 return false;
560
561 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
562
563 ucode_size = ucode->ucode_size;
564 ucode_mem = (uint32_t *)ucode->kaddr;
565 while (ucode_size) {
566 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
567
568 if (*ucode_mem != fw_sram_reg_val)
569 return false;
570
571 ucode_mem++;
572 /* 4 bytes */
573 ucode_size -= 4;
574 }
575
576 return true;
577}
578
579static int psp_v11_0_mode1_reset(struct psp_context *psp)
580{
581 int ret;
582 uint32_t offset;
583 struct amdgpu_device *adev = psp->adev;
584
585 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
586
587 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
588
589 if (ret) {
590 DRM_INFO("psp is not working correctly before mode1 reset!\n");
591 return -EINVAL;
592 }
593
594 /*send the mode 1 reset command*/
595 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
596
38cd8a28 597 msleep(500);
654f761c
FX		 598
599 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
600
601 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
602
603 if (ret) {
604 DRM_INFO("psp mode 1 reset failed!\n");
605 return -EINVAL;
606 }
607
608 DRM_INFO("psp mode1 reset succeed \n");
609
610 return 0;
611}
612
78122127
SL		 613/* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
614 * For now, return success and hack the hive_id so high level code can
615 * start testing
616 */
617static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
618 int number_devices, struct psp_xgmi_topology_info *topology)
619{
ec1a975e
HZ		 620 struct ta_xgmi_shared_memory *xgmi_cmd;
621 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
622 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
623 int i;
624 int ret;
625
626 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
627 return -EINVAL;
628
629 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
630 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
631
632 /* Fill in the shared memory with topology information as input */
633 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
634 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
635 topology_info_input->num_nodes = number_devices;
636
637 for (i = 0; i < topology_info_input->num_nodes; i++) {
638 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
639 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
640 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
641 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
642 }
643
644 /* Invoke xgmi ta to get the topology information */
645 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
646 if (ret)
647 return ret;
648
649 /* Read the output topology information from the shared memory */
650 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
651 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
652 for (i = 0; i < topology->num_nodes; i++) {
653 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
654 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
655 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
656 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
657 }
658
78122127
SL		 659 return 0;
660}
661
662static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
663 int number_devices, struct psp_xgmi_topology_info *topology)
664{
bb8310cc
HZ		 665 struct ta_xgmi_shared_memory *xgmi_cmd;
666 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
667 int i;
668
669 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
670 return -EINVAL;
671
672 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
673 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
674
675 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
676 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
677 topology_info_input->num_nodes = number_devices;
678
679 for (i = 0; i < topology_info_input->num_nodes; i++) {
680 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
681 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
682 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
683 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
684 }
685
686 /* Invoke xgmi ta to set topology information */
687 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
78122127
SL		 688}
689
379c237e 690static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
78122127 691{
4b93151f
HZ		 692 struct ta_xgmi_shared_memory *xgmi_cmd;
693 int ret;
694
695 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
696 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
78122127 697
4b93151f 698 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
78122127 699
4b93151f
HZ		 700 /* Invoke xgmi ta to get hive id */
701 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
702 if (ret)
379c237e
EQ		 703 return ret;
704
705 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
706
707 return 0;
78122127
SL		 708}
709
379c237e 710static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
dd3c45d3
HZ		 711{
712 struct ta_xgmi_shared_memory *xgmi_cmd;
713 int ret;
714
715 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
716 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
717
718 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
719
720 /* Invoke xgmi ta to get the node id */
721 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
722 if (ret)
379c237e
EQ		 723 return ret;
724
725 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
726
727 return 0;
dd3c45d3
HZ		 728}
729
654f761c
FX		 730static const struct psp_funcs psp_v11_0_funcs = {
731 .init_microcode = psp_v11_0_init_microcode,
732 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
733 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
734 .prep_cmd_buf = psp_v11_0_prep_cmd_buf,
735 .ring_init = psp_v11_0_ring_init,
736 .ring_create = psp_v11_0_ring_create,
737 .ring_stop = psp_v11_0_ring_stop,
738 .ring_destroy = psp_v11_0_ring_destroy,
739 .cmd_submit = psp_v11_0_cmd_submit,
740 .compare_sram_data = psp_v11_0_compare_sram_data,
741 .mode1_reset = psp_v11_0_mode1_reset,
78122127
SL		 742 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
743 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
744 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
dd3c45d3 745 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
e27a73d1 746 .support_vmr_ring = psp_v11_0_support_vmr_ring,
654f761c
FX		 747};
748
749void psp_v11_0_set_psp_funcs(struct psp_context *psp)
750{
751 psp->funcs = &psp_v11_0_funcs;
752}
Linux 6.x block layer and io_uring tree(s)