[linux-block.git] / drivers / gpu / drm / amd / amdgpu / psp_v11_0.c

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_psp.h"
#include "amdgpu_ucode.h"
#include "soc15_common.h"
#include "psp_v11_0.h"

#include "mp/mp_11_0_offset.h"
#include "mp/mp_11_0_sh_mask.h"
#include "gc/gc_9_0_offset.h"
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_7_4_offset.h"

MODULE_FIRMWARE("amdgpu/vega20_sos.bin");

/* address block */
#define smnMP1_FIRMWARE_FLAGS		0x3010024

static int
psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
{
	switch (ucode->ucode_id) {
	case AMDGPU_UCODE_ID_SDMA0:
		*type = GFX_FW_TYPE_SDMA0;
		break;
	case AMDGPU_UCODE_ID_SDMA1:
		*type = GFX_FW_TYPE_SDMA1;
		break;
	case AMDGPU_UCODE_ID_CP_CE:
		*type = GFX_FW_TYPE_CP_CE;
		break;
	case AMDGPU_UCODE_ID_CP_PFP:
		*type = GFX_FW_TYPE_CP_PFP;
		break;
	case AMDGPU_UCODE_ID_CP_ME:
		*type = GFX_FW_TYPE_CP_ME;
		break;
	case AMDGPU_UCODE_ID_CP_MEC1:
		*type = GFX_FW_TYPE_CP_MEC;
		break;
	case AMDGPU_UCODE_ID_CP_MEC1_JT:
		*type = GFX_FW_TYPE_CP_MEC_ME1;
		break;
	case AMDGPU_UCODE_ID_CP_MEC2:
		*type = GFX_FW_TYPE_CP_MEC;
		break;
	case AMDGPU_UCODE_ID_CP_MEC2_JT:
		*type = GFX_FW_TYPE_CP_MEC_ME2;
		break;
	case AMDGPU_UCODE_ID_RLC_G:
		*type = GFX_FW_TYPE_RLC_G;
		break;
	case AMDGPU_UCODE_ID_SMC:
		*type = GFX_FW_TYPE_SMU;
		break;
	case AMDGPU_UCODE_ID_UVD:
		*type = GFX_FW_TYPE_UVD;
		break;
	case AMDGPU_UCODE_ID_VCE:
		*type = GFX_FW_TYPE_VCE;
		break;
	case AMDGPU_UCODE_ID_MAXIMUM:
	default:
		return -EINVAL;
	}

	return 0;
}

static int psp_v11_0_init_microcode(struct psp_context *psp)
{
	struct amdgpu_device *adev = psp->adev;
	const char *chip_name;
	char fw_name[30];
	int err = 0;
	const struct psp_firmware_header_v1_0 *hdr;

	DRM_DEBUG("\n");

	switch (adev->asic_type) {
	case CHIP_VEGA20:
		chip_name = "vega20";
		break;
	default:
		BUG();
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
	err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
	if (err)
		goto out;

	err = amdgpu_ucode_validate(adev->psp.sos_fw);
	if (err)
		goto out;

	hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
	adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
	adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
	adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
	adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
					le32_to_cpu(hdr->sos_size_bytes);
	adev->psp.sys_start_addr = (uint8_t *)hdr +
				le32_to_cpu(hdr->header.ucode_array_offset_bytes);
	adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
				le32_to_cpu(hdr->sos_offset_bytes);
	return 0;
out:
	if (err) {
		dev_err(adev->dev,
			"psp v11.0: Failed to load firmware \"%s\"\n",
			fw_name);
		release_firmware(adev->psp.sos_fw);
		adev->psp.sos_fw = NULL;
	}

	return err;
}

static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
{
	int ret;
	uint32_t psp_gfxdrv_command_reg = 0;
	struct amdgpu_device *adev = psp->adev;
	uint32_t sol_reg;

	/* Check sOS sign of life register to confirm sys driver and sOS
	 * are already been loaded.
	 */
	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
	if (sol_reg)
		return 0;

	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
			   0x80000000, 0x80000000, false);
	if (ret)
		return ret;

	memset(psp->fw_pri_buf, 0, PSP_1_MEG);

	/* Copy PSP System Driver binary to memory */
	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);

	/* Provide the sys driver to bootrom */
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
	psp_gfxdrv_command_reg = 1 << 16;
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
	       psp_gfxdrv_command_reg);

	/* there might be handshake issue with hardware which needs delay */
	mdelay(20);

	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
			   0x80000000, 0x80000000, false);

	return ret;
}

static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
{
	int ret;
	unsigned int psp_gfxdrv_command_reg = 0;
	struct amdgpu_device *adev = psp->adev;
	uint32_t sol_reg;

	/* Check sOS sign of life register to confirm sys driver and sOS
	 * are already been loaded.
	 */
	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
	if (sol_reg)
		return 0;

	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
			   0x80000000, 0x80000000, false);
	if (ret)
		return ret;

	memset(psp->fw_pri_buf, 0, PSP_1_MEG);

	/* Copy Secure OS binary to PSP memory */
	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);

	/* Provide the PSP secure OS to bootrom */
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
	psp_gfxdrv_command_reg = 2 << 16;
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
	       psp_gfxdrv_command_reg);

	/* there might be handshake issue with hardware which needs delay */
	mdelay(20);
	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
			   0, true);

	return ret;
}

static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
				 struct psp_gfx_cmd_resp *cmd)
{
	int ret;
	uint64_t fw_mem_mc_addr = ucode->mc_addr;

	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));

	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;

	ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
	if (ret)
		DRM_ERROR("Unknown firmware type\n");

	return ret;
}

static int psp_v11_0_ring_init(struct psp_context *psp,
			      enum psp_ring_type ring_type)
{
	int ret = 0;
	struct psp_ring *ring;
	struct amdgpu_device *adev = psp->adev;

	ring = &psp->km_ring;

	ring->ring_type = ring_type;

	/* allocate 4k Page of Local Frame Buffer memory for ring */
	ring->ring_size = 0x1000;
	ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
				      AMDGPU_GEM_DOMAIN_VRAM,
				      &adev->firmware.rbuf,
				      &ring->ring_mem_mc_addr,
				      (void **)&ring->ring_mem);
	if (ret) {
		ring->ring_size = 0;
		return ret;
	}

	return 0;
}

static int psp_v11_0_ring_create(struct psp_context *psp,
				enum psp_ring_type ring_type)
{
	int ret = 0;
	unsigned int psp_ring_reg = 0;
	struct psp_ring *ring = &psp->km_ring;
	struct amdgpu_device *adev = psp->adev;

	/* Write low address of the ring to C2PMSG_69 */
	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
	/* Write high address of the ring to C2PMSG_70 */
	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
	/* Write size of ring to C2PMSG_71 */
	psp_ring_reg = ring->ring_size;
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
	/* Write the ring initialization command to C2PMSG_64 */
	psp_ring_reg = ring_type;
	psp_ring_reg = psp_ring_reg << 16;
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);

	/* there might be handshake issue with hardware which needs delay */
	mdelay(20);

	/* Wait for response flag (bit 31) in C2PMSG_64 */
	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
			   0x80000000, 0x8000FFFF, false);

	return ret;
}

static int psp_v11_0_ring_stop(struct psp_context *psp,
			      enum psp_ring_type ring_type)
{
	int ret = 0;
	struct psp_ring *ring;
	struct amdgpu_device *adev = psp->adev;

	ring = &psp->km_ring;

	/* Write the ring destroy command to C2PMSG_64 */
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS);

	/* there might be handshake issue with hardware which needs delay */
	mdelay(20);

	/* Wait for response flag (bit 31) in C2PMSG_64 */
	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
			   0x80000000, 0x80000000, false);

	return ret;
}

static int psp_v11_0_ring_destroy(struct psp_context *psp,
				 enum psp_ring_type ring_type)
{
	int ret = 0;
	struct psp_ring *ring = &psp->km_ring;
	struct amdgpu_device *adev = psp->adev;

	ret = psp_v11_0_ring_stop(psp, ring_type);
	if (ret)
		DRM_ERROR("Fail to stop psp ring\n");

	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
			      &ring->ring_mem_mc_addr,
			      (void **)&ring->ring_mem);

	return ret;
}

static int psp_v11_0_cmd_submit(struct psp_context *psp,
			       struct amdgpu_firmware_info *ucode,
			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
			       int index)
{
	unsigned int psp_write_ptr_reg = 0;
	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
	struct psp_ring *ring = &psp->km_ring;
	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
	struct amdgpu_device *adev = psp->adev;
	uint32_t ring_size_dw = ring->ring_size / 4;
	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;

	/* KM (GPCOM) prepare write pointer */
	psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

	/* Update KM RB frame pointer to new frame */
	/* write_frame ptr increments by size of rb_frame in bytes */
	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
	if ((psp_write_ptr_reg % ring_size_dw) == 0)
		write_frame = ring_buffer_start;
	else
		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
	/* Check invalid write_frame ptr address */
	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
			  ring_buffer_start, ring_buffer_end, write_frame);
		DRM_ERROR("write_frame is pointing to address out of bounds\n");
		return -EINVAL;
	}

	/* Initialize KM RB frame */
	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));

	/* Update KM RB frame */
	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
	write_frame->fence_value = index;

	/* Update the write Pointer in DWORDs */
	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);

	return 0;
}

static int
psp_v11_0_sram_map(struct amdgpu_device *adev,
		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
		  unsigned int *sram_data_reg_offset,
		  enum AMDGPU_UCODE_ID ucode_id)
{
	int ret = 0;

	switch (ucode_id) {
/* TODO: needs to confirm */
#if 0
	case AMDGPU_UCODE_ID_SMC:
		*sram_offset = 0;
		*sram_addr_reg_offset = 0;
		*sram_data_reg_offset = 0;
		break;
#endif

	case AMDGPU_UCODE_ID_CP_CE:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
		break;

	case AMDGPU_UCODE_ID_CP_PFP:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
		break;

	case AMDGPU_UCODE_ID_CP_ME:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
		break;

	case AMDGPU_UCODE_ID_CP_MEC1:
		*sram_offset = 0x10000;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
		break;

	case AMDGPU_UCODE_ID_CP_MEC2:
		*sram_offset = 0x10000;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
		break;

	case AMDGPU_UCODE_ID_RLC_G:
		*sram_offset = 0x2000;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
		break;

	case AMDGPU_UCODE_ID_SDMA0:
		*sram_offset = 0x0;
		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
		break;

/* TODO: needs to confirm */
#if 0
	case AMDGPU_UCODE_ID_SDMA1:
		*sram_offset = ;
		*sram_addr_reg_offset = ;
		break;

	case AMDGPU_UCODE_ID_UVD:
		*sram_offset = ;
		*sram_addr_reg_offset = ;
		break;

	case AMDGPU_UCODE_ID_VCE:
		*sram_offset = ;
		*sram_addr_reg_offset = ;
		break;
#endif

	case AMDGPU_UCODE_ID_MAXIMUM:
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
				       struct amdgpu_firmware_info *ucode,
				       enum AMDGPU_UCODE_ID ucode_type)
{
	int err = 0;
	unsigned int fw_sram_reg_val = 0;
	unsigned int fw_sram_addr_reg_offset = 0;
	unsigned int fw_sram_data_reg_offset = 0;
	unsigned int ucode_size;
	uint32_t *ucode_mem = NULL;
	struct amdgpu_device *adev = psp->adev;

	err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
				&fw_sram_data_reg_offset, ucode_type);
	if (err)
		return false;

	WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);

	ucode_size = ucode->ucode_size;
	ucode_mem = (uint32_t *)ucode->kaddr;
	while (ucode_size) {
		fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);

		if (*ucode_mem != fw_sram_reg_val)
			return false;

		ucode_mem++;
		/* 4 bytes */
		ucode_size -= 4;
	}

	return true;
}

static int psp_v11_0_mode1_reset(struct psp_context *psp)
{
	int ret;
	uint32_t offset;
	struct amdgpu_device *adev = psp->adev;

	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);

	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);

	if (ret) {
		DRM_INFO("psp is not working correctly before mode1 reset!\n");
		return -EINVAL;
	}

	/*send the mode 1 reset command*/
	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);

	mdelay(1000);

	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);

	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);

	if (ret) {
		DRM_INFO("psp mode 1 reset failed!\n");
		return -EINVAL;
	}

	DRM_INFO("psp mode1 reset succeed \n");

	return 0;
}

static const struct psp_funcs psp_v11_0_funcs = {
	.init_microcode = psp_v11_0_init_microcode,
	.bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
	.bootloader_load_sos = psp_v11_0_bootloader_load_sos,
	.prep_cmd_buf = psp_v11_0_prep_cmd_buf,
	.ring_init = psp_v11_0_ring_init,
	.ring_create = psp_v11_0_ring_create,
	.ring_stop = psp_v11_0_ring_stop,
	.ring_destroy = psp_v11_0_ring_destroy,
	.cmd_submit = psp_v11_0_cmd_submit,
	.compare_sram_data = psp_v11_0_compare_sram_data,
	.mode1_reset = psp_v11_0_mode1_reset,
};

void psp_v11_0_set_psp_funcs(struct psp_context *psp)
{
	psp->funcs = &psp_v11_0_funcs;
}
Commit	Line	Data
654f761c FX	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#include <linux/firmware.h>
	24	#include "amdgpu.h"
	25	#include "amdgpu_psp.h"
	26	#include "amdgpu_ucode.h"
	27	#include "soc15_common.h"
	28	#include "psp_v11_0.h"
	29
	30	#include "mp/mp_11_0_offset.h"
	31	#include "mp/mp_11_0_sh_mask.h"
	32	#include "gc/gc_9_0_offset.h"
	33	#include "sdma0/sdma0_4_0_offset.h"
	34	#include "nbio/nbio_7_4_offset.h"
	35
	36	MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
	37
	38	/* address block */
	39	#define smnMP1_FIRMWARE_FLAGS 0x3010024
	40
	41	static int
	42	psp_v11_0_get_fw_type(struct amdgpu_firmware_info ucode, enum psp_gfx_fw_type type)
	43	{
	44	switch (ucode->ucode_id) {
	45	case AMDGPU_UCODE_ID_SDMA0:
	46	*type = GFX_FW_TYPE_SDMA0;
	47	break;
	48	case AMDGPU_UCODE_ID_SDMA1:
	49	*type = GFX_FW_TYPE_SDMA1;
	50	break;
	51	case AMDGPU_UCODE_ID_CP_CE:
	52	*type = GFX_FW_TYPE_CP_CE;
	53	break;
	54	case AMDGPU_UCODE_ID_CP_PFP:
	55	*type = GFX_FW_TYPE_CP_PFP;
	56	break;
	57	case AMDGPU_UCODE_ID_CP_ME:
	58	*type = GFX_FW_TYPE_CP_ME;
	59	break;
	60	case AMDGPU_UCODE_ID_CP_MEC1:
	61	*type = GFX_FW_TYPE_CP_MEC;
	62	break;
	63	case AMDGPU_UCODE_ID_CP_MEC1_JT:
	64	*type = GFX_FW_TYPE_CP_MEC_ME1;
65	break;
66	case AMDGPU_UCODE_ID_CP_MEC2:
67	*type = GFX_FW_TYPE_CP_MEC;
68	break;
69	case AMDGPU_UCODE_ID_CP_MEC2_JT:
70	*type = GFX_FW_TYPE_CP_MEC_ME2;
71	break;
72	case AMDGPU_UCODE_ID_RLC_G:
73	*type = GFX_FW_TYPE_RLC_G;
74	break;
75	case AMDGPU_UCODE_ID_SMC:
76	*type = GFX_FW_TYPE_SMU;
77	break;
78	case AMDGPU_UCODE_ID_UVD:
79	*type = GFX_FW_TYPE_UVD;
80	break;
81	case AMDGPU_UCODE_ID_VCE:
82	*type = GFX_FW_TYPE_VCE;
83	break;
84	case AMDGPU_UCODE_ID_MAXIMUM:
85	default:
86	return -EINVAL;
87	}
88
89	return 0;
90	}
91
92	static int psp_v11_0_init_microcode(struct psp_context *psp)
93	{
94	struct amdgpu_device *adev = psp->adev;
95	const char *chip_name;
96	char fw_name[30];
97	int err = 0;
98	const struct psp_firmware_header_v1_0 *hdr;
99
100	DRM_DEBUG("\n");
101
102	switch (adev->asic_type) {
103	case CHIP_VEGA20:
104	chip_name = "vega20";
105	break;
106	default:
107	BUG();
108	}
109
110	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
111	err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
112	if (err)
113	goto out;
114
115	err = amdgpu_ucode_validate(adev->psp.sos_fw);
116	if (err)
117	goto out;
118
119	hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
120	adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
121	adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
122	adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
123	adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
124	le32_to_cpu(hdr->sos_size_bytes);
125	adev->psp.sys_start_addr = (uint8_t *)hdr +
126	le32_to_cpu(hdr->header.ucode_array_offset_bytes);
127	adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
128	le32_to_cpu(hdr->sos_offset_bytes);
129	return 0;
130	out:
131	if (err) {
132	dev_err(adev->dev,
133	"psp v11.0: Failed to load firmware \"%s\"\n",
134	fw_name);
135	release_firmware(adev->psp.sos_fw);
136	adev->psp.sos_fw = NULL;
137	}
138
139	return err;
140	}
141
142	static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
143	{
144	int ret;
145	uint32_t psp_gfxdrv_command_reg = 0;
146	struct amdgpu_device *adev = psp->adev;
147	uint32_t sol_reg;
148
149	/* Check sOS sign of life register to confirm sys driver and sOS
150	* are already been loaded.
151	*/
152	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
153	if (sol_reg)
154	return 0;
155
156	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
157	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
158	0x80000000, 0x80000000, false);
159	if (ret)
160	return ret;
161
162	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
163
164	/* Copy PSP System Driver binary to memory */
165	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
166
167	/* Provide the sys driver to bootrom */
168	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
169	(uint32_t)(psp->fw_pri_mc_addr >> 20));
170	psp_gfxdrv_command_reg = 1 << 16;
171	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
172	psp_gfxdrv_command_reg);
173
174	/* there might be handshake issue with hardware which needs delay */
175	mdelay(20);
176
177	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
178	0x80000000, 0x80000000, false);
179
180	return ret;
181	}
182
183	static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
184	{
185	int ret;
186	unsigned int psp_gfxdrv_command_reg = 0;
187	struct amdgpu_device *adev = psp->adev;
188	uint32_t sol_reg;
189
190	/* Check sOS sign of life register to confirm sys driver and sOS
191	* are already been loaded.
192	*/
193	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
194	if (sol_reg)
195	return 0;
196
197	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
198	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
199	0x80000000, 0x80000000, false);
200	if (ret)
201	return ret;
202
203	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
204
205	/* Copy Secure OS binary to PSP memory */
206	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
207
208	/* Provide the PSP secure OS to bootrom */
209	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
210	(uint32_t)(psp->fw_pri_mc_addr >> 20));
211	psp_gfxdrv_command_reg = 2 << 16;
212	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
213	psp_gfxdrv_command_reg);
214
215	/* there might be handshake issue with hardware which needs delay */
216	mdelay(20);
217	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
218	RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
219	0, true);
220
221	return ret;
222	}
223
224	static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
225	struct psp_gfx_cmd_resp *cmd)
226	{
227	int ret;
228	uint64_t fw_mem_mc_addr = ucode->mc_addr;
229
230	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
231
232	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
233	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
234	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
235	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
236
237	ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
238	if (ret)
239	DRM_ERROR("Unknown firmware type\n");
240
241	return ret;
242	}
243
244	static int psp_v11_0_ring_init(struct psp_context *psp,
245	enum psp_ring_type ring_type)
246	{
247	int ret = 0;
248	struct psp_ring *ring;
249	struct amdgpu_device *adev = psp->adev;
250
251	ring = &psp->km_ring;
252
253	ring->ring_type = ring_type;
254
255	/* allocate 4k Page of Local Frame Buffer memory for ring */
256	ring->ring_size = 0x1000;
257	ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
258	AMDGPU_GEM_DOMAIN_VRAM,
259	&adev->firmware.rbuf,
260	&ring->ring_mem_mc_addr,
261	(void **)&ring->ring_mem);
262	if (ret) {
263	ring->ring_size = 0;
264	return ret;
265	}
266
267	return 0;
268	}
269
270	static int psp_v11_0_ring_create(struct psp_context *psp,
271	enum psp_ring_type ring_type)
272	{
273	int ret = 0;
274	unsigned int psp_ring_reg = 0;
275	struct psp_ring *ring = &psp->km_ring;
276	struct amdgpu_device *adev = psp->adev;
277
278	/* Write low address of the ring to C2PMSG_69 */
279	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
280	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
281	/* Write high address of the ring to C2PMSG_70 */
282	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
283	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
284	/* Write size of ring to C2PMSG_71 */
285	psp_ring_reg = ring->ring_size;
286	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
287	/* Write the ring initialization command to C2PMSG_64 */
288	psp_ring_reg = ring_type;
289	psp_ring_reg = psp_ring_reg << 16;
290	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
291
292	/* there might be handshake issue with hardware which needs delay */
293	mdelay(20);
294
295	/* Wait for response flag (bit 31) in C2PMSG_64 */
296	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
297	0x80000000, 0x8000FFFF, false);
298
299	return ret;
300	}
301
302	static int psp_v11_0_ring_stop(struct psp_context *psp,
303	enum psp_ring_type ring_type)
304	{
305	int ret = 0;
306	struct psp_ring *ring;
307	struct amdgpu_device *adev = psp->adev;
308
309	ring = &psp->km_ring;
310
311	/* Write the ring destroy command to C2PMSG_64 */
312	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS);
313
314	/* there might be handshake issue with hardware which needs delay */
315	mdelay(20);
316
317	/* Wait for response flag (bit 31) in C2PMSG_64 */
318	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
319	0x80000000, 0x80000000, false);
320
321	return ret;
322	}
323
324	static int psp_v11_0_ring_destroy(struct psp_context *psp,
325	enum psp_ring_type ring_type)
326	{
327	int ret = 0;
328	struct psp_ring *ring = &psp->km_ring;
329	struct amdgpu_device *adev = psp->adev;
330
331	ret = psp_v11_0_ring_stop(psp, ring_type);
332	if (ret)
333	DRM_ERROR("Fail to stop psp ring\n");
334
335	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
336	&ring->ring_mem_mc_addr,
337	(void **)&ring->ring_mem);
338
339	return ret;
340	}
341
342	static int psp_v11_0_cmd_submit(struct psp_context *psp,
343	struct amdgpu_firmware_info *ucode,
344	uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
345	int index)
346	{
347	unsigned int psp_write_ptr_reg = 0;
348	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
349	struct psp_ring *ring = &psp->km_ring;
350	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
351	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
352	ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
353	struct amdgpu_device *adev = psp->adev;
354	uint32_t ring_size_dw = ring->ring_size / 4;
355	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
356
357	/* KM (GPCOM) prepare write pointer */
358	psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
359
360	/* Update KM RB frame pointer to new frame */
361	/* write_frame ptr increments by size of rb_frame in bytes */
362	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
363	if ((psp_write_ptr_reg % ring_size_dw) == 0)
364	write_frame = ring_buffer_start;
365	else
366	write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
367	/* Check invalid write_frame ptr address */
368	if ((write_frame < ring_buffer_start) \|\| (ring_buffer_end < write_frame)) {
369	DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
370	ring_buffer_start, ring_buffer_end, write_frame);
371	DRM_ERROR("write_frame is pointing to address out of bounds\n");
372	return -EINVAL;
373	}
374
375	/* Initialize KM RB frame */
376	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
377
378	/* Update KM RB frame */
379	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
380	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
381	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
382	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
383	write_frame->fence_value = index;
384
385	/* Update the write Pointer in DWORDs */
386	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
387	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
388
389	return 0;
390	}
391
392	static int
393	psp_v11_0_sram_map(struct amdgpu_device *adev,
394	unsigned int sram_offset, unsigned int sram_addr_reg_offset,
395	unsigned int *sram_data_reg_offset,
396	enum AMDGPU_UCODE_ID ucode_id)
397	{
398	int ret = 0;
399
400	switch (ucode_id) {
401	/* TODO: needs to confirm */
402	#if 0
403	case AMDGPU_UCODE_ID_SMC:
404	*sram_offset = 0;
405	*sram_addr_reg_offset = 0;
406	*sram_data_reg_offset = 0;
407	break;
408	#endif
409
410	case AMDGPU_UCODE_ID_CP_CE:
411	*sram_offset = 0x0;
412	*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
413	*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
414	break;
415
416	case AMDGPU_UCODE_ID_CP_PFP:
417	*sram_offset = 0x0;
418	*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
419	*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
420	break;
421
422	case AMDGPU_UCODE_ID_CP_ME:
423	*sram_offset = 0x0;
424	*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
425	*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
426	break;
427
428	case AMDGPU_UCODE_ID_CP_MEC1:
429	*sram_offset = 0x10000;
430	*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
431	*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
432	break;
433
434	case AMDGPU_UCODE_ID_CP_MEC2:
435	*sram_offset = 0x10000;
436	*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
437	*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
438	break;
439
440	case AMDGPU_UCODE_ID_RLC_G:
441	*sram_offset = 0x2000;
442	*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
443	*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
444	break;
445
446	case AMDGPU_UCODE_ID_SDMA0:
447	*sram_offset = 0x0;
448	*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
449	*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
450	break;
451
452	/* TODO: needs to confirm */
453	#if 0
454	case AMDGPU_UCODE_ID_SDMA1:
455	*sram_offset = ;
456	*sram_addr_reg_offset = ;
457	break;
458
459	case AMDGPU_UCODE_ID_UVD:
460	*sram_offset = ;
461	*sram_addr_reg_offset = ;
462	break;
463
464	case AMDGPU_UCODE_ID_VCE:
465	*sram_offset = ;
466	*sram_addr_reg_offset = ;
467	break;
468	#endif
469
470	case AMDGPU_UCODE_ID_MAXIMUM:
471	default:
472	ret = -EINVAL;
473	break;
474	}
475
476	return ret;
477	}
478
479	static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
480	struct amdgpu_firmware_info *ucode,
481	enum AMDGPU_UCODE_ID ucode_type)
482	{
483	int err = 0;
484	unsigned int fw_sram_reg_val = 0;
485	unsigned int fw_sram_addr_reg_offset = 0;
486	unsigned int fw_sram_data_reg_offset = 0;
487	unsigned int ucode_size;
488	uint32_t *ucode_mem = NULL;
489	struct amdgpu_device *adev = psp->adev;
490
491	err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
492	&fw_sram_data_reg_offset, ucode_type);
493	if (err)
494	return false;
495
496	WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
497
498	ucode_size = ucode->ucode_size;
499	ucode_mem = (uint32_t *)ucode->kaddr;
500	while (ucode_size) {
501	fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
502
503	if (*ucode_mem != fw_sram_reg_val)
504	return false;
505
506	ucode_mem++;
507	/* 4 bytes */
508	ucode_size -= 4;
509	}
510
511	return true;
512	}
513
514	static int psp_v11_0_mode1_reset(struct psp_context *psp)
515	{
516	int ret;
517	uint32_t offset;
518	struct amdgpu_device *adev = psp->adev;
519
520	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
521
522	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
523
524	if (ret) {
525	DRM_INFO("psp is not working correctly before mode1 reset!\n");
526	return -EINVAL;
527	}
528
529	/send the mode 1 reset command/
530	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
531
532	mdelay(1000);
533
534	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
535
536	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
537
538	if (ret) {
539	DRM_INFO("psp mode 1 reset failed!\n");
540	return -EINVAL;
541	}
542
543	DRM_INFO("psp mode1 reset succeed \n");
544
545	return 0;
546	}
547
548	static const struct psp_funcs psp_v11_0_funcs = {
549	.init_microcode = psp_v11_0_init_microcode,
550	.bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
551	.bootloader_load_sos = psp_v11_0_bootloader_load_sos,
552	.prep_cmd_buf = psp_v11_0_prep_cmd_buf,
553	.ring_init = psp_v11_0_ring_init,
554	.ring_create = psp_v11_0_ring_create,
555	.ring_stop = psp_v11_0_ring_stop,
556	.ring_destroy = psp_v11_0_ring_destroy,
557	.cmd_submit = psp_v11_0_cmd_submit,
558	.compare_sram_data = psp_v11_0_compare_sram_data,
559	.mode1_reset = psp_v11_0_mode1_reset,
560	};
561
562	void psp_v11_0_set_psp_funcs(struct psp_context *psp)
563	{
564	psp->funcs = &psp_v11_0_funcs;
565	}