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654f761c FX |
1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include <linux/firmware.h> | |
f867723b SR |
24 | #include <linux/module.h> |
25 | ||
654f761c FX |
26 | #include "amdgpu.h" |
27 | #include "amdgpu_psp.h" | |
28 | #include "amdgpu_ucode.h" | |
29 | #include "soc15_common.h" | |
30 | #include "psp_v11_0.h" | |
31 | ||
32 | #include "mp/mp_11_0_offset.h" | |
33 | #include "mp/mp_11_0_sh_mask.h" | |
34 | #include "gc/gc_9_0_offset.h" | |
35 | #include "sdma0/sdma0_4_0_offset.h" | |
36 | #include "nbio/nbio_7_4_offset.h" | |
37 | ||
b849aaa4 CK |
38 | #include "oss/osssys_4_0_offset.h" |
39 | #include "oss/osssys_4_0_sh_mask.h" | |
40 | ||
654f761c | 41 | MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); |
06d6370e | 42 | MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); |
51e7177f | 43 | MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); |
bc290fe5 | 44 | MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); |
a698faf8 | 45 | MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); |
82522b2d | 46 | MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); |
8687b47e | 47 | MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); |
739cdbd6 XY |
48 | MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); |
49 | MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); | |
f36d9ab9 JC |
50 | MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); |
51 | MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); | |
4fb60b02 | 52 | MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); |
654f761c FX |
53 | |
54 | /* address block */ | |
55 | #define smnMP1_FIRMWARE_FLAGS 0x3010024 | |
bc290fe5 TZ |
56 | /* navi10 reg offset define */ |
57 | #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 | |
58 | #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 | |
59 | #define mmSDMA0_UCODE_ADDR_NV10 0x5880 | |
60 | #define mmSDMA0_UCODE_DATA_NV10 0x5881 | |
654f761c | 61 | |
654f761c FX |
62 | static int psp_v11_0_init_microcode(struct psp_context *psp) |
63 | { | |
64 | struct amdgpu_device *adev = psp->adev; | |
65 | const char *chip_name; | |
66 | char fw_name[30]; | |
67 | int err = 0; | |
51e7177f | 68 | const struct psp_firmware_header_v1_0 *sos_hdr; |
93d8f222 | 69 | const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; |
dc0d9622 | 70 | const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; |
06d6370e | 71 | const struct psp_firmware_header_v1_0 *asd_hdr; |
51e7177f | 72 | const struct ta_firmware_header_v1_0 *ta_hdr; |
654f761c FX |
73 | |
74 | DRM_DEBUG("\n"); | |
75 | ||
76 | switch (adev->asic_type) { | |
77 | case CHIP_VEGA20: | |
78 | chip_name = "vega20"; | |
79 | break; | |
bc290fe5 TZ |
80 | case CHIP_NAVI10: |
81 | chip_name = "navi10"; | |
82 | break; | |
82522b2d XY |
83 | case CHIP_NAVI14: |
84 | chip_name = "navi14"; | |
85 | break; | |
739cdbd6 XY |
86 | case CHIP_NAVI12: |
87 | chip_name = "navi12"; | |
88 | break; | |
dc0d9622 JC |
89 | case CHIP_ARCTURUS: |
90 | chip_name = "arcturus"; | |
91 | break; | |
654f761c FX |
92 | default: |
93 | BUG(); | |
94 | } | |
95 | ||
96 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); | |
97 | err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); | |
98 | if (err) | |
99 | goto out; | |
100 | ||
101 | err = amdgpu_ucode_validate(adev->psp.sos_fw); | |
102 | if (err) | |
103 | goto out; | |
104 | ||
51e7177f | 105 | sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; |
37e91918 | 106 | amdgpu_ucode_print_psp_hdr(&sos_hdr->header); |
93d8f222 HZ |
107 | |
108 | switch (sos_hdr->header.header_version_major) { | |
109 | case 1: | |
110 | adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); | |
111 | adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); | |
112 | adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); | |
5160709d | 113 | adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); |
93d8f222 | 114 | adev->psp.sys_start_addr = (uint8_t *)sos_hdr + |
51e7177f | 115 | le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); |
93d8f222 | 116 | adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + |
51e7177f | 117 | le32_to_cpu(sos_hdr->sos_offset_bytes); |
93d8f222 HZ |
118 | if (sos_hdr->header.header_version_minor == 1) { |
119 | sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; | |
120 | adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); | |
121 | adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + | |
122 | le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); | |
42989359 HZ |
123 | adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); |
124 | adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + | |
125 | le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); | |
93d8f222 | 126 | } |
dc0d9622 JC |
127 | if (sos_hdr->header.header_version_minor == 2) { |
128 | sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; | |
129 | adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); | |
130 | adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + | |
131 | le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); | |
132 | } | |
93d8f222 HZ |
133 | break; |
134 | default: | |
135 | dev_err(adev->dev, | |
136 | "Unsupported psp sos firmware\n"); | |
137 | err = -EINVAL; | |
138 | goto out; | |
139 | } | |
51e7177f | 140 | |
06d6370e EQ |
141 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); |
142 | err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); | |
143 | if (err) | |
144 | goto out1; | |
145 | ||
146 | err = amdgpu_ucode_validate(adev->psp.asd_fw); | |
147 | if (err) | |
148 | goto out1; | |
149 | ||
150 | asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; | |
151 | adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); | |
152 | adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); | |
153 | adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); | |
154 | adev->psp.asd_start_addr = (uint8_t *)asd_hdr + | |
155 | le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); | |
156 | ||
a954f3ff HZ |
157 | switch (adev->asic_type) { |
158 | case CHIP_VEGA20: | |
4fb60b02 | 159 | case CHIP_ARCTURUS: |
a954f3ff HZ |
160 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); |
161 | err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); | |
162 | if (err) { | |
163 | release_firmware(adev->psp.ta_fw); | |
164 | adev->psp.ta_fw = NULL; | |
165 | dev_info(adev->dev, | |
166 | "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); | |
167 | } else { | |
168 | err = amdgpu_ucode_validate(adev->psp.ta_fw); | |
169 | if (err) | |
170 | goto out2; | |
171 | ||
172 | ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; | |
173 | adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); | |
174 | adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); | |
175 | adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + | |
176 | le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); | |
177 | adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); | |
178 | adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); | |
179 | adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); | |
180 | adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + | |
181 | le32_to_cpu(ta_hdr->ta_ras_offset_bytes); | |
182 | } | |
183 | break; | |
184 | case CHIP_NAVI10: | |
e470d287 | 185 | case CHIP_NAVI14: |
739cdbd6 | 186 | case CHIP_NAVI12: |
a954f3ff HZ |
187 | break; |
188 | default: | |
189 | BUG(); | |
1d69511e | 190 | } |
51e7177f | 191 | |
654f761c | 192 | return 0; |
06d6370e EQ |
193 | |
194 | out2: | |
195 | release_firmware(adev->psp.ta_fw); | |
196 | adev->psp.ta_fw = NULL; | |
197 | out1: | |
198 | release_firmware(adev->psp.asd_fw); | |
199 | adev->psp.asd_fw = NULL; | |
654f761c | 200 | out: |
06d6370e EQ |
201 | dev_err(adev->dev, |
202 | "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); | |
203 | release_firmware(adev->psp.sos_fw); | |
204 | adev->psp.sos_fw = NULL; | |
654f761c FX |
205 | |
206 | return err; | |
207 | } | |
208 | ||
a7d4c920 TY |
209 | static bool psp_v11_0_is_sos_alive(struct psp_context *psp) |
210 | { | |
211 | struct amdgpu_device *adev = psp->adev; | |
212 | uint32_t sol_reg; | |
213 | ||
214 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
215 | ||
216 | return sol_reg != 0x0; | |
217 | } | |
218 | ||
42989359 HZ |
219 | static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) |
220 | { | |
221 | int ret; | |
222 | uint32_t psp_gfxdrv_command_reg = 0; | |
223 | struct amdgpu_device *adev = psp->adev; | |
42989359 HZ |
224 | |
225 | /* Check tOS sign of life register to confirm sys driver and sOS | |
226 | * are already been loaded. | |
227 | */ | |
a7d4c920 | 228 | if (psp_v11_0_is_sos_alive(psp)) { |
42989359 HZ |
229 | psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); |
230 | dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); | |
231 | return 0; | |
232 | } | |
233 | ||
234 | /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ | |
235 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
236 | 0x80000000, 0x80000000, false); | |
237 | if (ret) | |
238 | return ret; | |
239 | ||
240 | memset(psp->fw_pri_buf, 0, PSP_1_MEG); | |
241 | ||
242 | /* Copy PSP KDB binary to memory */ | |
243 | memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); | |
244 | ||
245 | /* Provide the sys driver to bootloader */ | |
246 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, | |
247 | (uint32_t)(psp->fw_pri_mc_addr >> 20)); | |
248 | psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; | |
249 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, | |
250 | psp_gfxdrv_command_reg); | |
251 | ||
252 | /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1*/ | |
253 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
254 | 0x80000000, 0x80000000, false); | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
654f761c FX |
259 | static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) |
260 | { | |
261 | int ret; | |
262 | uint32_t psp_gfxdrv_command_reg = 0; | |
263 | struct amdgpu_device *adev = psp->adev; | |
654f761c FX |
264 | |
265 | /* Check sOS sign of life register to confirm sys driver and sOS | |
266 | * are already been loaded. | |
267 | */ | |
a7d4c920 | 268 | if (psp_v11_0_is_sos_alive(psp)) { |
d63cda5b | 269 | psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); |
42989359 | 270 | dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); |
654f761c | 271 | return 0; |
d63cda5b | 272 | } |
654f761c FX |
273 | |
274 | /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ | |
275 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
276 | 0x80000000, 0x80000000, false); | |
277 | if (ret) | |
278 | return ret; | |
279 | ||
280 | memset(psp->fw_pri_buf, 0, PSP_1_MEG); | |
281 | ||
282 | /* Copy PSP System Driver binary to memory */ | |
283 | memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); | |
284 | ||
548f2ecc | 285 | /* Provide the sys driver to bootloader */ |
654f761c FX |
286 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, |
287 | (uint32_t)(psp->fw_pri_mc_addr >> 20)); | |
3840fe25 | 288 | psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; |
654f761c FX |
289 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, |
290 | psp_gfxdrv_command_reg); | |
291 | ||
292 | /* there might be handshake issue with hardware which needs delay */ | |
293 | mdelay(20); | |
294 | ||
295 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
296 | 0x80000000, 0x80000000, false); | |
297 | ||
298 | return ret; | |
299 | } | |
300 | ||
301 | static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) | |
302 | { | |
303 | int ret; | |
304 | unsigned int psp_gfxdrv_command_reg = 0; | |
305 | struct amdgpu_device *adev = psp->adev; | |
654f761c FX |
306 | |
307 | /* Check sOS sign of life register to confirm sys driver and sOS | |
308 | * are already been loaded. | |
309 | */ | |
a7d4c920 | 310 | if (psp_v11_0_is_sos_alive(psp)) |
654f761c FX |
311 | return 0; |
312 | ||
313 | /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ | |
314 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), | |
315 | 0x80000000, 0x80000000, false); | |
316 | if (ret) | |
317 | return ret; | |
318 | ||
319 | memset(psp->fw_pri_buf, 0, PSP_1_MEG); | |
320 | ||
321 | /* Copy Secure OS binary to PSP memory */ | |
322 | memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); | |
323 | ||
548f2ecc | 324 | /* Provide the PSP secure OS to bootloader */ |
654f761c FX |
325 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, |
326 | (uint32_t)(psp->fw_pri_mc_addr >> 20)); | |
3840fe25 | 327 | psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; |
654f761c FX |
328 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, |
329 | psp_gfxdrv_command_reg); | |
330 | ||
331 | /* there might be handshake issue with hardware which needs delay */ | |
332 | mdelay(20); | |
333 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), | |
334 | RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), | |
335 | 0, true); | |
336 | ||
337 | return ret; | |
338 | } | |
339 | ||
b849aaa4 CK |
340 | static void psp_v11_0_reroute_ih(struct psp_context *psp) |
341 | { | |
342 | struct amdgpu_device *adev = psp->adev; | |
343 | uint32_t tmp; | |
344 | ||
345 | /* Change IH ring for VMC */ | |
346 | tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); | |
347 | tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); | |
348 | tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); | |
349 | ||
350 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); | |
351 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); | |
352 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); | |
353 | ||
354 | mdelay(20); | |
355 | psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), | |
356 | 0x80000000, 0x8000FFFF, false); | |
357 | ||
358 | /* Change IH ring for UMC */ | |
359 | tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); | |
360 | tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); | |
361 | ||
362 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); | |
363 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); | |
364 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); | |
365 | ||
366 | mdelay(20); | |
367 | psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), | |
368 | 0x80000000, 0x8000FFFF, false); | |
369 | } | |
370 | ||
654f761c FX |
371 | static int psp_v11_0_ring_init(struct psp_context *psp, |
372 | enum psp_ring_type ring_type) | |
373 | { | |
374 | int ret = 0; | |
375 | struct psp_ring *ring; | |
376 | struct amdgpu_device *adev = psp->adev; | |
377 | ||
b849aaa4 CK |
378 | psp_v11_0_reroute_ih(psp); |
379 | ||
654f761c FX |
380 | ring = &psp->km_ring; |
381 | ||
382 | ring->ring_type = ring_type; | |
383 | ||
384 | /* allocate 4k Page of Local Frame Buffer memory for ring */ | |
385 | ring->ring_size = 0x1000; | |
386 | ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, | |
387 | AMDGPU_GEM_DOMAIN_VRAM, | |
388 | &adev->firmware.rbuf, | |
389 | &ring->ring_mem_mc_addr, | |
390 | (void **)&ring->ring_mem); | |
391 | if (ret) { | |
392 | ring->ring_size = 0; | |
393 | return ret; | |
394 | } | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
e27a73d1 ED |
399 | static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) |
400 | { | |
401 | if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) | |
402 | return true; | |
403 | return false; | |
404 | } | |
405 | ||
51c0f58e JZ |
406 | static int psp_v11_0_ring_stop(struct psp_context *psp, |
407 | enum psp_ring_type ring_type) | |
408 | { | |
409 | int ret = 0; | |
410 | struct amdgpu_device *adev = psp->adev; | |
411 | ||
412 | /* Write the ring destroy command*/ | |
413 | if (psp_v11_0_support_vmr_ring(psp)) | |
414 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, | |
415 | GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); | |
416 | else | |
417 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, | |
418 | GFX_CTRL_CMD_ID_DESTROY_RINGS); | |
419 | ||
420 | /* there might be handshake issue with hardware which needs delay */ | |
421 | mdelay(20); | |
422 | ||
423 | /* Wait for response flag (bit 31) */ | |
424 | if (psp_v11_0_support_vmr_ring(psp)) | |
425 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), | |
426 | 0x80000000, 0x80000000, false); | |
427 | else | |
428 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), | |
429 | 0x80000000, 0x80000000, false); | |
430 | ||
431 | return ret; | |
432 | } | |
433 | ||
654f761c FX |
434 | static int psp_v11_0_ring_create(struct psp_context *psp, |
435 | enum psp_ring_type ring_type) | |
436 | { | |
437 | int ret = 0; | |
438 | unsigned int psp_ring_reg = 0; | |
439 | struct psp_ring *ring = &psp->km_ring; | |
440 | struct amdgpu_device *adev = psp->adev; | |
441 | ||
e27a73d1 | 442 | if (psp_v11_0_support_vmr_ring(psp)) { |
51c0f58e JZ |
443 | ret = psp_v11_0_ring_stop(psp, ring_type); |
444 | if (ret) { | |
445 | DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); | |
446 | return ret; | |
447 | } | |
448 | ||
5ec996df XY |
449 | /* Write low address of the ring to C2PMSG_102 */ |
450 | psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); | |
451 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); | |
452 | /* Write high address of the ring to C2PMSG_103 */ | |
453 | psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); | |
454 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); | |
455 | ||
456 | /* Write the ring initialization command to C2PMSG_101 */ | |
457 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, | |
458 | GFX_CTRL_CMD_ID_INIT_GPCOM_RING); | |
459 | ||
460 | /* there might be handshake issue with hardware which needs delay */ | |
461 | mdelay(20); | |
462 | ||
463 | /* Wait for response flag (bit 31) in C2PMSG_101 */ | |
464 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), | |
465 | 0x80000000, 0x8000FFFF, false); | |
466 | ||
467 | } else { | |
468 | /* Write low address of the ring to C2PMSG_69 */ | |
469 | psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); | |
470 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); | |
471 | /* Write high address of the ring to C2PMSG_70 */ | |
472 | psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); | |
473 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); | |
474 | /* Write size of ring to C2PMSG_71 */ | |
475 | psp_ring_reg = ring->ring_size; | |
476 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); | |
477 | /* Write the ring initialization command to C2PMSG_64 */ | |
478 | psp_ring_reg = ring_type; | |
479 | psp_ring_reg = psp_ring_reg << 16; | |
480 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); | |
481 | ||
482 | /* there might be handshake issue with hardware which needs delay */ | |
483 | mdelay(20); | |
484 | ||
485 | /* Wait for response flag (bit 31) in C2PMSG_64 */ | |
486 | ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), | |
487 | 0x80000000, 0x8000FFFF, false); | |
488 | } | |
654f761c FX |
489 | |
490 | return ret; | |
491 | } | |
492 | ||
654f761c FX |
493 | |
494 | static int psp_v11_0_ring_destroy(struct psp_context *psp, | |
495 | enum psp_ring_type ring_type) | |
496 | { | |
497 | int ret = 0; | |
498 | struct psp_ring *ring = &psp->km_ring; | |
499 | struct amdgpu_device *adev = psp->adev; | |
500 | ||
501 | ret = psp_v11_0_ring_stop(psp, ring_type); | |
502 | if (ret) | |
503 | DRM_ERROR("Fail to stop psp ring\n"); | |
504 | ||
505 | amdgpu_bo_free_kernel(&adev->firmware.rbuf, | |
506 | &ring->ring_mem_mc_addr, | |
507 | (void **)&ring->ring_mem); | |
508 | ||
509 | return ret; | |
510 | } | |
511 | ||
512 | static int psp_v11_0_cmd_submit(struct psp_context *psp, | |
654f761c FX |
513 | uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, |
514 | int index) | |
515 | { | |
516 | unsigned int psp_write_ptr_reg = 0; | |
517 | struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; | |
518 | struct psp_ring *ring = &psp->km_ring; | |
519 | struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; | |
520 | struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + | |
521 | ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; | |
522 | struct amdgpu_device *adev = psp->adev; | |
523 | uint32_t ring_size_dw = ring->ring_size / 4; | |
524 | uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; | |
525 | ||
526 | /* KM (GPCOM) prepare write pointer */ | |
e27a73d1 | 527 | if (psp_v11_0_support_vmr_ring(psp)) |
5ec996df XY |
528 | psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); |
529 | else | |
530 | psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); | |
654f761c FX |
531 | |
532 | /* Update KM RB frame pointer to new frame */ | |
533 | /* write_frame ptr increments by size of rb_frame in bytes */ | |
534 | /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ | |
535 | if ((psp_write_ptr_reg % ring_size_dw) == 0) | |
536 | write_frame = ring_buffer_start; | |
537 | else | |
538 | write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); | |
539 | /* Check invalid write_frame ptr address */ | |
540 | if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { | |
541 | DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", | |
542 | ring_buffer_start, ring_buffer_end, write_frame); | |
543 | DRM_ERROR("write_frame is pointing to address out of bounds\n"); | |
544 | return -EINVAL; | |
545 | } | |
546 | ||
547 | /* Initialize KM RB frame */ | |
548 | memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); | |
549 | ||
550 | /* Update KM RB frame */ | |
551 | write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); | |
552 | write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); | |
553 | write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); | |
554 | write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); | |
555 | write_frame->fence_value = index; | |
e8186eec | 556 | amdgpu_asic_flush_hdp(adev, NULL); |
654f761c FX |
557 | |
558 | /* Update the write Pointer in DWORDs */ | |
559 | psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; | |
e27a73d1 | 560 | if (psp_v11_0_support_vmr_ring(psp)) { |
5ec996df XY |
561 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); |
562 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); | |
563 | } else | |
564 | WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); | |
654f761c FX |
565 | |
566 | return 0; | |
567 | } | |
568 | ||
569 | static int | |
570 | psp_v11_0_sram_map(struct amdgpu_device *adev, | |
571 | unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, | |
572 | unsigned int *sram_data_reg_offset, | |
573 | enum AMDGPU_UCODE_ID ucode_id) | |
574 | { | |
575 | int ret = 0; | |
576 | ||
577 | switch (ucode_id) { | |
578 | /* TODO: needs to confirm */ | |
579 | #if 0 | |
580 | case AMDGPU_UCODE_ID_SMC: | |
581 | *sram_offset = 0; | |
582 | *sram_addr_reg_offset = 0; | |
583 | *sram_data_reg_offset = 0; | |
584 | break; | |
585 | #endif | |
586 | ||
587 | case AMDGPU_UCODE_ID_CP_CE: | |
588 | *sram_offset = 0x0; | |
589 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); | |
590 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); | |
591 | break; | |
592 | ||
593 | case AMDGPU_UCODE_ID_CP_PFP: | |
594 | *sram_offset = 0x0; | |
595 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); | |
596 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); | |
597 | break; | |
598 | ||
599 | case AMDGPU_UCODE_ID_CP_ME: | |
600 | *sram_offset = 0x0; | |
601 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); | |
602 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); | |
603 | break; | |
604 | ||
605 | case AMDGPU_UCODE_ID_CP_MEC1: | |
606 | *sram_offset = 0x10000; | |
607 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); | |
608 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); | |
609 | break; | |
610 | ||
611 | case AMDGPU_UCODE_ID_CP_MEC2: | |
612 | *sram_offset = 0x10000; | |
613 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); | |
614 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); | |
615 | break; | |
616 | ||
617 | case AMDGPU_UCODE_ID_RLC_G: | |
618 | *sram_offset = 0x2000; | |
173da95d | 619 | if (adev->asic_type < CHIP_NAVI10) { |
bc290fe5 TZ |
620 | *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); |
621 | *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); | |
622 | } else { | |
623 | *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; | |
624 | *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; | |
625 | } | |
654f761c FX |
626 | break; |
627 | ||
628 | case AMDGPU_UCODE_ID_SDMA0: | |
629 | *sram_offset = 0x0; | |
173da95d | 630 | if (adev->asic_type < CHIP_NAVI10) { |
bc290fe5 TZ |
631 | *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); |
632 | *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); | |
633 | } else { | |
634 | *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; | |
635 | *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; | |
636 | } | |
654f761c FX |
637 | break; |
638 | ||
639 | /* TODO: needs to confirm */ | |
640 | #if 0 | |
641 | case AMDGPU_UCODE_ID_SDMA1: | |
642 | *sram_offset = ; | |
643 | *sram_addr_reg_offset = ; | |
644 | break; | |
645 | ||
646 | case AMDGPU_UCODE_ID_UVD: | |
647 | *sram_offset = ; | |
648 | *sram_addr_reg_offset = ; | |
649 | break; | |
650 | ||
651 | case AMDGPU_UCODE_ID_VCE: | |
652 | *sram_offset = ; | |
653 | *sram_addr_reg_offset = ; | |
654 | break; | |
655 | #endif | |
656 | ||
657 | case AMDGPU_UCODE_ID_MAXIMUM: | |
658 | default: | |
659 | ret = -EINVAL; | |
660 | break; | |
661 | } | |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
666 | static bool psp_v11_0_compare_sram_data(struct psp_context *psp, | |
667 | struct amdgpu_firmware_info *ucode, | |
668 | enum AMDGPU_UCODE_ID ucode_type) | |
669 | { | |
670 | int err = 0; | |
671 | unsigned int fw_sram_reg_val = 0; | |
672 | unsigned int fw_sram_addr_reg_offset = 0; | |
673 | unsigned int fw_sram_data_reg_offset = 0; | |
674 | unsigned int ucode_size; | |
675 | uint32_t *ucode_mem = NULL; | |
676 | struct amdgpu_device *adev = psp->adev; | |
677 | ||
678 | err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, | |
679 | &fw_sram_data_reg_offset, ucode_type); | |
680 | if (err) | |
681 | return false; | |
682 | ||
683 | WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); | |
684 | ||
685 | ucode_size = ucode->ucode_size; | |
686 | ucode_mem = (uint32_t *)ucode->kaddr; | |
687 | while (ucode_size) { | |
688 | fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); | |
689 | ||
690 | if (*ucode_mem != fw_sram_reg_val) | |
691 | return false; | |
692 | ||
693 | ucode_mem++; | |
694 | /* 4 bytes */ | |
695 | ucode_size -= 4; | |
696 | } | |
697 | ||
698 | return true; | |
699 | } | |
700 | ||
701 | static int psp_v11_0_mode1_reset(struct psp_context *psp) | |
702 | { | |
703 | int ret; | |
704 | uint32_t offset; | |
705 | struct amdgpu_device *adev = psp->adev; | |
706 | ||
707 | offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); | |
708 | ||
709 | ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); | |
710 | ||
711 | if (ret) { | |
712 | DRM_INFO("psp is not working correctly before mode1 reset!\n"); | |
713 | return -EINVAL; | |
714 | } | |
715 | ||
716 | /*send the mode 1 reset command*/ | |
717 | WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); | |
718 | ||
38cd8a28 | 719 | msleep(500); |
654f761c FX |
720 | |
721 | offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); | |
722 | ||
723 | ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); | |
724 | ||
725 | if (ret) { | |
726 | DRM_INFO("psp mode 1 reset failed!\n"); | |
727 | return -EINVAL; | |
728 | } | |
729 | ||
730 | DRM_INFO("psp mode1 reset succeed \n"); | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
78122127 SL |
735 | /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. |
736 | * For now, return success and hack the hive_id so high level code can | |
737 | * start testing | |
738 | */ | |
739 | static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, | |
740 | int number_devices, struct psp_xgmi_topology_info *topology) | |
741 | { | |
ec1a975e HZ |
742 | struct ta_xgmi_shared_memory *xgmi_cmd; |
743 | struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; | |
744 | struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; | |
745 | int i; | |
746 | int ret; | |
747 | ||
748 | if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) | |
749 | return -EINVAL; | |
750 | ||
751 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
752 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
753 | ||
754 | /* Fill in the shared memory with topology information as input */ | |
755 | topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; | |
756 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; | |
757 | topology_info_input->num_nodes = number_devices; | |
758 | ||
759 | for (i = 0; i < topology_info_input->num_nodes; i++) { | |
760 | topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; | |
761 | topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; | |
762 | topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; | |
763 | topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; | |
764 | } | |
765 | ||
766 | /* Invoke xgmi ta to get the topology information */ | |
767 | ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); | |
768 | if (ret) | |
769 | return ret; | |
770 | ||
771 | /* Read the output topology information from the shared memory */ | |
772 | topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; | |
773 | topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; | |
774 | for (i = 0; i < topology->num_nodes; i++) { | |
775 | topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; | |
776 | topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; | |
777 | topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; | |
778 | topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; | |
779 | } | |
780 | ||
78122127 SL |
781 | return 0; |
782 | } | |
783 | ||
784 | static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, | |
785 | int number_devices, struct psp_xgmi_topology_info *topology) | |
786 | { | |
bb8310cc HZ |
787 | struct ta_xgmi_shared_memory *xgmi_cmd; |
788 | struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; | |
789 | int i; | |
790 | ||
791 | if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) | |
792 | return -EINVAL; | |
793 | ||
794 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
795 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
796 | ||
797 | topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; | |
798 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; | |
799 | topology_info_input->num_nodes = number_devices; | |
800 | ||
801 | for (i = 0; i < topology_info_input->num_nodes; i++) { | |
802 | topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; | |
803 | topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; | |
b0960c35 | 804 | topology_info_input->nodes[i].is_sharing_enabled = 1; |
bb8310cc HZ |
805 | topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; |
806 | } | |
807 | ||
808 | /* Invoke xgmi ta to set topology information */ | |
809 | return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); | |
78122127 SL |
810 | } |
811 | ||
379c237e | 812 | static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) |
78122127 | 813 | { |
4b93151f HZ |
814 | struct ta_xgmi_shared_memory *xgmi_cmd; |
815 | int ret; | |
816 | ||
817 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
818 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
78122127 | 819 | |
4b93151f | 820 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; |
78122127 | 821 | |
4b93151f HZ |
822 | /* Invoke xgmi ta to get hive id */ |
823 | ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); | |
824 | if (ret) | |
379c237e EQ |
825 | return ret; |
826 | ||
827 | *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; | |
828 | ||
829 | return 0; | |
78122127 SL |
830 | } |
831 | ||
379c237e | 832 | static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) |
dd3c45d3 HZ |
833 | { |
834 | struct ta_xgmi_shared_memory *xgmi_cmd; | |
835 | int ret; | |
836 | ||
837 | xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; | |
838 | memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); | |
839 | ||
840 | xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; | |
841 | ||
842 | /* Invoke xgmi ta to get the node id */ | |
843 | ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); | |
844 | if (ret) | |
379c237e EQ |
845 | return ret; |
846 | ||
847 | *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; | |
848 | ||
849 | return 0; | |
dd3c45d3 HZ |
850 | } |
851 | ||
3ea8fb8c | 852 | static int psp_v11_0_ras_trigger_error(struct psp_context *psp, |
853 | struct ta_ras_trigger_error_input *info) | |
854 | { | |
855 | struct ta_ras_shared_memory *ras_cmd; | |
856 | int ret; | |
857 | ||
858 | if (!psp->ras.ras_initialized) | |
859 | return -EINVAL; | |
860 | ||
861 | ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; | |
862 | memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); | |
863 | ||
864 | ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; | |
865 | ras_cmd->ras_in_message.trigger_error = *info; | |
866 | ||
867 | ret = psp_ras_invoke(psp, ras_cmd->cmd_id); | |
868 | if (ret) | |
869 | return -EINVAL; | |
870 | ||
871 | return ras_cmd->ras_status; | |
872 | } | |
873 | ||
874 | static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) | |
875 | { | |
876 | #if 0 | |
877 | // not support yet. | |
878 | struct ta_ras_shared_memory *ras_cmd; | |
879 | int ret; | |
880 | ||
881 | if (!psp->ras.ras_initialized) | |
882 | return -EINVAL; | |
883 | ||
884 | ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; | |
885 | memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); | |
886 | ||
887 | ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; | |
888 | ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; | |
889 | ||
890 | ret = psp_ras_invoke(psp, ras_cmd->cmd_id); | |
891 | if (ret) | |
892 | return -EINVAL; | |
893 | ||
894 | return ras_cmd->ras_status; | |
895 | #else | |
896 | return -EINVAL; | |
897 | #endif | |
898 | } | |
899 | ||
1a5b4cca HZ |
900 | static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) |
901 | { | |
902 | return psp_rlc_autoload_start(psp); | |
903 | } | |
904 | ||
654f761c FX |
905 | static const struct psp_funcs psp_v11_0_funcs = { |
906 | .init_microcode = psp_v11_0_init_microcode, | |
42989359 | 907 | .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, |
654f761c FX |
908 | .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, |
909 | .bootloader_load_sos = psp_v11_0_bootloader_load_sos, | |
654f761c FX |
910 | .ring_init = psp_v11_0_ring_init, |
911 | .ring_create = psp_v11_0_ring_create, | |
912 | .ring_stop = psp_v11_0_ring_stop, | |
913 | .ring_destroy = psp_v11_0_ring_destroy, | |
914 | .cmd_submit = psp_v11_0_cmd_submit, | |
915 | .compare_sram_data = psp_v11_0_compare_sram_data, | |
916 | .mode1_reset = psp_v11_0_mode1_reset, | |
78122127 SL |
917 | .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, |
918 | .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, | |
919 | .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, | |
dd3c45d3 | 920 | .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, |
e27a73d1 | 921 | .support_vmr_ring = psp_v11_0_support_vmr_ring, |
3ea8fb8c | 922 | .ras_trigger_error = psp_v11_0_ras_trigger_error, |
923 | .ras_cure_posion = psp_v11_0_ras_cure_posion, | |
1a5b4cca | 924 | .rlc_autoload_start = psp_v11_0_rlc_autoload_start, |
654f761c FX |
925 | }; |
926 | ||
927 | void psp_v11_0_set_psp_funcs(struct psp_context *psp) | |
928 | { | |
929 | psp->funcs = &psp_v11_0_funcs; | |
930 | } |