Commit | Line | Data |
---|---|---|
c6b6a421 HZ |
1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include <linux/firmware.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/module.h> | |
e9eea902 AD |
26 | #include <linux/pci.h> |
27 | ||
6f786950 AD |
28 | #include <drm/amdgpu_drm.h> |
29 | ||
c6b6a421 HZ |
30 | #include "amdgpu.h" |
31 | #include "amdgpu_atombios.h" | |
32 | #include "amdgpu_ih.h" | |
33 | #include "amdgpu_uvd.h" | |
34 | #include "amdgpu_vce.h" | |
35 | #include "amdgpu_ucode.h" | |
36 | #include "amdgpu_psp.h" | |
37 | #include "atom.h" | |
38 | #include "amd_pcie.h" | |
39 | ||
40 | #include "gc/gc_10_1_0_offset.h" | |
41 | #include "gc/gc_10_1_0_sh_mask.h" | |
3967ae6d | 42 | #include "mp/mp_11_0_offset.h" |
c6b6a421 HZ |
43 | |
44 | #include "soc15.h" | |
45 | #include "soc15_common.h" | |
46 | #include "gmc_v10_0.h" | |
47 | #include "gfxhub_v2_0.h" | |
48 | #include "mmhub_v2_0.h" | |
bebc0762 | 49 | #include "nbio_v2_3.h" |
a7e91bd7 | 50 | #include "nbio_v7_2.h" |
bf087285 | 51 | #include "hdp_v5_0.h" |
c6b6a421 HZ |
52 | #include "nv.h" |
53 | #include "navi10_ih.h" | |
54 | #include "gfx_v10_0.h" | |
55 | #include "sdma_v5_0.h" | |
157e72e8 | 56 | #include "sdma_v5_2.h" |
c6b6a421 | 57 | #include "vcn_v2_0.h" |
5be45a26 | 58 | #include "jpeg_v2_0.h" |
b8f10585 | 59 | #include "vcn_v3_0.h" |
4d72dd12 | 60 | #include "jpeg_v3_0.h" |
c6b6a421 HZ |
61 | #include "dce_virtual.h" |
62 | #include "mes_v10_1.h" | |
b05b6903 | 63 | #include "mxgpu_nv.h" |
0bf7f2dc LG |
64 | #include "smuio_v11_0.h" |
65 | #include "smuio_v11_0_6.h" | |
c6b6a421 HZ |
66 | |
67 | static const struct amd_ip_funcs nv_common_ip_funcs; | |
68 | ||
3b246e8b AD |
69 | /* Navi */ |
70 | static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = | |
71 | { | |
72 | { | |
6f786950 | 73 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
74 | .max_width = 4096, |
75 | .max_height = 2304, | |
76 | .max_pixels_per_frame = 4096 * 2304, | |
77 | .max_level = 0, | |
78 | }, | |
79 | { | |
6f786950 | 80 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
81 | .max_width = 4096, |
82 | .max_height = 2304, | |
83 | .max_pixels_per_frame = 4096 * 2304, | |
84 | .max_level = 0, | |
85 | }, | |
86 | }; | |
87 | ||
88 | static const struct amdgpu_video_codecs nv_video_codecs_encode = | |
89 | { | |
90 | .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), | |
91 | .codec_array = nv_video_codecs_encode_array, | |
92 | }; | |
93 | ||
94 | /* Navi1x */ | |
95 | static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = | |
96 | { | |
97 | { | |
6f786950 | 98 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
99 | .max_width = 4096, |
100 | .max_height = 4096, | |
101 | .max_pixels_per_frame = 4096 * 4096, | |
102 | .max_level = 3, | |
103 | }, | |
104 | { | |
6f786950 | 105 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
106 | .max_width = 4096, |
107 | .max_height = 4096, | |
108 | .max_pixels_per_frame = 4096 * 4096, | |
109 | .max_level = 5, | |
110 | }, | |
111 | { | |
6f786950 | 112 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
113 | .max_width = 4096, |
114 | .max_height = 4096, | |
115 | .max_pixels_per_frame = 4096 * 4096, | |
116 | .max_level = 52, | |
117 | }, | |
118 | { | |
6f786950 | 119 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
120 | .max_width = 4096, |
121 | .max_height = 4096, | |
122 | .max_pixels_per_frame = 4096 * 4096, | |
123 | .max_level = 4, | |
124 | }, | |
125 | { | |
6f786950 | 126 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
127 | .max_width = 8192, |
128 | .max_height = 4352, | |
129 | .max_pixels_per_frame = 8192 * 4352, | |
130 | .max_level = 186, | |
131 | }, | |
132 | { | |
6f786950 | 133 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
134 | .max_width = 4096, |
135 | .max_height = 4096, | |
136 | .max_pixels_per_frame = 4096 * 4096, | |
137 | .max_level = 0, | |
138 | }, | |
139 | { | |
6f786950 | 140 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, |
3b246e8b AD |
141 | .max_width = 8192, |
142 | .max_height = 4352, | |
143 | .max_pixels_per_frame = 8192 * 4352, | |
144 | .max_level = 0, | |
145 | }, | |
146 | }; | |
147 | ||
148 | static const struct amdgpu_video_codecs nv_video_codecs_decode = | |
149 | { | |
150 | .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), | |
151 | .codec_array = nv_video_codecs_decode_array, | |
152 | }; | |
153 | ||
154 | /* Sienna Cichlid */ | |
155 | static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = | |
156 | { | |
157 | { | |
6f786950 | 158 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, |
3b246e8b AD |
159 | .max_width = 4096, |
160 | .max_height = 4096, | |
161 | .max_pixels_per_frame = 4096 * 4096, | |
162 | .max_level = 3, | |
163 | }, | |
164 | { | |
6f786950 | 165 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, |
3b246e8b AD |
166 | .max_width = 4096, |
167 | .max_height = 4096, | |
168 | .max_pixels_per_frame = 4096 * 4096, | |
169 | .max_level = 5, | |
170 | }, | |
171 | { | |
6f786950 | 172 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, |
3b246e8b AD |
173 | .max_width = 4096, |
174 | .max_height = 4096, | |
175 | .max_pixels_per_frame = 4096 * 4096, | |
176 | .max_level = 52, | |
177 | }, | |
178 | { | |
6f786950 | 179 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, |
3b246e8b AD |
180 | .max_width = 4096, |
181 | .max_height = 4096, | |
182 | .max_pixels_per_frame = 4096 * 4096, | |
183 | .max_level = 4, | |
184 | }, | |
185 | { | |
6f786950 | 186 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, |
3b246e8b AD |
187 | .max_width = 8192, |
188 | .max_height = 4352, | |
189 | .max_pixels_per_frame = 8192 * 4352, | |
190 | .max_level = 186, | |
191 | }, | |
192 | { | |
6f786950 | 193 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, |
3b246e8b AD |
194 | .max_width = 4096, |
195 | .max_height = 4096, | |
196 | .max_pixels_per_frame = 4096 * 4096, | |
197 | .max_level = 0, | |
198 | }, | |
199 | { | |
6f786950 | 200 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, |
3b246e8b AD |
201 | .max_width = 8192, |
202 | .max_height = 4352, | |
203 | .max_pixels_per_frame = 8192 * 4352, | |
204 | .max_level = 0, | |
205 | }, | |
206 | { | |
6f786950 | 207 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, |
3b246e8b AD |
208 | .max_width = 8192, |
209 | .max_height = 4352, | |
210 | .max_pixels_per_frame = 8192 * 4352, | |
211 | .max_level = 0, | |
212 | }, | |
213 | }; | |
214 | ||
215 | static const struct amdgpu_video_codecs sc_video_codecs_decode = | |
216 | { | |
217 | .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), | |
218 | .codec_array = sc_video_codecs_decode_array, | |
219 | }; | |
220 | ||
ed9d2053 BZ |
221 | /* SRIOV Sienna Cichlid, not const since data is controlled by host */ |
222 | static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = | |
223 | { | |
224 | { | |
225 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
226 | .max_width = 4096, | |
227 | .max_height = 2304, | |
228 | .max_pixels_per_frame = 4096 * 2304, | |
229 | .max_level = 0, | |
230 | }, | |
231 | { | |
232 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
233 | .max_width = 4096, | |
234 | .max_height = 2304, | |
235 | .max_pixels_per_frame = 4096 * 2304, | |
236 | .max_level = 0, | |
237 | }, | |
238 | }; | |
239 | ||
240 | static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = | |
241 | { | |
242 | { | |
243 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, | |
244 | .max_width = 4096, | |
245 | .max_height = 4096, | |
246 | .max_pixels_per_frame = 4096 * 4096, | |
247 | .max_level = 3, | |
248 | }, | |
249 | { | |
250 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, | |
251 | .max_width = 4096, | |
252 | .max_height = 4096, | |
253 | .max_pixels_per_frame = 4096 * 4096, | |
254 | .max_level = 5, | |
255 | }, | |
256 | { | |
257 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, | |
258 | .max_width = 4096, | |
259 | .max_height = 4096, | |
260 | .max_pixels_per_frame = 4096 * 4096, | |
261 | .max_level = 52, | |
262 | }, | |
263 | { | |
264 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, | |
265 | .max_width = 4096, | |
266 | .max_height = 4096, | |
267 | .max_pixels_per_frame = 4096 * 4096, | |
268 | .max_level = 4, | |
269 | }, | |
270 | { | |
271 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, | |
272 | .max_width = 8192, | |
273 | .max_height = 4352, | |
274 | .max_pixels_per_frame = 8192 * 4352, | |
275 | .max_level = 186, | |
276 | }, | |
277 | { | |
278 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, | |
279 | .max_width = 4096, | |
280 | .max_height = 4096, | |
281 | .max_pixels_per_frame = 4096 * 4096, | |
282 | .max_level = 0, | |
283 | }, | |
284 | { | |
285 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, | |
286 | .max_width = 8192, | |
287 | .max_height = 4352, | |
288 | .max_pixels_per_frame = 8192 * 4352, | |
289 | .max_level = 0, | |
290 | }, | |
291 | { | |
292 | .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, | |
293 | .max_width = 8192, | |
294 | .max_height = 4352, | |
295 | .max_pixels_per_frame = 8192 * 4352, | |
296 | .max_level = 0, | |
297 | }, | |
298 | }; | |
299 | ||
300 | static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = | |
301 | { | |
302 | .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), | |
303 | .codec_array = sriov_sc_video_codecs_encode_array, | |
304 | }; | |
305 | ||
306 | static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = | |
307 | { | |
308 | .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), | |
309 | .codec_array = sriov_sc_video_codecs_decode_array, | |
310 | }; | |
311 | ||
3b246e8b AD |
312 | static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, |
313 | const struct amdgpu_video_codecs **codecs) | |
314 | { | |
315 | switch (adev->asic_type) { | |
316 | case CHIP_SIENNA_CICHLID: | |
ed9d2053 BZ |
317 | if (amdgpu_sriov_vf(adev)) { |
318 | if (encode) | |
319 | *codecs = &sriov_sc_video_codecs_encode; | |
320 | else | |
321 | *codecs = &sriov_sc_video_codecs_decode; | |
322 | } else { | |
323 | if (encode) | |
324 | *codecs = &nv_video_codecs_encode; | |
325 | else | |
326 | *codecs = &sc_video_codecs_decode; | |
327 | } | |
328 | return 0; | |
3b246e8b AD |
329 | case CHIP_NAVY_FLOUNDER: |
330 | case CHIP_DIMGREY_CAVEFISH: | |
331 | case CHIP_VANGOGH: | |
332 | if (encode) | |
333 | *codecs = &nv_video_codecs_encode; | |
334 | else | |
335 | *codecs = &sc_video_codecs_decode; | |
336 | return 0; | |
337 | case CHIP_NAVI10: | |
338 | case CHIP_NAVI14: | |
339 | case CHIP_NAVI12: | |
340 | if (encode) | |
341 | *codecs = &nv_video_codecs_encode; | |
342 | else | |
343 | *codecs = &nv_video_codecs_decode; | |
344 | return 0; | |
345 | default: | |
346 | return -EINVAL; | |
347 | } | |
348 | } | |
349 | ||
c6b6a421 HZ |
350 | /* |
351 | * Indirect registers accessor | |
352 | */ | |
353 | static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) | |
354 | { | |
705a2b5b | 355 | unsigned long address, data; |
bebc0762 HZ |
356 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
357 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
c6b6a421 | 358 | |
705a2b5b | 359 | return amdgpu_device_indirect_rreg(adev, address, data, reg); |
c6b6a421 HZ |
360 | } |
361 | ||
362 | static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
363 | { | |
705a2b5b | 364 | unsigned long address, data; |
c6b6a421 | 365 | |
bebc0762 HZ |
366 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
367 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
c6b6a421 | 368 | |
705a2b5b | 369 | amdgpu_device_indirect_wreg(adev, address, data, reg, v); |
c6b6a421 HZ |
370 | } |
371 | ||
4922f1bc JC |
372 | static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) |
373 | { | |
705a2b5b | 374 | unsigned long address, data; |
4922f1bc JC |
375 | address = adev->nbio.funcs->get_pcie_index_offset(adev); |
376 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
377 | ||
705a2b5b | 378 | return amdgpu_device_indirect_rreg64(adev, address, data, reg); |
4922f1bc JC |
379 | } |
380 | ||
5de54343 HR |
381 | static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) |
382 | { | |
383 | unsigned long flags, address, data; | |
384 | u32 r; | |
385 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
386 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
387 | ||
388 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
389 | WREG32(address, reg * 4); | |
390 | (void)RREG32(address); | |
391 | r = RREG32(data); | |
392 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
393 | return r; | |
394 | } | |
395 | ||
4922f1bc JC |
396 | static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) |
397 | { | |
705a2b5b | 398 | unsigned long address, data; |
4922f1bc JC |
399 | |
400 | address = adev->nbio.funcs->get_pcie_index_offset(adev); | |
401 | data = adev->nbio.funcs->get_pcie_data_offset(adev); | |
402 | ||
705a2b5b | 403 | amdgpu_device_indirect_wreg64(adev, address, data, reg, v); |
4922f1bc JC |
404 | } |
405 | ||
5de54343 HR |
406 | static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
407 | { | |
408 | unsigned long flags, address, data; | |
409 | ||
410 | address = adev->nbio.funcs->get_pcie_port_index_offset(adev); | |
411 | data = adev->nbio.funcs->get_pcie_port_data_offset(adev); | |
412 | ||
413 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
414 | WREG32(address, reg * 4); | |
415 | (void)RREG32(address); | |
416 | WREG32(data, v); | |
417 | (void)RREG32(data); | |
418 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
419 | } | |
420 | ||
c6b6a421 HZ |
421 | static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) |
422 | { | |
423 | unsigned long flags, address, data; | |
424 | u32 r; | |
425 | ||
426 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); | |
427 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); | |
428 | ||
429 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
430 | WREG32(address, (reg)); | |
431 | r = RREG32(data); | |
432 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
433 | return r; | |
434 | } | |
435 | ||
436 | static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
437 | { | |
438 | unsigned long flags, address, data; | |
439 | ||
440 | address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); | |
441 | data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); | |
442 | ||
443 | spin_lock_irqsave(&adev->didt_idx_lock, flags); | |
444 | WREG32(address, (reg)); | |
445 | WREG32(data, (v)); | |
446 | spin_unlock_irqrestore(&adev->didt_idx_lock, flags); | |
447 | } | |
448 | ||
449 | static u32 nv_get_config_memsize(struct amdgpu_device *adev) | |
450 | { | |
bebc0762 | 451 | return adev->nbio.funcs->get_memsize(adev); |
c6b6a421 HZ |
452 | } |
453 | ||
454 | static u32 nv_get_xclk(struct amdgpu_device *adev) | |
455 | { | |
462a70d8 | 456 | return adev->clock.spll.reference_freq; |
c6b6a421 HZ |
457 | } |
458 | ||
459 | ||
460 | void nv_grbm_select(struct amdgpu_device *adev, | |
461 | u32 me, u32 pipe, u32 queue, u32 vmid) | |
462 | { | |
463 | u32 grbm_gfx_cntl = 0; | |
464 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); | |
465 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); | |
466 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); | |
467 | grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); | |
468 | ||
f2958a8b | 469 | WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); |
c6b6a421 HZ |
470 | } |
471 | ||
472 | static void nv_vga_set_state(struct amdgpu_device *adev, bool state) | |
473 | { | |
474 | /* todo */ | |
475 | } | |
476 | ||
477 | static bool nv_read_disabled_bios(struct amdgpu_device *adev) | |
478 | { | |
479 | /* todo */ | |
480 | return false; | |
481 | } | |
482 | ||
483 | static bool nv_read_bios_from_rom(struct amdgpu_device *adev, | |
484 | u8 *bios, u32 length_bytes) | |
485 | { | |
29bc37b4 AD |
486 | u32 *dw_ptr; |
487 | u32 i, length_dw; | |
0bf7f2dc | 488 | u32 rom_index_offset, rom_data_offset; |
29bc37b4 AD |
489 | |
490 | if (bios == NULL) | |
491 | return false; | |
492 | if (length_bytes == 0) | |
493 | return false; | |
494 | /* APU vbios image is part of sbios image */ | |
495 | if (adev->flags & AMD_IS_APU) | |
496 | return false; | |
497 | ||
498 | dw_ptr = (u32 *)bios; | |
499 | length_dw = ALIGN(length_bytes, 4) / 4; | |
500 | ||
0bf7f2dc LG |
501 | rom_index_offset = |
502 | adev->smuio.funcs->get_rom_index_offset(adev); | |
503 | rom_data_offset = | |
504 | adev->smuio.funcs->get_rom_data_offset(adev); | |
505 | ||
29bc37b4 | 506 | /* set rom index to 0 */ |
0bf7f2dc | 507 | WREG32(rom_index_offset, 0); |
29bc37b4 AD |
508 | /* read out the rom data */ |
509 | for (i = 0; i < length_dw; i++) | |
0bf7f2dc | 510 | dw_ptr[i] = RREG32(rom_data_offset); |
29bc37b4 AD |
511 | |
512 | return true; | |
c6b6a421 HZ |
513 | } |
514 | ||
515 | static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { | |
516 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, | |
517 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, | |
518 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, | |
519 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, | |
520 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, | |
521 | { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, | |
c6b6a421 HZ |
522 | { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, |
523 | { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, | |
c6b6a421 HZ |
524 | { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, |
525 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, | |
526 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, | |
527 | { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, | |
528 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, | |
529 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, | |
530 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, | |
664fe85a | 531 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, |
c6b6a421 HZ |
532 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, |
533 | { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, | |
534 | { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, | |
535 | }; | |
536 | ||
537 | static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, | |
538 | u32 sh_num, u32 reg_offset) | |
539 | { | |
540 | uint32_t val; | |
541 | ||
542 | mutex_lock(&adev->grbm_idx_mutex); | |
543 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
544 | amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); | |
545 | ||
546 | val = RREG32(reg_offset); | |
547 | ||
548 | if (se_num != 0xffffffff || sh_num != 0xffffffff) | |
549 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
550 | mutex_unlock(&adev->grbm_idx_mutex); | |
551 | return val; | |
552 | } | |
553 | ||
554 | static uint32_t nv_get_register_value(struct amdgpu_device *adev, | |
555 | bool indexed, u32 se_num, | |
556 | u32 sh_num, u32 reg_offset) | |
557 | { | |
558 | if (indexed) { | |
559 | return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); | |
560 | } else { | |
561 | if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) | |
562 | return adev->gfx.config.gb_addr_config; | |
563 | return RREG32(reg_offset); | |
564 | } | |
565 | } | |
566 | ||
567 | static int nv_read_register(struct amdgpu_device *adev, u32 se_num, | |
568 | u32 sh_num, u32 reg_offset, u32 *value) | |
569 | { | |
570 | uint32_t i; | |
571 | struct soc15_allowed_register_entry *en; | |
572 | ||
573 | *value = 0; | |
574 | for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { | |
575 | en = &nv_allowed_read_registers[i]; | |
fced3c3a HR |
576 | if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ |
577 | reg_offset != | |
c6b6a421 HZ |
578 | (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) |
579 | continue; | |
580 | ||
581 | *value = nv_get_register_value(adev, | |
582 | nv_allowed_read_registers[i].grbm_indexed, | |
583 | se_num, sh_num, reg_offset); | |
584 | return 0; | |
585 | } | |
586 | return -EINVAL; | |
587 | } | |
588 | ||
b913ec62 AD |
589 | static int nv_asic_mode2_reset(struct amdgpu_device *adev) |
590 | { | |
591 | u32 i; | |
592 | int ret = 0; | |
593 | ||
594 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
595 | ||
596 | /* disable BM */ | |
597 | pci_clear_master(adev->pdev); | |
598 | ||
599 | amdgpu_device_cache_pci_state(adev->pdev); | |
600 | ||
601 | ret = amdgpu_dpm_mode2_reset(adev); | |
602 | if (ret) | |
603 | dev_err(adev->dev, "GPU mode2 reset failed\n"); | |
604 | ||
605 | amdgpu_device_load_pci_state(adev->pdev); | |
606 | ||
607 | /* wait for asic to come out of reset */ | |
608 | for (i = 0; i < adev->usec_timeout; i++) { | |
609 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
610 | ||
611 | if (memsize != 0xffffffff) | |
612 | break; | |
613 | udelay(1); | |
614 | } | |
615 | ||
616 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
617 | ||
618 | return ret; | |
619 | } | |
620 | ||
2ddc6c3e AD |
621 | static enum amd_reset_method |
622 | nv_asic_reset_method(struct amdgpu_device *adev) | |
623 | { | |
273da6ff | 624 | if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || |
16086355 | 625 | amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || |
f172865a AD |
626 | amdgpu_reset_method == AMD_RESET_METHOD_BACO || |
627 | amdgpu_reset_method == AMD_RESET_METHOD_PCI) | |
273da6ff WS |
628 | return amdgpu_reset_method; |
629 | ||
630 | if (amdgpu_reset_method != -1) | |
631 | dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", | |
632 | amdgpu_reset_method); | |
633 | ||
ca6fd7a6 | 634 | switch (adev->asic_type) { |
16086355 AD |
635 | case CHIP_VANGOGH: |
636 | return AMD_RESET_METHOD_MODE2; | |
ca6fd7a6 | 637 | case CHIP_SIENNA_CICHLID: |
22dd44f4 | 638 | case CHIP_NAVY_FLOUNDER: |
15ed44c0 | 639 | case CHIP_DIMGREY_CAVEFISH: |
5ed7715d | 640 | case CHIP_BEIGE_GOBY: |
2ddc6c3e | 641 | return AMD_RESET_METHOD_MODE1; |
ca6fd7a6 | 642 | default: |
181e772f | 643 | if (amdgpu_dpm_is_baco_supported(adev)) |
ca6fd7a6 LG |
644 | return AMD_RESET_METHOD_BACO; |
645 | else | |
646 | return AMD_RESET_METHOD_MODE1; | |
647 | } | |
2ddc6c3e AD |
648 | } |
649 | ||
c6b6a421 HZ |
650 | static int nv_asic_reset(struct amdgpu_device *adev) |
651 | { | |
767acabd | 652 | int ret = 0; |
c6b6a421 | 653 | |
16086355 | 654 | switch (nv_asic_reset_method(adev)) { |
f172865a AD |
655 | case AMD_RESET_METHOD_PCI: |
656 | dev_info(adev->dev, "PCI reset\n"); | |
657 | ret = amdgpu_device_pci_reset(adev); | |
658 | break; | |
16086355 | 659 | case AMD_RESET_METHOD_BACO: |
11043b7a | 660 | dev_info(adev->dev, "BACO reset\n"); |
181e772f | 661 | ret = amdgpu_dpm_baco_reset(adev); |
16086355 AD |
662 | break; |
663 | case AMD_RESET_METHOD_MODE2: | |
664 | dev_info(adev->dev, "MODE2 reset\n"); | |
b913ec62 | 665 | ret = nv_asic_mode2_reset(adev); |
16086355 AD |
666 | break; |
667 | default: | |
11043b7a | 668 | dev_info(adev->dev, "MODE1 reset\n"); |
5c03e584 | 669 | ret = amdgpu_device_mode1_reset(adev); |
16086355 | 670 | break; |
11043b7a | 671 | } |
767acabd KW |
672 | |
673 | return ret; | |
c6b6a421 HZ |
674 | } |
675 | ||
676 | static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) | |
677 | { | |
678 | /* todo */ | |
679 | return 0; | |
680 | } | |
681 | ||
682 | static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) | |
683 | { | |
684 | /* todo */ | |
685 | return 0; | |
686 | } | |
687 | ||
688 | static void nv_pcie_gen3_enable(struct amdgpu_device *adev) | |
689 | { | |
690 | if (pci_is_root_bus(adev->pdev->bus)) | |
691 | return; | |
692 | ||
693 | if (amdgpu_pcie_gen2 == 0) | |
694 | return; | |
695 | ||
696 | if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
697 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) | |
698 | return; | |
699 | ||
700 | /* todo */ | |
701 | } | |
702 | ||
703 | static void nv_program_aspm(struct amdgpu_device *adev) | |
704 | { | |
0064b0ce | 705 | if (!amdgpu_aspm) |
c6b6a421 HZ |
706 | return; |
707 | ||
3273f8b9 | 708 | if (!(adev->flags & AMD_IS_APU) && |
e1edaeaf LG |
709 | (adev->nbio.funcs->program_aspm)) |
710 | adev->nbio.funcs->program_aspm(adev); | |
711 | ||
c6b6a421 HZ |
712 | } |
713 | ||
714 | static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, | |
715 | bool enable) | |
716 | { | |
bebc0762 HZ |
717 | adev->nbio.funcs->enable_doorbell_aperture(adev, enable); |
718 | adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); | |
c6b6a421 HZ |
719 | } |
720 | ||
721 | static const struct amdgpu_ip_block_version nv_common_ip_block = | |
722 | { | |
723 | .type = AMD_IP_BLOCK_TYPE_COMMON, | |
724 | .major = 1, | |
725 | .minor = 0, | |
726 | .rev = 0, | |
727 | .funcs = &nv_common_ip_funcs, | |
728 | }; | |
729 | ||
32358093 LG |
730 | static bool nv_is_headless_sku(struct pci_dev *pdev) |
731 | { | |
732 | if ((pdev->device == 0x731E && | |
733 | (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || | |
734 | (pdev->device == 0x7340 && pdev->revision == 0xC9) || | |
735 | (pdev->device == 0x7360 && pdev->revision == 0xC7)) | |
736 | return true; | |
737 | return false; | |
738 | } | |
739 | ||
b5c73856 | 740 | static int nv_reg_base_init(struct amdgpu_device *adev) |
c6b6a421 | 741 | { |
b5c73856 XY |
742 | int r; |
743 | ||
744 | if (amdgpu_discovery) { | |
745 | r = amdgpu_discovery_reg_base_init(adev); | |
746 | if (r) { | |
747 | DRM_WARN("failed to init reg base from ip discovery table, " | |
748 | "fallback to legacy init method\n"); | |
749 | goto legacy_init; | |
750 | } | |
751 | ||
7bd939d0 | 752 | amdgpu_discovery_harvest_ip(adev); |
32358093 LG |
753 | if (nv_is_headless_sku(adev->pdev)) { |
754 | adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; | |
755 | adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; | |
756 | } | |
7bd939d0 | 757 | |
b5c73856 XY |
758 | return 0; |
759 | } | |
760 | ||
761 | legacy_init: | |
c6b6a421 HZ |
762 | switch (adev->asic_type) { |
763 | case CHIP_NAVI10: | |
764 | navi10_reg_base_init(adev); | |
765 | break; | |
a0f6d926 XY |
766 | case CHIP_NAVI14: |
767 | navi14_reg_base_init(adev); | |
768 | break; | |
03d0a073 XY |
769 | case CHIP_NAVI12: |
770 | navi12_reg_base_init(adev); | |
771 | break; | |
dccdbf3f | 772 | case CHIP_SIENNA_CICHLID: |
c8c959f6 | 773 | case CHIP_NAVY_FLOUNDER: |
dccdbf3f LG |
774 | sienna_cichlid_reg_base_init(adev); |
775 | break; | |
026570e6 HR |
776 | case CHIP_VANGOGH: |
777 | vangogh_reg_base_init(adev); | |
778 | break; | |
038d757b TZ |
779 | case CHIP_DIMGREY_CAVEFISH: |
780 | dimgrey_cavefish_reg_base_init(adev); | |
781 | break; | |
fd5b4b44 CG |
782 | case CHIP_BEIGE_GOBY: |
783 | beige_goby_reg_base_init(adev); | |
784 | break; | |
e7990721 AL |
785 | case CHIP_YELLOW_CARP: |
786 | yellow_carp_reg_base_init(adev); | |
787 | break; | |
c6b6a421 HZ |
788 | default: |
789 | return -EINVAL; | |
790 | } | |
791 | ||
b5c73856 XY |
792 | return 0; |
793 | } | |
794 | ||
c1299461 WS |
795 | void nv_set_virt_ops(struct amdgpu_device *adev) |
796 | { | |
797 | adev->virt.ops = &xgpu_nv_virt_ops; | |
798 | } | |
799 | ||
b5c73856 XY |
800 | int nv_set_ip_blocks(struct amdgpu_device *adev) |
801 | { | |
802 | int r; | |
803 | ||
a7e91bd7 HR |
804 | if (adev->flags & AMD_IS_APU) { |
805 | adev->nbio.funcs = &nbio_v7_2_funcs; | |
806 | adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; | |
807 | } else { | |
808 | adev->nbio.funcs = &nbio_v2_3_funcs; | |
809 | adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; | |
810 | } | |
bf087285 | 811 | adev->hdp.funcs = &hdp_v5_0_funcs; |
c6b6a421 | 812 | |
0bf7f2dc LG |
813 | if (adev->asic_type >= CHIP_SIENNA_CICHLID) |
814 | adev->smuio.funcs = &smuio_v11_0_6_funcs; | |
815 | else | |
816 | adev->smuio.funcs = &smuio_v11_0_funcs; | |
817 | ||
c652923a JC |
818 | if (adev->asic_type == CHIP_SIENNA_CICHLID) |
819 | adev->gmc.xgmi.supported = true; | |
820 | ||
122078de ML |
821 | /* Set IP register base before any HW register access */ |
822 | r = nv_reg_base_init(adev); | |
823 | if (r) | |
824 | return r; | |
b05b6903 | 825 | |
c6b6a421 HZ |
826 | switch (adev->asic_type) { |
827 | case CHIP_NAVI10: | |
d1daf850 | 828 | case CHIP_NAVI14: |
c6b6a421 HZ |
829 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); |
830 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); | |
831 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); | |
832 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
833 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && | |
9530273e | 834 | !amdgpu_sriov_vf(adev)) |
c6b6a421 HZ |
835 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
836 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) | |
837 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
f8a7976b | 838 | #if defined(CONFIG_DRM_AMD_DC) |
8301f6b9 | 839 | else if (amdgpu_device_has_dc_support(adev)) |
b4f199c7 | 840 | amdgpu_device_ip_block_add(adev, &dm_ip_block); |
f8a7976b | 841 | #endif |
c6b6a421 HZ |
842 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); |
843 | amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); | |
844 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && | |
9530273e | 845 | !amdgpu_sriov_vf(adev)) |
c6b6a421 | 846 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
32358093 | 847 | amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); |
5be45a26 | 848 | amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); |
c6b6a421 HZ |
849 | if (adev->enable_mes) |
850 | amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); | |
851 | break; | |
44e9e7c9 XY |
852 | case CHIP_NAVI12: |
853 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); | |
854 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); | |
2a4021cc PJZ |
855 | if (!amdgpu_sriov_vf(adev)) { |
856 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); | |
857 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
858 | } else { | |
859 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
860 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); | |
861 | } | |
79bebabb | 862 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) |
7f47efeb | 863 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
79902029 XY |
864 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
865 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
20c14ee1 | 866 | #if defined(CONFIG_DRM_AMD_DC) |
078655d9 LL |
867 | else if (amdgpu_device_has_dc_support(adev)) |
868 | amdgpu_device_ip_block_add(adev, &dm_ip_block); | |
20c14ee1 | 869 | #endif |
44e9e7c9 XY |
870 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); |
871 | amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); | |
7f47efeb | 872 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && |
9530273e | 873 | !amdgpu_sriov_vf(adev)) |
7f47efeb | 874 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
32358093 | 875 | amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); |
fe442491 ML |
876 | if (!amdgpu_sriov_vf(adev)) |
877 | amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); | |
44e9e7c9 | 878 | break; |
2e1ba10e LG |
879 | case CHIP_SIENNA_CICHLID: |
880 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); | |
0b3df16b | 881 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); |
4aa7e6e0 YW |
882 | if (!amdgpu_sriov_vf(adev)) { |
883 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); | |
884 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
885 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
886 | } else { | |
887 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) | |
888 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
889 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); | |
890 | } | |
b07e5c60 | 891 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && |
acf2740f | 892 | is_support_sw_smu(adev)) |
b07e5c60 | 893 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
9a986760 LG |
894 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
895 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
464ab91a BL |
896 | #if defined(CONFIG_DRM_AMD_DC) |
897 | else if (amdgpu_device_has_dc_support(adev)) | |
898 | amdgpu_device_ip_block_add(adev, &dm_ip_block); | |
899 | #endif | |
933c8a93 | 900 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); |
157e72e8 | 901 | amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); |
b8f10585 | 902 | amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); |
c45fbe1b JZ |
903 | if (!amdgpu_sriov_vf(adev)) |
904 | amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); | |
a346ef86 JX |
905 | if (adev->enable_mes) |
906 | amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); | |
2e1ba10e | 907 | break; |
8515e0a4 JC |
908 | case CHIP_NAVY_FLOUNDER: |
909 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); | |
fc8f07da | 910 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); |
026c396b | 911 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); |
7420eab2 JC |
912 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
913 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
914 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && | |
915 | is_support_sw_smu(adev)) | |
916 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); | |
5404f073 JC |
917 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
918 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
a6c5308f BL |
919 | #if defined(CONFIG_DRM_AMD_DC) |
920 | else if (amdgpu_device_has_dc_support(adev)) | |
921 | amdgpu_device_ip_block_add(adev, &dm_ip_block); | |
922 | #endif | |
885eb3fa | 923 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); |
df2d15df | 924 | amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); |
290b4ad5 BZ |
925 | amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); |
926 | amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); | |
f4497d10 JC |
927 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && |
928 | is_support_sw_smu(adev)) | |
929 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); | |
8515e0a4 | 930 | break; |
88edbad6 HR |
931 | case CHIP_VANGOGH: |
932 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); | |
933 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); | |
934 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); | |
ed3b7353 HR |
935 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
936 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
c821e0fb | 937 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); |
88edbad6 HR |
938 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
939 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
84b934bc HR |
940 | #if defined(CONFIG_DRM_AMD_DC) |
941 | else if (amdgpu_device_has_dc_support(adev)) | |
942 | amdgpu_device_ip_block_add(adev, &dm_ip_block); | |
943 | #endif | |
88edbad6 HR |
944 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); |
945 | amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); | |
b4e532d6 TT |
946 | amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); |
947 | amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); | |
88edbad6 | 948 | break; |
2aa92b12 TZ |
949 | case CHIP_DIMGREY_CAVEFISH: |
950 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); | |
3e02ad44 | 951 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); |
771cc67e | 952 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); |
aff39cde TZ |
953 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
954 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
955 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && | |
956 | is_support_sw_smu(adev)) | |
957 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); | |
76a2d9ea TZ |
958 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
959 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
7cc656e2 TZ |
960 | #if defined(CONFIG_DRM_AMD_DC) |
961 | else if (amdgpu_device_has_dc_support(adev)) | |
962 | amdgpu_device_ip_block_add(adev, &dm_ip_block); | |
963 | #endif | |
feb6329c | 964 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); |
01069226 | 965 | amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); |
0afc770b | 966 | amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); |
be6b1cd3 | 967 | amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); |
2aa92b12 | 968 | break; |
aa2caa2a CG |
969 | case CHIP_BEIGE_GOBY: |
970 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); | |
2d527ea6 | 971 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); |
a1dede36 | 972 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); |
c0729819 CG |
973 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
974 | amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); | |
975 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && | |
976 | is_support_sw_smu(adev)) | |
977 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); | |
898319ca | 978 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); |
8760403e | 979 | amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); |
5663da86 CG |
980 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
981 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
ddaed58b AP |
982 | #if defined(CONFIG_DRM_AMD_DC) |
983 | else if (amdgpu_device_has_dc_support(adev)) | |
984 | amdgpu_device_ip_block_add(adev, &dm_ip_block); | |
985 | #endif | |
4d352669 CG |
986 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && |
987 | is_support_sw_smu(adev)) | |
988 | amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); | |
f703d4b6 | 989 | amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); |
aa2caa2a | 990 | break; |
5c462ca9 AL |
991 | case CHIP_YELLOW_CARP: |
992 | amdgpu_device_ip_block_add(adev, &nv_common_ip_block); | |
993 | amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); | |
994 | amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); | |
903bb18b AL |
995 | if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) |
996 | amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); | |
120a6db4 | 997 | amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); |
5c462ca9 AL |
998 | if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) |
999 | amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); | |
1000 | amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); | |
1001 | amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); | |
1002 | break; | |
c6b6a421 HZ |
1003 | default: |
1004 | return -EINVAL; | |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | static uint32_t nv_get_rev_id(struct amdgpu_device *adev) | |
1011 | { | |
bebc0762 | 1012 | return adev->nbio.funcs->get_rev_id(adev); |
c6b6a421 HZ |
1013 | } |
1014 | ||
c6b6a421 HZ |
1015 | static bool nv_need_full_reset(struct amdgpu_device *adev) |
1016 | { | |
1017 | return true; | |
1018 | } | |
1019 | ||
c6b6a421 HZ |
1020 | static bool nv_need_reset_on_init(struct amdgpu_device *adev) |
1021 | { | |
c6b6a421 HZ |
1022 | u32 sol_reg; |
1023 | ||
1024 | if (adev->flags & AMD_IS_APU) | |
1025 | return false; | |
1026 | ||
1027 | /* Check sOS sign of life register to confirm sys driver and sOS | |
1028 | * are already been loaded. | |
1029 | */ | |
1030 | sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); | |
1031 | if (sol_reg) | |
1032 | return true; | |
3967ae6d | 1033 | |
c6b6a421 HZ |
1034 | return false; |
1035 | } | |
1036 | ||
2af81531 KW |
1037 | static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) |
1038 | { | |
1039 | ||
1040 | /* TODO | |
1041 | * dummy implement for pcie_replay_count sysfs interface | |
1042 | * */ | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
c6b6a421 HZ |
1047 | static void nv_init_doorbell_index(struct amdgpu_device *adev) |
1048 | { | |
1049 | adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; | |
1050 | adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; | |
1051 | adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; | |
1052 | adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; | |
1053 | adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; | |
1054 | adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; | |
1055 | adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; | |
1056 | adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; | |
1057 | adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; | |
1058 | adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; | |
1059 | adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; | |
1060 | adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; | |
1061 | adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; | |
20519232 | 1062 | adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; |
c6b6a421 HZ |
1063 | adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; |
1064 | adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; | |
157e72e8 LG |
1065 | adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; |
1066 | adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; | |
c6b6a421 HZ |
1067 | adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; |
1068 | adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; | |
1069 | adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; | |
1070 | adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; | |
1071 | adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; | |
1072 | adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; | |
1073 | adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; | |
1074 | ||
1075 | adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; | |
1076 | adev->doorbell_index.sdma_doorbell_range = 20; | |
1077 | } | |
1078 | ||
a7173731 AD |
1079 | static void nv_pre_asic_init(struct amdgpu_device *adev) |
1080 | { | |
1081 | } | |
1082 | ||
27747293 EQ |
1083 | static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, |
1084 | bool enter) | |
1085 | { | |
1086 | if (enter) | |
1087 | amdgpu_gfx_rlc_enter_safe_mode(adev); | |
1088 | else | |
1089 | amdgpu_gfx_rlc_exit_safe_mode(adev); | |
1090 | ||
1091 | if (adev->gfx.funcs->update_perfmon_mgcg) | |
1092 | adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); | |
1093 | ||
3273f8b9 | 1094 | if (!(adev->flags & AMD_IS_APU) && |
e1edaeaf | 1095 | (adev->nbio.funcs->enable_aspm)) |
27747293 | 1096 | adev->nbio.funcs->enable_aspm(adev, !enter); |
27747293 EQ |
1097 | |
1098 | return 0; | |
1099 | } | |
1100 | ||
c6b6a421 HZ |
1101 | static const struct amdgpu_asic_funcs nv_asic_funcs = |
1102 | { | |
1103 | .read_disabled_bios = &nv_read_disabled_bios, | |
1104 | .read_bios_from_rom = &nv_read_bios_from_rom, | |
1105 | .read_register = &nv_read_register, | |
1106 | .reset = &nv_asic_reset, | |
2ddc6c3e | 1107 | .reset_method = &nv_asic_reset_method, |
c6b6a421 HZ |
1108 | .set_vga_state = &nv_vga_set_state, |
1109 | .get_xclk = &nv_get_xclk, | |
1110 | .set_uvd_clocks = &nv_set_uvd_clocks, | |
1111 | .set_vce_clocks = &nv_set_vce_clocks, | |
1112 | .get_config_memsize = &nv_get_config_memsize, | |
c6b6a421 HZ |
1113 | .init_doorbell_index = &nv_init_doorbell_index, |
1114 | .need_full_reset = &nv_need_full_reset, | |
c6b6a421 | 1115 | .need_reset_on_init = &nv_need_reset_on_init, |
2af81531 | 1116 | .get_pcie_replay_count = &nv_get_pcie_replay_count, |
181e772f | 1117 | .supports_baco = &amdgpu_dpm_is_baco_supported, |
a7173731 | 1118 | .pre_asic_init = &nv_pre_asic_init, |
27747293 | 1119 | .update_umd_stable_pstate = &nv_update_umd_stable_pstate, |
3b246e8b | 1120 | .query_video_codecs = &nv_query_video_codecs, |
c6b6a421 HZ |
1121 | }; |
1122 | ||
1123 | static int nv_common_early_init(void *handle) | |
1124 | { | |
923c087a | 1125 | #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) |
c6b6a421 HZ |
1126 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1127 | ||
923c087a YZ |
1128 | adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; |
1129 | adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; | |
c6b6a421 HZ |
1130 | adev->smc_rreg = NULL; |
1131 | adev->smc_wreg = NULL; | |
1132 | adev->pcie_rreg = &nv_pcie_rreg; | |
1133 | adev->pcie_wreg = &nv_pcie_wreg; | |
4922f1bc JC |
1134 | adev->pcie_rreg64 = &nv_pcie_rreg64; |
1135 | adev->pcie_wreg64 = &nv_pcie_wreg64; | |
5de54343 HR |
1136 | adev->pciep_rreg = &nv_pcie_port_rreg; |
1137 | adev->pciep_wreg = &nv_pcie_port_wreg; | |
c6b6a421 HZ |
1138 | |
1139 | /* TODO: will add them during VCN v2 implementation */ | |
1140 | adev->uvd_ctx_rreg = NULL; | |
1141 | adev->uvd_ctx_wreg = NULL; | |
1142 | ||
1143 | adev->didt_rreg = &nv_didt_rreg; | |
1144 | adev->didt_wreg = &nv_didt_wreg; | |
1145 | ||
1146 | adev->asic_funcs = &nv_asic_funcs; | |
1147 | ||
c6b6a421 HZ |
1148 | adev->rev_id = nv_get_rev_id(adev); |
1149 | adev->external_rev_id = 0xff; | |
1150 | switch (adev->asic_type) { | |
1151 | case CHIP_NAVI10: | |
1152 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | | |
c6b6a421 HZ |
1153 | AMD_CG_SUPPORT_GFX_CGCG | |
1154 | AMD_CG_SUPPORT_IH_CG | | |
1155 | AMD_CG_SUPPORT_HDP_MGCG | | |
1156 | AMD_CG_SUPPORT_HDP_LS | | |
1157 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1158 | AMD_CG_SUPPORT_SDMA_LS | | |
1159 | AMD_CG_SUPPORT_MC_MGCG | | |
1160 | AMD_CG_SUPPORT_MC_LS | | |
1161 | AMD_CG_SUPPORT_ATHUB_MGCG | | |
1162 | AMD_CG_SUPPORT_ATHUB_LS | | |
1163 | AMD_CG_SUPPORT_VCN_MGCG | | |
099d66e4 | 1164 | AMD_CG_SUPPORT_JPEG_MGCG | |
c6b6a421 HZ |
1165 | AMD_CG_SUPPORT_BIF_MGCG | |
1166 | AMD_CG_SUPPORT_BIF_LS; | |
157710ea | 1167 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
c12d410f | 1168 | AMD_PG_SUPPORT_VCN_DPG | |
099d66e4 | 1169 | AMD_PG_SUPPORT_JPEG | |
a201b6ac | 1170 | AMD_PG_SUPPORT_ATHUB; |
c6b6a421 HZ |
1171 | adev->external_rev_id = adev->rev_id + 0x1; |
1172 | break; | |
5e71e011 | 1173 | case CHIP_NAVI14: |
d0c39f8c XY |
1174 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1175 | AMD_CG_SUPPORT_GFX_CGCG | | |
1176 | AMD_CG_SUPPORT_IH_CG | | |
1177 | AMD_CG_SUPPORT_HDP_MGCG | | |
1178 | AMD_CG_SUPPORT_HDP_LS | | |
1179 | AMD_CG_SUPPORT_SDMA_MGCG | | |
1180 | AMD_CG_SUPPORT_SDMA_LS | | |
1181 | AMD_CG_SUPPORT_MC_MGCG | | |
1182 | AMD_CG_SUPPORT_MC_LS | | |
1183 | AMD_CG_SUPPORT_ATHUB_MGCG | | |
1184 | AMD_CG_SUPPORT_ATHUB_LS | | |
1185 | AMD_CG_SUPPORT_VCN_MGCG | | |
099d66e4 | 1186 | AMD_CG_SUPPORT_JPEG_MGCG | |
d0c39f8c XY |
1187 | AMD_CG_SUPPORT_BIF_MGCG | |
1188 | AMD_CG_SUPPORT_BIF_LS; | |
0377b088 | 1189 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
099d66e4 | 1190 | AMD_PG_SUPPORT_JPEG | |
0377b088 | 1191 | AMD_PG_SUPPORT_VCN_DPG; |
35ef88fa | 1192 | adev->external_rev_id = adev->rev_id + 20; |
5e71e011 | 1193 | break; |
74b5e509 | 1194 | case CHIP_NAVI12: |
dca009e7 XY |
1195 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1196 | AMD_CG_SUPPORT_GFX_MGLS | | |
1197 | AMD_CG_SUPPORT_GFX_CGCG | | |
1198 | AMD_CG_SUPPORT_GFX_CP_LS | | |
5211c37a | 1199 | AMD_CG_SUPPORT_GFX_RLC_LS | |
fbe0bc57 | 1200 | AMD_CG_SUPPORT_IH_CG | |
5211c37a | 1201 | AMD_CG_SUPPORT_HDP_MGCG | |
358ab97f XY |
1202 | AMD_CG_SUPPORT_HDP_LS | |
1203 | AMD_CG_SUPPORT_SDMA_MGCG | | |
8b797b3d XY |
1204 | AMD_CG_SUPPORT_SDMA_LS | |
1205 | AMD_CG_SUPPORT_MC_MGCG | | |
ca51678d XY |
1206 | AMD_CG_SUPPORT_MC_LS | |
1207 | AMD_CG_SUPPORT_ATHUB_MGCG | | |
65872e59 | 1208 | AMD_CG_SUPPORT_ATHUB_LS | |
099d66e4 LL |
1209 | AMD_CG_SUPPORT_VCN_MGCG | |
1210 | AMD_CG_SUPPORT_JPEG_MGCG; | |
c1653ea0 | 1211 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
5ef3b8ac | 1212 | AMD_PG_SUPPORT_VCN_DPG | |
099d66e4 | 1213 | AMD_PG_SUPPORT_JPEG | |
1b0443b1 | 1214 | AMD_PG_SUPPORT_ATHUB; |
df5e984c TZ |
1215 | /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, |
1216 | * as a consequence, the rev_id and external_rev_id are wrong. | |
1217 | * workaround it by hardcoding rev_id to 0 (default value). | |
1218 | */ | |
1219 | if (amdgpu_sriov_vf(adev)) | |
1220 | adev->rev_id = 0; | |
74b5e509 XY |
1221 | adev->external_rev_id = adev->rev_id + 0xa; |
1222 | break; | |
117910ed | 1223 | case CHIP_SIENNA_CICHLID: |
00194def LG |
1224 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1225 | AMD_CG_SUPPORT_GFX_CGCG | | |
1d712be9 | 1226 | AMD_CG_SUPPORT_GFX_CGLS | |
00194def | 1227 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
98f8ea29 | 1228 | AMD_CG_SUPPORT_MC_MGCG | |
00194def | 1229 | AMD_CG_SUPPORT_VCN_MGCG | |
ca36461f KF |
1230 | AMD_CG_SUPPORT_JPEG_MGCG | |
1231 | AMD_CG_SUPPORT_HDP_MGCG | | |
3a32c25a | 1232 | AMD_CG_SUPPORT_HDP_LS | |
bcc8367f KF |
1233 | AMD_CG_SUPPORT_IH_CG | |
1234 | AMD_CG_SUPPORT_MC_LS; | |
b467c4f5 | 1235 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
d00b0fa9 | 1236 | AMD_PG_SUPPORT_VCN_DPG | |
b794616d | 1237 | AMD_PG_SUPPORT_JPEG | |
1b0443b1 LG |
1238 | AMD_PG_SUPPORT_ATHUB | |
1239 | AMD_PG_SUPPORT_MMHUB; | |
c45fbe1b JZ |
1240 | if (amdgpu_sriov_vf(adev)) { |
1241 | /* hypervisor control CG and PG enablement */ | |
1242 | adev->cg_flags = 0; | |
1243 | adev->pg_flags = 0; | |
1244 | } | |
117910ed LG |
1245 | adev->external_rev_id = adev->rev_id + 0x28; |
1246 | break; | |
543aa259 | 1247 | case CHIP_NAVY_FLOUNDER: |
40582e67 JC |
1248 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1249 | AMD_CG_SUPPORT_GFX_CGCG | | |
1d712be9 | 1250 | AMD_CG_SUPPORT_GFX_CGLS | |
40582e67 JC |
1251 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
1252 | AMD_CG_SUPPORT_VCN_MGCG | | |
92c73756 JC |
1253 | AMD_CG_SUPPORT_JPEG_MGCG | |
1254 | AMD_CG_SUPPORT_MC_MGCG | | |
4759f887 JC |
1255 | AMD_CG_SUPPORT_MC_LS | |
1256 | AMD_CG_SUPPORT_HDP_MGCG | | |
85e7151b JC |
1257 | AMD_CG_SUPPORT_HDP_LS | |
1258 | AMD_CG_SUPPORT_IH_CG; | |
c6e9dd0e | 1259 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
00740df9 | 1260 | AMD_PG_SUPPORT_VCN_DPG | |
47fc894a JC |
1261 | AMD_PG_SUPPORT_JPEG | |
1262 | AMD_PG_SUPPORT_ATHUB | | |
1263 | AMD_PG_SUPPORT_MMHUB; | |
543aa259 JC |
1264 | adev->external_rev_id = adev->rev_id + 0x32; |
1265 | break; | |
1266 | ||
026570e6 | 1267 | case CHIP_VANGOGH: |
c345c89b | 1268 | adev->apu_flags |= AMD_APU_IS_VANGOGH; |
51a7e938 JS |
1269 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1270 | AMD_CG_SUPPORT_GFX_MGLS | | |
1271 | AMD_CG_SUPPORT_GFX_CP_LS | | |
1272 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1273 | AMD_CG_SUPPORT_GFX_CGCG | | |
ac0dc4c5 HR |
1274 | AMD_CG_SUPPORT_GFX_CGLS | |
1275 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
07f9c22f | 1276 | AMD_CG_SUPPORT_GFX_3D_CGLS | |
0ebce667 JS |
1277 | AMD_CG_SUPPORT_MC_MGCG | |
1278 | AMD_CG_SUPPORT_MC_LS | | |
a3964ec4 | 1279 | AMD_CG_SUPPORT_GFX_FGCG | |
07f9c22f | 1280 | AMD_CG_SUPPORT_VCN_MGCG | |
ef9bcfde | 1281 | AMD_CG_SUPPORT_SDMA_MGCG | |
ec0f72cb | 1282 | AMD_CG_SUPPORT_SDMA_LS | |
07f9c22f BZ |
1283 | AMD_CG_SUPPORT_JPEG_MGCG; |
1284 | adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | | |
1285 | AMD_PG_SUPPORT_VCN | | |
1286 | AMD_PG_SUPPORT_VCN_DPG | | |
1287 | AMD_PG_SUPPORT_JPEG; | |
c345c89b HR |
1288 | if (adev->apu_flags & AMD_APU_IS_VANGOGH) |
1289 | adev->external_rev_id = adev->rev_id + 0x01; | |
026570e6 | 1290 | break; |
550c58e0 | 1291 | case CHIP_DIMGREY_CAVEFISH: |
583e5a5e TZ |
1292 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1293 | AMD_CG_SUPPORT_GFX_CGCG | | |
1d712be9 | 1294 | AMD_CG_SUPPORT_GFX_CGLS | |
583e5a5e TZ |
1295 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
1296 | AMD_CG_SUPPORT_VCN_MGCG | | |
135333a0 TZ |
1297 | AMD_CG_SUPPORT_JPEG_MGCG | |
1298 | AMD_CG_SUPPORT_MC_MGCG | | |
2c70c332 TZ |
1299 | AMD_CG_SUPPORT_MC_LS | |
1300 | AMD_CG_SUPPORT_HDP_MGCG | | |
8e3bfb99 TZ |
1301 | AMD_CG_SUPPORT_HDP_LS | |
1302 | AMD_CG_SUPPORT_IH_CG; | |
d5bc1579 | 1303 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
cc6161aa | 1304 | AMD_PG_SUPPORT_VCN_DPG | |
73da8e86 TZ |
1305 | AMD_PG_SUPPORT_JPEG | |
1306 | AMD_PG_SUPPORT_ATHUB | | |
1307 | AMD_PG_SUPPORT_MMHUB; | |
550c58e0 TZ |
1308 | adev->external_rev_id = adev->rev_id + 0x3c; |
1309 | break; | |
8573035a | 1310 | case CHIP_BEIGE_GOBY: |
bc6bd46b TZ |
1311 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1312 | AMD_CG_SUPPORT_GFX_CGCG | | |
d69d278f | 1313 | AMD_CG_SUPPORT_GFX_CGLS | |
5d36b865 TZ |
1314 | AMD_CG_SUPPORT_GFX_3D_CGCG | |
1315 | AMD_CG_SUPPORT_MC_MGCG | | |
170c193f TZ |
1316 | AMD_CG_SUPPORT_MC_LS | |
1317 | AMD_CG_SUPPORT_HDP_MGCG | | |
a764bef3 | 1318 | AMD_CG_SUPPORT_HDP_LS | |
e47e4c0e VG |
1319 | AMD_CG_SUPPORT_IH_CG | |
1320 | AMD_CG_SUPPORT_VCN_MGCG; | |
f703d4b6 | 1321 | adev->pg_flags = AMD_PG_SUPPORT_VCN | |
147de218 TZ |
1322 | AMD_PG_SUPPORT_VCN_DPG | |
1323 | AMD_PG_SUPPORT_ATHUB | | |
1324 | AMD_PG_SUPPORT_MMHUB; | |
8573035a CG |
1325 | adev->external_rev_id = adev->rev_id + 0x46; |
1326 | break; | |
e7990721 | 1327 | case CHIP_YELLOW_CARP: |
9c6c48e6 AL |
1328 | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | |
1329 | AMD_CG_SUPPORT_GFX_MGLS | | |
1330 | AMD_CG_SUPPORT_GFX_CGCG | | |
1331 | AMD_CG_SUPPORT_GFX_CGLS | | |
1332 | AMD_CG_SUPPORT_GFX_3D_CGCG | | |
1333 | AMD_CG_SUPPORT_GFX_3D_CGLS | | |
1334 | AMD_CG_SUPPORT_GFX_RLC_LS | | |
1335 | AMD_CG_SUPPORT_GFX_CP_LS | | |
83ae09b5 AL |
1336 | AMD_CG_SUPPORT_GFX_FGCG | |
1337 | AMD_CG_SUPPORT_MC_MGCG | | |
f1e9aa65 | 1338 | AMD_CG_SUPPORT_MC_LS | |
6bd95572 AL |
1339 | AMD_CG_SUPPORT_SDMA_LS | |
1340 | AMD_CG_SUPPORT_HDP_MGCG | | |
b7dd14c7 AL |
1341 | AMD_CG_SUPPORT_HDP_LS | |
1342 | AMD_CG_SUPPORT_ATHUB_MGCG | | |
db72c3fa AL |
1343 | AMD_CG_SUPPORT_ATHUB_LS | |
1344 | AMD_CG_SUPPORT_IH_CG; | |
fd0a316e | 1345 | adev->pg_flags = AMD_PG_SUPPORT_GFX_PG; |
e7990721 AL |
1346 | adev->external_rev_id = adev->rev_id + 0x01; |
1347 | break; | |
c6b6a421 HZ |
1348 | default: |
1349 | /* FIXME: not supported yet */ | |
1350 | return -EINVAL; | |
1351 | } | |
1352 | ||
7bd939d0 LG |
1353 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) |
1354 | adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | | |
1355 | AMD_PG_SUPPORT_VCN_DPG | | |
1356 | AMD_PG_SUPPORT_JPEG); | |
1357 | ||
b05b6903 JZ |
1358 | if (amdgpu_sriov_vf(adev)) { |
1359 | amdgpu_virt_init_setting(adev); | |
1360 | xgpu_nv_mailbox_set_irq_funcs(adev); | |
1361 | } | |
1362 | ||
c6b6a421 HZ |
1363 | return 0; |
1364 | } | |
1365 | ||
1366 | static int nv_common_late_init(void *handle) | |
1367 | { | |
b05b6903 JZ |
1368 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1369 | ||
ed9d2053 | 1370 | if (amdgpu_sriov_vf(adev)) { |
b05b6903 | 1371 | xgpu_nv_mailbox_get_irq(adev); |
ed9d2053 BZ |
1372 | amdgpu_virt_update_sriov_video_codec(adev, |
1373 | sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), | |
1374 | sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); | |
1375 | } | |
b05b6903 | 1376 | |
c6b6a421 HZ |
1377 | return 0; |
1378 | } | |
1379 | ||
1380 | static int nv_common_sw_init(void *handle) | |
1381 | { | |
b05b6903 JZ |
1382 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1383 | ||
1384 | if (amdgpu_sriov_vf(adev)) | |
1385 | xgpu_nv_mailbox_add_irq_id(adev); | |
1386 | ||
c6b6a421 HZ |
1387 | return 0; |
1388 | } | |
1389 | ||
1390 | static int nv_common_sw_fini(void *handle) | |
1391 | { | |
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | static int nv_common_hw_init(void *handle) | |
1396 | { | |
1397 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1398 | ||
1399 | /* enable pcie gen2/3 link */ | |
1400 | nv_pcie_gen3_enable(adev); | |
1401 | /* enable aspm */ | |
1402 | nv_program_aspm(adev); | |
1403 | /* setup nbio registers */ | |
bebc0762 | 1404 | adev->nbio.funcs->init_registers(adev); |
923c087a YZ |
1405 | /* remap HDP registers to a hole in mmio space, |
1406 | * for the purpose of expose those registers | |
1407 | * to process space | |
1408 | */ | |
1409 | if (adev->nbio.funcs->remap_hdp_registers) | |
1410 | adev->nbio.funcs->remap_hdp_registers(adev); | |
c6b6a421 HZ |
1411 | /* enable the doorbell aperture */ |
1412 | nv_enable_doorbell_aperture(adev, true); | |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | static int nv_common_hw_fini(void *handle) | |
1418 | { | |
1419 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1420 | ||
1421 | /* disable the doorbell aperture */ | |
1422 | nv_enable_doorbell_aperture(adev, false); | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
1427 | static int nv_common_suspend(void *handle) | |
1428 | { | |
1429 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1430 | ||
1431 | return nv_common_hw_fini(adev); | |
1432 | } | |
1433 | ||
1434 | static int nv_common_resume(void *handle) | |
1435 | { | |
1436 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1437 | ||
1438 | return nv_common_hw_init(adev); | |
1439 | } | |
1440 | ||
1441 | static bool nv_common_is_idle(void *handle) | |
1442 | { | |
1443 | return true; | |
1444 | } | |
1445 | ||
1446 | static int nv_common_wait_for_idle(void *handle) | |
1447 | { | |
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | static int nv_common_soft_reset(void *handle) | |
1452 | { | |
1453 | return 0; | |
1454 | } | |
1455 | ||
c6b6a421 HZ |
1456 | static int nv_common_set_clockgating_state(void *handle, |
1457 | enum amd_clockgating_state state) | |
1458 | { | |
1459 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
1460 | ||
1461 | if (amdgpu_sriov_vf(adev)) | |
1462 | return 0; | |
1463 | ||
1464 | switch (adev->asic_type) { | |
1465 | case CHIP_NAVI10: | |
5e71e011 | 1466 | case CHIP_NAVI14: |
7e17e58b | 1467 | case CHIP_NAVI12: |
117910ed | 1468 | case CHIP_SIENNA_CICHLID: |
543aa259 | 1469 | case CHIP_NAVY_FLOUNDER: |
550c58e0 | 1470 | case CHIP_DIMGREY_CAVEFISH: |
8573035a | 1471 | case CHIP_BEIGE_GOBY: |
bebc0762 | 1472 | adev->nbio.funcs->update_medium_grain_clock_gating(adev, |
a9d4fe2f | 1473 | state == AMD_CG_STATE_GATE); |
bebc0762 | 1474 | adev->nbio.funcs->update_medium_grain_light_sleep(adev, |
a9d4fe2f | 1475 | state == AMD_CG_STATE_GATE); |
bf087285 | 1476 | adev->hdp.funcs->update_clock_gating(adev, |
a9d4fe2f | 1477 | state == AMD_CG_STATE_GATE); |
1001f2a1 LG |
1478 | adev->smuio.funcs->update_rom_clock_gating(adev, |
1479 | state == AMD_CG_STATE_GATE); | |
c6b6a421 HZ |
1480 | break; |
1481 | default: | |
1482 | break; | |
1483 | } | |
1484 | return 0; | |
1485 | } | |
1486 | ||
1487 | static int nv_common_set_powergating_state(void *handle, | |
1488 | enum amd_powergating_state state) | |
1489 | { | |
1490 | /* TODO */ | |
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | static void nv_common_get_clockgating_state(void *handle, u32 *flags) | |
1495 | { | |
1496 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | |
c6b6a421 HZ |
1497 | |
1498 | if (amdgpu_sriov_vf(adev)) | |
1499 | *flags = 0; | |
1500 | ||
bebc0762 | 1501 | adev->nbio.funcs->get_clockgating_state(adev, flags); |
c6b6a421 | 1502 | |
bf087285 | 1503 | adev->hdp.funcs->get_clock_gating_state(adev, flags); |
c6b6a421 | 1504 | |
1001f2a1 LG |
1505 | adev->smuio.funcs->get_clock_gating_state(adev, flags); |
1506 | ||
c6b6a421 HZ |
1507 | return; |
1508 | } | |
1509 | ||
1510 | static const struct amd_ip_funcs nv_common_ip_funcs = { | |
1511 | .name = "nv_common", | |
1512 | .early_init = nv_common_early_init, | |
1513 | .late_init = nv_common_late_init, | |
1514 | .sw_init = nv_common_sw_init, | |
1515 | .sw_fini = nv_common_sw_fini, | |
1516 | .hw_init = nv_common_hw_init, | |
1517 | .hw_fini = nv_common_hw_fini, | |
1518 | .suspend = nv_common_suspend, | |
1519 | .resume = nv_common_resume, | |
1520 | .is_idle = nv_common_is_idle, | |
1521 | .wait_for_idle = nv_common_wait_for_idle, | |
1522 | .soft_reset = nv_common_soft_reset, | |
1523 | .set_clockgating_state = nv_common_set_clockgating_state, | |
1524 | .set_powergating_state = nv_common_set_powergating_state, | |
1525 | .get_clockgating_state = nv_common_get_clockgating_state, | |
1526 | }; |