[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / nbio_v6_1.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu.h"
#include "amdgpu_atombios.h"
#include "nbio_v6_1.h"

#include "nbio/nbio_6_1_default.h"
#include "nbio/nbio_6_1_offset.h"
#include "nbio/nbio_6_1_sh_mask.h"
#include "nbio/nbio_6_1_smn.h"
#include "vega10_enum.h"

static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
{
        u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

	tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
	tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;

	return tmp;
}

static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
{
	if (enable)
		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
			     BIF_FB_EN__FB_READ_EN_MASK |
			     BIF_FB_EN__FB_WRITE_EN_MASK);
	else
		WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
}

static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
				struct amdgpu_ring *ring)
{
	if (!ring || !ring->funcs->emit_wreg)
		WREG32_SOC15_NO_KIQ(NBIO, 0,
				    mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
				    0);
	else
		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
			NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
}

static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
{
	return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
}

static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
			bool use_doorbell, int doorbell_index, int doorbell_size)
{
	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

	u32 doorbell_range = RREG32(reg);

	if (use_doorbell) {
		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
	} else
		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

	WREG32(reg, doorbell_range);

}

static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
					       bool enable)
{
	WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
}

static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
							bool enable)
{
	u32 tmp = 0;

	if (enable) {
		tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);

		WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
			     lower_32_bits(adev->doorbell.base));
		WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
			     upper_32_bits(adev->doorbell.base));
	}

	WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
}


static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
					bool use_doorbell, int doorbell_index)
{
	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

	if (use_doorbell) {
		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
						  BIF_IH_DOORBELL_RANGE, SIZE, 6);
	} else
		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

	WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
}

static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
{
	u32 interrupt_cntl;

	/* setup interrupt control */
	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
	interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	 */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
}

static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
						       bool enable)
{
	uint32_t def, data;

	def = data = RREG32_PCIE(smnCPM_CONTROL);
	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
		data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
			 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
			 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
			 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
			 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
			 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
			 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
	} else {
		data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
			  CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
			  CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
			  CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
			  CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
			  CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
			  CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
	}

	if (def != data)
		WREG32_PCIE(smnCPM_CONTROL, data);
}

static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
						      bool enable)
{
	uint32_t def, data;

	def = data = RREG32_PCIE(smnPCIE_CNTL2);
	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
			 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
			 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
	} else {
		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
			  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
			  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
	}

	if (def != data)
		WREG32_PCIE(smnPCIE_CNTL2, data);
}

static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
					    u32 *flags)
{
	int data;

	/* AMD_CG_SUPPORT_BIF_MGCG */
	data = RREG32_PCIE(smnCPM_CONTROL);
	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
		*flags |= AMD_CG_SUPPORT_BIF_MGCG;

	/* AMD_CG_SUPPORT_BIF_LS */
	data = RREG32_PCIE(smnPCIE_CNTL2);
	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
		*flags |= AMD_CG_SUPPORT_BIF_LS;
}

static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
{
	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
}

static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
{
	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
}

static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
{
	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
}

static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
{
	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
}

const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
	.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
	.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
	.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
	.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
	.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
	.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
	.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
	.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
	.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
};

static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
{
	uint32_t def, data;

	def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);

	if (def != data)
		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);

	def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);

	if (def != data)
		WREG32_PCIE(smnPCIE_CI_CNTL, data);
}

const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
	.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
	.get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
	.get_rev_id = nbio_v6_1_get_rev_id,
	.mc_access_enable = nbio_v6_1_mc_access_enable,
	.hdp_flush = nbio_v6_1_hdp_flush,
	.get_memsize = nbio_v6_1_get_memsize,
	.sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
	.enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
	.enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
	.ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
	.update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
	.update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
	.get_clockgating_state = nbio_v6_1_get_clockgating_state,
	.ih_control = nbio_v6_1_ih_control,
	.init_registers = nbio_v6_1_init_registers,
};
Commit	Line	Data
c1d83da9 JZ	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu.h"
	24	#include "amdgpu_atombios.h"
	25	#include "nbio_v6_1.h"
	26
f0a58aa3 FX	27	#include "nbio/nbio_6_1_default.h"
	28	#include "nbio/nbio_6_1_offset.h"
	29	#include "nbio/nbio_6_1_sh_mask.h"
a0bb79e2	30	#include "nbio/nbio_6_1_smn.h"
fb960bd2	31	#include "vega10_enum.h"
c1d83da9	32
bf383fb6	33	static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
c1d83da9	34	{
db0c4d26	35	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
c1d83da9 JZ	36
	37	tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
	38	tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
	39
	40	return tmp;
	41	}
	42
bf383fb6	43	static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
c1d83da9 JZ	44	{
c1d83da9 JZ	45	if (enable)
db0c4d26 TSD	46	WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
	47	BIF_FB_EN__FB_READ_EN_MASK \|
	48	BIF_FB_EN__FB_WRITE_EN_MASK);
c1d83da9	49	else
db0c4d26	50	WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
c1d83da9 JZ	51	}
c1d83da9 JZ	52
69882565 CK	53	static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
69882565 CK	54	struct amdgpu_ring *ring)
c1d83da9	55	{
69882565 CK	56	if (!ring \|\| !ring->funcs->emit_wreg)
	57	WREG32_SOC15_NO_KIQ(NBIO, 0,
	58	mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
	59	0);
	60	else
	61	amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
	62	NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
c1d83da9 JZ	63	}
c1d83da9 JZ	64
bf383fb6	65	static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
c1d83da9	66	{
db0c4d26	67	return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
c1d83da9 JZ	68	}
c1d83da9 JZ	69
bf383fb6	70	static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
8987e2e2	71	bool use_doorbell, int doorbell_index, int doorbell_size)
c1d83da9	72	{
946a4d5b SL	73	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
	74	SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
	75
	76	u32 doorbell_range = RREG32(reg);
c1d83da9 JZ	77
	78	if (use_doorbell) {
	79	doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
8987e2e2	80	doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
c1d83da9 JZ	81	} else
	82	doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
	83
946a4d5b SL	84	WREG32(reg, doorbell_range);
946a4d5b SL	85
c1d83da9 JZ	86	}
c1d83da9 JZ	87
bf383fb6 AD	88	static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
bf383fb6 AD	89	bool enable)
c1d83da9	90	{
db0c4d26	91	WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
c1d83da9 JZ	92	}
c1d83da9 JZ	93
bf383fb6 AD	94	static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
bf383fb6 AD	95	bool enable)
c1d83da9 JZ	96	{
	97	u32 tmp = 0;
	98
	99	if (enable) {
	100	tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) \|
db0c4d26 TSD	101	REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) \|
db0c4d26 TSD	102	REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
c1d83da9	103
db0c4d26 TSD	104	WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
	105	lower_32_bits(adev->doorbell.base));
	106	WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
	107	upper_32_bits(adev->doorbell.base));
c1d83da9 JZ	108	}
c1d83da9 JZ	109
db0c4d26	110	WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
c1d83da9 JZ	111	}
	112
	113
bf383fb6 AD	114	static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
bf383fb6 AD	115	bool use_doorbell, int doorbell_index)
c1d83da9	116	{
db0c4d26	117	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
c1d83da9 JZ	118
	119	if (use_doorbell) {
	120	ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
1ae64cec CK	121	ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
1ae64cec CK	122	BIF_IH_DOORBELL_RANGE, SIZE, 6);
c1d83da9 JZ	123	} else
	124	ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
	125
db0c4d26	126	WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
c1d83da9 JZ	127	}
c1d83da9 JZ	128
bf383fb6	129	static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
c1d83da9 JZ	130	{
	131	u32 interrupt_cntl;
	132
	133	/* setup interrupt control */
92e71b06	134	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
db0c4d26	135	interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
c1d83da9 JZ	136	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
	137	* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
	138	*/
	139	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
	140	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
	141	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
db0c4d26	142	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
c1d83da9 JZ	143	}
c1d83da9 JZ	144
bf383fb6 AD	145	static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
bf383fb6 AD	146	bool enable)
c1d83da9 JZ	147	{
	148	uint32_t def, data;
	149
	150	def = data = RREG32_PCIE(smnCPM_CONTROL);
	151	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
	152	data \|= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK \|
	153	CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK \|
	154	CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK \|
	155	CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK \|
	156	CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK \|
	157	CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK \|
	158	CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
	159	} else {
	160	data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK \|
	161	CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK \|
	162	CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK \|
	163	CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK \|
	164	CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK \|
	165	CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK \|
	166	CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
	167	}
	168
	169	if (def != data)
	170	WREG32_PCIE(smnCPM_CONTROL, data);
	171	}
	172
bf383fb6 AD	173	static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
bf383fb6 AD	174	bool enable)
c1d83da9 JZ	175	{
	176	uint32_t def, data;
	177
	178	def = data = RREG32_PCIE(smnPCIE_CNTL2);
	179	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
	180	data \|= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK \|
	181	PCIE_CNTL2__MST_MEM_LS_EN_MASK \|
	182	PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
	183	} else {
	184	data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK \|
	185	PCIE_CNTL2__MST_MEM_LS_EN_MASK \|
	186	PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
	187	}
	188
	189	if (def != data)
	190	WREG32_PCIE(smnPCIE_CNTL2, data);
	191	}
	192
bf383fb6 AD	193	static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
bf383fb6 AD	194	u32 *flags)
e96487a6 HR	195	{
	196	int data;
	197
	198	/* AMD_CG_SUPPORT_BIF_MGCG */
	199	data = RREG32_PCIE(smnCPM_CONTROL);
	200	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
	201	*flags \|= AMD_CG_SUPPORT_BIF_MGCG;
	202
	203	/* AMD_CG_SUPPORT_BIF_LS */
	204	data = RREG32_PCIE(smnPCIE_CNTL2);
	205	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
	206	*flags \|= AMD_CG_SUPPORT_BIF_LS;
	207	}
	208
74e1d67c	209	static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
946a4d5b SL	210	{
	211	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
	212	}
	213
74e1d67c	214	static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
946a4d5b SL	215	{
	216	return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
	217	}
	218
74e1d67c	219	static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
946a4d5b	220	{
bd08a8d9	221	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
946a4d5b SL	222	}
946a4d5b SL	223
74e1d67c	224	static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
946a4d5b	225	{
bd08a8d9	226	return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
946a4d5b SL	227	}
946a4d5b SL	228
bebc0762	229	const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
c6622f3a DA	230	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
	231	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
	232	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
	233	.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
	234	.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
	235	.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
	236	.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
	237	.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
	238	.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
	239	.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
	240	.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
	241	.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
	242	};
	243
bf383fb6	244	static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
12097c6d AD	245	{
	246	uint32_t def, data;
	247
	248	def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
	249	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
	250	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
	251
	252	if (def != data)
	253	WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
40978ac6 AD	254
	255	def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
	256	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
	257
	258	if (def != data)
	259	WREG32_PCIE(smnPCIE_CI_CNTL, data);
12097c6d	260	}
bf383fb6 AD	261
bf383fb6 AD	262	const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
bf383fb6 AD	263	.get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
	264	.get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
	265	.get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
	266	.get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
	267	.get_rev_id = nbio_v6_1_get_rev_id,
bf383fb6 AD	268	.mc_access_enable = nbio_v6_1_mc_access_enable,
	269	.hdp_flush = nbio_v6_1_hdp_flush,
	270	.get_memsize = nbio_v6_1_get_memsize,
	271	.sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
	272	.enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
	273	.enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
	274	.ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
	275	.update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
	276	.update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
	277	.get_clockgating_state = nbio_v6_1_get_clockgating_state,
	278	.ih_control = nbio_v6_1_ih_control,
	279	.init_registers = nbio_v6_1_init_registers,
bf383fb6	280	};