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c9c9de93 XY |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include "amdgpu.h" | |
f0a58aa3 FX |
25 | #include "nbio/nbio_6_1_offset.h" |
26 | #include "nbio/nbio_6_1_sh_mask.h" | |
cde5c34f FX |
27 | #include "gc/gc_9_0_offset.h" |
28 | #include "gc/gc_9_0_sh_mask.h" | |
78d48112 | 29 | #include "mp/mp_9_0_offset.h" |
c9c9de93 | 30 | #include "soc15.h" |
f98b617e | 31 | #include "vega10_ih.h" |
c9c9de93 XY |
32 | #include "soc15_common.h" |
33 | #include "mxgpu_ai.h" | |
34 | ||
35 | static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev) | |
36 | { | |
48527e52 | 37 | WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); |
c9c9de93 XY |
38 | } |
39 | ||
40 | static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) | |
41 | { | |
48527e52 ML |
42 | WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); |
43 | } | |
c9c9de93 | 44 | |
48527e52 ML |
45 | /* |
46 | * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine | |
47 | * RCV_MSG_VALID filed of BIF_BX_PF0_MAILBOX_CONTROL must already be set to 1 | |
48 | * by host. | |
49 | * | |
50 | * if called no in IRQ routine, this peek_msg cannot guaranteed to return the | |
51 | * correct value since it doesn't return the RCV_DW0 under the case that | |
52 | * RCV_MSG_VALID is set by host. | |
53 | */ | |
54 | static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev) | |
55 | { | |
56 | return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, | |
57 | mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0)); | |
c9c9de93 XY |
58 | } |
59 | ||
48527e52 | 60 | |
c9c9de93 XY |
61 | static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev, |
62 | enum idh_event event) | |
63 | { | |
64 | u32 reg; | |
c9c9de93 XY |
65 | |
66 | reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, | |
67 | mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0)); | |
68 | if (reg != event) | |
69 | return -ENOENT; | |
70 | ||
71 | xgpu_ai_mailbox_send_ack(adev); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
48527e52 ML |
76 | static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) { |
77 | return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; | |
78 | } | |
79 | ||
c9c9de93 XY |
80 | static int xgpu_ai_poll_ack(struct amdgpu_device *adev) |
81 | { | |
48527e52 ML |
82 | int timeout = AI_MAILBOX_POLL_ACK_TIMEDOUT; |
83 | u8 reg; | |
84 | ||
85 | do { | |
86 | reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE); | |
87 | if (reg & 2) | |
88 | return 0; | |
c9c9de93 | 89 | |
17b2e332 ML |
90 | mdelay(5); |
91 | timeout -= 5; | |
48527e52 | 92 | } while (timeout > 1); |
c9c9de93 | 93 | |
48527e52 | 94 | pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT); |
c9c9de93 | 95 | |
48527e52 | 96 | return -ETIME; |
c9c9de93 XY |
97 | } |
98 | ||
94b4fd72 | 99 | static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event) |
c9c9de93 | 100 | { |
48527e52 | 101 | int r, timeout = AI_MAILBOX_POLL_MSG_TIMEDOUT; |
c9c9de93 | 102 | |
48527e52 | 103 | do { |
c9c9de93 | 104 | r = xgpu_ai_mailbox_rcv_msg(adev, event); |
48527e52 ML |
105 | if (!r) |
106 | return 0; | |
c9c9de93 | 107 | |
48527e52 ML |
108 | msleep(10); |
109 | timeout -= 10; | |
110 | } while (timeout > 1); | |
111 | ||
112 | pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r); | |
113 | ||
114 | return -ETIME; | |
c9c9de93 XY |
115 | } |
116 | ||
89041940 GW |
117 | static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev, |
118 | enum idh_request req, u32 data1, u32 data2, u32 data3) { | |
119 | u32 reg; | |
c9c9de93 | 120 | int r; |
48527e52 ML |
121 | uint8_t trn; |
122 | ||
123 | /* IMPORTANT: | |
124 | * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK | |
125 | * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK | |
126 | * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_ai_poll_ack() | |
127 | * will return immediatly | |
128 | */ | |
129 | do { | |
130 | xgpu_ai_mailbox_set_valid(adev, false); | |
131 | trn = xgpu_ai_peek_ack(adev); | |
132 | if (trn) { | |
36b3f84a | 133 | pr_err("trn=%x ACK should not assert! wait again !\n", trn); |
48527e52 ML |
134 | msleep(1); |
135 | } | |
136 | } while(trn); | |
c9c9de93 | 137 | |
89041940 GW |
138 | reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, |
139 | mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0)); | |
140 | reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0, | |
141 | MSGBUF_DATA, req); | |
142 | WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), | |
143 | reg); | |
144 | WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), | |
145 | data1); | |
146 | WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), | |
147 | data2); | |
148 | WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), | |
149 | data3); | |
150 | ||
151 | xgpu_ai_mailbox_set_valid(adev, true); | |
c9c9de93 XY |
152 | |
153 | /* start to poll ack */ | |
154 | r = xgpu_ai_poll_ack(adev); | |
155 | if (r) | |
17b2e332 | 156 | pr_err("Doesn't get ack from pf, continue\n"); |
c9c9de93 XY |
157 | |
158 | xgpu_ai_mailbox_set_valid(adev, false); | |
89041940 GW |
159 | } |
160 | ||
161 | static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, | |
162 | enum idh_request req) | |
163 | { | |
164 | int r; | |
165 | ||
166 | xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0); | |
c9c9de93 XY |
167 | |
168 | /* start to check msg if request is idh_req_gpu_init_access */ | |
169 | if (req == IDH_REQ_GPU_INIT_ACCESS || | |
170 | req == IDH_REQ_GPU_FINI_ACCESS || | |
171 | req == IDH_REQ_GPU_RESET_ACCESS) { | |
94b4fd72 | 172 | r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); |
17b2e332 ML |
173 | if (r) { |
174 | pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n"); | |
c9c9de93 | 175 | return r; |
17b2e332 | 176 | } |
2dc8f81e | 177 | /* Retrieve checksum from mailbox2 */ |
d3c117e5 | 178 | if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) { |
2dc8f81e HC |
179 | adev->virt.fw_reserve.checksum_key = |
180 | RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, | |
181 | mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2)); | |
182 | } | |
c9c9de93 XY |
183 | } |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
f98b617e ML |
188 | static int xgpu_ai_request_reset(struct amdgpu_device *adev) |
189 | { | |
3aa883ac JZ |
190 | int ret, i = 0; |
191 | ||
192 | while (i < AI_MAILBOX_POLL_MSG_REP_MAX) { | |
193 | ret = xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS); | |
194 | if (!ret) | |
195 | break; | |
196 | i++; | |
197 | } | |
198 | ||
199 | return ret; | |
f98b617e ML |
200 | } |
201 | ||
c9c9de93 XY |
202 | static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev, |
203 | bool init) | |
204 | { | |
205 | enum idh_request req; | |
206 | ||
207 | req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS; | |
208 | return xgpu_ai_send_access_requests(adev, req); | |
209 | } | |
210 | ||
211 | static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev, | |
212 | bool init) | |
213 | { | |
214 | enum idh_request req; | |
215 | int r = 0; | |
216 | ||
217 | req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS; | |
218 | r = xgpu_ai_send_access_requests(adev, req); | |
219 | ||
220 | return r; | |
221 | } | |
222 | ||
f98b617e ML |
223 | static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev, |
224 | struct amdgpu_irq_src *source, | |
225 | struct amdgpu_iv_entry *entry) | |
226 | { | |
034b6867 | 227 | DRM_DEBUG("get ack intr and do nothing.\n"); |
f98b617e ML |
228 | return 0; |
229 | } | |
230 | ||
231 | static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev, | |
232 | struct amdgpu_irq_src *source, | |
233 | unsigned type, | |
234 | enum amdgpu_interrupt_state state) | |
235 | { | |
236 | u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); | |
237 | ||
238 | tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN, | |
239 | (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); | |
240 | WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
245 | static void xgpu_ai_mailbox_flr_work(struct work_struct *work) | |
246 | { | |
247 | struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work); | |
248 | struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); | |
48527e52 | 249 | int timeout = AI_MAILBOX_POLL_FLR_TIMEDOUT; |
48527e52 ML |
250 | |
251 | /* block amdgpu_gpu_recover till msg FLR COMPLETE received, | |
252 | * otherwise the mailbox msg will be ruined/reseted by | |
253 | * the VF FLR. | |
48527e52 | 254 | */ |
798c5115 | 255 | if (!down_write_trylock(&adev->reset_sem)) |
6049db43 DL |
256 | return; |
257 | ||
3c2a01cb | 258 | amdgpu_virt_fini_data_exchange(adev); |
6049db43 | 259 | atomic_set(&adev->in_gpu_reset, 1); |
f1403342 | 260 | |
48527e52 ML |
261 | do { |
262 | if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) | |
263 | goto flr_done; | |
264 | ||
265 | msleep(10); | |
266 | timeout -= 10; | |
267 | } while (timeout > 1); | |
268 | ||
269 | flr_done: | |
6049db43 | 270 | atomic_set(&adev->in_gpu_reset, 0); |
798c5115 | 271 | up_write(&adev->reset_sem); |
48527e52 ML |
272 | |
273 | /* Trigger recovery for world switch failure if no TDR */ | |
2c11ee6a | 274 | if (amdgpu_device_should_recover_gpu(adev) |
2a9787dc LC |
275 | && (!amdgpu_device_has_job_running(adev) || |
276 | adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT)) | |
12938fad | 277 | amdgpu_device_gpu_recover(adev, NULL); |
f98b617e ML |
278 | } |
279 | ||
280 | static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, | |
281 | struct amdgpu_irq_src *src, | |
282 | unsigned type, | |
283 | enum amdgpu_interrupt_state state) | |
284 | { | |
285 | u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); | |
286 | ||
287 | tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN, | |
288 | (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); | |
289 | WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, | |
295 | struct amdgpu_irq_src *source, | |
296 | struct amdgpu_iv_entry *entry) | |
297 | { | |
48527e52 ML |
298 | enum idh_event event = xgpu_ai_mailbox_peek_msg(adev); |
299 | ||
300 | switch (event) { | |
301 | case IDH_FLR_NOTIFICATION: | |
302 | if (amdgpu_sriov_runtime(adev)) | |
303 | schedule_work(&adev->virt.flr_work); | |
304 | break; | |
b6818520 TH |
305 | case IDH_QUERY_ALIVE: |
306 | xgpu_ai_mailbox_send_ack(adev); | |
307 | break; | |
48527e52 ML |
308 | /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore |
309 | * it byfar since that polling thread will handle it, | |
310 | * other msg like flr complete is not handled here. | |
34a4d2bf | 311 | */ |
48527e52 ML |
312 | case IDH_CLR_MSG_BUF: |
313 | case IDH_FLR_NOTIFICATION_CMPL: | |
314 | case IDH_READY_TO_ACCESS_GPU: | |
315 | default: | |
316 | break; | |
0c63e113 | 317 | } |
f98b617e ML |
318 | |
319 | return 0; | |
320 | } | |
321 | ||
322 | static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_ack_irq_funcs = { | |
323 | .set = xgpu_ai_set_mailbox_ack_irq, | |
324 | .process = xgpu_ai_mailbox_ack_irq, | |
325 | }; | |
326 | ||
327 | static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_rcv_irq_funcs = { | |
328 | .set = xgpu_ai_set_mailbox_rcv_irq, | |
329 | .process = xgpu_ai_mailbox_rcv_irq, | |
330 | }; | |
331 | ||
332 | void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev) | |
333 | { | |
334 | adev->virt.ack_irq.num_types = 1; | |
335 | adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; | |
336 | adev->virt.rcv_irq.num_types = 1; | |
337 | adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs; | |
338 | } | |
339 | ||
340 | int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev) | |
341 | { | |
342 | int r; | |
343 | ||
3760f76c | 344 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); |
f98b617e ML |
345 | if (r) |
346 | return r; | |
347 | ||
3760f76c | 348 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); |
f98b617e ML |
349 | if (r) { |
350 | amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); | |
351 | return r; | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev) | |
358 | { | |
359 | int r; | |
360 | ||
361 | r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); | |
362 | if (r) | |
363 | return r; | |
364 | r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); | |
365 | if (r) { | |
366 | amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); | |
367 | return r; | |
368 | } | |
369 | ||
370 | INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work); | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev) | |
376 | { | |
377 | amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); | |
378 | amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); | |
379 | } | |
380 | ||
c9c9de93 XY |
381 | const struct amdgpu_virt_ops xgpu_ai_virt_ops = { |
382 | .req_full_gpu = xgpu_ai_request_full_gpu_access, | |
383 | .rel_full_gpu = xgpu_ai_release_full_gpu_access, | |
f98b617e | 384 | .reset_gpu = xgpu_ai_request_reset, |
b5914238 | 385 | .wait_reset = NULL, |
89041940 | 386 | .trans_msg = xgpu_ai_mailbox_trans_msg, |
c9c9de93 | 387 | }; |