[linux-block.git] / drivers / gpu / drm / amd / amdgpu / jpeg_v3_0.c

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "amdgpu.h"
#include "amdgpu_jpeg.h"
#include "amdgpu_pm.h"
#include "soc15.h"
#include "soc15d.h"
#include "jpeg_v2_0.h"

#include "vcn/vcn_3_0_0_offset.h"
#include "vcn/vcn_3_0_0_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"

#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET	0x401f

static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
static int jpeg_v3_0_set_powergating_state(void *handle,
				enum amd_powergating_state state);

/**
 * jpeg_v3_0_early_init - set function pointers
 *
 * @handle: amdgpu_device pointer
 *
 * Set ring and irq function pointers
 */
static int jpeg_v3_0_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	u32 harvest;

	switch (adev->ip_versions[UVD_HWIP][0]) {
	case IP_VERSION(3, 1, 1):
		break;
	default:
		harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
		if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
			return -ENOENT;
		break;
	}

	adev->jpeg.num_jpeg_inst = 1;

	jpeg_v3_0_set_dec_ring_funcs(adev);
	jpeg_v3_0_set_irq_funcs(adev);

	return 0;
}

/**
 * jpeg_v3_0_sw_init - sw init for JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * Load firmware and sw initialization
 */
static int jpeg_v3_0_sw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct amdgpu_ring *ring;
	int r;

	/* JPEG TRAP */
	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
		VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
	if (r)
		return r;

	r = amdgpu_jpeg_sw_init(adev);
	if (r)
		return r;

	r = amdgpu_jpeg_resume(adev);
	if (r)
		return r;

	ring = &adev->jpeg.inst->ring_dec;
	ring->use_doorbell = true;
	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
	sprintf(ring->name, "jpeg_dec");
	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
			     AMDGPU_RING_PRIO_DEFAULT, NULL);
	if (r)
		return r;

	adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);

	return 0;
}

/**
 * jpeg_v3_0_sw_fini - sw fini for JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * JPEG suspend and free up sw allocation
 */
static int jpeg_v3_0_sw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int r;

	r = amdgpu_jpeg_suspend(adev);
	if (r)
		return r;

	r = amdgpu_jpeg_sw_fini(adev);

	return r;
}

/**
 * jpeg_v3_0_hw_init - start and test JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 */
static int jpeg_v3_0_hw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
	int r;

	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
		(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);

	r = amdgpu_ring_test_helper(ring);
	if (r)
		return r;

	DRM_INFO("JPEG decode initialized successfully.\n");

	return 0;
}

/**
 * jpeg_v3_0_hw_fini - stop the hardware block
 *
 * @handle: amdgpu_device pointer
 *
 * Stop the JPEG block, mark ring as not ready any more
 */
static int jpeg_v3_0_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	cancel_delayed_work_sync(&adev->vcn.idle_work);

	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
		jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

	return 0;
}

/**
 * jpeg_v3_0_suspend - suspend JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * HW fini and suspend JPEG block
 */
static int jpeg_v3_0_suspend(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int r;

	r = jpeg_v3_0_hw_fini(adev);
	if (r)
		return r;

	r = amdgpu_jpeg_suspend(adev);

	return r;
}

/**
 * jpeg_v3_0_resume - resume JPEG block
 *
 * @handle: amdgpu_device pointer
 *
 * Resume firmware and hw init JPEG block
 */
static int jpeg_v3_0_resume(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int r;

	r = amdgpu_jpeg_resume(adev);
	if (r)
		return r;

	r = jpeg_v3_0_hw_init(adev);

	return r;
}

static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev)
{
	uint32_t data = 0;

	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
		data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
	else
		data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

	data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
	data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);

	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
	data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
		| JPEG_CGC_GATE__JPEG2_DEC_MASK
		| JPEG_CGC_GATE__JPEG_ENC_MASK
		| JPEG_CGC_GATE__JMCIF_MASK
		| JPEG_CGC_GATE__JRBBM_MASK);
	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);

	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
	data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
		| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
		| JPEG_CGC_CTRL__JMCIF_MODE_MASK
		| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
}

static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev)
{
	uint32_t data = 0;

	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
	data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
		|JPEG_CGC_GATE__JPEG2_DEC_MASK
		|JPEG_CGC_GATE__JPEG_ENC_MASK
		|JPEG_CGC_GATE__JMCIF_MASK
		|JPEG_CGC_GATE__JRBBM_MASK);
	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
}

static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)
{
	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
		uint32_t data = 0;
		int r = 0;

		data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);

		r = SOC15_WAIT_ON_RREG(JPEG, 0,
			mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);

		if (r) {
			DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
			return r;
		}
	}

	/* disable anti hang mechanism */
	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);

	/* keep the JPEG in static PG mode */
	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
		~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);

	return 0;
}

static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev)
{
	/* enable anti hang mechanism */
	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
		UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
		~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);

	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
		uint32_t data = 0;
		int r = 0;

		data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
		WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);

		r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
			(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
			UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);

		if (r) {
			DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
			return r;
		}
	}

	return 0;
}

/**
 * jpeg_v3_0_start - start JPEG block
 *
 * @adev: amdgpu_device pointer
 *
 * Setup and start the JPEG block
 */
static int jpeg_v3_0_start(struct amdgpu_device *adev)
{
	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
	int r;

	if (adev->pm.dpm_enabled)
		amdgpu_dpm_enable_jpeg(adev, true);

	/* disable power gating */
	r = jpeg_v3_0_disable_static_power_gating(adev);
	if (r)
		return r;

	/* JPEG disable CGC */
	jpeg_v3_0_disable_clock_gating(adev);

	/* MJPEG global tiling registers */
	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
		adev->gfx.config.gb_addr_config);
	WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,
		adev->gfx.config.gb_addr_config);

	/* enable JMI channel */
	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
		~UVD_JMI_CNTL__SOFT_RESET_MASK);

	/* enable System Interrupt for JRBC */
	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
		JPEG_SYS_INT_EN__DJRBC_MASK,
		~JPEG_SYS_INT_EN__DJRBC_MASK);

	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
		lower_32_bits(ring->gpu_addr));
	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
		upper_32_bits(ring->gpu_addr));
	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

	return 0;
}

/**
 * jpeg_v3_0_stop - stop JPEG block
 *
 * @adev: amdgpu_device pointer
 *
 * stop the JPEG block
 */
static int jpeg_v3_0_stop(struct amdgpu_device *adev)
{
	int r;

	/* reset JMI */
	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
		UVD_JMI_CNTL__SOFT_RESET_MASK,
		~UVD_JMI_CNTL__SOFT_RESET_MASK);

	jpeg_v3_0_enable_clock_gating(adev);

	/* enable power gating */
	r = jpeg_v3_0_enable_static_power_gating(adev);
	if (r)
		return r;

	if (adev->pm.dpm_enabled)
		amdgpu_dpm_enable_jpeg(adev, false);

	return 0;
}

/**
 * jpeg_v3_0_dec_ring_get_rptr - get read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware read pointer
 */
static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
}

/**
 * jpeg_v3_0_dec_ring_get_wptr - get write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware write pointer
 */
static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring->use_doorbell)
		return *ring->wptr_cpu_addr;
	else
		return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
}

/**
 * jpeg_v3_0_dec_ring_set_wptr - set write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the write pointer to the hardware
 */
static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring->use_doorbell) {
		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
	} else {
		WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
	}
}

static bool jpeg_v3_0_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret = 1;

	ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
		UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
		UVD_JRBC_STATUS__RB_JOB_DONE_MASK));

	return ret;
}

static int jpeg_v3_0_wait_for_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
		UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
		UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
}

static int jpeg_v3_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;

	if (enable) {
		if (!jpeg_v3_0_is_idle(handle))
			return -EBUSY;
		jpeg_v3_0_enable_clock_gating(adev);
	} else {
		jpeg_v3_0_disable_clock_gating(adev);
	}

	return 0;
}

static int jpeg_v3_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int ret;

	if(state == adev->jpeg.cur_state)
		return 0;

	if (state == AMD_PG_STATE_GATE)
		ret = jpeg_v3_0_stop(adev);
	else
		ret = jpeg_v3_0_start(adev);

	if(!ret)
		adev->jpeg.cur_state = state;

	return ret;
}

static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					unsigned type,
					enum amdgpu_interrupt_state state)
{
	return 0;
}

static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{
	DRM_DEBUG("IH: JPEG TRAP\n");

	switch (entry->src_id) {
	case VCN_2_0__SRCID__JPEG_DECODE:
		amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
		break;
	default:
		DRM_ERROR("Unhandled interrupt: %d %d\n",
			  entry->src_id, entry->src_data[0]);
		break;
	}

	return 0;
}

static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
	.name = "jpeg_v3_0",
	.early_init = jpeg_v3_0_early_init,
	.late_init = NULL,
	.sw_init = jpeg_v3_0_sw_init,
	.sw_fini = jpeg_v3_0_sw_fini,
	.hw_init = jpeg_v3_0_hw_init,
	.hw_fini = jpeg_v3_0_hw_fini,
	.suspend = jpeg_v3_0_suspend,
	.resume = jpeg_v3_0_resume,
	.is_idle = jpeg_v3_0_is_idle,
	.wait_for_idle = jpeg_v3_0_wait_for_idle,
	.check_soft_reset = NULL,
	.pre_soft_reset = NULL,
	.soft_reset = NULL,
	.post_soft_reset = NULL,
	.set_clockgating_state = jpeg_v3_0_set_clockgating_state,
	.set_powergating_state = jpeg_v3_0_set_powergating_state,
};

static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
	.type = AMDGPU_RING_TYPE_VCN_JPEG,
	.align_mask = 0xf,
	.vmhub = AMDGPU_MMHUB_0,
	.get_rptr = jpeg_v3_0_dec_ring_get_rptr,
	.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
	.set_wptr = jpeg_v3_0_dec_ring_set_wptr,
	.emit_frame_size =
		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
		8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */
		18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */
		8 + 16,
	.emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */
	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
	.insert_nop = jpeg_v2_0_dec_ring_nop,
	.insert_start = jpeg_v2_0_dec_ring_insert_start,
	.insert_end = jpeg_v2_0_dec_ring_insert_end,
	.pad_ib = amdgpu_ring_generic_pad_ib,
	.begin_use = amdgpu_jpeg_ring_begin_use,
	.end_use = amdgpu_jpeg_ring_end_use,
	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
};

static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
{
	adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;
	DRM_INFO("JPEG decode is enabled in VM mode\n");
}

static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {
	.set = jpeg_v3_0_set_interrupt_state,
	.process = jpeg_v3_0_process_interrupt,
};

static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)
{
	adev->jpeg.inst->irq.num_types = 1;
	adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
}

const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_JPEG,
	.major = 3,
	.minor = 0,
	.rev = 0,
	.funcs = &jpeg_v3_0_ip_funcs,
};
Commit	Line	Data
dfd57dbf LL	1	/*
	2	* Copyright 2019 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include "amdgpu.h"
	25	#include "amdgpu_jpeg.h"
	26	#include "amdgpu_pm.h"
	27	#include "soc15.h"
	28	#include "soc15d.h"
	29	#include "jpeg_v2_0.h"
	30
	31	#include "vcn/vcn_3_0_0_offset.h"
	32	#include "vcn/vcn_3_0_0_sh_mask.h"
	33	#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
	34
	35	#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
	36
	37	static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
	38	static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
	39	static int jpeg_v3_0_set_powergating_state(void *handle,
	40	enum amd_powergating_state state);
	41
	42	/**
	43	* jpeg_v3_0_early_init - set function pointers
	44	*
	45	* @handle: amdgpu_device pointer
	46	*
	47	* Set ring and irq function pointers
	48	*/
	49	static int jpeg_v3_0_early_init(void *handle)
	50	{
	51	struct amdgpu_device adev = (struct amdgpu_device )handle;
156589f7	52
37d6b150	53	u32 harvest;
3d417b58	54
37d6b150 TH	55	switch (adev->ip_versions[UVD_HWIP][0]) {
	56	case IP_VERSION(3, 1, 1):
	57	break;
	58	default:
	59	harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
3d417b58 JZ	60	if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
3d417b58 JZ	61	return -ENOENT;
37d6b150	62	break;
3d417b58	63	}
dfd57dbf	64
dfd57dbf LL	65	adev->jpeg.num_jpeg_inst = 1;
	66
	67	jpeg_v3_0_set_dec_ring_funcs(adev);
	68	jpeg_v3_0_set_irq_funcs(adev);
	69
	70	return 0;
	71	}
	72
	73	/**
	74	* jpeg_v3_0_sw_init - sw init for JPEG block
	75	*
	76	* @handle: amdgpu_device pointer
	77	*
	78	* Load firmware and sw initialization
	79	*/
	80	static int jpeg_v3_0_sw_init(void *handle)
	81	{
	82	struct amdgpu_device adev = (struct amdgpu_device )handle;
	83	struct amdgpu_ring *ring;
	84	int r;
	85
	86	/* JPEG TRAP */
	87	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
	88	VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
	89	if (r)
	90	return r;
	91
	92	r = amdgpu_jpeg_sw_init(adev);
	93	if (r)
	94	return r;
	95
	96	r = amdgpu_jpeg_resume(adev);
	97	if (r)
	98	return r;
	99
	100	ring = &adev->jpeg.inst->ring_dec;
	101	ring->use_doorbell = true;
	102	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
	103	sprintf(ring->name, "jpeg_dec");
	104	r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
c107171b	105	AMDGPU_RING_PRIO_DEFAULT, NULL);
dfd57dbf LL	106	if (r)
	107	return r;
	108
	109	adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
	110	adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
	111
	112	return 0;
	113	}
	114
	115	/**
	116	* jpeg_v3_0_sw_fini - sw fini for JPEG block
	117	*
	118	* @handle: amdgpu_device pointer
	119	*
	120	* JPEG suspend and free up sw allocation
	121	*/
	122	static int jpeg_v3_0_sw_fini(void *handle)
	123	{
	124	struct amdgpu_device adev = (struct amdgpu_device )handle;
	125	int r;
	126
	127	r = amdgpu_jpeg_suspend(adev);
	128	if (r)
	129	return r;
	130
	131	r = amdgpu_jpeg_sw_fini(adev);
	132
	133	return r;
	134	}
	135
	136	/**
	137	* jpeg_v3_0_hw_init - start and test JPEG block
	138	*
	139	* @handle: amdgpu_device pointer
	140	*
	141	*/
	142	static int jpeg_v3_0_hw_init(void *handle)
	143	{
	144	struct amdgpu_device adev = (struct amdgpu_device )handle;
	145	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
	146	int r;
	147
	148	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
	149	(adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
	150
	151	r = amdgpu_ring_test_helper(ring);
	152	if (r)
	153	return r;
	154
	155	DRM_INFO("JPEG decode initialized successfully.\n");
	156
	157	return 0;
	158	}
	159
	160	/**
	161	* jpeg_v3_0_hw_fini - stop the hardware block
	162	*
	163	* @handle: amdgpu_device pointer
	164	*
	165	* Stop the JPEG block, mark ring as not ready any more
	166	*/
	167	static int jpeg_v3_0_hw_fini(void *handle)
	168	{
	169	struct amdgpu_device adev = (struct amdgpu_device )handle;
dfd57dbf	170
223ce1d5 JZ	171	cancel_delayed_work_sync(&adev->vcn.idle_work);
223ce1d5 JZ	172
dfd57dbf LL	173	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
	174	RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
	175	jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
	176
dfd57dbf LL	177	return 0;
	178	}
	179
	180	/**
	181	* jpeg_v3_0_suspend - suspend JPEG block
	182	*
	183	* @handle: amdgpu_device pointer
	184	*
	185	* HW fini and suspend JPEG block
	186	*/
	187	static int jpeg_v3_0_suspend(void *handle)
	188	{
	189	struct amdgpu_device adev = (struct amdgpu_device )handle;
	190	int r;
	191
	192	r = jpeg_v3_0_hw_fini(adev);
	193	if (r)
	194	return r;
	195
	196	r = amdgpu_jpeg_suspend(adev);
	197
	198	return r;
	199	}
	200
	201	/**
	202	* jpeg_v3_0_resume - resume JPEG block
	203	*
	204	* @handle: amdgpu_device pointer
	205	*
	206	* Resume firmware and hw init JPEG block
	207	*/
	208	static int jpeg_v3_0_resume(void *handle)
	209	{
	210	struct amdgpu_device adev = (struct amdgpu_device )handle;
	211	int r;
	212
	213	r = amdgpu_jpeg_resume(adev);
	214	if (r)
	215	return r;
	216
	217	r = jpeg_v3_0_hw_init(adev);
	218
	219	return r;
	220	}
	221
77f5c737	222	static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev)
b52e271e LL	223	{
	224	uint32_t data = 0;
	225
	226	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
	227	if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
	228	data \|= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
	229	else
	230	data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
	231
	232	data \|= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
	233	data \|= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
	234	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
	235
	236	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
	237	data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
	238	\| JPEG_CGC_GATE__JPEG2_DEC_MASK
	239	\| JPEG_CGC_GATE__JPEG_ENC_MASK
	240	\| JPEG_CGC_GATE__JMCIF_MASK
	241	\| JPEG_CGC_GATE__JRBBM_MASK);
	242	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
	243
	244	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
	245	data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
	246	\| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
	247	\| JPEG_CGC_CTRL__JMCIF_MODE_MASK
	248	\| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
	249	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
	250	}
	251
77f5c737	252	static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev)
b52e271e LL	253	{
	254	uint32_t data = 0;
	255
	256	data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
	257	data \|= (JPEG_CGC_GATE__JPEG_DEC_MASK
	258	\|JPEG_CGC_GATE__JPEG2_DEC_MASK
	259	\|JPEG_CGC_GATE__JPEG_ENC_MASK
	260	\|JPEG_CGC_GATE__JMCIF_MASK
	261	\|JPEG_CGC_GATE__JRBBM_MASK);
	262	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
	263	}
	264
	265	static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)
	266	{
	267	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
	268	uint32_t data = 0;
	269	int r = 0;
	270
	271	data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
	272	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
	273
450da2ef	274	r = SOC15_WAIT_ON_RREG(JPEG, 0,
b52e271e	275	mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
450da2ef	276	UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
b52e271e LL	277
	278	if (r) {
	279	DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
	280	return r;
	281	}
	282	}
	283
	284	/* disable anti hang mechanism */
	285	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
	286	~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
	287
	288	/* keep the JPEG in static PG mode */
	289	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
	290	~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
	291
	292	return 0;
	293	}
	294
77f5c737	295	static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev)
b52e271e LL	296	{
	297	/* enable anti hang mechanism */
	298	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
	299	UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
	300	~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
	301
	302	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
	303	uint32_t data = 0;
	304	int r = 0;
	305
	306	data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
	307	WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
	308
450da2ef	309	r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
b52e271e	310	(2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
450da2ef	311	UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
b52e271e LL	312
	313	if (r) {
	314	DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
	315	return r;
	316	}
	317	}
	318
	319	return 0;
	320	}
	321
dfd57dbf LL	322	/**
	323	* jpeg_v3_0_start - start JPEG block
	324	*
	325	* @adev: amdgpu_device pointer
	326	*
	327	* Setup and start the JPEG block
	328	*/
	329	static int jpeg_v3_0_start(struct amdgpu_device *adev)
	330	{
	331	struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
b52e271e	332	int r;
dfd57dbf LL	333
	334	if (adev->pm.dpm_enabled)
	335	amdgpu_dpm_enable_jpeg(adev, true);
	336
b52e271e LL	337	/* disable power gating */
	338	r = jpeg_v3_0_disable_static_power_gating(adev);
	339	if (r)
	340	return r;
	341
	342	/* JPEG disable CGC */
	343	jpeg_v3_0_disable_clock_gating(adev);
	344
dfd57dbf LL	345	/* MJPEG global tiling registers */
	346	WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
	347	adev->gfx.config.gb_addr_config);
	348	WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,
	349	adev->gfx.config.gb_addr_config);
	350
	351	/* enable JMI channel */
	352	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
	353	~UVD_JMI_CNTL__SOFT_RESET_MASK);
	354
	355	/* enable System Interrupt for JRBC */
	356	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
	357	JPEG_SYS_INT_EN__DJRBC_MASK,
	358	~JPEG_SYS_INT_EN__DJRBC_MASK);
	359
	360	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
	361	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L \| 0x00000002L));
	362	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
	363	lower_32_bits(ring->gpu_addr));
	364	WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
	365	upper_32_bits(ring->gpu_addr));
	366	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
	367	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
	368	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
	369	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
	370	ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
	371
	372	return 0;
	373	}
	374
	375	/**
	376	* jpeg_v3_0_stop - stop JPEG block
	377	*
	378	* @adev: amdgpu_device pointer
	379	*
	380	* stop the JPEG block
	381	*/
	382	static int jpeg_v3_0_stop(struct amdgpu_device *adev)
	383	{
b52e271e LL	384	int r;
b52e271e LL	385
dfd57dbf LL	386	/* reset JMI */
	387	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
	388	UVD_JMI_CNTL__SOFT_RESET_MASK,
	389	~UVD_JMI_CNTL__SOFT_RESET_MASK);
	390
b52e271e LL	391	jpeg_v3_0_enable_clock_gating(adev);
	392
	393	/* enable power gating */
	394	r = jpeg_v3_0_enable_static_power_gating(adev);
	395	if (r)
	396	return r;
	397
dfd57dbf LL	398	if (adev->pm.dpm_enabled)
	399	amdgpu_dpm_enable_jpeg(adev, false);
	400
	401	return 0;
	402	}
	403
	404	/**
	405	* jpeg_v3_0_dec_ring_get_rptr - get read pointer
	406	*
	407	* @ring: amdgpu_ring pointer
	408	*
	409	* Returns the current hardware read pointer
	410	*/
	411	static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
	412	{
	413	struct amdgpu_device *adev = ring->adev;
	414
	415	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
	416	}
	417
	418	/**
	419	* jpeg_v3_0_dec_ring_get_wptr - get write pointer
	420	*
	421	* @ring: amdgpu_ring pointer
	422	*
	423	* Returns the current hardware write pointer
	424	*/
	425	static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
	426	{
	427	struct amdgpu_device *adev = ring->adev;
	428
	429	if (ring->use_doorbell)
3748424b	430	return *ring->wptr_cpu_addr;
dfd57dbf LL	431	else
	432	return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
	433	}
	434
	435	/**
	436	* jpeg_v3_0_dec_ring_set_wptr - set write pointer
	437	*
	438	* @ring: amdgpu_ring pointer
	439	*
	440	* Commits the write pointer to the hardware
	441	*/
	442	static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
	443	{
	444	struct amdgpu_device *adev = ring->adev;
	445
	446	if (ring->use_doorbell) {
3748424b	447	*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
dfd57dbf LL	448	WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
	449	} else {
	450	WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
	451	}
	452	}
	453
	454	static bool jpeg_v3_0_is_idle(void *handle)
	455	{
	456	struct amdgpu_device adev = (struct amdgpu_device )handle;
	457	int ret = 1;
	458
	459	ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
	460	UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
	461	UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
	462
	463	return ret;
	464	}
	465
	466	static int jpeg_v3_0_wait_for_idle(void *handle)
	467	{
	468	struct amdgpu_device adev = (struct amdgpu_device )handle;
dfd57dbf	469
cdab4211	470	return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
dfd57dbf	471	UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
450da2ef	472	UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
dfd57dbf LL	473	}
	474
	475	static int jpeg_v3_0_set_clockgating_state(void *handle,
	476	enum amd_clockgating_state state)
	477	{
b52e271e LL	478	struct amdgpu_device adev = (struct amdgpu_device )handle;
	479	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
	480
	481	if (enable) {
df3183b3	482	if (!jpeg_v3_0_is_idle(handle))
b52e271e LL	483	return -EBUSY;
	484	jpeg_v3_0_enable_clock_gating(adev);
	485	} else {
	486	jpeg_v3_0_disable_clock_gating(adev);
	487	}
	488
dfd57dbf LL	489	return 0;
	490	}
	491
	492	static int jpeg_v3_0_set_powergating_state(void *handle,
	493	enum amd_powergating_state state)
	494	{
	495	struct amdgpu_device adev = (struct amdgpu_device )handle;
	496	int ret;
	497
	498	if(state == adev->jpeg.cur_state)
	499	return 0;
	500
	501	if (state == AMD_PG_STATE_GATE)
	502	ret = jpeg_v3_0_stop(adev);
	503	else
	504	ret = jpeg_v3_0_start(adev);
	505
	506	if(!ret)
	507	adev->jpeg.cur_state = state;
	508
	509	return ret;
	510	}
	511
	512	static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,
	513	struct amdgpu_irq_src *source,
	514	unsigned type,
	515	enum amdgpu_interrupt_state state)
	516	{
	517	return 0;
	518	}
	519
	520	static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,
	521	struct amdgpu_irq_src *source,
	522	struct amdgpu_iv_entry *entry)
	523	{
	524	DRM_DEBUG("IH: JPEG TRAP\n");
	525
	526	switch (entry->src_id) {
	527	case VCN_2_0__SRCID__JPEG_DECODE:
	528	amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
	529	break;
	530	default:
	531	DRM_ERROR("Unhandled interrupt: %d %d\n",
	532	entry->src_id, entry->src_data[0]);
	533	break;
	534	}
	535
	536	return 0;
	537	}
	538
	539	static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
	540	.name = "jpeg_v3_0",
	541	.early_init = jpeg_v3_0_early_init,
	542	.late_init = NULL,
	543	.sw_init = jpeg_v3_0_sw_init,
	544	.sw_fini = jpeg_v3_0_sw_fini,
	545	.hw_init = jpeg_v3_0_hw_init,
	546	.hw_fini = jpeg_v3_0_hw_fini,
	547	.suspend = jpeg_v3_0_suspend,
	548	.resume = jpeg_v3_0_resume,
	549	.is_idle = jpeg_v3_0_is_idle,
	550	.wait_for_idle = jpeg_v3_0_wait_for_idle,
	551	.check_soft_reset = NULL,
	552	.pre_soft_reset = NULL,
553	.soft_reset = NULL,
554	.post_soft_reset = NULL,
555	.set_clockgating_state = jpeg_v3_0_set_clockgating_state,
556	.set_powergating_state = jpeg_v3_0_set_powergating_state,
557	};
558
559	static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
560	.type = AMDGPU_RING_TYPE_VCN_JPEG,
561	.align_mask = 0xf,
562	.vmhub = AMDGPU_MMHUB_0,
563	.get_rptr = jpeg_v3_0_dec_ring_get_rptr,
564	.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
565	.set_wptr = jpeg_v3_0_dec_ring_set_wptr,
566	.emit_frame_size =
567	SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
568	SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
569	8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */
570	18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */
571	8 + 16,
572	.emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */
573	.emit_ib = jpeg_v2_0_dec_ring_emit_ib,
574	.emit_fence = jpeg_v2_0_dec_ring_emit_fence,
575	.emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
576	.test_ring = amdgpu_jpeg_dec_ring_test_ring,
577	.test_ib = amdgpu_jpeg_dec_ring_test_ib,
578	.insert_nop = jpeg_v2_0_dec_ring_nop,
579	.insert_start = jpeg_v2_0_dec_ring_insert_start,
580	.insert_end = jpeg_v2_0_dec_ring_insert_end,
581	.pad_ib = amdgpu_ring_generic_pad_ib,
582	.begin_use = amdgpu_jpeg_ring_begin_use,
583	.end_use = amdgpu_jpeg_ring_end_use,
584	.emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
585	.emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
586	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
587	};
588
589	static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
590	{
591	adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;
592	DRM_INFO("JPEG decode is enabled in VM mode\n");
593	}
594
595	static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {
596	.set = jpeg_v3_0_set_interrupt_state,
597	.process = jpeg_v3_0_process_interrupt,
598	};
599
600	static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)
601	{
602	adev->jpeg.inst->irq.num_types = 1;
603	adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
604	}
605
606	const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =
607	{
608	.type = AMD_IP_BLOCK_TYPE_JPEG,
609	.major = 3,
610	.minor = 0,
611	.rev = 0,
612	.funcs = &jpeg_v3_0_ip_funcs,
613	};